diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 2c02fa1c13e..122d1dc8c48 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -114,7 +114,7 @@ jobs: strategy: matrix: - boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, other, risc-v, sim01, sim02, xtensa] + boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, other, risc-v, sim-01, sim-02, xtensa] steps: - name: Download Source Artifact @@ -159,7 +159,7 @@ jobs: needs: Fetch-Source strategy: matrix: - boards: [macos, sim01, sim02] + boards: [macos, sim-01, sim-02] steps: - name: Download Source Artifact uses: actions/download-artifact@v1 diff --git a/Documentation/applications/nsh/commands.rst b/Documentation/applications/nsh/commands.rst index 3524128a52a..cb91899b398 100644 --- a/Documentation/applications/nsh/commands.rst +++ b/Documentation/applications/nsh/commands.rst @@ -495,8 +495,9 @@ Show Memory Manager Status (free) example:: nsh> free - total used free largest - Mem: 4194288 1591552 2602736 2601584 + total used free largest nused nfree + Mem: 5583024 1614784 3968240 3967792 244 4 + nsh> **Where:** @@ -506,6 +507,8 @@ total This is the total size of memory allocated for use by malloc in bytes. used This is the total size of memory occupied by chunks handed out by malloc. free This is the total size of memory occupied by free (not in use) chunks. largest Size of the largest free (not in use) chunk. +nused This is the number of allocated chunks +nfree This is the number of free chunks ======= ====================================== .. _cmdget: diff --git a/Documentation/applications/nsh/login.rst b/Documentation/applications/nsh/login.rst index 6aabfc3cbbc..01d538630c1 100644 --- a/Documentation/applications/nsh/login.rst +++ b/Documentation/applications/nsh/login.rst @@ -57,7 +57,7 @@ credentials at login time: This is not very flexible since there can be only one user and the password is fixed in the FLASH image. This option is also not very secure because a malicious user could get the password by just - looking at the ``.text`` stings in the flash image. + looking at the ``.text`` strings in the flash image. #. NSH can also be configured to defer the entire user credential verification to platform-specific logic with this setting:: diff --git a/Documentation/components/drivers/character/foc.rst b/Documentation/components/drivers/character/foc.rst index 1a1612acb75..e694cc06e6d 100644 --- a/Documentation/components/drivers/character/foc.rst +++ b/Documentation/components/drivers/character/foc.rst @@ -13,11 +13,11 @@ The device on the kernel side is responsible for the following: #. return ADC current samples #. synchronize user-space with PWM events -The Nuttx FOC driver is split into two parts: +The NuttX FOC driver is split into two parts: #. An "upper half", generic driver that provides the common FOC interface to application level code, -#. A "lower half", platform-specific driver that implemets +#. A "lower half", platform-specific driver that implements the low-level logic to implement the FOC functionality Files supporting FOC can be found in the following locations: diff --git a/Documentation/components/drivers/character/watchdog.rst b/Documentation/components/drivers/character/watchdog.rst index b4e8e53b0a3..287aa452810 100644 --- a/Documentation/components/drivers/character/watchdog.rst +++ b/Documentation/components/drivers/character/watchdog.rst @@ -65,7 +65,7 @@ Enabling the Watchdog Support and Example in ``menuconfing`` 4. Include the Debug Watchdog Feature In order to get the watchdog timer status, you need to enable it. For production code and for your application you may disable it. - + Go into menu :menuselection:`Build Setup --> Debug Options` and press :kbd:`Enter`. Then enable: - [x] Enable Debug Features @@ -79,7 +79,7 @@ The previously selected example will basically do the following: * Open the watchdog device * Set the watchdog timeout * Start the watchdog timer -* Ping (feed the dog) during the ``pingtime`` with a delay of ``pingdelay`` and print out the wdt status in case debug was enabled. +* Ping (feed the dog) during the ``pingtime`` with a delay of ``pingdelay`` and print out the wdt status in case debug was enabled. * Enter into an endless loop without pinging. It will cause the watchdog timer to reset the chip on timeout, i.e., after timer expiration. @@ -136,7 +136,7 @@ This command gets the status of the watchdog timer. It receives a writeable poin .. c:macro:: WDIOC_SETTIMEOUT -This command sets the timeout value, i.e., the value that will trigger the reset or interrupt. The argument is a ``uint32_t`` value in miliseconds. +This command sets the timeout value, i.e., the value that will trigger the reset or interrupt. The argument is a ``uint32_t`` value in milliseconds. .. c:macro:: WDIOC_CAPTURE @@ -153,12 +153,12 @@ This command registers an user callback that will be triggered on timeout. It re .. c:macro:: WDIOC_KEEPALIVE - This command resets the watchdog timer AKA '**ping**", "**kick**", "**pet**", "**feed**" the dog". + This command resets the watchdog timer AKA '**ping**", "**kick**", "**pet**", "**feed**" the dog". Enable Built in System Monitoring to reset the watchdog ------------------------------------------------------- -The auto-monitor provides an OS-internal mechanism to automatically start and repeatedly reset the watchdog. +The auto-monitor provides an OS-internal mechanism to automatically start and repeatedly reset the watchdog. To enable it, follow the next instructions: @@ -181,16 +181,16 @@ To enable it, follow the next instructions: After selecting the option you may want to configure some parameters: * **Timeout**: It is the watchdog timer expiration time in seconds. - * **Keep a live interval**: This is the interval in which the watchdog will be fed. It is in seconds. It can't be bigger than the timeout. If this interval is equal to timeout interval, than this interval will automatically change to half timeout. + * **Keep a live interval**: This is the interval in which the watchdog will be fed. It is in seconds. It can't be bigger than the timeout. If this interval is equal to timeout interval, than this interval will automatically change to half timeout. * **Keep alive by**: This is a choice to determine who is going to feed the dog. There are 4 possible choices that are described as follows. - ``Capture callback``: This choice registers a watchdog timer callback to reset the watchdog every time it expires, i.e., on timeout. + ``Capture callback``: This choice registers a watchdog timer callback to reset the watchdog every time it expires, i.e., on timeout. ``Timer callback``: This choice also uses a timer callback to reset the watchdog, but it will reset the watchdog every "keep a live interval". ``Worker callback``: This choice uses a Work Queue to reset the watchdog every "keep a live interval". This choice depends on having the Low or High Priority Work Queue enabled. - If only the High Priority Work Queue is enabled, this one will be used, otherwise Low Priority Work Queue is used. - + If only the High Priority Work Queue is enabled, this one will be used, otherwise Low Priority Work Queue is used. + So, before enabling it, go into menu :menuselection:`RTOS Features --> Work queue support` and press :kbd:`Enter`. - [x] Low priority (kernel) worker thread @@ -200,5 +200,5 @@ To enable it, follow the next instructions: Go into menu :menuselection:`Device Drivers` and enable: - [x] Power Management Support - -After selecting one of these choices, the chip will keep itself alive by one of these options. + +After selecting one of these choices, the chip will keep itself alive by one of these options. diff --git a/Documentation/components/drivers/special/syslog.rst b/Documentation/components/drivers/special/syslog.rst index 2a28258b980..a63233a43ee 100644 --- a/Documentation/components/drivers/special/syslog.rst +++ b/Documentation/components/drivers/special/syslog.rst @@ -392,7 +392,8 @@ mounting of the file systems. The interface ``syslog_file_channel()`` is used to configure the SYSLOG file channel: -.. c:function:: int syslog_file_channel(FAR const char *devpath); +.. c:function:: FAR struct syslog_channel_s * + syslog_file_channel(FAR const char *devpath); Configure to use a file in a mounted file system at ``devpath`` as the SYSLOG channel. @@ -423,8 +424,8 @@ SYSLOG file channel: ``syslog_file_channel()`` will create the file. :return: - Zero (``OK``) is returned on success; a - negated ``errno`` value is returned on any failure. + A pointer to the new syslog channel; ``NULL`` is returned + on any failure. References: ``drivers/syslog/syslog_filechannel.c``, ``drivers/syslog/syslog_device.c``, and diff --git a/Documentation/components/nxgraphics/nxtk.rst b/Documentation/components/nxgraphics/nxtk.rst index 6ff4a0271b5..22378b9f1ff 100644 --- a/Documentation/components/nxgraphics/nxtk.rst +++ b/Documentation/components/nxgraphics/nxtk.rst @@ -500,9 +500,9 @@ these sub-windows to be managed more-or-less independently: :param rect: The location within the toolbar window to be retrieved. :param plane: - TSpecifies the color plane to get from. + Specifies the color plane to get from. :param dest: - TThe location to copy the memory region. + The location to copy the memory region. :param deststride: The width, in bytes, of the dest memory. diff --git a/Documentation/contributing/documentation.rst b/Documentation/contributing/documentation.rst index a430716f164..6f57b1d96f1 100644 --- a/Documentation/contributing/documentation.rst +++ b/Documentation/contributing/documentation.rst @@ -24,7 +24,7 @@ go into ``Documentation`` directory. Then, $ pip3 install pipenv $ pipenv install - $ # activate the virtual environent + $ # activate the virtual environment $ pipenv shell 2. Build documentation: @@ -82,7 +82,7 @@ sometimes Sphinx's approach is used over standard RST since it is more powerful Documentation Conventions ========================= -While RST/Sphinx provide many ways to do things, it is best to follow a given convention to mantain consistency and avoid +While RST/Sphinx provide many ways to do things, it is best to follow a given convention to maintain consistency and avoid pitfalls. For this reason, documentation changes should follow the following set of conventions. Indentation @@ -180,7 +180,7 @@ Tips Spacing ------- -If you are getting formatting errors, be sure to provide the appropiate spacing between a directive and its content. +If you are getting formatting errors, be sure to provide the appropriate spacing between a directive and its content. Generally, you should follow this format: .. code-block:: RST diff --git a/Documentation/contributing/workflow.rst b/Documentation/contributing/workflow.rst index 574c8737949..d6bf8884a3b 100644 --- a/Documentation/contributing/workflow.rst +++ b/Documentation/contributing/workflow.rst @@ -13,7 +13,7 @@ You should be aware of the following: automatically during CI to ensure conformance. Note that not all existing files in the repository are already adapted to conform to the standard as this is an ongoing effort. Thus, - if you're submitting a patch to an existing file you may have to make the file conform to the standard, even if you are not reponsible + if you're submitting a patch to an existing file you may have to make the file conform to the standard, even if you are not responsible for those standard violations. It is also appreciated that you separate any styling fixes in a separate commit from the functional changes so that these are more @@ -37,6 +37,6 @@ You should be aware of the following: - If this is from an inactive project, it may be considered for inclusion in NuttX, provided that licensing terms allow to do so and it is deemed of sufficient value to be included, considering that this code will have to be maintained in NuttX afterwards. - Note that it is undesireable to included non Apache 2.0 Licensed code inside the repository, even if the license itself allows it + Note that it is undesirable to included non Apache 2.0 Licensed code inside the repository, even if the license itself allows it (for example BSD License). diff --git a/Documentation/guides/cpp_cmake.rst b/Documentation/guides/cpp_cmake.rst index f9220794649..b5dd8382132 100644 --- a/Documentation/guides/cpp_cmake.rst +++ b/Documentation/guides/cpp_cmake.rst @@ -76,7 +76,7 @@ Creating the project project(HelloCpp VERSION 1.0 - DESCRIPTION "Hello world C++ Nuttx" + DESCRIPTION "Hello world C++ NuttX" ) set(CMAKE_CXX_STANDARD 17) diff --git a/Documentation/guides/tasktraceuser.rst b/Documentation/guides/tasktraceuser.rst index 293c3ffaaef..a04c160bbf9 100644 --- a/Documentation/guides/tasktraceuser.rst +++ b/Documentation/guides/tasktraceuser.rst @@ -109,7 +109,7 @@ After getting the trace, the following command displays the accumulated trace da nsh> trace dump -This will be get the trace results like the followings: +This will get the trace results like the following: .. code-block:: @@ -266,7 +266,7 @@ The default value is given by the kernel configuration ``CONFIG_SCHED_INSTRUMENT - ``-a`` : Disable recording the system call arguments. - ``+i`` : Enable interrupt trace. - It records the event of enter/leave interrupt handler which is occured while the tracing. + It records the event of enter/leave interrupt handler which occurred while tracing. All IRQs are recorded by default. ``trace irq`` command can filter the IRQs to be recorded. - ``-i`` : Disable interrupt trace. diff --git a/Documentation/introduction/detailed_support.rst b/Documentation/introduction/detailed_support.rst index 39791431f44..65ab05955d6 100644 --- a/Documentation/introduction/detailed_support.rst +++ b/Documentation/introduction/detailed_support.rst @@ -2464,7 +2464,7 @@ Also refer to the NuttX board file for further information about the current state of the port. NuttX-9.0 added basic support for Microchip SAME54 Xplained Pro board. -An ethernet driver was also added to the SAME5x familly. +An ethernet driver was also added to the SAME5x family. STMicro STM32 F72x/F73x ----------------------- diff --git a/Documentation/introduction/resources.rst b/Documentation/introduction/resources.rst index 0ac8cf44713..4ef40afd270 100644 --- a/Documentation/introduction/resources.rst +++ b/Documentation/introduction/resources.rst @@ -13,7 +13,7 @@ Here's a list of Apache NuttX resources that you might find helpful: * `Apache NuttX mailing list `_ – a very active mailing list, the place to get help with your application or any questions you have about NuttX. * `Apache NuttX YouTube channel `_ – Alan Carvalho de Assis's YouTube channel on NuttX. It's a source of a lot of great practical information. * `Apache NuttX Coding Standard `_ — How code should look when you submit new files or modify existing ones. - * `Apache NuttX Code Contribution Guidlines `_ — The full workflow to follow for submitting code with all the details. + * `Apache NuttX Code Contribution Guidelines `_ — The full workflow to follow for submitting code with all the details. * Git diff --git a/Documentation/platforms/arm/imxrt/boards/imxrt1020-evk/index.rst b/Documentation/platforms/arm/imxrt/boards/imxrt1020-evk/index.rst new file mode 100644 index 00000000000..922e062ea0f --- /dev/null +++ b/Documentation/platforms/arm/imxrt/boards/imxrt1020-evk/index.rst @@ -0,0 +1,103 @@ +=============== +i.MX RT1020 EVK +=============== + +`i.MX RT1020 EVK `_ +is an evaluation kit by NXP company. This kit uses the i.MX RT1020 crossover MCU in LQFP144 package with ARM Cortex M7 core. + +Features +======== + +- Processor + - MIMXRT1021DAG5A processor +- Memory + - 256 Mb SDRAM memory + - 64 Mb QSPI Flash + - TF socket for SD card +- Display and Audio + - Audio CODEC + - 4-pole audio headphone jack + - External speaker connection + - Microphone +- Connectivity + - Micro USB host and OTG connectors + - Ethernet (10/100T) connector + - CAN transceivers + - Arduino® interface + +Serial Console +============== + +The EVK default console is on LPUART1, which is multiplexed onto +the debug port (either OpenSDA or SEGGER JLink). + +It runs at 115200,n,8,1. + +LEDs and Buttons +================ + +LEDs +---- + +There is one user accessible LED status indicator located on the 1020-EVK, +USERLED. The function of the LEDs include: + +=== ============ ====== +Pin Description Colour +=== ============ ====== +D3 Power Supply Green +D5 User LED Green +D15 Reset LED Red +=== ============ ====== + +This LED is not used by the board port unless CONFIG_ARCH_LEDS is +defined. In that case, the usage by the board port is defined in +include/board.h and src/imxrt_autoleds.c. The LED is used to encode +OS-related events as documented in board.h + +================ ======================= ===== +SYMBOL Meaning LED +================ ======================= ===== +LED_STARTED NuttX has been started OFF +LED_HEAPALLOCATE Heap has been allocated OFF +LED_IRQSENABLED Interrupts enabled OFF +LED_STACKCREATED Idle stack created ON +LED_INIRQ In an interrupt N/C +LED_SIGNAL In a signal handler N/C +LED_ASSERTION An assertion failed N/C +LED_PANIC The system has crashed FLASH +================ ======================= ===== + +Thus if the LED is statically on, NuttX has successfully booted and is, +apparently, running normally. If the LED is flashing at approximately +2Hz, then a fatal error has been detected and the system has halted. + + +Buttons +------- + +This IMXRT board has three external buttons + +=== ============== ======================== +SW2 (IRQ88, ONOFF) Not on a GPIO, No muxing +SW3 (IRQ88, POR) Not on a GPIO, No muxing +SW4 (IRQ88, USER) Wakeup, GPIO5-0 +=== ============== ======================== + +Configurations +============== + +netnsh +------ + +This configuration is similar to the nsh configuration except that is +has networking enabled, both IPv4 and IPv6. This NSH configuration is +focused on network-related testing. + +nsh +--- + +Configures the NuttShell (nsh) located at examples/nsh. This NSH +configuration is focused on low level, command-line driver testing. +Built-in applications are supported, but none are enabled. This +configuration does not support a network. diff --git a/Documentation/platforms/arm/imxrt/boards/imxrt1050-evk/index.rst b/Documentation/platforms/arm/imxrt/boards/imxrt1050-evk/index.rst new file mode 100644 index 00000000000..ad90ec80e52 --- /dev/null +++ b/Documentation/platforms/arm/imxrt/boards/imxrt1050-evk/index.rst @@ -0,0 +1,129 @@ +=============== +i.MX RT1050 EVK +=============== + +`i.MX RT1050 EVK `_ +is an evaluation kit by NXP company. This kit uses the i.MX RT1050 crossover MCU with ARM Cortex M7 core. + +Features +======== + +- Processor + - MIMXRT1052DVL6A processor +- Memory + - 256 Mb SDRAM memory + - 512 Mb Hyper Flash + - Footprint for QSPI Flash + - TF socket for SD card +- Display and Audio + - Parallel LCD connector + - Camera connector + - Audio CODEC + - 4-pole audio headphone jack + - External speaker connection + - Microphone + - SPDIF connector +- Connectivity + - Micro USB host and OTG connectors + - Ethernet (10/100T) connector + - CAN transceivers + - Arduino® interface + +Serial Console +============== + +Virtual console port provided by OpenSDA: + +========= ============= ========== +UART1_TXD GPIO_AD_B0_12 LPUART1_TX +UART1_RXD GPIO_AD_B0_13 LPUART1_RX +========= ============= ========== + +Arduino RS-232 Shield: + +=== == ======= ============= ========== +J22 D0 UART_RX GPIO_AD_B1_07 LPUART3_RX +J22 D1 UART_TX GPIO_AD_B1_06 LPUART3_TX +=== == ======= ============= ========== + +LEDs and buttons +================ + +LEDs +---- + +There are four LED status indicators located on the EVK Board. The +functions of these LEDs include: + +=== ============ +Pin Description +=== ============ +D3 Power Supply +D15 Reset LED +D16 OpenSDA +D18 User LED +=== ============ + +Only a single LED, D18, is under software control. It connects to +GPIO_AD_B0_09 which is shared with JTAG_TDI and ENET_RST + +This LED is not used by the board port unless CONFIG_ARCH_LEDS is +defined. In that case, the usage by the board port is defined in +include/board.h and src/imxrt_autoleds.c. The LED is used to encode +OS-related events as follows: + +================ ======================= ===== +SYMBOL Meaning LED +================ ======================= ===== +LED_STARTED NuttX has been started OFF +LED_HEAPALLOCATE Heap has been allocated OFF +LED_IRQSENABLED Interrupts enabled OFF +LED_STACKCREATED Idle stack created ON +LED_INIRQ In an interrupt N/C +LED_SIGNAL In a signal handler N/C +LED_ASSERTION An assertion failed N/C +LED_PANIC The system has crashed FLASH +================ ======================= ===== + +Thus if the LED is statically on, NuttX has successfully booted and is, +apparently, running normally. If the LED is flashing at approximately +2Hz, then a fatal error has been detected and the system has halted. + +Buttons +------- + +There are four user interface switches on the MIMXRT1050 EVK Board: + + - SW1: Power Switch (slide switch) + - SW2: ON/OFF Button + - SW3: Reset button + - SW8: User button + +Only the user button is available to the software. It is sensed on the +WAKEUP pin which will be pulled low when the button is pressed. + +Configurations +============== + +knsh +---- + +This is identical to the nsh configuration below except that NuttX +is built as a protected mode, monolithic module and the user applications +are built separately. For further information about compiling and +running this configuration please refer to imxrt1064-evk documentation. + +netnsh +------ + +This configuration is similar to the nsh configuration except that is +has networking enabled, both IPv4 and IPv6. This NSH configuration is +focused on network-related testing. + +nsh +--- + +Configures the NuttShell (nsh) located at examples/nsh. This NSH +configuration is focused on low level, command-line driver testing. +Built-in applications are supported, but none are enabled. This +configuration does not support a network. diff --git a/Documentation/platforms/arm/imxrt/boards/imxrt1060-evk/imxrt1060-evk-front.jpg b/Documentation/platforms/arm/imxrt/boards/imxrt1060-evk/imxrt1060-evk-front.jpg new file mode 100644 index 00000000000..b0335a38b65 Binary files /dev/null and b/Documentation/platforms/arm/imxrt/boards/imxrt1060-evk/imxrt1060-evk-front.jpg differ diff --git a/Documentation/platforms/arm/imxrt/boards/imxrt1060-evk/index.rst b/Documentation/platforms/arm/imxrt/boards/imxrt1060-evk/index.rst new file mode 100644 index 00000000000..8ee9eeea33c --- /dev/null +++ b/Documentation/platforms/arm/imxrt/boards/imxrt1060-evk/index.rst @@ -0,0 +1,200 @@ +=============== +i.MX RT1060 EVK +=============== + +`i.MX RT1060 EVK `_ +is an evaluation kit by NXP company. This kit uses the i.MX RT1060 crossover MCU with ARM Cortex M7 core. + +.. figure:: imxrt1060-evk-front.jpg + :align: center + :width: 50% + + i.MX RT1060 EVK + +Features +======== + +- Processor + - MIMXRT1062DVL6A processor +- Memory + - 1 Mb OCRAM memory + - 256 Mb SDRAM memory + - 512 Mb Hyper Flash - Populated but 0 ohm DNP + - 64 Mb QSPI Flash + - TF socket for SD card +- Display and Audio + - Parallel LCD connector + - Camera connector + - Audio CODEC + - 4-pole audio headphone jack + - External speaker connection + - Microphone + - SPDIF connector +- Connectivity + - Micro USB host and OTG connectors + - Ethernet (10/100T) connector + - CAN transceivers (including one CAN FD) + - Arduino® interface +- Sensors + - FXOS8700CQ 6-Axis Ecompass (3-Axis Mag, 3-Axis Accel) + +Serial Console +============== + +Virtual console port provided by OpenSDA: + +========= ============= ========== +UART1_TXD GPIO_AD_B0_12 LPUART1_TX +UART1_RXD GPIO_AD_B0_13 LPUART1_RX +========= ============= ========== + +Arduino RS-232 Shield: + +=== == ======= ============= ========== +J22 D0 UART_RX GPIO_AD_B1_07 LPUART3_RX +J22 D1 UART_TX GPIO_AD_B1_06 LPUART3_TX +=== == ======= ============= ========== + +LEDs and buttons +================ + +LEDs +---- + +There are four LED status indicators located on the EVK Board. The +functions of these LEDs include: + +=== ============ +Pin Description +=== ============ +D3 Power Supply +D18 User LED +D20 OpenSDA +D21 Reset LED +=== ============ + +Only a single LED, D18, is under software control. It connects to +GPIO_AD_B0_09 which is shared with JTAG_TDI and ENET_RST + +This LED is not used by the board port unless CONFIG_ARCH_LEDS is +defined. In that case, the usage by the board port is defined in +include/board.h and src/imxrt_autoleds.c. The LED is used to encode +OS-related events as follows: + +================ ======================= ===== +SYMBOL Meaning LED +================ ======================= ===== +LED_STARTED NuttX has been started OFF +LED_HEAPALLOCATE Heap has been allocated OFF +LED_IRQSENABLED Interrupts enabled OFF +LED_STACKCREATED Idle stack created ON +LED_INIRQ In an interrupt N/C +LED_SIGNAL In a signal handler N/C +LED_ASSERTION An assertion failed N/C +LED_PANIC The system has crashed FLASH +================ ======================= ===== + +Thus if the LED is statically on, NuttX has successfully booted and is, +apparently, running normally. If the LED is flashing at approximately +2Hz, then a fatal error has been detected and the system has halted. + +Buttons +------- + +There are five user interface switches on the MIMXRT1050 EVK Board: + + - SW1: Power Switch (slide switch fir power from J2) + - SW2: ON/OFF Button + - SW3: Power-on Reset button state forces to reset the system power except SNVS domain + - SW9: Reset button + - SW8: User button GPIO5-00 + +Only the user button is available to the software. It is sensed on the +WAKEUP pin which will be pulled low when the button is pressed. + + +J-Link External Debug Probe +=========================== + +Install the J-Link Debug Host Tools and make sure they are in your search path. + +Attach a J-Link 20-pin connector to J21. Check that jumpers J47 and J48 are +off (they are on by default when boards ship from the factory) to ensure SWD +signals are disconnected from the OpenSDA microcontroller. + +Configurations +============== + +can +--- + +This is an nsh configuration (see below) with added support of CAN driver. +FlexCAN3 is chosen as default, the change can be made at System type peripheral +selection. Please note that only FlexCAN3 and FlexCAN2 is available on this board. + +Bitrate and sample point can be also changed at System type peripheral selection, +basic values are 1 MHz for bitrate and 0.80 for sample point. The FlexCAN driver +for imxrt runs at 80 MHz clock frequency. + +The configuration also includes CAN utilities as candump and cansend. + +canfd +----- + +This is an nsh configuration (see below) with added support of CAN_FD driver. +FlexCAN3 is chosen as default, please note that only FlexCAN3 is capable of +providing CAN_FD support. + +Bitrate and sample point can be also changed at System type peripheral selection, +basic values are 1 MHz for bitrate and 0.80 for sample point for arbitration phase +and 4 MHz (bitrate) and 0.90 (sample point) for data phase. The FlexCAN driver +for imxrt runs at 80 MHz clock frequency. + +The configuration also includes CAN utilities as candump and cansend. + +knsh +---- + +This is identical to the nsh configuration below except that NuttX +is built as a protected mode, monolithic module and the user applications +are built separately. For further information about compiling and +running this configuration please refer to imxrt1064-evk documentation. + +netnsh +------ + +This configuration is similar to the nsh configuration except that is +has networking enabled, both IPv4 and IPv6. This NSH configuration is +focused on network-related testing. + +nsh +--- + +Configures the NuttShell (nsh) located at examples/nsh. This NSH +configuration is focused on low level, command-line driver testing. +Built-in applications are supported, but none are enabled. This +configuration does not support a network. + +lvgl +---- + +Configures the Littlev graphic library (lvgl) demo located under +examples/lvgldemo. This configuration needs the optional LCD model +RK043FN02H-CT from NXP. The LCD panel comes with the integrated +capacitive touchscreen sensor FT5336GQQ connected to the LPI2C1 bus, +address 0x38. NuttX support such touchscreen device via the driver +ft5x06 (drivers/input/ft5x06.c). At the moment only the polling +method is available, the board features an interrupt line connected +to the touchscreen sensor IC. + +IMXRT1060 MCU provides the integrated LCD driver. + +The LCD panel features: + - size 4.3" + - resolution 480×272 RGB + - backlight driver + - dimensions [mm]: 105.5 (W) x 67.2(H) x 4.35(D) Max. + +To run the lvgl demo please type "lvgldemo" at nsh prompt:: + + nsh> lvgldemo diff --git a/Documentation/platforms/arm/imxrt/boards/imxrt1064-evk/index.rst b/Documentation/platforms/arm/imxrt/boards/imxrt1064-evk/index.rst new file mode 100644 index 00000000000..34aaa7cadfe --- /dev/null +++ b/Documentation/platforms/arm/imxrt/boards/imxrt1064-evk/index.rst @@ -0,0 +1,277 @@ +=============== +i.MX RT1064 EVK +=============== + +`i.MX RT1064 EVK `_ +is an evaluation kit by NXP company. This kit uses the i.MX RT1064 crossover MCU with ARM Cortex M7 core. + +Features +======== + +- Processor + - MIMXRT1066DVL6A processor +- Memory + - 1 Mb OCRAM memory + - 256 Mb SDRAM memory + - 512 Mb Hyper Flash - Populated but 0 ohm DNP + - 64 Mb QSPI Flash + - TF socket for SD card +- Display and Audio + - Parallel LCD connector + - Camera connector + - Audio CODEC + - 4-pole audio headphone jack + - External speaker connection + - Microphone + - SPDIF connector +- Connectivity + - Micro USB host and OTG connectors + - Ethernet (10/100T) connector + - CAN transceivers + - Arduino® interface +- Sensors + - FXOS8700CQ 6-Axis Ecompass (3-Axis Mag, 3-Axis Accel) + +Serial Console +============== + +Virtual console port provided by OpenSDA: + +========= ============= ========== +UART1_TXD GPIO_AD_B0_12 LPUART1_TX +UART1_RXD GPIO_AD_B0_13 LPUART1_RX +========= ============= ========== + +Arduino RS-232 Shield: + +=== == ======= ============= ========== +J22 D0 UART_RX GPIO_AD_B1_07 LPUART3_RX +J22 D1 UART_TX GPIO_AD_B1_06 LPUART3_TX +=== == ======= ============= ========== + +LEDs and buttons +================ + +LEDs +---- + +There are four LED status indicators located on the EVK Board. The +functions of these LEDs include: + +=== ============ +Pin Description +=== ============ +D3 Power Supply +D18 User LED +D20 OpenSDA +D21 Reset LED +=== ============ + +Only a single LED, D18, is under software control. It connects to +GPIO_AD_B0_09 which is shared with JTAG_TDI and ENET_RST + +This LED is not used by the board port unless CONFIG_ARCH_LEDS is +defined. In that case, the usage by the board port is defined in +include/board.h and src/imxrt_autoleds.c. The LED is used to encode +OS-related events as follows: + +================ ======================= ===== +SYMBOL Meaning LED +================ ======================= ===== +LED_STARTED NuttX has been started OFF +LED_HEAPALLOCATE Heap has been allocated OFF +LED_IRQSENABLED Interrupts enabled OFF +LED_STACKCREATED Idle stack created ON +LED_INIRQ In an interrupt N/C +LED_SIGNAL In a signal handler N/C +LED_ASSERTION An assertion failed N/C +LED_PANIC The system has crashed FLASH +================ ======================= ===== + +Thus if the LED is statically on, NuttX has successfully booted and is, +apparently, running normally. If the LED is flashing at approximately +2Hz, then a fatal error has been detected and the system has halted. + +Buttons +------- + +There are five user interface switches on the MIMXRT1050 EVK Board: + + - SW1: Power Switch (slide switch fir power from J2) + - SW2: ON/OFF Button + - SW3: Power-on Reset button state forces to reset the system power except SNVS domain + - SW9: Reset button + - SW8: User button GPIO5-00 + +Only the user button is available to the software. It is sensed on the +WAKEUP pin which will be pulled low when the button is pressed. + + +J-Link External Debug Probe +=========================== + +Install the J-Link Debug Host Tools and make sure they are in your search path. + +Attach a J-Link 20-pin connector to J21. Check that jumpers J47 and J48 are +off (they are on by default when boards ship from the factory) to ensure SWD +signals are disconnected from the OpenSDA microcontroller. + +Configurations +============== + +can +--- + +This is an nsh configuration (see below) with added support of CAN driver. +FlexCAN3 is chosen as default, the change can be made at System type peripheral +selection. Please note that only FlexCAN3 and FlexCAN2 is available on this board. + +Bitrate and sample point can be also changed at System type peripheral selection, +basic values are 1 MHz for bitrate and 0.80 for sample point. The FlexCAN driver +for imxrt runs at 80 MHz clock frequency. + +The configuration also includes CAN utilities as candump and cansend. + +canfd +----- + +This is an nsh configuration (see below) with added support of CAN_FD driver. +FlexCAN3 is chosen as default, please note that only FlexCAN3 is capable of +providing CAN_FD support. + +Bitrate and sample point can be also changed at System type peripheral selection, +basic values are 1 MHz for bitrate and 0.80 for sample point for arbitration phase +and 4 MHz (bitrate) and 0.90 (sample point) for data phase. The FlexCAN driver +for imxrt runs at 80 MHz clock frequency. + +The configuration also includes CAN utilities as candump and cansend. + +knsh +---- + +This is identical to the nsh configuration below except that NuttX +is built as a protected mode, monolithic module and the user applications +are built separately. It is recommends to use a special make command; +not just 'make' but make with the following two arguments: + +.. code-block:: console + + $ make pass1 pass2 + +In the normal case (just 'make'), make will attempt to build both user- +and kernel-mode blobs more or less interleaved. This actual works! +However, for me it is very confusing so I prefer the above make command: +Make the user-space binaries first (pass1), then make the kernel-space +binaries (pass2) + +NOTES: + +At the end of the build, there will be several files in the top-level +NuttX build directory: + +PASS1: + - nuttx_user.elf - The pass1 user-space ELF file + - nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig) + - User.map - Symbols in the user-space ELF file + +PASS2: + - nuttx - The pass2 kernel-space ELF file + - nuttx.hex - The pass2 Intel HEX file (selected in defconfig) + - System.map - Symbols in the kernel-space ELF file + +The J-Link programmer will except files in .hex, .mot, .srec, and .bin +formats. + +Combining .hex files. If you plan to use the .hex files with your +debugger or FLASH utility, then you may need to combine the two hex +files into a single .hex file. Here is how you can do that. + +The 'tail' of the nuttx.hex file should look something like this +(with my comments added beginning with #): + +.. code-block:: console:: + + $ tail nuttx.hex + #xx xxxx 00 data records + ... + :10 C93C 00 000000000040184000C2010000000000 90 + :10 C94C 00 2400080000801B4000C01B4000001C40 5D + :10 C95C 00 00401C4000000C4050BF0060FF000100 74 + #xx xxxx 05 Start Linear Address Record + :04 0000 05 6000 02C1 D4 + #xx xxxx 01 End Of File record + :00 0000 01 FF + +Use an editor such as vi to remove the 05 and 01 records. + +The 'head' of the nuttx_user.hex file should look something like +this (again with my comments added beginning with #): + +.. code-block:: console:: + + $ head nuttx_user.hex + #xx xxxx 04 Extended Linear Address Record + :02 0000 04 6020 7A + #xx xxxx 00 data records + :10 0000 00 8905206030002060F2622060FC622060 80 + :10 0010 00 0000242008002420080024205C012420 63 + :10 0020 00 140024203D0020603100206071052060 14 + ... + +Nothing needs to be done here. The nuttx_user.hex file should +be fine. + +Combine the edited nuttx.hex and un-edited nuttx_user.hex +file to produce a single combined hex file: + +.. code-block:: console:: + + $ cat nuttx.hex nuttx_user.hex >combined.hex + +Then use the combined.hex file with the to write the FLASH image. +If you do this a lot, you will probably want to invest a little time +to develop a tool to automate these steps. + +STATUS: This configuration was added on 8 June 2018 primarily to assure +that all of the components are in place to support the PROTECTED mode +build. This configuration, however, has not been verified as of this +writing. + +netnsh +------ + +This configuration is similar to the nsh configuration except that is +has networking enabled, both IPv4 and IPv6. This NSH configuration is +focused on network-related testing. + +nsh +--- + +Configures the NuttShell (nsh) located at examples/nsh. This NSH +configuration is focused on low level, command-line driver testing. +Built-in applications are supported, but none are enabled. This +configuration does not support a network. + +lvgl +---- + +Configures the Littlev graphic library (lvgl) demo located under +examples/lvgldemo. This configuration needs the optional LCD model +RK043FN02H-CT from NXP. The LCD panel comes with the integrated +capacitive touchscreen sensor FT5336GQQ connected to the LPI2C1 bus, +address 0x38. NuttX support such touchscreen device via the driver +ft5x06 (drivers/input/ft5x06.c). At the moment only the polling +method is available, the board features an interrupt line connected +to the touchscreen sensor IC. + +IMXRT1064 MCU provides the integrated LCD driver. + +The LCD panel features: + - size 4.3" + - resolution 480×272 RGB + - backlight driver + - dimensions [mm]: 105.5 (W) x 67.2(H) x 4.35(D) Max. + +To run the lvgl demo please type "lvgldemo" at nsh prompt:: + + nsh> lvgldemo diff --git a/Documentation/platforms/arm/imxrt/boards/teensy-4.x/index.rst b/Documentation/platforms/arm/imxrt/boards/teensy-4.x/index.rst index 5745d304837..d3dcb1b3c42 100644 --- a/Documentation/platforms/arm/imxrt/boards/teensy-4.x/index.rst +++ b/Documentation/platforms/arm/imxrt/boards/teensy-4.x/index.rst @@ -96,7 +96,17 @@ This configuration can be easily changed to work with Teensy 4.0 by selecting ``CONFIG_TEENSY_40=y``. This configuration runs over LPUART1 (pins 24 and 25 on Teensy). Communication -over USB console can be turn on, but it couses problems with FlexCAN. +over USB console can be turn on, but it causes problems with FlexCAN. + +enc-4.1 +------- + +This is an nsh configuration (see above) with added support of incremental +encoder. Phase A is connected to GPIO_EMC_07 (pin 33), phase B to GPIO_EMC_06 +(pin 4) and INDEX to GPIO_B0_12 (pin 32). Only encoder 1 is connected to those +pins. + +Function of the encoder can be tested by application "qe". netnsh-4.1 ---------- @@ -108,6 +118,17 @@ focused on network-related testing. This configuration cannot be changed to Teensy 4.0 as this board does not have Ethernet capability. +pwm-4.1 +------- + +This configuration is similar to the nsh configuration with enabled +FlexPWM driver. Submodules 1 (pin 4) and 2 (pin 5) of FlexPWM2 are turn +on aswell as ultiple channel PWM output. Functionality can be tested +with example application "pwm". Each channel runs different duty cycle. + +This configuration can be easily changed to work with Teensy 4.0 by +selecting ``CONFIG_TEENSY_40=y``. + sd-4.1 ------ diff --git a/Documentation/platforms/arm/imxrt/index.rst b/Documentation/platforms/arm/imxrt/index.rst index 6a0f9b3d4ba..95381f5ee6b 100644 --- a/Documentation/platforms/arm/imxrt/index.rst +++ b/Documentation/platforms/arm/imxrt/index.rst @@ -52,7 +52,7 @@ ENET Yes FlexIO No GPIO Yes I2S Yes -PWM No +PWM Yes SAI No SPDIF No SPI Yes @@ -69,7 +69,7 @@ range of supply voltage (rail-to-rail operation). ADC --- -ADC driver with the successive approximation analog/digital convertor. The lower-half of +ADC driver with the successive approximation analog/digital converter. The lower-half of this driver is initialize by calling :c:func:`imxrt_adcinitialize`. CAN @@ -82,7 +82,7 @@ calling :c:func:`imxrt_cannitialize()`. There is an booting option that automatically provides initialization of network interface in the early stages of booting and therefore calling :c:func:`imxrt_cannitialize()` via -board specific logic is not neccessary. This however works only when there is only one +board specific logic is not necessary. This however works only when there is only one interface in the chip. For running more interfaces (like CAN and Ethernet), network late initialization must be turn on by CONFIG_NETDEV_LATEINIT and board specific logic must call lower-half part of drivers. @@ -95,7 +95,7 @@ CMOS Sensor interface which enables the chip to connect directly to external CMO DAC --- -Digital/analog convertor for external signal is only supported in i.MX RT1170 MCU. It is 12 bit +Digital/analog converter for external signal is only supported in i.MX RT1170 MCU. It is 12 bit lower power, general purpose DAC. eLCDIF @@ -117,7 +117,7 @@ by calling :c:func:`imxrt_netnitialize`. There is an booting option that automatically provides initialization of network interface in the early stages of booting and therefore calling :c:func:`imxrt_cannitialize()` via -board specific logic is not neccessary. This however works only when there is only one +board specific logic is not necessary. This however works only when there is only one interface in the chip. For running more interfaces (like CAN and Ethernet), network late initialization must be turn on by CONFIG_NETDEV_LATEINIT and board specific logic must call lower-half part of drivers. @@ -137,7 +137,7 @@ done by :c:func:`imxrt_gpio_write` function and reading is done by :c:func:`imxr MCUs i.MX RT1060 and higher includes both standard speed GPIOs (1-5) and high speed GPIOS (6-9). Regular and high speed GPIO share the same pins (GPIO1 is with GPIO6 etc), -therefore IOMUXC_GPR_GPR26-29 registers are used to determine what modue is used for the +therefore IOMUXC_GPR_GPR26-29 registers are used to determine what module is used for the GPIO pins. @@ -150,7 +150,9 @@ as a slave. The lower-half of this driver is initialize by calling :c:func:`imxr PWM --- -Pulse width modulator supported in i.MX RT1010 and higher. +Pulse width modulator supported in i.MX RT1010 and higher. Multiple channels option is evailable. +Output on pin B is currently supported only as a complementary option to pin A. +The lower-half of this driver is initialize by calling :c:func:`imxrt_pwminitialize`. SAI --- @@ -160,7 +162,7 @@ Synchronous audio interface provided by I2C module. Supported in i.MX RT1015 and SPDIF ----- -Sony/Philips digital interface audio block. It is a stereo transciever that allows the +Sony/Philips digital interface audio block. It is a stereo transceiver that allows the processor to receive and transmit digital audio. Supported in i.MX RT1010 and higher. SPI diff --git a/Documentation/platforms/arm/nrf52/index.rst b/Documentation/platforms/arm/nrf52/index.rst index fee6e803270..582de9cc192 100644 --- a/Documentation/platforms/arm/nrf52/index.rst +++ b/Documentation/platforms/arm/nrf52/index.rst @@ -63,7 +63,7 @@ GPIO/GPIOTE ----------- Pins can be configured/operated using ``nrf52_gpio_*`` functions. Interrupts are -handled via the GPIOTE peripheral in one of two ways: via a GPIOTE channel or via +handled via the GPIOTE peripheral in one of two ways: via a GPIOTE channel or via PORT events. The former allows for simultaneous rising/falling edge-sensitive interrupts per-pin. However, as there are a limited number of channels (and sometimes these are used by some drivers for specific tasks), it may not always be possible to use @@ -88,7 +88,7 @@ is initialized by calling :c:func:`nrf52_adcinitialize`. I2C --- -I2C is supported both in polling and interrupt mode (via EasyDMA). +I2C is supported both in polling and interrupt mode (via EasyDMA). .. note:: The I2C peripheral does not support sending two transfers without sending a START nor RSTART. For this reason, this is supported via an internal buffer where @@ -105,7 +105,7 @@ SPI is supported both in polling and interrupt-based (via EasyDMA) mode. The lat supports arbitrarily long transfers using Nordic's list-mode EasyDMA (intermediate transfers are currently still manually started). -It is possible to use SPI without either MOSI/MISO pin defined by simply not providing +It is possible to use SPI without either MOSI/MISO pin defined by simply not providing the relevant ``BOARD_SPI*_MISO/MOSI_PIN`` definition. This implementation support power management hooks, which will disable SPI peripheral when @@ -115,7 +115,7 @@ UART ---- UART is implemented using polling. UARTE EasyDMA feature is not yet supported. -This may introduce a large number of interrupts which may be undesireable. +This may introduce a large number of interrupts which may be undesirable. PPI --- @@ -166,7 +166,7 @@ you need to call :c:func:`nrf52_sdc_initialize` on boot, which will initialize t SDC support involves registering various high-priority zero-latency interrupts and thus requires enabling BASEPRI and high-priority interrupt support. On supported boards, a sample ``sdc`` configuration -is provided with settings already set. +is provided with settings already set. Note that in this case, some peripherals (mostly those related to BLE) will be unavailable. Some PPI channels will also be ocuppied (``NRF52_PPI_NUM_CONFIGURABLE_CHANNELS`` will be set accordingly in this case). diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitC-02-v1.1.png b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitC-02-v1.1.png new file mode 100644 index 00000000000..88a89947554 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitC-02-v1.1.png differ diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitM-1-v1.0.png b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitM-1-v1.0.png new file mode 100644 index 00000000000..ad0c387cc73 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitM-1-v1.0.png differ diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst new file mode 100644 index 00000000000..180245a3c90 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst @@ -0,0 +1,97 @@ +=============== +ESP32-C3 DevKit +=============== + +The ESP32-C3 DevKit is an entry-level development board equipped with either +an ESP32-C3-WROOM-02 or an ESP32-C3-MINI-1. +ESP32-C3-WROOM-02 and ESP32-C3-MINI-1 are SoMs based on the RISC-V ESP32-C3 CPU. + +Most of the I/O pins are broken out to the pin headers on both sides for easy +interfacing. Developers can either connect peripherals with jumper wires or +mount ESP32-C3 DevKit on a breadboard. + +.. list-table:: + :align: center + + * - .. figure:: ESP32-C3-DevKitC-02-v1.1.png + :align: center + + ESP32-C3-DevKitC-02 + + - .. figure:: ESP32-C3-DevKitM-1-v1.0.png + :align: center + + ESP32-C3-DevKitM-1 + +Buttons and LEDs +================ + +Buttons +------- +There are two buttons labeled Boot and RST. The RST button is not available +to software. It pulls the chip enable line that doubles as a reset line. + +The BOOT button is connected to IO9. On reset it is used as a strapping +pin to determine whether the chip boots normally or into the serial +bootloader. After reset, however, the BOOT button can be used for software +input. + +LEDs +---- +There is one on-board LED that indicates the presence of power. +Another WS2812 LED is connected to GPIO8 and is available for software. + +Configurations +============== + +nsh +--- + +Basic configuration to run the NuttShell (nsh). + +gpio +____ + +This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and +GPIO9 as an interrupt pin. + +At the nsh, we can turn the outputs on and off with the following:: + + nsh> gpio -o 1 /dev/gpout0 + nsh> gpio -o 1 /dev/gpout1 + + nsh> gpio -o 0 /dev/gpout0 + nsh> gpio -o 0 /dev/gpout1 + +We can use the interrupt pin to send a signal when the interrupt fires:: + + nsh> gpio -w 14 /dev/gpint2 + +The pin is configured as a rising edge interrupt, so after issuing the +above command, connect it to 3.3V. + +watchdog +-------- + +This configuration tests the watchdog timers. It includes the 2 MWDTS, +adds driver support, registers the WDTs as devices and includes the watchdog +example application. + +To test it, just run the following command:: + + nsh> wdog -i /dev/watchdogX + +Where X is the watchdog instance. + +watcher +------- + +This configuration tests the watchdog timers in the capture mode. +It includes the 2 MWDTS, adds driver support, registers the WDTs as devices +and includes the watcher and watched example applications. + +To test it, just run the following command:: + + nsh> watcher + nsh> watched + diff --git a/Documentation/platforms/risc-v/esp32c3/index.rst b/Documentation/platforms/risc-v/esp32c3/index.rst new file mode 100644 index 00000000000..3a9c9ca13b8 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32c3/index.rst @@ -0,0 +1,127 @@ +================== +Espressif ESP32-C3 +================== + +The ESP32-C3 is an ultra-low-power and highly integrated SoC with a RISC-V +core and supports 2.4 GHz Wi-Fi and Bluetooth Low Energy. + +* Address Space + - 800 KB of internal memory address space accessed from the instruction bus + - 560 KB of internal memory address space accessed from the data bus + - 1016 KB of peripheral address space + - 8 MB of external memory virtual address space accessed from the instruction bus + - 8 MB of external memory virtual address space accessed from the data bus + - 480 KB of internal DMA address space +* Internal Memory + - 384 KB ROM + - 400 KB SRAM (16 KB can be configured as Cache) + - 8 KB of SRAM in RTC +* External Memory + - Up to 16 MB of external flash +* Peripherals + - 35 peripherals +* GDMA + - 7 modules are capable of DMA operations. + +ESP32-C3 Toolchain +================== + +A generic RISC-V toolchain can be used to build ESP32-C3 projects. +SiFive's toolchain can be downloaded from: https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz + +Second stage bootloader and partition table +=========================================== + +The NuttX port for now relies on IDF's second stage bootloader to carry on some hardware +initializations. The binaries for the bootloader and the partition table can be found in +this repository: https://github.com/espressif/esp-nuttx-bootloader +That repository contains a dummy IDF project that's used to build the bootloader and +partition table, these are then presented as Github assets and can be downloaded +from: https://github.com/espressif/esp-nuttx-bootloader/releases +Download ``bootloader-esp32c3.bin`` and ``partition-table-esp32c3.bin`` and place them +in a folder, the path to this folder will be used later to program them. This +can be: ``../esp-bins`` + +Building and flashing +===================== + +First make sure that ``esptool.py`` is installed. This tool is used to convert +the ELF to a compatible ESP32 image and to flash the image into the board. +It can be installed with: ``pip install esptool``. + +Configure the NUttX project: ``./tools/configure.sh esp32c3-devkit:nsh`` +Run ``make`` to build the project. Note that the conversion mentioned above is +included in the build process. +The `esptool.py` command to flash all the binaries is:: + + esptool.py --chip esp32c3 --port /dev/ttyUSBXX --baud 921600 write_flash 0x0 bootloader.bin 0x8000 partition-table.bin 0x10000 nuttx.bin + +However, this is also included in the build process and we can build and flash with:: + + make download ESPTOOL_PORT= ESPTOOL_BINDIR=../esp-bins + +Where ```` is typically ``/dev/ttyUSB0`` or similar and ``../esp-bins`` is +the path to the folder containing the bootloader and the partition table +for the ESP32-C3 as explained above. +Note that this step is required only one time. Once the bootloader and partition +table are flashed, we don't need to flash them again. So subsequent builds +would just require: ``make download ESPTOOL_PORT=/dev/ttyUSBXX`` + +Debugging with OpenOCD +====================== + +Download and build OpenOCD from Espressif, that can be found in +https://github.com/espressif/openocd-esp32 + +If you have an ESP32-C3 ECO3, no external JTAG is required to debug, the ESP32-C3 +integrates a USB-to-JTAG adapter. + +OpenOCD can then be used:: + + openocd -c 'set ESP_RTOS none' -f board/esp32c3-builtin.cfg + +For versions prior to ESP32-C3 ECO3, an external JTAG adapter is needed. +It can be connected as follows:: + + TMS -> GPIO4 + TDI -> GPIO5 + TCK -> GPIO6 + TDO -> GPIO7 + +Furthermore, an efuse needs to be burnt to be able to debug:: + + espefuse.py -p burn_efuse DIS_USB_JTAG + +OpenOCD can then be used:: + + openocd -c 'set ESP_RTOS none' -f board/esp32c3-ftdi.cfg + +Peripheral Support +================== + +The following list indicates the state of peripherals' support in NuttX: + +========== ======= ===== +Peripheral Support NOTES +========== ======= ===== +GPIO Yes +UART Yes +SPI Yes +I2C Yes +DMA Yes +Wifi Yes +SPIFLASH Yes +Timers Yes +Watchdog Yes +RTC No +RNG Yes +AES No +eFuse No +ADC No +Bluetooth No +LED_PWM No +SHA No +RSA No +========== ======= ===== + + diff --git a/Documentation/platforms/risc-v/mpfs/boards/icicle/icicle.png b/Documentation/platforms/risc-v/mpfs/boards/icicle/icicle.png new file mode 100644 index 00000000000..3ed60749767 Binary files /dev/null and b/Documentation/platforms/risc-v/mpfs/boards/icicle/icicle.png differ diff --git a/Documentation/platforms/risc-v/mpfs/boards/icicle/index.rst b/Documentation/platforms/risc-v/mpfs/boards/icicle/index.rst new file mode 100644 index 00000000000..725654566a5 --- /dev/null +++ b/Documentation/platforms/risc-v/mpfs/boards/icicle/index.rst @@ -0,0 +1,79 @@ +==================== +PolarFire Icicle Kit +==================== + +.. list-table:: + :align: center + + * - .. figure:: icicle.png + :align: center + +CPU +--- +PolarFire SoC FPGA (MPFS250T-FCVG484EES) + +- SiFive E51 Monitor core (1 x RV64IMAC) +- SiFive U54 Application cores (4 x RV64GC) +- and Secure boot + + +Memory and storage +------------------ +- 2 GB LPDDR4 x 32 +- 1 Gb SPI flash +- 8 GB eMMC flash & SD card slot (multiplexed) + + +Programming & Debugging +----------------------- +Onboard JTAG connector or onboard embedded FlashPro (multiplexed) + +- UART via micro USB +- 52 x test points + + +Interfaces +---------- + +- 4 x 12.7 Gbps SERDES +- PCIe Gen2 Rootport +- 2 x Gigabit Ethernet +- Micro USB 2.0 Hi-Speed OTG +- 4 x UART (via single micro USB) +- 2 x CAN +- 2 x SPI +- 2 x I²C + +Expansion +--------- +- Raspberry Pi compatible 40-pin header +- mikroBUS socket + +Sensor +------ +- Power sensor (pac1934) + + + +Buttons and LEDs +================ + +Buttons +------- +There are 3 buttons and reset button. The Reset button is not available +to software by default. + + +LEDs +---- +There is 4 user controlled on-board LEDs. + + +Configurations +============== + +nsh +--- + +Basic configuration to run the NuttShell (nsh). + diff --git a/Documentation/platforms/risc-v/mpfs/index.rst b/Documentation/platforms/risc-v/mpfs/index.rst new file mode 100644 index 00000000000..3ab77a1a257 --- /dev/null +++ b/Documentation/platforms/risc-v/mpfs/index.rst @@ -0,0 +1,82 @@ +=========================== +Microchip Polarfile (MPFS) +=========================== + +RV64 64-bit RISC-V multiprocessor-based Microcontroller Subsystem +(MPFS025T, MPFS095T, MPFS160T, MPFS250T, MPFS460T) + + +MPFS Toolchain +============== + +A generic RISC-V toolchain can be used to build MPFS projects. +Like: https://xpack.github.io/riscv-none-embed-gcc or https://github.com/sifive/freedom-tools/releases + + +Booting +======= + +The NuttX port for now relies on HSS bootloader to carry on some hardware initializations. + + +Building and flashing +===================== + +First make sure that ``hss-payload-generator`` is installed. +Available from: https://github.com/polarfire-soc/hart-software-services + +This tool is used to convert the ELF/bin to a compatible HSS payload image + +Configure the NuttX project: ``./tools/configure.sh icicle:nsh`` +Run ``make`` to build the project. + +Create HSS payload bin:: + + hss-payload-generator -v -c hss-nuttx.yml payload.bin + + +Debugging with OpenOCD +====================== + +Compatible OpenOCD and configs can be downloaded from: +https://www.microsemi.com/product-directory/design-tools/4879-softconsole#downloads + + +OpenOCD can then be used:: + + openocd -c "set DEVICE MPFS" --file board/microsemi-riscv.cfg + + +Peripheral Support +================== + +The following list indicates the state of peripherals' support in NuttX: + +============ ======= ===== +Peripheral Support NOTES +============ ======= ===== +GPIO Yes +MMUART Yes Uart mode only +SPI Yes +I2C Yes +Timers No +Watchdog No +RTC No +CAN No +eNVM No +USB No +eMMC SD/SDIO No +============ ======= ===== + + + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* + + diff --git a/Documentation/platforms/xtensa/esp32/index.rst b/Documentation/platforms/xtensa/esp32/index.rst index c47ab0c05ea..98465240ba8 100644 --- a/Documentation/platforms/xtensa/esp32/index.rst +++ b/Documentation/platforms/xtensa/esp32/index.rst @@ -417,7 +417,7 @@ I assume that: - You did not install OpenOCD; binaries are available at openocd-esp32/src and interface scripts are in - openocd-eps32/tcl/interface + openocd-esp32/tcl/interface - I select the configuration for the Olimex ARM-USB-OCD debugger. diff --git a/Documentation/quickstart/compiling.rst b/Documentation/quickstart/compiling.rst index c2a2ae48237..0aef2072a7b 100644 --- a/Documentation/quickstart/compiling.rst +++ b/Documentation/quickstart/compiling.rst @@ -21,7 +21,7 @@ a pre-existing configuration. To list all supported configurations you can do: $ ./tools/configure.sh -L | less The output is in the format ``:``. You will see that -generally all boards support the ``nsh`` configuration which is a good sarting point +generally all boards support the ``nsh`` configuration which is a good starting point since it enables booting into the interactive command line :doc:`/applications/nsh/index`. @@ -43,7 +43,7 @@ configuration system with: $ cd nuttx/ $ make menuconfig - + Modifying the configuration is covered in :doc:`configuring`. Build NuttX @@ -66,7 +66,7 @@ To clean the build, you can do: .. code-block:: console $ make clean - + .. tip:: To increase build speed (or of any other target such as ``clean``), you can diff --git a/Documentation/quickstart/install.rst b/Documentation/quickstart/install.rst index e423d028d53..f08b0362eda 100644 --- a/Documentation/quickstart/install.rst +++ b/Documentation/quickstart/install.rst @@ -61,7 +61,7 @@ First, install the following set of system dependencies according to your Operat KConfig frontend ---------------- -NuttX configuration system uses `KConfig `_ which is exposed via a series of interactive menu-based *frontends*, part of the ``kconfig-frontends`` package. Depending on your OS you may use a precompiled package or you will have to build it from source: +NuttX configuration system uses `KConfig `_ which is exposed via a series of interactive menu-based *frontends*, part of the ``kconfig-frontends`` package. Depending on your OS you may use a precompiled package or you will have to build it from source, which is available in the `NuttX tools repository `_: .. tabs:: @@ -71,12 +71,13 @@ NuttX configuration system uses `KConfig dialout - + Where ```` is your username. You will need to log out from your desktop for the change to have effect. diff --git a/Documentation/reference/os/iob.rst b/Documentation/reference/os/iob.rst index 908dce8ba4e..287aa3d7437 100644 --- a/Documentation/reference/os/iob.rst +++ b/Documentation/reference/os/iob.rst @@ -164,7 +164,8 @@ Public Function Prototypes - :c:func:`iob_remove_queue()` - :c:func:`iob_peek_queue()` - :c:func:`iob_free_queue()` - - :c:func:`iob_destroy_queue()` + - :c:func:`iob_free_queue_qentry()` + - :c:func:`iob_get_queue_size()` - :c:func:`iob_copyin()` - :c:func:`iob_trycopyin()` - :c:func:`iob_copyout()` @@ -192,23 +193,25 @@ Public Function Prototypes buffer at the head of the free list without waiting for a buffer to become free. -.. c:function:: FAR struct iob_s *iob_free(FAR struct iob_s *iob); +.. c:function:: FAR struct iob_s *iob_free(FAR struct iob_s *iob, \ + enum iob_user_e producerid); Free the I/O buffer at the head of a buffer chain returning it to the free list. The link to the next I/O buffer in the chain is return. -.. c:function:: void iob_free_chain(FAR struct iob_s *iob); +.. c:function:: void iob_free_chain(FAR struct iob_s *iob, \ + enum iob_user_e producerid); Free an entire buffer chain, starting at the beginning of the I/O buffer chain -.. c:function:: int iob_add_queue(FAR struct iob_s *iob, FAR void *priv, FAR struct iob_queue_s *iobq) +.. c:function:: int iob_add_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq) Add one I/O buffer chain to the end of a queue. May fail due to lack of resources. -.. c:function:: void iob_tryadd_queue(FAR struct iob_s *iob, FAR void *priv, FAR struct iob_queue_s *iobq) +.. c:function:: void iob_tryadd_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq) Add one I/O buffer chain to the end of a queue without waiting for resources to become free. @@ -232,13 +235,19 @@ Public Function Prototypes :return: Returns a reference to the I/O buffer chain at the head of the queue. -.. c:function:: void iob_free_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq); +.. c:function:: void iob_free_queue(FAR struct iob_queue_s *qhead, \ + enum iob_user_e producerid); Free an entire queue of I/O buffer chains. -.. c:function:: void iob_destroy_queue(FAR struct iob_queue_s *qhead); +.. c:function:: void iob_free_queue_qentry(FAR struct iob_s *iob, \ + FAR struct iob_queue_s *iobq); - Destroy all I/O buffer chains from the iob queue. + Queue helper for get the iob queue buffer size. + +.. c:function:: unsigned int iob_get_queue_size(FAR struct iob_queue_s *queue); + + Free an iob entire queue of I/O buffer chains. .. c:function:: int iob_copyin(FAR struct iob_s *iob, FAR const uint8_t *src, \ unsigned int len, unsigned int offset, bool throttled); @@ -270,14 +279,15 @@ Public Function Prototypes Concatenate iob_s chain iob2 to iob1. -.. c:function:: FAR struct iob_s *iob_trimhead(FAR struct iob_s *iob, unsigned int trimlen) +.. c:function:: FAR struct iob_s *iob_trimhead(FAR struct iob_s *iob, \ + unsigned int trimlen, enum iob_user_e producerid) Remove bytes from the beginning of an I/O chain. Emptied I/O buffers are freed and, hence, the beginning of the chain may change. .. c:function:: FAR struct iob_s *iob_trimhead_queue(FAR struct iob_queue_s *qhead, \ - unsigned int trimlen); + unsigned int trimlen, enum iob_user_e producerid); Remove bytes from the beginning of an I/O chain at the head of the queue. Emptied I/O buffers are freed and, @@ -290,19 +300,22 @@ Public Function Prototypes :return: The new iob at the head of the queue is returned. -.. c:function:: FAR struct iob_s *iob_trimtail(FAR struct iob_s *iob, unsigned int trimlen); +.. c:function:: FAR struct iob_s *iob_trimtail(FAR struct iob_s *iob, \ + unsigned int trimlen, enum iob_user_e producerid); Remove bytes from the end of an I/O chain. Emptied I/O buffers are freed NULL will be returned in the special case where the entry I/O buffer chain is freed. -.. c:function:: FAR struct iob_s *iob_pack(FAR struct iob_s *iob); +.. c:function:: FAR struct iob_s *iob_pack(FAR struct iob_s *iob, \ + enum iob_user_e producerid); Pack all data in the I/O buffer chain so that the data offset is zero and all but the final buffer in the chain are filled. Any emptied buffers at the end of the chain are freed. -.. c:function:: int iob_contig(FAR struct iob_s *iob, unsigned int len); +.. c:function:: int iob_contig(FAR struct iob_s *iob, unsigned int len, \ + enum iob_user_e producerid); Ensure that there is ``len`` bytes of contiguous space at the beginning of the I/O buffer chain starting at diff --git a/Documentation/reference/os/wqueue.rst b/Documentation/reference/os/wqueue.rst index d22291bdb32..c3fc95489a8 100644 --- a/Documentation/reference/os/wqueue.rst +++ b/Documentation/reference/os/wqueue.rst @@ -10,10 +10,10 @@ for delayed processing, or for serializing activities. Classes of Work Queues ====================== -There are three different classes of -work queues, each with different properties and intended usage. -These class of work queues along with the common work queue -interface are described in the following paragraphs. +There are three different classes of work queues, each with +different properties and intended usage. These classes of work +queues along with the common work queue interface are described in +the following paragraphs. High Priority Kernel Work queue ------------------------------- @@ -60,7 +60,7 @@ to match the highest priority client. **Configuration Options**. -- ``CONFIG_SCHED_HPWORK``. Enables the hight priority work queue. +- ``CONFIG_SCHED_HPWORK``. Enables the high priority work queue. - ``CONFIG_SCHED_HPNTHREADS``. The number of threads in the high-priority queue's thread pool. Default: 1 - ``CONFIG_SCHED_HPWORKPRIORITY``. The execution priority of the @@ -72,7 +72,8 @@ to match the highest priority client. queues: - ``CONFIG_SIG_SIGWORK`` The signal number that will be used to - wake-up the worker thread. This same signal is used with the + wake-up the worker thread. This same signal is used with various + internal worker threads. Default: 17 Low Priority Kernel Work Queue @@ -88,9 +89,9 @@ work queue runs at a lower priority than the high priority work queue, of course, and so is inappropriate to serve as a driver *bottom half*. It is, otherwise, very similar to the high priority work queue and most of the discussion above for the high priority -work queue applies equally here. The lower priority work queue -does have one important, however, that make it better suited for -some tasks: +work queue applies equally here. The lower priority work queue does +have one important property, however, that makes it better suited +for some tasks: **Priority Inheritance**. The lower priority worker thread(s) support *priority inheritance* (if @@ -99,8 +100,8 @@ lower priority worker thread can then be adjusted to match the highest priority client. **NOTE:** This priority inheritance feature is not automatic. - The lower priority worker thread will always a fixed priority - unless additional logic implements that calls + The lower priority worker thread will always have a fixed + priority unless additional logic calls ``lpwork_boostpriority()`` to raise the priority of the lower priority worker thread (typically called before scheduling the work) and then calls the matching ``lpwork_restorepriority()`` @@ -143,19 +144,18 @@ User-Mode Work Queue **Work Queue Accessibility**. The high- and low-priority worker threads are kernel-mode threads. In the normal, *flat* NuttX -build, these work queues are are useful to application code and +build, these work queues are useful to application code and may be shared. However, in the NuttX protected and kernel build modes, kernel mode code is isolated and cannot be accessed from user-mode code. **User-Mode Work Queue**. if either ``CONFIG_BUILD_PROTECTED`` or ``CONFIG_BUILD_KERNEL`` are selected, then the option to enable a -special user-mode work queue is enable. The interface to the -user-mode work queue is identical to the interface to the -kernel-mode work queues and the user-mode work queue is -functionally equivalent to the high priority work queue. It -differs in that its implementation does not depend on internal, -kernel-space facilities. +special user-mode work queue is enabled. The interface to the user- +mode work queue is identical to that of the kernel-mode work queues +and the user-mode work queue is functionally equivalent to the high +priority work queue. It differs in that its implementation does not +depend on internal, kernel-space facilities. **Configuration Options**. @@ -181,10 +181,10 @@ interface function identifies the work queue: **Kernel-Mode Work Queue IDs:** - ``HPWORK``. This ID of the high priority work queue that should - only be used for hi-priority, time-critical, driver bottom-half + only be used for high-priority, time-critical, driver bottom-half functions. - ``LPWORK``. This is the ID of the low priority work queue that - can be used for any purpose. if ``CONFIG_SCHED_LPWORK`` is not + can be used for any purpose. If ``CONFIG_SCHED_LPWORK`` is not defined, then there is only one kernel work queue and ``LPWORK`` is equal to ``HPWORK``. @@ -192,7 +192,7 @@ interface function identifies the work queue: - ``USRWORK``. This is the ID of the user-mode work queue that can be used for any purpose by applications. In a flat build, - ``LPWORK`` is equal to ``LPWORK`` so that user applications + ``USRWORK`` is equal to ``LPWORK`` so that user applications will use the lower priority work queue (if there is one). Work Queue Interface Types @@ -221,14 +221,14 @@ Work Queue Interfaces zero by the caller. Otherwise, the work structure is completely managed by the work queue logic. The caller should never modify the contents of the work queue structure directly. If - ``work_queue()`` is called before the previous work as been + ``work_queue()`` is called before the previous work has been performed and removed from the queue, then any pending work will be canceled and lost. :param qid: The work queue ID. :param work: The work structure to queue :param worker: The worker callback to be invoked. The callback - will invoked on the worker thread of execution. + will be invoked on the worker thread of execution. :param arg: The argument that will be passed to the worker callback function when it is invoked. @@ -243,10 +243,10 @@ Work Queue Interfaces Cancel previously queued work. This removes work from the work queue. After work has been cancelled, it may be - re-queue by calling ``work_queue()`` again. + re-queued by calling ``work_queue()`` again. :param qid: The work queue ID. - :param work: The previously queue work structure to cancel. + :param work: The previously queued work structure to cancel. :return: Zero is returned on success; a negated ``errno`` is returned on failure. diff --git a/Documentation/reference/user/01_task_control.rst b/Documentation/reference/user/01_task_control.rst index 268250e3cbf..b3d0c90d9bb 100644 --- a/Documentation/reference/user/01_task_control.rst +++ b/Documentation/reference/user/01_task_control.rst @@ -199,7 +199,7 @@ Functions - Deletion of self is supported, but only because ``task_delete()`` will re-direct processing to ``exit()``. -.. :c:funcion:: int task_restart(pid_t pid) +.. :c:function:: int task_restart(pid_t pid) This function *restarts* a task. The task is first terminated and then reinitialized with same ID, priority, original entry diff --git a/Documentation/reference/user/02_task_scheduling.rst b/Documentation/reference/user/02_task_scheduling.rst index c24b2dcce46..ece54ac852b 100644 --- a/Documentation/reference/user/02_task_scheduling.rst +++ b/Documentation/reference/user/02_task_scheduling.rst @@ -54,7 +54,8 @@ Functions **POSIX Compatibility:** Comparable to the POSIX interface of the same name. Differences from the full POSIX implementation include: - - The range of priority values for the POSIX call is 0 to 255. + - The range of priority values for the POSIX call is 0 to 255. The + priority 0 is the lowest priority and 255 is the highest priority. .. note:: Setting a task's priority to the same value has the similar effect to ``sched_yield()``: The task will be moved to after all other tasks diff --git a/Documentation/reference/user/03_task_control.rst b/Documentation/reference/user/03_task_control.rst index 85f13582638..3b2c5241748 100644 --- a/Documentation/reference/user/03_task_control.rst +++ b/Documentation/reference/user/03_task_control.rst @@ -86,15 +86,7 @@ there are three important configuration options that can change that. allocations and to improve allocation performance, child task exit status structures are pre-allocated when the system boots. This setting determines the number of child status structures that will be - pre-allocated. If this setting is not defined or if it is defined to - be zero then a value of 2\*\ ``MAX_TASKS`` is used. - - Note that there cannot be more that ``CONFIG_MAX_TASKS`` tasks in - total. However, the number of child status structures may need to be - significantly larger because this number includes the maximum number - of tasks that are running PLUS the number of tasks that have exit'ed - without having their exit status reaped (via :c:func:`wait`, - :c:func:`waitpid` or :c:func:`waitid`). + pre-allocated. Obviously, if tasks spawn children indefinitely and never have the exit status reaped, then you may have a memory leak! (See **Warning** diff --git a/Documentation/reference/user/04_message_queue.rst b/Documentation/reference/user/04_message_queue.rst index 22877039b47..d5d6b8ebe08 100644 --- a/Documentation/reference/user/04_message_queue.rst +++ b/Documentation/reference/user/04_message_queue.rst @@ -19,11 +19,10 @@ handlers may send messages via named message queues. .. c:function:: mqd_t mq_open(const char *mqName, int oflags, ...) - Establishes a connection between a named - message queue and the calling task. After a successful call of - mq_open(), the task can reference the message queue using the address - returned by the call. The message queue remains usable until it is - closed by a successful call to mq_close(). + Establishes a connection between a named message queue and the calling + task. After a successful call of mq_open(), the task can reference the + message queue using the address returned by the call. The message queue + remains usable until it is closed by a successful call to mq_close(). :param mqName: Name of the queue to open :param oflags: Open flags. These may be any combination of: @@ -65,10 +64,10 @@ handlers may send messages via named message queues. .. c:function:: int mq_close(mqd_t mqdes) - Used to indicate that the calling task - is finished with the specified message queued mqdes. The mq_close() - deallocates any system resources allocated by the system for use by this - task for its message queue. + Used to indicate that the calling task is finished with the specified + message queued ``mqdes``. The ``mq_close()`` deallocates any system + resources allocated by the system for use by this task for its message + queue. If the calling task has attached a notification request to the message queue via this ``mqdes`` (see ``mq_notify()``), this attachment will be @@ -104,10 +103,10 @@ handlers may send messages via named message queues. .. c:function:: int mq_send(mqd_t mqdes, const void *msg, size_t msglen, int prio) - Adds the specified message, ``msg``, to - the message queue, ``mqdes``. The ``msglen`` parameter specifies the - length of the message in bytes pointed to by ``msg``. This length must - not exceed the maximum message length from the ``mq_getattr()``. + Adds the specified message, ``msg``, to the message queue, ``mqdes``. + The ``msglen`` parameter specifies the length of the message in bytes + pointed to by ``msg``. This length must not exceed the maximum message + length from the ``mq_getattr()``. If the message queue is not full, ``mq_send()`` will place the ``msg`` in the message queue at the position indicated by the ``prio`` argument. @@ -125,14 +124,14 @@ handlers may send messages via named message queues. However, it behaves differently when called from the interrupt level: - It does not check the size of the queue. It will always post the - message, even if there is already too many messages in queue. This is + message, even if there are already too many messages in queue. This is because the interrupt handler does not have the option of waiting for the message queue to become non-full. - It doesn't allocate new memory (because you cannot allocate memory - from an interrupt handler). Instead, there are are pool of - pre-allocated message structures that may be used just for sending - messages from interrupt handlers. The number of such pre-allocated - messages is a configuration parameter. + from an interrupt handler). Instead, there is a pool of pre-allocated + message structures that may be used just for sending messages from + interrupt handlers. The number of such pre-allocated messages is set + by the ``PREALLOC_MQ_IRQ_MSGS`` configuration parameter. :param mqdes: Message queue descriptor. :param msg: Message to send. @@ -157,10 +156,10 @@ handlers may send messages via named message queues. .. c:function:: int mq_timedsend(mqd_t mqdes, const char *msg, size_t msglen, int prio, \ const struct timespec *abstime); - Adds the specified message, ``msg``, to - the message queue, ``mqdes``. The ``msglen`` parameter specifies the - length of the message in bytes pointed to by ``msg``. This length must - not exceed the maximum message length from the ``mq_getattr()``. + Adds the specified message, ``msg``, to the message queue, ``mqdes``. + The ``msglen`` parameter specifies the length of the message in bytes + pointed to by ``msg``. This length must not exceed the maximum message + length from the ``mq_getattr()``. If the message queue is not full, ``mq_timedsend()`` will place the ``msg`` in the message queue at the position indicated by the ``prio`` @@ -203,12 +202,11 @@ handlers may send messages via named message queues. .. c:function:: ssize_t mq_receive(mqd_t mqdes, void *msg, size_t msglen, int *prio) - Receives the oldest of the highest - priority messages from the message queue specified by ``mqdes``. If the - size of the buffer in bytes, ``msgLen``, is less than the ``mq_msgsize`` - attribute of the message queue, ``mq_receive()`` will return an error. - Otherwise, the selected message is removed from the queue and copied to - ``msg``. + Receives the oldest of the highest priority messages from the message + queue specified by ``mqdes``. If the size of the buffer in bytes, + ``msgLen``, is less than the ``mq_msgsize`` attribute of the message + queue, ``mq_receive()`` will return an error. Otherwise, the selected + message is removed from the queue and copied to ``msg``. If the message queue is empty and ``O_NONBLOCK`` was not set, ``mq_receive()`` will block until a message is added to the message @@ -223,8 +221,8 @@ handlers may send messages via named message queues. :param msg: Buffer to receive the message. :param msglen: Size of the buffer in bytes. :param prio: If not NULL, the location to store message priority. - :return: One success, the length of the selected message in - bytes is returned. On failure, -1 (``ERROR``) is returned and the + :return: On success, the length of the selected message in bytes is + returned. On failure, -1 (``ERROR``) is returned and the ```errno`` <#ErrnoAccess>`__ is set appropriately: - ``EAGAIN`` The queue was empty and the ``O_NONBLOCK`` flag was set @@ -241,12 +239,11 @@ handlers may send messages via named message queues. .. c:function:: ssize_t mq_timedreceive(mqd_t mqdes, void *msg, size_t msglen, \ int *prio, const struct timespec *abstime); - Receives the oldest of the highest - priority messages from the message queue specified by ``mqdes``. If the - size of the buffer in bytes, ``msgLen``, is less than the ``mq_msgsize`` - attribute of the message queue, ``mq_timedreceive()`` will return an - error. Otherwise, the selected message is removed from the queue and - copied to ``msg``. + Receives the oldest of the highest priority messages from the message + queue specified by ``mqdes``. If the size of the buffer in bytes, + ``msgLen``, is less than the ``mq_msgsize`` attribute of the message + queue, ``mq_timedreceive()`` will return an error. Otherwise, the + selected message is removed from the queue and copied to ``msg``. If the message queue is empty and ``O_NONBLOCK`` was not set, ``mq_timedreceive()`` will block until a message is added to the message @@ -270,8 +267,8 @@ handlers may send messages via named message queues. :param prio: If not NULL, the location to store message priority. :param abstime: The absolute time to wait until a timeout is declared. - :return: One success, the length of the selected message in - bytes is returned. On failure, -1 (``ERROR``) is returned and the + :return: On success, the length of the selected message in bytes is + returned. On failure, -1 (``ERROR``) is returned and the ```errno`` <#ErrnoAccess>`__ is set appropriately: - ``EAGAIN``: The queue was empty and the ``O_NONBLOCK`` flag was set @@ -289,11 +286,10 @@ handlers may send messages via named message queues. .. c:function:: int mq_notify(mqd_t mqdes, FAR const struct sigevent *notification) - If the ``notification`` input parameter is not - ``NULL``, this function connects the task with the message queue such - that the specified signal will be sent to the task whenever the message - changes from empty to non-empty. One notification can be attached to a - message queue. + If the ``notification`` input parameter is not ``NULL``, this function + connects the task with the message queue such that the specified signal + will be sent to the task whenever the message queue changes from empty + to non-empty. One notification can be attached to a message queue. If ``notification``; is ``NULL``, the attached notification is detached (if it was held by the calling task) and the queue is available to @@ -337,9 +333,8 @@ handlers may send messages via named message queues. .. c:function:: int mq_setattr(mqd_t mqdes, const struct mq_attr *mqStat, \ struct mq_attr *oldMqStat); - Sets the attributes associated with the - specified message queue "mqdes." Only the "O_NONBLOCK" bit of the - "mq_flags" can be changed. + Sets the attributes associated with the specified message queue "mqdes." + Only the "O_NONBLOCK" bit of the "mq_flags" can be changed. If ``oldMqStat`` is non-null, mq_setattr() will store the previous message queue attributes at that location (just as would have been returned by @@ -357,8 +352,8 @@ handlers may send messages via named message queues. .. c:function:: int mq_getattr(mqd_t mqdes, struct mq_attr *mqStat) - Gets status information and attributes - associated with the specified message queue. + Gets status information and attributes associated with the specified + message queue. :param mqdes: Message queue descriptor :param mqStat: Buffer in which to return attributes. The returned diff --git a/Kconfig b/Kconfig index 9120ec6d4ec..e841572b16e 100644 --- a/Kconfig +++ b/Kconfig @@ -1766,7 +1766,9 @@ config STACK_USAGE_SAFE_PERCENT ---help--- Stack usage precent = up_check_tcbstack() * 100 / tcb->adj_stack_size, this should lower then STACK_USAGE_SAFE_PERCENT. - Idle thread will timely check stack usage when this marco value > 0. + Idle thread will timely check stack usage when this macro value > 0. + + N.B. This feature should not be used in production code. config STACK_CANARIES bool "Compiler stack canaries" diff --git a/LICENSE b/LICENSE index 10472b0873d..44876b3deed 100644 --- a/LICENSE +++ b/LICENSE @@ -205,21 +205,54 @@ uIP === -Many lower-level networking components of NuttX derive from uIP which -has a similar BSD style license: +Many lower-level networking components of NuttX derive from uIP: Copyright (c) 2001-2003, Adam Dunkels. All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote + products derived from this software without specific prior + written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + Rhombus Math Library ==================== The math library used in NuttX derives from the Rhombus OS by Nick Johnson -(with many, many addtions). The Rhombus OS is/was distributed under the ISC -license. The ISC licsense is a permissive license that allows people do -anything with your code with proper attribution and without warranty. The -ISC license is functionally equivalent to the BSD 2-Clause and MIT licenses, -removing some language that is no longer necessary. +(with many, many additions): + + Copyright (C) 2009-2011 Nick Johnson + + Permission to use, copy, modify, and distribute this software for any + purpose with or without fee is hereby granted, provided that the above + copyright notice and this permission notice appear in all copies. + + THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. IGMP ==== diff --git a/README.md b/README.md index fd09d45422c..7d4017555aa 100644 --- a/README.md +++ b/README.md @@ -2092,6 +2092,8 @@ Below is a guide to the available README files in the NuttX source tree: | | | | `- README.txt | | | |- cloudctrl/ | | | | `- README.txt + | | | |- emw3162/ + | | | | `- README.txt | | | |- fire-stm32v2/ | | | | `- README.txt | | | |- hymini-stm32v/ diff --git a/ReleaseNotes b/ReleaseNotes index 5cd996bb28a..dcd1605faef 100644 --- a/ReleaseNotes +++ b/ReleaseNotes @@ -27123,6 +27123,254 @@ NuttX-9.1.0 Release Notes ------------------------- - PR-287 PR-290 examples: Update nxflat and thttpd Makefile's to fix a build breakage. + * Compatibility Concerns -- Changes to Build System: + + If you are building NuttX for a custom board, you may need to make + some of the following changes in build-related files for your board: + + * Rename EXTRADEFINES to EXTRAFLAGS + + In your custom board's scripts/Make.defs file, rename EXTRADEFINES to + EXTRAFLAGS. + + For example, these lines: + + ``` + CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe + ... + CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe + ... + CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) + ``` + + would change as follows: + + ``` + CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe + ... + CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe + ... + CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) + ``` + + See git commit # 459ad9937377a42785692098ff0d73baaa9551e6 in the main + NuttX repository. + + If you forget to do this, memory allocations on the heap probably won't + work and your user tasks won't start. + + To see why, tools/Config.mk assigns a value to KDEFINE such that the + preprocessor symbol __KERNEL__ will be defined when certain source + files are compiled. KDEFINE is passed to nested invocations of 'make' + as EXTRAFLAGS. If your board's scripts/Make.defs still attempts to use + EXTRADEFINES, the preprocessor symbol __KERNEL__ will not be defined in + some of the places that it should be. Suppose you're building a FLAT + build. In this case, include/nuttx/mm/mm.h will not define + MM_KERNEL_USRHEAP_INIT like it should, which will cause nx_start.c not + to call up_allocate_heap() at startup. Therefore, any attempt to + allocate memory on the heap will fail. + + * Rename src/Makefile to src/Make.defs and Modify + + This item pertains only to custom boards that are developed in- tree, + meaning under the NuttX boards/ subdirectory. Out-of-tree boards are + not affected. + + If your custom board directory is in-tree and in a board family that + uses a 'boards/ARCH/FAMILY/common' directory (such as + boards/arm/stm32/common, boards/arm/cxd56xx/common, etc), then you'll + need to make two minor changes to your custom board's src/Makefile: + + (1) Rename it from src/Makefile to src/Make.defs, and + + (2) Near the end of that file, replace this line, which usually + appears at the end: + + ``` + include $(TOPDIR)/boards/Board.mk + ``` + + with these three lines: + + ``` + DEPPATH += --dep-path board + VPATH += :board + CFLAGS += $(shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) + ``` + + See git commit # 6ca46520df38854bf660f9be54957cceede39ded in the main + NuttX repository. + + If you forget to do this, 'make' will report an error, "no rule to make + libboard.a," and the build will fail. + + * Rename WINTOOL to CONFIG_CYGWIN_WINTOOL + + In your custom board's scripts/Make.defs file, rename any instances of + WINTOOL to CONFIG_CYGWIN_WINTOOL. + + For example, change this line: + + ``` + ifeq ($(WINTOOL),y) + ``` + + to this: + + ``` + ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ``` + + See git commit # bd656888f26c92e8832f0e76b395a5ece7704530 in the main + NuttX repository. + + * Remove INCDIROPT + + In your custom board's src/Make.defs file, remove INCDIROPT from CFLAGS. + + For example, change this line: + + ``` + CFLAGS += $(shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) + ``` + + to this: + + ``` + CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) + ``` + + This option, which resolves to -w when CONFIG_CYGWIN_WINTOOL is + configured, is now appended to INCDIR in tools/Config.mk. + + See git commit # 5eae32577e5d5226e5d3027c169eeb369f83f77d in the main + NuttX repository. + + * Remove Unnecessary Variables + + In your custom board's scripts/Make.defs file, It is no longer + necessary to define the following variables unless your build requires + that you assign special values to them: + + - DIRLINK + - DIRUNLINK + - MKDEP + - ASMEXT + - OBJEXT + - LIBEXT + - EXEEXT + + These variables have been refactored into tools/Config.mk. + + See these git commits in the main NuttX repository: + 9ec9431706fd0eb7c4c4410d84dafff68ff31366 (DIRLINK and DIRUNLINK), + 8b42ee421a41214093c0238e479d73a1099b0e82 (MKDEP), and + 567962bd6263bf8809fb63c739f6ec668c69c416 (ASMEXT, OBJEXT, LIBEXT, EXEEXT) + + * Change ${TOPDIR} to $(TOPDIR) + + In your custom board's scripts/Make.defs file, it is recommended to + change ${TOPDIR} to $(TOPDIR) for consistency (change curly braces to + parenthesis). + + See git commit # faf3c0254bb63af89f9eb59beefacb4cba26dd9 in the main + NuttX repository. + + * Remove Workaround For Missing $(TOPDIR)/Make.defs + + In src/Make.defs or src/Makefile for your custom board or custom apps, + the workaround for missing $(TOPDIR)/.config and/or + $(TOPDIR)/Make.defs is no longer needed. To remove the workaround, + delete the minus sign in front of include .config. This is now handled + in the main Makefile and, if those files are missing, will print an + error message with hint to run tools/configure.sh . + + Change this line, located near the top of the file: + + ``` + -include $(TOPDIR)/Make.defs + ``` + + to this: + + ``` + include $(TOPDIR)/Make.defs + ``` + + See git commit # 1a95cce1a3c3ed8b04d1d86b7bd744352cca45a2 in the main + NuttX repository, and git commit + # ead498a7883a654b1d542da94a5fab3ce163361e in the apps repository. + + * Simplify ARCHINCLUDES and ARCHXXINCLUDES + + In your custom board's scripts/Make.defs, ARCHINCLUDES and + ARCHXXINCLUDES can be defined without maintaining two different + versions conditioned upon CONFIG_CYGWIN_WINTOOL (renamed from WINTOOL). + Replace syntax similar to the following: + + ``` + ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + # Windows-native toolchains + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include$(DELIM)cxx}" + else + # Linux/Cygwin-native toolchain + ARCHINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include -isystem $(TOPDIR)$(DELIM)include$(DELIM)cxx + endif + ``` + + with syntax similar to: + + ``` + ARCHINCLUDES += ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include} + ARCHXXINCLUDES += ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include} + ARCHXXINCLUDES += ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include$(DELIM)cxx} + INCDIR is defined in tools/Config.mk and resolves to a shell script or batch file that constructs the appropriate command line argument string to specify include directories for your compiler. + ``` + + See git commit # 7e5b0f81e93c7e879ce8434d57e8bf4e2319c1c0 in the main + NuttX repository. + + * Simplify Board Directory Handling With BOARD_DIR + + In your custom board's Make.defs or Makefile, when setting up build + variables containing paths inside your board directory, a new variable + BOARD_DIR has been introduced that simplifies the syntax: + + Replace syntax like this: + + ``` + $(TOPDIR)$(DELIM)boards$(DELIM)$(CONFIG_ARCH)$(DELIM)$(CONFIG_ARCH_CHIP)$(DELIM)$(CONFIG_ARCH_BOARD) + ``` + + with this variable: + + ``` + $(BOARD_DIR) + ``` + + For example, change this: + + ``` + ARCHSCRIPT = -T$(TOPDIR)$(DELIM)boards$(DELIM)$(CONFIG_ARCH)$(DELIM)$(CONFIG_ARCH_CHIP)$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + ``` + + to this much simpler syntax: + + ``` + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + ``` + + You may find the old syntax being used for variables like ARCHSCRIPT, + LDELFFLAGS, LINKCMDTEMPLATE, SCRIPTDIR, USER_LDSCRIPT, or others. + + BOARD_DIR is defined in tools/Config.mk. + + See git commit # e83c1400b65c65cbdf59c5abcf2ae368f540faef in the main + NuttX repository. + + NuttX-10.0.0 Release Notes ------------------------ diff --git a/arch/Kconfig b/arch/Kconfig index ac10cd23839..7d71aba22ce 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -259,9 +259,17 @@ config ARCH_NEED_ADDRENV_MAPPING bool default n -config ARCH_HAVE_MODULE_TEXT - bool "Special memory region for dynamic code loading" +config ARCH_HAVE_EXTRA_HEAPS + bool default n + ---help--- + Special memory regions used as separate heaps + +config ARCH_HAVE_TEXT_HEAP + bool + default n + ---help--- + Special memory region for dynamic code loading config ARCH_HAVE_MULTICPU bool @@ -371,12 +379,12 @@ config ARCH_USE_MPU is enabled by other, platform-specific logic. In those cases, this selection will always be forced. -config ARCH_USE_MODULE_TEXT - bool "Enable module text allocator" +config ARCH_USE_TEXT_HEAP + bool "Enable separate text allocation for dynamic code loading" default n - depends on ARCH_HAVE_MODULE_TEXT + depends on ARCH_HAVE_TEXT_HEAP ---help--- - This option enable architecture-sepecific memory allocator + This option enables architecture-sepecific memory allocator for dynamic code loading. For example, ESP32 has a separate memory regions for instruction and data and the memory region used for usual malloc doesn't work for instruction. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f51235be88a..c0c30860c14 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -456,6 +456,7 @@ config ARCH_CHIP_CXD56XX select ARCH_HAVE_FPU select ARCH_HAVE_HEAPCHECK select ARCH_HAVE_MULTICPU + select ARCH_HAVE_TEXT_HEAP select ARCH_HAVE_SDIO if MMCSD select ARCH_HAVE_MATH_H ---help--- diff --git a/arch/arm/include/cxd56xx/chip.h b/arch/arm/include/cxd56xx/chip.h index c1afb4dfe0f..794ab8f2627 100644 --- a/arch/arm/include/cxd56xx/chip.h +++ b/arch/arm/include/cxd56xx/chip.h @@ -25,6 +25,10 @@ * Pre-processor Prototypes ****************************************************************************/ +/* physical address conversion macro */ + +#define CXD56_PHYSADDR(a) ((uint32_t)((uint32_t)(a) & 0x9ffffffful)) + #define CXD56M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */ #define CXD56M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ #define CXD56M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ diff --git a/arch/arm/include/cxd56xx/hostif.h b/arch/arm/include/cxd56xx/hostif.h new file mode 100644 index 00000000000..3c58bd70a33 --- /dev/null +++ b/arch/arm/include/cxd56xx/hostif.h @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/arm/include/cxd56xx/hostif.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_CXD56XX_HOSTIF_H +#define __ARCH_ARM_INCLUDE_CXD56XX_HOSTIF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Host interface maximum number of buffers */ + +#define MAX_BUFFER_NUM 32 + +/* Host interface buffer attributes */ + +#define HOSTIF_BUFF_ATTR_ADDR_OFFSET(n) (((n) & 0x3) << 4) + /* 2 to the power of n */ +#define HOSTIF_BUFF_ATTR_FIXLEN (0 << 2) /* fixed length */ +#define HOSTIF_BUFF_ATTR_VARLEN (1 << 2) /* variable length */ +#define HOSTIF_BUFF_ATTR_WRITE (0 << 1) /* from target to host */ +#define HOSTIF_BUFF_ATTR_READ (1 << 1) /* from host to target */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Common buffer configuration */ + +struct hostif_buff_s +{ + uint16_t size; + uint16_t flag; +}; + +/* I2C buffer configuration */ + +struct hostif_i2cconf_s +{ + int address; /* slave address */ + struct hostif_buff_s buff[MAX_BUFFER_NUM]; +}; + +/* SPI buffer configuration */ + +struct hostif_spiconf_s +{ + struct hostif_buff_s buff[MAX_BUFFER_NUM]; +}; + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: hostif_i2cinitialize + * + * Description: + * Initialize the host interface for I2C slave + * + * Input Parameter: + * config - pointer to I2C buffer configuration + * + * Returned Value: + * Return 0 on success. Otherwise, return a negated errno. + * + ****************************************************************************/ + +int hostif_i2cinitialize(FAR struct hostif_i2cconf_s *config); + +/**************************************************************************** + * Name: hostif_spiinitialize + * + * Description: + * Initialize the host interface for SPI slave + * + * Input Parameter: + * config - pointer to SPI buffer configuration + * + * Returned Value: + * Return 0 on success. Otherwise, return a negated errno. + * + ****************************************************************************/ + +int hostif_spiinitialize(FAR struct hostif_spiconf_s *config); + +/**************************************************************************** + * Name: hostif_uninitialize + * + * Description: + * Uninitialize the host interface + * + * Returned Value: + * Return 0 on success. Otherwise, return a negated errno. + * + ****************************************************************************/ + +int hostif_uninitialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_INCLUDE_CXD56XX_HOSTIF_H */ diff --git a/arch/arm/include/cxd56xx/pm.h b/arch/arm/include/cxd56xx/pm.h index 824a0a30541..40506dbbcb9 100644 --- a/arch/arm/include/cxd56xx/pm.h +++ b/arch/arm/include/cxd56xx/pm.h @@ -25,6 +25,7 @@ * Included Files ****************************************************************************/ +#include #include /**************************************************************************** @@ -62,8 +63,9 @@ /* FrequencyLock request flag definitions */ -#define PM_CPUFREQLOCK_FLAG_HV (0x0001) /* request HV */ -#define PM_CPUFREQLOCK_FLAG_LV (0x4000) /* request LV */ +#define PM_CPUFREQLOCK_FLAG_HV (0x0001) /* request HV */ +#define PM_CPUFREQLOCK_FLAG_LV (0x4000) /* request LV */ +#define PM_CPUFREQLOCK_FLAG_HOLD (0x8000) /* hold the current frequency */ /* FrequencyLock identifier tag helper macro function */ @@ -160,7 +162,7 @@ extern "C" int up_pmramctrl(int cmd, uintptr_t addr, size_t size); -#ifdef CONFIG_DEBUG_PM +#ifdef CONFIG_CXD56_PM_DEBUG_INFO /**************************************************************************** * Name: up_pmstatdump * diff --git a/arch/arm/include/imxrt/imxrt102x_irq.h b/arch/arm/include/imxrt/imxrt102x_irq.h index 2918b578972..13ae2b1e254 100644 --- a/arch/arm/include/imxrt/imxrt102x_irq.h +++ b/arch/arm/include/imxrt/imxrt102x_irq.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/include/imxrt/imxrt102x_irq.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/kinetis/kinetis_dma.h b/arch/arm/include/kinetis/kinetis_dma.h index b4da0773318..b5de7926034 100644 --- a/arch/arm/include/kinetis/kinetis_dma.h +++ b/arch/arm/include/kinetis/kinetis_dma.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/include/kinetis/kinetis_dma.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Jan Okle + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/kinetis/kinetis_dmamux.h b/arch/arm/include/kinetis/kinetis_dmamux.h index 113064bfcc9..8d27348b754 100644 --- a/arch/arm/include/kinetis/kinetis_dmamux.h +++ b/arch/arm/include/kinetis/kinetis_dmamux.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/include/kinetis/kinetis_dmamux.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Jan Okle + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/lpc17xx_40xx/chip.h b/arch/arm/include/lpc17xx_40xx/chip.h index bece30c9f7e..acd03046093 100644 --- a/arch/arm/include/lpc17xx_40xx/chip.h +++ b/arch/arm/include/lpc17xx_40xx/chip.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/include/lpc17xx_40xx/chip.h * - * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * with LPC178x support from Rommel Marcelo + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h b/arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h index 4c55268cf26..8fb5255c6f2 100644 --- a/arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h +++ b/arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Authors: Rommel Marcelo - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/lpc2378/irq.h b/arch/arm/include/lpc2378/irq.h index 05b75ada61b..4ea50a32e60 100644 --- a/arch/arm/include/lpc2378/irq.h +++ b/arch/arm/include/lpc2378/irq.h @@ -1,41 +1,20 @@ /**************************************************************************** * arch/arm/include/lpc2378/irq.h * - * Copyright (C) 2010 Rommel Marcelo. All rights reserved. - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Rommel Marcelo + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * This file is part of the NuttX RTOS and based on the lpc2148 port: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/stm32/stm32f37xxx_irq.h b/arch/arm/include/stm32/stm32f37xxx_irq.h index 6c00b24ec9b..f3f2f599c70 100644 --- a/arch/arm/include/stm32/stm32f37xxx_irq.h +++ b/arch/arm/include/stm32/stm32f37xxx_irq.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/include/stm32/stm32f37xxx_irq.h * - * Copyright (C) 2012, 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Modified for STM32F373 by Marten Svanfeldt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h index ff5d0c9f33f..3e349325938 100644 --- a/arch/arm/include/stm32f0l0g0/chip.h +++ b/arch/arm/include/stm32f0l0g0/chip.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/include/stm32f0l0g0/chip.h * - * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * Daniel Pereira Volpato + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h index 1a496a9292b..6965e530e22 100644 --- a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h +++ b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/include/stm32f0l0g0/stm32g0_irq.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Mateusz Szafoni - * Daniel Pereira Volpato + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index 3c16e21ebe9..3d0d0be4915 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/include/stm32h7/chip.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Simon Laube + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h index 43360ee19fd..ff161031a4c 100644 --- a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/include/stm32l4/stm32l4x3xx_irq.h * - * Copyright (C) 2015 Sebastien Lorquet. All rights reserved. - * Authors: Sebastien Lorquet - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/tiva/chip.h b/arch/arm/include/tiva/chip.h index 0899ac34c91..84037f9c43a 100644 --- a/arch/arm/include/tiva/chip.h +++ b/arch/arm/include/tiva/chip.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/include/tiva/chip.h * - * Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Jose Pablo Carballo - * Jim Ewing + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/Makefile b/arch/arm/src/Makefile index aaef0525d76..77ca97af4ba 100644 --- a/arch/arm/src/Makefile +++ b/arch/arm/src/Makefile @@ -56,7 +56,7 @@ endif # Additional rules for system call wrapper ifeq ($(CONFIG_SCHED_INSTRUMENTATION_SYSCALL),y) - EXTRALINKCMDS += @$(TOPDIR)/syscall/syscall_wraps.ldcmd + EXTRALINKCMDS += -Wl,@$(TOPDIR)/syscall/syscall_wraps.ldcmd endif # The "head" object @@ -93,8 +93,8 @@ LDFLAGS += $(ARCHSCRIPT) $(EXTRALINKCMDS) # Override in Make.defs if linker is not 'ld' -LDSTARTGROUP ?= --start-group -LDENDGROUP ?= --end-group +LDSTARTGROUP ?= -Wl,--start-group +LDENDGROUP ?= -Wl,--end-group BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,) @@ -153,7 +153,7 @@ board$(DELIM)libboard$(LIBEXT): nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT) $(Q) echo "LD: nuttx" - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + $(Q) $(LD) -Wl,--entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(filter-out board/libboard$(LIBEXT), $^) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) diff --git a/arch/arm/src/a1x/Make.defs b/arch/arm/src/a1x/Make.defs index 8cb5a8fb269..a547ebecdc2 100644 --- a/arch/arm/src/a1x/Make.defs +++ b/arch/arm/src/a1x/Make.defs @@ -74,6 +74,7 @@ endif ifeq ($(CONFIG_BUILD_KERNEL),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c +CMN_CSRCS += arm_pthread_exit.c endif ifeq ($(CONFIG_ARCH_ADDRENV),y) diff --git a/arch/arm/src/a1x/a1x_irq.c b/arch/arm/src/a1x/a1x_irq.c index f66b917d5c7..dc34aca9178 100644 --- a/arch/arm/src/a1x/a1x_irq.c +++ b/arch/arm/src/a1x/a1x_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c index 07cf465eabf..022e1a1d610 100644 --- a/arch/arm/src/a1x/a1x_serial.c +++ b/arch/arm/src/a1x/a1x_serial.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_SERIAL_TERMIOS diff --git a/arch/arm/src/am335x/Make.defs b/arch/arm/src/am335x/Make.defs index b8a7ed51bd8..df6f7fec44c 100644 --- a/arch/arm/src/am335x/Make.defs +++ b/arch/arm/src/am335x/Make.defs @@ -70,6 +70,7 @@ endif ifeq ($(CONFIG_BUILD_KERNEL),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c +CMN_CSRCS += arm_pthread_exit.c endif ifeq ($(CONFIG_ARCH_ADDRENV),y) diff --git a/arch/arm/src/am335x/am335x_can.c b/arch/arm/src/am335x/am335x_can.c index f56cc5132ca..859b12e3f65 100644 --- a/arch/arm/src/am335x/am335x_can.c +++ b/arch/arm/src/am335x/am335x_can.c @@ -24,6 +24,8 @@ #include +#include + #include #include #include diff --git a/arch/arm/src/am335x/am335x_i2c.c b/arch/arm/src/am335x/am335x_i2c.c index b6cd5c4784d..43c979a6dd0 100644 --- a/arch/arm/src/am335x/am335x_i2c.c +++ b/arch/arm/src/am335x/am335x_i2c.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/am335x/am335x_lcdc.c b/arch/arm/src/am335x/am335x_lcdc.c index 7a96263163c..14892521380 100644 --- a/arch/arm/src/am335x/am335x_lcdc.c +++ b/arch/arm/src/am335x/am335x_lcdc.c @@ -48,6 +48,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/am335x/am335x_serial.c b/arch/arm/src/am335x/am335x_serial.c index 4e1b35e3043..83f3039b758 100644 --- a/arch/arm/src/am335x/am335x_serial.c +++ b/arch/arm/src/am335x/am335x_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_SERIAL_TERMIOS diff --git a/arch/arm/src/arm/Toolchain.defs b/arch/arm/src/arm/Toolchain.defs index 0997ffeae0c..b2a53322905 100644 --- a/arch/arm/src/arm/Toolchain.defs +++ b/arch/arm/src/arm/Toolchain.defs @@ -63,6 +63,8 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif # NuttX buildroot under Linux or Cygwin @@ -73,14 +75,12 @@ ifeq ($(CONFIG_ARM_OABI_TOOLCHAIN),y) else CROSSDEV ?= arm-nuttx-eabi- endif - MAXOPTIMIZATION ?= -Os endif # Generic GNU EABI toolchain ifeq ($(CONFIG_ARM_TOOLCHAIN),GNU_EABI) CROSSDEV ?= arm-none-eabi- - MAXOPTIMIZATION ?= -Os endif # Default toolchain @@ -88,7 +88,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/arm/src/arm/arm_allocpage.c b/arch/arm/src/arm/arm_allocpage.c index ad503bfdaa0..27de03bd29e 100644 --- a/arch/arm/src/arm/arm_allocpage.c +++ b/arch/arm/src/arm/arm_allocpage.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/arm/arm_blocktask.c b/arch/arm/src/arm/arm_blocktask.c index f2fd961ffe9..dd8378a7582 100644 --- a/arch/arm/src/arm/arm_blocktask.c +++ b/arch/arm/src/arm/arm_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/arm/arm_checkmapping.c b/arch/arm/src/arm/arm_checkmapping.c index cff6666b1d4..80cb2b3dc4d 100644 --- a/arch/arm/src/arm/arm_checkmapping.c +++ b/arch/arm/src/arm/arm_checkmapping.c @@ -27,6 +27,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/arm/arm_dataabort.c b/arch/arm/src/arm/arm_dataabort.c index 4af3ee79e77..5ab1d0376b1 100644 --- a/arch/arm/src/arm/arm_dataabort.c +++ b/arch/arm/src/arm/arm_dataabort.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/arm/arm_head.S b/arch/arm/src/arm/arm_head.S index 0cfa6d507bf..6c334677004 100644 --- a/arch/arm/src/arm/arm_head.S +++ b/arch/arm/src/arm/arm_head.S @@ -603,22 +603,6 @@ __start: bl arm_boot -#ifdef CONFIG_STACK_COLORATION - /* Write a known value to the IDLE thread stack to support stack - * monitoring logic - */ - - adr r3, .Lstkinit - ldmia r3, {r0, r1, r2} /* R0 = start of IDLE stack; R1 = Size of tack; R2 = coloration */ - -2: /* Top of the loop */ - sub r1, r1, #1 /* R1 = Number of words remaining */ - cmp r1, #0 /* Check (nwords == 0) */ - str r2, [r0], #4 /* Save stack color word, increment stack address */ - bne 2b /* Bottom of the loop */ - -#endif - /* Finally branch to the OS entry point */ mov lr, #0 /* LR = return address (none) */ @@ -674,15 +658,6 @@ __start: .long _sdata /* Where .data needs to reside in SDRAM */ .long _edata #endif - -#ifdef CONFIG_STACK_COLORATION - .type .Lstkinit, %object -.Lstkinit: - .long _ebss /* Beginning of the IDLE stack, then words of IDLE stack */ - .long (CONFIG_IDLETHREAD_STACKSIZE >> 2) - .long STACK_COLOR /* Stack coloration word */ - .size .Lstkinit, . -.Lstkinit -#endif .size .Lvstart, .-.Lvstart /*************************************************************************** diff --git a/arch/arm/src/arm/arm_nommuhead.S b/arch/arm/src/arm/arm_nommuhead.S index 27c53b9ffe4..6ddc3c69553 100644 --- a/arch/arm/src/arm/arm_nommuhead.S +++ b/arch/arm/src/arm/arm_nommuhead.S @@ -112,22 +112,6 @@ __start: bl board_autoled_initialize #endif -#ifdef CONFIG_STACK_COLORATION - /* Write a known value to the IDLE thread stack to support stack - * monitoring logic - */ - - adr r3, .Lstkinit - ldmia r3, {r0, r1, r2} /* R0 = start of IDLE stack; R1 = Size of tack; R2 = coloration */ - -2: /* Top of the loop */ - sub r1, r1, #1 /* R1 = Number of words remaining */ - cmp r1, #0 /* Check (nwords == 0) */ - str r2, [r0], #4 /* Save stack color word, increment stack address */ - bne 2b /* Bottom of the loop */ - -#endif - /* Finally branch to the OS entry point */ mov lr, #0 /* LR = return address (none) */ @@ -154,14 +138,6 @@ __start: .long _edata #endif -#ifdef CONFIG_STACK_COLORATION - .type .Lstkinit, %object -.Lstkinit: - .long _ebss /* Beginning of the IDLE stack, then words of IDLE stack */ - .long (CONFIG_IDLETHREAD_STACKSIZE >> 2) - .long STACK_COLOR /* Stack coloration word */ - .size .Lstkinit, . -.Lstkinit -#endif .size __start, .-__start /* This global variable is unsigned long g_idle_topstack and is diff --git a/arch/arm/src/arm/arm_prefetchabort.c b/arch/arm/src/arm/arm_prefetchabort.c index 008c872912d..314ac0cbd08 100644 --- a/arch/arm/src/arm/arm_prefetchabort.c +++ b/arch/arm/src/arm/arm_prefetchabort.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/arm/arm_reprioritizertr.c b/arch/arm/src/arm/arm_reprioritizertr.c index 3cb9bd73ee8..50970cce5a9 100644 --- a/arch/arm/src/arm/arm_reprioritizertr.c +++ b/arch/arm/src/arm/arm_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/arm/arm_sigdeliver.c b/arch/arm/src/arm/arm_sigdeliver.c index af9d47e25c3..983d1de6246 100644 --- a/arch/arm/src/arm/arm_sigdeliver.c +++ b/arch/arm/src/arm/arm_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/arm/arm_syscall.c b/arch/arm/src/arm/arm_syscall.c index 57f2aa89a58..9f4b0566f24 100644 --- a/arch/arm/src/arm/arm_syscall.c +++ b/arch/arm/src/arm/arm_syscall.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/arm/arm_unblocktask.c b/arch/arm/src/arm/arm_unblocktask.c index f5720867e8b..850018d1cf5 100644 --- a/arch/arm/src/arm/arm_unblocktask.c +++ b/arch/arm/src/arm/arm_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/arm/arm_va2pte.c b/arch/arm/src/arm/arm_va2pte.c index be7867103a3..4e8ae09745d 100644 --- a/arch/arm/src/arm/arm_va2pte.c +++ b/arch/arm/src/arm/arm_va2pte.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv6-m/Toolchain.defs b/arch/arm/src/armv6-m/Toolchain.defs index 3684668f2ca..10a169a32c2 100644 --- a/arch/arm/src/armv6-m/Toolchain.defs +++ b/arch/arm/src/armv6-m/Toolchain.defs @@ -57,6 +57,8 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif # NuttX buildroot under Linux or Cygwin @@ -73,17 +75,12 @@ ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),GNU_EABI) ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft endif -# Individual tools may limit the optimizatin level but, by default, the -# optimization level will be set to -Os - -MAXOPTIMIZATION ?= -Os - # Default toolchain CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/arm/src/armv6-m/arm_blocktask.c b/arch/arm/src/armv6-m/arm_blocktask.c index 90562fa6221..fb8999badcb 100644 --- a/arch/arm/src/armv6-m/arm_blocktask.c +++ b/arch/arm/src/armv6-m/arm_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv6-m/arm_exception.S b/arch/arm/src/armv6-m/arm_exception.S index a2200be6df0..b71a912bbb6 100644 --- a/arch/arm/src/armv6-m/arm_exception.S +++ b/arch/arm/src/armv6-m/arm_exception.S @@ -44,6 +44,11 @@ #include #include + +#ifdef CONFIG_SMP +# include "chip.h" +#endif + #include "exc_return.h" /**************************************************************************** @@ -53,6 +58,26 @@ .globl exception_common .file "arm_exception.S" +/**************************************************************************** + * Macro Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: setintstack + * + * Description: + * Set the current stack pointer to the "top" the interrupt stack. Single CPU + * case. Must be provided by MCU-specific logic in the SMP case. + * + ****************************************************************************/ + +#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 3 + .macro setintstack, tmp1, tmp2 + ldr \tmp1, =g_intstacktop + mov sp, \tmp1 + .endm +#endif + /**************************************************************************** * .text ****************************************************************************/ @@ -142,8 +167,7 @@ exception_common: */ #if CONFIG_ARCH_INTERRUPTSTACK > 3 - ldr r7, =g_intstacktop /* R7=Top of the interrupt stack */ - mov sp, r7 /* Set the new stack point */ + setintstack r7, r6 /* SP = IRQ stack top */ push {r1} /* Save the MSP on the interrupt stack */ bl arm_doirq /* R0=IRQ, R1=register save area on stack */ pop {r1} /* Recover R1=main stack pointer */ diff --git a/arch/arm/src/armv6-m/arm_ramvec_initialize.c b/arch/arm/src/armv6-m/arm_ramvec_initialize.c index 7e037155284..09be4b6b147 100644 --- a/arch/arm/src/armv6-m/arm_ramvec_initialize.c +++ b/arch/arm/src/armv6-m/arm_ramvec_initialize.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/armv6-m/arm_reprioritizertr.c b/arch/arm/src/armv6-m/arm_reprioritizertr.c index 7e1f06f59be..e22faeedae6 100644 --- a/arch/arm/src/armv6-m/arm_reprioritizertr.c +++ b/arch/arm/src/armv6-m/arm_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/armv6-m/arm_schedulesigaction.c b/arch/arm/src/armv6-m/arm_schedulesigaction.c index b7dcf8a60c7..31376bf8206 100644 --- a/arch/arm/src/armv6-m/arm_schedulesigaction.c +++ b/arch/arm/src/armv6-m/arm_schedulesigaction.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv6-m/arm_sigdeliver.c b/arch/arm/src/armv6-m/arm_sigdeliver.c index 28b73eb0bba..53178409342 100644 --- a/arch/arm/src/armv6-m/arm_sigdeliver.c +++ b/arch/arm/src/armv6-m/arm_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv6-m/arm_svcall.c b/arch/arm/src/armv6-m/arm_svcall.c index d7b5430c9d8..6517b4c0f12 100644 --- a/arch/arm/src/armv6-m/arm_svcall.c +++ b/arch/arm/src/armv6-m/arm_svcall.c @@ -298,34 +298,65 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg) break; #endif +#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD) + /* R0=SYS_pthread_start: This a user pthread start * - * void up_pthread_start(pthread_startroutine_t entrypt, - * pthread_addr_t arg) noreturn_function; + * void up_pthread_start(pthread_trampoline_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) * * At this point, the following values are saved in context: * * R0 = SYS_pthread_start - * R1 = entrypt - * R2 = arg + * R1 = startup + * R2 = entrypt + * R3 = arg */ -#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_PTHREAD) case SYS_pthread_start: { /* Set up to return to the user-space pthread start-up function in * unprivileged mode. */ - regs[REG_PC] = (uint32_t)USERSPACE->pthread_startup; + regs[REG_PC] = (uint32_t)regs[REG_R1] & ~1; /* startup */ regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; - /* Change the parameter ordering to match the expectation of struct - * userpace_s pthread_startup: + /* Change the parameter ordering to match the expectation of the + * user space pthread_startup: */ - regs[REG_R0] = regs[REG_R1]; /* pthread entry */ - regs[REG_R1] = regs[REG_R2]; /* arg */ + regs[REG_R0] = regs[REG_R2]; /* pthread entry */ + regs[REG_R1] = regs[REG_R3]; /* arg */ + } + break; + + /* R0=SYS_pthread_exit: This pthread_exit call in user-space + * + * void up_pthread_exit(pthread_exitroutine_t exit, + * FAR void *exit_value) + * + * At this point, the following values are saved in context: + * + * R0 = SYS_pthread_exit + * R1 = pthread_exit trampoline routine + * R2 = exit_value + */ + + case SYS_pthread_exit: + { + /* Set up to return to the user-space pthread start-up function in + * unprivileged mode. + */ + + regs[REG_PC] = (uint32_t)regs[REG_R1] & ~1; /* startup */ + regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; + + /* Change the parameter ordering to match the expectation of the + * user space pthread_startup: + */ + + regs[REG_R0] = regs[REG_R2]; /* exit_value */ } break; #endif diff --git a/arch/arm/src/armv6-m/arm_unblocktask.c b/arch/arm/src/armv6-m/arm_unblocktask.c index 00db4a34530..2d50cfe14a4 100644 --- a/arch/arm/src/armv6-m/arm_unblocktask.c +++ b/arch/arm/src/armv6-m/arm_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/armv6-m/svcall.h b/arch/arm/src/armv6-m/svcall.h index 7f2f45f5592..0b0f8d7cd82 100644 --- a/arch/arm/src/armv6-m/svcall.h +++ b/arch/arm/src/armv6-m/svcall.h @@ -45,9 +45,9 @@ #ifdef CONFIG_LIB_SYSCALL # ifdef CONFIG_BUILD_PROTECTED # ifndef CONFIG_SYS_RESERVED -# error "CONFIG_SYS_RESERVED must be defined to have the value 8" -# elif CONFIG_SYS_RESERVED != 8 -# error "CONFIG_SYS_RESERVED must have the value 8" +# error "CONFIG_SYS_RESERVED must be defined to have the value 9" +# elif CONFIG_SYS_RESERVED != 9 +# error "CONFIG_SYS_RESERVED must have the value 9" # endif # else # ifndef CONFIG_SYS_RESERVED @@ -89,6 +89,7 @@ #define SYS_syscall_return (3) +#ifndef CONFIG_BUILD_FLAT #ifdef CONFIG_BUILD_PROTECTED /* SYS call 4: * @@ -98,15 +99,6 @@ #define SYS_task_start (4) -/* SYS call 5: - * - * void up_pthread_start(pthread_startroutine_t entrypt, - * pthread_addr_t arg) - * noreturn_function - */ - -#define SYS_pthread_start (5) - /* SYS call 6: * * void signal_handler(_sa_sigaction_t sighand, int signo, @@ -124,6 +116,17 @@ #define SYS_signal_handler_return (7) #endif /* CONFIG_BUILD_PROTECTED */ + +/* SYS call 5: + * + * void up_pthread_start(pthread_startroutine_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (5) + +#endif /* !CONFIG_BUILD_FLAT */ #endif /* CONFIG_LIB_SYSCALL */ /**************************************************************************** diff --git a/arch/arm/src/armv7-a/Toolchain.defs b/arch/arm/src/armv7-a/Toolchain.defs index 21aeca56eff..c9446517abc 100644 --- a/arch/arm/src/armv7-a/Toolchain.defs +++ b/arch/arm/src/armv7-a/Toolchain.defs @@ -75,6 +75,8 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif ifeq ($(CONFIG_ENDIAN_BIG),y) @@ -91,14 +93,12 @@ ifeq ($(CONFIG_ARMV7A_OABI_TOOLCHAIN),y) else CROSSDEV ?= $(TARGET_ARCH)-nuttx-eabi- endif - MAXOPTIMIZATION ?= -Os endif # Generic GNU EABI toolchain ifeq ($(CONFIG_ARMV7A_TOOLCHAIN),GNU_EABI) CROSSDEV ?= $(TARGET_ARCH)-none-eabi- - MAXOPTIMIZATION ?= -Os endif # Default toolchain @@ -106,7 +106,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/arm/src/armv7-a/arm_addrenv_shm.c b/arch/arm/src/armv7-a/arm_addrenv_shm.c index 8a711c8c512..5548b439b56 100644 --- a/arch/arm/src/armv7-a/arm_addrenv_shm.c +++ b/arch/arm/src/armv7-a/arm_addrenv_shm.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_addrenv_utils.c b/arch/arm/src/armv7-a/arm_addrenv_utils.c index bd81199eeab..4a22e2a4586 100644 --- a/arch/arm/src/armv7-a/arm_addrenv_utils.c +++ b/arch/arm/src/armv7-a/arm_addrenv_utils.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_allocpage.c b/arch/arm/src/armv7-a/arm_allocpage.c index ae2a4fbdb35..46891ec00b7 100644 --- a/arch/arm/src/armv7-a/arm_allocpage.c +++ b/arch/arm/src/armv7-a/arm_allocpage.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_blocktask.c b/arch/arm/src/armv7-a/arm_blocktask.c index 26a5aadee80..0acadccf452 100644 --- a/arch/arm/src/armv7-a/arm_blocktask.c +++ b/arch/arm/src/armv7-a/arm_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_checkmapping.c b/arch/arm/src/armv7-a/arm_checkmapping.c index f29e40e1e0e..b1a8985f46d 100644 --- a/arch/arm/src/armv7-a/arm_checkmapping.c +++ b/arch/arm/src/armv7-a/arm_checkmapping.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_cpuidlestack.c b/arch/arm/src/armv7-a/arm_cpuidlestack.c index 2e9a1181b98..bc23ebaa071 100644 --- a/arch/arm/src/armv7-a/arm_cpuidlestack.c +++ b/arch/arm/src/armv7-a/arm_cpuidlestack.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 88bac22e0fb..fbb6c38dd16 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index 7e86312f98e..1bcac9d50f1 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -25,6 +25,8 @@ #include #include +#include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c index 4603974c7ce..584b5286a57 100644 --- a/arch/arm/src/armv7-a/arm_dataabort.c +++ b/arch/arm/src/armv7-a/arm_dataabort.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_doirq.c b/arch/arm/src/armv7-a/arm_doirq.c index 33d3134c77b..21dc09e4768 100644 --- a/arch/arm/src/armv7-a/arm_doirq.c +++ b/arch/arm/src/armv7-a/arm_doirq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index 30f910b5cb1..25362634e65 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -632,21 +632,6 @@ __start: bl arm_boot -#ifdef CONFIG_STACK_COLORATION - /* Write a known value to the IDLE thread stack to support stack - * monitoring logic - */ - - adr r3, .Lstkinit - ldmia r3, {r0, r1, r2} /* R0 = start of IDLE stack; R1 = Size of tack; R2 = coloration */ - -1: /* Top of the loop */ - sub r1, r1, #1 /* R1 = Number of words remaining */ - cmp r1, #0 /* Check (nwords == 0) */ - str r2, [r0], #4 /* Save stack color word, increment stack address */ - bne 1b /* Bottom of the loop */ -#endif - /* Finally branch to the OS entry point */ mov lr, #0 /* LR = return address (none) */ @@ -753,21 +738,6 @@ arm_data_initialize: .size .Ldatainit, . -.Ldatainit #endif -#ifdef CONFIG_STACK_COLORATION - .type .Lstkinit, %object -.Lstkinit: -#ifdef CONFIG_BOOT_SDRAM_DATA - .long IDLE_STACK_VBASE /* Beginning of the IDLE stack, then words of IDLE stack */ -#elif defined(CONFIG_SMP) - .long _enoinit -#else - .long _ebss /* Beginning of the IDLE stack, then words of IDLE stack */ -#endif - .long (CONFIG_IDLETHREAD_STACKSIZE >> 2) - .long STACK_COLOR /* Stack coloration word */ - .size .Lstkinit, . -.Lstkinit -#endif - /*************************************************************************** * Data section variables ***************************************************************************/ diff --git a/arch/arm/src/armv7-a/arm_pgalloc.c b/arch/arm/src/armv7-a/arm_pgalloc.c index 988a735c01d..13f33b7c3ec 100644 --- a/arch/arm/src/armv7-a/arm_pgalloc.c +++ b/arch/arm/src/armv7-a/arm_pgalloc.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S index 2d744032528..09089285cdc 100644 --- a/arch/arm/src/armv7-a/arm_pghead.S +++ b/arch/arm/src/armv7-a/arm_pghead.S @@ -668,21 +668,6 @@ __start: bl arm_boot -#ifdef CONFIG_STACK_COLORATION - /* Write a known value to the IDLE thread stack to support stack - * monitoring logic - */ - - adr r3, .Lstkinit - ldmia r3, {r0, r1, r2} /* R0 = start of IDLE stack; R1 = Size of tack; R2 = coloration */ - -1: /* Top of the loop */ - sub r1, r1, #1 /* R1 = Number of words remaining */ - cmp r1, #0 /* Check (nwords == 0) */ - str r2, [r0], #4 /* Save stack color word, increment stack address */ - bne 1b /* Bottom of the loop */ -#endif - /* Finally branch to the OS entry point */ mov lr, #0 /* LR = return address (none) */ @@ -792,19 +777,6 @@ arm_data_initialize: .long _edata .size .Ldatainit, . -.Ldatainit -#ifdef CONFIG_STACK_COLORATION - .type .Lstkinit, %object -.Lstkinit: -#ifdef CONFIG_BOOT_SDRAM_DATA - .long IDLE_STACK_VBASE /* Beginning of the IDLE stack, then words of IDLE stack */ -#else - .long _ebss /* Beginning of the IDLE stack, then words of IDLE stack */ -#endif - .long (CONFIG_IDLETHREAD_STACKSIZE >> 2) - .long STACK_COLOR /* Stack coloration word */ - .size .Lstkinit, . -.Lstkinit -#endif - /*************************************************************************** * Data section variables ***************************************************************************/ diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c index 85bac7c25ac..adb9c88ece1 100644 --- a/arch/arm/src/armv7-a/arm_prefetchabort.c +++ b/arch/arm/src/armv7-a/arm_prefetchabort.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c index a96052cbd95..1cd6ff38d0a 100644 --- a/arch/arm/src/armv7-a/arm_reprioritizertr.c +++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c index cfe474df8d8..9aa8c78026d 100644 --- a/arch/arm/src/armv7-a/arm_schedulesigaction.c +++ b/arch/arm/src/armv7-a/arm_schedulesigaction.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c index 20baf6a4dfc..374170b62ce 100644 --- a/arch/arm/src/armv7-a/arm_sigdeliver.c +++ b/arch/arm/src/armv7-a/arm_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c index ea6b31ee18d..999d1b1df20 100644 --- a/arch/arm/src/armv7-a/arm_syscall.c +++ b/arch/arm/src/armv7-a/arm_syscall.c @@ -278,31 +278,48 @@ uint32_t *arm_syscall(uint32_t *regs) break; #endif +#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD) + /* R0=SYS_pthread_start: This a user pthread start * - * void up_pthread_start(pthread_startroutine_t entrypt, - * pthread_addr_t arg) noreturn_function; + * void up_pthread_start(pthread_trampoline_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) * * At this point, the following values are saved in context: * * R0 = SYS_pthread_start - * R1 = entrypt - * R2 = arg + * R1 = startup + * R2 = entrypt + * R3 = arg */ -#if defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_DISABLE_PTHREAD) case SYS_pthread_start: { - /* Set up to return to the user-space pthread start-up function in - * unprivileged mode. We need: - * - * R0 = arg - * PC = entrypt - * CSPR = user mode - */ + regs[REG_PC] = regs[REG_R0]; + regs[REG_R0] = regs[REG_R1]; + regs[REG_R1] = regs[REG_R2]; - regs[REG_PC] = regs[REG_R1]; - regs[REG_R0] = regs[REG_R2]; + cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK; + regs[REG_CPSR] = cpsr | PSR_MODE_USR; + } + break; + + /* R0=SYS_pthread_exit: This pthread_exit call in user-space + * + * void up_pthread_exit(pthread_exitroutine_t exit, + * FAR void *exit_value) + * + * At this point, the following values are saved in context: + * + * R0 = SYS_pthread_exit + * R1 = pthread_exit trampoline routine + * R2 = exit_value + */ + + case SYS_pthread_exit: + { + regs[REG_PC] = regs[REG_R0]; + regs[REG_R0] = regs[REG_R1]; cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK; regs[REG_CPSR] = cpsr | PSR_MODE_USR; diff --git a/arch/arm/src/armv7-a/arm_unblocktask.c b/arch/arm/src/armv7-a/arm_unblocktask.c index 204c9aea76f..71e04600e76 100644 --- a/arch/arm/src/armv7-a/arm_unblocktask.c +++ b/arch/arm/src/armv7-a/arm_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/armv7-a/arm_va2pte.c b/arch/arm/src/armv7-a/arm_va2pte.c index 301e4208656..df692ff9716 100644 --- a/arch/arm/src/armv7-a/arm_va2pte.c +++ b/arch/arm/src/armv7-a/arm_va2pte.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-a/svcall.h b/arch/arm/src/armv7-a/svcall.h index f0bb70013b2..d22fde1c87b 100644 --- a/arch/arm/src/armv7-a/svcall.h +++ b/arch/arm/src/armv7-a/svcall.h @@ -44,8 +44,8 @@ #ifdef CONFIG_BUILD_KERNEL # ifndef CONFIG_SYS_RESERVED -# error "CONFIG_SYS_RESERVED must be defined to have the value 6" -# elif CONFIG_SYS_RESERVED != 6 +# error "CONFIG_SYS_RESERVED must be defined to have the value 7" +# elif CONFIG_SYS_RESERVED != 7 # error "CONFIG_SYS_RESERVED must have the value 6" # endif #else @@ -65,6 +65,7 @@ #define SYS_syscall_return (0) +#ifndef CONFIG_BUILD_FLAT #ifdef CONFIG_BUILD_KERNEL /* SYS call 1: * @@ -81,14 +82,6 @@ #define SYS_task_start (2) -/* SYS call 3: - * - * void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) - * noreturn_function - */ - -#define SYS_pthread_start (3) - /* SYS call 4: * * void signal_handler(_sa_sigaction_t sighand, @@ -105,6 +98,24 @@ #define SYS_signal_handler_return (5) +#endif /* !CONFIG_BUILD_FLAT */ + +/* SYS call 3: + * + * void up_pthread_start(pthread_startroutine_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (3) + +/* SYS call 8: + * + * void up_pthread_exit(pthread_exitroutine_t exit, FAR void *exit_value) + */ + +#define SYS_pthread_exit (6) + #endif /* CONFIG_BUILD_KERNEL */ /**************************************************************************** diff --git a/arch/arm/src/armv7-m/Toolchain.defs b/arch/arm/src/armv7-m/Toolchain.defs index 3745142872f..68ff2b05c40 100644 --- a/arch/arm/src/armv7-m/Toolchain.defs +++ b/arch/arm/src/armv7-m/Toolchain.defs @@ -71,6 +71,8 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif # Parametrization for ARCHCPUFLAGS @@ -117,14 +119,12 @@ else CROSSDEV ?= arm-nuttx-eabi- ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT) endif - MAXOPTIMIZATION ?= -Os endif # Generic GNU EABI toolchain ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),GNU_EABI) CROSSDEV ?= arm-none-eabi- - MAXOPTIMIZATION ?= -Os ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT) endif @@ -132,7 +132,6 @@ endif ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CLANG) CROSSDEV ?= arm-none-eabi- - MAXOPTIMIZATION ?= -Os ARCHCPUFLAGS = -target arm-none-eabi $(TOOLCHAIN_MCPU) $(TOOLCHAIN_MFLOAT) CC = clang CXX = clang++ @@ -143,7 +142,7 @@ else CPP = $(CROSSDEV)gcc -E -P -x c endif -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/arm/src/armv7-m/arm_blocktask.c b/arch/arm/src/armv7-m/arm_blocktask.c index 3f6b8bac3d6..a55b9b9ecfb 100644 --- a/arch/arm/src/armv7-m/arm_blocktask.c +++ b/arch/arm/src/armv7-m/arm_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-m/arm_ramvec_initialize.c b/arch/arm/src/armv7-m/arm_ramvec_initialize.c index 3a78adce80a..1cf59620568 100644 --- a/arch/arm/src/armv7-m/arm_ramvec_initialize.c +++ b/arch/arm/src/armv7-m/arm_ramvec_initialize.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/armv7-m/arm_reprioritizertr.c b/arch/arm/src/armv7-m/arm_reprioritizertr.c index 7d4c8ea0369..a3373553f9e 100644 --- a/arch/arm/src/armv7-m/arm_reprioritizertr.c +++ b/arch/arm/src/armv7-m/arm_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/armv7-m/arm_schedulesigaction.c b/arch/arm/src/armv7-m/arm_schedulesigaction.c index 85ed00b6022..25e81742445 100644 --- a/arch/arm/src/armv7-m/arm_schedulesigaction.c +++ b/arch/arm/src/armv7-m/arm_schedulesigaction.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-m/arm_sigdeliver.c b/arch/arm/src/armv7-m/arm_sigdeliver.c index 50dbec3abaf..ad1574b76b3 100644 --- a/arch/arm/src/armv7-m/arm_sigdeliver.c +++ b/arch/arm/src/armv7-m/arm_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-m/arm_svcall.c b/arch/arm/src/armv7-m/arm_svcall.c index 2112ea794a5..ca38d1b60ab 100644 --- a/arch/arm/src/armv7-m/arm_svcall.c +++ b/arch/arm/src/armv7-m/arm_svcall.c @@ -312,34 +312,65 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg) break; #endif +#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD) + /* R0=SYS_pthread_start: This a user pthread start * - * void up_pthread_start(pthread_startroutine_t entrypt, - * pthread_addr_t arg) noreturn_function; + * void up_pthread_start(pthread_trampoline_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) * * At this point, the following values are saved in context: * * R0 = SYS_pthread_start - * R1 = entrypt - * R2 = arg + * R1 = startup + * R2 = entrypt + * R3 = arg */ -#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_PTHREAD) case SYS_pthread_start: { /* Set up to return to the user-space pthread start-up function in * unprivileged mode. */ - regs[REG_PC] = (uint32_t)USERSPACE->pthread_startup & ~1; + regs[REG_PC] = (uint32_t)regs[REG_R1] & ~1; /* startup */ regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; - /* Change the parameter ordering to match the expectation of struct - * userpace_s pthread_startup: + /* Change the parameter ordering to match the expectation of the + * user space pthread_startup: */ - regs[REG_R0] = regs[REG_R1]; /* pthread entry */ - regs[REG_R1] = regs[REG_R2]; /* arg */ + regs[REG_R0] = regs[REG_R2]; /* pthread entry */ + regs[REG_R1] = regs[REG_R3]; /* arg */ + } + break; + + /* R0=SYS_pthread_exit: This pthread_exit call in user-space + * + * void up_pthread_exit(pthread_exitroutine_t exit, + * FAR void *exit_value) + * + * At this point, the following values are saved in context: + * + * R0 = SYS_pthread_exit + * R1 = pthread_exit trampoline routine + * R2 = exit_value + */ + + case SYS_pthread_exit: + { + /* Set up to return to the user-space pthread start-up function in + * unprivileged mode. + */ + + regs[REG_PC] = (uint32_t)regs[REG_R1] & ~1; /* startup */ + regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; + + /* Change the parameter ordering to match the expectation of the + * user space pthread_startup: + */ + + regs[REG_R0] = regs[REG_R2]; /* exit_value */ } break; #endif diff --git a/arch/arm/src/armv7-m/arm_unblocktask.c b/arch/arm/src/armv7-m/arm_unblocktask.c index 5fd0e9575a2..4a96c33187e 100644 --- a/arch/arm/src/armv7-m/arm_unblocktask.c +++ b/arch/arm/src/armv7-m/arm_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/armv7-m/svcall.h b/arch/arm/src/armv7-m/svcall.h index 9f3b9776a4f..1fd56ea4c4c 100644 --- a/arch/arm/src/armv7-m/svcall.h +++ b/arch/arm/src/armv7-m/svcall.h @@ -45,9 +45,9 @@ #ifdef CONFIG_LIB_SYSCALL # ifdef CONFIG_BUILD_PROTECTED # ifndef CONFIG_SYS_RESERVED -# error "CONFIG_SYS_RESERVED must be defined to have the value 8" -# elif CONFIG_SYS_RESERVED != 8 -# error "CONFIG_SYS_RESERVED must have the value 8" +# error "CONFIG_SYS_RESERVED must be defined to have the value 9" +# elif CONFIG_SYS_RESERVED != 9 +# error "CONFIG_SYS_RESERVED must have the value 9" # endif # else # ifndef CONFIG_SYS_RESERVED @@ -81,6 +81,7 @@ #define SYS_switch_context (2) +#ifndef CONFIG_BUILD_FLAT #ifdef CONFIG_LIB_SYSCALL /* SYS call 3: * @@ -98,14 +99,6 @@ #define SYS_task_start (4) -/* SYS call 5: - * - * void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) - * noreturn_function - */ - -#define SYS_pthread_start (5) - /* SYS call 6: * * void signal_handler(_sa_sigaction_t sighand, @@ -123,6 +116,24 @@ #define SYS_signal_handler_return (7) #endif /* CONFIG_BUILD_PROTECTED */ + +/* SYS call 5: + * + * void up_pthread_start((pthread_startroutine_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (5) + +/* SYS call 8: + * + * void up_pthread_exit(pthread_exitroutine_t exit, FAR void *exit_value) + */ + +#define SYS_pthread_exit (8) + +#endif /* !CONFIG_BUILD_FLAT */ #endif /* CONFIG_LIB_SYSCALL */ /**************************************************************************** diff --git a/arch/arm/src/armv7-r/Toolchain.defs b/arch/arm/src/armv7-r/Toolchain.defs index be48f2d8b82..c9ea7995424 100644 --- a/arch/arm/src/armv7-r/Toolchain.defs +++ b/arch/arm/src/armv7-r/Toolchain.defs @@ -57,6 +57,8 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif ifeq ($(CONFIG_ENDIAN_BIG),y) @@ -73,14 +75,12 @@ ifeq ($(CONFIG_ARMV7R_OABI_TOOLCHAIN),y) else CROSSDEV ?= $(TARGET_ARCH)-nuttx-eabi- endif - MAXOPTIMIZATION ?= -Os endif # Generic GNU EABI toolchain ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),GNU_EABI) CROSSDEV ?= $(TARGET_ARCH)-none-eabi- - MAXOPTIMIZATION ?= -Os endif # Default toolchain @@ -88,7 +88,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/arm/src/armv7-r/arm_blocktask.c b/arch/arm/src/armv7-r/arm_blocktask.c index 71c8da65a52..6dafcc17bfe 100644 --- a/arch/arm/src/armv7-r/arm_blocktask.c +++ b/arch/arm/src/armv7-r/arm_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-r/arm_dataabort.c b/arch/arm/src/armv7-r/arm_dataabort.c index 51e6cbfba0e..96d2316de89 100644 --- a/arch/arm/src/armv7-r/arm_dataabort.c +++ b/arch/arm/src/armv7-r/arm_dataabort.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-r/arm_prefetchabort.c b/arch/arm/src/armv7-r/arm_prefetchabort.c index 4ae10c6520e..72c68b0de90 100644 --- a/arch/arm/src/armv7-r/arm_prefetchabort.c +++ b/arch/arm/src/armv7-r/arm_prefetchabort.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-r/arm_reprioritizertr.c b/arch/arm/src/armv7-r/arm_reprioritizertr.c index 79d6a7ef0b9..f664dcd26fa 100644 --- a/arch/arm/src/armv7-r/arm_reprioritizertr.c +++ b/arch/arm/src/armv7-r/arm_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/armv7-r/arm_sigdeliver.c b/arch/arm/src/armv7-r/arm_sigdeliver.c index e361ca3cef7..bee9a5590aa 100644 --- a/arch/arm/src/armv7-r/arm_sigdeliver.c +++ b/arch/arm/src/armv7-r/arm_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c index ff49468682d..367c41cf8e7 100644 --- a/arch/arm/src/armv7-r/arm_syscall.c +++ b/arch/arm/src/armv7-r/arm_syscall.c @@ -273,31 +273,48 @@ uint32_t *arm_syscall(uint32_t *regs) break; #endif +#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD) + /* R0=SYS_pthread_start: This a user pthread start * - * void up_pthread_start(pthread_startroutine_t entrypt, - * pthread_addr_t arg) noreturn_function; + * void up_pthread_start(pthread_trampoline_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) * * At this point, the following values are saved in context: * * R0 = SYS_pthread_start - * R1 = entrypt - * R2 = arg + * R1 = startup + * R2 = entrypt + * R3 = arg */ -#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_PTHREAD) case SYS_pthread_start: { - /* Set up to return to the user-space pthread start-up function in - * unprivileged mode. We need: - * - * R0 = arg - * PC = entrypt - * CSPR = user mode - */ + regs[REG_PC] = regs[REG_R0]; + regs[REG_R0] = regs[REG_R1]; + regs[REG_R1] = regs[REG_R2]; - regs[REG_PC] = regs[REG_R1]; - regs[REG_R0] = regs[REG_R2]; + cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK; + regs[REG_CPSR] = cpsr | PSR_MODE_USR; + } + break; + + /* R0=SYS_pthread_exit: This pthread_exit call in user-space + * + * void up_pthread_exit(pthread_exitroutine_t exit, + * FAR void *exit_value) + * + * At this point, the following values are saved in context: + * + * R0 = SYS_pthread_exit + * R1 = pthread_exit trampoline routine + * R2 = exit_value + */ + + case SYS_pthread_exit: + { + regs[REG_PC] = regs[REG_R0]; + regs[REG_R0] = regs[REG_R1]; cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK; regs[REG_CPSR] = cpsr | PSR_MODE_USR; diff --git a/arch/arm/src/armv7-r/arm_unblocktask.c b/arch/arm/src/armv7-r/arm_unblocktask.c index 69275a85e53..0d4d489bb49 100644 --- a/arch/arm/src/armv7-r/arm_unblocktask.c +++ b/arch/arm/src/armv7-r/arm_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/armv7-r/svcall.h b/arch/arm/src/armv7-r/svcall.h index ffd87371341..2470da7e5d9 100644 --- a/arch/arm/src/armv7-r/svcall.h +++ b/arch/arm/src/armv7-r/svcall.h @@ -66,6 +66,7 @@ #define SYS_syscall_return (0) +#ifndef CONFIG_BUILD_FLAT #ifdef CONFIG_BUILD_PROTECTED /* SYS call 1: * @@ -82,14 +83,6 @@ #define SYS_task_start (2) -/* SYS call 3: - * - * void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) - * noreturn_function - */ - -#define SYS_pthread_start (3) - /* SYS call 4: * * void signal_handler(_sa_sigaction_t sighand, int signo, @@ -108,6 +101,17 @@ #endif /* CONFIG_BUILD_PROTECTED */ +/* SYS call 3: + * + * void up_pthread_start(pthread_startroutine_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (3) + +#endif /* !CONFIG_BUILD_FLAT */ + /**************************************************************************** * Inline Functions ****************************************************************************/ diff --git a/arch/arm/src/armv8-m/Toolchain.defs b/arch/arm/src/armv8-m/Toolchain.defs index 0ccad3895b6..dbb3420b888 100644 --- a/arch/arm/src/armv8-m/Toolchain.defs +++ b/arch/arm/src/armv8-m/Toolchain.defs @@ -71,6 +71,8 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif # Parametrization for ARCHCPUFLAGS @@ -107,14 +109,12 @@ else CROSSDEV ?= arm-nuttx-eabi- ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT) endif - MAXOPTIMIZATION ?= -Os endif # Generic GNU EABI toolchain ifeq ($(CONFIG_ARMV8M_TOOLCHAIN),GNU_EABI) CROSSDEV ?= arm-none-eabi- - MAXOPTIMIZATION ?= -Os ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT) endif @@ -122,7 +122,6 @@ endif ifeq ($(CONFIG_ARMV8M_TOOLCHAIN),CLANG) CROSSDEV ?= arm-none-eabi- - MAXOPTIMIZATION ?= -Os ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT) endif @@ -131,7 +130,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/arm/src/armv8-m/arm_assert.c b/arch/arm/src/armv8-m/arm_assert.c index 871bc45c5d3..094f97c4f81 100644 --- a/arch/arm/src/armv8-m/arm_assert.c +++ b/arch/arm/src/armv8-m/arm_assert.c @@ -398,7 +398,7 @@ void up_assert(const char *filename, int lineno) syslog_flush(); #ifdef CONFIG_SMP -#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) +#if CONFIG_TASK_NAME_SIZE > 0 _alert("Assertion failed CPU%d at file:%s line: %d task: %s\n", up_cpu_index(), filename, lineno, rtcb->name); #else @@ -406,7 +406,7 @@ void up_assert(const char *filename, int lineno) up_cpu_index(), filename, lineno); #endif #else -#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) +#if CONFIG_TASK_NAME_SIZE > 0 _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else diff --git a/arch/arm/src/armv8-m/arm_blocktask.c b/arch/arm/src/armv8-m/arm_blocktask.c index ae2b46e036e..30a1e5af929 100644 --- a/arch/arm/src/armv8-m/arm_blocktask.c +++ b/arch/arm/src/armv8-m/arm_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv8-m/arm_ramvec_initialize.c b/arch/arm/src/armv8-m/arm_ramvec_initialize.c index b0b71e868ec..1174f8462a4 100644 --- a/arch/arm/src/armv8-m/arm_ramvec_initialize.c +++ b/arch/arm/src/armv8-m/arm_ramvec_initialize.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/armv8-m/arm_reprioritizertr.c b/arch/arm/src/armv8-m/arm_reprioritizertr.c index 7b3c0af7938..13c3f0264e7 100644 --- a/arch/arm/src/armv8-m/arm_reprioritizertr.c +++ b/arch/arm/src/armv8-m/arm_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/armv8-m/arm_schedulesigaction.c b/arch/arm/src/armv8-m/arm_schedulesigaction.c index d8352b94adc..b5cb1826ba9 100644 --- a/arch/arm/src/armv8-m/arm_schedulesigaction.c +++ b/arch/arm/src/armv8-m/arm_schedulesigaction.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv8-m/arm_sigdeliver.c b/arch/arm/src/armv8-m/arm_sigdeliver.c index cb5a2de72dd..2e578556087 100644 --- a/arch/arm/src/armv8-m/arm_sigdeliver.c +++ b/arch/arm/src/armv8-m/arm_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/armv8-m/arm_svcall.c b/arch/arm/src/armv8-m/arm_svcall.c index ed28937e1b5..4f57fb30270 100644 --- a/arch/arm/src/armv8-m/arm_svcall.c +++ b/arch/arm/src/armv8-m/arm_svcall.c @@ -311,34 +311,65 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg) break; #endif +#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD) + /* R0=SYS_pthread_start: This a user pthread start * - * void up_pthread_start(pthread_startroutine_t entrypt, - * pthread_addr_t arg) noreturn_function; + * void up_pthread_start(pthread_trampoline_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) * * At this point, the following values are saved in context: * * R0 = SYS_pthread_start - * R1 = entrypt - * R2 = arg + * R1 = startup + * R2 = entrypt + * R3 = arg */ -#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_PTHREAD) case SYS_pthread_start: { /* Set up to return to the user-space pthread start-up function in * unprivileged mode. */ - regs[REG_PC] = (uint32_t)USERSPACE->pthread_startup & ~1; + regs[REG_PC] = (uint32_t)regs[REG_R1] & ~1; /* startup */ regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; - /* Change the parameter ordering to match the expectation of struct - * userpace_s pthread_startup: + /* Change the parameter ordering to match the expectation of the + * user space pthread_startup: */ - regs[REG_R0] = regs[REG_R1]; /* pthread entry */ - regs[REG_R1] = regs[REG_R2]; /* arg */ + regs[REG_R0] = regs[REG_R2]; /* pthread entry */ + regs[REG_R1] = regs[REG_R3]; /* arg */ + } + break; + + /* R0=SYS_pthread_exit: This pthread_exit call in user-space + * + * void up_pthread_exit(pthread_exitroutine_t exit, + * FAR void *exit_value) + * + * At this point, the following values are saved in context: + * + * R0 = SYS_pthread_exit + * R1 = pthread_exit trampoline routine + * R2 = exit_value + */ + + case SYS_pthread_exit: + { + /* Set up to return to the user-space pthread start-up function in + * unprivileged mode. + */ + + regs[REG_PC] = (uint32_t)regs[REG_R1] & ~1; /* startup */ + regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; + + /* Change the parameter ordering to match the expectation of the + * user space pthread_startup: + */ + + regs[REG_R0] = regs[REG_R2]; /* exit_value */ } break; #endif diff --git a/arch/arm/src/armv8-m/arm_unblocktask.c b/arch/arm/src/armv8-m/arm_unblocktask.c index 7d2dde6e7ca..2af78527c6e 100644 --- a/arch/arm/src/armv8-m/arm_unblocktask.c +++ b/arch/arm/src/armv8-m/arm_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/armv8-m/svcall.h b/arch/arm/src/armv8-m/svcall.h index 77a1f9257eb..7213084634f 100644 --- a/arch/arm/src/armv8-m/svcall.h +++ b/arch/arm/src/armv8-m/svcall.h @@ -88,6 +88,7 @@ #define SYS_syscall_return (3) +#ifndef CONFIG_BUILD_FLAT #ifdef CONFIG_BUILD_PROTECTED /* SYS call 4: * @@ -97,14 +98,6 @@ #define SYS_task_start (4) -/* SYS call 5: - * - * void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) - * noreturn_function - */ - -#define SYS_pthread_start (5) - /* SYS call 6: * * void signal_handler(_sa_sigaction_t sighand, @@ -122,6 +115,17 @@ #define SYS_signal_handler_return (7) #endif /* CONFIG_BUILD_PROTECTED */ + +/* SYS call 5: + * + * void up_pthread_start(pthread_startroutine_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (5) + +#endif /* !CONFIG_BUILD_FLAT */ #endif /* CONFIG_LIB_SYSCALL */ /**************************************************************************** diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c index 51e922f4998..f7659fb2436 100644 --- a/arch/arm/src/c5471/c5471_serial.c +++ b/arch/arm/src/c5471/c5471_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/common/arm_pthread_exit.c b/arch/arm/src/common/arm_pthread_exit.c new file mode 100644 index 00000000000..ba7eb825d2b --- /dev/null +++ b/arch/arm/src/common/arm_pthread_exit.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/arm/src/common/arm_pthread_exit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "svcall.h" +#include "arm_internal.h" + +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) && \ + !defined(CONFIG_DISABLE_PTHREAD) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_pthread_exit + * + * Description: + * In this kernel mode build, this function will be called to execute a + * pthread in user-space. This kernel-mode stub will then be called + * transfer control to the user-mode pthread_exit. + * + * Input Parameters: + * exit - The user-space pthread_exit function + * exit_value - The pointer of the pthread exit parameter + * + * Returned Value: + * None + ****************************************************************************/ + +void up_pthread_exit(pthread_exitroutine_t exit, FAR void *exit_value) +{ + /* Let sys_call2() do all of the work */ + + sys_call2(SYS_pthread_exit, (uintptr_t)exit, (uintptr_t)exit_value); +} + +#endif /* !CONFIG_BUILD_FLAT && __KERNEL__ && !CONFIG_DISABLE_PTHREAD */ diff --git a/arch/arm/src/common/arm_pthread_start.c b/arch/arm/src/common/arm_pthread_start.c index f96c4a5d7a1..0caf5efb790 100644 --- a/arch/arm/src/common/arm_pthread_start.c +++ b/arch/arm/src/common/arm_pthread_start.c @@ -26,6 +26,8 @@ #include #include +#include + #include "svcall.h" #include "arm_internal.h" @@ -47,9 +49,10 @@ * pthread. * * Normally the a user-mode start-up stub will also execute before the - * pthread actually starts. See libc/pthread/pthread_startup.c + * pthread actually starts. See libc/pthread/pthread_create.c * * Input Parameters: + * startup - The user-space pthread startup function * entrypt - The user-space address of the pthread entry point * arg - Standard argument for the pthread entry point * @@ -60,11 +63,13 @@ * ****************************************************************************/ -void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) +void up_pthread_start(pthread_trampoline_t startup, + pthread_startroutine_t entrypt, pthread_addr_t arg) { - /* Let sys_call2() do all of the work */ + /* Let sys_call3() do all of the work */ - sys_call2(SYS_pthread_start, (uintptr_t)entrypt, (uintptr_t)arg); + sys_call3(SYS_pthread_start, (uintptr_t)startup, (uintptr_t)entrypt, + (uintptr_t)arg); PANIC(); } diff --git a/arch/arm/src/common/arm_task_start.c b/arch/arm/src/common/arm_task_start.c index 3cd180898be..53cfd8b46e2 100644 --- a/arch/arm/src/common/arm_task_start.c +++ b/arch/arm/src/common/arm_task_start.c @@ -25,6 +25,8 @@ #include #include +#include + #include "svcall.h" #include "arm_internal.h" diff --git a/arch/arm/src/cxd56xx/Kconfig b/arch/arm/src/cxd56xx/Kconfig index 2f1f404e9da..c168c3e5a66 100644 --- a/arch/arm/src/cxd56xx/Kconfig +++ b/arch/arm/src/cxd56xx/Kconfig @@ -75,6 +75,17 @@ config CXD56_PMIC default y if CXD56_MAINCORE default n if CXD56_SUBCORE +if CXD56_PMIC + +config CXD56_PMIC_INT + bool "PMIC interrupt" + default n + depends on SCHED_LPWORK + ---help--- + Enable PMIC interrupt. + +endif + config CXD56_CPUFIFO bool default y @@ -190,6 +201,7 @@ config CXD56_WDT_INTERRUPT config CXD56_WDT_REGDEBUG bool "Register level debug" default n + depends on DEBUG_WATCHDOG_INFO ---help--- Enable low-level register debug output @@ -223,6 +235,37 @@ config CXD56_PM_PROCFS ---help--- Enable the power domain status or the clock frequency monitor. +config CXD56_PM_DEBUG + bool "Power Management Debug Features" + default n + ---help--- + Enable power management debug features. + +if CXD56_PM_DEBUG + +config CXD56_PM_DEBUG_ERROR + bool "Power Management Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable power management error output to SYSLOG. + +config CXD56_PM_DEBUG_WARN + bool "Power Management Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable power management warning output to SYSLOG. + +config CXD56_PM_DEBUG_INFO + bool "Power Management Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable power management informational output to SYSLOG. + +endif # CXD56_PM_DEBUG + endif # CXD56_PM config CXD56_GAUGE @@ -1092,6 +1135,45 @@ config CXD56_CISIF default n ---help--- CMOS image sensor interface for cx5602 chip + +config CXD56_HOSTIF + bool "Host interface" + default n + ---help--- + Host interface supports I2C or SPI slave feature. + +config CXD56_HOSTIF_DEBUG + bool "Host interface Debug Features" + default n + depends on CXD56_HOSTIF + ---help--- + Enable host interface device debug features. + +if CXD56_HOSTIF_DEBUG + +config CXD56_HOSTIF_DEBUG_ERROR + bool "Host interface Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable host interface error output to SYSLOG. + +config CXD56_HOSTIF_DEBUG_WARN + bool "Host interface Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable host interface warning output to SYSLOG. + +config CXD56_HOSTIF_DEBUG_INFO + bool "Host interface Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable host interface informational output to SYSLOG. + +endif # CXD56_HOSTIF_DEBUG + endmenu comment "Storage Options" @@ -1194,6 +1276,16 @@ config CXD56_EMMC ---help--- Emmc driver for cxd56xx chip +if CXD56_EMMC + +config CXD56_EMMC_VENDOR_TOSHIBA + bool "Toshiba eMMC device" + default n + ---help--- + Enable vendor-specific commands for Toshiba eMMC device. + +endif # CXD56_EMMC + endmenu config CXD56_GE2D @@ -1286,9 +1378,25 @@ endif config CXD56_TESTSET bool "Use custom testset for spinlock" - default n - depends on SPINLOCK + default y + depends on SMP ---help--- - Use custom testset based on hardware semaphore + Use custom testset +if CXD56_TESTSET + +config CXD56_TESTSET_WITH_HWSEM + bool "Use custom testset based on hardware semaphore" + default n if CXD56_USE_SYSBUS + default y if !CXD56_USE_SYSBUS + ---help--- + +endif + +config CXD56_USE_SYSBUS + bool "Use the system bus for the data section" + default y + select ARCH_USE_TEXT_HEAP if ELF + ---help--- + To make ldrex/strex work correctly, this option must be enabled endmenu diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs index 1c386a0160b..ab4119eef2c 100644 --- a/arch/arm/src/cxd56xx/Make.defs +++ b/arch/arm/src/cxd56xx/Make.defs @@ -51,6 +51,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif @@ -96,6 +97,10 @@ CHIP_CSRCS += cxd56_testset.c endif endif +ifeq ($(CONFIG_ARCH_USE_TEXT_HEAP), y) +CHIP_CSRCS += cxd56_textheap.c +endif + ifeq ($(CONFIG_CXD56_UART0),y) CHIP_CSRCS += cxd56_uart0.c endif @@ -201,3 +206,7 @@ endif ifeq ($(CONFIG_CXD56_BACKUPLOG),y) CHIP_CSRCS += cxd56_backuplog.c endif + +ifeq ($(CONFIG_CXD56_HOSTIF),y) +CHIP_CSRCS += cxd56_hostif.c +endif diff --git a/arch/arm/src/cxd56xx/cxd56_adc.c b/arch/arm/src/cxd56xx/cxd56_adc.c index 728a01bebdb..d75d614061b 100644 --- a/arch/arm/src/cxd56xx/cxd56_adc.c +++ b/arch/arm/src/cxd56xx/cxd56_adc.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -35,6 +36,7 @@ #include #include #include +#include #include #include @@ -172,6 +174,8 @@ struct cxd56adc_dev_s struct scufifo_wm_s *wm; /* water mark */ struct math_filter_s *filter; /* math filter */ struct scuev_notify_s * notify; /* notify */ + sem_t exclsem; /* exclusive semaphore */ + int crefs; /* reference count */ }; /**************************************************************************** @@ -218,6 +222,7 @@ static struct cxd56adc_dev_s g_lpadc0priv = .wm = NULL, .filter = NULL, .notify = NULL, + .crefs = 0, }; #endif @@ -233,6 +238,7 @@ static struct cxd56adc_dev_s g_lpadc1priv = .wm = NULL, .filter = NULL, .notify = NULL, + .crefs = 0, }; #endif @@ -248,6 +254,7 @@ static struct cxd56adc_dev_s g_lpadc2priv = .wm = NULL, .filter = NULL, .notify = NULL, + .crefs = 0, }; #endif @@ -263,6 +270,7 @@ static struct cxd56adc_dev_s g_lpadc3priv = .wm = NULL, .filter = NULL, .notify = NULL, + .crefs = 0, }; #endif @@ -278,6 +286,7 @@ static struct cxd56adc_dev_s g_hpadc0priv = .wm = NULL, .filter = NULL, .notify = NULL, + .crefs = 0, }; #endif @@ -293,6 +302,7 @@ static struct cxd56adc_dev_s g_hpadc1priv = .wm = NULL, .filter = NULL, .notify = NULL, + .crefs = 0, }; #endif @@ -703,9 +713,23 @@ static int cxd56_adc_open(FAR struct file *filep) int type; DEBUGASSERT(priv != NULL); - DEBUGASSERT(priv->seq == NULL); DEBUGASSERT(priv->ch < CH_MAX); + /* Increment reference counter */ + + nxsem_wait_uninterruptible(&priv->exclsem); + + priv->crefs++; + DEBUGASSERT(priv->crefs > 0); + + if (priv->crefs > 1) + { + nxsem_post(&priv->exclsem); + return OK; + } + + DEBUGASSERT(priv->seq == NULL); + type = SCU_BUS_LPADC0 + priv->ch; /* Open sequencer */ @@ -713,6 +737,7 @@ static int cxd56_adc_open(FAR struct file *filep) priv->seq = seq_open(SEQ_TYPE_NORMAL, type); if (!priv->seq) { + nxsem_post(&priv->exclsem); return -ENOENT; } @@ -725,11 +750,14 @@ static int cxd56_adc_open(FAR struct file *filep) ret = set_ofstgain(priv); if (ret < 0) { + nxsem_post(&priv->exclsem); return ret; } ainfo("open ch%d freq%d scufifo%d\n", priv->ch, priv->freq, priv->fsize); + nxsem_post(&priv->exclsem); + return OK; } @@ -750,6 +778,19 @@ static int cxd56_adc_close(FAR struct file *filep) DEBUGASSERT(priv->seq != NULL); DEBUGASSERT(priv->ch < CH_MAX); + /* Decrement reference counter */ + + nxsem_wait_uninterruptible(&priv->exclsem); + + DEBUGASSERT(priv->crefs > 0); + priv->crefs--; + + if (priv->crefs > 0) + { + nxsem_post(&priv->exclsem); + return OK; + } + /* Close sequencer */ seq_close(priv->seq); @@ -773,6 +814,8 @@ static int cxd56_adc_close(FAR struct file *filep) priv->notify = NULL; } + nxsem_post(&priv->exclsem); + return OK; } @@ -1058,6 +1101,7 @@ int cxd56_adcinitialize(void) return ret; } + nxsem_init(&g_lpadc0priv.exclsem, 0, 1); #endif #if defined (CONFIG_CXD56_LPADC1) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL) ret = register_driver("/dev/lpadc1", &g_adcops, 0666, &g_lpadc1priv); @@ -1067,6 +1111,7 @@ int cxd56_adcinitialize(void) return ret; } + nxsem_init(&g_lpadc1priv.exclsem, 0, 1); #endif #if defined (CONFIG_CXD56_LPADC2) || defined (CONFIG_CXD56_LPADC_ALL) ret = register_driver("/dev/lpadc2", &g_adcops, 0666, &g_lpadc2priv); @@ -1076,6 +1121,7 @@ int cxd56_adcinitialize(void) return ret; } + nxsem_init(&g_lpadc2priv.exclsem, 0, 1); #endif #if defined (CONFIG_CXD56_LPADC3) || defined (CONFIG_CXD56_LPADC_ALL) ret = register_driver("/dev/lpadc3", &g_adcops, 0666, &g_lpadc3priv); @@ -1085,6 +1131,7 @@ int cxd56_adcinitialize(void) return ret; } + nxsem_init(&g_lpadc3priv.exclsem, 0, 1); #endif #ifdef CONFIG_CXD56_HPADC0 ret = register_driver("/dev/hpadc0", &g_adcops, 0666, &g_hpadc0priv); @@ -1094,6 +1141,7 @@ int cxd56_adcinitialize(void) return ret; } + nxsem_init(&g_hpadc0priv.exclsem, 0, 1); #endif #ifdef CONFIG_CXD56_HPADC1 ret = register_driver("/dev/hpadc1", &g_adcops, 0666, &g_hpadc1priv); @@ -1103,6 +1151,7 @@ int cxd56_adcinitialize(void) return ret; } + nxsem_init(&g_hpadc1priv.exclsem, 0, 1); #endif return ret; diff --git a/arch/arm/src/cxd56xx/cxd56_backuplog.c b/arch/arm/src/cxd56xx/cxd56_backuplog.c index 9795a4083cd..011738e4f3c 100644 --- a/arch/arm/src/cxd56xx/cxd56_backuplog.c +++ b/arch/arm/src/cxd56xx/cxd56_backuplog.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_charger.c b/arch/arm/src/cxd56xx/cxd56_charger.c index 48d9bf9e4ba..1bd3970f095 100644 --- a/arch/arm/src/cxd56xx/cxd56_charger.c +++ b/arch/arm/src/cxd56xx/cxd56_charger.c @@ -26,6 +26,7 @@ ****************************************************************************/ #include +#include #include #include @@ -61,13 +62,8 @@ /* Configuration */ -#undef USE_FLOAT_CONVERSION - #ifdef CONFIG_CXD56_CHARGER_TEMP_PRECISE -#if !defined(CONFIG_LIBM) && !defined(CONFIG_ARCH_MATH_H) -# error Temperature conversion in float requires math library. -#endif -#define USE_FLOAT_CONVERSION 1 +# define USE_FLOAT_CONVERSION #endif /**************************************************************************** @@ -672,7 +668,7 @@ int cxd56_charger_initialize(FAR const char *devpath) ret = register_driver(devpath, &g_chargerops, 0666, priv); if (ret < 0) { - _err("ERROR: register_driver failed: %d\n", ret); + baterr("ERROR: register_driver failed: %d\n", ret); return -EFAULT; } diff --git a/arch/arm/src/cxd56xx/cxd56_cisif.c b/arch/arm/src/cxd56xx/cxd56_cisif.c index e4445b91f47..1e0951991f4 100644 --- a/arch/arm/src/cxd56xx/cxd56_cisif.c +++ b/arch/arm/src/cxd56xx/cxd56_cisif.c @@ -604,7 +604,7 @@ static int cisif_set_yuv_sarea(void *s) /* must align 32 bytes */ cisif_reg_write(CISIF_YCC_DAREA_SIZE, (ss->strg_size & 0xffffffe0)); - cisif_reg_write(CISIF_YCC_START_ADDR, (uint32_t)ss->strg_addr); + cisif_reg_write(CISIF_YCC_START_ADDR, CXD56_PHYSADDR(ss->strg_addr)); return OK; } @@ -636,7 +636,7 @@ static int cisif_set_jpg_sarea(void *s) /* must align 32 bytes */ cisif_reg_write(CISIF_JPG_DAREA_SIZE, (ss->strg_size & 0xffffffe0)); - cisif_reg_write(CISIF_JPG_START_ADDR, (uint32_t)ss->strg_addr); + cisif_reg_write(CISIF_JPG_START_ADDR, CXD56_PHYSADDR(ss->strg_addr)); return OK; } diff --git a/arch/arm/src/cxd56xx/cxd56_clock.c b/arch/arm/src/cxd56xx/cxd56_clock.c index a46acc354a8..7a05641f636 100644 --- a/arch/arm/src/cxd56xx/cxd56_clock.c +++ b/arch/arm/src/cxd56xx/cxd56_clock.c @@ -24,8 +24,9 @@ #include #include -#include +#include +#include #include #include @@ -44,14 +45,22 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_DEBUG_PM -# define pmerr(fmt, ...) logerr(fmt, ## __VA_ARGS__) -# define pminfo(fmt, ...) loginfo(fmt, ## __VA_ARGS__) -# define pmdbg(fmt, ...) logdebug(fmt, ## __VA_ARGS__) +/* Debug */ + +#ifdef CONFIG_CXD56_PM_DEBUG_ERROR +# define pmerr(format, ...) _err(format, ##__VA_ARGS__) #else -# define pmerr(fmt, ...) -# define pminfo(fmt, ...) -# define pmdbg(fmt, ...) +# define pmerr(x, ...) +#endif +#ifdef CONFIG_CXD56_PM_DEBUG_WARN +# define pmwarn(format, ...) _warn(format, ##__VA_ARGS__) +#else +# define pmwarn(x, ...) +#endif +#ifdef CONFIG_CXD56_PM_DEBUG_INFO +# define pminfo(format, ...) _info(format, ##__VA_ARGS__) +#else +# define pminfo(x, ...) #endif /* For enable_pwd, disable_pwd (digital domain) */ @@ -2291,6 +2300,182 @@ uint32_t cxd56_get_img_vsync_baseclock(void) } } +static int cxd56_hostif_clock_ctrl(uint32_t block, uint32_t intr, int on) +{ + uint32_t val; + uint32_t stat; + int retry = 10000; + + putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0); + + val = getreg32(CXD56_TOPREG_SYSIOP_CKEN); + if (on) + { + if ((val & block) == block) + { + /* Already clock on */ + + return OK; + } + + putreg32(val | block, CXD56_TOPREG_SYSIOP_CKEN); + } + else + { + if ((val & block) == 0) + { + /* Already clock off */ + + return OK; + } + + putreg32(val & ~block, CXD56_TOPREG_SYSIOP_CKEN); + } + + do + { + stat = getreg32(CXD56_TOPREG_CRG_INT_STAT_RAW0); + busy_wait(1000); + } + while (retry-- && !(stat & intr)); + + putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0); + + return (retry) ? OK : -ETIMEDOUT; +} + +int cxd56_hostif_clock_enable(void) +{ + int ret = OK; + uint32_t mask; + uint32_t intr; + + /* Enable HOSTIF IRAM/DRAM & general RAM memory power. */ + + putreg32((0x3 << 24) | 0xf, CXD56_TOPREG_HOSTIFC_RAMMODE_SEL); + + do_power_control(); + + mask = CKEN_HOSSPI | CKEN_HOSI2C | CKEN_HOSTIFC_SEQ | CKEN_BRG_HOST | + CKEN_I2CS | CKEN_PCLK_HOSTIFC | CKEN_PCLK_UART0 | CKEN_UART0; + + if (getreg32(CXD56_TOPREG_SYSIOP_CKEN) & mask) + { + /* Already enabled */ + + return ret; + } + + putreg32(0, CXD56_TOPREG_CKDIV_HOSTIFC); + putreg32(0, CXD56_TOPREG_CKSEL_SYSIOP); + + mask = CKEN_HOSSPI | CKEN_HOSI2C | CKEN_BRG_HOST | + CKEN_I2CS | CKEN_PCLK_HOSTIFC; + + intr = CRG_CK_BRG_HOST | CRG_CK_I2CS | CRG_CK_PCLK_HOSTIFC; + + ret = cxd56_hostif_clock_ctrl(mask, intr, 1); + if (ret < 0) + { + return ret; + } + + ret = cxd56_hostif_clock_ctrl(mask, intr, 0); + if (ret < 0) + { + return ret; + } + + modifyreg32(CXD56_TOPREG_SWRESET_BUS, 0, XRST_HOSTIFC); + ret = cxd56_hostif_clock_ctrl(mask, intr, 1); + + return ret; +} + +int cxd56_hostif_clock_disable(void) +{ + int ret = OK; + uint32_t mask; + uint32_t intr; + + mask = CKEN_HOSSPI | CKEN_HOSI2C | CKEN_HOSTIFC_SEQ | CKEN_BRG_HOST | + CKEN_I2CS | CKEN_PCLK_HOSTIFC | CKEN_PCLK_UART0 | CKEN_UART0; + + if (0 == (getreg32(CXD56_TOPREG_SYSIOP_CKEN) & mask)) + { + /* Already disabled */ + + return ret; + } + + mask = CKEN_HOSSPI | CKEN_HOSI2C | CKEN_BRG_HOST | + CKEN_I2CS | CKEN_PCLK_HOSTIFC; + + intr = CRG_CK_BRG_HOST | CRG_CK_I2CS | CRG_CK_PCLK_HOSTIFC; + + ret = cxd56_hostif_clock_ctrl(mask, intr, 0); + if (ret < 0) + { + return ret; + } + + modifyreg32(CXD56_TOPREG_SWRESET_BUS, XRST_HOSTIFC, 0); + + /* Disable HOSTIF IRAM/DRAM & general RAM memory power. */ + + putreg32(0x3, CXD56_TOPREG_HOSTIFC_RAMMODE_SEL); + + do_power_control(); + + return ret; +} + +int cxd56_hostseq_clock_enable(void) +{ + int ret = OK; + + if (getreg32(CXD56_TOPREG_SYSIOP_CKEN) & CKEN_HOSTIFC_SEQ) + { + /* Already enabled */ + + return ret; + } + + ret = cxd56_hostif_clock_ctrl(CKEN_HOSTIFC_SEQ, CRG_CK_HOSTIFC_SEQ, 1); + if (ret < 0) + { + return ret; + } + + ret = cxd56_hostif_clock_ctrl(CKEN_HOSTIFC_SEQ, CRG_CK_HOSTIFC_SEQ, 0); + if (ret < 0) + { + return ret; + } + + modifyreg32(CXD56_TOPREG_SWRESET_BUS, 0, XRST_HOSTIFC_ISOP); + ret = cxd56_hostif_clock_ctrl(CKEN_HOSTIFC_SEQ, CRG_CK_HOSTIFC_SEQ, 1); + + return ret; +} + +int cxd56_hostseq_clock_disable(void) +{ + int ret = OK; + + if (0 == (getreg32(CXD56_TOPREG_SYSIOP_CKEN) & CKEN_HOSTIFC_SEQ)) + { + /* Already disabled */ + + return ret; + } + + modifyreg32(CXD56_TOPREG_SWRESET_BUS, XRST_HOSTIFC_ISOP, 0); + ret = cxd56_hostif_clock_ctrl(CKEN_HOSTIFC_SEQ, CRG_CK_HOSTIFC_SEQ, 0); + + return ret; +} + int up_pmramctrl(int cmd, uintptr_t addr, size_t size) { int startidx; @@ -2312,8 +2497,8 @@ int up_pmramctrl(int cmd, uintptr_t addr, size_t size) endidx = TILEALIGNIDX(TILEALIGN(addr + size)); DEBUGASSERT(startidx < 12 && endidx <= 12); - pmdbg("%x (size: %x) [%d:%d] -> %d\n", addr, size, - startidx, endidx, cmd); + pminfo("%x (size: %x) [%d:%d] -> %d\n", addr, size, + startidx, endidx, cmd); /* Make controls bits for RAM power control */ @@ -2378,7 +2563,7 @@ int up_pmramctrl(int cmd, uintptr_t addr, size_t size) return OK; } -#ifdef CONFIG_DEBUG_PM +#ifdef CONFIG_CXD56_PM_DEBUG_INFO /**************************************************************************** * Name: up_pmstatdump * @@ -2397,34 +2582,34 @@ void up_pmstatdump(void) stat0 = getreg32(CXD56_TOPREG_APPDSP_RAMMODE_STAT0); stat1 = getreg32(CXD56_TOPREG_APPDSP_RAMMODE_STAT1); - pmdbg(" 0 1 2 3 4 5 6 7 8 9 A B\n"); - pmdbg("DSP RAM stat: %c %c %c %c %c %c %c %c %c %c %c %c\n", - statch[(stat0 >> 0) & 3], - statch[(stat0 >> 2) & 3], - statch[(stat0 >> 4) & 3], - statch[(stat0 >> 6) & 3], - statch[(stat0 >> 8) & 3], - statch[(stat0 >> 10) & 3], - statch[(stat1 >> 0) & 3], - statch[(stat1 >> 2) & 3], - statch[(stat1 >> 4) & 3], - statch[(stat1 >> 6) & 3], - statch[(stat1 >> 8) & 3], - statch[(stat1 >> 10) & 3]); + pminfo(" 0 1 2 3 4 5 6 7 8 9 A B\n"); + pminfo("DSP RAM stat: %c %c %c %c %c %c %c %c %c %c %c %c\n", + statch[(stat0 >> 0) & 3], + statch[(stat0 >> 2) & 3], + statch[(stat0 >> 4) & 3], + statch[(stat0 >> 6) & 3], + statch[(stat0 >> 8) & 3], + statch[(stat0 >> 10) & 3], + statch[(stat1 >> 0) & 3], + statch[(stat1 >> 2) & 3], + statch[(stat1 >> 4) & 3], + statch[(stat1 >> 6) & 3], + statch[(stat1 >> 8) & 3], + statch[(stat1 >> 10) & 3]); stat0 = getreg32(CXD56_CRG_APP_TILE_CLK_GATING_ENB); - pmdbg("Clock gating: %c %c %c %c %c %c %c %c %c %c %c %c\n", - gatech[(stat0 >> 0) & 1], - gatech[(stat0 >> 1) & 1], - gatech[(stat0 >> 2) & 1], - gatech[(stat0 >> 3) & 1], - gatech[(stat0 >> 4) & 1], - gatech[(stat0 >> 5) & 1], - gatech[(stat0 >> 6) & 1], - gatech[(stat0 >> 7) & 1], - gatech[(stat0 >> 8) & 1], - gatech[(stat0 >> 9) & 1], - gatech[(stat0 >> 10) & 1], - gatech[(stat0 >> 11) & 1]); + pminfo("Clock gating: %c %c %c %c %c %c %c %c %c %c %c %c\n", + gatech[(stat0 >> 0) & 1], + gatech[(stat0 >> 1) & 1], + gatech[(stat0 >> 2) & 1], + gatech[(stat0 >> 3) & 1], + gatech[(stat0 >> 4) & 1], + gatech[(stat0 >> 5) & 1], + gatech[(stat0 >> 6) & 1], + gatech[(stat0 >> 7) & 1], + gatech[(stat0 >> 8) & 1], + gatech[(stat0 >> 9) & 1], + gatech[(stat0 >> 10) & 1], + gatech[(stat0 >> 11) & 1]); } #endif diff --git a/arch/arm/src/cxd56xx/cxd56_clock.h b/arch/arm/src/cxd56xx/cxd56_clock.h index 1f488ed6484..81014ca1fb8 100644 --- a/arch/arm/src/cxd56xx/cxd56_clock.h +++ b/arch/arm/src/cxd56xx/cxd56_clock.h @@ -684,6 +684,46 @@ uint32_t cxd56_get_img_vsync_baseclock(void); uint32_t cxd56_get_appsmp_baseclock(void); +/**************************************************************************** + * Name: cxd56_hostif_clock_enable + * + * Description: + * Enable clock of the hostif block + * + ****************************************************************************/ + +int cxd56_hostif_clock_enable(void); + +/**************************************************************************** + * Name: cxd56_hostif_clock_disable + * + * Description: + * Disable clock of the hostif block + * + ****************************************************************************/ + +int cxd56_hostif_clock_disable(void); + +/**************************************************************************** + * Name: cxd56_hostseq_clock_enable + * + * Description: + * Enable clock of the hostif sequencer block + * + ****************************************************************************/ + +int cxd56_hostseq_clock_enable(void); + +/**************************************************************************** + * Name: cxd56_hostseq_clock_disable + * + * Description: + * Disable clock of the hostif sequencer block + * + ****************************************************************************/ + +int cxd56_hostseq_clock_disable(void); + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/cxd56xx/cxd56_cpu1signal.c b/arch/arm/src/cxd56xx/cxd56_cpu1signal.c index 42b775b537e..1dcccc60e47 100644 --- a/arch/arm/src/cxd56xx/cxd56_cpu1signal.c +++ b/arch/arm/src/cxd56xx/cxd56_cpu1signal.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include "cxd56_icc.h" diff --git a/arch/arm/src/cxd56xx/cxd56_cpufifo.c b/arch/arm/src/cxd56xx/cxd56_cpufifo.c index db978ac680e..34ffceb67a1 100644 --- a/arch/arm/src/cxd56xx/cxd56_cpufifo.c +++ b/arch/arm/src/cxd56xx/cxd56_cpufifo.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_delay.c b/arch/arm/src/cxd56xx/cxd56_delay.c index c4011c82325..3797963b52e 100644 --- a/arch/arm/src/cxd56xx/cxd56_delay.c +++ b/arch/arm/src/cxd56xx/cxd56_delay.c @@ -34,13 +34,22 @@ * Pre-processor Definitions ****************************************************************************/ -#define CXD56XX_LOOPSPERMSEC_156MHZ 7428ull +#ifdef CONFIG_CXD56_USE_SYSBUS +# define CXD56XX_LOOPSPERMSEC_156MHZ 15533ull +#else +# define CXD56XX_LOOPSPERMSEC_156MHZ 7428ull +#endif + #define CXD56XX_LOOPSPERMSEC_BY_CLOCK(clock) \ (uint32_t)(CXD56XX_LOOPSPERMSEC_156MHZ * (clock) / 156000000ull) /* Adjust manually to be up_udelay(1000) is neary equal with up_udelay(999) */ -#define CXD56XX_LOOPSPERUSEC_ADJUST 810ul; +#ifdef CONFIG_CXD56_USE_SYSBUS +# define CXD56XX_LOOPSPERUSEC_ADJUST 1010ul; +#else +# define CXD56XX_LOOPSPERUSEC_ADJUST 810ul; +#endif /**************************************************************************** * Public Functions diff --git a/arch/arm/src/cxd56xx/cxd56_dmac.c b/arch/arm/src/cxd56xx/cxd56_dmac.c index 61850d09616..a47cef1ea7d 100644 --- a/arch/arm/src/cxd56xx/cxd56_dmac.c +++ b/arch/arm/src/cxd56xx/cxd56_dmac.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -37,6 +38,10 @@ #include "cxd56_dmac.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + #define PM_APP_ADMAC 51 #define PM_APP_SKDMAC 52 #define PM_APP_IDMAC 54 @@ -900,6 +905,7 @@ void cxd56_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, di = 0; } + dst = CXD56_PHYSADDR(dst); rest = nbytes; list_num = (nbytes + CXD56_DMAC_MAX_SIZE - 1) / CXD56_DMAC_MAX_SIZE; @@ -907,7 +913,7 @@ void cxd56_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, { dmach->list[i].src_addr = paddr; dmach->list[i].dest_addr = dst; - dmach->list[i].nextlli = (uint32_t)&dmach->list[i + 1]; + dmach->list[i].nextlli = CXD56_PHYSADDR(&dmach->list[i + 1]); dmach->list[i].control = DMAC_EX_CTRL_HELPER(0, di, 0, /* interrupt / Dest inc / Src inc */ CXD56_DMAC_MASTER1, CXD56_DMAC_MASTER2, /* AHB dst master / AHB src master (fixed) */ config.dest_width, config.src_width, /* Dest / Src transfer width */ @@ -970,6 +976,7 @@ void cxd56_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, si = 0; } + src = CXD56_PHYSADDR(src); rest = nbytes; list_num = (nbytes + CXD56_DMAC_MAX_SIZE - 1) / CXD56_DMAC_MAX_SIZE; @@ -977,7 +984,7 @@ void cxd56_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, { dmach->list[i].src_addr = src; dmach->list[i].dest_addr = paddr; - dmach->list[i].nextlli = (uint32_t)&dmach->list[i + 1]; + dmach->list[i].nextlli = CXD56_PHYSADDR(&dmach->list[i + 1]); dmach->list[i].control = DMAC_EX_CTRL_HELPER(0, 0, si, /* interrupt / Dest inc / Src inc */ CXD56_DMAC_MASTER2, CXD56_DMAC_MASTER1, /* AHB dst master / AHB src master (fixed) */ config.dest_width, config.src_width, /* Dest / Src transfer width (fixed) */ diff --git a/arch/arm/src/cxd56xx/cxd56_emmc.c b/arch/arm/src/cxd56xx/cxd56_emmc.c index b7843a603fc..2fd8ca16b8b 100644 --- a/arch/arm/src/cxd56xx/cxd56_emmc.c +++ b/arch/arm/src/cxd56xx/cxd56_emmc.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -299,7 +300,7 @@ static struct emmc_dma_desc_s *emmc_setupdma(void *buf, unsigned int nbytes) } remain = nbytes; - addr = (uint32_t)(uintptr_t)buf; + addr = CXD56_PHYSADDR(buf); for (i = 0, d = descs; i < ndescs; i++, d++) { @@ -309,7 +310,7 @@ static struct emmc_dma_desc_s *emmc_setupdma(void *buf, unsigned int nbytes) size = MIN(remain, 4096); d->size = size; d->addr = addr; - d->next = (uint32_t)(uintptr_t)(d + 1); + d->next = CXD56_PHYSADDR(d + 1); remain -= size; addr += size; @@ -323,7 +324,7 @@ static struct emmc_dma_desc_s *emmc_setupdma(void *buf, unsigned int nbytes) descs[ndescs - 1].ctrl |= EMMC_IDMAC_DES0_LD; descs[ndescs - 1].next = 0; -#ifdef CONFIG_DEBUG_VERBOSE +#ifdef CONFIG_DEBUG_FS_INFO for (i = 0, d = descs; i < ndescs; i++, d++) { finfo("desc %p = ctrl 0x%x, size 0x%x, addr 0x%x, next 0x%x\n", @@ -331,7 +332,7 @@ static struct emmc_dma_desc_s *emmc_setupdma(void *buf, unsigned int nbytes) } #endif - putreg32((uint32_t)(uintptr_t)descs, EMMC_DBADDR); + putreg32(CXD56_PHYSADDR(descs), EMMC_DBADDR); return descs; } @@ -667,11 +668,15 @@ static int emmc_hwinitialize(void) emmc_changeclock(EMMC_CLKDIV_NON_DIV); +#ifdef CONFIG_CXD56_EMMC_VENDOR_TOSHIBA + /* Vendor-specific command */ + ret = emmc_switchcmd(EXTCSD_PON, EXTCSD_PON_POWERED_ON); if (ret) { goto errout; } +#endif return OK; diff --git a/arch/arm/src/cxd56xx/cxd56_farapi.c b/arch/arm/src/cxd56xx/cxd56_farapi.c index 093a449704a..bf7cf986c07 100644 --- a/arch/arm/src/cxd56xx/cxd56_farapi.c +++ b/arch/arm/src/cxd56xx/cxd56_farapi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_farapistub.h b/arch/arm/src/cxd56xx/cxd56_farapistub.h index 5fa5c272448..3e12f7551e5 100644 --- a/arch/arm/src/cxd56xx/cxd56_farapistub.h +++ b/arch/arm/src/cxd56xx/cxd56_farapistub.h @@ -21,6 +21,6 @@ #ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPISTUB_H #define __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPISTUB_H -#define FARAPISTUB_VERSION 20129 +#define FARAPISTUB_VERSION 20175 #endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPISTUB_H */ diff --git a/arch/arm/src/cxd56xx/cxd56_gauge.c b/arch/arm/src/cxd56xx/cxd56_gauge.c index 1decda4d865..769838a7db5 100644 --- a/arch/arm/src/cxd56xx/cxd56_gauge.c +++ b/arch/arm/src/cxd56xx/cxd56_gauge.c @@ -52,11 +52,11 @@ /* Debug ********************************************************************/ #ifdef CONFIG_CXD56_GAUGE_DEBUG -#define baterr(fmt, ...) logerr(fmt, ## __VA_ARGS__) -#define batdbg(fmt, ...) logdebug(fmt, ## __VA_ARGS__) +#define baterr(fmt, ...) _err(fmt, ## __VA_ARGS__) +#define batinfo(fmt, ...) _info(fmt, ## __VA_ARGS__) #else #define baterr(fmt, ...) -#define batdbg(fmt, ...) +#define batinfo(fmt, ...) #endif /**************************************************************************** @@ -152,7 +152,7 @@ static int gauge_get_status(FAR enum battery_gauge_status_e *status) break; default: - _info("Charge state %d\n", state); + batinfo("Charge state %d\n", state); *status = BATTERY_IDLE; break; } @@ -394,7 +394,7 @@ int cxd56_gauge_initialize(FAR const char *devpath) ret = register_driver(devpath, &g_gaugeops, 0666, priv); if (ret < 0) { - _err("ERROR: register_driver failed: %d\n", ret); + baterr("ERROR: register_driver failed: %d\n", ret); return -EFAULT; } diff --git a/arch/arm/src/cxd56xx/cxd56_ge2d.c b/arch/arm/src/cxd56xx/cxd56_ge2d.c index e77f9e99a14..ec0305009f9 100644 --- a/arch/arm/src/cxd56xx/cxd56_ge2d.c +++ b/arch/arm/src/cxd56xx/cxd56_ge2d.c @@ -151,7 +151,7 @@ static ssize_t ge2d_write(FAR struct file *filep, * can't set except 1 in this chip. */ - putreg32((uint32_t)(uintptr_t)buffer | 1, GE2D_ADDRESS_DESCRIPTOR_START); + putreg32(CXD56_PHYSADDR(buffer) | 1, GE2D_ADDRESS_DESCRIPTOR_START); putreg32(GE2D_EXEC, GE2D_CMD_DESCRIPTOR); /* Enable error and completion interrupts. */ diff --git a/arch/arm/src/cxd56xx/cxd56_gnss.c b/arch/arm/src/cxd56xx/cxd56_gnss.c index eea3027bf0b..6a893659cae 100644 --- a/arch/arm/src/cxd56xx/cxd56_gnss.c +++ b/arch/arm/src/cxd56xx/cxd56_gnss.c @@ -132,14 +132,12 @@ extern int fw_pm_sleepcpu(int cpuid, int mode); * Private Types ****************************************************************************/ -#ifndef CONFIG_DISABLE_SIGNAL struct cxd56_gnss_sig_s { uint8_t enable; int pid; FAR struct cxd56_gnss_signal_info_s info; }; -#endif struct cxd56_gnss_shared_info_s { @@ -163,8 +161,7 @@ struct cxd56_gnss_dev_s struct file cepfp; FAR void * cepbuf; FAR struct pollfd *fds[CONFIG_CXD56_GNSS_NPOLLWAITERS]; -#if !defined(CONFIG_DISABLE_SIGNAL) && \ - (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) +#if CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0 struct cxd56_gnss_sig_s sigs[CONFIG_CXD56_GNSS_NSIGNALRECEIVERS]; #endif struct cxd56_gnss_shared_info_s shared_info; @@ -392,6 +389,11 @@ static struct pm_cpu_freqlock_s g_lv_lock = PM_CPUFREQLOCK_INIT(PM_CPUFREQLOCK_TAG('G', 'T', 0), PM_CPUFREQLOCK_FLAG_LV); +/* Lock to prohibit clock change in gnss open */ + +static struct pm_cpu_freqlock_s g_hold_lock = + PM_CPUFREQLOCK_INIT(0, PM_CPUFREQLOCK_FLAG_HOLD); + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -517,7 +519,7 @@ static int cxd56_gnss_get_satellite_system(FAR struct file *filep, unsigned long arg) { int ret; - uint32_t system; + uint32_t system = 0; if (!arg) { @@ -699,7 +701,7 @@ static int cxd56_gnss_get_tcxo_offset(FAR struct file *filep, unsigned long arg) { int ret; - int32_t offset; + int32_t offset = 0; if (!arg) { @@ -1459,8 +1461,7 @@ static int cxd56_gnss_set_signal(FAR struct file *filep, unsigned long arg) { int ret = 0; -#if !defined(CONFIG_DISABLE_SIGNAL) && \ - (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) +#if CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0 FAR struct inode *inode; FAR struct cxd56_gnss_dev_s *priv; FAR struct cxd56_gnss_signal_setting_s *setting; @@ -1533,10 +1534,7 @@ static int cxd56_gnss_set_signal(FAR struct file *filep, unsigned long arg) _success: _err: nxsem_post(&priv->devsem); -#endif -/* if !defined(CONFIG_DISABLE_SIGNAL) && - * (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) - */ +#endif /* CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0 */ return ret; } @@ -1743,7 +1741,7 @@ static int cxd56_gnss_get_rtk_interval(FAR struct file *filep, unsigned long arg) { int ret; - int interval; + int interval = 0; if (!arg) { @@ -1800,7 +1798,7 @@ static int cxd56_gnss_get_rtk_satellite(FAR struct file *filep, unsigned long arg) { int ret; - uint32_t gnss; + uint32_t gnss = 0; if (!arg) { @@ -1857,7 +1855,7 @@ static int cxd56_gnss_get_rtk_ephemeris_enable(FAR struct file *filep, unsigned long arg) { int ret; - int enable; + int enable = 0; if (!arg) { @@ -2257,9 +2255,6 @@ static void cxd56_gnss_read_backup_file(FAR int *retval) cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_BKUPFILE, 0); } -#if !defined(CONFIG_DISABLE_SIGNAL) && \ - (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) - /**************************************************************************** * Name: cxd56_gnss_common_signalhandler * @@ -2276,6 +2271,7 @@ static void cxd56_gnss_read_backup_file(FAR int *retval) * ****************************************************************************/ +#if CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0 static void cxd56_gnss_common_signalhandler(uint32_t data, FAR void *userdata) { @@ -2312,11 +2308,7 @@ static void cxd56_gnss_common_signalhandler(uint32_t data, nxsem_post(&priv->devsem); } - -#endif -/* if !defined(CONFIG_DISABLE_SIGNAL) && - * (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) - */ +#endif /* CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0 */ /**************************************************************************** * Name: cxd56_gnss_default_sighandler @@ -2418,8 +2410,7 @@ static void cxd56_gnss_default_sighandler(uint32_t data, FAR void *userdata) nxsem_post(&priv->devsem); -#if !defined(CONFIG_DISABLE_SIGNAL) && \ - (CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) +#if CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0 cxd56_gnss_common_signalhandler(data, userdata); #endif } @@ -2646,7 +2637,16 @@ static int cxd56_gnss_open(FAR struct file *filep) nxsem_set_protocol(&priv->syncsem, SEM_PRIO_NONE); + /* Prohibit the clock change during loading image */ + + up_pm_acquire_freqlock(&g_hold_lock); + ret = fw_pm_loadimage(CXD56_GNSS_GPS_CPUID, CXD56_GNSS_FWNAME); + + /* Allow the clock change after loading image */ + + up_pm_release_freqlock(&g_hold_lock); + if (ret < 0) { goto _err1; diff --git a/arch/arm/src/cxd56xx/cxd56_gnss.h b/arch/arm/src/cxd56xx/cxd56_gnss.h index e0e61a80394..e66e7f3d35b 100644 --- a/arch/arm/src/cxd56xx/cxd56_gnss.h +++ b/arch/arm/src/cxd56xx/cxd56_gnss.h @@ -47,19 +47,19 @@ extern "C" /* GNSS specific debug */ #ifdef CONFIG_CXD56_GNSS_DEBUG_ERROR -# define gnsserr(fmt, ...) logerr(fmt, ## __VA_ARGS__) +# define gnsserr(fmt, ...) _err(fmt, ## __VA_ARGS__) #else # define gnsserr(fmt, ...) #endif #ifdef CONFIG_CXD56_GNSS_DEBUG_WARN -# define gnsswarn(fmt, ...) logwarn(fmt, ## __VA_ARGS__) +# define gnsswarn(fmt, ...) _warn(fmt, ## __VA_ARGS__) #else # define gnsswarn(fmt, ...) #endif #ifdef CONFIG_CXD56_GNSS_DEBUG_INFO -# define gnssinfo(fmt, ...) loginfo(fmt, ## __VA_ARGS__) +# define gnssinfo(fmt, ...) _info(fmt, ## __VA_ARGS__) #else # define gnssinfo(fmt, ...) #endif diff --git a/arch/arm/src/cxd56xx/cxd56_gpioint.c b/arch/arm/src/cxd56xx/cxd56_gpioint.c index 1b1eab08995..1428555ffd0 100644 --- a/arch/arm/src/cxd56xx/cxd56_gpioint.c +++ b/arch/arm/src/cxd56xx/cxd56_gpioint.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_hostif.c b/arch/arm/src/cxd56xx/cxd56_hostif.c new file mode 100644 index 00000000000..1dac5b15175 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_hostif.c @@ -0,0 +1,595 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_hostif.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_arch.h" + +#include "cxd56_clock.h" +#include "cxd56_pinconfig.h" +#include "cxd56_icc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Debug */ + +#ifdef CONFIG_CXD56_HOSTIF_DEBUG_ERROR +#define hiferr(format, ...) _err(format, ##__VA_ARGS__) +#else +#define hiferr(x, ...) +#endif +#ifdef CONFIG_CXD56_HOSTIF_DEBUG_WARN +#define hifwarn(format, ...) _warn(format, ##__VA_ARGS__) +#else +#define hifwarn(x, ...) +#endif +#ifdef CONFIG_CXD56_HOSTIF_DEBUG_INFO +#define hifinfo(format, ...) _info(format, ##__VA_ARGS__) +#else +#define hifinfo(x, ...) +#endif + +/* Message id definitions */ + +#define HIF_I2C_INIT 1 +#define HIF_SPI_INIT 2 +#define HIF_READ_DEVICE 3 +#define HIF_WRITE_DEVICE 4 + +/* Message timeout definition in units of msec */ + +#define HIF_TIMEOUT 5000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Host interface device structure for each buffer */ + +struct cxd56_hifdev_s +{ + int id; + uint32_t flags; + const void *buffer; + size_t len; + sem_t exclsem; + int crefs; +}; + +/* Host interface driver structure */ + +struct cxd56_hifdrv_s +{ + struct cxd56_hifdev_s *dev; + int ndev; + sem_t sync; + int errcode; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Character driver methods */ + +static int hif_open(FAR struct file *filep); +static int hif_close(FAR struct file *filep); +static off_t hif_seek(FAR struct file *filep, off_t offset, + int whence); +static ssize_t hif_read(FAR struct file *filep, FAR char *buffer, + size_t len); +static ssize_t hif_write(FAR struct file *filep, + FAR const char *buffer, size_t len); +static int hif_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); +static int hif_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup); +static int hif_unlink(FAR struct inode *inode); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Host interface driver */ + +static struct cxd56_hifdrv_s g_hifdrv; + +/* Host interface operations */ + +static const struct file_operations g_hif_fops = +{ + hif_open, /* open */ + hif_close, /* close */ + hif_read, /* read */ + hif_write, /* write */ + hif_seek, /* seek */ + hif_ioctl, /* ioctl */ + hif_poll, /* poll */ + hif_unlink /* unlink */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int hif_sendmsg(uint8_t id, void *arg) +{ + struct cxd56_hifdrv_s *drv = &g_hifdrv; + iccmsg_t msg; + int ret; + + /* Check parameters */ + + DEBUGASSERT((HIF_I2C_INIT <= id) && (id <= HIF_WRITE_DEVICE)); + DEBUGASSERT(arg); + + /* Send any message to system CPU */ + + msg.cpuid = 0; + msg.msgid = id; + msg.protodata = id; + msg.data = (uint32_t)arg; + + ret = cxd56_iccsend(CXD56_PROTO_HOSTIF, &msg, HIF_TIMEOUT); + if (ret < 0) + { + hiferr("ERROR: Send message (%d)\n", ret); + return ret; + } + + /* Wait for reply message from system CPU */ + + nxsem_wait_uninterruptible(&drv->sync); + + /* Get the error code returned from system cpu */ + + ret = drv->errcode; + + return ret; +} + +static int hif_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct cxd56_hifdev_s *priv; + + DEBUGASSERT(filep && filep->f_inode); + inode = filep->f_inode; + + priv = (FAR struct cxd56_hifdev_s *)inode->i_private; + DEBUGASSERT(priv); + + /* Check parameters */ + + if ((filep->f_oflags & O_WRONLY) != 0 && + (filep->f_oflags & O_RDONLY) != 0) + { + return -EACCES; + } + + if ((filep->f_oflags & O_RDONLY) && + ((priv->flags & HOSTIF_BUFF_ATTR_READ) == 0)) + { + return -EINVAL; + } + + if ((filep->f_oflags & O_WRONLY) && + ((priv->flags & HOSTIF_BUFF_ATTR_READ) != 0)) + { + return -EINVAL; + } + + /* Increment reference counter */ + + nxsem_wait_uninterruptible(&priv->exclsem); + + priv->crefs++; + DEBUGASSERT(priv->crefs > 0); + + if (priv->crefs > 1) + { + nxsem_post(&priv->exclsem); + return OK; + } + + /* Check if non-blocking mode */ + + if (filep->f_oflags & O_NONBLOCK) + { + priv->flags |= O_NONBLOCK; + } + + nxsem_post(&priv->exclsem); + + return OK; +} + +static int hif_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct cxd56_hifdev_s *priv; + + DEBUGASSERT(filep && filep->f_inode); + inode = filep->f_inode; + + priv = (FAR struct cxd56_hifdev_s *)inode->i_private; + DEBUGASSERT(priv); + + /* Decrement reference counter */ + + nxsem_wait_uninterruptible(&priv->exclsem); + + DEBUGASSERT(priv->crefs > 0); + priv->crefs--; + + nxsem_post(&priv->exclsem); + + return OK; +} + +static off_t hif_seek(FAR struct file *filep, off_t offset, int whence) +{ + return OK; +} + +static ssize_t hif_read(FAR struct file *filep, FAR char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct cxd56_hifdev_s *priv; + int ret; + + DEBUGASSERT(filep && filep->f_inode); + inode = filep->f_inode; + + priv = (FAR struct cxd56_hifdev_s *)inode->i_private; + DEBUGASSERT(priv); + + /* Check parameters */ + + DEBUGASSERT(buffer); + + if ((filep->f_oflags & O_RDONLY) == 0) + { + return -EACCES; + } + + /* Receive data from host */ + + priv->buffer = buffer; + priv->len = len; + + ret = hif_sendmsg(HIF_READ_DEVICE, priv); + + return ret; +} + +static ssize_t hif_write(FAR struct file *filep, + FAR const char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct cxd56_hifdev_s *priv; + int ret; + + DEBUGASSERT(filep && filep->f_inode); + inode = filep->f_inode; + + priv = (FAR struct cxd56_hifdev_s *)inode->i_private; + DEBUGASSERT(priv); + + /* Check parameters */ + + DEBUGASSERT(buffer); + + if ((filep->f_oflags & O_WRONLY) == 0) + { + return -EACCES; + } + + /* Send data to host */ + + priv->buffer = buffer; + priv->len = len; + + ret = hif_sendmsg(HIF_WRITE_DEVICE, priv); + + return ret; +} + +static int hif_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + return OK; +} + +static int hif_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup) +{ + return OK; +} + +static int hif_unlink(FAR struct inode *inode) +{ + return OK; +} + +static int hif_rxhandler(int cpuid, int protoid, + uint32_t pdata, uint32_t data, + FAR void *userdata) +{ + struct cxd56_hifdrv_s *drv = &g_hifdrv; + + DEBUGASSERT(cpuid == 0); + DEBUGASSERT(protoid == CXD56_PROTO_HOSTIF); + + drv->errcode = (int)data; + + nxsem_post(&drv->sync); + + return OK; +} + +static int hif_initialize(struct hostif_buff_s *buffer) +{ + struct cxd56_hifdrv_s *drv = &g_hifdrv; + struct cxd56_hifdev_s *priv; + char devpath[16]; + int num; + int ret; + + /* Check parameters */ + + DEBUGASSERT(buffer); + + memset(drv, 0, sizeof(struct cxd56_hifdrv_s)); + + /* Get the number of devices */ + + for (num = 0; num < MAX_BUFFER_NUM; num++) + { + if (buffer[num].size == 0) + { + break; + } + } + + /* Setup driver structure */ + + drv->dev = + (struct cxd56_hifdev_s *)kmm_malloc(sizeof(struct cxd56_hifdev_s) * num); + if (drv->dev == NULL) + { + hiferr("ERROR: hostif allocation failed\n"); + + return -ENOMEM; + } + + drv->ndev = num; + + /* Setup each device structure */ + + for (num = 0; num < drv->ndev; num++) + { + priv = &drv->dev[num]; + + priv->id = num; + priv->flags = buffer[num].flag; + snprintf(devpath, sizeof(devpath), "/dev/hostif%c%d", + (priv->flags & HOSTIF_BUFF_ATTR_READ) ? 'r' : 'w', num); + + ret = register_driver(devpath, &g_hif_fops, 0666, priv); + if (ret < 0) + { + hiferr("ERROR: Failed to register %s (%d)\n", devpath, ret); + kmm_free(drv->dev); + return ret; + } + + nxsem_init(&priv->exclsem, 0, 1); + priv->crefs = 0; + } + + /* Enable hostif clock */ + + ret = cxd56_hostif_clock_enable(); + if (ret < 0) + { + hiferr("ERROR: Enable clock (%d)\n", ret); + kmm_free(drv->dev); + return ret; + } + + /* Initialize communication with system CPU */ + + cxd56_iccinit(CXD56_PROTO_HOSTIF); + + nxsem_init(&drv->sync, 0, 0); + nxsem_set_protocol(&drv->sync, SEM_PRIO_NONE); + + ret = cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL); + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hostif_i2cinitialize + * + * Description: + * Initialize the host interface for I2C slave + * + * Input Parameter: + * config - pointer to I2C buffer configuration + * + * Returned Value: + * Return 0 on success. Otherwise, return a negated errno. + * + ****************************************************************************/ + +int hostif_i2cinitialize(struct hostif_i2cconf_s *config) +{ + int ret; + + DEBUGASSERT(config); + + /* Initialize common driver */ + + ret = hif_initialize(config->buff); + if (ret < 0) + { + hiferr("ERROR: Failed to initialize (%d)\n", ret); + return ret; + } + + /* Initialize I2C driver */ + + ret = hif_sendmsg(HIF_I2C_INIT, config); + if (ret < 0) + { + hiferr("ERROR: Initialize I2C (%d)\n", ret); + return ret; + } + + /* Enable hostif sequencer clock */ + + ret = cxd56_hostseq_clock_enable(); + if (ret < 0) + { + hiferr("ERROR: Enable sequencer clock (%d)\n", ret); + return ret; + } + + /* Pin setting */ + + CXD56_PIN_CONFIGS(PINCONFS_SPI2A_I2C3); + + return OK; +} + +/**************************************************************************** + * Name: hostif_spiinitialize + * + * Description: + * Initialize the host interface for SPI slave + * + * Input Parameter: + * config - pointer to SPI buffer configuration + * + * Returned Value: + * Return 0 on success. Otherwise, return a negated errno. + * + ****************************************************************************/ + +int hostif_spiinitialize(struct hostif_spiconf_s *config) +{ + int ret; + + DEBUGASSERT(config); + + /* Initialize common driver */ + + ret = hif_initialize(config->buff); + if (ret < 0) + { + hiferr("ERROR: Failed to initialize (%d)\n", ret); + return ret; + } + + /* Initialize SPI driver */ + + ret = hif_sendmsg(HIF_SPI_INIT, config); + if (ret < 0) + { + hiferr("ERROR: Initialize SPI (%d)\n", ret); + return ret; + } + + /* Enable hostif sequencer clock */ + + ret = cxd56_hostseq_clock_enable(); + if (ret < 0) + { + hiferr("ERROR: Enable sequencer clock (%d)\n", ret); + return ret; + } + + /* Pin setting */ + + CXD56_PIN_CONFIGS(PINCONFS_SPI2); + + return OK; +} + +/**************************************************************************** + * Name: hostif_uninitialize + * + * Description: + * Uninitialize the host interface + * + * Returned Value: + * Return 0 on success. Otherwise, return a negated errno. + * + ****************************************************************************/ + +int hostif_uninitialize(void) +{ + struct cxd56_hifdrv_s *drv = &g_hifdrv; + struct cxd56_hifdev_s *priv; + char devpath[16]; + int num; + + for (num = 0; num < drv->ndev; num++) + { + priv = &drv->dev[num]; + + snprintf(devpath, sizeof(devpath), "/dev/hostif%c%d", + (priv->flags & HOSTIF_BUFF_ATTR_READ) ? 'r' : 'w', num); + unregister_driver(devpath); + } + + if (drv->dev) + { + kmm_free(drv->dev); + } + + return OK; +} diff --git a/arch/arm/src/cxd56xx/cxd56_i2c.c b/arch/arm/src/cxd56xx/cxd56_i2c.c index 5b0d29aff45..c206a382b76 100644 --- a/arch/arm/src/cxd56xx/cxd56_i2c.c +++ b/arch/arm/src/cxd56xx/cxd56_i2c.c @@ -846,9 +846,6 @@ static int cxd56_i2c_transfer_scu(FAR struct i2c_master_s *dev, cxd56_i2c_clock_gate_disable(priv->port); cxd56_i2c_disable(priv); cxd56_i2c_setfrequency(priv, msgs->frequency); - i2c_reg_rmw(priv, CXD56_IC_CON, IC_RESTART_EN, IC_RESTART_EN); - i2c_reg_write(priv, CXD56_IC_TAR, msgs->addr & 0x7f); - cxd56_i2c_enable(priv); cxd56_i2c_clock_gate_enable(priv->port); priv->frequency = msgs->frequency; @@ -1028,7 +1025,9 @@ struct i2c_master_s *cxd56_i2cbus_initialize(int port) i2c_reg_write(priv, CXD56_IC_SDA_HOLD, 1); i2c_reg_write(priv, CXD56_IC_CON, - (IC_SLAVE_DISABLE | IC_MASTER_MODE | IC_TX_EMPTY_CTRL)); + (IC_RX_FIFO_FULL_HLD_CTRL | IC_RESTART_EN | + IC_SLAVE_DISABLE | IC_MASTER_MODE | IC_TX_EMPTY_CTRL)); + cxd56_i2c_setfrequency(priv, I2C_DEFAULT_FREQUENCY); leave_critical_section(flags); diff --git a/arch/arm/src/cxd56xx/cxd56_i2c_bitbang.c b/arch/arm/src/cxd56xx/cxd56_i2c_bitbang.c index 372e19e53fb..c0f3b8af1d3 100644 --- a/arch/arm/src/cxd56xx/cxd56_i2c_bitbang.c +++ b/arch/arm/src/cxd56xx/cxd56_i2c_bitbang.c @@ -23,6 +23,9 @@ ****************************************************************************/ #include + +#include + #include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_icc.c b/arch/arm/src/cxd56xx/cxd56_icc.c index 66c8c1c81ab..6c714035245 100644 --- a/arch/arm/src/cxd56xx/cxd56_icc.c +++ b/arch/arm/src/cxd56xx/cxd56_icc.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -239,7 +240,6 @@ static int icc_irqhandler(int cpuid, uint32_t word[2]) * process. */ -#ifndef CONFIG_DISABLE_SIGNAL if (priv->pid != INVALID_PROCESS_ID) { union sigval value; @@ -247,7 +247,6 @@ static int icc_irqhandler(int cpuid, uint32_t word[2]) value.sival_ptr = priv->sigdata; nxsig_queue(priv->pid, priv->signo, value); } -#endif return OK; } diff --git a/arch/arm/src/cxd56xx/cxd56_icc.h b/arch/arm/src/cxd56xx/cxd56_icc.h index a27774968bb..59d9ed07370 100644 --- a/arch/arm/src/cxd56xx/cxd56_icc.h +++ b/arch/arm/src/cxd56xx/cxd56_icc.h @@ -32,6 +32,7 @@ #define CXD56_PROTO_HOTSLEEP 8 #define CXD56_PROTO_IMAGE 9 #define CXD56_PROTO_PM 10 /* Power manager */ +#define CXD56_PROTO_HOSTIF 11 #define CXD56_PROTO_SYSCTL 12 #define CXD56_PROTO_GNSS 13 #define CXD56_PROTO_SIG 15 /* Inter-CPU Comm signal */ diff --git a/arch/arm/src/cxd56xx/cxd56_idle.c b/arch/arm/src/cxd56xx/cxd56_idle.c index 41f21f7a2af..8ca9b307295 100644 --- a/arch/arm/src/cxd56xx/cxd56_idle.c +++ b/arch/arm/src/cxd56xx/cxd56_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index 7e03f435e6d..4b9cfa7227f 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_pmic.c b/arch/arm/src/cxd56xx/cxd56_pmic.c index 54f5f03e662..d6d1d833c47 100644 --- a/arch/arm/src/cxd56xx/cxd56_pmic.c +++ b/arch/arm/src/cxd56xx/cxd56_pmic.c @@ -246,7 +246,7 @@ static int pmic_int_handler(int irq, void *context, void *arg) ret = work_queue(LPWORK, &g_irqwork, pmic_int_worker, NULL, 0); if (ret < 0) { - logerr("ERROR: work_queue failed: %d\n", ret); + _err("ERROR: work_queue failed: %d\n", ret); } /* Disable any further pmic interrupts */ diff --git a/arch/arm/src/cxd56xx/cxd56_powermgr.c b/arch/arm/src/cxd56xx/cxd56_powermgr.c index 489216a867b..2c71c4a4123 100644 --- a/arch/arm/src/cxd56xx/cxd56_powermgr.c +++ b/arch/arm/src/cxd56xx/cxd56_powermgr.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -83,14 +84,22 @@ #define PM_CPUFREQLOCK_FLAG_INITIALIZED (0x8000) -#ifdef CONFIG_CXD56_PM_DEBUG -# define pmerr(format, ...) _err(format, ##__VA_ARGS__) -# define pmwarn(format, ...) _warn(format, ##__VA_ARGS__) -# define pminfo(format, ...) _info(format, ##__VA_ARGS__) +/* Debug */ + +#ifdef CONFIG_CXD56_PM_DEBUG_ERROR +# define pmerr(format, ...) _err(format, ##__VA_ARGS__) #else -# define pmerr(x...) -# define pmwarn(x...) -# define pminfo(x...) +# define pmerr(x, ...) +#endif +#ifdef CONFIG_CXD56_PM_DEBUG_WARN +# define pmwarn(format, ...) _warn(format, ##__VA_ARGS__) +#else +# define pmwarn(x, ...) +#endif +#ifdef CONFIG_CXD56_PM_DEBUG_INFO +# define pminfo(format, ...) _info(format, ##__VA_ARGS__) +#else +# define pminfo(x, ...) #endif void up_cpuctxload(void); @@ -577,6 +586,13 @@ void up_pm_acquire_freqlock(struct pm_cpu_freqlock_s *lock) cxd56_pm_semtake(&g_freqlock); + if (lock->flag == PM_CPUFREQLOCK_FLAG_HOLD) + { + /* Return with holding the current frequency */ + + return; + } + for (entry = sq_peek(&g_freqlockqueue); entry; entry = sq_next(entry)) { if (entry == (struct sq_entry_s *)lock) @@ -616,6 +632,13 @@ void up_pm_release_freqlock(struct pm_cpu_freqlock_s *lock) DEBUGASSERT(lock); + if (lock->flag == PM_CPUFREQLOCK_FLAG_HOLD) + { + /* Release holding the current frequency */ + + goto exit; + } + up_pm_acquire_wakelock(&g_wlock); cxd56_pm_semtake(&g_freqlock); @@ -634,6 +657,7 @@ void up_pm_release_freqlock(struct pm_cpu_freqlock_s *lock) } } +exit: nxsem_post(&g_freqlock); up_pm_release_wakelock(&g_wlock); diff --git a/arch/arm/src/cxd56xx/cxd56_powermgr_procfs.c b/arch/arm/src/cxd56xx/cxd56_powermgr_procfs.c index e6af13249dd..6f5549a97e8 100644 --- a/arch/arm/src/cxd56xx/cxd56_powermgr_procfs.c +++ b/arch/arm/src/cxd56xx/cxd56_powermgr_procfs.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -45,14 +46,22 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_CXD56_PM_DEBUG -# define pmerr(format, ...) _err(format, ##__VA_ARGS__) -# define pmwarn(format, ...) _warn(format, ##__VA_ARGS__) -# define pminfo(format, ...) _info(format, ##__VA_ARGS__) +/* Debug */ + +#ifdef CONFIG_CXD56_PM_DEBUG_ERROR +# define pmerr(format, ...) _err(format, ##__VA_ARGS__) #else -# define pmerr(x...) -# define pmwarn(x...) -# define pminfo(x...) +# define pmerr(x, ...) +#endif +#ifdef CONFIG_CXD56_PM_DEBUG_WARN +# define pmwarn(format, ...) _warn(format, ##__VA_ARGS__) +#else +# define pmwarn(x, ...) +#endif +#ifdef CONFIG_CXD56_PM_DEBUG_INFO +# define pminfo(format, ...) _info(format, ##__VA_ARGS__) +#else +# define pminfo(x, ...) #endif #define PWD_STAT(val, shift) ((val >> shift) & 0x1) @@ -279,21 +288,21 @@ static void cxd56_powermgr_procfs_clock(void) len = snprintf(g_powermg_procfs_buffer + g_powermg_procfs_len, g_powermg_procfs_size - g_powermg_procfs_len, "Clock Status [Hz]\n" - " |-RTC : %9d"" |-APP : %9d\n" - " |-RCOSC : %9d"" ||-DSP0 : %9d\n" - " |-XOSC : %9d"" ||-DSP1 : %9d\n" - " |-SYSPLL : %9d"" ||-DSP2 : %9d\n" - " |-M0P : %9d"" ||-DSP3 : %9d\n" - " ||-AHB : %9d"" ||-DSP4 : %9d\n" - " | |-APB : %9d"" ||-DSP5 : %9d\n" - " |-UART1 : %9d"" ||-UART2 : %9d\n" - " |-SFC : %9d"" ||-SPI4 : %9d\n" - " |-SCU : %9d"" ||-SPI5 : %9d\n" - " ||-LPADC : %9d"" ||-USB : %9d\n" - " ||-HPADC : %9d"" ||-EMMC : %9d\n" - " |-I2C4 : %9d"" ||-SDIO : %9d\n" - " |-GPS : %9d"" ||-VSYNC : %9d\n" - " ||-AHB : %9d\n", + " |-RTC : %9ld"" |-APP : %9ld\n" + " |-RCOSC : %9ld"" ||-DSP0 : %9ld\n" + " |-XOSC : %9ld"" ||-DSP1 : %9ld\n" + " |-SYSPLL : %9ld"" ||-DSP2 : %9ld\n" + " |-M0P : %9ld"" ||-DSP3 : %9ld\n" + " ||-AHB : %9ld"" ||-DSP4 : %9ld\n" + " | |-APB : %9ld"" ||-DSP5 : %9ld\n" + " |-UART1 : %9ld"" ||-UART2 : %9ld\n" + " |-SFC : %9ld"" ||-SPI4 : %9ld\n" + " |-SCU : %9ld"" ||-SPI5 : %9ld\n" + " ||-LPADC : %9ld"" ||-USB : %9ld\n" + " ||-HPADC : %9ld"" ||-EMMC : %9ld\n" + " |-I2C4 : %9ld"" ||-SDIO : %9ld\n" + " |-GPS : %9ld"" ||-VSYNC : %9ld\n" + " ||-AHB : %9ld\n", cxd56_get_rtc_clock(), cxd56_get_appsmp_baseclock(), cxd56_get_rcosc_clock(), dsptabl[0], cxd56_get_xosc_clock(), dsptabl[1], diff --git a/arch/arm/src/cxd56xx/cxd56_rtc.c b/arch/arm/src/cxd56xx/cxd56_rtc.c index 520d065b1d9..48ca51aee69 100644 --- a/arch/arm/src/cxd56xx/cxd56_rtc.c +++ b/arch/arm/src/cxd56xx/cxd56_rtc.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include #include @@ -543,6 +545,7 @@ int cxd56_rtc_setalarm(FAR struct alm_setalarm_s *alminfo) int ret = -EBUSY; int id; uint64_t count; + uint32_t mask; ASSERT(alminfo != NULL); DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id); @@ -566,6 +569,13 @@ int cxd56_rtc_setalarm(FAR struct alm_setalarm_s *alminfo) count -= g_rtc_save->offset; + /* clear previsous setting */ + + mask = RTCREG_ALM0_ERR_FLAG_MASK | RTCREG_ALM0_FLAG_MASK; + mask <<= id; + + putreg32(mask, CXD56_RTC0_ALMCLR); + /* wait until previous alarm request is completed */ while (RTCREG_ASET_BUSY_MASK & getreg32(CXD56_RTC0_SETALMPRECNT(id))); @@ -610,10 +620,11 @@ int cxd56_rtc_cancelalarm(enum alm_id_e alarmid) FAR struct alm_cbinfo_s *cbinfo; irqstate_t flags; int ret = -ENODATA; + uint32_t mask; DEBUGASSERT(RTC_ALARM_LAST > alarmid); - /* Set the alarm in hardware and enable interrupts */ + /* Cancel the alarm in hardware and clear interrupts */ cbinfo = &g_alarmcb[alarmid]; @@ -629,6 +640,31 @@ int cxd56_rtc_cancelalarm(enum alm_id_e alarmid) putreg32(0, CXD56_RTC0_ALMOUTEN(alarmid)); + while (RTCREG_ALM_BUSY_MASK & getreg32(CXD56_RTC0_ALMOUTEN(alarmid))); + + /* wait until previous alarm request is completed */ + + while (RTCREG_ASET_BUSY_MASK & + getreg32(CXD56_RTC0_SETALMPRECNT(alarmid))); + + /* clear the alarm counter */ + + putreg32(0, CXD56_RTC0_SETALMPOSTCNT(alarmid)); + putreg32(0, CXD56_RTC0_SETALMPRECNT(alarmid)); + + while (RTCREG_ASET_BUSY_MASK & + getreg32(CXD56_RTC0_SETALMPRECNT(alarmid))); + + /* wait until the interrupt flag is clear */ + + mask = RTCREG_ALM0_ERR_FLAG_MASK | RTCREG_ALM0_FLAG_MASK; + mask <<= alarmid; + + while (mask & getreg32(CXD56_RTC0_ALMFLG)) + { + putreg32(mask, CXD56_RTC0_ALMCLR); + } + spin_unlock_irqrestore(NULL, flags); ret = OK; diff --git a/arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c b/arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c index cf37e35c37d..20df0d7a7b4 100644 --- a/arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c +++ b/arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_scu.c b/arch/arm/src/cxd56xx/cxd56_scu.c index 88d25afceb7..12f4e3a38bd 100644 --- a/arch/arm/src/cxd56xx/cxd56_scu.c +++ b/arch/arm/src/cxd56xx/cxd56_scu.c @@ -28,10 +28,12 @@ #include #include +#include #include #include #include #include +#include #include #include @@ -196,10 +198,10 @@ struct cxd56_scudev_s uint8_t oneshot; /* Bitmap for Oneshots */ sem_t oneshotwait[3]; /* Semaphore for wait oneshot sequence is done */ -#ifndef CONFIG_DISABLE_SIGNAL + int oneshoterr[3]; /* error code for oneshot sequencer */ + struct ev_notify_s event[3]; /* MATHFUNC event notify */ struct wm_notify_s wm[14]; /* Watermark notify */ -#endif int currentreq; }; @@ -274,7 +276,6 @@ static void seq_setdecimation(int wid, uint8_t ratio, uint8_t leveladj, uint8_t forcethrough); static int seq_setwatermark(FAR struct seq_s *seq, int fifoid, FAR struct scufifo_wm_s *wm); -#ifndef CONFIG_DISABLE_SIGNAL static void convert_firsttimestamp(struct scutimestamp_s *tm, uint16_t interval, uint16_t sample, uint16_t adjust); @@ -282,7 +283,6 @@ static void latest_timestamp(struct scufifo_s *fifo, uint32_t interval, struct scutimestamp_s *tm, uint16_t *samples); static void seq_gettimestamp(struct scufifo_s *fifo, struct scutimestamp_s *tm); -#endif static int seq_oneshot(int bustype, int slave, FAR uint16_t *inst, uint32_t nr_insts, FAR uint8_t *buffer, int len); @@ -1069,6 +1069,7 @@ static int seq_oneshot(int bustype, int slave, FAR uint16_t *inst, putreg32(1 << (tid + 24), SCU_INT_ENABLE_MAIN); scuinfo("Sequencer start.\n"); + priv->oneshoterr[tid] = 0; /* Start sequencer as one shot mode */ @@ -1085,7 +1086,11 @@ static int seq_oneshot(int bustype, int slave, FAR uint16_t *inst, scuinfo("Sequencer done.\n"); - if (buffer) + if (priv->oneshoterr[tid] < 0) + { + ret = ERROR; + } + else { /* Copy sequencer output results to user buffer. * XXX: Sequencer output RAM offset is differ from document. @@ -1478,10 +1483,8 @@ static void seq_handlefifointr(FAR struct cxd56_scudev_s *priv, { uint32_t bit; int i; -#ifndef CONFIG_DISABLE_SIGNAL struct wm_notify_s *notify; union sigval value; -#endif if ((intr & 0x007ffe00) == 0) { @@ -1498,7 +1501,6 @@ static void seq_handlefifointr(FAR struct cxd56_scudev_s *priv, putreg32(bit, SCU_INT_CLEAR_MAIN); -#ifndef CONFIG_DISABLE_SIGNAL notify = &priv->wm[i]; if (notify->ts) @@ -1510,7 +1512,6 @@ static void seq_handlefifointr(FAR struct cxd56_scudev_s *priv, value.sival_ptr = notify->ts; nxsig_queue(notify->pid, notify->signo, value); -#endif } } } @@ -1530,10 +1531,8 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv, uint32_t bit; uint32_t rise; uint32_t fall; -#ifndef CONFIG_DISABLE_SIGNAL struct ev_notify_s *notify; int detected = 0; -#endif rise = (intr >> 6) & 0x7; fall = (intr >> 28) & 0x7; @@ -1545,16 +1544,14 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv, for (i = 0, bit = 1; i < 3; i++, bit <<= 1) { -#ifndef CONFIG_DISABLE_SIGNAL notify = &priv->event[i]; -#endif + /* Detect rise event */ if (rise & bit) { putreg32(bit << 6, SCU_INT_CLEAR_MAIN); -#ifndef CONFIG_DISABLE_SIGNAL /* Get rise event occurred timestamp */ if (notify->arg) @@ -1567,7 +1564,6 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv, } detected = 1; -#endif } /* Detect fall event */ @@ -1576,7 +1572,6 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv, { putreg32(bit << 28, SCU_INT_CLEAR_MAIN); -#ifndef CONFIG_DISABLE_SIGNAL /* Get fall event occurred timestamp */ if (notify->arg) @@ -1589,10 +1584,8 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv, } detected = 1; -#endif } -#ifndef CONFIG_DISABLE_SIGNAL if (detected) { union sigval value; @@ -1603,7 +1596,6 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv, nxsig_queue(notify->pid, notify->signo, value); detected = 0; } -#endif } } @@ -1677,6 +1669,8 @@ static int seq_scuirqhandler(int irq, FAR void *context, FAR void *arg) uint32_t ierr0; uint32_t ierr1; uint32_t ierr2; + uint32_t out; + int tid; int i; intr = getreg32(SCU_INT_MASKED_STT_MAIN); @@ -1696,7 +1690,7 @@ static int seq_scuirqhandler(int irq, FAR void *context, FAR void *arg) if (ierr0 != 0) { - scuerr("err0: %08x\n", ierr0); + scuerr("err0: %08" PRIx32 "\n", ierr0); ierr0 = (ierr0 >> 9) & 0x3fff; for (i = 0; i < 14; i++) { @@ -1718,7 +1712,7 @@ static int seq_scuirqhandler(int irq, FAR void *context, FAR void *arg) if (ierr1 != 0) { - scuerr("err1: %08x\n", ierr1); + scuerr("err1: %08" PRIx32 "\n", ierr1); ierr1 = (ierr1 >> 9) & 0x3fff; for (i = 0; i < 14; i++) { @@ -1736,17 +1730,31 @@ static int seq_scuirqhandler(int irq, FAR void *context, FAR void *arg) if (ierr2 != 0) { - scuerr("err2: %08x\n", ierr2); - ierr2 &= 0x03ff; + scuerr("err2: %08" PRIx32 "\n", ierr2); + for (i = 0; i < 10; i++) { - if (ierr2 & (1 << i)) + if (ierr2 & (0x00010001 << i)) { seq_stopseq(i); + + /* Get sequencer output selector */ + + out = (getreg32(SCUSEQ_PROPERTY(i)) >> 12) & 0x3; + + if (0 < out) + { + /* Set error code to oneshot sequencer id */ + + tid = out - 1; + + priv->oneshoterr[tid] = -EIO; + seq_semgive(&priv->oneshotwait[tid]); + } } } - putreg32(0x03ff, SCU_INT_CLEAR_ERR_2); + putreg32(ierr2, SCU_INT_CLEAR_ERR_2); } return 0; @@ -2232,9 +2240,7 @@ static int seq_seteventnotifier(FAR struct scufifo_s *fifo, int riseint; int fallint; int mid; -#ifndef CONFIG_DISABLE_SIGNAL irqstate_t flags; -#endif DEBUGASSERT(fifo && ev); @@ -2247,7 +2253,6 @@ static int seq_seteventnotifier(FAR struct scufifo_s *fifo, mid = fifo->mid; -#ifndef CONFIG_DISABLE_SIGNAL /* Save signal number and target PID */ flags = enter_critical_section(); @@ -2256,7 +2261,6 @@ static int seq_seteventnotifier(FAR struct scufifo_s *fifo, priv->event[mid].arg = ev->arg; priv->event[mid].fifo = fifo; leave_critical_section(flags); -#endif thresh = count0 = count1 = delaysample = 0; riseint = fallint = 0; @@ -2306,8 +2310,6 @@ static int seq_seteventnotifier(FAR struct scufifo_s *fifo, return OK; } -#ifndef CONFIG_DISABLE_SIGNAL - /**************************************************************************** * Name: seq_setwatermark * @@ -2481,9 +2483,6 @@ static void seq_gettimestamp(struct scufifo_s *fifo, convert_firsttimestamp(tm, interval, sample, adjust); } -#else -#define seq_setwatermark(seq, fifoid, wm) (-ENOSYS) -#endif /**************************************************************************** * Name: seq_setfifomode @@ -2498,22 +2497,16 @@ static void seq_setfifomode(FAR struct seq_s *seq, int fifoid, int enable) FAR struct scufifo_s *fifo = seq_getfifo(seq, fifoid); uint32_t val; irqstate_t flags; -#ifndef CONFIG_DISABLE_SIGNAL FAR struct cxd56_scudev_s *priv = &g_scudev; FAR struct wm_notify_s *notify = &priv->wm[fifo->rid]; bool iswtmk = false; -#endif - - DEBUGASSERT(fifo); scuinfo("FIFO mode %d wid %d\n", enable, fifo->wid); -#ifndef CONFIG_DISABLE_SIGNAL if (notify->ts) { iswtmk = true; } -#endif flags = enter_critical_section(); @@ -2535,15 +2528,12 @@ static void seq_setfifomode(FAR struct seq_s *seq, int fifoid, int enable) val = 0x1 << (fifo->rid + 9); putreg32(val, SCU_INT_DISABLE_ERR_0); -#ifndef CONFIG_DISABLE_SIGNAL - /* disable almostfull interrupt */ if (iswtmk) { putreg32(val, SCU_INT_DISABLE_MAIN); } -#endif } else { @@ -2557,8 +2547,6 @@ static void seq_setfifomode(FAR struct seq_s *seq, int fifoid, int enable) val = 0x1 << (fifo->rid + 9); putreg32(val, SCU_INT_ENABLE_ERR_0); -#ifndef CONFIG_DISABLE_SIGNAL - /* enable almostfull interrupt */ if (iswtmk) @@ -2566,7 +2554,6 @@ static void seq_setfifomode(FAR struct seq_s *seq, int fifoid, int enable) val = 0x1 << (fifo->rid + 9); putreg32(val, SCU_INT_ENABLE_MAIN); } -#endif } leave_critical_section(flags); @@ -2996,7 +2983,7 @@ int seq_read(FAR struct seq_s *seq, int fifoid, FAR char *buffer, int length) scuinfo("Available %d samples\n", avail); #ifdef CONFIG_CXD56_SCU_DEBUG status = getreg32(SCUFIFO_R_STATUS1(fifo->rid)); - scuinfo("Status: %08x\n", status); + scuinfo("Status: %08" PRIx32 "\n", status); #endif avail *= seq->sample; length = MIN(avail, length); @@ -3148,7 +3135,7 @@ int seq_ioctl(FAR struct seq_s *seq, int fifoid, int cmd, unsigned long arg) return -EINVAL; } - scuinfo("cmd = %04x, arg = %08x\n", cmd, arg); + scuinfo("cmd = %04x, arg = %08" PRIx32 "\n", cmd, arg); switch (cmd) { @@ -3498,7 +3485,11 @@ void scu_initialize(void) /* Enable error interrupt */ putreg32(0x007ffe00, SCU_INT_ENABLE_ERR_0); - putreg32(0x03ff, SCU_INT_ENABLE_ERR_2); + putreg32(0x03ff03ff, SCU_INT_ENABLE_ERR_2); + + /* Set the number of TxAbort repeat times */ + + putreg32(5, SCUSEQ_REPEAT_TXABORT); /* Enable SCU IRQ */ diff --git a/arch/arm/src/cxd56xx/cxd56_sdhci.c b/arch/arm/src/cxd56xx/cxd56_sdhci.c index fcb9746bc56..c736c3d43e9 100644 --- a/arch/arm/src/cxd56xx/cxd56_sdhci.c +++ b/arch/arm/src/cxd56xx/cxd56_sdhci.c @@ -80,7 +80,7 @@ # define CONFIG_CXD56_SDHCI_DMAPRIO DMA_CCR_PRIMED #endif -#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_VERBOSE) +#ifndef CONFIG_DEBUG_MEMCARD_INFO # undef CONFIG_SDIO_XFRDEBUG #endif @@ -667,7 +667,7 @@ static void cxd56_dumpsample(struct cxd56_sdiodev_s *priv, mcinfo(" HTCAPBLT[%08x]: %08x\n", CXD56_SDHCI_HTCAPBLT, regs->htcapblt); mcinfo(" ADMAES[%08x]: %08x\n", CXD56_SDHCI_ADMAES, regs->admaes); mcinfo(" ADSADDR[%08x]: %08x\n", CXD56_SDHCI_ADSADDR, regs->adsaddr); - mcinfo(" VENDSPEC[%08x]: %08x\n", CXD56_SDHCI_VENDSPEC, regs->hostver); + mcinfo(" VENDSPEC[%08x]: %08x\n", CXD56_SDHCI_VENDSPEC, regs->vendspec); } #endif @@ -1059,7 +1059,7 @@ static void cxd56_endtransfer(struct cxd56_sdiodev_s *priv, putreg32(regval, CXD56_SDHCI_SYSCTL); cxd56_sdhci_adma_dscr[0] = 0; cxd56_sdhci_adma_dscr[1] = 0; - putreg32((uint32_t)cxd56_sdhci_adma_dscr, CXD56_SDHCI_ADSADDR); + putreg32(CXD56_PHYSADDR(cxd56_sdhci_adma_dscr), CXD56_SDHCI_ADSADDR); putreg32(0, CXD56_SDHCI_ADSADDR_H); priv->usedma = false; priv->dmasend_prepare = false; @@ -2082,7 +2082,7 @@ static int cxd56_sdio_cancel(FAR struct sdio_dev_s *dev) priv->dmasend_regcmd = 0; cxd56_sdhci_adma_dscr[0] = 0; cxd56_sdhci_adma_dscr[1] = 0; - putreg32((uint32_t)cxd56_sdhci_adma_dscr, CXD56_SDHCI_ADSADDR); + putreg32(CXD56_PHYSADDR(cxd56_sdhci_adma_dscr), CXD56_SDHCI_ADSADDR); putreg32(0, CXD56_SDHCI_ADSADDR_H); #endif regval = getreg32(CXD56_SDHCI_SYSCTL); @@ -2756,12 +2756,12 @@ static int cxd56_sdio_registercallback(FAR struct sdio_dev_s *dev, #ifdef CONFIG_SDIO_DMA static int cxd56_sdio_admasetup(FAR const uint8_t *buffer, size_t buflen) { - uint32_t dscr_top = (uint32_t)cxd56_sdhci_adma_dscr; + uint32_t dscr_top = CXD56_PHYSADDR(cxd56_sdhci_adma_dscr); uint32_t dscr_l; uint32_t i; uint32_t remaining; uint32_t len; - uint32_t data_addr = (uint32_t)buffer; + uint32_t data_addr = CXD56_PHYSADDR(buffer); remaining = buflen; putreg32(0x0, CXD56_SDHCI_ADSADDR_H); @@ -2903,7 +2903,7 @@ static int cxd56_sdio_dmarecvsetup(FAR struct sdio_dev_s *dev, priv->usedma = true; cxd56_configxfrints(priv, SDHCI_DMADONE_INTS); - putreg32((uint32_t)buffer, CXD56_SDHCI_DSADDR); + putreg32(CXD56_PHYSADDR(buffer), CXD56_SDHCI_DSADDR); /* Sample the register state */ @@ -3250,7 +3250,7 @@ FAR struct sdio_dev_s *cxd56_sdhci_initialize(int slotno) cxd56_sdhci_adma_dscr[i] = 0; } - putreg32((uint32_t)cxd56_sdhci_adma_dscr, CXD56_SDHCI_ADSADDR); + putreg32(CXD56_PHYSADDR(cxd56_sdhci_adma_dscr), CXD56_SDHCI_ADSADDR); putreg32(0, CXD56_SDHCI_ADSADDR_H); putreg32(SDHCI_PROCTL_DMAS_ADMA2 | (getreg32(CXD56_SDHCI_PROCTL) & ~SDHCI_PROCTL_DMAS_MASK), diff --git a/arch/arm/src/cxd56xx/cxd56_serial.c b/arch/arm/src/cxd56xx/cxd56_serial.c index 6ef147a04e2..5ece1db4ccb 100644 --- a/arch/arm/src/cxd56xx/cxd56_serial.c +++ b/arch/arm/src/cxd56xx/cxd56_serial.c @@ -460,6 +460,17 @@ static int up_setup(FAR struct uart_dev_s *dev) uint32_t lcr; uint32_t cr; +#ifdef CONFIG_CXD56_SUBCORE + if (priv->id == 1) + { + /* In case of SUBCORE, UART1 has been already initialized, + * then we don't need to do anything. + */ + + return OK; + } +#endif + cxd56_uart_setup(priv->id); /* Init HW */ @@ -851,11 +862,11 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg) #endif priv->baud = cfgetispeed(termiosp); + spin_unlock_irqrestore(&priv->lock, flags); + /* Configure the UART line format and speed. */ up_set_format(dev); - - spin_unlock_irqrestore(&priv->lock, flags); } break; #endif diff --git a/arch/arm/src/cxd56xx/cxd56_sfc.c b/arch/arm/src/cxd56xx/cxd56_sfc.c index 3f4e7f79d9a..2fd185b4289 100644 --- a/arch/arm/src/cxd56xx/cxd56_sfc.c +++ b/arch/arm/src/cxd56xx/cxd56_sfc.c @@ -30,6 +30,7 @@ #include #include #include +#include #include /* Prototypes for Remote API */ diff --git a/arch/arm/src/cxd56xx/cxd56_sph.c b/arch/arm/src/cxd56xx/cxd56_sph.c index d2222ada948..0affeab2cb8 100644 --- a/arch/arm/src/cxd56xx/cxd56_sph.c +++ b/arch/arm/src/cxd56xx/cxd56_sph.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_spi.c b/arch/arm/src/cxd56xx/cxd56_spi.c index 5a648ed21ad..f8fbd12abe7 100644 --- a/arch/arm/src/cxd56xx/cxd56_spi.c +++ b/arch/arm/src/cxd56xx/cxd56_spi.c @@ -28,11 +28,13 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -327,6 +329,11 @@ static struct cxd56_spidev_s g_spi3dev = }; #endif +/* Inhibit clock change */ + +static struct pm_cpu_freqlock_s g_hold_lock = + PM_CPUFREQLOCK_INIT(0, PM_CPUFREQLOCK_FLAG_HOLD); + /**************************************************************************** * Public Data ****************************************************************************/ @@ -503,6 +510,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { FAR struct cxd56_spidev_s *priv = (FAR struct cxd56_spidev_s *)dev; uint32_t regval; + uint32_t cr1val; /* Has the mode changed? */ @@ -545,8 +553,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) return; } + /* Disable SSE */ + + cr1val = spi_getreg(priv, CXD56_SPI_CR1_OFFSET); + spi_putreg(priv, CXD56_SPI_CR1_OFFSET, cr1val & ~SPI_CR1_SSE); + spi_putreg(priv, CXD56_SPI_CR0_OFFSET, regval); + /* Enable SSE after a few microseconds delay */ + + up_udelay(3); + + spi_putreg(priv, CXD56_SPI_CR1_OFFSET, cr1val); + /* Enable clock gating (clock disable) */ cxd56_spi_clock_gate_enable(priv->port); @@ -643,6 +662,10 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) register uint32_t regval; register uint32_t cr1val = 0; + /* Prohibit the clock change during SPI transfer */ + + up_pm_acquire_freqlock(&g_hold_lock); + /* Disable clock gating (clock enable) */ cxd56_spi_clock_gate_disable(priv->port); @@ -683,6 +706,10 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) cxd56_spi_clock_gate_enable(priv->port); + /* Allow the clock change after SPI transfer */ + + up_pm_release_freqlock(&g_hold_lock); + return regval; } @@ -737,6 +764,10 @@ static void spi_do_exchange(FAR struct spi_dev_s *dev, tx.pv = txbuffer; rx.pv = rxbuffer; + /* Prohibit the clock change during SPI transfer */ + + up_pm_acquire_freqlock(&g_hold_lock); + /* Disable clock gating (clock enable) */ cxd56_spi_clock_gate_disable(priv->port); @@ -811,6 +842,10 @@ static void spi_do_exchange(FAR struct spi_dev_s *dev, /* Enable clock gating (clock disable) */ cxd56_spi_clock_gate_enable(priv->port); + + /* Allow the clock change after SPI transfer */ + + up_pm_release_freqlock(&g_hold_lock); } /**************************************************************************** @@ -1350,6 +1385,10 @@ void spi_flush(FAR struct spi_dev_s *dev) FAR struct cxd56_spidev_s *priv = (FAR struct cxd56_spidev_s *)dev; uint32_t regval = 0; + /* Prohibit the clock change during SPI transfer */ + + up_pm_acquire_freqlock(&g_hold_lock); + /* Disable clock gating (clock enable) */ cxd56_spi_clock_gate_disable(priv->port); @@ -1393,6 +1432,10 @@ void spi_flush(FAR struct spi_dev_s *dev) /* Enable clock gating (clock disable) */ cxd56_spi_clock_gate_enable(priv->port); + + /* Allow the clock change after SPI transfer */ + + up_pm_release_freqlock(&g_hold_lock); } #ifdef CONFIG_CXD56_DMAC @@ -1414,6 +1457,10 @@ static void spi_dmaexchange(FAR struct spi_dev_s *dev, DEBUGASSERT(priv && priv->spibase); + /* Prohibit the clock change during SPI transfer */ + + up_pm_acquire_freqlock(&g_hold_lock); + /* Disable clock gating (clock enable) */ cxd56_spi_clock_gate_disable(priv->port); @@ -1450,6 +1497,10 @@ static void spi_dmaexchange(FAR struct spi_dev_s *dev, /* Enable clock gating (clock disable) */ cxd56_spi_clock_gate_enable(priv->port); + + /* Allow the clock change after SPI transfer */ + + up_pm_release_freqlock(&g_hold_lock); } #ifndef CONFIG_SPI_EXCHANGE diff --git a/arch/arm/src/cxd56xx/cxd56_start.c b/arch/arm/src/cxd56xx/cxd56_start.c index 0518be6c92e..b66f2dafe6f 100644 --- a/arch/arm/src/cxd56xx/cxd56_start.c +++ b/arch/arm/src/cxd56xx/cxd56_start.c @@ -75,15 +75,6 @@ void weak_function up_cpuctxload(void); -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__((naked, no_instrument_function, noreturn)); -#endif - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -116,46 +107,6 @@ extern uint32_t _vectors[]; * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -303,7 +254,9 @@ void __start(void) putreg32(0, CXD56_EXCCONF_BASE + 0); +#ifndef CONFIG_CXD56_SUBCORE cxd56_lowsetup(); +#endif showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -327,7 +280,7 @@ void __start(void) /* Perform early serial initialization */ -#ifdef USE_EARLYSERIALINIT +#if defined(USE_EARLYSERIALINIT) && !defined(CONFIG_CXD56_SUBCORE) arm_earlyserialinit(); #endif showprogress('E'); @@ -352,17 +305,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/cxd56xx/cxd56_sysctl.c b/arch/arm/src/cxd56xx/cxd56_sysctl.c index 2c1aec496b6..20da9e57d5f 100644 --- a/arch/arm/src/cxd56xx/cxd56_sysctl.c +++ b/arch/arm/src/cxd56xx/cxd56_sysctl.c @@ -31,6 +31,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_testset.c b/arch/arm/src/cxd56xx/cxd56_testset.c index 5a238ea2f26..ecc6580d7ab 100644 --- a/arch/arm/src/cxd56xx/cxd56_testset.c +++ b/arch/arm/src/cxd56xx/cxd56_testset.c @@ -42,6 +42,36 @@ * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: up_testset2 + ****************************************************************************/ + +spinlock_t up_testset2(volatile FAR spinlock_t *lock) +{ + register uintptr_t ret asm("r0") = (uintptr_t)(lock); + + asm volatile ( + "mov r1, #1 \n" + "1: \n" + "ldrexb r2, [%0] \n" + "cmp r2, r1 \n" + "beq 2f \n" + "strexb r2, r1, [%0] \n" + "cmp r2, r1 \n" + "beq 1b \n" + "dmb \n" + "mov %0, #0 \n" + "bx lr \n" + "2: \n" + "strexb r2, r1, [%0] \n" /* dummy strex to release */ + "mov %0, #1 \n" + : "+r" (ret) + : + : "r1", "r2"); + + return ret; +} + /**************************************************************************** * Name: up_testset * @@ -63,6 +93,7 @@ spinlock_t up_testset(volatile FAR spinlock_t *lock) { +#ifdef CONFIG_CXD56_TESTSET_WITH_HWSEM spinlock_t ret; uint32_t sphlocked = ((up_cpu_index() + 2) << 16) | 0x1; @@ -85,6 +116,9 @@ spinlock_t up_testset(volatile FAR spinlock_t *lock) /* Unlock hardware semaphore */ putreg32(REQ_UNLOCK, CXD56_SPH_REQ(SPH_SMP)); +#else + spinlock_t ret = up_testset2(lock); +#endif return ret; } diff --git a/arch/arm/src/cxd56xx/cxd56_textheap.c b/arch/arm/src/cxd56xx/cxd56_textheap.c new file mode 100644 index 00000000000..95bf571636e --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_textheap.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_textheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SYSBUS_ADDRESS_OFFSET 0x20000000 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_textheap_memalign() + ****************************************************************************/ + +FAR void *up_textheap_memalign(size_t align, size_t size) +{ + FAR void *ret; + ret = (FAR void *)kmm_malloc(size); + +#ifdef CONFIG_CXD56_USE_SYSBUS + if (ret) + { + binfo("** ret=%p \n", ret); + + /* NOTE: + * kmm_malloc() will return the address in SYSBUS. + * So convert the address to I/D BUS. + */ + + ret -= SYSBUS_ADDRESS_OFFSET; + + binfo("** mapped to %p \n", ret); + } +#endif + + return ret; +} + +/**************************************************************************** + * Name: up_textheap_free() + ****************************************************************************/ + +void up_textheap_free(FAR void *p) +{ +#ifdef CONFIG_CXD56_USE_SYSBUS + if (p) + { + binfo("** p=%p \n", p); + + /* NOTE: + * The address p will be in I/D BUS. + * So convert the address to SYSBUS. + */ + + p += SYSBUS_ADDRESS_OFFSET; + + binfo("** mapped to %p \n", p); + } +#endif + + kmm_free(p); +} diff --git a/arch/arm/src/cxd56xx/cxd56_timer.c b/arch/arm/src/cxd56xx/cxd56_timer.c index 803be143d25..e586dce86d7 100644 --- a/arch/arm/src/cxd56xx/cxd56_timer.c +++ b/arch/arm/src/cxd56xx/cxd56_timer.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/cxd56xx/cxd56_uart.c b/arch/arm/src/cxd56xx/cxd56_uart.c index f3cc38fb466..54cc65bbc6f 100644 --- a/arch/arm/src/cxd56xx/cxd56_uart.c +++ b/arch/arm/src/cxd56xx/cxd56_uart.c @@ -206,11 +206,15 @@ static void cxd56_uart_pincontrol(int ch, bool on) static void cxd56_uart_start(int ch) { + irqstate_t flags = enter_critical_section(); + cxd56_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD); putreg32(g_lcr, g_uartdevs[ch].uartbase + CXD56_UART_LCR_H); putreg32(g_cr, g_uartdevs[ch].uartbase + CXD56_UART_CR); + + leave_critical_section(flags); } /**************************************************************************** @@ -226,6 +230,8 @@ static void cxd56_uart_stop(int ch) { uint32_t cr; + irqstate_t flags = enter_critical_section(); + while (UART_FR_BUSY & getreg32(g_uartdevs[ch].uartbase + CXD56_UART_FR)); cr = getreg32(g_uartdevs[ch].uartbase + CXD56_UART_CR); @@ -235,6 +241,8 @@ static void cxd56_uart_stop(int ch) g_lcr = getreg32(g_uartdevs[ch].uartbase + CXD56_UART_LCR_H); putreg32(0, g_uartdevs[ch].uartbase + CXD56_UART_LCR_H); + + leave_critical_section(flags); } /**************************************************************************** diff --git a/arch/arm/src/cxd56xx/cxd56_udmac.c b/arch/arm/src/cxd56xx/cxd56_udmac.c index ac3d3b09704..fa9c7440f22 100644 --- a/arch/arm/src/cxd56xx/cxd56_udmac.c +++ b/arch/arm/src/cxd56xx/cxd56_udmac.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -254,7 +255,7 @@ void cxd56_udmainitialize(void) * will obtain the alternative descriptors. */ - putreg32((uint32_t)g_descriptors, CXD56_DMA_CTRLBASE); + putreg32(CXD56_PHYSADDR(g_descriptors), CXD56_DMA_CTRLBASE); /* Enable the DMA controller */ @@ -441,8 +442,8 @@ void cxd56_rxudmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, /* Configure the primary channel descriptor */ desc = cxd56_get_descriptor(dmach, false); - desc->srcend = (uint32_t *)paddr; - desc->dstend = (uint32_t *)(maddr + nbytes - xfersize); + desc->srcend = paddr; + desc->dstend = CXD56_PHYSADDR(maddr + nbytes - xfersize); /* No source increment, destination increments according to transfer size. * No privileges. Arbitrate after each transfer. Default priority. @@ -538,8 +539,8 @@ void cxd56_txudmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, /* Configure the primary channel descriptor */ desc = cxd56_get_descriptor(dmach, false); - desc->srcend = (uint32_t *)(maddr + nbytes - xfersize); - desc->dstend = (uint32_t *)paddr; + desc->srcend = CXD56_PHYSADDR(maddr + nbytes - xfersize); + desc->dstend = paddr; /* No destination increment, source increments according to transfer size. * No privileges. Arbitrate after each transfer. Default priority. diff --git a/arch/arm/src/cxd56xx/cxd56_usbdev.c b/arch/arm/src/cxd56xx/cxd56_usbdev.c index 8a966368ca7..fb23f3dfbcd 100644 --- a/arch/arm/src/cxd56xx/cxd56_usbdev.c +++ b/arch/arm/src/cxd56xx/cxd56_usbdev.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -755,7 +756,7 @@ static int cxd56_epwrite(FAR struct cxd56_ep_s *privep, FAR uint8_t *buf, return 0; } - desc->buf = (uint32_t)(uintptr_t)buf; + desc->buf = CXD56_PHYSADDR(buf); desc->status = nbytes | DESC_LAST; /* always last descriptor */ /* Set Poll bit to ready to send */ @@ -1042,7 +1043,7 @@ static int cxd56_rdrequest(FAR struct cxd56_ep_s *privep) usbtrace(TRACE_READ(privep->epphy), privep->ep.maxpacket); - desc->buf = (uint32_t)(uintptr_t)privreq->req.buf; + desc->buf = CXD56_PHYSADDR(privreq->req.buf); desc->status = privep->ep.maxpacket | DESC_LAST; /* Ready to receive next packet */ @@ -2023,12 +2024,12 @@ static void cxd56_ep0hwinitialize(FAR struct cxd56_usbdev_s *priv) memset(&g_ep0in, 0, sizeof(g_ep0in)); memset(&g_ep0out, 0, sizeof(g_ep0out)); - g_ep0out.buf = (uint32_t)(uintptr_t)g_ep0outbuffer; + g_ep0out.buf = CXD56_PHYSADDR(g_ep0outbuffer); g_ep0out.status = CXD56_EP0MAXPACKET | DESC_LAST; - putreg32((uint32_t)(uintptr_t)&g_ep0setup, CXD56_USB_OUT_EP_SETUP(0)); - putreg32((uint32_t)(uintptr_t)&g_ep0in, CXD56_USB_IN_EP_DATADESC(0)); - putreg32((uint32_t)(uintptr_t)&g_ep0out, CXD56_USB_OUT_EP_DATADESC(0)); + putreg32(CXD56_PHYSADDR(&g_ep0setup), CXD56_USB_OUT_EP_SETUP(0)); + putreg32(CXD56_PHYSADDR(&g_ep0in), CXD56_USB_IN_EP_DATADESC(0)); + putreg32(CXD56_PHYSADDR(&g_ep0out), CXD56_USB_OUT_EP_DATADESC(0)); /* Clear all interrupts */ @@ -2253,12 +2254,12 @@ static int cxd56_epconfigure(FAR struct usbdev_ep_s *ep, if (privep->in) { - putreg32((uint32_t)(uintptr_t)privep->desc, + putreg32(CXD56_PHYSADDR(privep->desc), CXD56_USB_IN_EP_DATADESC(privep->epphy)); } else { - putreg32((uint32_t)(uintptr_t)privep->desc, + putreg32(CXD56_PHYSADDR(privep->desc), CXD56_USB_OUT_EP_DATADESC(privep->epphy)); } @@ -2629,12 +2630,12 @@ static int cxd56_allocepbuffer(FAR struct cxd56_ep_s *privep) if (privep->in) { - putreg32((uint32_t)(uintptr_t)privep->desc, + putreg32(CXD56_PHYSADDR(privep->desc), CXD56_USB_IN_EP_DATADESC(privep->epphy)); } else { - putreg32((uint32_t)(uintptr_t)privep->desc, + putreg32(CXD56_PHYSADDR(privep->desc), CXD56_USB_OUT_EP_DATADESC(privep->epphy)); } @@ -3339,12 +3340,12 @@ static void cxd56_usbreset(FAR struct cxd56_usbdev_s *priv) if (priv->eplist[i].in) { - putreg32((uint32_t)(uintptr_t)priv->eplist[i].desc, + putreg32(CXD56_PHYSADDR(priv->eplist[i].desc), CXD56_USB_IN_EP_DATADESC(priv->eplist[i].epphy)); } else { - putreg32((uint32_t)(uintptr_t)priv->eplist[i].desc, + putreg32(CXD56_PHYSADDR(priv->eplist[i].desc), CXD56_USB_OUT_EP_DATADESC(priv->eplist[i].epphy)); } diff --git a/arch/arm/src/cxd56xx/cxd56_wdt.c b/arch/arm/src/cxd56xx/cxd56_wdt.c index 301f3238379..014db123fe8 100644 --- a/arch/arm/src/cxd56xx/cxd56_wdt.c +++ b/arch/arm/src/cxd56xx/cxd56_wdt.c @@ -23,13 +23,12 @@ ****************************************************************************/ #include -#ifdef CONFIG_DEBUG_FEATURES -#include -#endif #include #include #include +#include +#include #include #include @@ -172,7 +171,7 @@ static uint32_t cxd56_getreg(uintptr_t regaddr) { if (count == 4) { - logdebug("...\n"); + wdinfo("...\n"); } return regval; @@ -189,7 +188,7 @@ static uint32_t cxd56_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - logdebug("[repeats %d more times]\n", count - 3); + wdinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -201,7 +200,7 @@ static uint32_t cxd56_getreg(uintptr_t regaddr) /* Show the register value read */ - logdebug("%08x->%08\n", regaddr, regval); + wdinfo("%08x->%08\n", regaddr, regval); return regval; } #endif @@ -219,7 +218,7 @@ static void cxd56_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - logdebug("%08x<-%08x\n", regaddr, regval); + wdinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ diff --git a/arch/arm/src/cxd56xx/hardware/cxd5602_isop.h b/arch/arm/src/cxd56xx/hardware/cxd5602_isop.h index de158099d19..28347203da4 100644 --- a/arch/arm/src/cxd56xx/hardware/cxd5602_isop.h +++ b/arch/arm/src/cxd56xx/hardware/cxd5602_isop.h @@ -1,4 +1,4 @@ -/* This file is generated at May 18 2016 16:19:52 */ +/* This file is generated at Dec 14 2020 13:28:30 */ /**************************************************************************** * Public Data @@ -9,442 +9,460 @@ const unsigned long scu_isopprog_array[] = 0xf7f8d600, 0xa2024f86, 0x0001a200, 0x18004081, 0x00008014, 0x00000000, 0x0000a207, 0x00000000, 0x0000a070, 0xac2d4ec6, 0xd000ac27, 0x50a2e444, - 0x70111801, 0x50011c01, 0xf34cd000, 0x0004800a, + 0x70111801, 0x50011c01, 0xf356d000, 0x0004800a, 0x40110114, 0x50031f43, 0x9ff42801, 0x90062911, 0x8fec5043, 0x00140003, 0x40640113, 0x1f344011, - 0x9fe42121, 0xd2005001, 0x5203f356, 0x50155004, + 0x9fe42121, 0xd2005001, 0x5203f360, 0x50155004, 0x04150845, 0x90082905, 0x2d444014, 0x00259ff2, 0x40110115, 0x21311f54, 0xd1009fe4, 0x5ff2e824, 0xe808d400, 0x01f8fc43, 0x07fffc33, 0xe804d000, 0xf000d700, 0x1c431c12, 0xe800d100, 0x1c025013, - 0x0103fc40, 0x0300fc30, 0xf3d8d200, 0x1c135be4, + 0x0103fc40, 0x0300fc30, 0xf3e0d200, 0x1c135be4, 0xe418d100, 0x1c105003, 0xf47250a1, 0x1c230300, 0x0004f721, 0xf7235e61, 0xf7230005, 0xf7230016, 0x00250017, 0x4fc10215, 0xf7531d53, 0xf753fffe, 0x2141ffff, 0xd1009fee, 0xd209f33c, 0xd000ec00, - 0x5004f4b8, 0x1c125005, 0x0304f470, 0x44020002, + 0x5004f4c0, 0x1c125005, 0x0304f470, 0x44020002, 0x0308f472, 0x41a10001, 0x00020053, 0x106350a7, 0x1c240132, 0x0004f727, 0x0005f724, 0x0016f724, 0x0017f724, 0x1d340013, 0xfffef734, 0xfffff734, 0x40434ff7, 0x9ff02907, 0x44014015, 0x9fca2925, - 0xd3005001, 0x5004f340, 0xf398d200, 0x01150035, - 0x1f544011, 0x9ff62941, 0xd4005fe3, 0x5005f344, - 0x00415f67, 0x4fc30231, 0xfffef512, 0x1f154202, - 0x9ff02173, 0xf334d200, 0xf000d100, 0xd4005003, - 0x5005f538, 0x030cf412, 0xac115001, 0xa819ac19, - 0x00470052, 0x00710112, 0x01211032, 0x00201c13, - 0x70407052, 0x1f450104, 0x00740070, 0xf34cd700, - 0x01200157, 0x1e724015, 0xf7131f02, 0xa8110016, - 0x210550a0, 0x9fc44021, 0xf376d000, 0x1000fc11, - 0x00345f02, 0x4ff30005, 0x21231014, 0x1d510245, - 0x50029ff2, 0xf334d000, 0xf000d700, 0xf458d300, - 0x1d025004, 0xf332d000, 0x0310f470, 0x00350041, - 0x01151041, 0x0004f452, 0x0008f454, 0xf7524014, - 0xf752000c, 0x1c52000d, 0x9fe22964, 0xd2005001, - 0x1f21f330, 0x0001f721, 0xf5711d01, 0xf77102fe, - 0xfc4102fc, 0xfc312016, 0xd2160518, 0x1c711951, - 0x0427fc41, 0x9e21fc31, 0x0004f472, 0xe412d200, - 0x0008f471, 0x1f215011, 0x0d86fa00, 0xa82da827, - 0x41465000, 0x0000a070, 0xac3d4e46, 0xf601ac37, - 0x28010005, 0xf6029178, 0xac200004, 0x10110021, - 0xd100ac29, 0xa828f538, 0x10300120, 0x7050ac18, - 0x1e150101, 0xfa000050, 0x00501890, 0x29006fb0, - 0x0050901a, 0xfa004010, 0x00501880, 0xfa004020, - 0x00501878, 0xfa004030, 0xd1001870, 0x5010e000, - 0x08501811, 0x28010401, 0xac15906c, 0x0128fa00, - 0x5003a822, 0xf6205005, 0xa8110004, 0xfa004062, - 0xa8230290, 0xf538d400, 0x91022900, 0x5021a818, - 0xf334d700, 0x1c410104, 0xf6305011, 0x1a720004, - 0x05120801, 0xf6301d72, 0xf7400005, 0x28000016, - 0x500090dc, 0x00320041, 0x01524010, 0xf6220151, - 0xf7120006, 0x00050006, 0x0005f632, 0x24256ff5, - 0x80ba9fe4, 0xd100a822, 0xf620e404, 0x18110004, - 0x28016201, 0xd3009028, 0x6ff0f330, 0x0001f631, - 0x90222101, 0x6ff01e30, 0x901a2910, 0x15f0fa00, - 0x5030a822, 0xf330d100, 0x800a1f10, 0xf330d000, - 0x1f015001, 0x0004f620, 0xf000d100, 0x01011050, - 0x0005f620, 0x0024f213, 0xac1b2800, 0x0024f211, - 0x905a0050, 0xac100015, 0x0562fa00, 0x0053a814, - 0x904a2910, 0x60f31243, 0x61f34013, 0x903e2803, - 0x5002a818, 0x60f05001, 0x0030ac18, 0x00470043, - 0xf418d400, 0x10234011, 0xf2430134, 0x1a440002, - 0x0152a81d, 0x0125a825, 0x0006f652, 0x00741f42, - 0x00031f32, 0x6ff20012, 0x9fd02432, 0xa83da837, - 0xa07041c6, 0xac454e06, 0xd000ac3f, 0xfc41e400, - 0x18000400, 0x28000410, 0x5000915e, 0xfc41ac10, - 0xd0000400, 0xac19e804, 0xd1001c01, 0x1810e080, - 0xe084d100, 0x00021811, 0xf76260f2, 0x00620014, - 0x0014fc02, 0x00040023, 0x13007022, 0x70131284, - 0x1f346034, 0xf5611d20, 0x13010018, 0xe088d000, - 0xf5615012, 0x1c02001a, 0x0014f265, 0x6ff5ac25, - 0xfa000050, 0xa8220498, 0xf418d100, 0x90902910, - 0xd0001025, 0x0017f000, 0xfc411282, 0x01500100, - 0xf0004012, 0x6ff20280, 0x50010410, 0x903a2900, - 0x50000075, 0x28020027, 0xf6629066, 0x00530014, + 0xf34cd200, 0xd3005001, 0x5004f340, 0x0002f721, + 0xf3a0d200, 0x01450035, 0x1f514014, 0x9ff62944, + 0xd4005fe3, 0x5005f344, 0x00415f67, 0x4fc30231, + 0xfffef512, 0x1f154202, 0x9ff02173, 0xf334d200, + 0xf000d100, 0xd4005003, 0x5005f540, 0x030cf412, + 0xac115001, 0xa819ac19, 0x00470052, 0x00710112, + 0x01211032, 0x00201c13, 0x70407052, 0x1f450104, + 0x00740070, 0xf356d700, 0x01200157, 0x1e724015, + 0xf7131f02, 0xa8110016, 0x210550a0, 0x9fc44021, + 0xf380d000, 0x1000fc11, 0x00345f02, 0x4ff30005, + 0x21231014, 0x1d510245, 0x50029ff2, 0xf334d000, + 0xf000d700, 0xf460d300, 0x1d025004, 0xf332d000, + 0x0310f470, 0x00350041, 0x01151041, 0x0004f452, + 0x0008f454, 0xf7524014, 0xf752000c, 0x1c52000d, + 0x9fe22964, 0xd2005001, 0x1f21f330, 0x0001f721, + 0xf5711d01, 0xf77102fe, 0xfc4102fc, 0xfc312020, + 0xd2131214, 0x1c712825, 0x01cdfc41, 0x4cf8fc31, + 0x0004f472, 0xe412d200, 0x0008f471, 0x1f215011, + 0x0e98fa00, 0xa82da827, 0x41465000, 0x0000a070, + 0xac3d4e46, 0xf601ac37, 0x28010005, 0xf6029178, + 0xac200004, 0x10110021, 0xd100ac29, 0xa828f540, + 0x10300120, 0x7050ac18, 0x1e150101, 0xfa000050, + 0x005019a2, 0x29006fb0, 0x0050901a, 0xfa004010, + 0x00501992, 0xfa004020, 0x0050198a, 0xfa004030, + 0xd1001982, 0x5010e000, 0x08501811, 0x28010401, + 0xac15906c, 0x0128fa00, 0x5003a822, 0xf6205005, + 0xa8110004, 0xfa004062, 0xa8230290, 0xf540d400, + 0x91022900, 0x5021a818, 0xf334d700, 0x1c410104, + 0xf6305011, 0x1a720004, 0x05120801, 0xf6301d72, + 0xf7400005, 0x28000016, 0x500090dc, 0x00320041, + 0x01524010, 0xf6220151, 0xf7120006, 0x00050006, + 0x0005f632, 0x24256ff5, 0x80ba9fe4, 0xd100a822, + 0xf620e404, 0x18110004, 0x28016201, 0xd3009028, + 0x6ff0f330, 0x0001f631, 0x90222101, 0x6ff01e30, + 0x901a2910, 0x1702fa00, 0x5030a822, 0xf330d100, + 0x800a1f10, 0xf330d000, 0x1f015001, 0x0004f620, + 0xf000d100, 0x01011050, 0x0005f620, 0x0024f213, + 0xac1b2800, 0x0024f211, 0x905a0050, 0xac100015, + 0x0562fa00, 0x0053a814, 0x904a2910, 0x60f31243, + 0x61f34013, 0x903e2803, 0x5002a818, 0x60f05001, + 0x0030ac18, 0x00470043, 0xf420d400, 0x10234011, + 0xf2430134, 0x1a440002, 0x0152a81d, 0x0125a825, + 0x0006f652, 0x00741f42, 0x00031f32, 0x6ff20012, + 0x9fd02432, 0xa83da837, 0xa07041c6, 0xac454e06, + 0xd000ac3f, 0xfc41e400, 0x18000400, 0x28000410, + 0x5000915e, 0xfc41ac10, 0xd0000400, 0xac19e804, + 0xd1001c01, 0x1810e080, 0xe084d100, 0x00021811, + 0xf76260f2, 0x00620014, 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0xd0001802, 0x900ee410, + 0x60421803, 0x90222802, 0x800c7043, 0x60221803, + 0x901c2802, 0x1c037023, 0xe804d000, 0x0400fc11, + 0x50001c01, 0x0606f800, 0xac245fb2, 0xac248006, + 0x04235fd2, 0xe400d200, 0xac2d1c03, 0x18225000, + 0x03fffc22, 0xf9002802, 0x50a305e4, 0x51442801, + 0xf000d700, 0xa545a435, 0x000cf074, 0xd5000954, + 0x0424f360, 0x00570042, 0x012761f2, 0x29521e72, + 0x1254900a, 0x1e520145, 0x20324052, 0x5014903e, + 0xe804d500, 0x08245013, 0x00251c54, 0x1025a824, + 0xf2450154, 0x2805001a, 0xd1009022, 0x1812e408, + 0xf655a825, 0x08530004, 0x1c130523, 0x001af241, + 0xf5414ff1, 0xf800001a, 0x00230574, 0x6ff350a4, + 0xf9002043, 0xa8240568, 0xf7425010, 0x1c400004, + 0xac19a82d, 0xe404d000, 0x2000fc42, 0x04201800, + 0x90182800, 0xf000d000, 0x02c4f000, 0x215060f0, + 0x5005900a, 0xf8001c45, 0x18450530, 0x926e2915, + 0x0004f641, 0x00400012, 0x01201022, 0x0019f602, + 0x0018f603, 0x90262123, 0xd2001051, 0x0112f000, + 0x0020f021, 0x0020f022, 0x13821301, 0x61f267f1, + 0x0018f701, 0x40110121, 0x0019f701, 0xa8180007, + 0xe444d200, 0x18235041, 0x28000801, 0xd1000513, + 0x1c23d800, 0xd400d300, 0xa512a432, 0xf6410023, + 0x00450004, 0xf000d400, 0x105176c3, 0xf0410114, + 0x50040020, 0x00141c34, 0x0400fc24, 0x900c2804, + 0x03fffc21, 0x1000fc31, 0x67f18004, 0x50107042, + 0x1c21ac17, 0x50011c30, 0xd410d200, 0x0018f674, + 0xf754ac25, 0xf7510017, 0xd1000005, 0xa818d810, + 0x00702800, 0xf601a512, 0x6ff10019, 0x0041ac29, + 0x6ff1a82b, 0x90c02513, 0x10114014, 0x0018f704, + 0xf000d400, 0xf2470114, 0xf2450160, 0x12c50160, + 0x00516075, 0x0160f243, 0xfc234011, 0x28030100, + 0xa8209010, 0x0005f603, 0xf7030113, 0xa8100005, + 0x0160fc04, 0x29030e53, 0xfc279008, 0x802607ff, + 0x28210073, 0x05fffc23, 0x90161c23, 0x90122815, + 0x4ff50071, 0x01fffc21, 0x1c214ff5, 0x9ffa2905, + 0x03fffc27, 0x1a411c27, 0x0018f604, 0x0800fc21, + 0x9f7c2801, 0x0019f601, 0x903c2541, 0xd1001014, + 0xd200f000, 0x0141c000, 0xf2310013, 0xfc210160, + 0x2121e000, 0xfc03901c, 0x1a310160, 0x40116ff1, + 0x001af501, 0x0018f601, 0xf7014011, 0x80080018, + 0xf5015001, 0xa824001a, 0x0005f640, 0x90162800, + 0xd200a81b, 0xd100d438, 0x4ff0d838, 0xa5122803, + 0x80141c20, 0xd100a81a, 0xd000d438, 0x2802d838, + 0xa50151f2, 0xd0001c12, 0x1800e404, 0x0200fc20, + 0x908e2800, 0xe41bd000, 0xd5005011, 0x1f01e408, + 0xf6431852, 0x41030004, 0xd3000831, 0x0521e808, + 0xfff8fc42, 0xfffffc32, 0xfc411c51, 0xfc31ffff, + 0xfc151fff, 0xa8184000, 0xa5212800, 0x28001832, + 0x1c320412, 0x2000fc13, 0x0001fc42, 0xd300a431, + 0xa521e804, 0x8000d200, 0x1c312800, 0x0004fc41, + 0x2800a512, 0x0002fc41, 0xa4521c32, 0xa5125005, + 0xf6421c32, 0x00410004, 0x01211022, 0x001af515, + 0x0017f642, 0x0018f712, 0x0ec2fa00, 0x801ca824, + 0xd100a81a, 0xfc40e000, 0xd3000007, 0x5025e808, + 0xa5012802, 0x05121832, 0x1c451c32, 0x92b82925, + 0x0004f640, 0xd000ac28, 0x1801e400, 0x2802a81a, + 0xfc429010, 0x04210004, 0x90122801, 0x80321800, + 0x8000fc21, 0x90062801, 0x802e1800, 0xd200a81b, + 0xd100d400, 0x2803d800, 0xa517a427, 0x77810071, + 0xf6421811, 0x25120005, 0x180090b0, 0x900a2803, + 0x0002fc41, 0x80060410, 0x4000fc20, 0x5021a81d, + 0x917a2800, 0xd46cd100, 0xd0002805, 0xa501d86c, + 0x28055000, 0xd1001c10, 0x1812e408, 0x0004f643, + 0x50140047, 0x4103ac27, 0x05240834, 0xfc441c14, + 0xfc34ffff, 0xfc411fff, 0xfc31fff8, 0xa442ffff, + 0xe808d400, 0x1843a512, 0xfc412805, 0x04230001, + 0xfc131c43, 0xfc142000, 0xa4324000, 0x8000d300, + 0xd100a512, 0x2805e804, 0xfc421c12, 0xa5230004, + 0xfc422805, 0x1c130002, 0xa523a443, 0xf6711c13, + 0x00720004, 0x01121021, 0x001af520, 0x0017f670, + 0x0018f720, 0x80dc0050, 0xfffffc41, 0x1ffffc31, + 0xfc402803, 0xfc30fff8, 0xd200ffff, 0xfc15e808, + 0xa5012000, 0xac112803, 0x04101820, 0x00411c20, + 0xfc40a454, 0xd2000001, 0xfc45e804, 0xa5040004, + 0x8000d000, 0x1c242803, 0xa553a403, 0xf6151c23, + 0x28050005, 0x71079022, 0x00525005, 0x40150010, + 0x01206ff2, 0xf7021e72, 0x00500006, 0x0005f612, 0x24206ff0, 0xd0009fe6, 0x0017e404, 0xfc201800, - 0x28000200, 0xd0009060, 0x5012e41b, 0xd0001f02, + 0x28000200, 0xd000914e, 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0x4000fc20, 0x90aa2800, - 0xd46cd100, 0xd0002803, 0x5014d86c, 0x5000a501, - 0xd1001c10, 0x0035e408, 0xac271812, 0xf6732805, - 0x41030004, 0x05240834, 0xfc441c14, 0xfc34ffff, - 0xfc411fff, 0xfc31fff8, 0xa442ffff, 0xe808d400, - 0x1843a512, 0xfc412805, 0x04230001, 0xfc131c43, - 0xfc142000, 0xa4324000, 0x8000d300, 0xd100a512, - 0x2805e804, 0xfc421c12, 0xa5230004, 0xfc422805, - 0x1c130002, 0xa523a443, 0xf6711c13, 0x00720004, - 0x01121021, 0x001af520, 0x0017f670, 0x0018f720, - 0xfa000050, 0xa8200b2e, 0x1c055005, 0xa3002905, - 0xa83da837, 0xa07041c6, 0x1c755025, 0x48468ff0, - 0xacf7acfd, 0xf000d500, 0xfa008006, 0x50030962, - 0xf05180f0, 0x12c10260, 0x211260f1, 0xd00090e4, - 0xf600f340, 0x6ff00003, 0x90d62900, 0x0260f050, - 0xf80013b0, 0xf537092e, 0x5010001a, 0xd094d100, - 0xd004d200, 0x1c105fd7, 0x50120021, 0x04701810, - 0xd1001c10, 0x0013e408, 0xf6411830, 0x08120004, - 0x1c320502, 0xe444d200, 0x18100021, 0x1c100470, - 0x1c415031, 0x0004f640, 0x10500051, 0xf0130101, - 0x00310020, 0x603112c1, 0x90102901, 0xfaff0040, - 0xd300f1fa, 0x5007f3d8, 0xd7008372, 0x4ff1e414, - 0x12835010, 0x63030810, 0x07021871, 0x60f20412, - 0x00521f72, 0xf6430132, 0x00470004, 0xfc020054, - 0x105302bc, 0xf2450134, 0x00730024, 0x0024f244, - 0x60f51244, 0x60f40153, 0x40144063, 0x4ff41e35, - 0x29044013, 0x40121f25, 0x05019ff4, 0xe414d000, - 0xf000d500, 0xd3005007, 0x60f1f3d8, 0x830c1f01, - 0x02fef250, 0xe404d100, 0xf5504010, 0x181002fe, - 0x29006200, 0xd000900a, 0x1f03f330, 0xd0008020, - 0x1e00f330, 0x90162900, 0xf330d000, 0x00015012, - 0xf0501f12, 0x60f002c4, 0x0001f710, 0xe440d000, - 0x00015082, 0x1d125000, 0x0836fa00, 0xfa005010, - 0x54000830, 0xe440d100, 0xfaff1d10, 0x5010f2ba, - 0xe440d100, 0xf3d8d400, 0x18401d10, 0x90802900, - 0xe404d000, 0xe410d200, 0x18201801, 0x29016011, - 0x5fe19248, 0xd1000410, 0x1c20e400, 0xfc211811, - 0x280103ff, 0xf050929a, 0xd200000c, 0x0410f356, - 0x61f10001, 0x1e210112, 0x900e2951, 0xd1001250, - 0x0101f356, 0x40511e11, 0x200150a0, 0x5010901e, - 0xe804d200, 0x1c200810, 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0x90ce2804, 0x0260f001, - 0x0005a8ba, 0x60f11301, 0x901a2112, 0xf344d000, - 0xf6005003, 0x29000002, 0xf8d8f9ff, 0x0260f050, - 0x812e13c0, 0x0260f051, 0x13415003, 0x211260f1, - 0xd0009018, 0xf600f344, 0x29000006, 0xf8b4f9ff, - 0x0260f050, 0x810a13d0, 0x0260f051, 0x211260f1, - 0xd0009056, 0x1e00f340, 0xf9ff2900, 0xf050f896, - 0x13800260, 0x043280ec, 0x50030005, 0xf9ff2902, - 0xd000f882, 0x1800f3d8, 0xf9ff2800, 0xd000f780, - 0x801ef3d8, 0x00050432, 0x29025003, 0xf864f9ff, - 0xf4b8d000, 0x28001800, 0xf762f9ff, 0xf4b8d000, - 0x0004f600, 0xf0518046, 0x12410260, 0x211260f1, - 0xd000907e, 0xf600f340, 0x29000001, 0xf834f9ff, - 0x0260f050, 0x808a1390, 0x00050432, 0x29025003, - 0xf820f9ff, 0xf4b8d000, 0x0040f000, 0xf9ff2800, - 0xd000f71c, 0xf600f4b8, 0x20100044, 0xf804f9ff, - 0xf70af8ff, 0xd1005010, 0x5fd2d094, 0xd1001c10, - 0x1810d004, 0x1c100420, 0xfabef8ff, 0xe408d100, - 0x00175013, 0xf6421871, 0x08230004, 0x1c730513, - 0x001af201, 0xf5014ff1, 0xf8ff001a, 0xf051faf4, - 0x12810260, 0x211260f1, 0xf6caf9ff, 0xf340d000, - 0x0002f600, 0xf9ff2900, 0xf050f7aa, 0x13a00260, - 0x29006010, 0xf79cf9ff, 0xf6a2f8ff, 0xe414d000, - 0x60711801, 0x70820012, 0x1f011f02, 0x4dc6a070, - 0xac47ac4d, 0xf000d200, 0x1000fc41, 0xf344d700, - 0x0260f024, 0x00420801, 0x00010412, 0x10210073, - 0x01132802, 0x0002f633, 0x6ff10031, 0x28019014, - 0x00019042, 0x10210072, 0xf6250112, 0x80440003, - 0x913e2911, 0x50140001, 0x41715003, 0xd1000814, - 0x1812e400, 0x28020442, 0xd2009128, 0x0003dc80, - 0x01231023, 0x18131833, 0x29030443, 0x50039ff2, - 0x00018110, 0x50050072, 0x10215013, 0xf7250112, - 0xac1b0003, 0x00720001, 0x10216ff5, 0x01122f85, - 0xac3a1a22, 0x00019040, 0xd7005012, 0xd300dc80, - 0x4171e400, 0x00010812, 0x1021ac20, 0x01740014, - 0x04271837, 0x90b62807, 0xa8380057, 0x10274015, - 0x01702c85, 0x1c071847, 0xd0009fe8, 0xf004f000, - 0x80040260, 0x4101ac20, 0xac2c0914, 0x60f00040, - 0xfa00ac30, 0xa82800e4, 0x290060b0, 0xa830901a, - 0xfa004010, 0xa83000d4, 0xfa004020, 0xa83000cc, - 0xfa004030, 0xa82000c4, 0x29005001, 0xd0009008, - 0x1801de50, 0x5010ac29, 0xe000d200, 0x0810a831, - 0x04011821, 0x90222801, 0xe96cfaff, 0xa830ac0d, - 0xa825a82a, 0xa8390053, 0x6ff26ff0, 0xfaff4043, - 0x0050ec92, 0x80285005, 0x90202805, 0xac38a838, - 0x1801a838, 0xa82aa830, 0x6ff26ff0, 0xeedefaff, - 0x4ff5a838, 0x40402905, 0x50059fe6, 0x0002a820, - 0xf344d700, 0x00711022, 0xf7150121, 0xa81b0003, - 0x01071020, 0x0002f773, 0xa84da847, 0xa0704246, - 0xe404d100, 0x18112800, 0x60419012, 0x90262801, - 0xe410d000, 0x70411801, 0x60218010, 0x90162801, - 0xe410d000, 0x70211801, 0xd0001c01, 0xfc12e804, - 0x1c020400, 0xd100a070, 0x0101f000, 0xf6111020, - 0x00130314, 0x60130002, 0x2000fc02, 0x900e2803, - 0xfc311011, 0xfc212000, 0x800621fc, 0xf338d100, - 0xf418d300, 0x1d320103, 0x0002f531, 0x0000a070, + 0x00050018, 0x0cc6fa00, 0x5001a824, 0xd1001c41, + 0x2805d400, 0xd0000057, 0xd200d800, 0xa501f000, + 0xf0220010, 0x73400010, 0x50001803, 0x28036403, + 0x001090aa, 0x18007800, 0x1000fc20, 0x90142800, + 0xd000a82b, 0x4012f34c, 0x1e000130, 0x24204010, + 0xd000901c, 0x1802e408, 0x0004f643, 0x50140045, + 0x08344103, 0x1c040524, 0x50000054, 0xfc427541, + 0xfc32ffff, 0x28071fff, 0x4000fc15, 0xfc411811, + 0xfc31fff8, 0xa512ffff, 0xe808d100, 0x18132807, + 0x1c130423, 0x2000fc13, 0x0001fc41, 0xd300a432, + 0xa5128000, 0xe804d100, 0x1c122807, 0x0004fc42, + 0x2807a523, 0x0002fc42, 0xa4531c13, 0xa5235005, + 0xf6411c13, 0x00420004, 0x01121021, 0x001af525, + 0x0017f643, 0x0018f723, 0xa82a1c45, 0xf34cd100, + 0x1f100121, 0x29051845, 0xa837a300, 0x41c6a83d, + 0xa818a070, 0xd46cd100, 0xd86cd200, 0x28005004, + 0x1c14a521, 0xe804d400, 0xd4001c43, 0x5013e408, + 0x00751841, 0x0004f652, 0x50420823, 0x08020513, + 0xd4001c43, 0x0723e444, 0x04321842, 0xfa001c42, + 0x00500b9c, 0xd3005031, 0x1c01f000, 0x0004f602, + 0x10520031, 0xf0170121, 0x00710020, 0x603112c1, + 0x90582801, 0x50124ff1, 0x08121287, 0xe414d100, + 0xac1a6307, 0x01370724, 0xfc071812, 0x042402bc, + 0x1f1460f4, 0x0004f604, 0x01431054, 0x0024f234, + 0x0024f233, 0x124360f4, 0x60f30104, 0x40134064, + 0x4ff31e45, 0x29034014, 0x40171f75, 0xa81b9ff4, + 0x60f20532, 0x00051f12, 0x00058008, 0xf184faff, + 0x1c505000, 0x8f240054, 0xacfd4846, 0xd500acf7, + 0x8006f000, 0x0962fa00, 0x80f05003, 0x0260f051, + 0x60f112c1, 0x90e42112, 0xf340d000, 0x0003f600, + 0x29006ff0, 0xf05090d6, 0x13b00260, 0x092ef800, + 0x001af537, 0xd1005010, 0xd200d094, 0x5fd7d004, + 0x00211c10, 0x18105012, 0x1c100470, 0xe408d100, + 0x18300013, 0x0004f641, 0x05020812, 0xd2001c32, + 0x0021e444, 0x04701810, 0x50311c10, 0xf6401c41, + 0x00510004, 0x01011050, 0x0020f013, 0x12c10031, + 0x29016031, 0x00409010, 0xf0e8faff, 0xf3e0d300, + 0x83725007, 0xe414d700, 0x50104ff1, 0x08101283, + 0x18716303, 0x04120702, 0x1f7260f2, 0x01320052, + 0x0004f643, 0x00540047, 0x02bcfc02, 0x01341053, + 0x0024f245, 0xf2440073, 0x12440024, 0x015360f5, + 0x406360f4, 0x1e354014, 0x40134ff4, 0x1f252904, + 0x9ff44012, 0xd0000501, 0xd500e414, 0x5007f000, + 0xf3e0d300, 0x1f0160f1, 0xf250830c, 0xd10002fe, + 0x4010e404, 0x02fef550, 0x62001810, 0x900a2900, + 0xf330d000, 0x80201f03, 0xf330d000, 0x29001e00, + 0xd0009016, 0x5012f330, 0x1f120001, 0x02c4f050, + 0xf71060f0, 0xd0000001, 0x5082e440, 0x50000001, + 0xfa001d12, 0x50100836, 0x0830fa00, 0xd1005400, + 0x1d10e440, 0xf1a8faff, 0xd1005010, 0xd400e440, + 0x1d10f3e0, 0x29001840, 0xd0009080, 0xd200e404, + 0x1801e410, 0x60111820, 0x92482901, 0x04105fe1, + 0xe400d100, 0x18111c20, 0x03fffc21, 0x929a2801, + 0x000cf050, 0xf360d200, 0x00010410, 0x011261f1, + 0x29511e21, 0x1250900e, 0xf360d100, 0x1e110101, + 0x50a04051, 0x901e2001, 0xd2005010, 0x0810e804, + 0x00121c20, 0x10220040, 0xf2020120, 0x2902001a, + 0x0746f900, 0x50a20010, 0x20206ff0, 0x5010924c, + 0x0004f741, 0x800a1c40, 0x923e2910, 0x0004f641, + 0x00106ff1, 0x10200043, 0xf6300103, 0xf6320019, + 0x21020018, 0x10519024, 0x01100050, 0x0020f001, + 0x0020f000, 0x13801301, 0x61f067f1, 0x0018f731, + 0x40110101, 0x0019f731, 0xe444d000, 0xd094d200, + 0xd004d700, 0x18100001, 0x1c107020, 0x0023aca3, + 0x5fd25011, 0x18701c31, 0xd2000420, 0x1c70d090, + 0x50021c21, 0x0004f640, 0x10500051, 0xf0100101, + 0xd1000020, 0x6ff0d098, 0x1c321c10, 0x1870a8a3, + 0x1c707020, 0x0005f742, 0x0018f631, 0x0017f741, + 0x0019f632, 0x6ff00010, 0x9daa2502, 0x40111010, + 0xf7310105, 0xacb50018, 0x0160f253, 0x0160f250, + 0x12c3aca8, 0x0160f251, 0x60730062, 0xfc024013, + 0xfc210060, 0x28010100, 0xf6419014, 0x00120005, + 0xf7420132, 0x00420005, 0x40620112, 0xacbb0035, + 0x50045003, 0xd008d700, 0x6ff5a8a8, 0x90142805, + 0x50016ff0, 0x1c704011, 0x6ff40014, 0xa8bc2454, + 0xd0009ff4, 0x5007f33c, 0x28001800, 0x0602f900, + 0xfc00a8b0, 0xacb00160, 0x50050047, 0x29076ff7, + 0x50049006, 0xd0008026, 0x1800d00c, 0x28006040, + 0xd1009018, 0x0020d008, 0x01501811, 0x1f014015, + 0x6ff00050, 0x9fe02470, 0x6ff40152, 0x02545007, + 0x6ff00040, 0x901e2800, 0xe404d000, 0xfc201800, + 0x29000200, 0xd0009074, 0x4013f33c, 0x24031800, + 0x80089fa8, 0xf33cd000, 0x20301800, 0x0592f900, + 0xd500a8b0, 0xd400f000, 0x1a00f3e0, 0xf631a8a3, + 0xfc200018, 0x28000800, 0xf6309ef8, 0x25100019, + 0x10119ca4, 0xd2000050, 0x0110c000, 0x0160f201, + 0xe000fc21, 0x9c8a2121, 0x0160fc00, 0x6ff01a00, + 0xf5304010, 0xf630001a, 0x40100018, 0x0018f730, + 0x70108c74, 0x80581c20, 0xd1005010, 0x1f10e41b, + 0xe408d000, 0xf3e0d300, 0xd5005012, 0x0004f000, + 0xf6311840, 0x41010004, 0x05020812, 0xf6301c42, + 0x00310004, 0x01011020, 0x001af517, 0x0017f630, + 0x0018f710, 0xd0001c37, 0x1800e404, 0x28006010, + 0xd0009018, 0x0001e410, 0x70101810, 0xd0001c10, + 0xfc11e804, 0x1c010400, 0xe440d000, 0x1d015401, + 0xeeccfaff, 0xd1005020, 0x1d10e440, 0xf4c0d000, + 0xfaff5001, 0xd000f49e, 0x5401e440, 0xfaff1d01, + 0x5040eeae, 0xe440d100, 0xd0001d10, 0x5011f4c0, + 0xfaff4400, 0xd000f47e, 0x5401e440, 0xfaff1d01, + 0x5007ee8e, 0xe400d400, 0xd1005080, 0x1d10e440, + 0x0260f051, 0xf340d200, 0x0100fc40, 0x08700172, + 0x0401ac8a, 0x29011e20, 0x00019030, 0x29116ff1, + 0x007090dc, 0x50111842, 0x08014130, 0x04125000, + 0x90ca2802, 0x10220072, 0xdc00fc32, 0x18431823, + 0x29030413, 0x80b69ff8, 0x50120071, 0x08124131, + 0x0001acaa, 0x28016ff1, 0xa501a611, 0x0070ac81, + 0x1020ac97, 0xfc30aca0, 0xac98dc00, 0xacb85000, + 0xa8a91840, 0x28000410, 0xf0559080, 0xa8a00260, + 0x00500905, 0xacb060f0, 0x0638fa00, 0x290560b5, + 0x901aa8b5, 0x40100050, 0x0628fa00, 0x40200050, + 0x0620fa00, 0x40300050, 0x0618fa00, 0xd200a898, + 0x1801e000, 0x08505010, 0x1822ace1, 0x29020402, + 0x6ff5900e, 0x00505002, 0xf35afaff, 0xfaff801c, + 0x5010edae, 0x50026ff5, 0x0061ac08, 0x0070fc01, + 0xa8930050, 0xf0d4faff, 0xd500a8b8, 0xd400f000, + 0x4010e400, 0x9f782c30, 0xa897a880, 0x4017a889, + 0x1f102947, 0xd0009efc, 0x5401e440, 0x1d510005, + 0xed6cfaff, 0xd1005100, 0x1d50f334, 0x50011a10, + 0x910a2800, 0x0010acb9, 0xf540d300, 0xace81010, + 0x0030a8ed, 0x10350115, 0xaca80150, 0x29101800, + 0x00509092, 0xf6040130, 0x00510016, 0x70510032, + 0x1e200112, 0x00320051, 0x28047041, 0x1e210112, + 0xf000d200, 0x01121051, 0x0024f221, 0xf221acb1, + 0x90980024, 0xac99aca0, 0xf20afaff, 0xa8a4a89a, + 0x90882910, 0x60f21242, 0x61f24012, 0x907c2802, + 0x7065a8b0, 0x60f05001, 0xacb00150, 0x00275000, + 0xd3000042, 0x4010f420, 0x01231022, 0x0002f232, + 0x00451a33, 0x0114a8b4, 0xf540d100, 0x00540141, + 0x1f311e11, 0x00721f21, 0x6ff10001, 0x9fd02421, + 0x2920803a, 0x0050904e, 0xf540d100, 0x00127060, + 0xacb10101, 0x70500050, 0xaca20102, 0xec90faff, + 0x7045a8a0, 0xf540d200, 0x01525003, 0x1e201e01, + 0xfaffa8b2, 0x2910edf4, 0xa8b9901a, 0xf334d200, + 0x08105010, 0x07001a21, 0x1d210401, 0xa8a85001, + 0xa8b91c01, 0x401150a0, 0x9efa2101, 0xe440d000, + 0x00055401, 0xfaff1d51, 0x5200ec46, 0xf332d100, + 0x50045003, 0xd5001d50, 0x1a10f460, 0x905e2800, + 0xf050acbc, 0x29100004, 0xf6529012, 0x1851000d, + 0x000cf650, 0xf1befaff, 0xa8bc8022, 0x90362920, + 0xec0cfaff, 0x0008f053, 0x000df652, 0x000cf650, + 0xac095011, 0xfaff0051, 0xa8bcef32, 0xf332d100, + 0x50035010, 0x1a210012, 0x07000840, 0x1d210401, + 0x0004f453, 0x41054014, 0x9fa62964, 0xe440d000, + 0x0080fc11, 0xe400d400, 0xf000d500, 0x1d011d01, + 0xf6511840, 0x00020263, 0x03fffc20, 0x04121332, + 0x050263f2, 0x90422902, 0xe404d000, 0x61001800, + 0x90362900, 0xe444d000, 0x00055fe1, 0xacb81850, + 0x04101850, 0xfaff1c50, 0xa8b8e78c, 0xe400d400, + 0xd2005003, 0xfc41e804, 0xfc3101f8, 0x701007ff, + 0xd5001c50, 0x1c21f000, 0xe404d000, 0x60801800, + 0xf9ff2800, 0xf051f958, 0xd00002c4, 0x1842f356, + 0xfc2260f1, 0x011003ff, 0xacb81e00, 0x00540013, + 0x01341053, 0xf0445013, 0x08130020, 0x00350050, + 0x000cf007, 0x03fffc25, 0x3000fc24, 0x28070457, + 0x28049006, 0xf007908c, 0x12a7000c, 0x28070457, + 0x28049006, 0xf007909a, 0x1347000c, 0x28070457, + 0x28049006, 0xf00190ce, 0xa8ba0260, 0x13010005, + 0x211260f1, 0xd000901a, 0x5003f344, 0x0002f600, + 0xf9ff2900, 0xf050f8d8, 0x13c00260, 0xf051812e, + 0x50030260, 0x60f11341, 0x90182112, 0xf344d000, + 0x0006f600, 0xf9ff2900, 0xf050f8b4, 0x13d00260, + 0xf051810a, 0x60f10260, 0x90562112, 0xf340d000, + 0x29001e00, 0xf896f9ff, 0x0260f050, 0x80ec1380, + 0x00050432, 0x29025003, 0xf882f9ff, 0xf3e0d000, + 0x28001800, 0xf780f9ff, 0xf3e0d000, 0x0432801e, + 0x50030005, 0xf9ff2902, 0xd000f864, 0x1800f4c0, + 0xf9ff2800, 0xd000f762, 0xf600f4c0, 0x80460004, + 0x0260f051, 0x60f11241, 0x907e2112, 0xf340d000, + 0x0001f600, 0xf9ff2900, 0xf050f834, 0x13900260, + 0x0432808a, 0x50030005, 0xf9ff2902, 0xd000f820, + 0xf000f4c0, 0x28000040, 0xf71cf9ff, 0xf4c0d000, + 0x0044f600, 0xf9ff2010, 0xf8fff804, 0x5010f70a, + 0xd094d100, 0x1c105fd2, 0xd004d100, 0x04201810, + 0xf8ff1c10, 0xd100fabe, 0x5013e408, 0x18710017, + 0x0004f642, 0x05130823, 0xf2011c73, 0x4ff1001a, + 0x001af501, 0xfaf4f8ff, 0x0260f051, 0x60f11281, + 0xf9ff2112, 0xd000f6ca, 0xf600f340, 0x29000002, + 0xf7aaf9ff, 0x0260f050, 0x601013a0, 0xf9ff2900, + 0xf8fff79c, 0xd000f6a2, 0x1801e414, 0x00126071, + 0x1f027082, 0xa0701f01, 0xac4d4dc6, 0xd200ac47, + 0xfc41f000, 0xd7001000, 0xf024f344, 0x08010260, + 0x04120042, 0x00730001, 0x28021021, 0xf6330113, + 0x00310002, 0x90146ff1, 0x90422801, 0x00720001, + 0x01121021, 0x0003f625, 0x29118044, 0x0001913e, + 0x50035014, 0x08144171, 0xe400d100, 0x04421812, + 0x91282802, 0xdc80d200, 0x10230003, 0x18330123, + 0x04431813, 0x9ff22903, 0x81105003, 0x00720001, + 0x50135005, 0x01121021, 0x0003f725, 0x0001ac1b, + 0x6ff50072, 0x2f851021, 0x1a220112, 0x9040ac3a, + 0x50120001, 0xdc80d700, 0xe400d300, 0x08124171, + 0xac200001, 0x00141021, 0x18370174, 0x28070427, + 0x005790b6, 0x4015a838, 0x2c851027, 0x18470170, + 0x9fe81c07, 0xf000d000, 0x0260f004, 0xac208004, + 0x09144101, 0x0040ac2c, 0xac3060f0, 0x00e4fa00, + 0x60b0a828, 0x901a2900, 0x4010a830, 0x00d4fa00, + 0x4020a830, 0x00ccfa00, 0x4030a830, 0x00c4fa00, + 0x5001a820, 0x90082900, 0xde50d000, 0xac291801, + 0xd2005010, 0xa831e000, 0x18210810, 0x28010401, + 0xfaff9022, 0xac0de85a, 0xa82aa830, 0x0053a825, + 0x6ff0a839, 0x40436ff2, 0xeb80faff, 0x50050050, + 0x28058028, 0xa8389020, 0xa838ac38, 0xa8301801, + 0x6ff0a82a, 0xfaff6ff2, 0xa838edcc, 0x29054ff5, + 0x9fe64040, 0xa8205005, 0xd7000002, 0x1022f344, + 0x01210071, 0x0003f715, 0x1020a81b, 0xf7730107, + 0xa8470002, 0x4246a84d, 0xd100a070, 0x2800e404, + 0x90121811, 0x28016041, 0xd0009026, 0x1801e410, + 0x80107041, 0x28016021, 0xd0009016, 0x1801e410, + 0x1c017021, 0xe804d000, 0x0400fc12, 0xa0701c02, + 0xf000d100, 0x10200101, 0x0314f611, 0x00020013, + 0xfc026013, 0x28032000, 0x1011900e, 0x2000fc31, + 0x21fcfc21, 0xd1008006, 0xd300f338, 0x0103f420, + 0xf5311d32, 0xa0700002, }; -const unsigned long sizeof_scu_isopprog_array = 7024; /* 0x00001b70 */ +const unsigned long sizeof_scu_isopprog_array = 7304; /* 0x00001c88 */ diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_emmc.h b/arch/arm/src/cxd56xx/hardware/cxd56_emmc.h index b310ed3f835..a5e2e4969c1 100644 --- a/arch/arm/src/cxd56xx/hardware/cxd56_emmc.h +++ b/arch/arm/src/cxd56xx/hardware/cxd56_emmc.h @@ -324,6 +324,9 @@ #define EXTCSD_BUS_WIDTH (183u) #define EXTCSD_BUS_WIDTH_4BIT_SDR (0x01u) #define EXTCSD_BUS_WIDTH_4BIT_DDR (0x05u) + +/* Vendor-specific Extended CSD */ + #define EXTCSD_PON (34u) /* Power Off Notification */ #define EXTCSD_PON_POWERED_ON (0x01u) #define EXTCSD_PON_POWERED_OFF_LONG (0x03u) diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_scu.h b/arch/arm/src/cxd56xx/hardware/cxd56_scu.h index 224d29313da..307f4fec218 100644 --- a/arch/arm/src/cxd56xx/hardware/cxd56_scu.h +++ b/arch/arm/src/cxd56xx/hardware/cxd56_scu.h @@ -21,12 +21,8 @@ #ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H #define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H -#define SCU_PWM0_PARAM (CXD56_SCU_BASE + 0x0000) -#define SCU_PWM0_EN (CXD56_SCU_BASE + 0x0004) -#define SCU_PWM0_UPDATE (CXD56_SCU_BASE + 0x0008) -#define SCU_PWM1_PARAM (CXD56_SCU_BASE + 0x000c) -#define SCU_PWM1_EN (CXD56_SCU_BASE + 0x0010) -#define SCU_PWM1_UPDATE (CXD56_SCU_BASE + 0x0014) +#define SCU_DEBUG_I2C0 (CXD56_SCU_BASE + 0x0018) +#define SCU_DEBUG_I2C1 (CXD56_SCU_BASE + 0x001c) #define SCU_SEQ_ENABLE_ALL (CXD56_SCU_BASE + 0x0020) #define SCU_SEQ_ACCESS_INHIBIT (CXD56_SCU_BASE + 0x0024) #define SCU_START_CTRL_COMMON (CXD56_SCU_BASE + 0x0028) @@ -178,5 +174,12 @@ #define SCU_INT_RAW_STT_ERR_2 (CXD56_SCU_BASE + 0x046c) #define SCU_INT_MASKED_STT_ERR_2 (CXD56_SCU_BASE + 0x0470) #define SCU_RAM_TEST (CXD56_SCU_BASE + 0x0500) +#define SCU_POWER (CXD56_SCU_BASE + 0x0510) +#define SCU_INT_ENABLE_MAIN_AD (CXD56_SCU_BASE + 0x0520) +#define SCU_INT_DISABLE_MAIN_AD (CXD56_SCU_BASE + 0x0524) +#define SCU_INT_CLEAR_MAIN_AD (CXD56_SCU_BASE + 0x0528) +#define SCU_INT_LEVEL_SEL_MAIN_AD (CXD56_SCU_BASE + 0x052c) +#define SCU_INT_RAW_STT_MAIN_AD (CXD56_SCU_BASE + 0x0530) +#define SCU_INT_MASKED_STT_MAIN_AD (CXD56_SCU_BASE + 0x0534) #endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H */ diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h b/arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h index 41fc417ceac..6a1d3998784 100644 --- a/arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h +++ b/arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h @@ -21,7 +21,11 @@ #ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUSEQ_H #define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUSEQ_H +#define SCUSEQ_SW_REVISION_DATE (CXD56_SCU_SEQ_DRAM_BASE + 0x000) +#define SCUSEQ_SW_REVISION_TIME (CXD56_SCU_SEQ_DRAM_BASE + 0x004) +#define SCUSEQ_SW_REVISION_GIT_HASH (CXD56_SCU_SEQ_DRAM_BASE + 0x008) #define SCUSEQ_SRC_SEL (CXD56_SCU_SEQ_DRAM_BASE + 0x00c) +#define SCUSEQ_REPEAT_TXABORT (CXD56_SCU_SEQ_DRAM_BASE + 0x010) #define SCUSEQ_PROPERTY(s) (CXD56_SCU_SEQ_DRAM_BASE + 0x020 + ((s) * 0x20)) #define SCUSEQ_OUT_FORMAT(s) (CXD56_SCU_SEQ_DRAM_BASE + 0x024 + ((s) * 0x20)) #define SCUSEQ_MATH_PROC_OFST_GAIN_X(s) (CXD56_SCU_SEQ_DRAM_BASE + 0x028 + ((s) * 0x20)) diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_udmac.h b/arch/arm/src/cxd56xx/hardware/cxd56_udmac.h index 297e366fd6e..156542cc1c5 100644 --- a/arch/arm/src/cxd56xx/hardware/cxd56_udmac.h +++ b/arch/arm/src/cxd56xx/hardware/cxd56_udmac.h @@ -135,10 +135,10 @@ struct dma_descriptor_s { - volatile void * volatile srcend; - volatile void * volatile dstend; - volatile uint32_t ctrl; - volatile uint32_t user; + volatile uintptr_t srcend; + volatile uintptr_t dstend; + volatile uint32_t ctrl; + volatile uint32_t user; }; /**************************************************************************** diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c index a15316bd5b9..9e5c065f3ae 100644 --- a/arch/arm/src/dm320/dm320_serial.c +++ b/arch/arm/src/dm320/dm320_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index 721300d63ec..d522f7a99e4 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/efm32/Make.defs b/arch/arm/src/efm32/Make.defs index 2f763950eb1..670d1a9132f 100644 --- a/arch/arm/src/efm32/Make.defs +++ b/arch/arm/src/efm32/Make.defs @@ -43,6 +43,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c index e2a48fd1e5a..c3a8494e1c5 100644 --- a/arch/arm/src/efm32/efm32_dma.c +++ b/arch/arm/src/efm32/efm32_dma.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c index 0ed5952d5ed..380de02ac0d 100644 --- a/arch/arm/src/efm32/efm32_flash.c +++ b/arch/arm/src/efm32/efm32_flash.c @@ -70,6 +70,7 @@ #include +#include #include #include diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c index abe87e40600..d5cc6738adb 100644 --- a/arch/arm/src/efm32/efm32_i2c.c +++ b/arch/arm/src/efm32/efm32_i2c.c @@ -65,6 +65,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c index ce929f6dfd5..2c9a5287b0f 100644 --- a/arch/arm/src/efm32/efm32_irq.c +++ b/arch/arm/src/efm32/efm32_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index 64bff2ee7a5..240b8c2bc5d 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index ce0359fcdc3..5442a74a9bf 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c index 090df585ca0..f65fbd7f02c 100644 --- a/arch/arm/src/efm32/efm32_start.c +++ b/arch/arm/src/efm32/efm32_start.c @@ -79,10 +79,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void efm32_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Private Functions @@ -198,47 +194,6 @@ static inline void efm32_fpuconfig(void) # define efm32_fpuconfig() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -319,17 +274,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/efm32/efm32_timer.c b/arch/arm/src/efm32/efm32_timer.c index 6d667c015b2..47277f7b252 100644 --- a/arch/arm/src/efm32/efm32_timer.c +++ b/arch/arm/src/efm32/efm32_timer.c @@ -107,7 +107,7 @@ void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg) tmrinfo("DTFAULT: %04x DTFAULTC: %04x DTLOCK: %04x \n", getreg32(base + EFM32_TIMER_CTRL_OFFSET), getreg32(base + EFM32_TIMER_STATUS_OFFSET), - getreg32(base + EFM32_TIMER_IEN_OFFSET), + getreg32(base + EFM32_TIMER_IEN_OFFSET)); #endif } diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index 5b29c9ca893..cf659e92be1 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -5597,7 +5598,7 @@ void arm_usbinitialize(void) ret = irq_attach(EFM32_IRQ_USB, efm32_usbinterrupt, NULL); if (ret < 0) { - uerr("ERROR: irq_attach failed\n", ret); + uerr("ERROR: irq_attach failed: %d\n", ret); goto errout; } diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index 34fb00d9635..027ac8cfeba 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/eoss3/Make.defs b/arch/arm/src/eoss3/Make.defs index 3e2bc2f3257..61492fe065d 100644 --- a/arch/arm/src/eoss3/Make.defs +++ b/arch/arm/src/eoss3/Make.defs @@ -43,6 +43,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/eoss3/eoss3_irq.c b/arch/arm/src/eoss3/eoss3_irq.c index 430a8b49218..869729795c8 100644 --- a/arch/arm/src/eoss3/eoss3_irq.c +++ b/arch/arm/src/eoss3/eoss3_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/eoss3/eoss3_start.c b/arch/arm/src/eoss3/eoss3_start.c index a3e36b68a44..57a3a83aac7 100644 --- a/arch/arm/src/eoss3/eoss3_start.c +++ b/arch/arm/src/eoss3/eoss3_start.c @@ -72,10 +72,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void eoss3_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Private Functions @@ -196,47 +192,6 @@ static inline void eoss3_fpuconfig(void) # define eoss3_fpuconfig() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -332,17 +287,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/imx1/imx_serial.c b/arch/arm/src/imx1/imx_serial.c index 1cf2d1918d6..a0b3fa12861 100644 --- a/arch/arm/src/imx1/imx_serial.c +++ b/arch/arm/src/imx1/imx_serial.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imx1/imx_spi.c b/arch/arm/src/imx1/imx_spi.c index 6719c619858..d345b6b5c2f 100644 --- a/arch/arm/src/imx1/imx_spi.c +++ b/arch/arm/src/imx1/imx_spi.c @@ -826,19 +826,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = CSPI_CTRL_PHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = CSPI_CTRL_POL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = CSPI_CTRL_PHA | CSPI_CTRL_POL; break; diff --git a/arch/arm/src/imx6/Kconfig b/arch/arm/src/imx6/Kconfig index b71c49da389..91c78e77d77 100644 --- a/arch/arm/src/imx6/Kconfig +++ b/arch/arm/src/imx6/Kconfig @@ -89,26 +89,31 @@ config IMX6_UART1 bool "UART1" default n select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config IMX6_UART2 bool "UART2" default n select UART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config IMX6_UART3 bool "UART3" default n select UART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config IMX6_UART4 bool "UART4" default n select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config IMX6_UART5 bool "UART5" default n select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config IMX6_SPI1 bool "SPI1" diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index f04bd17b4c1..bc9884e1030 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -90,6 +90,7 @@ endif ifeq ($(CONFIG_BUILD_KERNEL),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c +CMN_CSRCS += arm_pthread_exit.c endif ifeq ($(CONFIG_ARCH_ADDRENV),y) diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c index 2f77640328b..0e0d166fe56 100644 --- a/arch/arm/src/imx6/imx_ecspi.c +++ b/arch/arm/src/imx6/imx_ecspi.c @@ -929,19 +929,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = ECSPI_CONREG_PHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = ECSPI_CONREG_POL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = ECSPI_CONREG_PHA | ECSPI_CONREG_POL; break; diff --git a/arch/arm/src/imx6/imx_enet.c b/arch/arm/src/imx6/imx_enet.c index 3dda1867d13..37427dfa39c 100644 --- a/arch/arm/src/imx6/imx_enet.c +++ b/arch/arm/src/imx6/imx_enet.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c index 84f2f141f29..239c412125b 100644 --- a/arch/arm/src/imx6/imx_serial.c +++ b/arch/arm/src/imx6/imx_serial.c @@ -29,11 +29,17 @@ #include #include #include +#include #include #include +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + #include #include +#include #include #include #include @@ -187,13 +193,18 @@ struct imx_uart_s { uint32_t uartbase; /* Base address of UART registers */ uint32_t baud; /* Configured baud */ + uint32_t ie; /* Saved enabled interrupts */ uint32_t ucr1; /* Saved UCR1 value */ uint8_t irq; /* IRQ associated with this UART */ uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (7 or 8) */ uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */ - uint8_t hwfc:1; /* 1: Hardware flow control */ - uint8_t reserved:6; +#ifdef CONFIG_SERIAL_IFLOWCONTROL + uint8_t iflow:1; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + uint8_t oflow:1; /* output flow control (CTS) enabled */ +#endif }; /**************************************************************************** @@ -688,9 +699,10 @@ static int imx_interrupt(int irq, void *context, FAR void *arg) static int imx_ioctl(struct file *filep, int cmd, unsigned long arg) { -#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT +#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; + irqstate_t flags; #endif int ret = OK; @@ -712,6 +724,176 @@ static int imx_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + + /* Return flow control */ + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0); +#endif + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + +#if defined(CS9) + case 9: + termiosp->c_cflag |= CS9; + break; +#endif + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv; + uint32_t baud; + uint32_t ie; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if ((!termiosp) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; + +#if defined(CS9) + case CS9: + nbits = 9; + break; +#endif + default: + ret = -EINVAL; + break; + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + flags = spin_lock_irqsave(NULL); + imx_disableuartint(priv, &ie); + ret = imx_setup(dev); + + /* Restore the interrupt state */ + + imx_restoreuartint(priv, ie); + priv->ie = ie; + spin_unlock_irqrestore(NULL, flags); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ default: diff --git a/arch/arm/src/imx6/imx_timerisr.c b/arch/arm/src/imx6/imx_timerisr.c index c6cc333e99f..6a66430bc2c 100644 --- a/arch/arm/src/imx6/imx_timerisr.c +++ b/arch/arm/src/imx6/imx_timerisr.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 4cff2b4a7d6..e1165ea4e7b 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -170,6 +170,11 @@ config IMXRT_FLEXCAN default n select ARCH_HAVE_NETDEV_STATISTICS +config IMXRT_FLEXPWM + bool + default n + select ARCH_HAVE_PWM_MULTICHAN + config IMXRT_LPI2C bool default n @@ -547,6 +552,246 @@ config FLEXCAN3_DATA_SAMPLEP endmenu # IMXRT_FLEXCAN3 +menu "FLEXPWM Peripherals" + +config IMXRT_FLEXPWM1 + bool "FLEXPWM1" + default n + select IMXRT_FLEXPWM + +config IMXRT_FLEXPWM2 + bool "FLEXPWM2" + default n + select IMXRT_FLEXPWM + +if ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +config IMXRT_FLEXPWM3 + bool "FLEXPWM3" + default n + select IMXRT_FLEXPWM + +config IMXRT_FLEXPWM4 + bool "FLEXPWM4" + default n + select IMXRT_FLEXPWM + +endif # ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +endmenu # FLEXPWM Peripherals + +menu "FLEXPWM1 Configuration" + depends on IMXRT_FLEXPWM1 + +config IMXRT_FLEXPWM1_MOD1 + bool "FLEXPWM1 Module 1" + default n + +if IMXRT_FLEXPWM1_MOD1 + +config IMXRT_FLEXPWM1_MOD1_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM1_MOD2 + bool "FLEXPWM1 Module 2" + default n + +if IMXRT_FLEXPWM1_MOD2 + +config IMXRT_FLEXPWM1_MOD2_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM1_MOD3 + bool "FLEXPWM1 Module 3" + default n + +if IMXRT_FLEXPWM1_MOD3 + +config IMXRT_FLEXPWM1_MOD3_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM1_MOD4 + bool "FLEXPWM1 Module 4" + default n + +if IMXRT_FLEXPWM1_MOD4 + +config IMXRT_FLEXPWM1_MOD4_COMP + bool "Use complementary output" + default n + +endif + +endmenu # IMXRT_FLEXPWM1 + +menu "FLEXPWM2 Configuration" + depends on IMXRT_FLEXPWM2 + +config IMXRT_FLEXPWM2_MOD1 + bool "FLEXPWM2 Module 1" + default n + +if IMXRT_FLEXPWM2_MOD1 + +config IMXRT_FLEXPWM2_MOD1_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM2_MOD2 + bool "FLEXPWM2 Module 2" + default n + +if IMXRT_FLEXPWM2_MOD2 + +config IMXRT_FLEXPWM2_MOD2_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM2_MOD3 + bool "FLEXPWM2 Module 3" + default n + +if IMXRT_FLEXPWM2_MOD3 + +config IMXRT_FLEXPWM2_MOD3_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM2_MOD4 + bool "FLEXPWM2 Module 4" + default n + +if IMXRT_FLEXPWM2_MOD4 + +config IMXRT_FLEXPWM2_MOD4_COMP + bool "Use complementary output" + default n + +endif + +endmenu # IMXRT_FLEXPWM2 + +menu "FLEXPWM3 Configuration" + depends on IMXRT_FLEXPWM3 + +config IMXRT_FLEXPWM3_MOD1 + bool "FLEXPWM3 Module 1" + default n + +if IMXRT_FLEXPWM3_MOD1 + +config IMXRT_FLEXPWM3_MOD1_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM3_MOD2 + bool "FLEXPWM3 Module 2" + default n + +if IMXRT_FLEXPWM3_MOD2 + +config IMXRT_FLEXPWM3_MOD2_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM3_MOD3 + bool "FLEXPWM3 Module 3" + default n + +if IMXRT_FLEXPWM3_MOD3 + +config IMXRT_FLEXPWM3_MOD3_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM3_MOD4 + bool "FLEXPWM3 Module 4" + default n + +if IMXRT_FLEXPWM3_MOD4 + +config IMXRT_FLEXPWM3_MOD4_COMP + bool "Use complementary output" + default n + +endif + +endmenu # IMXRT_FLEXPWM3 + +menu "FLEXPWM4 Configuration" + depends on IMXRT_FLEXPWM4 + +config IMXRT_FLEXPWM4_MOD1 + bool "FLEXPWM4 Module 1" + default n + +if IMXRT_FLEXPWM4_MOD1 + +config IMXRT_FLEXPWM4_MOD1_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM4_MOD2 + bool "FLEXPWM4 Module 2" + default n + +if IMXRT_FLEXPWM4_MOD2 + +config IMXRT_FLEXPWM4_MOD2_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM4_MOD3 + bool "FLEXPWM4 Module 3" + default n + +if IMXRT_FLEXPWM4_MOD3 + +config IMXRT_FLEXPWM4_MOD3_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM4_MOD4 + bool "FLEXPWM4 Module 4" + default n + +if IMXRT_FLEXPWM4_MOD4 + +config IMXRT_FLEXPWM4_MOD4_COMP + bool "Use complementary output" + default n + +endif + +endmenu # IMXRT_FLEXPWM4 + menu "LPI2C Peripherals" menuconfig IMXRT_LPI2C1 diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs index 5d5946b234e..ae9026135ad 100644 --- a/arch/arm/src/imxrt/Make.defs +++ b/arch/arm/src/imxrt/Make.defs @@ -55,6 +55,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif @@ -115,6 +116,10 @@ ifeq ($(CONFIG_IMXRT_FLEXCAN),y) CHIP_CSRCS += imxrt_flexcan.c endif +ifeq ($(CONFIG_IMXRT_FLEXPWM),y) +CHIP_CSRCS += imxrt_flexpwm.c +endif + ifeq ($(CONFIG_IMXRT_SNVS_LPSRTC),y) CHIP_CSRCS += imxrt_lpsrtc.c CHIP_CSRCS += imxrt_hprtc.c diff --git a/arch/arm/src/imxrt/hardware/imxrt_ccm.h b/arch/arm/src/imxrt/hardware/imxrt_ccm.h index aa4fd281f3a..9b4fad926b2 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_ccm.h +++ b/arch/arm/src/imxrt/hardware/imxrt_ccm.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_ccm.h * - * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. - * Authors: Janne Rosberg - * David Sidrane - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h index 6f39ab5bc32..3f06ce73089 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h @@ -149,9 +149,14 @@ #define IOMUX_ENET_TX_CLK_DEFAULT (IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE ) +#define IOMUX_ENC_DEFAULT (0) + #define IOMUX_CAN_DEFAULT (IOMUX_SLEW_SLOW | \ IOMUX_DRIVE_50OHM | IOMUX_SPEED_LOW ) +#define IOMUX_PWM_DEFAULT (IOMUX_SLEW_FAST | \ + IOMUX_DRIVE_50OHM | IOMUX_SPEED_LOW ) + #define IOMUX_USDHC1_DATAX_DEFAULT (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | \ IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER) #define IOMUX_USDHC1_CMD_DEFAULT (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | \ diff --git a/arch/arm/src/imxrt/hardware/imxrt_lpspi.h b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h index 7e648420147..2aefffe3a4a 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_lpspi.h +++ b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_lpspi.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Pavlina Koleva + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/hardware/imxrt_usbotg.h b/arch/arm/src/imxrt/hardware/imxrt_usbotg.h index 0c58f55445e..5921081a2e2 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_usbotg.h +++ b/arch/arm/src/imxrt/hardware/imxrt_usbotg.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_usbotg.h * - * Copyright (C) 2009-2011, 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h index ab9990d919a..9fed4f46d32 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h * - * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. - * Authors: Janne Rosberg - * David Sidrane - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h index 7eadab88b8a..b2d7941d1a3 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h index 7cc56b8c440..7851be548a4 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h index e987ff7d4b4..59ad102020b 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h @@ -1,37 +1,21 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * David Sidrane - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_IOMUXC_H diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h index 859b6ba7d05..5e086f5b13f 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h index 9b1ba6f2798..fa850e3e648 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt102x_daisy.c b/arch/arm/src/imxrt/imxrt102x_daisy.c index 63f57d7860e..bad0169ab47 100644 --- a/arch/arm/src/imxrt/imxrt102x_daisy.c +++ b/arch/arm/src/imxrt/imxrt102x_daisy.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt102x_daisy.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_clrpend.c b/arch/arm/src/imxrt/imxrt_clrpend.c index 9a9f26bdefc..b84831b7ed9 100644 --- a/arch/arm/src/imxrt/imxrt_clrpend.c +++ b/arch/arm/src/imxrt/imxrt_clrpend.c @@ -25,6 +25,7 @@ #include #include +#include #include "nvic.h" #include "arm_arch.h" diff --git a/arch/arm/src/imxrt/imxrt_edma.c b/arch/arm/src/imxrt/imxrt_edma.c index 737c8a112ad..60fa10947cd 100644 --- a/arch/arm/src/imxrt/imxrt_edma.c +++ b/arch/arm/src/imxrt/imxrt_edma.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_ehci.c b/arch/arm/src/imxrt/imxrt_ehci.c index 4576de0ac2f..d5c031c060f 100644 --- a/arch/arm/src/imxrt/imxrt_ehci.c +++ b/arch/arm/src/imxrt/imxrt_ehci.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_ehci.c * - * Copyright (C) 2013-2017, 2020 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_ehci.h b/arch/arm/src/imxrt/imxrt_ehci.h index 5a646999d77..dc4f6ef1c59 100644 --- a/arch/arm/src/imxrt/imxrt_ehci.h +++ b/arch/arm/src/imxrt/imxrt_ehci.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_ehci.h * - * Copyright (C) 2012, 2015, 2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_enc.c b/arch/arm/src/imxrt/imxrt_enc.c index 318e1759155..85168444c90 100644 --- a/arch/arm/src/imxrt/imxrt_enc.c +++ b/arch/arm/src/imxrt/imxrt_enc.c @@ -779,13 +779,22 @@ static int imxrt_enc_test_gen(FAR struct imxrt_enc_lowerhalf_s *priv, return -EINVAL; } + if (value == 0) + { + imxrt_enc_modifyreg16(priv, IMXRT_ENC_TST_OFFSET, + ENC_TST_TCE | ENC_TST_TEN, 0); + return OK; + } + if (value & (1 << 8)) { - imxrt_enc_modifyreg16(priv, IMXRT_ENC_TST_OFFSET, 0, ENC_TST_QDN); + imxrt_enc_modifyreg16(priv, IMXRT_ENC_TST_OFFSET, 0, ENC_TST_QDN + | ENC_TST_TCE | ENC_TST_TEN); } else { - imxrt_enc_modifyreg16(priv, IMXRT_ENC_TST_OFFSET, ENC_TST_QDN, 0); + imxrt_enc_modifyreg16(priv, IMXRT_ENC_TST_OFFSET, ENC_TST_QDN, + ENC_TST_TCE | ENC_TST_TEN); } imxrt_enc_modifyreg16(priv, IMXRT_ENC_TST_OFFSET, 0, @@ -851,8 +860,7 @@ static int imxrt_setup(FAR struct qe_lowerhalf_s *lower) /* Test Registers */ #ifdef CONFIG_DEBUG_SENSORS - regval = ENC_TST_TCE | ENC_TST_TEN; - regval |= config->tst_dir_adv ? ENC_TST_QDN : 0; + regval = config->tst_dir_adv ? ENC_TST_QDN : 0; regval |= (config->tst_period & ENC_TST_PERIOD_MASK) << ENC_TST_PERIOD_SHIFT; imxrt_enc_putreg16(priv, IMXRT_ENC_TST_OFFSET, regval); @@ -872,6 +880,7 @@ static int imxrt_setup(FAR struct qe_lowerhalf_s *lower) imxrt_enc_putreg16(priv, IMXRT_ENC_CTRL2_OFFSET, regval); imxrt_enc_sem_post(priv); + return OK; } diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index 61ed27a1622..d1042d32186 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_flexcan.c b/arch/arm/src/imxrt/imxrt_flexcan.c index dfd4e0b95f0..b2ef5dacda7 100644 --- a/arch/arm/src/imxrt/imxrt_flexcan.c +++ b/arch/arm/src/imxrt/imxrt_flexcan.c @@ -1006,10 +1006,13 @@ static void imxrt_txdone(FAR struct imxrt_driver_s *priv) NETDEV_TXDONE(&priv->dev); #ifdef TX_TIMEOUT_WQ /* We are here because a transmission completed, so the - * corresponding watchdog can be canceled. + * corresponding watchdog can be canceled + * mailbox be set to inactive */ - wd_cancel(priv->txtimeout[mbi]); + wd_cancel(&priv->txtimeout[mbi]); + struct mb_s *mb = &priv->tx[mbi]; + mb->cs.code = CAN_TXMB_INACTIVE; #endif } @@ -1129,7 +1132,9 @@ static int imxrt_flexcan_interrupt(int irq, FAR void *context, static void imxrt_txtimeout_work(FAR void *arg) { FAR struct imxrt_driver_s *priv = (FAR struct imxrt_driver_s *)arg; + uint32_t flags; uint32_t mbi; + uint32_t mb_bit; struct timespec ts; struct timeval *now = (struct timeval *)&ts; @@ -1140,6 +1145,8 @@ static void imxrt_txtimeout_work(FAR void *arg) * transmit function transmitted a new frame */ + flags = getreg32(priv->base + IMXRT_CAN_IFLAG1_OFFSET); + for (mbi = 0; mbi < TXMBCOUNT; mbi++) { if (priv->txmb[mbi].deadline.tv_sec != 0 @@ -1147,6 +1154,14 @@ static void imxrt_txtimeout_work(FAR void *arg) || now->tv_usec > priv->txmb[mbi].deadline.tv_usec)) { NETDEV_TXTIMEOUTS(&priv->dev); + + mb_bit = 1 << (RXMBCOUNT + mbi); + + if (flags & mb_bit) + { + putreg32(mb_bit, priv->base + IMXRT_CAN_IFLAG1_OFFSET); + } + struct mb_s *mb = &priv->tx[mbi]; mb->cs.code = CAN_TXMB_ABORT; priv->txmb[mbi].pending = TX_ABORT; diff --git a/arch/arm/src/imxrt/imxrt_flexpwm.c b/arch/arm/src/imxrt/imxrt_flexpwm.c new file mode 100644 index 00000000000..9864c6f1851 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_flexpwm.c @@ -0,0 +1,1064 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_flexpwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_arch.h" +#include "chip.h" +#include "imxrt_config.h" +#include "imxrt_flexpwm.h" +#include "imxrt_periphclks.h" +#include "hardware/imxrt_flexpwm.h" +#include "hardware/imxrt_pinmux.h" +#include "hardware/imxrt_ccm.h" + +#include + +#include + +#ifdef CONFIG_IMXRT_FLEXPWM + +#ifdef CONFIG_PWM_NCHANNELS +# define PWM_NCHANNELS CONFIG_PWM_NCHANNELS +#else +# define PWM_NCHANNELS 1 +#endif + +#define MODULE_OFFSET 0x60 +#define CLK_FREQ 132000000 +#define PWM_RES 65535 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imxrt_flexpwm_out_s +{ + bool used; + uint32_t pin; /* Output pin */ +}; + +struct imxrt_flexpwm_module_s +{ + uint8_t module; /* Number of PWM module */ + bool used; /* True if the module is used */ + struct imxrt_flexpwm_out_s out_a; /* PWM output */ + struct imxrt_flexpwm_out_s out_b; /* PWM output */ + bool complementary; /* True if outputs are complementary */ + uint32_t irq; /* Combined interrupt */ +}; + +struct imxrt_flexpwm_s +{ + const struct pwm_ops_s *ops; /* PWM operations */ + FAR struct imxrt_flexpwm_module_s *modules; + uint8_t modules_num; /* Number of modules */ + uint32_t frequency; /* PWM frequency */ + uint32_t base; /* Base addres of peripheral register */ +}; + +/* PWM driver methods */ + +static int pwm_setup(FAR struct pwm_lowerhalf_s *dev); +static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev); +static int pwm_start(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info); +static int pwm_stop(FAR struct pwm_lowerhalf_s *dev); +static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/* Helper functions */ + +static int pwm_set_output(FAR struct pwm_lowerhalf_s *dev, uint8_t channel, + ub16_t duty); +static int pwm_change_freq(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info, uint8_t channel); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct pwm_ops_s g_pwmops = +{ + .setup = pwm_setup, + .shutdown = pwm_shutdown, + .start = pwm_start, + .stop = pwm_stop, + .ioctl = pwm_ioctl, +}; + +#ifdef CONFIG_IMXRT_FLEXPWM1 + +static struct imxrt_flexpwm_module_s g_pwm1_modules[] = +{ + /* FlexPWM1 has 4 submodules with 2 outputs for each */ + +#ifdef CONFIG_IMXRT_FLEXPWM1_MOD1 + { + .module = 1, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM1_MOD1_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM1_MOD1_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM1_MOD1_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM1_MOD2 + { + .module = 2, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM1_MOD2_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM1_MOD2_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM1_MOD2_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM1_MOD3 + { + .module = 3, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM1_MOD3_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM1_MOD3_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM1_MOD3_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM1_MOD4 + { + .module = 4, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM1_MOD4_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM1_MOD4_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM1_MOD4_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +}; + +static struct imxrt_flexpwm_s g_pwm1 = +{ + .ops = &g_pwmops, + .modules = g_pwm1_modules, + .modules_num = 4, + .frequency = 0, + .base = IMXRT_FLEXPWM1_BASE, +}; +#endif /* CONFIG_IMXRT_FLEXPWM1 */ + +#ifdef CONFIG_IMXRT_FLEXPWM2 + +static struct imxrt_flexpwm_module_s g_pwm2_modules[] = +{ + /* FlexPWM2 has 4 submodules with 2 outputs for each */ + +#ifdef CONFIG_IMXRT_FLEXPWM2_MOD1 + { + .module = 1, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM2_MOD1_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM2_MOD1_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM2_MOD1_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM2_MOD2 + { + .module = 2, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM2_MOD2_A, + }, +#ifdef CONFIG_IMXRT_FLEXPWM2_MOD2_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM2_MOD2_B + } + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM2_MOD3 + { + .module = 3, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM2_MOD3_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM2_MOD3_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM2_MOD3_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM2_MOD4 + { + .module = 4, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM2_MOD4_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM2_MOD4_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM2_MOD4_B + }, + .complementary = true +#else + .complementary = false +#endif + } +#endif +}; + +static struct imxrt_flexpwm_s g_pwm2 = +{ + .ops = &g_pwmops, + .modules = g_pwm2_modules, + .modules_num = 4, + .frequency = 0, + .base = IMXRT_FLEXPWM2_BASE, +}; +#endif /* CONFIG_IMXRT_FLEXPWM2 */ + +#ifdef CONFIG_IMXRT_FLEXPWM3 + +static struct imxrt_flexpwm_module_s g_pwm3_modules[] = +{ + /* FlexPWM3 has 4 submodules with 2 outputs for each */ + +#ifdef CONFIG_IMXRT_FLEXPWM3_MOD1 + { + .module = 1, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM3_MOD1_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM3_MOD1_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM3_MOD1_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM3_MOD2 + { + .module = 2, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM3_MOD2_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM3_MOD2_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM3_MOD2_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM3_MOD3 + { + .module = 3, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM3_MOD3_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM3_MOD3_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM3_MOD3_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM3_MOD4 + { + .module = 4, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM3_MOD4_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM3_MOD4_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM3_MOD4_B + }, + .complementary = true +#else + .complementary = false +#endif + }, +#endif +}; + +static struct imxrt_flexpwm_s g_pwm3 = +{ + .ops = &g_pwmops, + .modules = g_pwm3_modules, + .modules_num = 4, + .frequency = 0, + .base = IMXRT_FLEXPWM3_BASE, +}; +#endif /* CONFIG_IMXRT_FLEXPWM3 */ + +#ifdef CONFIG_IMXRT_FLEXPWM4 + +static struct imxrt_flexpwm_module_s g_pwm4_modules[] = +{ + /* FlexPWM4 has 4 submodules with 2 outputs for each */ + +#ifdef CONFIG_IMXRT_FLEXPWM4_MOD1 + { + .module = 1, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM4_MOD1_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM4_MOD1_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM4_MOD1_B + } + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM4_MOD2 + { + .module = 2, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM4_MOD2_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM4_MOD2_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM4_MOD2_B + } + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM4_MOD3 + { + .module = 3, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM4_MOD3_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM4_MOD3_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM4_MOD3_B + } + .complementary = true +#else + .complementary = false +#endif + }, +#endif +#ifdef CONFIG_IMXRT_FLEXPWM4_MOD4 + { + .module = 4, + .used = true, + .out_a = + { + .used = true, + .pin = GPIO_FLEXPWM4_MOD4_A + }, +#ifdef CONFIG_IMXRT_FLEXPWM4_MOD3_COMP + .out_b = + { + .used = true, + .pin = GPIO_FLEXPWM4_MOD4_B + } + .complementary = true +#else + .complementary = false +#endif + }, +#endif +}; + +static struct imxrt_flexpwm_s g_pwm4 = +{ + .ops = &g_pwmops, + .modules = g_pwm4_modules, + .modules_num = 4, + .frequency = 0, + .base = IMXRT_FLEXPWM4_BASE, +}; +#endif /* CONFIG_IMXRT_FLEXPWM4 */ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pwm_change_freq + * + * Description: + * Set timer frequency and change registers value to respect that + * frequency. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_change_freq(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info, uint8_t channel) +{ + FAR struct imxrt_flexpwm_s *priv = (FAR struct imxrt_flexpwm_s *)dev; +#ifdef CONFIG_PWM_MULTICHAN + uint8_t shift = info->channels[channel].channel - 1; +#else + uint8_t shift = priv->modules[0].module - 1; +#endif + uint16_t regval; + uint16_t olddiv = getreg16(priv->base + IMXRT_FLEXPWM_SM0VAL1_OFFSET + + MODULE_OFFSET * shift); + uint16_t newdiv = (uint32_t)((float)CLK_FREQ / info->frequency + 0.5f); + uint16_t prescale = 0; + + while (newdiv > PWM_RES && prescale < 7) + { + newdiv = newdiv >> 1; + prescale = prescale + 1; + } + + if (newdiv > PWM_RES) + { + newdiv = PWM_RES; + } + else if (newdiv < 2) + { + newdiv = 2; + } + + regval = getreg16(priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + regval |= MCTRL_CLDOK(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + + regval = SMCTRL_FULL | SMCTRL_PRSC(prescale); + putreg16(regval, priv->base + IMXRT_FLEXPWM_SM0CTRL_OFFSET + + MODULE_OFFSET * shift); + + putreg16(newdiv - 1, priv->base + IMXRT_FLEXPWM_SM0VAL1_OFFSET + + MODULE_OFFSET * shift); + + /* Update VAL0, VAL3 and VAL5 registers */ + + regval = getreg16(priv->base + IMXRT_FLEXPWM_SM0VAL0_OFFSET + + MODULE_OFFSET * shift); + regval = regval * newdiv / olddiv; + putreg16(regval, priv->base + IMXRT_FLEXPWM_SM0VAL0_OFFSET + + MODULE_OFFSET * shift); + + regval = getreg16(priv->base + IMXRT_FLEXPWM_SM0VAL3_OFFSET + + MODULE_OFFSET * shift); + regval = regval * newdiv / olddiv; + putreg16(regval, priv->base + IMXRT_FLEXPWM_SM0VAL3_OFFSET + + MODULE_OFFSET * shift); + + regval = getreg16(priv->base + IMXRT_FLEXPWM_SM0VAL5_OFFSET + + MODULE_OFFSET * shift); + regval = regval * newdiv / olddiv; + putreg16(regval, priv->base + IMXRT_FLEXPWM_SM0VAL5_OFFSET + + MODULE_OFFSET * shift); + + regval = getreg16(priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + regval |= MCTRL_LDOK(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + + return OK; +} + +/**************************************************************************** + * Name: pwm_set_output + * + * Description: + * Set duty cycle and enable PWM output. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * channel - Channel to by updated + * duty - New duty + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_set_output(FAR struct pwm_lowerhalf_s *dev, uint8_t channel, + ub16_t duty) +{ + FAR struct imxrt_flexpwm_s *priv = (FAR struct imxrt_flexpwm_s *)dev; + uint16_t period; + uint16_t width; + uint16_t regval; + double duty_pct; + uint8_t shift = channel - 1; /* Shift submodle offset addresses */ + + /* Get the period value */ + + period = getreg16(priv->base + IMXRT_FLEXPWM_SM0VAL1_OFFSET + + MODULE_OFFSET * shift); + + /* Compute PWM width (count value to set PWM low) */ + + duty_pct = (duty / 65536.0) * 100; + width = (uint16_t)(((uint16_t)duty_pct * period) / 100); + + /* Clear corresponding MCTRL[LDOK] bit */ + + regval = getreg16(priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + regval |= MCTRL_CLDOK(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + + /* Write width to value register 3 and enable output A */ + + putreg16(width, priv->base + IMXRT_FLEXPWM_SM0VAL3_OFFSET + + MODULE_OFFSET * shift); + + regval = getreg16(priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); + regval |= OUTEN_PWMA_EN(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); + + /* Enable output B if complementary option is turn on */ + + if (priv->modules[shift].complementary) + { + regval = getreg16(priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); + regval |= OUTEN_PWMB_EN(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); + } + + regval = getreg16(priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + regval |= MCTRL_LDOK(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + + return OK; +} + +/**************************************************************************** + * Name: pwm_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct imxrt_flexpwm_s *priv = (FAR struct imxrt_flexpwm_s *)dev; + uint32_t pin = 0; + uint16_t regval; + uint8_t shift; + + putreg16(FCTRL0_FLVL(15), priv->base + IMXRT_FLEXPWM_FCTRL0_OFFSET); + putreg16(0x000f, priv->base + IMXRT_FLEXPWM_FSTS0_OFFSET); + putreg16(0, priv->base + IMXRT_FLEXPWM_FFILT0_OFFSET); + + for (int i = 0; i < priv->modules_num; i++) + { + /* Configure the module only if is set to be used */ + + if (priv->modules[i].used != 1) + { + continue; + } + + if (priv->modules[i].out_a.used) + { + pin = priv->modules[i].out_a.pin; + if (pin != 0) + { + imxrt_config_gpio(pin); + } + } + + /* Configure PIN_B if complementary option is turn on */ + + if (priv->modules[i].complementary) + { + if (priv->modules[i].out_b.used) + { + pin = priv->modules[i].out_b.pin; + if (pin != 0) + { + imxrt_config_gpio(pin); + } + } + } + + shift = priv->modules[i].module - 1; + + regval = getreg16(priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + regval |= MCTRL_CLDOK(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + + /* Set control registers 1 and 2 */ + + if (!priv->modules[i].complementary) + { + /* Enable independent PWM_A and PWM_B output */ + + regval = SMCTRL2_INDEP; + putreg16(regval, priv->base + IMXRT_FLEXPWM_SM0CTRL2_OFFSET + + MODULE_OFFSET * shift); + } + + regval = SMCTRL_FULL; /* Enable full read cycle reload */ + putreg16(regval, priv->base + IMXRT_FLEXPWM_SM0CTRL_OFFSET + + MODULE_OFFSET * shift); + + /* Set output control register */ + + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0OCTRL_OFFSET + + MODULE_OFFSET * shift); + + /* Set deadtime count register 0 */ + + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0DTCNT0_OFFSET + + MODULE_OFFSET * shift); + + /* Set initial count register */ + + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0INIT_OFFSET + + MODULE_OFFSET * shift); + + /* Set value registers */ + + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL0_OFFSET + + MODULE_OFFSET * shift); + putreg16(0x82b8, priv->base + IMXRT_FLEXPWM_SM0VAL1_OFFSET + + MODULE_OFFSET * shift); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL2_OFFSET + + MODULE_OFFSET * shift); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL3_OFFSET + + MODULE_OFFSET * shift); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL4_OFFSET + + MODULE_OFFSET * shift); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL5_OFFSET + + MODULE_OFFSET * shift); + + regval = getreg16(priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + regval |= MCTRL_LDOK(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + + regval = getreg16(priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + regval |= MCTRL_RUN(1 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + } + + return OK; +} + +/**************************************************************************** + * Name: pwm_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct imxrt_flexpwm_s *priv = (FAR struct imxrt_flexpwm_s *)dev; + + for (int i = 0; i < priv->modules_num; i++) + { + /* Skip modules that are not used */ + + if (priv->modules[i].used != 1) + { + continue; + } + + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0CTRL_OFFSET + + MODULE_OFFSET * i); + + /* Reset fractional value registers */ + + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL0_OFFSET + + MODULE_OFFSET * i); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL1_OFFSET + + MODULE_OFFSET * i); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL2_OFFSET + + MODULE_OFFSET * i); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL3_OFFSET + + MODULE_OFFSET * i); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL4_OFFSET + + MODULE_OFFSET * i); + putreg16(0, priv->base + IMXRT_FLEXPWM_SM0VAL5_OFFSET + + MODULE_OFFSET * i); + } + + /* Stop run */ + + putreg16(0, priv->base + IMXRT_FLEXPWM_MCTRL_OFFSET); + + return OK; +} + +/**************************************************************************** + * Name: pwm_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_start(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info) +{ + FAR struct imxrt_flexpwm_s *priv = (FAR struct imxrt_flexpwm_s *)dev; + int ret = OK; + + /* Change frequency only if it is needed */ + + if (info->frequency != priv->frequency) + { + for (int i = 0; i < PWM_NCHANNELS; i++) + { + /* Configure the module freq only if is set to be used */ + + ret = pwm_change_freq(dev, info, i); + } + + /* Save current frequency */ + + if (ret == OK) + { + priv->frequency = info->frequency; + } + } + +#ifdef CONFIG_PWM_MULTICHAN + for (int i = 0; ret == OK && i < PWM_NCHANNELS; i++) + { + /* Enable PWM output for each channel */ + + ret = pwm_set_output(dev, info->channels[i].channel, + info->channels[i].duty); + } +#else + /* Enable PWM output just for first channel */ + + ret = pwm_set_output(dev, priv->modules[0].module, info->duty); +#endif /* CONFIG_PWM_MULTICHAN */ + + return ret; +} + +/**************************************************************************** + * Name: pwm_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. This + * method is also called from the timer interrupt handler when a repetition + * count expires... automatically stopping the timer. + * + ****************************************************************************/ + +static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct imxrt_flexpwm_s *priv = (FAR struct imxrt_flexpwm_s *)dev; + uint8_t shift; + uint16_t regval; + +#ifdef CONFIG_PWM_MULTICHAN + for (int i = 0; i < priv->modules_num; i++) + { + /* Skip settings if channel is not configured */ + + if (!priv->modules[i].used) + { + continue; + } + + shift = priv->modules[i].module - 1; + + regval = OUTEN_PWMA_EN(0 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); + + regval = OUTEN_PWMB_EN(0 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); + } +#else + shift = priv->modules[0].module - 1; + + regval = OUTEN_PWMA_EN(0 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); + + regval = OUTEN_PWMB_EN(0 << shift); + putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); + +#endif /* CONFIG_PWM_MULTICHAN */ + + return OK; +} + +/**************************************************************************** + * Name: pwm_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imxrt_pwminitialize + * + * Description: + * Initialize the PWM channel for use with the upper level PWM driver. + * + * Input Parameters: + * channel - a number identifying the PWM channel. + * + * Returned Value: + * A pointer to the lower half PWM driver is returned on success, + * NULL on failure. + * + ****************************************************************************/ + +FAR struct pwm_lowerhalf_s *imxrt_pwminitialize(int pwm) +{ + FAR struct imxrt_flexpwm_s *priv; + + pwminfo("Initializing pwm %d\n", pwm); + + switch (pwm) + { +#ifdef CONFIG_IMXRT_FLEXPWM1 + case 1: + imxrt_clockall_pwm1(); + priv = &g_pwm1; + break; +#endif +#ifdef CONFIG_IMXRT_FLEXPWM2 + case 2: + imxrt_clockall_pwm2(); + priv = &g_pwm2; + break; +#endif +#ifdef CONFIG_IMXRT_FLEXPWM3 + case 3: + imxrt_clockall_pwm3(); + priv = &g_pwm3; + break; +#endif +#ifdef CONFIG_IMXRT_FLEXPWM4 + case 4: + imxrt_clockall_pwm4(); + priv = &g_pwm4; + break; +#endif + default: + pwmerr("ERROR: PWM number invalid or not configured %d\n", pwm); + return NULL; + } + + return (FAR struct pwm_lowerhalf_s *)priv; +} +#endif /* CONFIG_IMXRT_FLEXPWM */ diff --git a/arch/arm/src/imxrt/imxrt_flexpwm.h b/arch/arm/src/imxrt/imxrt_flexpwm.h new file mode 100644 index 00000000000..591fd8bc71e --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_flexpwm.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_flexpwm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_FLEXPWM_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_FLEXPWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "hardware/imxrt_flexpwm.h" + +#ifdef CONFIG_IMXRT_FLEXPWM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Function: imxrt_pwminitialize + * + * Description: + * Initialize the PWM module for use with the upper level PWM driver. + * + * Input Parameters: + * pwm - a number identifying the PWM driver. + * + * Returned Value: + * A pointer to the lower half PWM driver is returned on success, + * NULL on failure. + * + ****************************************************************************/ + +FAR struct pwm_lowerhalf_s *imxrt_pwminitialize(int pwm); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_IMXRT_FLEXPWM */ +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_FLEXPWM_H */ diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c index b0bb6551179..85ab32ef897 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.c +++ b/arch/arm/src/imxrt/imxrt_gpio.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_gpio.c * - * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_hprtc.c b/arch/arm/src/imxrt/imxrt_hprtc.c index fb15ad66b27..d6861562b34 100644 --- a/arch/arm/src/imxrt/imxrt_hprtc.c +++ b/arch/arm/src/imxrt/imxrt_hprtc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_idle.c b/arch/arm/src/imxrt/imxrt_idle.c index 4eaf00a18d5..4e8e5c87252 100644 --- a/arch/arm/src/imxrt/imxrt_idle.c +++ b/arch/arm/src/imxrt/imxrt_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/imxrt/imxrt_irq.c b/arch/arm/src/imxrt/imxrt_irq.c index db3d852e348..6f38413a222 100644 --- a/arch/arm/src/imxrt/imxrt_irq.c +++ b/arch/arm/src/imxrt/imxrt_irq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_lcd.c b/arch/arm/src/imxrt/imxrt_lcd.c index 2a1e81ecd6b..fbc662e5371 100644 --- a/arch/arm/src/imxrt/imxrt_lcd.c +++ b/arch/arm/src/imxrt/imxrt_lcd.c @@ -45,6 +45,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c index 8effc1f663f..534a92feed1 100644 --- a/arch/arm/src/imxrt/imxrt_lpi2c.c +++ b/arch/arm/src/imxrt/imxrt_lpi2c.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index 238b058517a..ccf50c13fbb 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include @@ -1260,7 +1261,7 @@ static uint32_t imxrt_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed diff --git a/arch/arm/src/imxrt/imxrt_lpsrtc.c b/arch/arm/src/imxrt/imxrt_lpsrtc.c index 1253ee4704c..521acca0fca 100644 --- a/arch/arm/src/imxrt/imxrt_lpsrtc.c +++ b/arch/arm/src/imxrt/imxrt_lpsrtc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_periphclks.h b/arch/arm/src/imxrt/imxrt_periphclks.h index c0a7c7d151b..e71aea4937d 100644 --- a/arch/arm/src/imxrt/imxrt_periphclks.h +++ b/arch/arm/src/imxrt/imxrt_periphclks.h @@ -144,7 +144,9 @@ #define imxrt_clockoff_wdog3() imxrt_periphclk_configure(CCM_CCGR_WDOG3, CCM_CG_OFF) #define imxrt_clockoff_xbar1() imxrt_periphclk_configure(CCM_CCGR_XBAR1, CCM_CG_OFF) #define imxrt_clockoff_xbar2() imxrt_periphclk_configure(CCM_CCGR_XBAR2, CCM_CG_OFF) +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) #define imxrt_clockoff_xbar3() imxrt_periphclk_configure(CCM_CCGR_XBAR3, CCM_CG_OFF) +#endif /* Clock is on in run mode, but off in WAIT and STOP modes. */ @@ -255,7 +257,9 @@ #define imxrt_clockrun_wdog3() imxrt_periphclk_configure(CCM_CCGR_WDOG3, CCM_CG_RUN) #define imxrt_clockrun_xbar1() imxrt_periphclk_configure(CCM_CCGR_XBAR1, CCM_CG_RUN) #define imxrt_clockrun_xbar2() imxrt_periphclk_configure(CCM_CCGR_XBAR2, CCM_CG_RUN) +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) #define imxrt_clockrun_xbar3() imxrt_periphclk_configure(CCM_CCGR_XBAR3, CCM_CG_RUN) +#endif /* Clock is on during all modes, except STOP mode. */ @@ -366,7 +370,9 @@ #define imxrt_clockall_wdog3() imxrt_periphclk_configure(CCM_CCGR_WDOG3, CCM_CG_ALL) #define imxrt_clockall_xbar1() imxrt_periphclk_configure(CCM_CCGR_XBAR1, CCM_CG_ALL) #define imxrt_clockall_xbar2() imxrt_periphclk_configure(CCM_CCGR_XBAR2, CCM_CG_ALL) +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) #define imxrt_clockall_xbar3() imxrt_periphclk_configure(CCM_CCGR_XBAR3, CCM_CG_ALL) +#endif #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c b/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c index 116c41eaa19..0712e62487b 100644 --- a/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c +++ b/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index 65076760e25..2b9fc124d95 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c index 205d46e74cf..681910d7761 100644 --- a/arch/arm/src/imxrt/imxrt_start.c +++ b/arch/arm/src/imxrt/imxrt_start.c @@ -73,10 +73,6 @@ #ifdef CONFIG_ARCH_FPU static inline void imxrt_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Private Functions @@ -226,47 +222,6 @@ static inline void imxrt_tcmenable(void) #endif } -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -375,17 +330,9 @@ void __start(void) /* Then start NuttX */ -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/imxrt/imxrt_timerisr.c b/arch/arm/src/imxrt/imxrt_timerisr.c index 7ea757dc4c4..eade31cc92a 100644 --- a/arch/arm/src/imxrt/imxrt_timerisr.c +++ b/arch/arm/src/imxrt/imxrt_timerisr.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_usbdev.c b/arch/arm/src/imxrt/imxrt_usbdev.c index 3dc548d3453..185303adaa4 100644 --- a/arch/arm/src/imxrt/imxrt_usbdev.c +++ b/arch/arm/src/imxrt/imxrt_usbdev.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c index 4665be2be0d..78cb199eb04 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.c +++ b/arch/arm/src/imxrt/imxrt_usdhc.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_usdhc.c * - * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples - * Ivan Ucherdzhiev + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_xbar.c b/arch/arm/src/imxrt/imxrt_xbar.c index df97ae4299a..695a67df9b3 100644 --- a/arch/arm/src/imxrt/imxrt_xbar.c +++ b/arch/arm/src/imxrt/imxrt_xbar.c @@ -82,6 +82,23 @@ int imxrt_xbar_connect(uint16_t mux_index_out, uint16_t mux_index_input) xbar_index = IMXRT_XBAR(mux_index_out); clearbits = IMXRT_SEL0_MASK; + switch (xbar_index) + { + case 0: + imxrt_clockall_xbar1(); + break; + case 1: + imxrt_clockall_xbar2(); + break; + case 2: +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) + imxrt_clockall_xbar3(); + break; +#endif + default: + break; + } + /* Verify: * 1) The Xbar index is valid. * 2) In and out are on the same Xbar. diff --git a/arch/arm/src/imxrt/imxrt_xbar.h b/arch/arm/src/imxrt/imxrt_xbar.h index f974856e34b..46b50c28eaa 100644 --- a/arch/arm/src/imxrt/imxrt_xbar.h +++ b/arch/arm/src/imxrt/imxrt_xbar.h @@ -29,6 +29,7 @@ #include #include "hardware/imxrt_xbar.h" #include "hardware/imxrt_memorymap.h" +#include "imxrt_periphclks.h" /* Collect correct XBAR definitions from chip file */ diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig index 5cdc32bf6a6..cbda473db51 100644 --- a/arch/arm/src/kinetis/Kconfig +++ b/arch/arm/src/kinetis/Kconfig @@ -330,6 +330,11 @@ config KINETIS_HAVE_DMA bool default n +config KINETIS_SPI + bool + default n + select SPI + config KINETIS_HAVE_I2C1 bool default n @@ -536,14 +541,14 @@ config KINETIS_FLEXCAN1 config KINETIS_SPI0 bool "SPI0" default n - select SPI + select KINETIS_SPI ---help--- Support SPI0 config KINETIS_SPI1 bool "SPI1" default n - select SPI + select KINETIS_SPI depends on KINETIS_HAVE_SPI1 ---help--- Support SPI1 @@ -551,7 +556,7 @@ config KINETIS_SPI1 config KINETIS_SPI2 bool "SPI2" default n - select SPI + select KINETIS_SPI depends on KINETIS_HAVE_SPI2 ---help--- Support SPI2 @@ -751,8 +756,8 @@ config KINETIS_FTFL ---help--- Support FLASH -config KINETIS_DMA - bool "DMA" +config KINETIS_EDMA + bool "eDMA" default n depends on KINETIS_HAVE_DMA select ARCH_DMA @@ -1114,6 +1119,138 @@ config KINETIS_SD4BIT_FREQ endif endmenu # Kinetis SDHC Configuration +menu "eDMA Configuration" + depends on KINETIS_EDMA + +config KINETIS_EDMA_NTCD + int "Number of transfer descriptors" + default 0 + ---help--- + Number of pre-allocated transfer descriptors. Needed for scatter- + gather DMA. Make to be set to zero to disable in-memory TCDs in + which case only the TCD channel registers will be used and scatter- + will not be supported. + +config KINETIS_EDMA_ELINK + bool "Channeling Linking" + default n + ---help--- + This option enables optional minor or major loop channel linking: + + Minor loop channel linking: As the channel completes the minor + loop, this flag enables linking to another channel. The link target + channel initiates a channel service request via an internal + mechanism that sets the TCDn_CSR[START] bit of the specified + channel. + + If minor loop channel linking is disabled, this link mechanism is + suppressed in favor of the major loop channel linking. + + Major loop channel linking: As the channel completes the minor + loop, this option enables the linking to another channel. The link + target channel initiates a channel service request via an internal + mechanism that sets the TCDn_CSR[START] bit of the linked channel. + +config KINETIS_EDMA_ERCA + bool "Round Robin Channel Arbitration" + default n + ---help--- + Normally, a fixed priority arbitration is used for channel + selection. If this option is selected, round robin arbitration is + used for channel selection. + +config KINETIS_EDMA_ERGA + bool "Round Robin Group Arbitration" + default n + ---help--- + Normally, a fixed priority arbitration is used for channel + selection among the groups. If this option is selected, + round Round robin arbitration is used for selection among + the groups. + +config KINETIS_EDMA_HOE + bool "Halt On Error" + default y + ---help--- + Any error causes the HALT bit to set. Subsequently, all service + requests are ignored until the HALT bit is cleared. + +config KINETIS_EDMA_CLM + bool "Continuous Link Mode" + default n + ---help--- + By default, A minor loop channel link made to itself goes through + channel arbitration before being activated again. If this option is + selected, a minor loop channel link made to itself does not go + through channel arbitration before being activated again. Upon minor + loop completion, the channel activates again if that channel has a + minor loop channel link enabled and the link channel is itself. This + effectively applies the minor loop offsets and restarts the next + minor loop. + +config KINETIS_EDMA_EMLIM + bool "Minor Loop Mapping" + default n + ---help--- + Normally TCD word 2 is a 32-bit NBYTES field. When this option is + enabled, TCD word 2 is redefined to include individual enable fields, + an offset field, and the NBYTES field. The individual enable fields + allow the minor loop offset to be applied to the source address, the + destination address, or both. The NBYTES field is reduced when either + offset is enabled. + +config KINETIS_EDMA_EDBG + bool "Enable Debug" + default n + ---help--- + When in debug mode, the DMA stalls the start of a new channel. Executing + channels are allowed to complete. Channel execution resumes when the + system exits debug mode or the EDBG bit is cleared + +endmenu # eDMA Global Configuration + +menu "Kinetis SPI Configuration" + depends on KINETIS_SPI && KINETIS_EDMA + +config KINETIS_SPI_DMA + bool "SPI DMA" + depends on KINETIS_EDMA + default n + ---help--- + Use DMA to improve SPI transfer performance. + +config KINETIS_SPI_DMATHRESHOLD + int "SPI DMA threshold" + default 4 + depends on KINETIS_SPI_DMA + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config KINETIS_SPI0_DMA + bool "SPI0 DMA" + default n + depends on KINETIS_SPI0 && KINETIS_SPI_DMA + ---help--- + Use DMA to improve SPI0 transfer performance. + +config KINETIS_SPI1_DMA + bool "SPI1 DMA" + default n + depends on KINETIS_SPI1 && KINETIS_SPI_DMA + ---help--- + Use DMA to improve SPI1 transfer performance. + +config KINETIS_SPI2_DMA + bool "SPI2 DMA" + default n + depends on KINETIS_SPI2 && KINETIS_SPI_DMA + ---help--- + Use DMA to improve SPI2 transfer performance. + +endmenu # Kinetis SPI Configuration + if KINETIS_USBHS && USBHOST menu "USB host controller driver (HCD) options" @@ -1208,42 +1345,42 @@ config KINETIS_UARTFIFOS config KINETIS_UART0_RXDMA bool "UART0 Rx DMA" default n - depends on KINETIS_UART0 && KINETIS_DMA + depends on KINETIS_UART0 && KINETIS_EDMA ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors config KINETIS_UART1_RXDMA bool "UART1 Rx DMA" default n - depends on KINETIS_UART1 && KINETIS_DMA + depends on KINETIS_UART1 && KINETIS_EDMA ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors config KINETIS_UART2_RXDMA bool "UART2 Rx DMA" default n - depends on KINETIS_UART2 && KINETIS_DMA + depends on KINETIS_UART2 && KINETIS_EDMA ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors config KINETIS_UART3_RXDMA bool "UART3 Rx DMA" default n - depends on KINETIS_UART3 && KINETIS_DMA + depends on KINETIS_UART3 && KINETIS_EDMA ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors config KINETIS_UART4_RXDMA bool "UART4 Rx DMA" default n - depends on KINETIS_UART4 && KINETIS_DMA + depends on KINETIS_UART4 && KINETIS_EDMA ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors config KINETIS_UART5_RXDMA bool "UART5 Rx DMA" default n - depends on KINETIS_UART5 && KINETIS_DMA + depends on KINETIS_UART5 && KINETIS_EDMA ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index 0f2fd14063d..6fd81e4a006 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -51,6 +51,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif @@ -139,8 +140,8 @@ CHIP_CSRCS += kinetis_usbhshost.c endif endif -ifeq ($(CONFIG_KINETIS_DMA),y) -CHIP_CSRCS += kinetis_dma.c kinetis_pindma.c +ifeq ($(CONFIG_KINETIS_EDMA),y) +CHIP_CSRCS += kinetis_edma.c kinetis_pindma.c endif ifeq ($(CONFIG_PWM),y) diff --git a/arch/arm/src/kinetis/hardware/kinetis_dma.h b/arch/arm/src/kinetis/hardware/kinetis_dma.h deleted file mode 100644 index bd2b941c72f..00000000000 --- a/arch/arm/src/kinetis/hardware/kinetis_dma.h +++ /dev/null @@ -1,776 +0,0 @@ -/**************************************************************************** - * arch/arm/src/kinetis/hardware/kinetis_dma.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H -#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define KINETIS_DMA_CR_OFFSET 0x0000 /* Control Register */ -#define KINETIS_DMA_ES_OFFSET 0x0004 /* Error Status Register */ -#define KINETIS_DMA_ERQ_OFFSET 0x000c /* Enable Request Register */ -#define KINETIS_DMA_EEI_OFFSET 0x0014 /* Enable Error Interrupt Register */ -#define KINETIS_DMA_CEEI_OFFSET 0x0018 /* Clear Enable Error Interrupt Register */ -#define KINETIS_DMA_SEEI_OFFSET 0x0019 /* Set Enable Error Interrupt Register */ -#define KINETIS_DMA_CERQ_OFFSET 0x001a /* Clear Enable Request Register */ -#define KINETIS_DMA_SERQ_OFFSET 0x001b /* Set Enable Request Register */ -#define KINETIS_DMA_CDNE_OFFSET 0x001c /* Clear DONE Status Bit Register */ -#define KINETIS_DMA_SSRT_OFFSET 0x001d /* Set START Bit Register */ -#define KINETIS_DMA_CERR_OFFSET 0x001e /* Clear Error Register */ -#define KINETIS_DMA_CINT_OFFSET 0x001f /* Clear Interrupt Request Register */ -#define KINETIS_DMA_INT_OFFSET 0x0024 /* Interrupt Request Register */ -#define KINETIS_DMA_ERR_OFFSET 0x002c /* Error Register */ -#define KINETIS_DMA_HRS_OFFSET 0x0034 /* Hardware Request Status Register */ - -#define KINETIS_DMA_DCHPRI3_OFFSET 0x0100 /* Channel 3 Priority Register */ -#define KINETIS_DMA_DCHPRI2_OFFSET 0x0101 /* Channel 2 Priority Register */ -#define KINETIS_DMA_DCHPRI1_OFFSET 0x0102 /* Channel 1 Priority Register */ -#define KINETIS_DMA_DCHPRI0_OFFSET 0x0103 /* Channel 0 Priority Register */ -#define KINETIS_DMA_DCHPRI7_OFFSET 0x0104 /* Channel 7 Priority Register */ -#define KINETIS_DMA_DCHPRI6_OFFSET 0x0105 /* Channel 6 Priority Register */ -#define KINETIS_DMA_DCHPRI5_OFFSET 0x0106 /* Channel 5 Priority Register */ -#define KINETIS_DMA_DCHPRI4_OFFSET 0x0107 /* Channel 4 Priority Register */ -#define KINETIS_DMA_DCHPRI11_OFFSET 0x0108 /* Channel 11 Priority Register */ -#define KINETIS_DMA_DCHPRI10_OFFSET 0x0109 /* Channel 10 Priority Register */ -#define KINETIS_DMA_DCHPRI9_OFFSET 0x010a /* Channel 9 Priority Register */ -#define KINETIS_DMA_DCHPRI8_OFFSET 0x010b /* Channel 8 Priority Register */ -#define KINETIS_DMA_DCHPRI15_OFFSET 0x010c /* Channel 15 Priority Register */ -#define KINETIS_DMA_DCHPRI14_OFFSET 0x010d /* Channel 14 Priority Register */ -#define KINETIS_DMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority Register */ -#define KINETIS_DMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority Register */ - -#define KINETIS_DMA_DCHPRI_OFFSET(n) 0x0100 + (n - (n % 4)) + (3 - (n % 4)) /* Channel n Priority Register */ - -#define KINETIS_DMA_TCD_OFFSET(n) (0x0000 + ((n) << 5)) -#define KINETIS_DMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */ -#define KINETIS_DMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */ -#define KINETIS_DMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */ -#define KINETIS_DMA_TCD_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD0_SADDR_OFFSET 0x0000 /* TCD Source Address */ -#define KINETIS_DMA_TCD0_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD0_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD0_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD0_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD0_DADDR_OFFSET 0x0010 /* TCD Destination Address */ -#define KINETIS_DMA_TCD0_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD0_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD0_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD0_CSR_OFFSET 0x001c /* TCD Control and Status */ -#define KINETIS_DMA_TCD0_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD1_SADDR_OFFSET 0x0020 /* TCD Source Address */ -#define KINETIS_DMA_TCD1_SOFF_OFFSET 0x0024 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD1_ATTR_OFFSET 0x0026 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD1_NBYTES_OFFSET 0x0028 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD1_SLAST_OFFSET 0x002c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD1_DADDR_OFFSET 0x0030 /* TCD Destination Address */ -#define KINETIS_DMA_TCD1_DOFF_OFFSET 0x0034 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD1_CITER_OFFSET 0x0036 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD1_DLASTSGA_OFFSET 0x0038 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD1_CSR_OFFSET 0x003c /* TCD Control and Status */ -#define KINETIS_DMA_TCD1_BITER_OFFSET 0x003e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD2_SADDR_OFFSET 0x0040 /* TCD Source Address */ -#define KINETIS_DMA_TCD2_SOFF_OFFSET 0x0044 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD2_ATTR_OFFSET 0x0046 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD2_NBYTES_OFFSET 0x0048 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD2_SLAST_OFFSET 0x004c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD2_DADDR_OFFSET 0x0050 /* TCD Destination Address */ -#define KINETIS_DMA_TCD2_DOFF_OFFSET 0x0054 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD2_CITER_OFFSET 0x0056 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD2_DLASTSGA_OFFSET 0x0058 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD2_CSR_OFFSET 0x005c /* TCD Control and Status */ -#define KINETIS_DMA_TCD2_BITER_OFFSET 0x005e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD3_SADDR_OFFSET 0x0060 /* TCD Source Address */ -#define KINETIS_DMA_TCD3_SOFF_OFFSET 0x0064 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD3_ATTR_OFFSET 0x0066 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD3_NBYTES_OFFSET 0x0068 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD3_SLAST_OFFSET 0x006c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD3_DADDR_OFFSET 0x0070 /* TCD Destination Address */ -#define KINETIS_DMA_TCD3_DOFF_OFFSET 0x0074 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD3_CITER_OFFSET 0x0076 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD3_DLASTSGA_OFFSET 0x0078 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD3_CSR_OFFSET 0x007c /* TCD Control and Status */ -#define KINETIS_DMA_TCD3_BITER_OFFSET 0x007e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD4_SADDR_OFFSET 0x0080 /* TCD Source Address */ -#define KINETIS_DMA_TCD4_SOFF_OFFSET 0x0084 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD4_ATTR_OFFSET 0x0086 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD4_NBYTES_OFFSET 0x0088 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD4_SLAST_OFFSET 0x008c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD4_DADDR_OFFSET 0x0090 /* TCD Destination Address */ -#define KINETIS_DMA_TCD4_DOFF_OFFSET 0x0094 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD4_CITER_OFFSET 0x0096 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD4_DLASTSGA_OFFSET 0x0098 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD4_CSR_OFFSET 0x009c /* TCD Control and Status */ -#define KINETIS_DMA_TCD4_BITER_OFFSET 0x009e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD5_SADDR_OFFSET 0x00a0 /* TCD Source Address */ -#define KINETIS_DMA_TCD5_SOFF_OFFSET 0x00a4 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD5_ATTR_OFFSET 0x00a6 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD5_NBYTES_OFFSET 0x00a8 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD5_SLAST_OFFSET 0x00ac /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD5_DADDR_OFFSET 0x00b0 /* TCD Destination Address */ -#define KINETIS_DMA_TCD5_DOFF_OFFSET 0x00b4 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD5_CITER_OFFSET 0x00b6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD5_DLASTSGA_OFFSET 0x00b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD5_CSR_OFFSET 0x00bc /* TCD Control and Status */ -#define KINETIS_DMA_TCD5_BITER_OFFSET 0x00be /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD6_SADDR_OFFSET 0x00c0 /* TCD Source Address */ -#define KINETIS_DMA_TCD6_SOFF_OFFSET 0x00c4 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD6_ATTR_OFFSET 0x00c6 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD6_NBYTES_OFFSET 0x00c8 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD6_SLAST_OFFSET 0x00cc /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD6_DADDR_OFFSET 0x00d0 /* TCD Destination Address */ -#define KINETIS_DMA_TCD6_DOFF_OFFSET 0x00d4 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD6_CITER_OFFSET 0x00d6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD6_DLASTSGA_OFFSET 0x00d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD6_CSR_OFFSET 0x00dc /* TCD Control and Status */ -#define KINETIS_DMA_TCD6_BITER_OFFSET 0x00de /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD7_SADDR_OFFSET 0x00e0 /* TCD Source Address */ -#define KINETIS_DMA_TCD7_SOFF_OFFSET 0x00e4 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD7_ATTR_OFFSET 0x00e6 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD7_NBYTES_OFFSET 0x00e8 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD7_SLAST_OFFSET 0x00ec /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD7_DADDR_OFFSET 0x00f0 /* TCD Destination Address */ -#define KINETIS_DMA_TCD7_DOFF_OFFSET 0x00f4 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD7_CITER_OFFSET 0x00f6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD7_DLASTSGA_OFFSET 0x00f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD7_CSR_OFFSET 0x00fc /* TCD Control and Status */ -#define KINETIS_DMA_TCD7_BITER_OFFSET 0x00fe /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD8_SADDR_OFFSET 0x0100 /* TCD Source Address */ -#define KINETIS_DMA_TCD8_SOFF_OFFSET 0x0104 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD8_ATTR_OFFSET 0x0106 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD8_NBYTES_OFFSET 0x0108 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD8_SLAST_OFFSET 0x010c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD8_DADDR_OFFSET 0x0110 /* TCD Destination Address */ -#define KINETIS_DMA_TCD8_DOFF_OFFSET 0x0114 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD8_CITER_OFFSET 0x0116 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD8_DLASTSGA_OFFSET 0x0118 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD8_CSR_OFFSET 0x011c /* TCD Control and Status */ -#define KINETIS_DMA_TCD8_BITER_OFFSET 0x011e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD9_SADDR_OFFSET 0x0120 /* TCD Source Address */ -#define KINETIS_DMA_TCD9_SOFF_OFFSET 0x0124 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD9_ATTR_OFFSET 0x0126 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD9_NBYTES_OFFSET 0x0128 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD9_SLAST_OFFSET 0x012c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD9_DADDR_OFFSET 0x0130 /* TCD Destination Address */ -#define KINETIS_DMA_TCD9_DOFF_OFFSET 0x0134 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD9_CITER_OFFSET 0x0136 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD9_DLASTSGA_OFFSET 0x0138 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD9_CSR_OFFSET 0x013c /* TCD Control and Status */ -#define KINETIS_DMA_TCD9_BITER_OFFSET 0x013e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD10_SADDR_OFFSET 0x0140 /* TCD Source Address */ -#define KINETIS_DMA_TCD10_SOFF_OFFSET 0x0144 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD10_ATTR_OFFSET 0x0146 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD10_NBYTES_OFFSET 0x0148 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD10_SLAST_OFFSET 0x014c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD10_DADDR_OFFSET 0x0150 /* TCD Destination Address */ -#define KINETIS_DMA_TCD10_DOFF_OFFSET 0x0154 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD10_CITER_OFFSET 0x0156 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD10_DLASTSGA_OFFSET 0x0158 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD10_CSR_OFFSET 0x015c /* TCD Control and Status */ -#define KINETIS_DMA_TCD10_BITER_OFFSET 0x015e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD11_SADDR_OFFSET 0x0160 /* TCD Source Address */ -#define KINETIS_DMA_TCD11_SOFF_OFFSET 0x0164 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD11_ATTR_OFFSET 0x0166 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD11_NBYTES_OFFSET 0x0168 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD11_SLAST_OFFSET 0x016c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD11_DADDR_OFFSET 0x0170 /* TCD Destination Address */ -#define KINETIS_DMA_TCD11_DOFF_OFFSET 0x0174 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD11_CITER_OFFSET 0x0176 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD11_DLASTSGA_OFFSET 0x0178 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD11_CSR_OFFSET 0x017c /* TCD Control and Status */ -#define KINETIS_DMA_TCD11_BITER_OFFSET 0x017e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD12_SADDR_OFFSET 0x0180 /* TCD Source Address */ -#define KINETIS_DMA_TCD12_SOFF_OFFSET 0x0184 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD12_ATTR_OFFSET 0x0186 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD12_NBYTES_OFFSET 0x0188 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD12_SLAST_OFFSET 0x018c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD12_DADDR_OFFSET 0x0190 /* TCD Destination Address */ -#define KINETIS_DMA_TCD12_DOFF_OFFSET 0x0194 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD12_CITER_OFFSET 0x0196 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD12_DLASTSGA_OFFSET 0x0198 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD12_CSR_OFFSET 0x019c /* TCD Control and Status */ -#define KINETIS_DMA_TCD12_BITER_OFFSET 0x019e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD13_SADDR_OFFSET 0x01a0 /* TCD Source Address */ -#define KINETIS_DMA_TCD13_SOFF_OFFSET 0x01a4 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD13_ATTR_OFFSET 0x01a6 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD13_NBYTES_OFFSET 0x01a8 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD13_SLAST_OFFSET 0x01ac /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD13_DADDR_OFFSET 0x01b0 /* TCD Destination Address */ -#define KINETIS_DMA_TCD13_DOFF_OFFSET 0x01b4 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD13_CITER_OFFSET 0x01b6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD13_DLASTSGA_OFFSET 0x01b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD13_CSR_OFFSET 0x01bc /* TCD Control and Status */ -#define KINETIS_DMA_TCD13_BITER_OFFSET 0x01be /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD14_SADDR_OFFSET 0x01c0 /* TCD Source Address */ -#define KINETIS_DMA_TCD14_SOFF_OFFSET 0x01c4 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD14_ATTR_OFFSET 0x01c6 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD14_NBYTES_OFFSET 0x01c8 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD14_SLAST_OFFSET 0x01cc /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD14_DADDR_OFFSET 0x01d0 /* TCD Destination Address */ -#define KINETIS_DMA_TCD14_DOFF_OFFSET 0x01d4 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD14_CITER_OFFSET 0x01d6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD14_DLASTSGA_OFFSET 0x01d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD14_CSR_OFFSET 0x01dc /* TCD Control and Status */ -#define KINETIS_DMA_TCD14_BITER_OFFSET 0x01de /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define KINETIS_DMA_TCD15_SADDR_OFFSET 0x01e0 /* TCD Source Address */ -#define KINETIS_DMA_TCD15_SOFF_OFFSET 0x01e4 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD15_ATTR_OFFSET 0x01e6 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD15_NBYTES_OFFSET 0x01e8 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD15_SLAST_OFFSET 0x01ec /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD15_DADDR_OFFSET 0x01f0 /* TCD Destination Address */ -#define KINETIS_DMA_TCD15_DOFF_OFFSET 0x01f4 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD15_CITER_OFFSET 0x01f6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD15_DLASTSGA_OFFSET 0x01f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD15_CSR_OFFSET 0x01fc /* TCD Control and Status */ -#define KINETIS_DMA_TCD15_BITER_OFFSET 0x01fe /* TCD Beginning Minor Loop Link, Major Loop Count */ - -/* Register Addresses *******************************************************/ - -#define KINETIS_DMA_CR (KINETIS_DMAC_BASE + KINETIS_DMA_CR_OFFSET) -#define KINETIS_DMA_ES (KINETIS_DMAC_BASE + KINETIS_DMA_ES_OFFSET) -#define KINETIS_DMA_ERQ (KINETIS_DMAC_BASE + KINETIS_DMA_ERQ_OFFSET) -#define KINETIS_DMA_EEI (KINETIS_DMAC_BASE + KINETIS_DMA_EEI_OFFSET) -#define KINETIS_DMA_CEEI (KINETIS_DMAC_BASE + KINETIS_DMA_CEEI_OFFSET) -#define KINETIS_DMA_SEEI (KINETIS_DMAC_BASE + KINETIS_DMA_SEEI_OFFSET) -#define KINETIS_DMA_CERQ (KINETIS_DMAC_BASE + KINETIS_DMA_CERQ_OFFSET) -#define KINETIS_DMA_SERQ (KINETIS_DMAC_BASE + KINETIS_DMA_SERQ_OFFSET) -#define KINETIS_DMA_CDNE (KINETIS_DMAC_BASE + KINETIS_DMA_CDNE_OFFSET) -#define KINETIS_DMA_SSRT (KINETIS_DMAC_BASE + KINETIS_DMA_SSRT_OFFSET) -#define KINETIS_DMA_CERR (KINETIS_DMAC_BASE + KINETIS_DMA_CERR_OFFSET) -#define KINETIS_DMA_CINT (KINETIS_DMAC_BASE + KINETIS_DMA_CINT_OFFSET) -#define KINETIS_DMA_INT (KINETIS_DMAC_BASE + KINETIS_DMA_INT_OFFSET) -#define KINETIS_DMA_ERR (KINETIS_DMAC_BASE + KINETIS_DMA_ERR_OFFSET) -#define KINETIS_DMA_HRS (KINETIS_DMAC_BASE + KINETIS_DMA_HRS_OFFSET) - -#define KINETIS_DMA_DCHPRI(n) (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI_OFFSET(n)) - -#define KINETIS_DMA_DCHPRI3 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI3_OFFSET) -#define KINETIS_DMA_DCHPRI2 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI2_OFFSET) -#define KINETIS_DMA_DCHPRI1 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI1_OFFSET) -#define KINETIS_DMA_DCHPRI0 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI0_OFFSET) -#define KINETIS_DMA_DCHPRI7 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI7_OFFSET) -#define KINETIS_DMA_DCHPRI6 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI6_OFFSET) -#define KINETIS_DMA_DCHPRI5 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI5_OFFSET) -#define KINETIS_DMA_DCHPRI4 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI4_OFFSET) -#define KINETIS_DMA_DCHPRI11 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI11_OFFSET) -#define KINETIS_DMA_DCHPRI10 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI10_OFFSET) -#define KINETIS_DMA_DCHPRI9 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI9_OFFSET) -#define KINETIS_DMA_DCHPRI8 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI8_OFFSET) -#define KINETIS_DMA_DCHPRI15 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI15_OFFSET) -#define KINETIS_DMA_DCHPRI14 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI14_OFFSET) -#define KINETIS_DMA_DCHPRI13 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI13_OFFSET) -#define KINETIS_DMA_DCHPRI12 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI12_OFFSET) - -#define KINETIS_DMA_TCD_BASE(n) (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD_OFFSET(n)) - -#define KINETIS_DMA_TCD_SADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SADDR_OFFSET) -#define KINETIS_DMA_TCD_SOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SOFF_OFFSET) -#define KINETIS_DMA_TCD_ATTR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_ATTR_OFFSET) -#define KINETIS_DMA_TCD_NBYTES(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_NBYTES_OFFSET) -#define KINETIS_DMA_TCD_SLAST(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SLAST_OFFSET) -#define KINETIS_DMA_TCD_DADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DADDR_OFFSET) -#define KINETIS_DMA_TCD_DOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DOFF_OFFSET) -#define KINETIS_DMA_TCD_CITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CITER_OFFSET) -#define KINETIS_DMA_TCD_DLASTSGA(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD_CSR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CSR_OFFSET) -#define KINETIS_DMA_TCD_BITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_BITER_OFFSET) - -#define KINETIS_DMA_TCD0_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SADDR_OFFSET) -#define KINETIS_DMA_TCD0_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SOFF_OFFSET) -#define KINETIS_DMA_TCD0_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_ATTR_OFFSET) -#define KINETIS_DMA_TCD0_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_NBYTES_OFFSET) -#define KINETIS_DMA_TCD0_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SLAST_OFFSET) -#define KINETIS_DMA_TCD0_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DADDR_OFFSET) -#define KINETIS_DMA_TCD0_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DOFF_OFFSET) -#define KINETIS_DMA_TCD0_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_CITER_OFFSET) -#define KINETIS_DMA_TCD0_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD0_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_CSR_OFFSET) -#define KINETIS_DMA_TCD0_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_BITER_OFFSET) - -#define KINETIS_DMA_TCD1_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SADDR_OFFSET) -#define KINETIS_DMA_TCD1_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SOFF_OFFSET) -#define KINETIS_DMA_TCD1_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_ATTR_OFFSET) -#define KINETIS_DMA_TCD1_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_NBYTES_OFFSET) -#define KINETIS_DMA_TCD1_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SLAST_OFFSET) -#define KINETIS_DMA_TCD1_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DADDR_OFFSET) -#define KINETIS_DMA_TCD1_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DOFF_OFFSET) -#define KINETIS_DMA_TCD1_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_CITER_OFFSET) -#define KINETIS_DMA_TCD1_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD1_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_CSR_OFFSET) -#define KINETIS_DMA_TCD1_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_BITER_OFFSET) - -#define KINETIS_DMA_TCD2_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SADDR_OFFSET) -#define KINETIS_DMA_TCD2_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SOFF_OFFSET) -#define KINETIS_DMA_TCD2_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_ATTR_OFFSET) -#define KINETIS_DMA_TCD2_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_NBYTES_OFFSET) -#define KINETIS_DMA_TCD2_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SLAST_OFFSET) -#define KINETIS_DMA_TCD2_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DADDR_OFFSET) -#define KINETIS_DMA_TCD2_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DOFF_OFFSET) -#define KINETIS_DMA_TCD2_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_CITER_OFFSET) -#define KINETIS_DMA_TCD2_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD2_CSR_ (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_CSR_OFFSET) -#define KINETIS_DMA_TCD2_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_BITER_OFFSET) - -#define KINETIS_DMA_TCD3_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SADDR_OFFSET) -#define KINETIS_DMA_TCD3_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SOFF_OFFSET) -#define KINETIS_DMA_TCD3_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_ATTR_OFFSET) -#define KINETIS_DMA_TCD3_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_NBYTES_OFFSET) -#define KINETIS_DMA_TCD3_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SLAST_OFFSET) -#define KINETIS_DMA_TCD3_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DADDR_OFFSET) -#define KINETIS_DMA_TCD3_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DOFF_OFFSET) -#define KINETIS_DMA_TCD3_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_CITER_OFFSET) -#define KINETIS_DMA_TCD3_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DLASTSGA_OFFSET -#define KINETIS_DMA_TCD3_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_CSR_OFFSET) -#define KINETIS_DMA_TCD3_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_BITER_OFFSET) - -#define KINETIS_DMA_TCD4_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SADDR_OFFSET) -#define KINETIS_DMA_TCD4_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SOFF_OFFSET) -#define KINETIS_DMA_TCD4_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_ATTR_OFFSET0) -#define KINETIS_DMA_TCD4_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_NBYTES_OFFSET) -#define KINETIS_DMA_TCD4_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SLAST_OFFSET) -#define KINETIS_DMA_TCD4_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DADDR_OFFSET) -#define KINETIS_DMA_TCD4_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DOFF_OFFSET) -#define KINETIS_DMA_TCD4_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_CITER_OFFSET) -#define KINETIS_DMA_TCD4_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD4_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_CSR_OFFSET) -#define KINETIS_DMA_TCD4_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_BITER_OFFSET) - -#define KINETIS_DMA_TCD5_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SADDR_OFFSET) -#define KINETIS_DMA_TCD5_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SOFF_OFFSET) -#define KINETIS_DMA_TCD5_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_ATTR_OFFSET) -#define KINETIS_DMA_TCD5_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_NBYTES_OFFSET) -#define KINETIS_DMA_TCD5_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SLAST_OFFSET) -#define KINETIS_DMA_TCD5_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DADDR_OFFSET) -#define KINETIS_DMA_TCD5_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DOFF_OFFSET) -#define KINETIS_DMA_TCD5_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_CITER_OFFSET) -#define KINETIS_DMA_TCD5_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD5_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_CSR_OFFSET) -#define KINETIS_DMA_TCD5_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_BITER_OFFSET) - -#define KINETIS_DMA_TCD6_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SADDR_OFFSET) -#define KINETIS_DMA_TCD6_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SOFF_OFFSET) -#define KINETIS_DMA_TCD6_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_ATTR_OFFSET) -#define KINETIS_DMA_TCD6_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_NBYTES_OFFSET) -#define KINETIS_DMA_TCD6_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SLAST_OFFSET) -#define KINETIS_DMA_TCD6_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DADDR_OFFSET) -#define KINETIS_DMA_TCD6_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DOFF_OFFSET) -#define KINETIS_DMA_TCD6_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_CITER_OFFSET) -#define KINETIS_DMA_TCD6_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD6_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_CSR_OFFSET) -#define KINETIS_DMA_TCD6_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_BITER_OFFSET) - -#define KINETIS_DMA_TCD7_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SADDR_OFFSET) -#define KINETIS_DMA_TCD7_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SOFF_OFFSET) -#define KINETIS_DMA_TCD7_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_ATTR_OFFSET) -#define KINETIS_DMA_TCD7_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_NBYTES_OFFSET) -#define KINETIS_DMA_TCD7_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SLAST_OFFSET) -#define KINETIS_DMA_TCD7_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DADDR_OFFSET) -#define KINETIS_DMA_TCD7_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DOFF_OFFSET) -#define KINETIS_DMA_TCD7_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_CITER_OFFSET) -#define KINETIS_DMA_TCD7_DLASTSGA_ (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD7_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_CSR_OFFSET) -#define KINETIS_DMA_TCD7_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_BITER_OFFSET) - -#define KINETIS_DMA_TCD8_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SADDR_OFFSET) -#define KINETIS_DMA_TCD8_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SOFF_OFFSET) -#define KINETIS_DMA_TCD8_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_ATTR_OFFSET) -#define KINETIS_DMA_TCD8_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_NBYTES_OFFSET) -#define KINETIS_DMA_TCD8_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SLAST_OFFSET) -#define KINETIS_DMA_TCD8_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DADDR_OFFSET) -#define KINETIS_DMA_TCD8_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DOFF_OFFSET) -#define KINETIS_DMA_TCD8_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_CITER_OFFSET) -#define KINETIS_DMA_TCD8_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD8_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_CSR_OFFSET) -#define KINETIS_DMA_TCD8_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_BITER_OFFSET) - -#define KINETIS_DMA_TCD9_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SADDR_OFFSET) -#define KINETIS_DMA_TCD9_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SOFF_OFFSET) -#define KINETIS_DMA_TCD9_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_ATTR_OFFSET) -#define KINETIS_DMA_TCD9_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_NBYTES_OFFSET) -#define KINETIS_DMA_TCD9_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SLAST_OFFSET) -#define KINETIS_DMA_TCD9_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DADDR_OFFSET) -#define KINETIS_DMA_TCD9_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DOFF_OFFSET) -#define KINETIS_DMA_TCD9_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_CITER_OFFSET) -#define KINETIS_DMA_TCD9_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD9_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_CSR_OFFSET) -#define KINETIS_DMA_TCD9_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_BITER_OFFSET) - -#define KINETIS_DMA_TCD10_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SADDR_OFFSET) -#define KINETIS_DMA_TCD10_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SOFF_OFFSET) -#define KINETIS_DMA_TCD10_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_ATTR_OFFSET) -#define KINETIS_DMA_TCD10_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_NBYTES_OFFSET) -#define KINETIS_DMA_TCD10_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SLAST_OFFSET) -#define KINETIS_DMA_TCD10_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DADDR_OFFSET) -#define KINETIS_DMA_TCD10_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DOFF_OFFSET) -#define KINETIS_DMA_TCD10_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_CITER_OFFSET) -#define KINETIS_DMA_TCD10_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD10_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_CSR_OFFSET) -#define KINETIS_DMA_TCD10_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_BITER_OFFSET) - -#define KINETIS_DMA_TCD11_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SADDR_OFFSET) -#define KINETIS_DMA_TCD11_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SOFF_OFFSET) -#define KINETIS_DMA_TCD11_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_ATTR_OFFSET) -#define KINETIS_DMA_TCD11_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_NBYTES_OFFSET) -#define KINETIS_DMA_TCD11_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SLAST_OFFSET) -#define KINETIS_DMA_TCD11_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DADDR_OFFSET) -#define KINETIS_DMA_TCD11_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DOFF_OFFSET) -#define KINETIS_DMA_TCD11_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_CITER_OFFSET) -#define KINETIS_DMA_TCD11_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD11_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_CSR_OFFSET) -#define KINETIS_DMA_TCD11_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_BITER_OFFSET) - -#define KINETIS_DMA_TCD12_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SADDR_OFFSET) -#define KINETIS_DMA_TCD12_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SOFF_OFFSET) -#define KINETIS_DMA_TCD12_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_ATTR_OFFSET) -#define KINETIS_DMA_TCD12_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_NBYTES_OFFSET) -#define KINETIS_DMA_TCD12_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SLAST_OFFSET) -#define KINETIS_DMA_TCD12_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DADDR_OFFSET) -#define KINETIS_DMA_TCD12_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DOFF_OFFSET) -#define KINETIS_DMA_TCD12_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_CITER_OFFSET) -#define KINETIS_DMA_TCD12_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD12_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_CSR_OFFSET) -#define KINETIS_DMA_TCD12_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_BITER_OFFSET) - -#define KINETIS_DMA_TCD13_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SADDR_OFFSET) -#define KINETIS_DMA_TCD13_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SOFF_OFFSET) -#define KINETIS_DMA_TCD13_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_ATTR_OFFSET) -#define KINETIS_DMA_TCD13_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_NBYTES_OFFSET) -#define KINETIS_DMA_TCD13_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SLAST_OFFSET) -#define KINETIS_DMA_TCD13_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DADDR_OFFSET) -#define KINETIS_DMA_TCD13_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DOFF_OFFSET) -#define KINETIS_DMA_TCD13_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_CITER_OFFSET) -#define KINETIS_DMA_TCD13_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD13_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_CSR_OFFSET) -#define KINETIS_DMA_TCD13_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_BITER_OFFSET) - -#define KINETIS_DMA_TCD14_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SADDR_OFFSET) -#define KINETIS_DMA_TCD14_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SOFF_OFFSET) -#define KINETIS_DMA_TCD14_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_ATTR_OFFSET) -#define KINETIS_DMA_TCD14_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_NBYTES_OFFSET) -#define KINETIS_DMA_TCD14_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SLAST_OFFSET) -#define KINETIS_DMA_TCD14_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DADDR_OFFSET) -#define KINETIS_DMA_TCD14_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DOFF_OFFSET) -#define KINETIS_DMA_TCD14_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_CITER_OFFSET) -#define KINETIS_DMA_TCD14_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD14_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_CSR_OFFSET) -#define KINETIS_DMA_TCD14_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_BITER_OFFSET) - -#define KINETIS_DMA_TCD15_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SADDR_OFFSET) -#define KINETIS_DMA_TCD15_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SOFF_OFFSET) -#define KINETIS_DMA_TCD15_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_ATTR_OFFSET) -#define KINETIS_DMA_TCD15_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_NBYTES_OFFSET) -#define KINETIS_DMA_TCD15_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SLAST_OFFSET) -#define KINETIS_DMA_TCD15_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DADDR_OFFSET) -#define KINETIS_DMA_TCD15_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DOFF_OFFSET) -#define KINETIS_DMA_TCD15_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_CITER_OFFSET) -#define KINETIS_DMA_TCD15_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD15_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_CSR_OFFSET) -#define KINETIS_DMA_TCD15_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_BITER_OFFSET) - -/* Register Bit Definitions *************************************************/ - -/* Control Register (32-bit) */ - - /* Bit 0: Reserved */ -#define DMA_CR_EDBG (1 << 1) /* Bit 1: Enable debug */ -#define DMA_CR_ERCA (1 << 2) /* Bit 2: Enable round robin channel arbitration */ -#if defined KINETIS_DMA_HAS_CR_ERGA -# define DMA_CR_ERGA (1 << 3) /* Bit 3: Enable round robin group arbitration */ -#endif -#define DMA_CR_HOE (1 << 4) /* Bit 4: Halt on error */ -#define DMA_CR_HALT (1 << 5) /* Bit 5: Halt DMA operations */ -#define DMA_CR_CLM (1 << 6) /* Bit 6: Continuous link mode */ -#define DMA_CR_EMLM (1 << 7) /* Bit 7: Enable minor loop mapping */ -#ifdef KINETIS_DMA_HAS_CR_GRP0PRI -# define DMA_CR_GRP0PRI (1 << 8) /* Bit 8: Channel Group 0 Priority */ -#endif - /* Bit 9: Reserved */ -#ifdef KINETIS_DMA_HAS_CR_GRP1PRI -# define DMA_CR_GRP1PRI (1 << 10) /* Bit 10: Channel Group 1 Priority */ -#endif - /* Bits 11-15: Reserved */ -#define DMA_CR_ECX (1 << 16) /* Bit 16: Error cancel transfer */ -#define DMA_CR_CX (1 << 17) /* Bit 17: Cancel transfer */ - /* Bits 18-31: Reserved */ - -/* Error Status Register */ - -#define DMA_ES_DBE (1 << 0) /* Bit 0: Destination bus error */ -#define DMA_ES_SBE (1 << 1) /* Bit 1: Source bus error */ -#define DMA_ES_SGE (1 << 2) /* Bit 2: Scatter/gather configuration error */ -#define DMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER configuration error */ -#define DMA_ES_DOE (1 << 4) /* Bit 4: Destination offset error */ -#define DMA_ES_DAE (1 << 5) /* Bit 5: Destination address error */ -#define DMA_ES_SOE (1 << 6) /* Bit 6: Source offset error */ -#define DMA_ES_SAE (1 << 7) /* Bit 7: Source address error */ -#define DMA_ES_ERRCHN_SHIFT (8) /* Bits 8-11/12: Error channel number or cancelled channel number */ -#define DMA_ES_ERRCHN_MASK (((1 << KINETIS_DMA_HAS_ES_ERRCHN_BITS) - 1) << DMA_ES_ERRCHN_SHIFT) - /* Bits 13: Reserved */ -#define DMA_ES_CPE (1 << 14) /* Bit 14: Channel priority error */ -#ifdef KINETIS_DMA_HAS_ES_GPE -# define DMA_ES_GPE (1 << 15) /* Bit 15: Group priority error */ -#endif -#define DMA_ES_ECX (1 << 16) /* Bit 16: Transfer cancelled */ - /* Bits 17-30: Reserved */ -#define DMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */ - -/* Enable Request Register (ERQ), Enable Error Interrupt Register (EEI), - * Interrupt Request Register (INT), Error Register (ERR), - * Hardware Request Status Register (HRS) common bit definitions - */ - -#define DMA_REQ(n) (1 << (n)) /* Bit n: DMA Request n, n=0.. - * Jan Okle + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -72,7 +56,7 @@ /* Channel n Configuration Register */ #define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-5: DMA Channel Source (slot) */ -#define DMAMUX_CHCFG_SOURCE_MASK (63 << DMAMUX_CHCFG_SOURCE_SHIFT) +#define DMAMUX_CHCFG_SOURCE_MASK (0x3f << DMAMUX_CHCFG_SOURCE_SHIFT) #define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable */ #define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_edma.h b/arch/arm/src/kinetis/hardware/kinetis_edma.h new file mode 100644 index 00000000000..c21c0d9f019 --- /dev/null +++ b/arch/arm/src/kinetis/hardware/kinetis_edma.h @@ -0,0 +1,855 @@ +/**************************************************************************** + * arch/arm/src/kinetis/hardware/kinetis_edma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EDMA_H +#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EDMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/kinetis_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define KINETIS_EDMA_NCHANNELS 16 + +/* eDMA Register Offsets ****************************************************/ + +#define KINETIS_EDMA_CR_OFFSET 0x0000 /* Control */ +#define KINETIS_EDMA_ES_OFFSET 0x0004 /* Error Status */ +#define KINETIS_EDMA_ERQ_OFFSET 0x000c /* Enable Request */ +#define KINETIS_EDMA_EEI_OFFSET 0x0014 /* Enable Error Interrupt */ +#define KINETIS_EDMA_CEEI_OFFSET 0x0018 /* Clear Enable Error Interrupt */ +#define KINETIS_EDMA_SEEI_OFFSET 0x0019 /* Set Enable Error Interrupt */ +#define KINETIS_EDMA_CERQ_OFFSET 0x001a /* Clear Enable Request */ +#define KINETIS_EDMA_SERQ_OFFSET 0x001b /* Set Enable Request */ +#define KINETIS_EDMA_CDNE_OFFSET 0x001c /* Clear DONE Status Bit */ +#define KINETIS_EDMA_SSRT_OFFSET 0x001d /* Set START Bit */ +#define KINETIS_EDMA_CERR_OFFSET 0x001e /* Clear Error */ +#define KINETIS_EDMA_CINT_OFFSET 0x001f /* Clear Interrupt Request */ +#define KINETIS_EDMA_INT_OFFSET 0x0024 /* Interrupt Request */ +#define KINETIS_EDMA_ERR_OFFSET 0x002c /* Error */ +#define KINETIS_EDMA_HRS_OFFSET 0x0034 /* Hardware Request Status */ +#define KINETIS_EDMA_EARS_OFFSET 0x0044 /* Enable Asynchronous Request in Stop */ + +#define KINETIS_EDMA_DCHPRI_OFFSET(n) (0x0100 + ((n) & ~3) + (3 - ((n) & 3))) + +#define KINETIS_EDMA_DCHPRI3_OFFSET 0x0100 /* Channel 3 Priority */ +#define KINETIS_EDMA_DCHPRI2_OFFSET 0x0101 /* Channel 2 Priority */ +#define KINETIS_EDMA_DCHPRI1_OFFSET 0x0102 /* Channel 1 Priority */ +#define KINETIS_EDMA_DCHPRI0_OFFSET 0x0103 /* Channel 0 Priority */ +#define KINETIS_EDMA_DCHPRI7_OFFSET 0x0104 /* Channel 7 Priority */ +#define KINETIS_EDMA_DCHPRI6_OFFSET 0x0105 /* Channel 6 Priority */ +#define KINETIS_EDMA_DCHPRI5_OFFSET 0x0106 /* Channel 5 Priority */ +#define KINETIS_EDMA_DCHPRI4_OFFSET 0x0107 /* Channel 4 Priority */ +#define KINETIS_EDMA_DCHPRI11_OFFSET 0x0108 /* Channel 11 Priority */ +#define KINETIS_EDMA_DCHPRI10_OFFSET 0x0109 /* Channel 10 Priority */ +#define KINETIS_EDMA_DCHPRI9_OFFSET 0x010a /* Channel 9 Priority */ +#define KINETIS_EDMA_DCHPRI8_OFFSET 0x010b /* Channel 8 Priority */ +#define KINETIS_EDMA_DCHPRI15_OFFSET 0x010c /* Channel 15 Priority */ +#define KINETIS_EDMA_DCHPRI14_OFFSET 0x010d /* Channel 14 Priority */ +#define KINETIS_EDMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority */ +#define KINETIS_EDMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority */ + +/* Transfer Control Descriptor (TCD) */ + +#define KINETIS_EDMA_TCD_OFFSET(n) (0x1000 + ((n) << 5)) +#define KINETIS_EDMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */ +#define KINETIS_EDMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD_NBYTES_ML_OFFSET 0x0008 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD_CITER_ELINK_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD_BITER_ELINK_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD0_SADDR_OFFSET 0x1000 /* TCD Source Address */ +#define KINETIS_EDMA_TCD0_SOFF_OFFSET 0x1004 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD0_ATTR_OFFSET 0x1006 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD0_NBYTES_ML_OFFSET 0x1008 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD0_SLAST_OFFSET 0x100c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD0_DADDR_OFFSET 0x1010 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD0_DOFF_OFFSET 0x1014 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD0_CITER_ELINK_OFFSET 0x1016 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD0_DLASTSGA_OFFSET 0x1018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD0_CSR_OFFSET 0x101c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD0_BITER_ELINK_OFFSET 0x101e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD1_SADDR_OFFSET 0x1020 /* TCD Source Address */ +#define KINETIS_EDMA_TCD1_SOFF_OFFSET 0x1024 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD1_ATTR_OFFSET 0x1026 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD1_NBYTES_ML_OFFSET 0x1028 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD1_SLAST_OFFSET 0x102c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD1_DADDR_OFFSET 0x1030 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD1_DOFF_OFFSET 0x1034 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD1_CITER_ELINK_OFFSET 0x1036 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD1_DLASTSGA_OFFSET 0x1038 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD1_CSR_OFFSET 0x103c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD1_BITER_ELINK_OFFSET 0x103e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD1_SADDR_OFFSET 0x1020 /* TCD Source Address */ +#define KINETIS_EDMA_TCD1_SOFF_OFFSET 0x1024 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD1_ATTR_OFFSET 0x1026 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD1_NBYTES_ML_OFFSET 0x1028 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD1_SLAST_OFFSET 0x102c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD1_DADDR_OFFSET 0x1030 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD1_DOFF_OFFSET 0x1034 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD1_CITER_ELINK_OFFSET 0x1036 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD1_DLASTSGA_OFFSET 0x1038 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD1_CSR_OFFSET 0x103c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD1_BITER_ELINK_OFFSET 0x103e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD2_SADDR_OFFSET 0x1040 /* TCD Source Address */ +#define KINETIS_EDMA_TCD2_SOFF_OFFSET 0x1044 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD2_ATTR_OFFSET 0x1046 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD2_NBYTES_ML_OFFSET 0x1048 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD2_SLAST_OFFSET 0x104c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD2_DADDR_OFFSET 0x1050 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD2_DOFF_OFFSET 0x1054 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD2_CITER_ELINK_OFFSET 0x1056 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD2_DLASTSGA_OFFSET 0x1058 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD2_CSR_OFFSET 0x105c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD2_BITER_ELINK_OFFSET 0x105e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD3_SADDR_OFFSET 0x1060 /* TCD Source Address */ +#define KINETIS_EDMA_TCD3_SOFF_OFFSET 0x1064 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD3_ATTR_OFFSET 0x1066 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD3_NBYTES_ML_OFFSET 0x1068 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD3_SLAST_OFFSET 0x106c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD3_DADDR_OFFSET 0x1070 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD3_DOFF_OFFSET 0x1074 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD3_CITER_ELINK_OFFSET 0x1076 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD3_DLASTSGA_OFFSET 0x1078 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD3_CSR_OFFSET 0x107c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD3_BITER_ELINK_OFFSET 0x107e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD4_SADDR_OFFSET 0x1080 /* TCD Source Address */ +#define KINETIS_EDMA_TCD4_SOFF_OFFSET 0x1084 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD4_ATTR_OFFSET 0x1086 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD4_NBYTES_ML_OFFSET 0x1088 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD4_SLAST_OFFSET 0x108c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD4_DADDR_OFFSET 0x1090 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD4_DOFF_OFFSET 0x1094 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD4_CITER_ELINK_OFFSET 0x1096 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD4_DLASTSGA_OFFSET 0x1098 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD4_CSR_OFFSET 0x109c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD4_BITER_ELINK_OFFSET 0x109e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD5_SADDR_OFFSET 0x10a0 /* TCD Source Address */ +#define KINETIS_EDMA_TCD5_SOFF_OFFSET 0x10a4 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD5_ATTR_OFFSET 0x10a6 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD5_NBYTES_ML_OFFSET 0x10a8 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD5_SLAST_OFFSET 0x10ac /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD5_DADDR_OFFSET 0x10b0 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD5_DOFF_OFFSET 0x10b4 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD5_CITER_ELINK_OFFSET 0x10b6 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD5_DLASTSGA_OFFSET 0x10b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD5_CSR_OFFSET 0x10bc /* TCD Control and Status */ +#define KINETIS_EDMA_TCD5_BITER_ELINK_OFFSET 0x10be /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD6_SADDR_OFFSET 0x10c0 /* TCD Source Address */ +#define KINETIS_EDMA_TCD6_SOFF_OFFSET 0x10c4 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD6_ATTR_OFFSET 0x10c6 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD6_NBYTES_ML_OFFSET 0x10c8 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD6_SLAST_OFFSET 0x10cc /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD6_DADDR_OFFSET 0x10d0 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD6_DOFF_OFFSET 0x10d4 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD6_CITER_ELINK_OFFSET 0x10d6 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD6_DLASTSGA_OFFSET 0x10d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD6_CSR_OFFSET 0x10dc /* TCD Control and Status */ +#define KINETIS_EDMA_TCD6_BITER_ELINK_OFFSET 0x10de /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD7_SADDR_OFFSET 0x10e0 /* TCD Source Address */ +#define KINETIS_EDMA_TCD7_SOFF_OFFSET 0x10e4 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD7_ATTR_OFFSET 0x10e6 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD7_NBYTES_ML_OFFSET 0x10e8 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD7_SLAST_OFFSET 0x10ec /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD7_DADDR_OFFSET 0x10f0 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD7_DOFF_OFFSET 0x10f4 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD7_CITER_ELINK_OFFSET 0x10f6 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD7_DLASTSGA_OFFSET 0x10f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD7_CSR_OFFSET 0x10fc /* TCD Control and Status */ +#define KINETIS_EDMA_TCD7_BITER_ELINK_OFFSET 0x10fe /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD8_SADDR_OFFSET 0x1100 /* TCD Source Address */ +#define KINETIS_EDMA_TCD8_SOFF_OFFSET 0x1104 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD8_ATTR_OFFSET 0x1106 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD8_NBYTES_ML_OFFSET 0x1108 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD8_SLAST_OFFSET 0x110c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD8_DADDR_OFFSET 0x1110 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD8_DOFF_OFFSET 0x1114 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD8_CITER_ELINK_OFFSET 0x1116 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD8_DLASTSGA_OFFSET 0x1118 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD8_CSR_OFFSET 0x111c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD8_BITER_ELINK_OFFSET 0x111e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD9_SADDR_OFFSET 0x1120 /* TCD Source Address */ +#define KINETIS_EDMA_TCD9_SOFF_OFFSET 0x1124 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD9_ATTR_OFFSET 0x1126 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD9_NBYTES_ML_OFFSET 0x1128 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD9_SLAST_OFFSET 0x112c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD9_DADDR_OFFSET 0x1130 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD9_DOFF_OFFSET 0x1134 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD9_CITER_ELINK_OFFSET 0x1136 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD9_DLASTSGA_OFFSET 0x1138 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD9_CSR_OFFSET 0x113c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD9_BITER_ELINK_OFFSET 0x113e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD10_SADDR_OFFSET 0x1140 /* TCD Source Address */ +#define KINETIS_EDMA_TCD10_SOFF_OFFSET 0x1144 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD10_ATTR_OFFSET 0x1146 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD10_NBYTES_ML_OFFSET 0x1148 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD10_SLAST_OFFSET 0x114c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD10_DADDR_OFFSET 0x1150 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD10_DOFF_OFFSET 0x1154 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD10_CITER_ELINK_OFFSET 0x1156 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD10_DLASTSGA_OFFSET 0x1158 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD10_CSR_OFFSET 0x115c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD10_BITER_ELINK_OFFSET 0x115e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD11_SADDR_OFFSET 0x1160 /* TCD Source Address */ +#define KINETIS_EDMA_TCD11_SOFF_OFFSET 0x1164 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD11_ATTR_OFFSET 0x1166 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD11_NBYTES_ML_OFFSET 0x1168 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD11_SLAST_OFFSET 0x116c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD11_DADDR_OFFSET 0x1170 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD11_DOFF_OFFSET 0x1174 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD11_CITER_ELINK_OFFSET 0x1176 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD11_DLASTSGA_OFFSET 0x1178 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD11_CSR_OFFSET 0x117c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD11_BITER_ELINK_OFFSET 0x117e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD12_SADDR_OFFSET 0x1180 /* TCD Source Address */ +#define KINETIS_EDMA_TCD12_SOFF_OFFSET 0x1184 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD12_ATTR_OFFSET 0x1186 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD12_NBYTES_ML_OFFSET 0x1188 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD12_SLAST_OFFSET 0x118c /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD12_DADDR_OFFSET 0x1190 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD12_DOFF_OFFSET 0x1194 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD12_CITER_ELINK_OFFSET 0x1196 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD12_DLASTSGA_OFFSET 0x1198 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD12_CSR_OFFSET 0x119c /* TCD Control and Status */ +#define KINETIS_EDMA_TCD12_BITER_ELINK_OFFSET 0x119e /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD13_SADDR_OFFSET 0x11a0 /* TCD Source Address */ +#define KINETIS_EDMA_TCD13_SOFF_OFFSET 0x11a4 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD13_ATTR_OFFSET 0x11a6 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD13_NBYTES_ML_OFFSET 0x11a8 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD13_SLAST_OFFSET 0x11ac /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD13_DADDR_OFFSET 0x11b0 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD13_DOFF_OFFSET 0x11b4 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD13_CITER_ELINK_OFFSET 0x11b6 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD13_DLASTSGA_OFFSET 0x11b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD13_CSR_OFFSET 0x11bc /* TCD Control and Status */ +#define KINETIS_EDMA_TCD13_BITER_ELINK_OFFSET 0x11be /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD14_SADDR_OFFSET 0x11c0 /* TCD Source Address */ +#define KINETIS_EDMA_TCD14_SOFF_OFFSET 0x11c4 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD14_ATTR_OFFSET 0x11c6 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD14_NBYTES_ML_OFFSET 0x11c8 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD14_SLAST_OFFSET 0x11cc /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD14_DADDR_OFFSET 0x11d0 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD14_DOFF_OFFSET 0x11d4 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD14_CITER_ELINK_OFFSET 0x11d6 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD14_DLASTSGA_OFFSET 0x11d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD14_CSR_OFFSET 0x11dc /* TCD Control and Status */ +#define KINETIS_EDMA_TCD14_BITER_ELINK_OFFSET 0x11de /* TCD Beginning Minor Loop Link, Major Loop Count */ + +#define KINETIS_EDMA_TCD15_SADDR_OFFSET 0x11e0 /* TCD Source Address */ +#define KINETIS_EDMA_TCD15_SOFF_OFFSET 0x11e4 /* TCD Signed Source Address Offset */ +#define KINETIS_EDMA_TCD15_ATTR_OFFSET 0x11e6 /* TCD Transfer Attributes */ +#define KINETIS_EDMA_TCD15_NBYTES_ML_OFFSET 0x11e8 /* TCD Signed Minor Loop Offset / Byte Count */ +#define KINETIS_EDMA_TCD15_SLAST_OFFSET 0x11ec /* TCD Last Source Address Adjustment */ +#define KINETIS_EDMA_TCD15_DADDR_OFFSET 0x11f0 /* TCD Destination Address */ +#define KINETIS_EDMA_TCD15_DOFF_OFFSET 0x11f4 /* TCD Signed Destination Address Offset */ +#define KINETIS_EDMA_TCD15_CITER_ELINK_OFFSET 0x11f6 /* TCD Current Minor Loop Link, Major Loop Count */ +#define KINETIS_EDMA_TCD15_DLASTSGA_OFFSET 0x11f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define KINETIS_EDMA_TCD15_CSR_OFFSET 0x11fc /* TCD Control and Status */ +#define KINETIS_EDMA_TCD15_BITER_ELINK_OFFSET 0x11fe /* TCD Beginning Minor Loop Link, Major Loop Count */ + +/* eDMA Register Addresses **************************************************/ + +#define KINETIS_EDMA_CR (KINETIS_DMAC_BASE + KINETIS_EDMA_CR_OFFSET) +#define KINETIS_EDMA_ES (KINETIS_DMAC_BASE + KINETIS_EDMA_ES_OFFSET) +#define KINETIS_EDMA_ERQ (KINETIS_DMAC_BASE + KINETIS_EDMA_ERQ_OFFSET) +#define KINETIS_EDMA_EEI (KINETIS_DMAC_BASE + KINETIS_EDMA_EEI_OFFSET) +#define KINETIS_EDMA_CEEI (KINETIS_DMAC_BASE + KINETIS_EDMA_CEEI_OFFSET) +#define KINETIS_EDMA_SEEI (KINETIS_DMAC_BASE + KINETIS_EDMA_SEEI_OFFSET) +#define KINETIS_EDMA_CERQ (KINETIS_DMAC_BASE + KINETIS_EDMA_CERQ_OFFSET) +#define KINETIS_EDMA_SERQ (KINETIS_DMAC_BASE + KINETIS_EDMA_SERQ_OFFSET) +#define KINETIS_EDMA_CDNE (KINETIS_DMAC_BASE + KINETIS_EDMA_CDNE_OFFSET) +#define KINETIS_EDMA_SSRT (KINETIS_DMAC_BASE + KINETIS_EDMA_SSRT_OFFSET) +#define KINETIS_EDMA_CERR (KINETIS_DMAC_BASE + KINETIS_EDMA_CERR_OFFSET) +#define KINETIS_EDMA_CINT (KINETIS_DMAC_BASE + KINETIS_EDMA_CINT_OFFSET) +#define KINETIS_EDMA_INT (KINETIS_DMAC_BASE + KINETIS_EDMA_INT_OFFSET) +#define KINETIS_EDMA_ERR (KINETIS_DMAC_BASE + KINETIS_EDMA_ERR_OFFSET) +#define KINETIS_EDMA_HRS (KINETIS_DMAC_BASE + KINETIS_EDMA_HRS_OFFSET) +#define KINETIS_EDMA_EARS (KINETIS_DMAC_BASE + KINETIS_EDMA_EARS_OFFSET) + +#define KINETIS_EDMA_DCHPRI(n) (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI_OFFSET(n)) + +#define KINETIS_EDMA_DCHPRI0 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI0_OFFSET) +#define KINETIS_EDMA_DCHPRI1 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI1_OFFSET) +#define KINETIS_EDMA_DCHPRI2 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI2_OFFSET) +#define KINETIS_EDMA_DCHPRI3 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI3_OFFSET) +#define KINETIS_EDMA_DCHPRI4 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI4_OFFSET) +#define KINETIS_EDMA_DCHPRI5 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI5_OFFSET) +#define KINETIS_EDMA_DCHPRI6 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI6_OFFSET) +#define KINETIS_EDMA_DCHPRI7 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI7_OFFSET) +#define KINETIS_EDMA_DCHPRI8 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI8_OFFSET) +#define KINETIS_EDMA_DCHPRI9 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI9_OFFSET) +#define KINETIS_EDMA_DCHPRI10 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI10_OFFSET) +#define KINETIS_EDMA_DCHPRI11 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI11_OFFSET) +#define KINETIS_EDMA_DCHPRI12 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI12_OFFSET) +#define KINETIS_EDMA_DCHPRI13 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI13_OFFSET) +#define KINETIS_EDMA_DCHPRI14 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI14_OFFSET) +#define KINETIS_EDMA_DCHPRI15 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI15_OFFSET) + +/* Transfer Control Descriptor (TCD) */ + +#define KINETIS_EDMA_TCD_BASE(n) (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD_OFFSET(n)) +#define KINETIS_EDMA_TCD_SADDR(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_SADDR_OFFSET) +#define KINETIS_EDMA_TCD_SOFF(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_SOFF_OFFSET) +#define KINETIS_EDMA_TCD_ATTR(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_ATTR_OFFSET) +#define KINETIS_EDMA_TCD_NBYTES_ML(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD_SLAST(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_SLAST_OFFSET) +#define KINETIS_EDMA_TCD_DADDR(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_DADDR_OFFSET) +#define KINETIS_EDMA_TCD_DOFF(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_DOFF_OFFSET) +#define KINETIS_EDMA_TCD_CITER_ELINK(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD_DLASTSGA(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD_CSR(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_CSR_OFFSET) +#define KINETIS_EDMA_TCD_BITER_ELINK(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD0_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_SADDR_OFFSET) +#define KINETIS_EDMA_TCD0_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_SOFF_OFFSET) +#define KINETIS_EDMA_TCD0_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_ATTR_OFFSET) +#define KINETIS_EDMA_TCD0_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD0_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_SLAST_OFFSET) +#define KINETIS_EDMA_TCD0_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_DADDR_OFFSET) +#define KINETIS_EDMA_TCD0_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_DOFF_OFFSET) +#define KINETIS_EDMA_TCD0_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD0_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD0_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_CSR_OFFSET) +#define KINETIS_EDMA_TCD0_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD1_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_SADDR_OFFSET) +#define KINETIS_EDMA_TCD1_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_SOFF_OFFSET) +#define KINETIS_EDMA_TCD1_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_ATTR_OFFSET) +#define KINETIS_EDMA_TCD1_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD1_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_SLAST_OFFSET) +#define KINETIS_EDMA_TCD1_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_DADDR_OFFSET) +#define KINETIS_EDMA_TCD1_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_DOFF_OFFSET) +#define KINETIS_EDMA_TCD1_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD1_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD1_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_CSR_OFFSET) +#define KINETIS_EDMA_TCD1_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD2_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_SADDR_OFFSET) +#define KINETIS_EDMA_TCD2_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_SOFF_OFFSET) +#define KINETIS_EDMA_TCD2_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_ATTR_OFFSET) +#define KINETIS_EDMA_TCD2_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD2_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_SLAST_OFFSET) +#define KINETIS_EDMA_TCD2_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_DADDR_OFFSET) +#define KINETIS_EDMA_TCD2_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_DOFF_OFFSET) +#define KINETIS_EDMA_TCD2_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD2_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD2_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_CSR_OFFSET) +#define KINETIS_EDMA_TCD2_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD3_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_SADDR_OFFSET) +#define KINETIS_EDMA_TCD3_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_SOFF_OFFSET) +#define KINETIS_EDMA_TCD3_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_ATTR_OFFSET) +#define KINETIS_EDMA_TCD3_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD3_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_SLAST_OFFSET) +#define KINETIS_EDMA_TCD3_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_DADDR_OFFSET) +#define KINETIS_EDMA_TCD3_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_DOFF_OFFSET) +#define KINETIS_EDMA_TCD3_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD3_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD3_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_CSR_OFFSET) +#define KINETIS_EDMA_TCD3_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD4_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_SADDR_OFFSET) +#define KINETIS_EDMA_TCD4_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_SOFF_OFFSET) +#define KINETIS_EDMA_TCD4_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_ATTR_OFFSET) +#define KINETIS_EDMA_TCD4_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD4_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_SLAST_OFFSET) +#define KINETIS_EDMA_TCD4_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_DADDR_OFFSET) +#define KINETIS_EDMA_TCD4_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_DOFF_OFFSET) +#define KINETIS_EDMA_TCD4_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD4_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD4_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_CSR_OFFSET) +#define KINETIS_EDMA_TCD4_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD5_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_SADDR_OFFSET) +#define KINETIS_EDMA_TCD5_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_SOFF_OFFSET) +#define KINETIS_EDMA_TCD5_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_ATTR_OFFSET) +#define KINETIS_EDMA_TCD5_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD5_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_SLAST_OFFSET) +#define KINETIS_EDMA_TCD5_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_DADDR_OFFSET) +#define KINETIS_EDMA_TCD5_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_DOFF_OFFSET) +#define KINETIS_EDMA_TCD5_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD5_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD5_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_CSR_OFFSET) +#define KINETIS_EDMA_TCD5_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD6_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_SADDR_OFFSET) +#define KINETIS_EDMA_TCD6_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_SOFF_OFFSET) +#define KINETIS_EDMA_TCD6_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_ATTR_OFFSET) +#define KINETIS_EDMA_TCD6_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD6_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_SLAST_OFFSET) +#define KINETIS_EDMA_TCD6_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_DADDR_OFFSET) +#define KINETIS_EDMA_TCD6_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_DOFF_OFFSET) +#define KINETIS_EDMA_TCD6_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD6_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD6_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_CSR_OFFSET) +#define KINETIS_EDMA_TCD6_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD7_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_SADDR_OFFSET) +#define KINETIS_EDMA_TCD7_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_SOFF_OFFSET) +#define KINETIS_EDMA_TCD7_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_ATTR_OFFSET) +#define KINETIS_EDMA_TCD7_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD7_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_SLAST_OFFSET) +#define KINETIS_EDMA_TCD7_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_DADDR_OFFSET) +#define KINETIS_EDMA_TCD7_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_DOFF_OFFSET) +#define KINETIS_EDMA_TCD7_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD7_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD7_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_CSR_OFFSET) +#define KINETIS_EDMA_TCD7_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD8_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_SADDR_OFFSET) +#define KINETIS_EDMA_TCD8_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_SOFF_OFFSET) +#define KINETIS_EDMA_TCD8_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_ATTR_OFFSET) +#define KINETIS_EDMA_TCD8_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD8_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_SLAST_OFFSET) +#define KINETIS_EDMA_TCD8_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_DADDR_OFFSET) +#define KINETIS_EDMA_TCD8_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_DOFF_OFFSET) +#define KINETIS_EDMA_TCD8_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD8_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD8_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_CSR_OFFSET) +#define KINETIS_EDMA_TCD8_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD9_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_SADDR_OFFSET) +#define KINETIS_EDMA_TCD9_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_SOFF_OFFSET) +#define KINETIS_EDMA_TCD9_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_ATTR_OFFSET) +#define KINETIS_EDMA_TCD9_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD9_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_SLAST_OFFSET) +#define KINETIS_EDMA_TCD9_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_DADDR_OFFSET) +#define KINETIS_EDMA_TCD9_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_DOFF_OFFSET) +#define KINETIS_EDMA_TCD9_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD9_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD9_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_CSR_OFFSET) +#define KINETIS_EDMA_TCD9_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD10_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_SADDR_OFFSET) +#define KINETIS_EDMA_TCD10_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_SOFF_OFFSET) +#define KINETIS_EDMA_TCD10_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_ATTR_OFFSET) +#define KINETIS_EDMA_TCD10_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD10_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_SLAST_OFFSET) +#define KINETIS_EDMA_TCD10_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_DADDR_OFFSET) +#define KINETIS_EDMA_TCD10_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_DOFF_OFFSET) +#define KINETIS_EDMA_TCD10_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD10_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD10_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_CSR_OFFSET) +#define KINETIS_EDMA_TCD10_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD11_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_SADDR_OFFSET) +#define KINETIS_EDMA_TCD11_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_SOFF_OFFSET) +#define KINETIS_EDMA_TCD11_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_ATTR_OFFSET) +#define KINETIS_EDMA_TCD11_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD11_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_SLAST_OFFSET) +#define KINETIS_EDMA_TCD11_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_DADDR_OFFSET) +#define KINETIS_EDMA_TCD11_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_DOFF_OFFSET) +#define KINETIS_EDMA_TCD11_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD11_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD11_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_CSR_OFFSET) +#define KINETIS_EDMA_TCD11_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD12_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_SADDR_OFFSET) +#define KINETIS_EDMA_TCD12_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_SOFF_OFFSET) +#define KINETIS_EDMA_TCD12_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_ATTR_OFFSET) +#define KINETIS_EDMA_TCD12_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD12_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_SLAST_OFFSET) +#define KINETIS_EDMA_TCD12_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_DADDR_OFFSET) +#define KINETIS_EDMA_TCD12_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_DOFF_OFFSET) +#define KINETIS_EDMA_TCD12_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD12_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD12_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_CSR_OFFSET) +#define KINETIS_EDMA_TCD12_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD13_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_SADDR_OFFSET) +#define KINETIS_EDMA_TCD13_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_SOFF_OFFSET) +#define KINETIS_EDMA_TCD13_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_ATTR_OFFSET) +#define KINETIS_EDMA_TCD13_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD13_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_SLAST_OFFSET) +#define KINETIS_EDMA_TCD13_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_DADDR_OFFSET) +#define KINETIS_EDMA_TCD13_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_DOFF_OFFSET) +#define KINETIS_EDMA_TCD13_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD13_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD13_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_CSR_OFFSET) +#define KINETIS_EDMA_TCD13_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD14_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_SADDR_OFFSET) +#define KINETIS_EDMA_TCD14_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_SOFF_OFFSET) +#define KINETIS_EDMA_TCD14_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_ATTR_OFFSET) +#define KINETIS_EDMA_TCD14_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD14_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_SLAST_OFFSET) +#define KINETIS_EDMA_TCD14_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_DADDR_OFFSET) +#define KINETIS_EDMA_TCD14_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_DOFF_OFFSET) +#define KINETIS_EDMA_TCD14_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD14_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD14_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_CSR_OFFSET) +#define KINETIS_EDMA_TCD14_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_BITER_ELINK_OFFSET) + +#define KINETIS_EDMA_TCD15_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_SADDR_OFFSET) +#define KINETIS_EDMA_TCD15_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_SOFF_OFFSET) +#define KINETIS_EDMA_TCD15_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_ATTR_OFFSET) +#define KINETIS_EDMA_TCD15_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_NBYTES_ML_OFFSET) +#define KINETIS_EDMA_TCD15_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_SLAST_OFFSET) +#define KINETIS_EDMA_TCD15_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_DADDR_OFFSET) +#define KINETIS_EDMA_TCD15_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_DOFF_OFFSET) +#define KINETIS_EDMA_TCD15_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_CITER_ELINK_OFFSET) +#define KINETIS_EDMA_TCD15_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_DLASTSGA_OFFSET) +#define KINETIS_EDMA_TCD15_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_CSR_OFFSET) +#define KINETIS_EDMA_TCD15_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_BITER_ELINK_OFFSET) + +/* eDMA Bit-Field Definitions ***********************************************/ + +/* Control */ + + /* Bit 0: Reserved */ +#define EDMA_CR_EDBG (1 << 1) /* Bit 1: Enable Debug */ +#define EDMA_CR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration */ +#define EDMA_CR_ERGA (1 << 3) /* Bit 3: Enable Round Robin Group Arbitration */ +#define EDMA_CR_HOE (1 << 4) /* Bit 4: Halt On Error */ +#define EDMA_CR_HALT (1 << 5) /* Bit 5: Halt DMA Operations */ +#define EDMA_CR_CLM (1 << 6) /* Bit 6: Continuous Link Mode */ +#define EDMA_CR_EMLM (1 << 7) /* Bit 7: Enable Minor Loop Mapping */ + /* Bit 8-15: Reserved */ +#define EDMA_CR_ECX (1 << 16) /* Bit 16: Error Cancel Transfer */ +#define EDMA_CR_CX (1 << 17) /* Bit 17: Cancel Transfer */ + /* Bits 18-23: Reserved */ + /* Bits 24-30: eDMA version number (reserved) */ +#define EDMA_CR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status */ + +/* Error Status */ + +#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error */ +#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error */ +#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error */ +#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error */ +#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error */ +#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error */ +#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error */ +#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error */ +#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 8-11: Error Channel Number or + * Canceled Channel Number */ +#define EDMA_ES_ERRCHN_MASK (15 << EDMA_ES_ERRCHN_SHIFT) + /* Bits 23-13: Reserved */ +#define EDMA_ES_CPE (1 << 14) /* Bit 14: Channel Priority Error */ + /* Bit 15: Reserved */ +#define EDMA_ES_ECX (1 << 16) /* Bit 16: Transfer Canceled */ + /* Bits 17-30: Reserved */ +#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */ + +/* Enable Request */ + +#define EDMA_ERQ(n) ((uint32_t)1 << (n)) /* Bit n: Enable DMA request n */ + +/* Enable Error Interrupt */ + +#define EDMA_EEI(n) ((uint32_t)1 << (n)) /* Bit n: Enable error interrupt n */ + +/* Clear Enable Error Interrupt */ + +#define EDMA_CEEI_SHIFT (0) /* Bits 0-3: Clear Enable Error Interrupt */ +#define EDMA_CEEI_MASK (15 << EDMA_CEEI_SHIFT) +# define EDMA_CEEI(n) ((uint32_t)(n) << EDMA_CEEI_SHIFT) + /* Bit 54-: Reserved */ +#define EDMA_CEEI_CAEE (1 << 6) /* Bit 6: Clear All Enable Error Interrupts */ +#define EDMA_CEEI_NOP (1 << 7) /* Bit 7: No Op enable */ + +/* Set Enable Error Interrupt */ + +#define EDMA_SEEI_SHIFT (0) /* Bits 0-3: Set Enable Error Interrupt */ +#define EDMA_SEEI_MASK (15 << EDMA_SEEI_SHIFT) +# define EDMA_SEEI(n) ((uint32_t)(n) << EDMA_SEEI_SHIFT) + /* Bit 54-: Reserved */ +#define EDMA_SEEI_SAEE (1 << 6) /* Bit 6: Set All Enable Error Interrupts */ +#define EDMA_SEEI_NOP (1 << 7) /* Bit 7: No Op enable */ + +/* Clear Enable Request */ + +#define EDMA_CERQ_SHIFT (0) /* Bits 0-3: Clear Enable Request */ +#define EDMA_CERQ_MASK (15 << EDMA_CERQ_SHIFT) +# define EDMA_CERQ(n) ((uint32_t)(n) << EDMA_CERQ_SHIFT) + /* Bit 4-5: Reserved */ +#define EDMA_CERQ_CAER (1 << 6) /* Bit 6: Clear All Enable Requests */ +#define EDMA_CERQ_NOP (1 << 7) /* Bit 7: No Op enable */ + +/* Set Enable Request */ + +#define EDMA_SERQ_SHIFT (0) /* Bits 0-3: Set Enable Request */ +#define EDMA_SERQ_MASK (15 << EDMA_SERQ_SHIFT) +# define EDMA_SERQ(n) ((uint32_t)(n) << EDMA_SERQ_SHIFT) + /* Bit 4-5: Reserved */ +#define EDMA_SERQ_SAER (1 << 6) /* Bit 6: Set All Enable Requests */ +#define EDMA_SERQ_NOP (1 << 7) /* Bit 7: No Op enable */ + +/* Clear DONE Status Bit */ + +#define EDMA_CDNE_SHIFT (0) /* Bits 0-3: Clear DONE Bit */ +#define EDMA_CDNE_MASK (15 << EDMA_CDNE_SHIFT) +# define EDMA_CDNE(n) ((uint32_t)(n) << EDMA_CDNE_SHIFT) + /* Bit 4-5: Reserved */ +#define EDMA_CDNE_CADN (1 << 6) /* Bit 6: Clears All DONE Bits */ +#define EDMA_CDNE_NOP (1 << 7) /* Bit 7: No Op enable */ + +/* Set START Bit */ + +#define EDMA_SSRT_SHIFT (0) /* Bits 0-3: Set START Bit */ +#define EDMA_SSRT_MASK (15 << EDMA_SSRT_SHIFT) +# define EDMA_SSRT(n) ((uint32_t)(n) << EDMA_SSRT_SHIFT) + /* Bit 4-5: Reserved */ +#define EDMA_SSRT_SAST (1 << 6) /* Bit 6: Set All START Bits (activates all channels) */ +#define EDMA_SSRT_NOP (1 << 7) /* Bit 7: No Op enable */ + +/* Clear Error */ + +#define EDMA_CERR_SHIFT (0) /* Bits 0-3: Clear Error Indicator */ +#define EDMA_CERR_MASK (15 << EDMA_CERR_SHIFT) +# define EDMA_CERR(n) ((uint32_t)(n) << EDMA_CERR_SHIFT) + /* Bit 4-5: Reserved */ +#define EDMA_CERR_CAEI (1 << 6) /* Bit 6: Clear All Error Indicators */ +#define EDMA_CERR_NOP (1 << 7) /* Bit 7: No Op enable */ + +/* Clear Interrupt Request */ + +#define EDMA_CINT_SHIFT (0) /* Bits 0-3: Clear Interrupt Request */ +#define EDMA_CINT_MASK (15 << EDMA_CINT_SHIFT) +# define EDMA_CINT(n) ((uint32_t)(n) << EDMA_CINT_SHIFT) + /* Bit 4-5: Reserved */ +#define EDMA_CINT_CAIR (1 << 6) /* Bit 6: Clear All Interrupt Requests */ +#define EDMA_CINT_NOP (1 << 7) /* Bit 7: No Op enable */ + +/* Interrupt Request */ + +#define EDMA_INT(n) ((uint32_t)1 << (n)) /* Bit n: Interrupt Request n */ + +/* Error */ + +#define EDMA_ERR(n) ((uint32_t)1 << (n)) /* Bit n: Error In Channel n */ + +/* Hardware Request Status */ + +#define EDMA_HRS(n) ((uint32_t)1 << (n)) /* Bit n: Hardware Request Status + * Channel n */ + +/* Enable Asynchronous Request in Stop */ + +#define EDMA_EARS(n) ((uint32_t)1 << (n)) /* Bit n: Enable asynchronous DMA + * request in stop mode for channel n */ + +/* Channel n Priority */ + +#define EDMA_DCHPRI_CHPRI_SHIFT (0) /* Bits 0-3: Channel n Arbitration Priority */ +#define EDMA_DCHPRI_CHPRI_MASK (15 << EDMA_DCHPRI_CHPRI_SHIFT) +# define EDMA_DCHPRI_CHPRI(n) ((uint32_t)(n) << EDMA_DCHPRI_CHPRI_SHIFT) + /* Bit 4-5: Reserved */ +#define EDMA_DCHPRI_DPA (1 << 6) /* Bit 6: Disable Preempt Ability */ +#define EDMA_DCHPRI_ECP (1 << 7) /* Bit 7: Enable Channel Preemption */ + +/* TCD Source Address (32-bit address) */ + +/* TCD Signed Source Address Offset (16-bit offset) */ + +/* TCD Transfer Attributes */ + +#define TCD_ATTR_SIZE_8BIT (0) /* 8-bit */ +#define TCD_ATTR_SIZE_16BIT (1) /* 16-bit */ +#define TCD_ATTR_SIZE_32BIT (2) /* 32-bit */ +#define TCD_ATTR_SIZE_64BIT (3) /* 64-bit */ +#define TCD_ATTR_SIZE_256BIT (5) /* 32-byte burst (4 beats of 64 bits) */ + +#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination data transfer size */ +#define EDMA_TCD_ATTR_DSIZE_MASK (7 << EDMA_TCD_ATTR_DSIZE_SHIFT) +# define EDMA_TCD_ATTR_DSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */ +# define EDMA_TCD_ATTR_DSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */ +# define EDMA_TCD_ATTR_DSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 16-bit */ +# define EDMA_TCD_ATTR_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */ +# define EDMA_TCD_ATTR_DSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 64-bit */ +# define EDMA_TCD_ATTR_DSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-byte burst */ + +#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo */ +#define EDMA_TCD_ATTR_DMOD_MASK (31 << EDMA_TCD_ATTR_DMOD_SHIFT) +# define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT) +#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source data transfer size */ +#define EDMA_TCD_ATTR_SSIZE_MASK (7 << EDMA_TCD_ATTR_SSIZE_SHIFT) +# define EDMA_TCD_ATTR_SSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ +# define EDMA_TCD_ATTR_SSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */ +# define EDMA_TCD_ATTR_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ +# define EDMA_TCD_ATTR_SSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */ +# define EDMA_TCD_ATTR_SSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte burst */ + +#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo */ +#define EDMA_TCD_ATTR_SMOD_MASK (31 << EDMA_TCD_ATTR_SMOD_SHIFT) +# define EDMA_TCD_ATTR_SMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SMOD_SHIFT) + +/* TCD Signed Minor Loop Offset / Byte Count */ + +/* Minor Byte Count (Minor Loop Mapping Disabled -- 32-bit byte count) */ + +/* TCD Signed Minor Loop Offset / Byte Count */ + +/* Minor Byte Count (Minor Loop Mapping Enabled, offset disabled) */ + +#define EDMA_TCD_NBYTES_ML_NBYTES_SHIFT (0) /* Bits 0-29: Minor Byte Transfer Count */ +#define EDMA_TCD_NBYTES_ML_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_ML_NBYTES_SHIFT) +# define EDMA_TCD_NBYTES_ML_NBYTES(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_ML_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_ML_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset enable */ +#define EDMA_TCD_NBYTES_ML_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */ + +/* TCD Signed Minor Loop Offset / Byte Count */ + +/* Minor Byte Count (Minor Loop Mapping Enabled, offset enabled) */ + +#define EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT (0) /* Bits 0-9: Minor Byte Transfer Count */ +#define EDMA_TCD_NBYTES_MLOFF_NBYTES_MASK (0x3ff << EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT) +# define EDMA_TCD_NBYTES_MLOFF_NBYTES(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT (10) /* Bits 10-29: Minor Byte Transfer Count */ +#define EDMA_TCD_NBYTES_MLOFF_MLOFF_MASK (0xfffff << EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT) +# define EDMA_TCD_NBYTES_MLOFF_MLOFF(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT) +#define EDMA_TCD_NBYTES_MLOFF_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset enable */ +#define EDMA_TCD_NBYTES_MLOFF_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */ + +/* TCD Last Source Address Adjustment (32-bit address adjustment) */ + +/* TCD Destination Address (32-bit address) */ + +/* TCD Signed Destination Address Offset (16-bit signed address offset) */ + +/* TCD Current Minor Loop Link, Major Loop Count (Channel linking disabled) */ + +#define EDMA_TCD_CITER_CITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */ +#define EDMA_TCD_CITER_CITER_MASK (0x7fff << EDMA_TCD_CITER_CITER_SHIFT) +# define EDMA_TCD_CITER_CITER(n) ((uint32_t)(n) << EDMA_TCD_CITER_CITER_SHIFT) +#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking + * on minor-loop complete */ + +/* TCD Current Minor Loop Link, Major Loop Count + * (Channel linking enabled) + */ + +#define EDMA_TCD_CITER_ELINK_CITER_SHIFT (0) /* Bit 0-8: Current major iteration count */ +#define EDMA_TCD_CITER_ELINK_CITER_MASK (0x1ff << EDMA_TCD_CITER_ELINK_CITER_SHIFT) +# define EDMA_TCD_CITER_ELINK_CITER(n) ((uint32_t)(n) << EDMA_TCD_CITER_ELINK_CITER_SHIFT) +#define EDMA_TCD_CITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-12: Minor Loop Link Channel Number */ +#define EDMA_TCD_CITER_ELINK_LINKCH_MASK (15 << EDMA_TCD_CITER_ELINK_LINKCH_SHIFT) +# define EDMA_TCD_CITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_CITER_ELINK_LINKCH_SHIFT) + /* Bit 13-14: Reserved */ +#define EDMA_TCD_CITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking + * on minor-loop complete */ + +/* TCD Last Destination Address Adjustment/Scatter Gather Address + * (32-bit address) + */ + +/* TCD Control and Status */ + +#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start */ +#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable an interrupt when major + * iteration count completes */ +#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable an interrupt when major + * counter is half complete */ +#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request */ +#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing */ +#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable channel-to-channel linking + * on major loop complete */ +#define EDMA_TCD_CSR_ACTIVE (1 << 6) /* Bit 6: Channel Active */ +#define EDMA_TCD_CSR_DONE (1 << 7) /* Bit 7: Channel Done */ +#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-11: Major Loop Link Channel Number */ +#define EDMA_TCD_CSR_MAJORLINKCH_MASK (15 << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) +# define EDMA_TCD_CSR_MAJORLINKCH(n) ((uint32_t)(n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) + /* Bit 112-3: Reserved */ +#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control */ +#define EDMA_TCD_CSR_BWC_MASK (3 << EDMA_TCD_CSR_BWC_SHIFT) +# define EDMA_TCD_CSR_BWC_NONE (0 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */ +# define EDMA_TCD_CSR_BWC_4CYCLES (2 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 + * cycles after each R/W */ +# define EDMA_TCD_CSR_BWC_8CYCLES (3 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 + * cycles after each R/W */ + +/* TCD Beginning Minor Loop Link, Major Loop Count + * (Channel linking disabled) + */ + +#define EDMA_TCD_BITER_BITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */ +#define EDMA_TCD_BITER_BITER_MASK (0x7fff << EDMA_TCD_BITER_BITER_SHIFT) +# define EDMA_TCD_BITER_BITER(n) ((uint32_t)(n) << EDMA_TCD_BITER_BITER_SHIFT) +#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking + * on minor-loop complete */ + +/* TCD Beginning Minor Loop Link, Major Loop Count + * (Channel linking enabled) + */ + +#define EDMA_TCD_BITER_ELINK_BITER_SHIFT (0) /* Bit 0-8: Current major iteration count */ +#define EDMA_TCD_BITER_ELINK_BITER_MASK (0x1ff << EDMA_TCD_BITER_ELINK_BITER_SHIFT) +# define EDMA_TCD_BITER_ELINK_BITER(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_BITER_SHIFT) +#define EDMA_TCD_BITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-12: Link Channel Number */ +#define EDMA_TCD_BITER_ELINK_LINKCH_MASK (15 << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT) +# define EDMA_TCD_BITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT) + /* Bit 13-4: Reserved */ +#define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking + * on minor-loop complete */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* In-memory representation of the 32-byte Transfer Control Descriptor + * (TCD) + */ + +struct kinetis_edmatcd_s +{ + sq_entry_t node; + uint8_t flags; /* See EDMA_CONFIG_* definitions */ + uint32_t saddr; /* Offset: 0x0000 TCD Source Address */ + uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */ + uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */ + uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */ + uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */ + uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */ + uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */ + uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */ + uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t csr; /* Offset: 0x001c TCD Control and Status */ + uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */ +}; + +#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EDMA_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_usbhs.h b/arch/arm/src/kinetis/hardware/kinetis_usbhs.h index 68f0d017fa0..ce9259514d5 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_usbhs.h +++ b/arch/arm/src/kinetis/hardware/kinetis_usbhs.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_usbhs.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_alarm.h b/arch/arm/src/kinetis/kinetis_alarm.h index 1a3ae797c7c..a08e50c0b79 100644 --- a/arch/arm/src/kinetis/kinetis_alarm.h +++ b/arch/arm/src/kinetis/kinetis_alarm.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_alarm.h * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: Matias v01d + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_dma.c b/arch/arm/src/kinetis/kinetis_dma.c deleted file mode 100644 index 13aec599f70..00000000000 --- a/arch/arm/src/kinetis/kinetis_dma.c +++ /dev/null @@ -1,471 +0,0 @@ -/**************************************************************************** - * arch/arm/src/kinetis/kinetis_dma.c - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Jan Okle - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include "arm_arch.h" -#include "arm_internal.h" - -#include "kinetis_config.h" -#include "chip.h" -#include "kinetis_dma.h" -#include "hardware/kinetis_dmamux.h" -#include "hardware/kinetis_sim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef DMA_CHN_PER_GROUP -# define DMA_CHN_PER_GROUP KINETIS_NDMACH /* Number of channels per group */ -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct kinetis_dma_ch -{ - bool used; - uint8_t ind; - uint8_t irq; - enum kinetis_dma_direction_e dir; - enum kinetis_dma_data_sz_e data_sz; - dma_callback_t callback; - void *arg; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct kinetis_dma_ch g_channels[KINETIS_NDMACH]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int kinetis_dmainterrupt_int(int irq, void *context, - struct kinetis_dma_ch *ch) -{ - /* Clear bit in the interrupt */ - - putreg8(ch->ind, KINETIS_DMA_CINT); - - /* Invoke the callback */ - - if (ch->callback) - { - ch->callback((DMA_HANDLE)&ch, ch->arg, 0); - } - - return OK; -} - -static int kinetis_dmainterrupt(int irq, void *context, void *arg) -{ - uint8_t irq_int = *(uint8_t *)arg; - uint32_t regval; - regval = getreg32(KINETIS_DMA_INT); - - /* Channel irq_int and irq_int + DMA_CHN_PER_GROUP use the same arg. Check - * which one requested an interrupt - */ - - if ((regval & (1 << irq_int)) != 0) - { - kinetis_dmainterrupt_int(irq, context, &g_channels[irq_int]); - } - - if ((regval & (1 << (irq_int + DMA_CHN_PER_GROUP))) != 0) - { - kinetis_dmainterrupt_int(irq, context, - &g_channels[irq_int + DMA_CHN_PER_GROUP]); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -size_t kinetis_dmaresidual(DMA_HANDLE handle) -{ - struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle; - - /* Channel Linking Disabled */ - - return ((getreg16(KINETIS_DMA_TCD_CITER(ch->ind)) >> - DMA_TCD_CITER2_SHIFT) & DMA_TCD_CITER2_MASK); -} - -/**************************************************************************** - * Name: kinetis_dmainitialize - * - * Description: - * Initialize the DMA subsystem. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void weak_function arm_dma_initialize(void) -{ - int i; - uint32_t regval; - int ret; - - for (i = KINETIS_NDMACH - 1; i >= 0; i--) - { - g_channels[i].ind = i; - g_channels[i].used = false; - g_channels[i].irq = KINETIS_IRQ_FIRST + (i % DMA_CHN_PER_GROUP); - - if (i < DMA_CHN_PER_GROUP) - { - /* Attach DMA interrupt */ - - ret = irq_attach(g_channels[i].irq, kinetis_dmainterrupt, - (void *)&g_channels[i].ind); - - if (ret == OK) - { - /* Enable the IRQ at the NVIC (still disabled at the DMA - * controller) - */ - - up_enable_irq(g_channels[i].irq); - } - else - { - g_channels[i].used = true; - g_channels[i + DMA_CHN_PER_GROUP].used = true; - } - } - } - - /* Enable clocking for DMA */ - - regval = getreg32(KINETIS_SIM_SCGC7); - regval |= SIM_SCGC7_DMA; - putreg32(regval, KINETIS_SIM_SCGC7); - - /* Configure DMA for round robin arbitration */ - - regval = 0; - regval |= DMA_CR_ERCA | DMA_CR_ERGA; - putreg32(regval, KINETIS_DMA_CR); - - /* Enable clocking for the DMA mux */ - - regval = getreg32(KINETIS_SIM_SCGC6); - regval |= SIM_SCGC6_DMAMUX0; - putreg32(regval, KINETIS_SIM_SCGC6); -} - -/**************************************************************************** - * Name: kinetis_dmachannel - * - * Description: - * Allocate a DMA channel. This function sets aside a DMA channel and - * gives the caller exclusive access to the DMA channel. - * - * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. - * - ****************************************************************************/ - -DMA_HANDLE kinetis_dmachannel(uint8_t src, uint32_t per_addr, - enum kinetis_dma_data_sz_e per_data_sz, - enum kinetis_dma_direction_e dir) -{ - int i; - int ch_ind; - uint8_t regval8; - uint16_t regval16; - irqstate_t flags; - struct kinetis_dma_ch *ch; - - /* Find available channel */ - - ch_ind = -1; - flags = enter_critical_section(); - for (i = 0; i < KINETIS_NDMACH; i++) - { - if (!g_channels[i].used) - { - ch_ind = i; - g_channels[ch_ind].used = true; - break; - } - } - - leave_critical_section(flags); - - if (ch_ind == -1) - { - /* No available channel */ - - return NULL; - } - - ch = &g_channels[ch_ind]; - - /* Copy arguments */ - - ch->dir = dir; - ch->data_sz = per_data_sz; - - /* DMAMUX Set DMA channel source and enable it */ - - regval8 = ((((uint8_t)src) << DMAMUX_CHCFG_SOURCE_SHIFT) & - DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_ENBL; - putreg8(regval8, KINETIS_DMAMUX_CHCFG(ch_ind)); - - /* DMA Set peripheral address in TCD */ - - if (ch->dir == KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY) - { - putreg32(per_addr, KINETIS_DMA_TCD_SADDR(ch->ind)); - putreg16(0, KINETIS_DMA_TCD_SOFF(ch->ind)); - putreg32(0, KINETIS_DMA_TCD_SLAST(ch->ind)); - } - else if (ch->dir == KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL) - { - putreg32(per_addr, KINETIS_DMA_TCD_DADDR(ch->ind)); - putreg16(0, KINETIS_DMA_TCD_DOFF(ch->ind)); - putreg32(0, KINETIS_DMA_TCD_DLASTSGA(ch->ind)); - } - else - { - ch->used = false; - return NULL; - } - - /* Set data sizes */ - - regval16 = (DMA_TCD_ATTR_SSIZE_MASK & ((uint16_t)per_data_sz) << - DMA_TCD_ATTR_SSIZE_SHIFT); - regval16 |= (DMA_TCD_ATTR_DSIZE_MASK & ((uint16_t)per_data_sz) << - DMA_TCD_ATTR_DSIZE_SHIFT); - putreg16(regval16, KINETIS_DMA_TCD_ATTR(ch->ind)); - - /* Set minor loop count */ - - putreg32(1 << (uint8_t)per_data_sz, KINETIS_DMA_TCD_NBYTES(ch->ind)); - return (DMA_HANDLE)ch; -} - -/**************************************************************************** - * Name: kinetis_dmafree - * - * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must - * NEVER be used again until kinetis_dmachannel() is called again to - * re-gain a valid handle. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void kinetis_dmafree(DMA_HANDLE handle) -{ - struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle; - irqstate_t flags; - - DEBUGASSERT(handle != NULL); - - /* Disable DMA channel in the dmamux */ - - putreg8(0, KINETIS_DMAMUX_CHCFG(ch->ind)); - - flags = enter_critical_section(); - ch->used = false; - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: kinetis_dmasetup - * - * Description: - * Configure DMA for one transfer. - * - ****************************************************************************/ - -int kinetis_dmasetup(DMA_HANDLE handle, uint32_t mem_addr, size_t ntransfers, - uint16_t control) -{ - struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle; - uint16_t regval = 0; - uint32_t nbytes; - - if (ntransfers > (DMA_TCD_CITER2_MASK >> DMA_TCD_CITER2_SHIFT)) - { - return -EINVAL; - } - - DEBUGASSERT(handle != NULL); - - nbytes = (uint32_t)ntransfers * (uint32_t)(1 << (uint8_t)ch->data_sz); - - if (ch->dir == KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY) - { - putreg32(mem_addr, KINETIS_DMA_TCD_DADDR(ch->ind)); - putreg16(1 << (uint8_t)ch->data_sz, KINETIS_DMA_TCD_DOFF(ch->ind)); - putreg32(-nbytes, KINETIS_DMA_TCD_DLASTSGA(ch->ind)); - } - else if (ch->dir == KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL) - { - putreg32(mem_addr, KINETIS_DMA_TCD_SADDR(ch->ind)); - putreg16(1 << (uint8_t)ch->data_sz, KINETIS_DMA_TCD_SOFF(ch->ind)); - putreg32(-nbytes, KINETIS_DMA_TCD_SLAST(ch->ind)); - } - else - { - return -EINVAL; - } - - /* Set up channel with control word */ - - regval = (control & DMA_TCD_CSR_MAJORELINK) ? ch->ind : 0; - regval <<= DMA_TCD_CSR_MAJORLINKCH_SHIFT; - regval &= DMA_TCD_CSR_MAJORLINKCH_MASK; - regval |= (DMA_TCD_CSR_INTMAJOR | - (control & (DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_MAJORELINK))); - putreg16(regval, KINETIS_DMA_TCD_CSR(ch->ind)); - - /* Set major loop count */ - - putreg16(ntransfers, KINETIS_DMA_TCD_BITER(ch->ind)); - putreg16(ntransfers, KINETIS_DMA_TCD_CITER(ch->ind)); - - return OK; -} - -/**************************************************************************** - * Name: kinetis_dmastart - * - * Description: - * Start the DMA transfer - * - ****************************************************************************/ - -int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) -{ - struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle; - - DEBUGASSERT(handle != NULL); - - ch->callback = callback; - ch->arg = arg; - - /* Enable request register for this channel */ - - putreg8(ch->ind, KINETIS_DMA_SERQ); - - return OK; -} - -/**************************************************************************** - * Name: kinetis_dmastop - * - * Description: - * Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is - * reset and kinetis_dmasetup() must be called before kinetis_dmastart() - * can be called again - * - ****************************************************************************/ - -void kinetis_dmastop(DMA_HANDLE handle) -{ - struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle; - - DEBUGASSERT(handle != NULL); - - putreg8(ch->ind, KINETIS_DMA_CERQ); -} - -/**************************************************************************** - * Name: kinetis_dmasample - * - * Description: - * Sample DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA -void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs) -{ - DEBUGASSERT(handle != NULL); -} -#endif - -/**************************************************************************** - * Name: kinetis_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA -void kinetis_dmadump(DMA_HANDLE handle, const struct kinetis_dmaregs_s *regs, - const char *msg) -{ - DEBUGASSERT(handle != NULL); -} -#endif diff --git a/arch/arm/src/kinetis/kinetis_dma.h b/arch/arm/src/kinetis/kinetis_dma.h deleted file mode 100644 index f352080b5c3..00000000000 --- a/arch/arm/src/kinetis/kinetis_dma.h +++ /dev/null @@ -1,267 +0,0 @@ -/**************************************************************************** - * arch/arm/src/kinetis/kinetis_dma.h - * - * Copyright (C) 2016-2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Jan Okle - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H -#define __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "hardware/kinetis_dma.h" - -/**************************************************************************** - * Pre-processor Declarations - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -typedef FAR void *DMA_HANDLE; -typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); - -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is - * selected. - */ - -#ifdef CONFIG_DEBUG_DMA -struct kinetis_dmaglobalregs_s -{ -#warning "Missing logic" - /* Global Registers */ -}; - -struct kinetis_dmachanregs_s -{ -#warning "Missing logic" - /* Channel Registers */ -}; - -struct kinetis_dmaregs_s -{ - /* Global Registers */ - - struct kinetis_dmaglobalregs_s gbl; - - /* Channel Registers */ - - struct kinetis_dmachanregs_s ch; -}; -#endif - -enum kinetis_dma_direction_e -{ - KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY, - KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL -}; - -/* Kinetis data transfer size */ - -enum kinetis_dma_data_sz_e -{ - KINETIS_DMA_DATA_SZ_8BIT = 0, - KINETIS_DMA_DATA_SZ_16BIT = 1, - KINETIS_DMA_DATA_SZ_32BIT = 2, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: kinetis_dmainitialize - * - * Description: - * Initialize the GPDMA subsystem. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void kinetis_dmainitialize(void); - -/**************************************************************************** - * Name: kinetis_dmachannel - * - * Description: - * Allocate a DMA channel. This function sets aside a DMA channel and - * gives the caller exclusive access to the DMA channel. - * - * Input Parameters: - * src - DMA request source - * per_addr - Address of the peripheral data - * per_data_sz - Peripheral data size (register size). Note that if this - * does not agree with the peripheral register size, DMA - * transfers will silently fail during operation. - * dir - transfer direction - * - * Returned Value: - * One success, this function returns a non-NULL, void * DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. - * - ****************************************************************************/ - -DMA_HANDLE kinetis_dmachannel(uint8_t src, - uint32_t per_addr, - enum kinetis_dma_data_sz_e per_data_sz, - enum kinetis_dma_direction_e dir); - -/**************************************************************************** - * Name: kinetis_dmafree - * - * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must - * NEVER be used again until kinetis_dmachannel() is called again to re- - * gain a valid handle. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void kinetis_dmafree(DMA_HANDLE handle); - -/**************************************************************************** - * Name: kinetis_dmasetup - * - * Description: - * Configure DMA for one transfer. - * - * Input Parameters: - * mem_addr - Memory address - * ntransfers - Number of transfers. Must be 0<= ntransfers <= 0x7FFF - * control - Channel control configuration - * - * Returned Value: - * result: 0 if ok, negative else - * - ****************************************************************************/ - -int kinetis_dmasetup(DMA_HANDLE handle, uint32_t mem_addr, - size_t ntransfers, uint16_t control); - -/**************************************************************************** - * Name: kinetis_dmastart - * - * Description: - * Start the DMA transfer - * - ****************************************************************************/ - -int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); - -/**************************************************************************** - * Name: kinetis_dmastop - * - * Description: - * Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is - * reset and kinetis_dmasetup() must be called before kinetis_dmastart() - * can be called again - * - ****************************************************************************/ - -void kinetis_dmastop(DMA_HANDLE handle); - -/**************************************************************************** - * Name: kinetis_dmaresidual - * - * Description: - * Returns the number of transfers left - * - * Returned Value: - * Residual transfers - ****************************************************************************/ - -size_t kinetis_dmaresidual(DMA_HANDLE handle); - -/**************************************************************************** - * Name: kinetis_dmasample - * - * Description: - * Sample DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA -void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs); -#else -# define kinetis_dmasample(handle,regs) -#endif - -/**************************************************************************** - * Name: kinetis_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA -void kinetis_dmadump(DMA_HANDLE handle, const struct kinetis_dmaregs_s *regs, - const char *msg); -#else -# define kinetis_dmadump(handle,regs,msg) -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H */ diff --git a/arch/arm/src/kinetis/kinetis_edma.c b/arch/arm/src/kinetis/kinetis_edma.c new file mode 100644 index 00000000000..f0b14bee923 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_edma.c @@ -0,0 +1,1464 @@ +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_edma.c + * + * Copyright (C) 2019, 2021 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * This file was leveraged from the NuttX S32K port. Portions of that eDMA + * logic derived from NXP sample code which has a compatible BSD 3-clause + * license: + * + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_arch.h" +#include "arm_internal.h" +#include "sched/sched.h" + +#include "chip.h" +#include "hardware/kinetis_edma.h" +#include "hardware/kinetis_dmamux.h" +#include "kinetis_edma.h" +#include "hardware/kinetis_sim.h" + +#ifdef CONFIG_KINETIS_EDMA + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TCD Alignment. + * + * eDMA TCDs must be aligned with the D-Cache line boundaries to facilitate + * cache operations on the TCDs when the D-Cache is enabled. + * + * NOTE: The TCDs are 32-bytes in length. We implicitly assume that the + * D-Cache line size is also 32-bits. Otherwise, padding would be required + * at the ends of the TCDS and buffers to protect data after the end of from + * invalidation. + */ + +#ifdef CONFIG_ARMV7M_DCACHE +/* Align to the cache line size which we assume is >= 8 */ + +# define EDMA_ALIGN ARMV7M_DCACHE_LINESIZE +# define EDMA_ALIGN_MASK (EDMA_ALIGN-1) +# define EDMA_ALIGN_UP(n) (((n) + EDMA_ALIGN_MASK) & ~EDMA_ALIGN_MASK) + +#else +/* Special alignment is not required in this case, + * but we will align to 8-bytes + */ + +# define EDMA_ALIGN 8 +# define EDMA_ALIGN_MASK 7 +# define EDMA_ALIGN_UP(n) (((n) + 7) & ~7) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* State of a DMA channel */ + +enum kinetis_dmastate_e +{ + KINETIS_DMA_IDLE = 0, /* No DMA in progress */ + KINETIS_DMA_CONFIGURED, /* DMA configured, but not yet started */ + KINETIS_DMA_ACTIVE /* DMA has been started and is in progress */ +}; + +/* This structure describes one DMA channel */ + +struct kinetis_dmach_s +{ + uint8_t chan; /* DMA channel number (0-KINETIS_EDMA_NCHANNELS) */ + bool inuse; /* true: The DMA channel is in use */ + uint8_t dmamux; /* The DMAMUX channel selection */ + uint8_t ttype; /* Transfer type: M2M, M2P, P2M, or P2P */ + uint8_t state; /* Channel state. See enum kinetis_dmastate_e */ + uint32_t flags; /* DMA channel flags */ + edma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ + +#if CONFIG_KINETIS_EDMA_NTCD > 0 + /* That TCD list is linked through the DLAST SGA field. The first transfer + * to be performed is at the head of the list. Subsequent TCDs are added + * at the tail of the list. + */ + + struct kinetis_edmatcd_s *head; /* First TCD in the list */ + struct kinetis_edmatcd_s *tail; /* Last TCD in the list */ +#endif +}; + +/* This structure describes the state of the eDMA controller */ + +struct kinetis_edma_s +{ + /* These semaphores protect the DMA channel and descriptor tables */ + + sem_t chsem; /* Protects channel table */ +#if CONFIG_KINETIS_EDMA_NTCD > 0 + sem_t dsem; /* Supports wait for free descriptors */ +#endif + + /* This array describes each DMA channel */ + + struct kinetis_dmach_s dmach[KINETIS_EDMA_NCHANNELS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The state of the eDMA */ + +static struct kinetis_edma_s g_edma; + +#if CONFIG_KINETIS_EDMA_NTCD > 0 +/* This is a singly-linked list of free TCDs */ + +static sq_queue_t g_tcd_free; + +/* This is a pool of pre-allocated TCDs */ + +static struct kinetis_edmatcd_s g_tcd_pool[CONFIG_KINETIS_EDMA_NTCD] + __attribute__((aligned(EDMA_ALIGN))); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_takechsem() and kinetis_givechsem() + * + * Description: + * Used to get exclusive access to the DMA channel table for channel + * allocation. + * + ****************************************************************************/ + +static int kinetis_takechsem(void) +{ + return nxsem_wait_uninterruptible(&g_edma.chsem); +} + +static inline void kinetis_givechsem(void) +{ + nxsem_post(&g_edma.chsem); +} + +/**************************************************************************** + * Name: kinetis_takedsem() and kinetis_givedsem() + * + * Description: + * Used to wait for availability of descriptors in the descriptor table. + * + ****************************************************************************/ + +#if CONFIG_KINETIS_EDMA_NTCD > 0 +static void kinetis_takedsem(void) +{ + nxsem_wait_uninterruptible(&g_edma.dsem); +} + +static inline void kinetis_givedsem(void) +{ + nxsem_post(&g_edma.dsem); +} +#endif + +/**************************************************************************** + * Name: kinetis_tcd_alloc + * + * Description: + * Allocate an in-memory, TCD + * + ****************************************************************************/ + +#if CONFIG_KINETIS_EDMA_NTCD > 0 +static struct kinetis_edmatcd_s *kinetis_tcd_alloc(void) +{ + struct kinetis_edmatcd_s *tcd; + irqstate_t flags; + + /* Take the 'dsem'. When we hold the the 'dsem', then we know that one + * TCD is reserved for us in the free list. + * + * NOTE: We use a critical section here because we may block waiting for + * the 'dsem'. The critical section will be suspended while we are + * waiting. + */ + + flags = enter_critical_section(); + kinetis_takedsem(); + + /* Now there should be a TCD in the free list reserved just for us */ + + tcd = (struct kinetis_edmatcd_s *)sq_remfirst(&g_tcd_free); + DEBUGASSERT(tcd != NULL); + + leave_critical_section(flags); + return tcd; +} +#endif + +/**************************************************************************** + * Name: kinetis_tcd_free + * + * Description: + * Free an in-memory, TCD + * + ****************************************************************************/ + +#if CONFIG_KINETIS_EDMA_NTCD > 0 +static void kinetis_tcd_free(struct kinetis_edmatcd_s *tcd) +{ + irqstate_t flags; + + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + flags = spin_lock_irqsave(NULL); + sq_addlast((sq_entry_t *)tcd, &g_tcd_free); + kinetis_givedsem(); + spin_unlock_irqrestore(NULL, flags); +} +#endif + +/**************************************************************************** + * Name: kinetis_tcd_initialize() + * + * Description: + * Initialize the TCD free list from the pool of pre-allocated TCDs. + * + * Assumptions: + * Called early in the initialization sequence so no special protection is + * necessary. + * + ****************************************************************************/ + +#if CONFIG_KINETIS_EDMA_NTCD > 0 +static inline void kinetis_tcd_initialize(void) +{ + sq_entry_t *tcd; + int i; + + /* Add each pre-allocated TCD to the tail of the TCD free list */ + + sq_init(&g_tcd_free); + for (i = 0; i < CONFIG_KINETIS_EDMA_NTCD; i++) + { + tcd = (sq_entry_t *)&g_tcd_pool[i]; + sq_addlast(tcd, &g_tcd_free); + } +} +#endif + +/**************************************************************************** + * Name: kinetis_tcd_chanlink + * + * Description: + * This function configures either a minor link or a major link. The minor + * link means the channel link is triggered every time CITER decreases by 1 + * The major link means that the channel link is triggered when the CITER + * is exhausted. + * + * NOTE: Users should ensure that DONE flag is cleared before calling this + * interface, or the configuration is invalid. + * + * Input Parameters: + * tcd - Point to the TCD structure. + * type - Channel link type. + * chan - The linked channel number. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_EDMA_ELINK +static inline void kinetis_tcd_chanlink(uint8_t flags, + struct kinetis_dmach_s *linkch, + struct kinetis_edmatcd_s *tcd) +{ + uint16_t regval16; + + flags &= EDMA_CONFIG_LINKTYPE_MASK; + + if (linkch == NULL || flags == EDMA_CONFIG_LINKTYPE_LINKNONE) + { +#if 0 /* Already done */ + /* No link or no link channel provided */ + + /* Disable minor links */ + + tcd->citer &= ~EDMA_TCD_CITER_ELINK; + tcd->biter &= ~EDMA_TCD_BITER_ELINK; + + /* Disable major link */ + + tcd->csr &= ~EDMA_TCD_CSR_MAJORELINK; +#endif + } + else if (flags == EDMA_CONFIG_LINKTYPE_MINORLINK) /* Minor link config */ + { + /* Enable minor link */ + + tcd->citer |= EDMA_TCD_CITER_ELINK_ELINK; + tcd->biter |= EDMA_TCD_BITER_ELINK_ELINK; + + /* Set linked channel */ + + regval16 = tcd->citer; + regval16 &= ~EDMA_TCD_CITER_ELINK_LINKCH_MASK; + regval16 |= EDMA_TCD_CITER_ELINK_LINKCH(linkch->chan); + tcd->citer = regval16; + + regval16 = tcd->biter; + regval16 &= ~EDMA_TCD_BITER_ELINK_LINKCH_MASK; + regval16 |= EDMA_TCD_BITER_ELINK_LINKCH(linkch->chan); + tcd->biter = regval16; + } + else /* if (flags == EDMA_CONFIG_LINKTYPE_MAJORLINK) Major link config */ + { + /* Enable major link */ + + regval16 = tcd->csr; + regval16 |= EDMA_TCD_CSR_MAJORELINK; + tcd->csr = regval16; + + /* Set major linked channel */ + + regval16 &= ~EDMA_TCD_CSR_MAJORLINKCH_MASK; + regval16 |= EDMA_TCD_CSR_MAJORLINKCH(linkch->chan); + tcd->csr = regval16; + } +} +#endif + +/**************************************************************************** + * Name: kinetis_tcd_configure + * + * Description: + * Configure all TCD registers to the specified values. 'tcd' is an + * 'overlay' that may refer either to either the TCD register set or to an + * in-memory TCD structure. + * + ****************************************************************************/ + +static inline void kinetis_tcd_configure(struct kinetis_edmatcd_s *tcd, + const struct kinetis_edma_xfrconfig_s *config) +{ + tcd->flags = config->flags; + tcd->saddr = config->saddr; + tcd->soff = config->soff; + tcd->attr = EDMA_TCD_ATTR_SSIZE(config->ssize) | /* Transfer Attributes */ + EDMA_TCD_ATTR_DSIZE(config->dsize); + tcd->nbytes = config->nbytes; + tcd->slast = config->flags & EDMA_CONFIG_LOOPSRC ? -config->iter : 0; + tcd->daddr = config->daddr; + tcd->doff = config->doff; + tcd->citer = config->iter & EDMA_TCD_CITER_CITER_MASK; + tcd->biter = config->iter & EDMA_TCD_BITER_BITER_MASK; + tcd->csr = config->flags & EDMA_CONFIG_LOOPDEST ? + 0 : EDMA_TCD_CSR_DREQ; + tcd->csr |= config->flags & EDMA_CONFIG_INTHALF ? + EDMA_TCD_CSR_INTHALF : 0; + tcd->dlastsga = config->flags & EDMA_CONFIG_LOOPDEST ? -config->iter : 0; + + /* And special case flags */ + +#ifdef CONFIG_KINETIS_EDMA_ELINK + /* Configure major/minor link mapping */ + + kinetis_tcd_chanlink(config->flags, + (struct kinetis_dmach_s *)config->linkch, + tcd); +#endif +} + +/**************************************************************************** + * Name: kinetis_tcd_instantiate + * + * Description: + * Copy an in-memory TCD into eDMA channel TCD registers + * + ****************************************************************************/ + +#if CONFIG_KINETIS_EDMA_NTCD > 0 +static void kinetis_tcd_instantiate(struct kinetis_dmach_s *dmach, + const struct kinetis_edmatcd_s *tcd) +{ + uintptr_t base = KINETIS_EDMA_TCD_BASE(dmach->chan); + + /* Push tcd into hardware TCD register */ + + putreg32(tcd->saddr, base + KINETIS_EDMA_TCD_SADDR_OFFSET); + putreg16(tcd->soff, base + KINETIS_EDMA_TCD_SOFF_OFFSET); + putreg16(tcd->attr, base + KINETIS_EDMA_TCD_ATTR_OFFSET); + putreg32(tcd->nbytes, base + KINETIS_EDMA_TCD_NBYTES_ML_OFFSET); + putreg32(tcd->slast, base + KINETIS_EDMA_TCD_SLAST_OFFSET); + putreg32(tcd->daddr, base + KINETIS_EDMA_TCD_DADDR_OFFSET); + putreg16(tcd->doff, base + KINETIS_EDMA_TCD_DOFF_OFFSET); + putreg16(tcd->citer, base + KINETIS_EDMA_TCD_CITER_ELINK_OFFSET); + putreg32(tcd->dlastsga, base + KINETIS_EDMA_TCD_DLASTSGA_OFFSET); + + /* Clear DONE bit first, otherwise ESG cannot be set */ + + putreg16(0, base + KINETIS_EDMA_TCD_CSR_OFFSET); + putreg16(tcd->csr, base + KINETIS_EDMA_TCD_CSR_OFFSET); + + putreg16(tcd->biter, base + KINETIS_EDMA_TCD_BITER_ELINK_OFFSET); +} +#endif + +/**************************************************************************** + * Name: kinetis_dmaterminate + * + * Description: + * Terminate the DMA transfer and disable the DMA channel + * + ****************************************************************************/ + +static void kinetis_dmaterminate(struct kinetis_dmach_s *dmach, int result) +{ +#if CONFIG_KINETIS_EDMA_NTCD > 0 + struct kinetis_edmatcd_s *tcd; + struct kinetis_edmatcd_s *next; +#endif + uintptr_t regaddr; + uint8_t regval8; + uint8_t chan; + + /* Disable channel ERROR interrupts */ + + chan = dmach->chan; + regval8 = EDMA_CEEI(chan); + putreg8(regval8, KINETIS_EDMA_CEEI); + + /* Disable channel IRQ requests */ + + regval8 = EDMA_CERQ(chan); + putreg8(regval8, KINETIS_EDMA_CERQ); + + /* Check for an Rx (memory-to-peripheral/memory-to-memory) DMA transfer */ + + if (dmach->ttype == EDMA_MEM2MEM || dmach->ttype == EDMA_PERIPH2MEM) + { + /* Invalidate the cache to force reloads from memory. */ + +#warning Missing logic + } + + /* Perform the DMA complete callback */ + + if (dmach->callback) + { + dmach->callback((DMACH_HANDLE)dmach, dmach->arg, true, result); + } + + /* Clear CSR to disable channel. Because if the given channel started, + * transfer CSR will be not zero. Because if it is the last transfer, DREQ + * will be set. If not, ESG will be set. + */ + + regaddr = KINETIS_EDMA_TCD_CSR(chan); + putreg16(0, regaddr); + + /* Cancel next TCD transfer. */ + + regaddr = KINETIS_EDMA_TCD_DLASTSGA(chan); + putreg16(0, regaddr); + +#if CONFIG_KINETIS_EDMA_NTCD > 0 + /* Return all allocated TCDs to the free list */ + + for (tcd = dmach->head; tcd != NULL; tcd = next) + { + /* If channel looped to itself we are done + * if not continue to free tcds in chain + */ + + next = tcd->flags & EDMA_CONFIG_LOOPDEST ? + NULL : (struct kinetis_edmatcd_s *)tcd->dlastsga; + + kinetis_tcd_free(tcd); + } + + dmach->head = NULL; + dmach->tail = NULL; +#endif + + dmach->callback = NULL; + dmach->arg = NULL; + dmach->state = KINETIS_DMA_IDLE; +} + +/**************************************************************************** + * Name: kinetis_edma_interrupt + * + * Description: + * DMA interrupt handler. This function clears the channel major + * interrupt flag and calls the callback function if it is not NULL. + * + * NOTE: For the case using TCD queue, when the major iteration count is + * exhausted, additional operations are performed. These include the + * final address adjustments and reloading of the BITER field into the + * CITER. Assertion of an optional interrupt request also occurs at this + * time, as does a possible fetch of a new TCD from memory using the + * scatter/gather address pointer included in the descriptor (if scatter/ + * gather is enabled). + * + ****************************************************************************/ + +static int kinetis_edma_interrupt(int irq, void *context, FAR void *arg) +{ + struct kinetis_dmach_s *dmach; + uintptr_t regaddr; + uint8_t regval8; + uint16_t regval16; + uint32_t regval32; + uint8_t chan; + int result; + + /* 'arg' should the DMA channel instance. */ + + dmach = (struct kinetis_dmach_s *)arg; + DEBUGASSERT(dmach != NULL); + + chan = dmach->chan; + DEBUGASSERT(chan < KINETIS_EDMA_NCHANNELS && dmach == &g_edma.dmach[chan]); + + /* Check for an eDMA pending interrupt on this channel */ + + regval32 = getreg32(KINETIS_EDMA_INT); + if ((regval32 & EDMA_INT(chan)) != 0) + { + /* An interrupt is pending. This should only happen if the channel is + * active. + */ + + DEBUGASSERT(dmach->state == KINETIS_DMA_ACTIVE); + + /* Clear the pending eDMA channel interrupt */ + + regval8 = EDMA_CINT(chan); + putreg8(regval8, KINETIS_EDMA_CINT); + + /* Get the eDMA TCD Control and Status register value. */ + + regaddr = KINETIS_EDMA_TCD_CSR(chan); + regval16 = getreg16(regaddr); + + /* Check if transfer has finished. */ + + if ((regval16 & EDMA_TCD_CSR_DONE) != 0) + { + /* Clear the pending DONE interrupt status. */ + + regval8 = EDMA_CDNE(chan); + putreg8(regval8, KINETIS_EDMA_CDNE); + result = OK; + } + else + { +#if CONFIG_KINETIS_EDMA_NTCD > 0 + /* Perform the end-of-major-cycle DMA callback */ + + if (dmach->callback != NULL) + { + dmach->callback((DMACH_HANDLE)dmach, dmach->arg, + false, 0); + } + + return OK; +#else + /* Otherwise the interrupt was not expected! */ + + DEBUGPANIC(); + result = -EPIPE; +#endif + } + + /* Terminate the transfer when it is done. */ + + kinetis_dmaterminate(dmach, result); + } + + return OK; +} + +/**************************************************************************** + * Name: kinetis_error_interrupt + * + * Description: + * DMA error interrupt handler + * + ****************************************************************************/ + +static int kinetis_error_interrupt(int irq, void *context, FAR void *arg) +{ + uint32_t errstatus; + uint32_t errmask; + uint8_t regval8; + unsigned int chan; + + /* Get the set of pending error interrupts */ + + errstatus = getreg32(KINETIS_EDMA_ERR); + + /* Check for an error on each channel */ + + for (chan = 0; chan < KINETIS_EDMA_NCHANNELS && errstatus != 0; chan++) + { + /* Check for a pending error interrupt on each channel */ + + errmask = EDMA_ERR(chan); + if ((errstatus & errmask) != 0) + { + dmaerr("ERROR: DMACH%u ES=%08lx\n", + chan, (unsigned long)getreg32(KINETIS_EDMA_ES)); + + /* Clear the pending error interrupt status. */ + + regval8 = EDMA_CERR(chan); + putreg8(regval8, KINETIS_EDMA_CERR); + + /* Remove the bit from the sample ERR register so that perhaps we + * can exit this loop early. + */ + + errstatus &= ~errmask; + + /* Terminate the transfer on any error */ + + kinetis_dmaterminate(&g_edma.dmach[chan], -EIO); + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_dma_initialize + * + * Description: + * Initialize the DMA subsystem + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm_dma_initialize(void) +{ + uintptr_t regaddr; + uint32_t regval; + int i; + + dmainfo("Initialize eDMA\n"); + + /* Enable clocking for DMA */ + + regval = getreg32(KINETIS_SIM_SCGC7); + regval |= SIM_SCGC7_DMA; + putreg32(regval, KINETIS_SIM_SCGC7); + + /* Enable clocking for the DMA mux */ + + regval = getreg32(KINETIS_SIM_SCGC6); + regval |= SIM_SCGC6_DMAMUX0; + putreg32(regval, KINETIS_SIM_SCGC6); + + /* Configure the eDMA controller */ + + regval = getreg32(KINETIS_EDMA_CR); + regval &= ~(EDMA_CR_EDBG | EDMA_CR_ERCA | EDMA_CR_HOE | EDMA_CR_CLM | + EDMA_CR_EMLM); + +#ifdef CONFIG_KINETIS_EDMA_EDBG + regval |= EDMA_CR_EDBG; /* Enable Debug */ +#endif +#ifdef CONFIG_KINETIS_EDMA_ERCA + regval |= EDMA_CR_ERCA; /* Enable Round Robin Channel Arbitration */ +#endif +#ifdef CONFIG_KINETIS_EDMA_ERGA + regval |= EDMA_CR_ERGA; /* Enable Round Robin Group Arbitration */ +#endif +#ifdef CONFIG_KINETIS_EDMA_HOE + regval |= EDMA_CR_HOE; /* Halt On Error */ +#endif +#ifdef CONFIG_KINETIS_EDMA_CLM + regval |= EDMA_CR_CLM; /* Continuous Link Mode */ +#endif +#ifdef CONFIG_KINETIS_EDMA_EMLIM + regval |= EDMA_CR_EMLM; /* Enable Minor Loop Mapping */ +#endif + + putreg32(regval, KINETIS_EDMA_CR); + + /* Initialize data structures */ + + memset(&g_edma, 0, sizeof(struct kinetis_edma_s)); + for (i = 0; i < KINETIS_EDMA_NCHANNELS; i++) + { + g_edma.dmach[i].chan = i; + } + + /* Initialize semaphores */ + + nxsem_init(&g_edma.chsem, 0, 1); +#if CONFIG_KINETIS_EDMA_NTCD > 0 + nxsem_init(&g_edma.dsem, 0, CONFIG_KINETIS_EDMA_NTCD); + + /* The 'dsem' is used for signaling rather than mutual exclusion and, + * hence, should not have priority inheritance enabled. + */ + + nxsem_set_protocol(&g_edma.dsem, SEM_PRIO_NONE); + + /* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */ + + kinetis_tcd_initialize(); +#endif + + /* Attach DMA interrupt vectors. */ + + for (i = 0; i < KINETIS_EDMA_NCHANNELS; i++) + { + irq_attach(KINETIS_IRQ_DMACH0 + i, + kinetis_edma_interrupt, &g_edma.dmach[i]); + } + + /* Attach the DMA error interrupt vector */ + + irq_attach(KINETIS_IRQ_DMAERR, kinetis_error_interrupt, NULL); + + /* Disable and clear all error interrupts */ + + putreg32(0, KINETIS_EDMA_EEI); + putreg32(0xffffffff, KINETIS_EDMA_ERR); + + /* Disable all DMA channel interrupts at the eDMA controller */ + + for (i = 0; i < KINETIS_EDMA_NCHANNELS; i++) + { + /* Disable all DMA channels and DMA channel interrupts */ + + regaddr = KINETIS_EDMA_TCD_CSR(i); + putreg16(0, regaddr); + } + + /* Clear all pending DMA channel interrupts */ + + putreg32(0xffffffff, KINETIS_EDMA_INT); + + /* Enable the channel interrupts at the NVIC (still disabled at the eDMA + * controller). + */ + + for (i = 0; i < KINETIS_EDMA_NCHANNELS; i++) + { + up_enable_irq(KINETIS_IRQ_DMACH0 + i); + } + + /* Enable the DMA error interrupt */ + + up_enable_irq(KINETIS_IRQ_DMAERR); +} + +/**************************************************************************** + * Name: kinetis_dmach_alloc + * + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. + * + * Input Parameters: + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in hardware/kinetis_dmamux.h. + * Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. + * dchpri - DCHPRI channel priority configuration. See DCHPRI channel + * configuration register bit-field definitions in + * hardware/kinetis_edma.h. Meaningful settings include: + * + * EDMA_DCHPRI_CHPRI Channel Arbitration Priority + * DCHPRI_DPA Disable Preempt Ability + * DCHPRI_ECP Enable Channel Preemption + * + * The power-on default, 0x05, is a reasonable choice. + * + * Returned Value: + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. + * + ****************************************************************************/ + +DMACH_HANDLE kinetis_dmach_alloc(uint8_t dmamux, uint8_t dchpri) +{ + struct kinetis_dmach_s *dmach; + unsigned int chndx; + int ret; + + /* Search for an available DMA channel */ + + dmach = NULL; + ret = kinetis_takechsem(); + if (ret < 0) + { + return NULL; + } + + for (chndx = 0; chndx < KINETIS_EDMA_NCHANNELS; chndx++) + { + struct kinetis_dmach_s *candidate = &g_edma.dmach[chndx]; + uintptr_t regaddr; + uint8_t regval8; + + if (!candidate->inuse) + { + dmach = candidate; + dmach->inuse = true; + dmach->state = KINETIS_DMA_IDLE; + dmach->dmamux = dmamux; + + /* Clear any pending interrupts on the channel */ + + DEBUGASSERT(chndx == dmach->chan); + regaddr = KINETIS_EDMA_TCD_CSR(chndx); + putreg16(0, regaddr); + + /* Make sure that the channel is disabled. */ + + regval8 = EDMA_CERQ(chndx); + putreg8(regval8, KINETIS_EDMA_CERQ); + + /* Disable the associated DMAMUX for now */ + + putreg8(0, KINETIS_DMAMUX_CHCFG(chndx)); + break; + } + } + + kinetis_givechsem(); + + /* Show the result of the allocation */ + + if (dmach != NULL) + { + dmainfo("CH%d: returning dmach: %p\n", dmach->chan, dmach); + } + else + { + dmaerr("ERROR: Failed allocate eDMA channel\n"); + } + + return (DMACH_HANDLE)dmach; +} + +/**************************************************************************** + * Name: kinetis_dmach_free + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until kinetis_dmach_alloc() is called again to + * re-gain a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kinetis_dmach_free(DMACH_HANDLE handle) +{ + struct kinetis_dmach_s *dmach = (struct kinetis_dmach_s *)handle; + uint8_t regval8; + + dmainfo("dmach: %p\n", dmach); + DEBUGASSERT(dmach != NULL && dmach->inuse && + dmach->state != KINETIS_DMA_ACTIVE); + + /* Mark the channel no longer in use. Clearing the inuse flag is an atomic + * operation and so should be safe. + */ + + dmach->flags = 0; + dmach->inuse = false; /* No longer in use */ + dmach->state = KINETIS_DMA_IDLE; /* Better not be active! */ + + /* Make sure that the channel is disabled. */ + + regval8 = EDMA_CERQ(dmach->chan); + putreg8(regval8, KINETIS_EDMA_CERQ); + + /* Disable the associated DMAMUX */ + + putreg8(0, KINETIS_DMAMUX_CHCFG(dmach->chan)); +} + +/**************************************************************************** + * Name: kinetis_dmach_xfrsetup + * + * Description: + * This function adds the eDMA transfer to the DMA sequence. The request + * is setup according to the content of the transfer configuration + * structure. For "normal" DMA, kinetis_dmach_xfrsetup is called only once. + * Scatter/gather DMA is accomplished by calling this function repeatedly, + * once for each transfer in the sequence. Scatter/gather DMA processing + * is enabled automatically when the second transfer configuration is + * received. + * + * This function may be called multiple times to handle multiple, + * discontinuous transfers (scatter-gather) + * + * Input Parameters: + * handle - DMA channel handle created by kinetis_dmach_alloc() + * config - A DMA transfer configuration instance, populated by the + * The content of 'config' describes the transfer + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int kinetis_dmach_xfrsetup(DMACH_HANDLE *handle, + const struct kinetis_edma_xfrconfig_s *config) +{ + struct kinetis_dmach_s *dmach = (struct kinetis_dmach_s *)handle; +#if CONFIG_KINETIS_EDMA_NTCD > 0 + struct kinetis_edmatcd_s *tcd; + struct kinetis_edmatcd_s *prev; +#endif + uintptr_t regaddr; + uint16_t regval16; + + DEBUGASSERT(dmach != NULL); + dmainfo("dmach%u: %p config: %p\n", dmach->chan, dmach, config); + +#if CONFIG_KINETIS_EDMA_NTCD > 0 + /* Scatter/gather DMA is supported */ + + /* Allocate a TCD, waiting if necessary */ + + tcd = kinetis_tcd_alloc(); + + /* Configure current TCD block transfer. */ + + kinetis_tcd_configure(tcd, config); + + /* Enable the interrupt when the major iteration count completes for this + * TCD. For "normal" DMAs, this will correspond to the DMA DONE + * interrupt; for scatter gather DMAs, multiple interrupts will be + * generated with the final being the DONE interrupt. + */ + + tcd->csr |= EDMA_TCD_CSR_INTMAJOR; + + /* Is looped to it's self? */ + + if (config->flags & EDMA_CONFIG_LOOP_MASK) + { + /* Enable major link */ + + tcd->csr |= EDMA_TCD_CSR_MAJORELINK; + + /* Set major linked channel back to this one */ + + tcd->csr &= ~EDMA_TCD_CSR_MAJORLINKCH_MASK; + tcd->csr |= EDMA_TCD_CSR_MAJORLINKCH(dmach->chan); + } + + /* Is this the first descriptor in the list? */ + + if (dmach->head == NULL) + { + /* Yes.. add it to the list */ + + dmach->head = tcd; + dmach->tail = tcd; + dmach->ttype = config->ttype; + + /* And instantiate the first TCD in the DMA channel TCD registers. */ + + kinetis_tcd_instantiate(dmach, tcd); + } + else + { + /* Cannot mix transfer types (only because of cache-related operations. + * this restriction could be removed with some effort). + */ + + if (dmach->ttype != config->ttype || + dmach->flags & EDMA_CONFIG_LOOPDEST) + { + kinetis_tcd_free(tcd); + return -EINVAL; + } + + /* Chain from previous descriptor in the list. */ + + /* Enable scatter/gather feature in the previous TCD. */ + + prev = dmach->tail; + regval16 = prev->csr; + regval16 &= ~EDMA_TCD_CSR_DREQ; + regval16 |= EDMA_TCD_CSR_ESG; + prev->csr = regval16; + + prev->dlastsga = (uint32_t)tcd; + dmach->tail = tcd; + + /* Clean cache associated with the previous TCD memory */ + + up_clean_dcache((uintptr_t)prev, + (uintptr_t)prev + sizeof(struct kinetis_edmatcd_s)); + + /* Check if the TCD block in the DMA channel registers is the same as + * the previous previous TCD. This can happen if the previous TCD was + * the first TCD and has already be loaded into the TCD registers. + */ + + if (dmach->head == prev) + { + /* Enable scatter/gather also in the TCD registers. */ + + regaddr = KINETIS_EDMA_TCD_CSR(dmach->chan); + regval16 = getreg16(regaddr); + regval16 &= ~EDMA_TCD_CSR_DREQ; + regval16 |= EDMA_TCD_CSR_ESG; + putreg16(regval16, regaddr); + + regaddr = KINETIS_EDMA_TCD_DLASTSGA(dmach->chan); + putreg32((uint32_t)tcd, regaddr); + } + } + + /* Clean cache associated with the TCD memory */ + + up_clean_dcache((uintptr_t)tcd, + (uintptr_t)tcd + sizeof(struct kinetis_edmatcd_s)); +#else + /* Scatter/gather DMA is NOT supported */ + + /* Check if eDMA is busy: if the channel has started transfer, CSR will be + * non-zero. + */ + + regaddr = KINETIS_EDMA_TCD_CSR(dmach->chan); + regval16 = getreg16(regaddr); + + if (regval16 != 0 && (regval16 & EDMA_TCD_CSR_DONE) == 0) + { + return -EBUSY; + } + + /* Configure channel TCD registers to the values specified in config. */ + + kinetis_tcd_configure((struct kinetis_edmatcd_s *) + KINETIS_EDMA_TCD_BASE(dmach->chan), config); + + /* Enable the DONE interrupt when the major iteration count completes. */ + + regaddr = KINETIS_EDMA_TCD_CSR(dmach->chan); + modifyreg16(regaddr, 0, EDMA_TCD_CSR_INTMAJOR); +#endif + + /* Check for an Rx (memory-to-peripheral/memory-to-memory) DMA transfer */ + + if (dmach->ttype == EDMA_MEM2MEM || dmach->ttype == EDMA_PERIPH2MEM) + { + /* Invalidate caches associated with the destination DMA memory. + * REVISIT: nbytes is the number of bytes transferred on each + * minor loop. The following is only valid when the major loop + * is one. + */ + + up_invalidate_dcache((uintptr_t)config->daddr, + (uintptr_t)config->daddr + config->nbytes); + } + + /* Check for an Tx (peripheral-to-memory/memory-to-memory) DMA transfer */ + + if (dmach->ttype == EDMA_MEM2MEM || dmach->ttype == EDMA_MEM2PERIPH) + { + /* Clean caches associated with the source DMA memory. + * REVISIT: nbytes is the number of bytes transferred on each + * minor loop. The following is only valid when the major loop + * is one. + */ +#warning Missing logic + + up_clean_dcache((uintptr_t)config->saddr, + (uintptr_t)config->saddr + config->nbytes); + } + + /* Set the DMAMUX source and enable and optional trigger */ + + putreg8(dmach->dmamux, KINETIS_DMAMUX_CHCFG(dmach->chan)); + + dmach->state = KINETIS_DMA_CONFIGURED; + return OK; +} + +/**************************************************************************** + * Name: kinetis_dmach_start + * + * Description: + * Start the DMA transfer. This function should be called after the final + * call to kinetis_dmach_xfrsetup() in order to avoid race conditions. + * + * At the conclusion of each major DMA loop, a callback to the user + * provided function is made: |For "normal" DMAs, this will correspond to + * the DMA DONE interrupt; for scatter gather DMAs, multiple interrupts + * will be generated with the final being the DONE interrupt. + * + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. + * + * NOTE: On Rx DMAs (peripheral-to-memory or memory-to-memory), it is + * necessary to invalidate the destination memory. That is not done + * automatically by the DMA module. Invalidation of the destination memory + * regions is the responsibility of the caller. + * + * Input Parameters: + * handle - DMA channel handle created by kinetis_dmach_alloc() + * callback - The callback to be invoked when the DMA is completes or is + * aborted. + * arg - An argument that accompanies the callback + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int kinetis_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, + void *arg) +{ + struct kinetis_dmach_s *dmach = (struct kinetis_dmach_s *)handle; + irqstate_t flags; + uint8_t regval8; + uint8_t chan; + + DEBUGASSERT(dmach != NULL && dmach->state == KINETIS_DMA_CONFIGURED); + chan = dmach->chan; + dmainfo("dmach%u: %p callback: %p arg: %p\n", chan, dmach, callback, arg); + + /* Save the callback info. This will be invoked when the DMA completes */ + + flags = spin_lock_irqsave(NULL); + dmach->callback = callback; + dmach->arg = arg; + +#if CONFIG_KINETIS_EDMA_NTCD > 0 + /* Although it is not recommended, it might be possible to call this + * function multiple times while adding TCDs on the fly. + */ + + if (dmach->state != KINETIS_DMA_ACTIVE) +#endif + { + dmach->state = KINETIS_DMA_ACTIVE; + + /* Enable channel ERROR interrupts */ + + regval8 = EDMA_SEEI(chan); + putreg8(regval8, KINETIS_EDMA_SEEI); + + /* Enable the DMA request for this channel */ + + regval8 = EDMA_SERQ(chan); + putreg8(regval8, KINETIS_EDMA_SERQ); + } + + spin_unlock_irqrestore(NULL, flags); + return OK; +} + +/**************************************************************************** + * Name: kinetis_dmach_stop + * + * Description: + * Cancel the DMA. After kinetis_dmach_stop() is called, the DMA channel + * is reset, all TCDs are freed, and kinetis_dmarx/txsetup() must be called + * before kinetis_dmach_start() can be called again. + * + * Input Parameters: + * handle - DMA channel handle created by kinetis_dmach_alloc() + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void kinetis_dmach_stop(DMACH_HANDLE handle) +{ + struct kinetis_dmach_s *dmach = (struct kinetis_dmach_s *)handle; + irqstate_t flags; + + dmainfo("dmach: %p\n", dmach); + DEBUGASSERT(dmach != NULL); + + flags = spin_lock_irqsave(NULL); + kinetis_dmaterminate(dmach, -EINTR); + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: kinetis_dmach_getcount + * + * Description: + * This function checks the TCD (Task Control Descriptor) status for a + * specified eDMA channel and returns the the number of major loop counts + * that have not finished. + * + * NOTES: + * 1. This function can only be used to get unfinished major loop count of + * transfer without the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly + * from registers while the channel is running. + * + * Because to calculate the remaining bytes, the initial NBYTES configured + * in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not + * support getting it while a channel is active. In another words, the + * NBYTES value reading is always the actual (decrementing) NBYTES value + * the dma_engine is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved + * initial value of NBYTES (for example copied before enabling the channel) + * is needed. The formula to calculate it is shown below: + * + * RemainingBytes = RemainingMajorLoopCount * + * NBYTES(initially configured) + * + * Input Parameters: + * handle - DMA channel handle created by kinetis_dmach_alloc() + * + * Returned Value: + * Major loop count which has not been transferred yet for the current TCD. + * + ****************************************************************************/ + +unsigned int kinetis_dmach_getcount(DMACH_HANDLE *handle) +{ + struct kinetis_dmach_s *dmach = (struct kinetis_dmach_s *)handle; + unsigned int remaining = 0; + uintptr_t regaddr; + uint16_t regval16; + + DEBUGASSERT(dmach != NULL); + + /* If the DMA is done, then the remaining count is zero */ + + regaddr = KINETIS_EDMA_TCD_CSR(dmach->chan); + regval16 = getreg16(regaddr); + + if ((regval16 & EDMA_TCD_CSR_DONE) == 0) + { + /* Calculate the unfinished bytes */ + + regaddr = KINETIS_EDMA_TCD_CITER_ELINK(dmach->chan); + regval16 = getreg16(regaddr); + + if ((regval16 & EDMA_TCD_CITER_ELINK) != 0) + { + remaining = (regval16 & EDMA_TCD_CITER_ELINK_CITER_MASK) >> + EDMA_TCD_CITER_ELINK_CITER_SHIFT; + } + else + { + remaining = (regval16 & EDMA_TCD_CITER_CITER_MASK) >> + EDMA_TCD_CITER_CITER_SHIFT; + } + } + + return remaining; +} + +/**************************************************************************** + * Name: kinetis_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by kinetis_dmach_alloc() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void kinetis_dmasample(DMACH_HANDLE handle, struct kinetis_dmaregs_s *regs) +{ + struct kinetis_dmach_s *dmach = (struct kinetis_dmach_s *)handle; + uintptr_t regaddr; + unsigned int chan; + irqstate_t flags; + + DEBUGASSERT(dmach != NULL && regs != NULL); + chan = dmach->chan; + regs->chan = chan; + + /* eDMA Global Registers */ + + flags = spin_lock_irqsave(NULL); + + regs->cr = getreg32(KINETIS_EDMA_CR); /* Control */ + regs->es = getreg32(KINETIS_EDMA_ES); /* Error Status */ + regs->erq = getreg32(KINETIS_EDMA_ERQ); /* Enable Request */ + regs->req = getreg32(KINETIS_EDMA_INT); /* Interrupt Request */ + regs->err = getreg32(KINETIS_EDMA_ERR); /* Error */ + regs->hrs = getreg32(KINETIS_EDMA_HRS); /* Hardware Request Status */ + regs->ears = getreg32(KINETIS_EDMA_EARS); /* Enable Asynchronous Request in Stop */ + + /* eDMA Channel registers */ + + regaddr = KINETIS_EDMA_DCHPRI(chan); + regs->dchpri = getreg8(regaddr); /* Channel priority */ + + /* eDMA TCD */ + + base = KINETIS_EDMA_TCD_BASE(chan); + regs->saddr = getreg32(base + KINETIS_EDMA_TCD_SADDR_OFFSET); + regs->soff = getreg16(base + KINETIS_EDMA_TCD_SOFF_OFFSET); + regs->attr = getreg16(base + KINETIS_EDMA_TCD_ATTR_OFFSET); + regs->nbml = getreg32(base + KINETIS_EDMA_TCD_NBYTES_ML_OFFSET); + regs->slast = getreg32(base + KINETIS_EDMA_TCD_SLAST_OFFSET); + regs->daddr = getreg32(base + KINETIS_EDMA_TCD_DADDR_OFFSET); + regs->doff = getreg16(base + KINETIS_EDMA_TCD_DOFF_OFFSET); + regs->citer = getreg16(base + KINETIS_EDMA_TCD_CITER_ELINK_OFFSET); + regs->dlastsga = getreg32(base + KINETIS_EDMA_TCD_DLASTSGA_OFFSET); + regs->csr = getreg16(base + KINETIS_EDMA_TCD_CSR_OFFSET); + regs->biter = getreg16(base + KINETIS_EDMA_TCD_BITER_ELINK_OFFSET); + + /* DMAMUX registers */ + + regaddr = KINETIS_DMAMUX_CHCFG(chan); + regs->dmamux = getreg32(regaddr); /* Channel configuration */ + + spin_unlock_irqrestore(NULL, flags); +} +#endif /* CONFIG_DEBUG_DMA */ + +/**************************************************************************** + * Name: kinetis_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by kinetis_dmach_alloc() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void kinetis_dmadump(const struct kinetis_dmaregs_s *regs, const char *msg) +{ + unsigned int chan; + + DEBUGASSERT(regs != NULL && msg != NULL); + + chan = regs->chan; + DEBUGASSERT(chan < KINETIS_EDMA_NCHANNELS); + + dmainfo("%s\n", msg); + dmainfo(" eDMA Global Registers:\n"); + dmainfo(" CR: %08x\n", regs->cr); + dmainfo(" ES: %08x\n", regs->es); + dmainfo(" ERQ: %08x\n", regs->erq); + dmainfo(" INT: %08x\n", regs->req); + dmainfo(" ERR: %08x\n", regs->err); + dmainfo(" EARS: %08x\n", regs->hrs); + + /* eDMA Channel registers */ + + dmainfo(" eDMA Channel %u Registers:\n", chan); + dmainfo(" DCHPRI: %02x\n", regs->dchpri); + + /* eDMA TCD */ + + dmainfo(" eDMA Channel %u TCD Registers:\n", chan); + dmainfo(" SADDR: %08x\n", regs->saddr); + dmainfo(" SOFF: %04x\n", regs->soff); + dmainfo(" ATTR: %04x\n", regs->attr); + dmainfo(" NBML: %05x\n", regs->nbml); + dmainfo(" SLAST: %05x\n", regs->slast); + dmainfo(" DADDR: %05x\n", regs->daddr); + dmainfo(" DOFF: %04x\n", regs->doff); + dmainfo(" CITER: %04x\n", regs->citer); + dmainfo(" DLASTSGA: %08x\n", regs->dlastsga); + dmainfo(" CSR: %04x\n", regs->csr); + dmainfo(" BITER: %04x\n", regs->biter); + + /* DMAMUX registers */ + + dmainfo(" DMAMUX Channel %u Registers:\n", chan); + dmainfo(" DMAMUX: %08x\n", regs->dmamux); +} +#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_KINETIS_EDMA */ diff --git a/arch/arm/src/kinetis/kinetis_edma.h b/arch/arm/src/kinetis/kinetis_edma.h new file mode 100644 index 00000000000..72ba8383376 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_edma.h @@ -0,0 +1,455 @@ +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_edma.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * This file was leveraged from the NuttX i.MXRT port. + * Portions of that eDMA logic derived from NXP sample code which has + * a compatible BSD 3-clause license: + * + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_EDMAC_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_EDMAC_H + +/* General Usage: + * + * 1. Allocate a DMA channel + * + * DMACH_HANDLE handle; + * handle = edma_dmach_alloc(dmamux, dchpri); + * + * Where 'dmamux' is the channel DMAMUX configuration register setting and + * 'dchpri' is the channel DCHPRIO priority register setting. + * + * 2. Create the transfer configuration: + * + * struct kinetis_edma_xfrconfig_s config; + * config.saddr = ..; + * config.daddr = ..; + * etc. + * + * 3. Setup the transfer in hardware: + * + * int ret; + * ret = kinetis_dmach_xfrsetup(handle, &config); + * + * 4. If you are setting up a scatter gather DMA + * (with CONFIG_KINETIS_EDMA_NTCD > 0), then repeat steps 2 and 3 for + * each segment of the transfer. + * + * 5. Start the DMA: + * + * ret = kinetis_dmach_start(handle, my_callback_func, priv); + * + * Where my_callback_func() is called when the DMA completes or an error + * occurs. 'priv' represents some internal driver state that will be + * provided with the callback. + * + * 6. If you need to stop the DMA and free resources (such as if a timeout + * occurs), then: + * + * i mxrt_dmach_stop(handle); + * + * 7. The callback will be received when the DMA completes (or an error + * occurs). After that, you may free the DMA channel, or re-use it on + * subsequent DMAs. + * + * kinetis_dmach_free(handle); + * + * Almost non-invasive debug instrumentation is available. You may call + * kinetis_dmasample() to save the current state of the eDMA registers at + * any given point in time. At some later, postmortem analysis, you can + * dump the content of the buffered registers with kinetis_dmadump(). + * kinetis_dmasample() is also available for monitoring DMA progress. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include "hardware/kinetis_edma.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration flags. + * + * REVISIT: Many missing options that should be represented as flags: + * 1. Bandwidth + * 2. Source/Destination modulo + */ + +#define EDMA_CONFIG_LINKTYPE_SHIFT (0) /* Bits 0-1: Link type */ +#define EDMA_CONFIG_LINKTYPE_MASK (3 << EDMA_CONFIG_LINKTYPE_SHIFT) +# define EDMA_CONFIG_LINKTYPE_LINKNONE (0 << EDMA_CONFIG_LINKTYPE_SHIFT) /* No channel link */ +# define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */ +# define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */ + +#define EDMA_CONFIG_LOOP_SHIFT (2) /* Bits 2: Loop type */ +#define EDMA_CONFIG_LOOP_MASK (3 << EDMA_CONFIG_LOOP_SHIFT) +# define EDMA_CONFIG_LOOPNONE (0 << EDMA_CONFIG_LOOP_SHIFT) /* No looping */ +# define EDMA_CONFIG_LOOPSRC (1 << EDMA_CONFIG_LOOP_SHIFT) /* Source looping */ +# define EDMA_CONFIG_LOOPDEST (2 << EDMA_CONFIG_LOOP_SHIFT) /* Dest looping */ + +#define EDMA_CONFIG_INTHALF (1 << 3) /* Bits 3: Int on HALF */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef FAR void *DMACH_HANDLE; +typedef void (*edma_callback_t)(DMACH_HANDLE handle, + void *arg, bool done, int result); + +/* eDMA transfer type */ + +enum kinetis_edma_xfrtype_e +{ + EDMA_MEM2MEM = 0, /* Transfer from memory to memory */ + EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */ + EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */ +}; + +/* eDMA transfer sises */ + +enum kinetis_edma_sizes_e +{ + EDMA_8BIT = 0, /* Transfer data size 8 */ + EDMA_16BIT = 1, /* Transfer data size 16 */ + EDMA_32BIT = 2, /* Transfer data size 32 */ +}; + +/* This structure holds the source/destination transfer attribute + * configuration. + */ + +struct kinetis_edma_xfrconfig_s +{ + uint32_t saddr; /* Source data address. */ + uint32_t daddr; /* Destination data address. */ + int16_t soff; /* Sign-extended offset for current source address. */ + int16_t doff; /* Sign-extended offset for current destination address. */ + uint16_t iter; /* Major loop iteration count. */ + uint8_t flags; /* See EDMA_CONFIG_* definitions */ + uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */ + uint8_t dsize; /* Destination data transfer size. */ + uint8_t ttype; /* Transfer type (see enum kinetis_edma_xfrtype_e). */ +#ifdef CONFIG_KINETIS_EDMA_EMLIM + uint16_t nbytes; /* Bytes to transfer in a minor loop */ +#else + uint32_t nbytes; /* Bytes to transfer in a minor loop */ +#endif +#ifdef CONFIG_KINETIS_EDMA_ELINK + DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */ +#endif +}; + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA + * is selected + */ + +#ifdef CONFIG_DEBUG_DMA +struct kinetis_dmaregs_s +{ + uint8_t chan; /* Sampled channel */ + + /* eDMA Global Registers */ + + uint32_t cr; /* Control */ + uint32_t es; /* Error Status */ + uint32_t erq; /* Enable Request */ + uint32_t req; /* Interrupt Request */ + uint32_t err; /* Error */ + uint32_t hrs; /* Hardware Request Status */ + uint32_t ears; /* Enable Asynchronous Request in Stop */ + + /* eDMA Channel registers */ + + uint8_t dchpri; /* Channel priority */ + + /* eDMA TCD */ + + uint32_t saddr; /* TCD Source Address */ + uint16_t soff; /* TCD Signed Source Address Offset */ + uint16_t attr; /* TCD Transfer Attributes */ + uint32_t nbml; /* TCD Signed Minor Loop Offset / Byte Count */ + uint32_t slast; /* TCD Last Source Address Adjustment */ + uint32_t daddr; /* TCD Destination Address */ + uint16_t doff; /* TCD Signed Destination Address Offset */ + uint16_t citer; /* TCD Current Minor Loop Link, Major Loop Count */ + uint32_t dlastsga; /* TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t csr; /* TCD Control and Status */ + uint16_t biter; /* TCD Beginning Minor Loop Link, Major Loop Count */ + + /* DMAMUX registers */ + + uint32_t dmamux; /* Channel configuration */ +}; +#endif /* CONFIG_DEBUG_DMA */ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_dmach_alloc + * + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. + * + * Input Parameters: + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in hardware/kinetis_dmamux.h. + * Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. + * dchpri - DCHPRI channel priority configuration. See DCHPRI channel + * configuration register bit-field definitions in + * hardware/kinetis_edma.h. Meaningful settings include: + * + * EDMA_DCHPRI_CHPRI Channel Arbitration Priority + * DCHPRI_DPA Disable Preempt Ability + * DCHPRI_ECP Enable Channel Preemption + * + * The power-on default, 0x05, is a reasonable choice. + * + * Returned Value: + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. + * + ****************************************************************************/ + +DMACH_HANDLE kinetis_dmach_alloc(uint8_t dmamux, uint8_t dchpri); + +/**************************************************************************** + * Name: kinetis_dmach_free + * + * Description: + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again + * until kinetis_dmach_alloc() is called again to re-gain a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kinetis_dmach_free(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: kinetis_dmach_xfrsetup + * + * Description: + * This function adds the eDMA transfer to the DMA sequence. The request + * is setup according to the content of the transfer configuration + * structure. For "normal" DMA, kinetis_dmach_xfrsetup is called only + * once. + * Scatter/gather DMA is accomplished by calling this function repeatedly, + * once for each transfer in the sequence. Scatter/gather DMA processing + * is enabled automatically when the second transfer configuration is + * received. + * + * This function may be called multiple times to handle multiple, + * discontinuous transfers (scatter-gather) + * + * Input Parameters: + * handle - DMA channel handle created by kinetis_dmach_alloc() + * config - A DMA transfer configuration instance, populated by the + * The content of 'config' describes the transfer + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int kinetis_dmach_xfrsetup(DMACH_HANDLE *handle, + const struct kinetis_edma_xfrconfig_s *config); + +/**************************************************************************** + * Name: kinetis_dmach_start + * + * Description: + * Start the DMA transfer by enabling the channel DMA request. + * This function should be called after the final call to + * kinetis_dmasetup() in order to avoid race conditions. + * + * At the conclusion of each major DMA loop, a callback to the + * user-provided function is made: |For "normal" DMAs, this will + * correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple + * interrupts will be generated with the final being the DONE interrupt. + * + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. + * + * NOTE: + * On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary + * to invalidate the destination memory. That is not done automatically + * by the DMA module. Invalidation of the destination memory regions is + * the responsibility of the caller. + * + * Input Parameters: + * handle - DMA channel handle created by kinetis_dmach_alloc() + * callback - The callback to be invoked when the DMA is completes or is + * aborted. + * arg - An argument that accompanies the callback + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int kinetis_dmach_start(DMACH_HANDLE handle, + edma_callback_t callback, void *arg); + +/**************************************************************************** + * Name: kinetis_dmach_stop + * + * Description: + * Cancel the DMA. After kinetis_dmach_stop() is called, the DMA channel + * is reset, all TCDs are freed, and kinetis_dmarx/txsetup() must be called + * before kinetis_dmach_start() can be called again + * + * Input Parameters: + * handle - DMA channel handle created by kinetis_dmach_alloc() + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void kinetis_dmach_stop(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: kinetis_dmach_getcount + * + * Description: + * This function checks the TCD (Task Control Descriptor) status for a + * specified eDMA channel and returns the the number of major loop counts + * that have not finished. + * + * NOTES: + * 1. This function can only be used to get unfinished major loop count of + * transfer without the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly + * from registers while the channel is running. + * + * Because to calculate the remaining bytes, the initial NBYTES configured + * in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not + * support getting it while a channel is active. In another words, the + * NBYTES value reading is always the actual (decrementing) NBYTES value + * the dma_engine is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved + * initial value of NBYTES (for example copied before enabling the channel) + * is needed. The formula to calculate it is shown below: + * + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + * + * Input Parameters: + * handle - DMA channel handle created by kinetis_dmach_alloc() + * + * Returned Value: + * Major loop count which has not been transferred yet for the current TCD. + * + ****************************************************************************/ + +unsigned int kinetis_dmach_getcount(DMACH_HANDLE *handle); + +/**************************************************************************** + * Name: kinetis_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void kinetis_dmasample(DMACH_HANDLE handle, struct kinetis_dmaregs_s *regs); +#else +# define kinetis_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: kinetis_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void kinetis_dmadump(const struct kinetis_dmaregs_s *regs, const char *msg); +#else +# define kinetis_dmadump(handle,regs,msg) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_EDMAC_H */ diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index f34aa98a7bf..2dd7fdd7517 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/kinetis/kinetis_flexcan.c b/arch/arm/src/kinetis/kinetis_flexcan.c index e22cf08bf12..9aacc05a87c 100644 --- a/arch/arm/src/kinetis/kinetis_flexcan.c +++ b/arch/arm/src/kinetis/kinetis_flexcan.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -634,7 +635,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv) if (mbi == TXMBCOUNT) { - nwarn("No TX MB available mbi %i\n", mbi); + nwarn("No TX MB available mbi %" PRIu32 "\n", mbi); NETDEV_TXERRORS(&priv->dev); return 0; /* No transmission for you! */ } @@ -1004,10 +1005,13 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv) NETDEV_TXDONE(&priv->dev); #ifdef TX_TIMEOUT_WQ /* We are here because a transmission completed, so the - * corresponding watchdog can be canceled. + * corresponding watchdog can be canceled + * mailbox be set to inactive */ wd_cancel(&priv->txtimeout[mbi]); + struct mb_s *mb = &priv->tx[mbi]; + mb->cs.code = CAN_TXMB_INACTIVE; #endif } @@ -1127,7 +1131,9 @@ static int kinetis_flexcan_interrupt(int irq, FAR void *context, static void kinetis_txtimeout_work(FAR void *arg) { FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; + uint32_t flags; uint32_t mbi; + uint32_t mb_bit; struct timespec ts; struct timeval *now = (struct timeval *)&ts; @@ -1138,6 +1144,8 @@ static void kinetis_txtimeout_work(FAR void *arg) * transmit function transmitted a new frame */ + flags = getreg32(priv->base + KINETIS_CAN_IFLAG1_OFFSET); + for (mbi = 0; mbi < TXMBCOUNT; mbi++) { if (priv->txmb[mbi].deadline.tv_sec != 0 @@ -1145,6 +1153,14 @@ static void kinetis_txtimeout_work(FAR void *arg) || now->tv_usec > priv->txmb[mbi].deadline.tv_usec)) { NETDEV_TXTIMEOUTS(&priv->dev); + + mb_bit = 1 << (RXMBCOUNT + mbi); + + if (flags & mb_bit) + { + putreg32(mb_bit, priv->base + KINETIS_CAN_IFLAG1_OFFSET); + } + struct mb_s *mb = &priv->tx[mbi]; mb->cs.code = CAN_TXMB_ABORT; priv->txmb[mbi].pending = TX_ABORT; @@ -1654,7 +1670,7 @@ static int kinetis_initialize(struct kinetis_driver_s *priv) for (i = 0; i < RXMBCOUNT; i++) { - ninfo("Set MB%i to receive %p\n", i, &priv->rx[i]); + ninfo("Set MB%" PRIu32 " to receive %p\n", i, &priv->rx[i]); priv->rx[i].cs.edl = 0x1; priv->rx[i].cs.brs = 0x1; priv->rx[i].cs.esi = 0x0; @@ -1718,8 +1734,8 @@ static void kinetis_reset(struct kinetis_driver_s *priv) for (i = 0; i < TOTALMBCOUNT; i++) { - ninfo("MB %i %p\n", i, &priv->rx[i]); - ninfo("MB %i %p\n", i, &priv->rx[i].id.w); + ninfo("MB %" PRIu32 " %p\n", i, &priv->rx[i]); + ninfo("MB %" PRIu32 " %p\n", i, &priv->rx[i].id.w); priv->rx[i].cs.cs = 0x0; priv->rx[i].id.w = 0x0; priv->rx[i].data[0].w00 = 0x0; diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c index 8a8c611dbfa..41193721a0f 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.c +++ b/arch/arm/src/kinetis/kinetis_i2c.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_i2c.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Authors: Matias v01d - * David Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -45,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/kinetis/kinetis_i2c.h b/arch/arm/src/kinetis/kinetis_i2c.h index 10fe489145f..b6c4f1587f3 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.h +++ b/arch/arm/src/kinetis/kinetis_i2c.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_i2c.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Matias v01d + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index 2f840a21f67..c0104aa1056 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c index 80084e45947..658d422142e 100644 --- a/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/arch/arm/src/kinetis/kinetis_lowputc.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c index 5cf3c899d47..42e4cc3e003 100644 --- a/arch/arm/src/kinetis/kinetis_lpserial.c +++ b/arch/arm/src/kinetis/kinetis_lpserial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/kinetis/kinetis_pindma.c b/arch/arm/src/kinetis/kinetis_pindma.c index e308ef8818a..8e0db93c9f9 100644 --- a/arch/arm/src/kinetis/kinetis_pindma.c +++ b/arch/arm/src/kinetis/kinetis_pindma.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/kinetis/kinetis_pindump.c b/arch/arm/src/kinetis/kinetis_pindump.c index 4c245dac289..400b05f8074 100644 --- a/arch/arm/src/kinetis/kinetis_pindump.c +++ b/arch/arm/src/kinetis/kinetis_pindump.c @@ -25,6 +25,7 @@ #include #include +#include #include #include @@ -78,7 +79,7 @@ static const char g_portchar[KINETIS_NPORTS] = * * Description: * Dump all GPIO registers associated with the provided pin description - * along with a descriptive messasge. + * along with a descriptive message. * ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c index 052e1822de0..100ced2f7e1 100644 --- a/arch/arm/src/kinetis/kinetis_pwm.c +++ b/arch/arm/src/kinetis/kinetis_pwm.c @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_pwm.c * - * Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Alan Carvalho de Assis - * Ken Fazzone - * David Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_pwm.h b/arch/arm/src/kinetis/kinetis_pwm.h index 67c7cb1bfc6..d19885baf55 100644 --- a/arch/arm/src/kinetis/kinetis_pwm.h +++ b/arch/arm/src/kinetis/kinetis_pwm.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_pwm.h * - * Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Alan Carvalho de Assis - * Ken Fazzone - * David Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_rtc.c b/arch/arm/src/kinetis/kinetis_rtc.c index 1ebbc4e9673..0d2578c234e 100644 --- a/arch/arm/src/kinetis/kinetis_rtc.c +++ b/arch/arm/src/kinetis/kinetis_rtc.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_rtc.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Matias v01d + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -47,6 +32,8 @@ #include #include #include +#include +#include #include #include "arm_arch.h" diff --git a/arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c b/arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c index 1111f091efd..2c9702f94fa 100644 --- a/arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c +++ b/arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index d81b40e2a75..3047b1fb6ea 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_serial.c * - * Copyright (C) 2011-2012, 2017-2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Jan Okle + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -46,6 +29,7 @@ #include #include #include +#include #include #include @@ -69,7 +53,7 @@ #include "hardware/kinetis_uart.h" #include "hardware/kinetis_pinmux.h" #include "kinetis.h" -#include "kinetis_dma.h" +#include "kinetis_edma.h" #include "kinetis_uart.h" /**************************************************************************** @@ -286,9 +270,6 @@ # define RXDMA_BUFFER_SIZE ((CONFIG_KINETIS_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) -# define SERIAL_DMA_CONTROL_WORD \ - (DMA_TCD_CSR_MAJORELINK | \ - DMA_TCD_CSR_INTHALF) #endif /* SERIAL_HAVE_DMA */ /**************************************************************************** @@ -322,7 +303,7 @@ struct up_dev_s #endif #ifdef SERIAL_HAVE_DMA const uint8_t rxdma_reqsrc; - DMA_HANDLE rxdma; /* currently-open receive DMA stream */ + DMACH_HANDLE rxdma; /* currently-open receive DMA stream */ uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ char *const rxfifo; /* Receive DMA buffer */ #endif @@ -363,7 +344,8 @@ static void up_dma_shutdown(struct uart_dev_s *dev); static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status); static bool up_dma_rxavailable(struct uart_dev_s *dev); static uint8_t get_and_clear_uart_status(struct up_dev_s *priv); -static void up_dma_rxcallback(DMA_HANDLE handle, void *arg, int result); +static void up_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result); #endif /**************************************************************************** @@ -944,7 +926,7 @@ static int up_dma_setup(struct uart_dev_s *dev) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int result; uint8_t regval; - DMA_HANDLE rxdma = NULL; + DMACH_HANDLE rxdma = NULL; /* Do the basic UART setup first, unless we are the console */ @@ -959,10 +941,7 @@ static int up_dma_setup(struct uart_dev_s *dev) /* Acquire the DMA channel. */ - rxdma = kinetis_dmachannel(priv->rxdma_reqsrc, - priv->uartbase + KINETIS_UART_D_OFFSET, - KINETIS_DMA_DATA_SZ_8BIT, - KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY); + rxdma = kinetis_dmach_alloc(priv->rxdma_reqsrc | DMAMUX_CHCFG_ENBL, 0); if (rxdma == NULL) { return -EBUSY; @@ -970,8 +949,21 @@ static int up_dma_setup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ - kinetis_dmasetup(rxdma, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, - SERIAL_DMA_CONTROL_WORD); + struct kinetis_edma_xfrconfig_s config; + config.saddr = priv->uartbase + KINETIS_UART_D_OFFSET; + config.daddr = (uint32_t) priv->rxfifo; + config.soff = 0; + config.doff = 1; + config.iter = RXDMA_BUFFER_SIZE; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE | EDMA_CONFIG_LOOPDEST; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.ttype = EDMA_PERIPH2MEM; + config.nbytes = 1; +#ifdef CONFIG_KINETIS_EDMA_ELINK + config.linkch = NULL; +#endif + kinetis_dmach_xfrsetup(rxdma, &config); /* Reset our DMA shadow pointer to match the address just programmed * above. @@ -990,7 +982,7 @@ static int up_dma_setup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - kinetis_dmastart(rxdma, up_dma_rxcallback, (void *)dev); + kinetis_dmach_start(rxdma, up_dma_rxcallback, (void *)dev); priv->rxdma = rxdma; return OK; } @@ -1031,8 +1023,7 @@ static void up_shutdown(struct uart_dev_s *dev) static void up_dma_shutdown(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - DMA_HANDLE rxdma = priv->rxdma; - priv->rxdma = NULL; + DMACH_HANDLE rxdma = priv->rxdma; /* Perform the normal UART shutdown */ @@ -1040,11 +1031,13 @@ static void up_dma_shutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - kinetis_dmastop(rxdma); + kinetis_dmach_stop(rxdma); /* Release the DMA channel */ - kinetis_dmafree(rxdma); + kinetis_dmach_free(rxdma); + + priv->rxdma = NULL; } #endif @@ -1259,6 +1252,22 @@ static int up_interrupts(int irq, void *context, FAR void *arg) uart_xmitchars(dev); handled = true; } + +#if defined(SERIAL_HAVE_DMA) && !defined(CONFIG_KINETIS_UARTFIFOS) + /* Check if the receiver has detected IDLE. If so + * then flush any partail data in the SW rx fifo. + */ + + if ((s1 & UART_S1_IDLE) != 0) + { + up_serialin(priv, KINETIS_UART_D_OFFSET); + up_dma_rxcallback(priv->rxdma, dev , false, 0); + + /* Exit ASAP */ + + handled = false; + } +#endif } return OK; @@ -1680,6 +1689,9 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS priv->ie |= UART_C2_RIE; +#if defined(SERIAL_HAVE_DMA) && !defined(CONFIG_KINETIS_UARTFIFOS) + priv->ie |= UART_C2_RIE | UART_C2_ILIE; +#endif up_setuartint(priv); #endif } @@ -1837,7 +1849,7 @@ static int up_dma_nextrx(struct up_dev_s *priv) { size_t dmaresidual; - dmaresidual = kinetis_dmaresidual(priv->rxdma); + dmaresidual = kinetis_dmach_getcount(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual) % RXDMA_BUFFER_SIZE; } @@ -1958,7 +1970,8 @@ static bool up_txempty(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static void up_dma_rxcallback(DMA_HANDLE handle, void *arg, int result) +static void up_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) { struct uart_dev_s *dev = (struct uart_dev_s *)arg; @@ -2074,70 +2087,6 @@ unsigned int kinetis_uart_serialinit(unsigned int first) return first; } -/**************************************************************************** - * Name: kinetis_serial_dma_poll - * - * Description: - * Checks receive DMA buffers for received bytes that have not accumulated - * to the point where the DMA half/full interrupt has triggered. - * - * This function should be called from a timer or other periodic context. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_DMA -void kinetis_serial_dma_poll(void) -{ - irqstate_t flags; - - flags = enter_critical_section(); - -#ifdef CONFIG_KINETIS_UART0_RXDMA - if (g_uart0priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart0priv.rxdma, (void *)&g_uart0port, 0); - } -#endif - -#ifdef CONFIG_KINETIS_UART1_RXDMA - if (g_uart1priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart1priv.rxdma, (void *)&g_uart1port, 0); - } -#endif - -#ifdef CONFIG_KINETIS_UART2_RXDMA - if (g_uart2priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart2priv.rxdma, (void *)&g_uart2port, 0); - } -#endif - -#ifdef CONFIG_KINETIS_UART3_RXDMA - if (g_uart3priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart3priv.rxdma, (void *)&g_uart3port, 0); - } -#endif - -#ifdef CONFIG_KINETIS_UART4_RXDMA - if (g_uart4priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart4priv.rxdma, (void *)&g_uart4port, 0); - } -#endif - -#ifdef CONFIG_KINETIS_UART5_RXDMA - if (g_uart5priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart5priv.rxdma, (void *)&g_uart5port, 0); - } -#endif - - leave_critical_section(flags); -} -#endif - /**************************************************************************** * Name: up_putc * diff --git a/arch/arm/src/kinetis/kinetis_spi.c b/arch/arm/src/kinetis/kinetis_spi.c index 7dcc52a2530..094ecdf491d 100644 --- a/arch/arm/src/kinetis/kinetis_spi.c +++ b/arch/arm/src/kinetis/kinetis_spi.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include @@ -66,7 +67,9 @@ #include "arm_arch.h" #include "kinetis.h" +#include "kinetis_edma.h" #include "kinetis_spi.h" +#include "hardware/kinetis_dmamux.h" #include "hardware/kinetis_memorymap.h" #include "hardware/kinetis_sim.h" #include "hardware/kinetis_dspi.h" @@ -82,20 +85,34 @@ #define KINETIS_SPI_CLK_MAX (BOARD_BUS_FREQ / 2) #define KINETIS_SPI_CLK_INIT 400000 +#define SPI_SR_CLEAR (SPI_SR_TCF | SPI_SR_EOQF | SPI_SR_TFUF | \ + SPI_SR_TFFF | SPI_SR_RFOF | SPI_SR_RFDF | \ + SPI_SR_TXRXS) + /**************************************************************************** * Private Types ****************************************************************************/ struct kinetis_spidev_s { - struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ - uint32_t spibase; /* Base address of SPI registers */ - sem_t exclsem; /* Held while chip is selected for mutual exclusion */ - uint32_t frequency; /* Requested clock frequency */ - uint32_t actual; /* Actual clock frequency */ - uint8_t nbits; /* Width of word in bits (8 to 16) */ - uint8_t mode; /* Mode 0,1,2,3 */ - uint8_t ctarsel; /* Which CTAR */ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ + uint32_t spibase; /* Base address of SPI registers */ + sem_t exclsem; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t nbits; /* Width of word in bits (8 to 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ + uint8_t ctarsel; /* Which CTAR */ +#ifdef CONFIG_KINETIS_SPI_DMA + volatile uint32_t rxresult; /* Result of the RX DMA */ + volatile uint32_t txresult; /* Result of the TX DMA */ + const uint8_t rxch; /* The RX DMA channel number */ + const uint8_t txch; /* The TX DMA channel number */ + DMACH_HANDLE rxdma; /* DMA channel handle for RX transfers */ + DMACH_HANDLE txdma; /* DMA channel handle for TX transfers */ + sem_t rxsem; /* Wait for RX DMA to complete */ + sem_t txsem; /* Wait for TX DMA to complete */ +#endif }; /**************************************************************************** @@ -131,6 +148,21 @@ static inline void spi_wait_status(FAR struct kinetis_spidev_s *priv, static uint16_t spi_send_data(FAR struct kinetis_spidev_s *priv, uint16_t wd, bool last); +/* DMA support */ + +#ifdef CONFIG_KINETIS_SPI_DMA +static int spi_dmarxwait(FAR struct kinetis_spidev_s *priv); +static int spi_dmatxwait(FAR struct kinetis_spidev_s *priv); +static inline void spi_dmarxwakeup(FAR struct kinetis_spidev_s *priv); +static inline void spi_dmatxwakeup(FAR struct kinetis_spidev_s *priv); +static void spi_dmarxcallback(DMACH_HANDLE handle, void *arg, + bool done, int result); +static void spi_dmatxcallback(DMACH_HANDLE handle, void *arg, + bool done, int result); +static inline void spi_dmarxstart(FAR struct kinetis_spidev_s *priv); +static inline void spi_dmatxstart(FAR struct kinetis_spidev_s *priv); +#endif + /* SPI methods */ static int spi_lock(FAR struct spi_dev_s *dev, bool lock); @@ -196,6 +228,15 @@ static struct kinetis_spidev_s g_spi0dev = }, .spibase = KINETIS_SPI0_BASE, .ctarsel = KINETIS_SPI_CTAR0_OFFSET, +#ifdef CONFIG_KINETIS_SPI_DMA +# ifdef CONFIG_KINETIS_SPI0_DMA + .rxch = KINETIS_DMA_REQUEST_SRC_SPI0_RX, + .txch = KINETIS_DMA_REQUEST_SRC_SPI0_TX, +# else + .rxch = 0, + .txch = 0, +# endif +#endif }; #endif @@ -236,6 +277,15 @@ static struct kinetis_spidev_s g_spi1dev = }, .spibase = KINETIS_SPI1_BASE, .ctarsel = KINETIS_SPI_CTAR0_OFFSET, +#ifdef CONFIG_KINETIS_SPI_DMA +# ifdef CONFIG_KINETIS_SPI1_DMA + .rxch = KINETIS_DMA_REQUEST_SRC_SPI1_RX, + .txch = KINETIS_DMA_REQUEST_SRC_SPI1_TX, +# else + .rxch = 0, + .txch = 0, +# endif +#endif }; #endif @@ -276,6 +326,15 @@ static struct kinetis_spidev_s g_spi2dev = }, .spibase = KINETIS_SPI2_BASE, .ctarsel = KINETIS_SPI_CTAR0_OFFSET, +#ifdef CONFIG_KINETIS_SPI_DMA +# ifdef CONFIG_KINETIS_SPI2_DMA + .rxch = KINETIS_DMA_REQUEST_SRC_FTM3_CH6__SPI2_RX, + .txch = KINETIS_DMA_REQUEST_SRC_FTM3_CH7__SPI2_TX, +# else + .rxch = 0, + .txch = 0, +# endif +#endif }; #endif @@ -283,6 +342,32 @@ static struct kinetis_spidev_s g_spi2dev = * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: spi_modifyreg + * + * Description: + * Atomic modification of the 32-bit contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * clearbits - bits to clear + * clearbits - bits to set + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static inline void spi_modifyreg(FAR struct kinetis_spidev_s *priv, + uint8_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(priv->spibase + offset, clearbits, setbits); +} +#endif + /**************************************************************************** * Name: spi_getreg * @@ -945,7 +1030,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) } /**************************************************************************** - * Name: spi_exchange + * Name: spi_exchange (no DMA). aka spi_exchange_nodma * * Description: * Exchange a block of data on SPI without using DMA @@ -954,7 +1039,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits > 8, the data is packed into @@ -965,8 +1050,15 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_SPI_DMATHRESHOLD) +# if !defined(CONFIG_KINETIS_SPI_DMA) static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords) +# else +static void spi_exchange_nodma(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +# endif { FAR struct kinetis_spidev_s *priv = (FAR struct kinetis_spidev_s *)dev; uint8_t *brxptr = (uint8_t *)rxbuffer; @@ -1038,7 +1130,161 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, } } } +#endif /* !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_SPI_DMATHRESHOLD) */ +/**************************************************************************** + * Name: spi_exchange (with DMA capability) + * + * Description: + * Exchange a block of data on SPI using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits > 8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +{ + int ret; + size_t adjust; + ssize_t nbytes; + static uint8_t rxdummy[4] __attribute__((aligned(4))); + static const uint16_t txdummy = 0xffff; + FAR struct kinetis_spidev_s *priv = (FAR struct kinetis_spidev_s *)dev; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv && priv->spibase); + spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + /* Convert the number of word to a number of bytes */ + + nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; + + /* Invalid DMA channels fall back to non-DMA method. */ + + if (priv->rxdma == NULL || priv->txdma == NULL +#ifdef CONFIG_KINETIS_SPI_DMATHRESHOLD + /* If this is a small SPI transfer, then let spi_exchange_nodma() + * do the work. + */ + + || nbytes <= CONFIG_KINETIS_SPI_DMATHRESHOLD +#endif + ) + { + spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } + + /* Halt the SPI */ + + spi_run(priv, false); + + /* Flush FIFOs */ + + spi_modifyreg(priv, KINETIS_SPI_MCR_OFFSET, + SPI_MCR_CLR_RXF | SPI_MCR_CLR_TXF, + SPI_MCR_CLR_RXF | SPI_MCR_CLR_TXF); + + /* Clear all status bits */ + + spi_write_status(priv, SPI_SR_CLEAR); + + /* disable DMA */ + + spi_modifyreg(priv, KINETIS_SPI_RSER_OFFSET, + SPI_RSER_RFDF_RE | SPI_RSER_TFFF_RE | + SPI_RSER_RFDF_DIRS | SPI_RSER_TFFF_DIRS, + 0); + + /* Set up the DMA */ + + adjust = (priv->nbits > 8) ? 2 : 1; + + struct kinetis_edma_xfrconfig_s config; + + config.saddr = priv->spibase + KINETIS_SPI_POPR_OFFSET; + config.daddr = (uint32_t) (rxbuffer ? rxbuffer : rxdummy); + config.soff = 0; + config.doff = rxbuffer ? adjust : 0; + config.iter = nbytes; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.dsize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.ttype = EDMA_PERIPH2MEM; + config.nbytes = adjust; +#ifdef CONFIG_KINETIS_EDMA_ELINK + config.linkch = NULL; +#endif + kinetis_dmach_xfrsetup(priv->rxdma, &config); + + config.saddr = (uint32_t) (txbuffer ? txbuffer : &txdummy); + config.daddr = priv->spibase + KINETIS_SPI_PUSHR_OFFSET; + config.soff = txbuffer ? adjust : 0; + config.doff = 0; + config.iter = nbytes; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.dsize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.ttype = EDMA_MEM2PERIPH; + config.nbytes = adjust; +#ifdef CONFIG_KINETIS_EDMA_ELINK + config.linkch = NULL; +#endif + kinetis_dmach_xfrsetup(priv->txdma, &config); + + spi_modifyreg(priv, KINETIS_SPI_RSER_OFFSET, 0 , + SPI_RSER_RFDF_RE | SPI_RSER_TFFF_RE | + SPI_RSER_RFDF_DIRS | SPI_RSER_TFFF_DIRS); + + /* Start the DMAs */ + + spi_dmarxstart(priv); + spi_run(priv, true); + + spi_putreg(priv, KINETIS_SPI_TCR_OFFSET, 0); + spi_write_control(priv, SPI_PUSHR_CTAS_CTAR0); + + spi_dmatxstart(priv); + + /* Then wait for each to complete */ + + ret = spi_dmarxwait(priv); + + if (ret < 0) + { + ret = spi_dmatxwait(priv); + } + + /* Reset any status */ + + spi_write_status(priv, spi_getreg(priv, KINETIS_SPI_SR_OFFSET)); + + /* Halt SPI */ + + spi_run(priv, false); + + /* Disable DMA */ + + spi_modifyreg(priv, KINETIS_SPI_RSER_OFFSET, + SPI_RSER_RFDF_RE | SPI_RSER_TFFF_RE | + SPI_RSER_RFDF_DIRS | SPI_RSER_TFFF_DIRS, + 0); +} + +#endif /* CONFIG_KINETIS_SPI_DMA */ /**************************************************************************** * Name: spi_sndblock * @@ -1098,6 +1344,174 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, } #endif +/**************************************************************************** + * Name: spi_dmarxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static int spi_dmarxwait(FAR struct kinetis_spidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed. + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->rxsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->rxresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static int spi_dmatxwait(FAR struct kinetis_spidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed. + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->txsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->txresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmarxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static inline void spi_dmarxwakeup(FAR struct kinetis_spidev_s *priv) +{ + nxsem_post(&priv->rxsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static inline void spi_dmatxwakeup(FAR struct kinetis_spidev_s *priv) +{ + nxsem_post(&priv->txsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static void spi_dmarxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + FAR struct kinetis_spidev_s *priv = (FAR struct kinetis_spidev_s *)arg; + + priv->rxresult = result | 0x80000000; /* assure non-zero */ + spi_dmarxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static void spi_dmatxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + FAR struct kinetis_spidev_s *priv = (FAR struct kinetis_spidev_s *)arg; + + /* Wake-up the SPI driver */ + + priv->txresult = result | 0x80000000; /* assure non-zero */ + spi_dmatxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxstart + * + * Description: + * Start RX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static inline void spi_dmarxstart(FAR struct kinetis_spidev_s *priv) +{ + priv->rxresult = 0; + kinetis_dmach_start(priv->rxdma, spi_dmarxcallback, priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxstart + * + * Description: + * Start TX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI_DMA +static inline void spi_dmatxstart(FAR struct kinetis_spidev_s *priv) +{ + priv->txresult = 0; + kinetis_dmach_start(priv->txdma, spi_dmatxcallback, priv); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -1250,6 +1664,39 @@ FAR struct spi_dev_s *kinetis_spibus_initialize(int port) /* Initialize the SPI semaphore that enforces mutually exclusive access */ nxsem_init(&priv->exclsem, 0, 1); +#ifdef CONFIG_KINETIS_SPI_DMA + /* Initialize the SPI semaphores that is used to wait for DMA completion. + * This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + if (priv->rxch && priv->txch) + { + if (priv->txdma == NULL && priv->rxdma == NULL) + { + nxsem_init(&priv->rxsem, 0, 0); + nxsem_init(&priv->txsem, 0, 0); + + nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE); + nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE); + + priv->txdma = kinetis_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL, + 0); + priv->rxdma = kinetis_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL, + 0); + DEBUGASSERT(priv->rxdma && priv->txdma); + spi_modifyreg(priv, KINETIS_SPI_MCR_OFFSET, + 0, + SPI_MCR_DIS_RXF | SPI_MCR_DIS_TXF + ); + } + } + else + { + priv->rxdma = NULL; + priv->txdma = NULL; + } +#endif return &priv->spidev; } diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index 23c0c24de8b..13ea9f17538 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -50,13 +50,6 @@ static inline void kinetis_fpuconfig(void); #endif -#if 0 /* Not used */ -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif -#endif - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -195,49 +188,6 @@ static inline void kinetis_fpuconfig(void) # define kinetis_fpuconfig() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#if 0 /* Not used */ -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_uart.h b/arch/arm/src/kinetis/kinetis_uart.h index 29ef3666be4..39b9aa9d7ec 100644 --- a/arch/arm/src/kinetis/kinetis_uart.h +++ b/arch/arm/src/kinetis/kinetis_uart.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_uart.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: David Sidrane - * Jan Okle + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -68,51 +52,5 @@ # endif #endif -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: kinetis_serial_dma_poll - * - * Description: - * Must be called periodically if any Kinetis UART is configured for DMA. - * The DMA callback is triggered for each fifo size/2 bytes, but this can - * result in some bytes being transferred but not collected if the incoming - * data is not a whole multiple of half the FIFO size. - * - * May be safely called from either interrupt or thread context. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_DMA -void kinetis_serial_dma_poll(void); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER) */ #endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H */ diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index 4af48c21644..8c592829c9b 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/kinetis/kinetis_usbhshost.c b/arch/arm/src/kinetis/kinetis_usbhshost.c index cc16587e776..ccfd71e0058 100644 --- a/arch/arm/src/kinetis/kinetis_usbhshost.c +++ b/arch/arm/src/kinetis/kinetis_usbhshost.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_usbhshost.c * - * Copyright (C) 2013-2017, 2020 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_usbhshost.h b/arch/arm/src/kinetis/kinetis_usbhshost.h index 7d1c1e8e006..af8d12e4e8b 100644 --- a/arch/arm/src/kinetis/kinetis_usbhshost.h +++ b/arch/arm/src/kinetis/kinetis_usbhshost.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_usbhshost.h * - * Copyright (C) 2012, 2015, 2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/kl/Make.defs b/arch/arm/src/kl/Make.defs index 912223bd066..2f7691745ab 100644 --- a/arch/arm/src/kl/Make.defs +++ b/arch/arm/src/kl/Make.defs @@ -32,6 +32,7 @@ CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/kl/kl_dma.h b/arch/arm/src/kl/kl_dma.h index a8c7e7017c8..1a6dfc43929 100644 --- a/arch/arm/src/kl/kl_dma.h +++ b/arch/arm/src/kl/kl_dma.h @@ -111,9 +111,9 @@ void kl_dmainitilaize(void); * gives the caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ****************************************************************************/ diff --git a/arch/arm/src/kl/kl_dumpgpio.c b/arch/arm/src/kl/kl_dumpgpio.c index 826c10f0638..7b7af6df2ae 100644 --- a/arch/arm/src/kl/kl_dumpgpio.c +++ b/arch/arm/src/kl/kl_dumpgpio.c @@ -30,6 +30,7 @@ #define CONFIG_DEBUG_INFO 1 #include +#include #include #include @@ -82,7 +83,7 @@ static const char g_portchar[KL_GPIO_NPORTS] = * * Description: * Dump all GPIO registers associated with the provided pin description - * along with a descriptive messasge. + * along with a descriptive message. * ****************************************************************************/ diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c index c82adfe7df0..f0d78a6b7ca 100644 --- a/arch/arm/src/kl/kl_idle.c +++ b/arch/arm/src/kl/kl_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c index 1407015b6d9..dc18748e434 100644 --- a/arch/arm/src/kl/kl_irq.c +++ b/arch/arm/src/kl/kl_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/kl/kl_lowputc.c b/arch/arm/src/kl/kl_lowputc.c index 1cd139d31e3..baa849faf26 100644 --- a/arch/arm/src/kl/kl_lowputc.c +++ b/arch/arm/src/kl/kl_lowputc.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index 97e038cba0d..93b66a459d2 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c index 9e356c88d86..15a007696cc 100644 --- a/arch/arm/src/kl/kl_spi.c +++ b/arch/arm/src/kl/kl_spi.c @@ -476,7 +476,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into diff --git a/arch/arm/src/lc823450/Make.defs b/arch/arm/src/lc823450/Make.defs index 74e92be97bd..4f37e68a7cb 100644 --- a/arch/arm/src/lc823450/Make.defs +++ b/arch/arm/src/lc823450/Make.defs @@ -42,6 +42,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/lc823450/lc823450_dma.c b/arch/arm/src/lc823450/lc823450_dma.c index 75803789231..1ed240c16fc 100644 --- a/arch/arm/src/lc823450/lc823450_dma.c +++ b/arch/arm/src/lc823450/lc823450_dma.c @@ -496,9 +496,9 @@ void lc823450_dmareauest_dir(DMA_HANDLE handle, uint8_t dmarequest, int m2p) * gives the caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ****************************************************************************/ diff --git a/arch/arm/src/lc823450/lc823450_gpio.c b/arch/arm/src/lc823450/lc823450_gpio.c index 7a6e400e8c8..a7cf85cb2f5 100644 --- a/arch/arm/src/lc823450/lc823450_gpio.c +++ b/arch/arm/src/lc823450/lc823450_gpio.c @@ -27,6 +27,8 @@ #include #include + +#include #include #include diff --git a/arch/arm/src/lc823450/lc823450_i2s.c b/arch/arm/src/lc823450/lc823450_i2s.c index ac9d3d768b5..36a1a099375 100644 --- a/arch/arm/src/lc823450/lc823450_i2s.c +++ b/arch/arm/src/lc823450/lc823450_i2s.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index ffaf86882c3..f49d2e2a903 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lc823450/lc823450_mmcl.c b/arch/arm/src/lc823450/lc823450_mmcl.c index f63c03f2290..60cc5440e1c 100644 --- a/arch/arm/src/lc823450/lc823450_mmcl.c +++ b/arch/arm/src/lc823450/lc823450_mmcl.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lc823450/lc823450_sdc.c b/arch/arm/src/lc823450/lc823450_sdc.c index 49eb6f343e5..f75b2f8c3e1 100644 --- a/arch/arm/src/lc823450/lc823450_sdc.c +++ b/arch/arm/src/lc823450/lc823450_sdc.c @@ -42,6 +42,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/lc823450/lc823450_sddrv_dep.c b/arch/arm/src/lc823450/lc823450_sddrv_dep.c index 92621029942..9b2e2a179ef 100644 --- a/arch/arm/src/lc823450/lc823450_sddrv_dep.c +++ b/arch/arm/src/lc823450/lc823450_sddrv_dep.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lc823450/lc823450_serial.c b/arch/arm/src/lc823450/lc823450_serial.c index 03a06ad82cd..21689df999a 100644 --- a/arch/arm/src/lc823450/lc823450_serial.c +++ b/arch/arm/src/lc823450/lc823450_serial.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lc823450/lc823450_spi.c b/arch/arm/src/lc823450/lc823450_spi.c index 8781c50e977..d8a67dba466 100644 --- a/arch/arm/src/lc823450/lc823450_spi.c +++ b/arch/arm/src/lc823450/lc823450_spi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lc823450/lc823450_start.c b/arch/arm/src/lc823450/lc823450_start.c index 6bfe2fa1b90..952f48a550a 100644 --- a/arch/arm/src/lc823450/lc823450_start.c +++ b/arch/arm/src/lc823450/lc823450_start.c @@ -105,15 +105,6 @@ extern uint32_t _etext_sram; extern uint32_t _ftext; extern uint32_t _svect; -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -132,47 +123,6 @@ static void go_nx_start(void *pv, unsigned int nbytes) # define showprogress(c) #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmov r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -385,17 +335,9 @@ void __start(void) CURRENT_REGS = NULL; -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/lc823450/lc823450_syscontrol.c b/arch/arm/src/lc823450/lc823450_syscontrol.c index 410fa142f75..d081e961719 100644 --- a/arch/arm/src/lc823450/lc823450_syscontrol.c +++ b/arch/arm/src/lc823450/lc823450_syscontrol.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lc823450/lc823450_timer.c b/arch/arm/src/lc823450/lc823450_timer.c index 18b4dce9b08..fe652aa6bc3 100644 --- a/arch/arm/src/lc823450/lc823450_timer.c +++ b/arch/arm/src/lc823450/lc823450_timer.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/lc823450/lc823450_wdt.c b/arch/arm/src/lc823450/lc823450_wdt.c index a8dc72debc0..b99e3e63b15 100644 --- a/arch/arm/src/lc823450/lc823450_wdt.c +++ b/arch/arm/src/lc823450/lc823450_wdt.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/Kconfig b/arch/arm/src/lpc17xx_40xx/Kconfig index 14fd18d54b4..e41961a4f35 100644 --- a/arch/arm/src/lpc17xx_40xx/Kconfig +++ b/arch/arm/src/lpc17xx_40xx/Kconfig @@ -386,6 +386,7 @@ config LPC17_40_RTCEV config LPC17_40_WDT bool "WDT" default n + select WATCHDOG config LPC17_40_ADC bool "ADC" @@ -1069,18 +1070,3 @@ config LPC17_40_USBHOST_REGDEBUG also CONFIG_DEBUG_USB_INFO. endmenu - -menu "Memory-Technolgy-Device Options (PROGMEM)" - depends on LPC17_40_PROGMEM - -config LPC17_40_PROGMEM_NSECTORS - int "Size in 32 kB sectors" - default 2 - ---help--- - Number of 32 kB sectors to use as an MTD-device. This driver - will allocate the last n sectors. Only 32 kB sectors are - supported, so this works only on devices with 128 kB, 256 kB and - 512 kB of flash. The maximum number of sectors for these - devices is 2, 6 and 14, respectively. Default is 2. - -endmenu diff --git a/arch/arm/src/lpc17xx_40xx/Make.defs b/arch/arm/src/lpc17xx_40xx/Make.defs index 96b01fd0b84..20883e70d8b 100644 --- a/arch/arm/src/lpc17xx_40xx/Make.defs +++ b/arch/arm/src/lpc17xx_40xx/Make.defs @@ -54,6 +54,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif @@ -147,6 +148,10 @@ ifeq ($(CONFIG_LPC17_40_RTC),y) CHIP_CSRCS += lpc176x_rtc.c endif +ifeq ($(CONFIG_LPC17_40_WDT),y) +CHIP_CSRCS += lpc17_40_wdt.c +endif + ifeq ($(CONFIG_LPC17_40_PWM1),y) CHIP_CSRCS += lpc17_40_pwm.c endif @@ -159,6 +164,6 @@ ifeq ($(CONFIG_LPC17_40_TMR0),y) CHIP_CSRCS += lpc17_40_timer.c endif -ifeq ($(CONFIG_MTD_PROGMEM),y) +ifeq ($(CONFIG_LPC17_40_PROGMEM),y) CHIP_CSRCS += lpc17_40_progmem.c endif diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h index 7547ec394bc..726153b39f2 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_iocon.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Rommel Marcelo - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h index e34cc67a61a..384f6a9bdf6 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Authors: Rommel Marcelo - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h index b9256e19f66..20ed62dbedf 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_pinconfig.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Authors: Rommel Marcelo - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h index dd18b465f73..0eee332710b 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Authors: Rommel Marcelo - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h index 076db8351c4..6c6d1b2297a 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h @@ -89,6 +89,8 @@ /* Watchdog feed sequence register */ +#define WDT_FEED_KEY_1 (0xAA) /* Watchdog feed key 1 */ +#define WDT_FEED_KEY_2 (0x55) /* Watchdog feed key 2 */ #define WDT_FEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa * followed by 0x55 */ /* Bits 14-31: Reserved */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c index 0d3e0fb4f76..a63408937a2 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c b/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c index 7df5242097c..404f4711727 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c @@ -175,30 +175,6 @@ static int rtc_setup(void) return OK; } -/**************************************************************************** - * Name: rtc_resume - * - * Description: - * Called when the RTC was already initialized on a previous power cycle. - * This just brings the RTC back into full operation. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_resume(void) -{ - /* Clear the RTC alarm flags */ - -#ifdef CONFIG_RTC_ALARM -#endif - return OK; -} - /**************************************************************************** * Name: rtc_interrupt * @@ -273,7 +249,7 @@ int up_rtc_initialize(void) g_rtc_enabled = true; rtc_dumpregs("After Initialization"); - return OK; + return ret; } /**************************************************************************** diff --git a/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c index 1a1c8341115..9b511fc0164 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c +++ b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c * - * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * With LPC178x extensions from Rommel Marcelo + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_allocateheap.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_allocateheap.c index 82a823346e5..f7694481f08 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_allocateheap.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_allocateheap.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c index 124a6cbfe8a..454ed3cd7c2 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c index 27befee53b8..29aef02b98f 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -655,9 +656,9 @@ static int lpc17_40_transmit(struct lpc17_40_driver_s *priv) *txdesc = TXDESC_CONTROL_INT | TXDESC_CONTROL_LAST | TXDESC_CONTROL_CRC | (priv->lp_dev.d_len - 1); - /* Copy the packet data into the Tx buffer assignd to this descriptor. It + /* Copy the packet data into the Tx buffer assigned to this descriptor. It * should fit because each packet buffer is the MTU size and breaking up - * largerTCP messasges is handled by higher level logic. The hardware + * larger TCP message is handled by higher level logic. The hardware * does, however, support breaking up larger messages into many fragments, * however, that capability is not exploited here. * diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c index 7d506676ee8..6029cb9a126 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c @@ -367,9 +367,9 @@ void lpc17_40_dmaconfigure(uint8_t dmarequest, bool alternate) * gives the caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h index 128be9848d3..a6db12cb304 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h @@ -149,9 +149,9 @@ void lpc17_40_dmaconfigure(uint8_t dmarequest, bool alternate); * gives the caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c index 03f2fa5bc94..5dd1432bb80 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc17xx_40xx/lpc17_40_gpio.c * - * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * With LPC178x extensions from Rommel Marcelo + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c index 0c1547c4e96..7e9ed99da7b 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c index 28c8241fb92..aed53faaa0b 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c index 58151cd95b5..a065f4e2c34 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c index b203bdf5ef1..7ad79302487 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.c @@ -27,13 +27,12 @@ * Included Files ****************************************************************************/ -#include - #include #include -#include -#include +#include +#include +#include #include #include #include @@ -74,7 +73,7 @@ static void lpc17_40_iap(FAR void *in, FAR void *out) flags = enter_critical_section(); - ((void *(FAR void *, FAR void *))LPC17_40_IAP_ENTRY_ADDR)(in, out); + ((void (*)(FAR void *, FAR void *))LPC17_40_IAP_ENTRY_ADDR)(in, out); leave_critical_section(flags); } @@ -171,7 +170,7 @@ static uint32_t lpc17_40_iap_copy_ram_to_flash(void *flash, const void *ram, size_t up_progmem_neraseblocks(void) { - return CONFIG_LPC17_40_PROGMEM_NSECTORS; + return LPC17_40_FLASH_NUM_SECTORS; } /**************************************************************************** @@ -184,7 +183,7 @@ size_t up_progmem_neraseblocks(void) bool up_progmem_isuniform(void) { - return true; + return false; } /**************************************************************************** @@ -197,7 +196,7 @@ bool up_progmem_isuniform(void) size_t up_progmem_pagesize(size_t page) { - return (size_t)LPC17_40_PROGMEM_PAGE_SIZE; + return up_progmem_erasesize(page); } /**************************************************************************** @@ -210,7 +209,19 @@ size_t up_progmem_pagesize(size_t page) size_t up_progmem_erasesize(size_t block) { - return (size_t)LPC17_40_PROGMEM_SECTOR_SIZE; + if (block >= LPC17_40_FLASH_NUM_SECTORS) + { + return 0; + } + + if (block < LPC17_40_FLASH_NUM_4K_SECTORS) + { + return (size_t)(4 * 1024); + } + else + { + return (size_t)(32 * 1024); + } } /**************************************************************************** @@ -233,12 +244,25 @@ size_t up_progmem_erasesize(size_t block) ssize_t up_progmem_getpage(size_t addr) { - if (addr >= LPC17_40_PROGMEM_START_ADDR) + ssize_t page; + + if (addr >= LPC17_40_FLASH_SIZE) { - addr -= LPC17_40_PROGMEM_START_ADDR; + return -EFAULT; } - return (size_t)(addr / LPC17_40_PROGMEM_PAGE_SIZE); + if (addr < (LPC17_40_FLASH_NUM_4K_SECTORS * (4 * 1024))) + { + page = addr / (4 * 1024); + } + else + { + page = LPC17_40_FLASH_NUM_4K_SECTORS + + ((addr - (LPC17_40_FLASH_NUM_4K_SECTORS * + (4 * 1024))) / (32 * 1024)); + } + + return page; } /**************************************************************************** @@ -257,8 +281,24 @@ ssize_t up_progmem_getpage(size_t addr) size_t up_progmem_getaddress(size_t page) { - return (size_t)(LPC17_40_PROGMEM_START_ADDR + - page * LPC17_40_PROGMEM_PAGE_SIZE); + size_t addr; + + if (page >= LPC17_40_FLASH_NUM_SECTORS) + { + return SIZE_MAX; + } + + if (page < LPC17_40_FLASH_NUM_4K_SECTORS) + { + addr = page * (4 * 1024); + } + else + { + addr = (LPC17_40_FLASH_NUM_4K_SECTORS * (4 * 1024)) + + ((page - LPC17_40_FLASH_NUM_4K_SECTORS) * (32 * 1024)); + } + + return addr; } /**************************************************************************** @@ -287,27 +327,25 @@ ssize_t up_progmem_eraseblock(size_t block) { uint32_t rc; - if (block >= CONFIG_LPC17_40_PROGMEM_NSECTORS) + if (block >= LPC17_40_FLASH_NUM_SECTORS) { return -EFAULT; } - rc = lpc17_40_iap_prepare_sector_for_write_operation((uint32_t)block + - LPC17_40_PROGMEM_START_SECTOR); + rc = lpc17_40_iap_prepare_sector_for_write_operation((uint32_t)block); if (rc != LPC17_40_IAP_RC_CMD_SUCCESS) { return -EIO; } - rc = lpc17_40_iap_erase_sector((uint32_t)block + - LPC17_40_PROGMEM_START_SECTOR); + rc = lpc17_40_iap_erase_sector((uint32_t)block); if (rc != LPC17_40_IAP_RC_CMD_SUCCESS) { return -EIO; } - return (ssize_t)LPC17_40_PROGMEM_SECTOR_SIZE; + return (ssize_t)up_progmem_erasesize(block); } /**************************************************************************** @@ -330,17 +368,19 @@ ssize_t up_progmem_eraseblock(size_t block) ssize_t up_progmem_ispageerased(size_t page) { + size_t page_size; const uint8_t *p; int i; - if (page >= CONFIG_LPC17_40_PROGMEM_NSECTORS) + if (page >= LPC17_40_FLASH_NUM_SECTORS) { return -EFAULT; } + page_size = up_progmem_pagesize(page); p = (const uint8_t *)up_progmem_getaddress(page); - for (i = 0; i < LPC17_40_PROGMEM_SECTOR_SIZE; i++) + for (i = 0; i < page_size; i++) { if (p[i] != 0xffu) { @@ -348,7 +388,7 @@ ssize_t up_progmem_ispageerased(size_t page) } } - return (ssize_t)(LPC17_40_PROGMEM_SECTOR_SIZE - i); + return (ssize_t)(page_size - i); } /**************************************************************************** @@ -386,13 +426,17 @@ ssize_t up_progmem_write(size_t addr, FAR const void *buf, size_t count) size_t page; uint32_t rc; - if (count % LPC17_40_PROGMEM_PAGE_SIZE) + if (addr % LPC17_40_WRITE_SIZE) + { + return -EFAULT; + } + + if (count % LPC17_40_WRITE_SIZE) { return -EINVAL; } - page = up_progmem_getpage(addr) / LPC17_40_PROGMEM_PAGES_PER_SECTOR + - LPC17_40_PROGMEM_START_SECTOR; + page = up_progmem_getpage(addr); rc = lpc17_40_iap_prepare_sector_for_write_operation((uint32_t)page); diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.h index a9fd3030002..18f766df67f 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_progmem.h @@ -35,60 +35,27 @@ * ****************************************************************************/ -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* The first 16 sectors are 4kB in size and thus not supported as progmem. */ +/* The first 16 sectors are 4kB in size. */ #define LPC17_40_FLASH_NUM_4K_SECTORS 16 -/* The number of 32kB sectors depends on the target device's flash size */ +/* The number of 32kB sectors depends on the target device's flash size. */ #define LPC17_40_FLASH_NUM_32K_SECTORS \ ((LPC17_40_FLASH_SIZE - LPC17_40_FLASH_NUM_4K_SECTORS * 4096) / 32768) -/* The number of 32kB sectors to be used for progmem is configurable. - * The sectors at the end of the flash are used for progmem, the rest is - * left for code and data. - */ +/* The total number of sectors is the sum of the 4k and 32k sectors. */ -#define LPC17_40_PROGMEM_START_SECTOR \ - (LPC17_40_FLASH_NUM_4K_SECTORS + LPC17_40_FLASH_NUM_32K_SECTORS - \ - CONFIG_LPC17_40_PROGMEM_NSECTORS) +#define LPC17_40_FLASH_NUM_SECTORS \ + (LPC17_40_FLASH_NUM_4K_SECTORS + LPC17_40_FLASH_NUM_32K_SECTORS) -/* Base address of the flash segment used for progmem. */ +/* Size of a write page. */ -#define LPC17_40_PROGMEM_START_ADDR \ - (LPC17_40_FLASH_NUM_4K_SECTORS * 4096 + \ - (LPC17_40_PROGMEM_START_SECTOR - LPC17_40_FLASH_NUM_4K_SECTORS) * 32768) - -/* Size of the flash segment used for progmem. */ - -#define LPC17_40_PROGMEM_SIZE (CONFIG_LPC17_40_PROGMEM_NSECTORS * 32768) - -/* Size of a read/write page. */ - -#define LPC17_40_PROGMEM_PAGE_SIZE 256 - -/* Total number of read/write pages. */ - -#define LPC17_40_PROGMEM_NUM_PAGES (LPC17_40_PROGMEM_SIZE / LPC17_40_PROGMEM_PAGE_SIZE) - -/* Size of an erase page. This driver only supports the 32kB sectors. */ - -#define LPC17_40_PROGMEM_SECTOR_SIZE 32768 - -/* Number of read/write pages per erase page. */ - -#define LPC17_40_PROGMEM_PAGES_PER_SECTOR \ - (LPC17_40_PROGMEM_SECTOR_SIZE / LPC17_40_PROGMEM_PAGE_SIZE) +#define LPC17_40_WRITE_SIZE 256 /* LPC17 entry point for In-Application-Programming boot rom service * function diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c index 0a5f62a308c..d8e98483ccf 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_SERIAL_TERMIOS diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c index 8f883c1e947..cb01b94ad21 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c index c9357bcc2b1..29417626166 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c index ce60a3b2f8f..77a23a974a6 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c index 5be37ccfca7..f6b6567f97d 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c * - * Copyright (C) 2010-2012, 2014-2017 Gregory Nutt. All rights reserved. - * Authors: Rafael Noronha - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -47,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.c new file mode 100644 index 00000000000..0c1bf51a1ee --- /dev/null +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.c @@ -0,0 +1,358 @@ +/**************************************************************************** + * arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_arch.h" +#include "hardware/lpc17_40_wdt.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_wdt.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_LPC17_40_WDT) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Default WDT timeout value, in ms. */ + +#define LPC17_40_WDT_DEFTIMEOUT 1000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct lpc17_40_lowerhalf_s +{ + FAR const struct watchdog_ops_s *ops; /* Lower half operations */ + uint32_t timeout; /* The (actual) selected timeout */ + uint32_t lastreset; /* The last reset time */ + bool started; /* true: The watchdog timer has been started */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* "Lower half" driver methods **********************************************/ + +static int lpc17_40_start(FAR struct watchdog_lowerhalf_s *lower); +static int lpc17_40_stop(FAR struct watchdog_lowerhalf_s *lower); +static int lpc17_40_keepalive(FAR struct watchdog_lowerhalf_s *lower); +static int lpc17_40_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status); +static int lpc17_40_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = lpc17_40_start, + .stop = lpc17_40_stop, + .keepalive = lpc17_40_keepalive, + .getstatus = lpc17_40_getstatus, + .settimeout = lpc17_40_settimeout, + .capture = NULL, + .ioctl = NULL, +}; + +/* "Lower half" driver state */ + +static struct lpc17_40_lowerhalf_s g_wdgdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc17_40_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout. + * + * Input Parameters: + * lower - A pointer to the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc17_40_start(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct lpc17_40_lowerhalf_s *priv = + (FAR struct lpc17_40_lowerhalf_s *)lower; + irqstate_t flags; + uint32_t wdmod; + + DEBUGASSERT(priv); + + /* Have we already been started? */ + + if (!priv->started) + { + flags = enter_critical_section(); + + priv->started = true; + priv->lastreset = clock_systime_ticks(); + + wdmod = getreg32(LPC17_40_WDT_MOD); + wdmod |= (WDT_MOD_WDEN | WDT_MOD_WDRESET); + putreg32(wdmod, LPC17_40_WDT_MOD); + + putreg32(WDT_FEED_KEY_1, LPC17_40_WDT_FEED); + putreg32(WDT_FEED_KEY_2, LPC17_40_WDT_FEED); + + leave_critical_section(flags); + } + + return OK; +} + +/**************************************************************************** + * Name: lpc17_40_stop + * + * Description: + * Stop the watchdog timer. + * + * Input Parameters: + * lower - A pointer to the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc17_40_stop(FAR struct watchdog_lowerhalf_s *lower) +{ + /* There is no way to disable WDT once it has been started. */ + + return -ENOSYS; +} + +/**************************************************************************** + * Name: lpc17_40_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "petting the dog". + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc17_40_keepalive(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct lpc17_40_lowerhalf_s *priv = + (FAR struct lpc17_40_lowerhalf_s *)lower; + irqstate_t flags; + + /* Reload the WDT. */ + + flags = enter_critical_section(); + putreg32(WDT_FEED_KEY_1, LPC17_40_WDT_FEED); + putreg32(WDT_FEED_KEY_2, LPC17_40_WDT_FEED); + priv->lastreset = clock_systime_ticks(); + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: lpc17_40_getstatus + * + * Description: + * Get the current watchdog timer status. + * + * Input Parameters: + * lower - A pointer to the publicly visible representation of the + * "lower-half" driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc17_40_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status) +{ + FAR struct lpc17_40_lowerhalf_s *priv = + (FAR struct lpc17_40_lowerhalf_s *)lower; + uint32_t ticks; + uint32_t elapsed; + + DEBUGASSERT(priv); + + /* Return the status bit. */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + /* Return the actual timeout in milliseconds. */ + + status->timeout = priv->timeout; + + /* Get the elapsed time since the last ping. */ + + ticks = clock_systime_ticks() - priv->lastreset; + elapsed = (int32_t)TICK2MSEC(ticks); + + if (elapsed > priv->timeout) + { + elapsed = priv->timeout; + } + + /* Return the approximate time until the watchdog timer expiration. */ + + status->timeleft = priv->timeout - elapsed; + + return OK; +} + +/**************************************************************************** + * Name: lpc17_40_settimeout + * + * Description: + * Set a new timeout value. + * + * Input Parameters: + * lower - A pointer to the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc17_40_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct lpc17_40_lowerhalf_s *priv = + (FAR struct lpc17_40_lowerhalf_s *)lower; + uint64_t wdt_clk; + uint64_t wdtc; + + priv->timeout = timeout; + +#ifdef LPC176x + /* The internal RC oscillator will be used for the WDT. It is clocked at + * 4MHz. This is further divided by 4, by the WDT fixed prescaller. + */ + + wdt_clk = 4000000 / 4; + putreg32(WDT_CLKSEL_WDSEL_INTRC, LPC17_40_WDT_CLKSEL); +#else + /* WDT has a dedicated clock, set at 500kHz. This is further divided by 4, + * by the WDT fixed prescaller. + */ + + wdt_clk = 500000 / 4; +#endif + + wdtc = ((uint64_t)timeout * wdt_clk) / 1000; + putreg32((uint32_t)wdtc, LPC17_40_WDT_TC); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc17_40_wdtinitialize + * + * Description: + * Initialize the watchdog timer. The watchdog timer is initialized and + * registers as 'devpath. The initial state of the watchdog timer is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void lpc17_40_wdtinitialize(FAR const char *devpath) +{ + FAR struct lpc17_40_lowerhalf_s *priv = &g_wdgdev; + + /* Initialize the driver state structure. */ + + priv->ops = &g_wdgops; + priv->timeout = 0; + priv->lastreset = 0; + priv->started = false; + + /* Select an arbitrary initial timeout value. But don't start the watchdog + * yet. + */ + + lpc17_40_settimeout((FAR struct watchdog_lowerhalf_s *)priv, + LPC17_40_WDT_DEFTIMEOUT); + + /* Register the watchdog driver as devpath. */ + + watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv); +} + +#endif /* CONFIG_WATCHDOG && CONFIG_LPC17_40_WDT */ + diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.h index c493f81cf80..fde2b095a5d 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_wdt.h @@ -28,20 +28,51 @@ #include #include "hardware/lpc17_40_wdt.h" +#ifdef CONFIG_LPC17_40_WDT + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Public Types - ****************************************************************************/ +#ifndef __ASSEMBLY__ -/**************************************************************************** - * Public Data - ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: lpc17_40_wdtinitialize + * + * Description: + * Initialize the watchdog timer. The watchdog timer is initialized and + * registers as 'devpath. The initial state of the watchdog timer is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void lpc17_40_wdtinitialize(FAR const char *devpath); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_LPC17_40_WDT */ #endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_WDT_H */ diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index 5a26ca8622e..82a27bd0e03 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c index 206b3076a5d..6717053aefa 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index 45383a7f97f..d789e282f95 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -59,6 +59,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index 89a9ce5ea6e..b9f63557cb0 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c index 3539841d496..0cba0101120 100644 --- a/arch/arm/src/lpc2378/lpc23xx_spi.c +++ b/arch/arm/src/lpc2378/lpc23xx_spi.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.c b/arch/arm/src/lpc31xx/lpc31_i2c.c index 437102503c2..a269d8c07d4 100644 --- a/arch/arm/src/lpc31xx/lpc31_i2c.c +++ b/arch/arm/src/lpc31xx/lpc31_i2c.c @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc31xx/lpc31_i2c.c * - * Author: David Hewson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Copyright (C) 2010-2011, 2014, 2016-2017 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -47,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c index 9bfdd1dd060..d651beb3269 100644 --- a/arch/arm/src/lpc31xx/lpc31_spi.c +++ b/arch/arm/src/lpc31xx/lpc31_spi.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc31xx/lpc31_spi.c * - * Copyright (C) 2009-2017 Gregory Nutt. All rights reserved. - * Author: David Hewson, deriving in part from other SPI drivers - * originally by Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include #include +#include #include #include @@ -765,7 +750,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t word) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c index 1d48739fcdf..eb60a7ff664 100644 --- a/arch/arm/src/lpc31xx/lpc31_usbdev.c +++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c @@ -1,40 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc31xx/lpc31_usbdev.c * - * Authors: David Hewson - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Part of the NuttX OS and based, in part, on the LPC2148 USB driver: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2010-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -49,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs index 05d8ba44de9..c42b7774d06 100644 --- a/arch/arm/src/lpc43xx/Make.defs +++ b/arch/arm/src/lpc43xx/Make.defs @@ -47,6 +47,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/lpc43xx/hardware/lpc43_rit.h b/arch/arm/src/lpc43xx/hardware/lpc43_rit.h index 3479e6ddf15..c8d21ec69d7 100644 --- a/arch/arm/src/lpc43xx/hardware/lpc43_rit.h +++ b/arch/arm/src/lpc43xx/hardware/lpc43_rit.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc43xx/hardware/lpc43_rit.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Brandon Warhurst - * Original Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_aes.c b/arch/arm/src/lpc43xx/lpc43_aes.c index 4735f99b1ad..53ef95c230a 100644 --- a/arch/arm/src/lpc43xx/lpc43_aes.c +++ b/arch/arm/src/lpc43xx/lpc43_aes.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_aes.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Alexander Vasiljev + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_can.c b/arch/arm/src/lpc43xx/lpc43_can.c index 45432e14395..48e0b90ec90 100644 --- a/arch/arm/src/lpc43xx/lpc43_can.c +++ b/arch/arm/src/lpc43xx/lpc43_can.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_can.c * - * Copyright(C) 2017 Gregory Nutt. All rights reserved. + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Created on: 2 May 2017 - * Author: katherine + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -45,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_can.h b/arch/arm/src/lpc43xx/lpc43_can.h index 457067807bc..30c9dd32d41 100644 --- a/arch/arm/src/lpc43xx/lpc43_can.h +++ b/arch/arm/src/lpc43xx/lpc43_can.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_can.h * - * Copyright(C) 2017 Gregory Nutt. All rights reserved. + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Created on: 2 May 2017 - * Author: katherine + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index 933888964f3..9aa907b53a9 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.c b/arch/arm/src/lpc43xx/lpc43_gpdma.c index 2d45d74b026..2143fb37f5b 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpdma.c +++ b/arch/arm/src/lpc43xx/lpc43_gpdma.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -366,9 +367,9 @@ void lpc43_dmaconfigure(uint8_t dmarequest, uint8_t dmasrc) * gives the caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.h b/arch/arm/src/lpc43xx/lpc43_gpdma.h index deaabc38d5d..ebd925961ff 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpdma.h +++ b/arch/arm/src/lpc43xx/lpc43_gpdma.h @@ -114,9 +114,9 @@ extern "C" * gives the caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_gpio.c b/arch/arm/src/lpc43xx/lpc43_gpio.c index 8e8c9da5d59..ece1b4c1657 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpio.c +++ b/arch/arm/src/lpc43xx/lpc43_gpio.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.c b/arch/arm/src/lpc43xx/lpc43_gpioint.c index 3ecd4747bc0..7c4a917e41a 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpioint.c +++ b/arch/arm/src/lpc43xx/lpc43_gpioint.c @@ -43,8 +43,9 @@ #include #include -#include +#include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c index f63caa3df8c..0299fcdc6c7 100644 --- a/arch/arm/src/lpc43xx/lpc43_i2c.c +++ b/arch/arm/src/lpc43xx/lpc43_i2c.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c index f82cc838bfd..0c01ef16a9c 100644 --- a/arch/arm/src/lpc43xx/lpc43_idle.c +++ b/arch/arm/src/lpc43xx/lpc43_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index 95dfc9bc985..3ae81acaf68 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c index 3c4e7725d40..5faaf9ccb91 100644 --- a/arch/arm/src/lpc43xx/lpc43_rit.c +++ b/arch/arm/src/lpc43xx/lpc43_rit.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_rit.c * - * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. - * Author: Brandon Warhurst + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_rit.h b/arch/arm/src/lpc43xx/lpc43_rit.h index 358db0dbbc2..855f44f81bb 100644 --- a/arch/arm/src/lpc43xx/lpc43_rit.h +++ b/arch/arm/src/lpc43xx/lpc43_rit.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_rit.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Brandon Warhurst + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_rtc.c b/arch/arm/src/lpc43xx/lpc43_rtc.c index 0d2c7101966..54591f9ec94 100644 --- a/arch/arm/src/lpc43xx/lpc43_rtc.c +++ b/arch/arm/src/lpc43xx/lpc43_rtc.c @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_rtc.c * - * Copyright (C) 2014, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Adapted for the LPC43xx by Gintaras Drukteinis from the similar - * LCP176x RTC driver. + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index cf9ab828399..d36555c8a87 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c index e6234f9ce82..591c6fab4c0 100644 --- a/arch/arm/src/lpc43xx/lpc43_spi.c +++ b/arch/arm/src/lpc43xx/lpc43_spi.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.c b/arch/arm/src/lpc43xx/lpc43_spifi.c index 3eec0eb21b7..1e5df209678 100644 --- a/arch/arm/src/lpc43xx/lpc43_spifi.c +++ b/arch/arm/src/lpc43xx/lpc43_spifi.c @@ -1146,7 +1146,7 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv) * None * * Returned Value: - * One success, a reference to the initialized MTD device instance is + * On success, a reference to the initialized MTD device instance is * returned; NULL is returned on any failure. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.h b/arch/arm/src/lpc43xx/lpc43_spifi.h index 86b9c44f0ec..e0ea6a65918 100644 --- a/arch/arm/src/lpc43xx/lpc43_spifi.h +++ b/arch/arm/src/lpc43xx/lpc43_spifi.h @@ -102,7 +102,7 @@ extern "C" * None * * Returned Value: - * One success, a reference to the initialized MTD device instance is + * On success, a reference to the initialized MTD device instance is * returned; NULL is returned on any failure. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c index a068013f344..861609fad79 100644 --- a/arch/arm/src/lpc43xx/lpc43_ssp.c +++ b/arch/arm/src/lpc43xx/lpc43_ssp.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_timer.c b/arch/arm/src/lpc43xx/lpc43_timer.c index 51798c326d2..ee518983344 100644 --- a/arch/arm/src/lpc43xx/lpc43_timer.c +++ b/arch/arm/src/lpc43xx/lpc43_timer.c @@ -29,6 +29,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_uart.c b/arch/arm/src/lpc43xx/lpc43_uart.c index 96efbb65203..f9077650520 100644 --- a/arch/arm/src/lpc43xx/lpc43_uart.c +++ b/arch/arm/src/lpc43xx/lpc43_uart.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index 9b95a58bf88..76381228dd2 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -1,45 +1,20 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_usb0dev.c * - * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Part of the NuttX OS and based, in part, on the LPC31xx USB driver: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Authors: David Hewson - * Gregory Nutt - * - * Which, in turn, was based on the LPC2148 USB driver: - * - * Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -54,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc43xx/lpc43_wwdt.c b/arch/arm/src/lpc43xx/lpc43_wwdt.c index f8a26e4f2b9..b1a2ce6d1c7 100644 --- a/arch/arm/src/lpc43xx/lpc43_wwdt.c +++ b/arch/arm/src/lpc43xx/lpc43_wwdt.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs index d40a65d3a14..2f89791d6a8 100644 --- a/arch/arm/src/lpc54xx/Make.defs +++ b/arch/arm/src/lpc54xx/Make.defs @@ -47,6 +47,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/lpc54xx/lpc54_dma.c b/arch/arm/src/lpc54xx/lpc54_dma.c index 2cfc7737811..c366647f6c6 100644 --- a/arch/arm/src/lpc54xx/lpc54_dma.c +++ b/arch/arm/src/lpc54xx/lpc54_dma.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_ethernet.c b/arch/arm/src/lpc54xx/lpc54_ethernet.c index fa4499a178b..223dc90cd82 100644 --- a/arch/arm/src/lpc54xx/lpc54_ethernet.c +++ b/arch/arm/src/lpc54xx/lpc54_ethernet.c @@ -3048,7 +3048,7 @@ int arm_netinitialize(int intf) { /* We could not attach the ISR to the interrupt */ - nerr("ERROR: irq_attach failed: %d\n", ret); + nerr("ERROR: irq_attach failed: %d\n", ret); return -EAGAIN; } diff --git a/arch/arm/src/lpc54xx/lpc54_gpioirq.c b/arch/arm/src/lpc54xx/lpc54_gpioirq.c index 94d05d05b42..080cd13d250 100644 --- a/arch/arm/src/lpc54xx/lpc54_gpioirq.c +++ b/arch/arm/src/lpc54xx/lpc54_gpioirq.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.c b/arch/arm/src/lpc54xx/lpc54_i2c_master.c index 20236dad52b..80ea9d5992f 100644 --- a/arch/arm/src/lpc54xx/lpc54_i2c_master.c +++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_idle.c b/arch/arm/src/lpc54xx/lpc54_idle.c index 9e061ea79b6..96693756336 100644 --- a/arch/arm/src/lpc54xx/lpc54_idle.c +++ b/arch/arm/src/lpc54xx/lpc54_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_irq.c b/arch/arm/src/lpc54xx/lpc54_irq.c index c71e53e1929..cf98323a54d 100644 --- a/arch/arm/src/lpc54xx/lpc54_irq.c +++ b/arch/arm/src/lpc54xx/lpc54_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_lcd.c b/arch/arm/src/lpc54xx/lpc54_lcd.c index ce4e2d2da17..db588b670b0 100644 --- a/arch/arm/src/lpc54xx/lpc54_lcd.c +++ b/arch/arm/src/lpc54xx/lpc54_lcd.c @@ -30,6 +30,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c b/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c index 7b106d812e6..3056d82c79b 100644 --- a/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c +++ b/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c index d8809159f4a..6d4eea4daab 100644 --- a/arch/arm/src/lpc54xx/lpc54_serial.c +++ b/arch/arm/src/lpc54xx/lpc54_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.c b/arch/arm/src/lpc54xx/lpc54_spi_master.c index b8e763f4659..9223883fb2e 100644 --- a/arch/arm/src/lpc54xx/lpc54_spi_master.c +++ b/arch/arm/src/lpc54xx/lpc54_spi_master.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c index 025f428bbec..f9ec61deaf2 100644 --- a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c +++ b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/lpc54xx/lpc54_wwdt.c b/arch/arm/src/lpc54xx/lpc54_wwdt.c index 59f61e0a0fd..dbc2edd18b3 100644 --- a/arch/arm/src/lpc54xx/lpc54_wwdt.c +++ b/arch/arm/src/lpc54xx/lpc54_wwdt.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/max326xx/Make.defs b/arch/arm/src/max326xx/Make.defs index 628bcdd0518..b4f7e63c93a 100644 --- a/arch/arm/src/max326xx/Make.defs +++ b/arch/arm/src/max326xx/Make.defs @@ -45,6 +45,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/max326xx/common/max326_idle.c b/arch/arm/src/max326xx/common/max326_idle.c index b4bd1e154ae..224d1a104c9 100644 --- a/arch/arm/src/max326xx/common/max326_idle.c +++ b/arch/arm/src/max326xx/common/max326_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/max326xx/common/max326_irq.c b/arch/arm/src/max326xx/common/max326_irq.c index 09dfe1ed110..6765753927c 100644 --- a/arch/arm/src/max326xx/common/max326_irq.c +++ b/arch/arm/src/max326xx/common/max326_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c b/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c index 06dc273498e..2489e59da02 100644 --- a/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c +++ b/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/max326xx/common/max326_timerisr.c b/arch/arm/src/max326xx/common/max326_timerisr.c index 205cf504ca3..f343b4a7025 100644 --- a/arch/arm/src/max326xx/common/max326_timerisr.c +++ b/arch/arm/src/max326xx/common/max326_timerisr.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/max326xx/max32660/max32660_clockconfig.c b/arch/arm/src/max326xx/max32660/max32660_clockconfig.c index b9c07b2f0fc..a2002eb3544 100644 --- a/arch/arm/src/max326xx/max32660/max32660_clockconfig.c +++ b/arch/arm/src/max326xx/max32660/max32660_clockconfig.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/max326xx/max32660/max32660_gpio.c b/arch/arm/src/max326xx/max32660/max32660_gpio.c index 1693851e4fd..9db7286fa30 100644 --- a/arch/arm/src/max326xx/max32660/max32660_gpio.c +++ b/arch/arm/src/max326xx/max32660/max32660_gpio.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/max326xx/max32660/max32660_gpioirq.c b/arch/arm/src/max326xx/max32660/max32660_gpioirq.c index 33d5ba4de6e..509dc51961d 100644 --- a/arch/arm/src/max326xx/max32660/max32660_gpioirq.c +++ b/arch/arm/src/max326xx/max32660/max32660_gpioirq.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/max326xx/max32660/max32660_lowputc.c b/arch/arm/src/max326xx/max32660/max32660_lowputc.c index e2d3419b8f7..f1c33cf9b02 100644 --- a/arch/arm/src/max326xx/max32660/max32660_lowputc.c +++ b/arch/arm/src/max326xx/max32660/max32660_lowputc.c @@ -26,6 +26,7 @@ #include #include +#include #include diff --git a/arch/arm/src/max326xx/max32660/max32660_rtc.c b/arch/arm/src/max326xx/max32660/max32660_rtc.c index 08fc3edf1b2..d90a2778129 100644 --- a/arch/arm/src/max326xx/max32660/max32660_rtc.c +++ b/arch/arm/src/max326xx/max32660/max32660_rtc.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/max326xx/max32660/max32660_serial.c b/arch/arm/src/max326xx/max32660/max32660_serial.c index 2b10d3e7d13..de5f43ae637 100644 --- a/arch/arm/src/max326xx/max32660/max32660_serial.c +++ b/arch/arm/src/max326xx/max32660/max32660_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/max326xx/max32660/max32660_spim.c b/arch/arm/src/max326xx/max32660/max32660_spim.c index 6cfd19a7a61..3b97e586452 100644 --- a/arch/arm/src/max326xx/max32660/max32660_spim.c +++ b/arch/arm/src/max326xx/max32660/max32660_spim.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/max326xx/max32660/max32660_wdt.c b/arch/arm/src/max326xx/max32660/max32660_wdt.c index 6c974e4b41d..dd9bad1fb08 100644 --- a/arch/arm/src/max326xx/max32660/max32660_wdt.c +++ b/arch/arm/src/max326xx/max32660/max32660_wdt.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/moxart/moxart_16550.c b/arch/arm/src/moxart/moxart_16550.c index 1a514702306..01a907e7976 100644 --- a/arch/arm/src/moxart/moxart_16550.c +++ b/arch/arm/src/moxart/moxart_16550.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/moxart/moxart_16550.c - * Driver for MoxaRT IRQ controller * - * Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved. - * Author: Anton D. Kachalov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/moxart/moxart_head.S b/arch/arm/src/moxart/moxart_head.S index 10cd3f176ce..ebfa02a19a5 100644 --- a/arch/arm/src/moxart/moxart_head.S +++ b/arch/arm/src/moxart/moxart_head.S @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/moxart/moxart_head.S * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Anton D. Kachalov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c index 981e3319961..512b01414d3 100644 --- a/arch/arm/src/moxart/moxart_irq.c +++ b/arch/arm/src/moxart/moxart_irq.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/moxart/moxart_irq.c - * Driver for MoxaRT IRQ controller * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Anton D. Kachalov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -42,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/moxart/moxart_lowputc.S b/arch/arm/src/moxart/moxart_lowputc.S index 8f76264b2db..0989ebeedea 100644 --- a/arch/arm/src/moxart/moxart_lowputc.S +++ b/arch/arm/src/moxart/moxart_lowputc.S @@ -1,35 +1,20 @@ /************************************************************************** * moxart/moxart_lowputc.S * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Anton D. Kachalov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * **************************************************************************/ diff --git a/arch/arm/src/moxart/moxart_systemreset.c b/arch/arm/src/moxart/moxart_systemreset.c index 68b49b8426b..0caa26a261e 100644 --- a/arch/arm/src/moxart/moxart_systemreset.c +++ b/arch/arm/src/moxart/moxart_systemreset.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/moxart/moxart_systemreset.c * - * Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved. - * Author: Anton D. Kachalov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/moxart/moxart_timer.c b/arch/arm/src/moxart/moxart_timer.c index 9a5a8440436..17c94245654 100644 --- a/arch/arm/src/moxart/moxart_timer.c +++ b/arch/arm/src/moxart/moxart_timer.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/moxart/moxart_timer.c - * MoxaRT internal Timer Driver * - * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. - * Author: Anton D. Kachalov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs index b6b4970593e..b5091bc5c21 100644 --- a/arch/arm/src/nrf52/Make.defs +++ b/arch/arm/src/nrf52/Make.defs @@ -51,6 +51,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/nrf52/hardware/nrf52_rng.h b/arch/arm/src/nrf52/hardware/nrf52_rng.h index 466f86d4ae3..0ce4c70ca0a 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_rng.h +++ b/arch/arm/src/nrf52/hardware/nrf52_rng.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/nrf52/hardware/nrf52_rng.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Zhiqiang Li + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/nrf52/hardware/nrf52_utils.h b/arch/arm/src/nrf52/hardware/nrf52_utils.h index dd1e252c1c3..dc0910e168d 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_utils.h +++ b/arch/arm/src/nrf52/hardware/nrf52_utils.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/nrf52/hardware/nrf52_utils.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Zhiqiang Li + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/nrf52/nrf52832_errdata.c b/arch/arm/src/nrf52/nrf52832_errdata.c index 4f6b4c4e240..c7c0dab7129 100644 --- a/arch/arm/src/nrf52/nrf52832_errdata.c +++ b/arch/arm/src/nrf52/nrf52832_errdata.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/nrf52/nrf52832_errdata.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Levin Li + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/nrf52/nrf52_adc.c b/arch/arm/src/nrf52/nrf52_adc.c index f805e9aa9a2..47c2136b3e8 100644 --- a/arch/arm/src/nrf52/nrf52_adc.c +++ b/arch/arm/src/nrf52/nrf52_adc.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/nrf52/nrf52_gpiote.c b/arch/arm/src/nrf52/nrf52_gpiote.c index 09fb7435266..c7c9f0dd4ae 100644 --- a/arch/arm/src/nrf52/nrf52_gpiote.c +++ b/arch/arm/src/nrf52/nrf52_gpiote.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/nrf52/nrf52_i2c.c b/arch/arm/src/nrf52/nrf52_i2c.c index c189a53a629..8529c08ae09 100644 --- a/arch/arm/src/nrf52/nrf52_i2c.c +++ b/arch/arm/src/nrf52/nrf52_i2c.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/nrf52/nrf52_i2c_bitbang.c b/arch/arm/src/nrf52/nrf52_i2c_bitbang.c index 21b3d5c82d3..27aa2dd22d4 100644 --- a/arch/arm/src/nrf52/nrf52_i2c_bitbang.c +++ b/arch/arm/src/nrf52/nrf52_i2c_bitbang.c @@ -23,6 +23,7 @@ ****************************************************************************/ #include +#include #include #include #include diff --git a/arch/arm/src/nrf52/nrf52_idle.c b/arch/arm/src/nrf52/nrf52_idle.c index 28ec6d2d92f..3fe3c4456a4 100644 --- a/arch/arm/src/nrf52/nrf52_idle.c +++ b/arch/arm/src/nrf52/nrf52_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/nrf52/nrf52_irq.c b/arch/arm/src/nrf52/nrf52_irq.c index 29f476eeefc..047ba87ae95 100644 --- a/arch/arm/src/nrf52/nrf52_irq.c +++ b/arch/arm/src/nrf52/nrf52_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/nrf52/nrf52_lowputc.c b/arch/arm/src/nrf52/nrf52_lowputc.c index 56a980cd9d3..59d7d8a2d9a 100644 --- a/arch/arm/src/nrf52/nrf52_lowputc.c +++ b/arch/arm/src/nrf52/nrf52_lowputc.c @@ -25,6 +25,7 @@ #include #include +#include #include "arm_arch.h" #include "arm_internal.h" diff --git a/arch/arm/src/nrf52/nrf52_ppi.c b/arch/arm/src/nrf52/nrf52_ppi.c index cbe20e2b118..aecc8077df8 100644 --- a/arch/arm/src/nrf52/nrf52_ppi.c +++ b/arch/arm/src/nrf52/nrf52_ppi.c @@ -24,6 +24,8 @@ #include +#include + #include "arm_arch.h" #include "chip.h" #include "nrf52_ppi.h" diff --git a/arch/arm/src/nrf52/nrf52_radio.c b/arch/arm/src/nrf52/nrf52_radio.c index 88c084b74a8..e7ee9c04358 100644 --- a/arch/arm/src/nrf52/nrf52_radio.c +++ b/arch/arm/src/nrf52/nrf52_radio.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/arch/arm/src/nrf52/nrf52_radio.h b/arch/arm/src/nrf52/nrf52_radio.h index 2332738684d..3adc732dc30 100644 --- a/arch/arm/src/nrf52/nrf52_radio.h +++ b/arch/arm/src/nrf52/nrf52_radio.h @@ -134,7 +134,7 @@ struct nrf52_radio_pktcfg_s uint8_t s0_len; /* S0 length */ uint8_t s1_len; /* S1 length */ uint8_t ci_len; /* CI length */ - uint8_t pl_len; /* Preable lenght */ + uint8_t pl_len; /* Preamble length */ uint8_t term_len; /* TERM length */ bool crcinc; /* LENGTH includes CRC */ bool endian; /* On air endianess of packet: diff --git a/arch/arm/src/nrf52/nrf52_rng.c b/arch/arm/src/nrf52/nrf52_rng.c index 02921cea2a4..6fbb42867ff 100644 --- a/arch/arm/src/nrf52/nrf52_rng.c +++ b/arch/arm/src/nrf52/nrf52_rng.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/nrf52/nrf52_rng.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Levin Li + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/nrf52/nrf52_rtc.c b/arch/arm/src/nrf52/nrf52_rtc.c index ffbc45d549b..95dfddde900 100644 --- a/arch/arm/src/nrf52/nrf52_rtc.c +++ b/arch/arm/src/nrf52/nrf52_rtc.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/nrf52/nrf52_sdc.c b/arch/arm/src/nrf52/nrf52_sdc.c index 4ed107f449b..c46513e40dd 100644 --- a/arch/arm/src/nrf52/nrf52_sdc.c +++ b/arch/arm/src/nrf52/nrf52_sdc.c @@ -23,6 +23,10 @@ ****************************************************************************/ #include + +#include +#include + #include #include #include diff --git a/arch/arm/src/nrf52/nrf52_serial.c b/arch/arm/src/nrf52/nrf52_serial.c index 02377567e5a..0d6a524a58b 100644 --- a/arch/arm/src/nrf52/nrf52_serial.c +++ b/arch/arm/src/nrf52/nrf52_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/nrf52/nrf52_spi.c b/arch/arm/src/nrf52/nrf52_spi.c index 7bfff12acf3..f6d0e297620 100644 --- a/arch/arm/src/nrf52/nrf52_spi.c +++ b/arch/arm/src/nrf52/nrf52_spi.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/arch/arm/src/nrf52/nrf52_start.c b/arch/arm/src/nrf52/nrf52_start.c index 11bd545fac5..58edc37aef4 100644 --- a/arch/arm/src/nrf52/nrf52_start.c +++ b/arch/arm/src/nrf52/nrf52_start.c @@ -72,11 +72,6 @@ void __start(void) __attribute__ ((no_instrument_function)); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif - /**************************************************************************** * Name: nrf52_fpuconfig * @@ -164,47 +159,6 @@ static inline void nrf52_fpuconfig(void) # define nrf52_fpuconfig() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -311,15 +265,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/nrf52/nrf52_tickless_rtc.c b/arch/arm/src/nrf52/nrf52_tickless_rtc.c index ef313733b34..1950d68d971 100644 --- a/arch/arm/src/nrf52/nrf52_tickless_rtc.c +++ b/arch/arm/src/nrf52/nrf52_tickless_rtc.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/nrf52/nrf52_tim.c b/arch/arm/src/nrf52/nrf52_tim.c index 24b2c99524e..181bd56489a 100644 --- a/arch/arm/src/nrf52/nrf52_tim.c +++ b/arch/arm/src/nrf52/nrf52_tim.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/arm/src/nrf52/nrf52_tim_lowerhalf.c b/arch/arm/src/nrf52/nrf52_tim_lowerhalf.c index 3bfcd6c7dd3..f7f11b6342c 100644 --- a/arch/arm/src/nrf52/nrf52_tim_lowerhalf.c +++ b/arch/arm/src/nrf52/nrf52_tim_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/nrf52/nrf52_wdt_lowerhalf.c b/arch/arm/src/nrf52/nrf52_wdt_lowerhalf.c index 8ea7c3417d4..c4b743566c1 100644 --- a/arch/arm/src/nrf52/nrf52_wdt_lowerhalf.c +++ b/arch/arm/src/nrf52/nrf52_wdt_lowerhalf.c @@ -43,6 +43,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/nuc1xx/Make.defs b/arch/arm/src/nuc1xx/Make.defs index 85152e72dcc..cd19f8ec884 100644 --- a/arch/arm/src/nuc1xx/Make.defs +++ b/arch/arm/src/nuc1xx/Make.defs @@ -32,6 +32,7 @@ CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/nuc1xx/nuc_dumpgpio.c b/arch/arm/src/nuc1xx/nuc_dumpgpio.c index ddbebf05f78..4596a249e3a 100644 --- a/arch/arm/src/nuc1xx/nuc_dumpgpio.c +++ b/arch/arm/src/nuc1xx/nuc_dumpgpio.c @@ -25,6 +25,7 @@ #include #include +#include #include #include @@ -78,7 +79,7 @@ static const char g_portchar[NUC_GPIO_NPORTS] = * * Description: * Dump all GPIO registers associated with the provided pin description - * along with a descriptive messasge. + * along with a descriptive message. * ****************************************************************************/ diff --git a/arch/arm/src/nuc1xx/nuc_gpio.h b/arch/arm/src/nuc1xx/nuc_gpio.h index bc0cc19b134..a3c0745b6b2 100644 --- a/arch/arm/src/nuc1xx/nuc_gpio.h +++ b/arch/arm/src/nuc1xx/nuc_gpio.h @@ -227,7 +227,7 @@ bool nuc_gpioread(gpio_cfgset_t pinset); * * Description: * Dump all GPIO registers associated with the provided pin description - * along with a descriptive messasge. + * along with a descriptive message. * ****************************************************************************/ diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c index d5bbf293b0f..acbd88dcae9 100644 --- a/arch/arm/src/nuc1xx/nuc_idle.c +++ b/arch/arm/src/nuc1xx/nuc_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/nuc1xx/nuc_irq.c b/arch/arm/src/nuc1xx/nuc_irq.c index 64cddb73c38..54ae84fcf34 100644 --- a/arch/arm/src/nuc1xx/nuc_irq.c +++ b/arch/arm/src/nuc1xx/nuc_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c index fcf70273bc3..9f093df6436 100644 --- a/arch/arm/src/nuc1xx/nuc_serial.c +++ b/arch/arm/src/nuc1xx/nuc_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/rp2040/Make.defs b/arch/arm/src/rp2040/Make.defs index a640d43c700..a2d21c75d8b 100644 --- a/arch/arm/src/rp2040/Make.defs +++ b/arch/arm/src/rp2040/Make.defs @@ -36,6 +36,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif @@ -85,6 +86,10 @@ CHIP_CSRCS += rp2040_i2s.c CHIP_CSRCS += rp2040_i2s_pio.c endif +ifeq ($(CONFIG_USBDEV),y) +CHIP_CSRCS += rp2040_usbdev.c +endif + ifeq ($(CONFIG_RP2040_FLASH_BOOT),y) ifneq ($(PICO_SDK_PATH),) include chip/boot2/Make.defs diff --git a/arch/arm/src/rp2040/chip.h b/arch/arm/src/rp2040/chip.h index e9fc1b0326b..7850384dfbf 100644 --- a/arch/arm/src/rp2040/chip.h +++ b/arch/arm/src/rp2040/chip.h @@ -47,20 +47,37 @@ #include "hardware/rp2040_memorymap.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 3 +# include "hardware/rp2040_sio.h" +# include "rp2040_irq.h" +#endif /**************************************************************************** - * Public Types + * Macro Definitions ****************************************************************************/ +#ifdef __ASSEMBLY__ + /**************************************************************************** - * Public Data + * Name: setintstack + * + * Description: + * Set the current stack pointer to the "top" the correct interrupt stack + * for the current CPU. + * ****************************************************************************/ -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 3 + .macro setintstack, tmp1, tmp2 + ldr \tmp1, =RP2040_SIO_CPUID + ldr \tmp1, [\tmp1, #0] + lsl \tmp1, \tmp1, #2 + ldr \tmp2, =g_cpu_intstack_top + add \tmp2, \tmp2, \tmp1 + ldr \tmp2, [\tmp2, #0] + mov sp, \tmp2 /* sp = g_cpu_intstack_top[cpuid] */ + .endm +#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_RP2040_CHIP_H */ diff --git a/arch/arm/src/rp2040/hardware/rp2040_memorymap.h b/arch/arm/src/rp2040/hardware/rp2040_memorymap.h index 6405f6021ee..46019c91d91 100644 --- a/arch/arm/src/rp2040/hardware/rp2040_memorymap.h +++ b/arch/arm/src/rp2040/hardware/rp2040_memorymap.h @@ -88,6 +88,7 @@ #define RP2040_VREG_AND_CHIP_RESET_BASE 0x40064000 /* control and status for on-chip voltage regulator and chip level reset subsystem */ #define RP2040_TBMAN_BASE 0x4006c000 /* Testbench manager. Allows the programmer to know what platform their software is running on. */ #define RP2040_DMA_BASE 0x50000000 /* DMA with separate read and write masters */ +#define RP2040_USBCTRL_DPSRAM_BASE 0x50100000 /* USB Dual Port SRAM */ #define RP2040_USBCTRL_REGS_BASE 0x50110000 /* USB FS/LS controller device registers */ #define RP2040_PIO0_BASE 0x50200000 /* Programmable IO block */ #define RP2040_PIO1_BASE 0x50300000 /* Programmable IO block */ diff --git a/arch/arm/src/rp2040/hardware/rp2040_usbctrl_dpsram.h b/arch/arm/src/rp2040/hardware/rp2040_usbctrl_dpsram.h new file mode 100644 index 00000000000..787267ef78b --- /dev/null +++ b/arch/arm/src/rp2040/hardware/rp2040_usbctrl_dpsram.h @@ -0,0 +1,102 @@ +/**************************************************************************** + * arch/arm/src/rp2040/hardware/rp2040_usbctrl_dpsram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_USBCTRL_DPSRAM_H +#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_USBCTRL_DPSRAM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/rp2040_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define RP2040_USBCTRL_DPSRAM_SETUP_PACKET_OFFSET 0x000000 +#define RP2040_USBCTRL_DPSRAM_EP_IN_CTRL_OFFSET(n) (0x000008 + ((n) - 1) * 8) +#define RP2040_USBCTRL_DPSRAM_EP_OUT_CTRL_OFFSET(n) (0x00000c + ((n) - 1) * 8) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_OFFSET(n) (0x000008 + ((n) - 2) * 4) +#define RP2040_USBCTRL_DPSRAM_EP_IN_BUF_CTRL_OFFSET(n) (0x000080 + (n) * 8) +#define RP2040_USBCTRL_DPSRAM_EP_OUT_BUF_CTRL_OFFSET(n) (0x000084 + (n) * 8) +#define RP2040_USBCTRL_DPSRAM_EP_BUF_CTRL_OFFSET(n) (0x000080 + (n) * 4) +#define RP2040_USBCTRL_DPSRAM_EP0_BUF_0_OFFSET 0x000100 +#define RP2040_USBCTRL_DPSRAM_EP0_BUF_1_OFFSET 0x000140 +#define RP2040_USBCTRL_DPSRAM_DATA_BUF_OFFSET 0x000180 + +/* Register definitions *****************************************************/ + +#define RP2040_USBCTRL_DPSRAM_SETUP_PACKET (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_SETUP_PACKET_OFFSET) +#define RP2040_USBCTRL_DPSRAM_EP_IN_CTRL(n) (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_EP_IN_CTRL_OFFSET(n)) +#define RP2040_USBCTRL_DPSRAM_EP_OUT_CTRL(n) (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_EP_OUT_CTRL_OFFSET(n)) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL(n) (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_EP_CTRL_OFFSET(n)) +#define RP2040_USBCTRL_DPSRAM_EP_IN_BUF_CTRL(n) (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_EP_IN_BUF_CTRL_OFFSET(n)) +#define RP2040_USBCTRL_DPSRAM_EP_OUT_BUF_CTRL(n) (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_EP_OUT_BUF_CTRL_OFFSET(n)) +#define RP2040_USBCTRL_DPSRAM_EP_BUF_CTRL(n) (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_EP_BUF_CTRL_OFFSET(n)) +#define RP2040_USBCTRL_DPSRAM_EP0_BUF_0 (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_EP0_BUF_0_OFFSET) +#define RP2040_USBCTRL_DPSRAM_EP0_BUF_1 (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_EP0_BUF_1_OFFSET) +#define RP2040_USBCTRL_DPSRAM_DATA_BUF (RP2040_USBCTRL_DPSRAM_BASE + RP2040_USBCTRL_DPSRAM_DATA_BUF_OFFSET) + +/* Register bit definitions *************************************************/ + +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_ENABLE (1 << 31) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_DOUBLE_BUF (1 << 30) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_INT_1BUF (1 << 29) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_INT_2BUF (1 << 28) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT (26) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_MASK (0x3 << RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_CTRL (0 << RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_ISO (1 << RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_BULK (2 << RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_INTR (3 << RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_INT_STALL (1 << 17) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_INT_NAK (1 << 16) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_ADDR_SHIFT (6) +#define RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_ADDR_MASK (0xffc0) + +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_FULL1 (1 << 31) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LAST1 (1 << 30) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_SHIFT (29) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_MASK (1 << RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA0_PID1 (0 << RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA1_PID1 (1 << RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DBUF_OFF_128 (0 << 27) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DBUF_OFF_256 (1 << 27) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DBUF_OFF_512 (2 << 27) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DBUF_OFF_1024 (3 << 27) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_AVAIL1 (1 << 26) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN1_SHIFT (16) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN1_MASK (0x3ff << RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN1_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_FULL (1 << 15) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LAST (1 << 14) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_SHIFT (13) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_MASK (1 << RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA0_PID (0 << RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA1_PID (1 << RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_SHIFT) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_SEL (1 << 12) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_STALL (1 << 11) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_AVAIL (1 << 10) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_SHIFT (0) +#define RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_MASK (0x3ff << RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_SHIFT) + +#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_USBCTRL_DPSRAM_H */ diff --git a/arch/arm/src/rp2040/hardware/rp2040_usbctrl_regs.h b/arch/arm/src/rp2040/hardware/rp2040_usbctrl_regs.h new file mode 100644 index 00000000000..d29414280a2 --- /dev/null +++ b/arch/arm/src/rp2040/hardware/rp2040_usbctrl_regs.h @@ -0,0 +1,484 @@ +/**************************************************************************** + * arch/arm/src/rp2040/hardware/rp2040_usbctrl_regs.h + * + * Generated from rp2040.svd originally provided by + * Raspberry Pi (Trading) Ltd. + * + * Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_USBCTRL_REGS_H +#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_USBCTRL_REGS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/rp2040_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define RP2040_USBCTRL_REGS_ADDR_ENDP_OFFSET 0x000000 /* Device address and endpoint control */ +#define RP2040_USBCTRL_REGS_ADDR_ENDPN_OFFSET(n) (0x000004 + ((n) - 1) * 4) + /* Interrupt endpoint 1. Only valid for HOST mode. */ +#define RP2040_USBCTRL_REGS_MAIN_CTRL_OFFSET 0x000040 /* Main control register */ +#define RP2040_USBCTRL_REGS_SOF_WR_OFFSET 0x000044 /* Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. */ +#define RP2040_USBCTRL_REGS_SOF_RD_OFFSET 0x000048 /* Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_OFFSET 0x00004c /* SIE control register */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_OFFSET 0x000050 /* SIE status register */ +#define RP2040_USBCTRL_REGS_INT_EP_CTRL_OFFSET 0x000054 /* interrupt endpoint control register */ +#define RP2040_USBCTRL_REGS_BUFF_STATUS_OFFSET 0x000058 /* Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. */ +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_OFFSET 0x00005c /* Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. */ +#define RP2040_USBCTRL_REGS_EP_ABORT_OFFSET 0x000060 /* Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. */ +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_OFFSET 0x000064 /* Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. */ +#define RP2040_USBCTRL_REGS_EP_STALL_ARM_OFFSET 0x000068 /* Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. */ +#define RP2040_USBCTRL_REGS_NAK_POLL_OFFSET 0x00006c /* Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. */ +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_OFFSET 0x000070 /* Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. */ +#define RP2040_USBCTRL_REGS_USB_MUXING_OFFSET 0x000074 /* Where to connect the USB controller. Should be to_phy by default. */ +#define RP2040_USBCTRL_REGS_USB_PWR_OFFSET 0x000078 /* Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OFFSET 0x00007c /* This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_OFFSET 0x000080 /* Override enable for each control in usbphy_direct */ +#define RP2040_USBCTRL_REGS_USBPHY_TRIM_OFFSET 0x000084 /* Used to adjust trim values of USB phy pull down resistors. */ +#define RP2040_USBCTRL_REGS_INTR_OFFSET 0x00008c /* Raw Interrupts */ +#define RP2040_USBCTRL_REGS_INTE_OFFSET 0x000090 /* Interrupt Enable */ +#define RP2040_USBCTRL_REGS_INTF_OFFSET 0x000094 /* Interrupt Force */ +#define RP2040_USBCTRL_REGS_INTS_OFFSET 0x000098 /* Interrupt status after masking & forcing */ + +/* Register definitions *****************************************************/ + +#define RP2040_USBCTRL_REGS_ADDR_ENDP (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_ADDR_ENDP_OFFSET) +#define RP2040_USBCTRL_REGS_ADDR_ENDPN(n) (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_ADDR_ENDPN_OFFSET(n)) +#define RP2040_USBCTRL_REGS_MAIN_CTRL (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_MAIN_CTRL_OFFSET) +#define RP2040_USBCTRL_REGS_SOF_WR (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_SOF_WR_OFFSET) +#define RP2040_USBCTRL_REGS_SOF_RD (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_SOF_RD_OFFSET) +#define RP2040_USBCTRL_REGS_SIE_CTRL (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_SIE_CTRL_OFFSET) +#define RP2040_USBCTRL_REGS_SIE_STATUS (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_SIE_STATUS_OFFSET) +#define RP2040_USBCTRL_REGS_INT_EP_CTRL (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_INT_EP_CTRL_OFFSET) +#define RP2040_USBCTRL_REGS_BUFF_STATUS (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_BUFF_STATUS_OFFSET) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_OFFSET) +#define RP2040_USBCTRL_REGS_EP_ABORT (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_EP_ABORT_OFFSET) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_EP_ABORT_DONE_OFFSET) +#define RP2040_USBCTRL_REGS_EP_STALL_ARM (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_EP_STALL_ARM_OFFSET) +#define RP2040_USBCTRL_REGS_NAK_POLL (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_NAK_POLL_OFFSET) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_OFFSET) +#define RP2040_USBCTRL_REGS_USB_MUXING (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_USB_MUXING_OFFSET) +#define RP2040_USBCTRL_REGS_USB_PWR (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_USB_PWR_OFFSET) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_USBPHY_DIRECT_OFFSET) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_OFFSET) +#define RP2040_USBCTRL_REGS_USBPHY_TRIM (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_USBPHY_TRIM_OFFSET) +#define RP2040_USBCTRL_REGS_INTR (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_INTR_OFFSET) +#define RP2040_USBCTRL_REGS_INTE (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_INTE_OFFSET) +#define RP2040_USBCTRL_REGS_INTF (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_INTF_OFFSET) +#define RP2040_USBCTRL_REGS_INTS (RP2040_USBCTRL_REGS_BASE + RP2040_USBCTRL_REGS_INTS_OFFSET) + +/* Register bit definitions *************************************************/ + +#define RP2040_USBCTRL_REGS_ADDR_ENDP_ENDPOINT_SHIFT (16) /* Device endpoint to send data to. Only valid for HOST mode. */ +#define RP2040_USBCTRL_REGS_ADDR_ENDP_ENDPOINT_MASK (0x0f << RP2040_USBCTRL_REGS_ADDR_ENDP_ENDPOINT_SHIFT) +#define RP2040_USBCTRL_REGS_ADDR_ENDP_ADDRESS_MASK (0x7f) /* In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. */ + +#define RP2040_USBCTRL_REGS_ADDR_ENDPN_INTEP_PREAMBLE (1 << 26) /* Interrupt EP requires preamble (is a low speed device on a full speed hub) */ +#define RP2040_USBCTRL_REGS_ADDR_ENDPN_INTEP_DIR (1 << 25) /* Direction of the interrupt endpoint. In=0, Out=1 */ +#define RP2040_USBCTRL_REGS_ADDR_ENDPN_ENDPOINT_SHIFT (16) /* Endpoint number of the interrupt endpoint */ +#define RP2040_USBCTRL_REGS_ADDR_ENDPN_ENDPOINT_MASK (0x0f << RP2040_USBCTRL_REGS_ADDR_ENDP1_ENDPOINT_SHIFT) +#define RP2040_USBCTRL_REGS_ADDR_ENDPN_ADDRESS_MASK (0x7f) /* Device address */ + +#define RP2040_USBCTRL_REGS_MAIN_CTRL_SIM_TIMING (1 << 31) /* Reduced timings for simulation */ +#define RP2040_USBCTRL_REGS_MAIN_CTRL_HOST_NDEVICE (1 << 1) /* Device mode = 0, Host mode = 1 */ +#define RP2040_USBCTRL_REGS_MAIN_CTRL_CONTROLLER_EN (1 << 0) /* Enable controller */ + +#define RP2040_USBCTRL_REGS_SOF_WR_COUNT_MASK (0x7ff) + +#define RP2040_USBCTRL_REGS_SOF_RD_COUNT_MASK (0x7ff) + +#define RP2040_USBCTRL_REGS_SIE_CTRL_EP0_INT_STALL (1 << 31) /* Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_EP0_DOUBLE_BUF (1 << 30) /* Device: EP0 single buffered = 0, double buffered = 1 */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_EP0_INT_1BUF (1 << 29) /* Device: Set bit in BUFF_STATUS for every buffer completed on EP0 */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_EP0_INT_2BUF (1 << 28) /* Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_EP0_INT_NAK (1 << 27) /* Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_DIRECT_EN (1 << 26) /* Direct bus drive enable */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_DIRECT_DP (1 << 25) /* Direct control of DP */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_DIRECT_DM (1 << 24) /* Direct control of DM */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_TRANSCEIVER_PD (1 << 18) /* Power down bus transceiver */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_RPU_OPT (1 << 17) /* Device: Pull-up strength (0=1K2, 1=2k3) */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_PULLUP_EN (1 << 16) /* Device: Enable pull up resistor */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_PULLDOWN_EN (1 << 15) /* Host: Enable pull down resistors */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_RESET_BUS (1 << 13) /* Host: Reset bus */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_RESUME (1 << 12) /* Device: Remote wakeup. Device can initiate its own resume after suspend. */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_VBUS_EN (1 << 11) /* Host: Enable VBUS */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_KEEP_ALIVE_EN (1 << 10) /* Host: Enable keep alive packet (for low speed bus) */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_SOF_EN (1 << 9) /* Host: Enable SOF generation (for full speed bus) */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_SOF_SYNC (1 << 8) /* Host: Delay packet(s) until after SOF */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_PREAMBLE_EN (1 << 6) /* Host: Preable enable for LS device on FS hub */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_STOP_TRANS (1 << 4) /* Host: Stop transaction */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_RECEIVE_DATA (1 << 3) /* Host: Receive transaction (IN to host) */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_SEND_DATA (1 << 2) /* Host: Send transaction (OUT from host) */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_SEND_SETUP (1 << 1) /* Host: Send Setup packet */ +#define RP2040_USBCTRL_REGS_SIE_CTRL_START_TRANS (1 << 0) /* Host: Start transaction */ + +#define RP2040_USBCTRL_REGS_SIE_STATUS_DATA_SEQ_ERROR (1 << 31) /* Data Sequence Error. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_ACK_REC (1 << 30) /* ACK received. Raised by both host and device. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_STALL_REC (1 << 29) /* Host: STALL received */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_NAK_REC (1 << 28) /* Host: NAK received */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_RX_TIMEOUT (1 << 27) /* RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_RX_OVERFLOW (1 << 26) /* RX overflow is raised by the Serial RX engine if the incoming data is too fast. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_BIT_STUFF_ERROR (1 << 25) /* Bit Stuff Error. Raised by the Serial RX engine. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_CRC_ERROR (1 << 24) /* CRC Error. Raised by the Serial RX engine. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_BUS_RESET (1 << 19) /* Device: bus reset received */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_TRANS_COMPLETE (1 << 18) /* Transaction complete. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_SETUP_REC (1 << 17) /* Device: Setup packet received */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_CONNECTED (1 << 16) /* Device: connected */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_RESUME (1 << 11) /* Host: Device has initiated a remote resume. Device: host has initiated a resume. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_VBUS_OVER_CURR (1 << 10) /* VBUS over current detected */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_SPEED_SHIFT (8) /* Host: device speed. Disconnected = 00, LS = 01, FS = 10 */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_SPEED_MASK (0x03 << RP2040_USBCTRL_REGS_SIE_STATUS_SPEED_SHIFT) +#define RP2040_USBCTRL_REGS_SIE_STATUS_SUSPENDED (1 << 4) /* Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_LINE_STATE_SHIFT (2) /* USB bus line state */ +#define RP2040_USBCTRL_REGS_SIE_STATUS_LINE_STATE_MASK (0x03 << RP2040_USBCTRL_REGS_SIE_STATUS_LINE_STATE_SHIFT) +#define RP2040_USBCTRL_REGS_SIE_STATUS_VBUS_DETECTED (1 << 0) /* Device: VBUS Detected */ + +#define RP2040_USBCTRL_REGS_INT_EP_CTRL_INT_EP_ACTIVE_SHIFT (1) /* Host: Enable interrupt endpoint 1 -> 15 */ +#define RP2040_USBCTRL_REGS_INT_EP_CTRL_INT_EP_ACTIVE_MASK (0x7fff << RP2040_USBCTRL_REGS_INT_EP_CTRL_INT_EP_ACTIVE_SHIFT) + +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP15_OUT (1 << 31) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP15_IN (1 << 30) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP14_OUT (1 << 29) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP14_IN (1 << 28) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP13_OUT (1 << 27) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP13_IN (1 << 26) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP12_OUT (1 << 25) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP12_IN (1 << 24) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP11_OUT (1 << 23) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP11_IN (1 << 22) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP10_OUT (1 << 21) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP10_IN (1 << 20) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP9_OUT (1 << 19) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP9_IN (1 << 18) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP8_OUT (1 << 17) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP8_IN (1 << 16) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP7_OUT (1 << 15) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP7_IN (1 << 14) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP6_OUT (1 << 13) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP6_IN (1 << 12) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP5_OUT (1 << 11) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP5_IN (1 << 10) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP4_OUT (1 << 9) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP4_IN (1 << 8) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP3_OUT (1 << 7) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP3_IN (1 << 6) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP2_OUT (1 << 5) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP2_IN (1 << 4) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP1_OUT (1 << 3) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP1_IN (1 << 2) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP0_OUT (1 << 1) +#define RP2040_USBCTRL_REGS_BUFF_STATUS_EP0_IN (1 << 0) + +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP15_OUT (1 << 31) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP15_IN (1 << 30) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP14_OUT (1 << 29) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP14_IN (1 << 28) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP13_OUT (1 << 27) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP13_IN (1 << 26) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP12_OUT (1 << 25) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP12_IN (1 << 24) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP11_OUT (1 << 23) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP11_IN (1 << 22) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP10_OUT (1 << 21) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP10_IN (1 << 20) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP9_OUT (1 << 19) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP9_IN (1 << 18) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP8_OUT (1 << 17) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP8_IN (1 << 16) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP7_OUT (1 << 15) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP7_IN (1 << 14) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP6_OUT (1 << 13) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP6_IN (1 << 12) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP5_OUT (1 << 11) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP5_IN (1 << 10) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP4_OUT (1 << 9) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP4_IN (1 << 8) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP3_OUT (1 << 7) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP3_IN (1 << 6) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP2_OUT (1 << 5) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP2_IN (1 << 4) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP1_OUT (1 << 3) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP1_IN (1 << 2) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP0_OUT (1 << 1) +#define RP2040_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP0_IN (1 << 0) + +#define RP2040_USBCTRL_REGS_EP_ABORT_EP15_OUT (1 << 31) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP15_IN (1 << 30) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP14_OUT (1 << 29) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP14_IN (1 << 28) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP13_OUT (1 << 27) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP13_IN (1 << 26) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP12_OUT (1 << 25) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP12_IN (1 << 24) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP11_OUT (1 << 23) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP11_IN (1 << 22) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP10_OUT (1 << 21) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP10_IN (1 << 20) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP9_OUT (1 << 19) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP9_IN (1 << 18) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP8_OUT (1 << 17) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP8_IN (1 << 16) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP7_OUT (1 << 15) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP7_IN (1 << 14) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP6_OUT (1 << 13) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP6_IN (1 << 12) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP5_OUT (1 << 11) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP5_IN (1 << 10) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP4_OUT (1 << 9) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP4_IN (1 << 8) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP3_OUT (1 << 7) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP3_IN (1 << 6) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP2_OUT (1 << 5) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP2_IN (1 << 4) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP1_OUT (1 << 3) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP1_IN (1 << 2) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP0_OUT (1 << 1) +#define RP2040_USBCTRL_REGS_EP_ABORT_EP0_IN (1 << 0) + +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP15_OUT (1 << 31) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP15_IN (1 << 30) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP14_OUT (1 << 29) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP14_IN (1 << 28) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP13_OUT (1 << 27) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP13_IN (1 << 26) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP12_OUT (1 << 25) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP12_IN (1 << 24) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP11_OUT (1 << 23) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP11_IN (1 << 22) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP10_OUT (1 << 21) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP10_IN (1 << 20) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP9_OUT (1 << 19) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP9_IN (1 << 18) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP8_OUT (1 << 17) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP8_IN (1 << 16) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP7_OUT (1 << 15) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP7_IN (1 << 14) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP6_OUT (1 << 13) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP6_IN (1 << 12) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP5_OUT (1 << 11) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP5_IN (1 << 10) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP4_OUT (1 << 9) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP4_IN (1 << 8) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP3_OUT (1 << 7) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP3_IN (1 << 6) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP2_OUT (1 << 5) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP2_IN (1 << 4) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP1_OUT (1 << 3) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP1_IN (1 << 2) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP0_OUT (1 << 1) +#define RP2040_USBCTRL_REGS_EP_ABORT_DONE_EP0_IN (1 << 0) + +#define RP2040_USBCTRL_REGS_EP_STALL_ARM_EP0_OUT (1 << 1) +#define RP2040_USBCTRL_REGS_EP_STALL_ARM_EP0_IN (1 << 0) + +#define RP2040_USBCTRL_REGS_NAK_POLL_DELAY_FS_SHIFT (16) /* NAK polling interval for a full speed device */ +#define RP2040_USBCTRL_REGS_NAK_POLL_DELAY_FS_MASK (0x3ff << RP2040_USBCTRL_REGS_NAK_POLL_DELAY_FS_SHIFT) +#define RP2040_USBCTRL_REGS_NAK_POLL_DELAY_LS_MASK (0x3ff) /* NAK polling interval for a low speed device */ + +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP15_OUT (1 << 31) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP15_IN (1 << 30) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP14_OUT (1 << 29) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP14_IN (1 << 28) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP13_OUT (1 << 27) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP13_IN (1 << 26) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP12_OUT (1 << 25) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP12_IN (1 << 24) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP11_OUT (1 << 23) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP11_IN (1 << 22) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP10_OUT (1 << 21) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP10_IN (1 << 20) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP9_OUT (1 << 19) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP9_IN (1 << 18) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP8_OUT (1 << 17) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP8_IN (1 << 16) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP7_OUT (1 << 15) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP7_IN (1 << 14) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP6_OUT (1 << 13) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP6_IN (1 << 12) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP5_OUT (1 << 11) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP5_IN (1 << 10) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP4_OUT (1 << 9) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP4_IN (1 << 8) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP3_OUT (1 << 7) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP3_IN (1 << 6) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP2_OUT (1 << 5) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP2_IN (1 << 4) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP1_OUT (1 << 3) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP1_IN (1 << 2) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP0_OUT (1 << 1) +#define RP2040_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP0_IN (1 << 0) + +#define RP2040_USBCTRL_REGS_USB_MUXING_SOFTCON (1 << 3) +#define RP2040_USBCTRL_REGS_USB_MUXING_TO_DIGITAL_PAD (1 << 2) +#define RP2040_USBCTRL_REGS_USB_MUXING_TO_EXTPHY (1 << 1) +#define RP2040_USBCTRL_REGS_USB_MUXING_TO_PHY (1 << 0) + +#define RP2040_USBCTRL_REGS_USB_PWR_OVERCURR_DETECT_EN (1 << 5) +#define RP2040_USBCTRL_REGS_USB_PWR_OVERCURR_DETECT (1 << 4) +#define RP2040_USBCTRL_REGS_USB_PWR_VBUS_DETECT_OVERRIDE_EN (1 << 3) +#define RP2040_USBCTRL_REGS_USB_PWR_VBUS_DETECT (1 << 2) +#define RP2040_USBCTRL_REGS_USB_PWR_VBUS_EN_OVERRIDE_EN (1 << 1) +#define RP2040_USBCTRL_REGS_USB_PWR_VBUS_EN (1 << 0) + +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DM_OVV (1 << 22) /* DM over voltage */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DP_OVV (1 << 21) /* DP over voltage */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DM_OVCN (1 << 20) /* DM overcurrent */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DP_OVCN (1 << 19) /* DP overcurrent */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_RX_DM (1 << 18) /* DPM pin state */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_RX_DP (1 << 17) /* DPP pin state */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_RX_DD (1 << 16) /* Differential RX */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_TX_DIFFMODE (1 << 15) /* TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_TX_FSSLEW (1 << 14) /* TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_TX_PD (1 << 13) /* TX power down override (if override enable is set). 1 = powered down. */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_RX_PD (1 << 12) /* RX power down override (if override enable is set). 1 = powered down. */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_TX_DM (1 << 11) /* Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_TX_DP (1 << 10) /* Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_TX_DM_OE (1 << 9) /* Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_TX_DP_OE (1 << 8) /* Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DM_PULLDN_EN (1 << 6) /* DM pull down enable */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DM_PULLUP_EN (1 << 5) /* DM pull up enable */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DM_PULLUP_HISEL (1 << 4) /* Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DP_PULLDN_EN (1 << 2) /* DP pull down enable */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_EN (1 << 1) /* DP pull up enable */ +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_HISEL (1 << 0) /* Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 */ + +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN (1 << 15) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN (1 << 12) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN (1 << 11) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN (1 << 10) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN (1 << 9) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN (1 << 8) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN (1 << 7) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN (1 << 6) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN (1 << 5) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN (1 << 4) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN (1 << 3) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN (1 << 2) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN (1 << 1) +#define RP2040_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN (1 << 0) + +#define RP2040_USBCTRL_REGS_USBPHY_TRIM_DM_PULLDN_TRIM_SHIFT (8) /* Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required */ +#define RP2040_USBCTRL_REGS_USBPHY_TRIM_DM_PULLDN_TRIM_MASK (0x1f << RP2040_USBCTRL_REGS_USBPHY_TRIM_DM_PULLDN_TRIM_SHIFT) +#define RP2040_USBCTRL_REGS_USBPHY_TRIM_DP_PULLDN_TRIM_MASK (0x1f) /* Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required */ + +#define RP2040_USBCTRL_REGS_INTR_EP_STALL_NAK (1 << 19) /* Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */ +#define RP2040_USBCTRL_REGS_INTR_ABORT_DONE (1 << 18) /* Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. */ +#define RP2040_USBCTRL_REGS_INTR_DEV_SOF (1 << 17) /* Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD */ +#define RP2040_USBCTRL_REGS_INTR_SETUP_REQ (1 << 16) /* Device. Source: SIE_STATUS.SETUP_REC */ +#define RP2040_USBCTRL_REGS_INTR_DEV_RESUME_FROM_HOST (1 << 15) /* Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME */ +#define RP2040_USBCTRL_REGS_INTR_DEV_SUSPEND (1 << 14) /* Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED */ +#define RP2040_USBCTRL_REGS_INTR_DEV_CONN_DIS (1 << 13) /* Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */ +#define RP2040_USBCTRL_REGS_INTR_BUS_RESET (1 << 12) /* Source: SIE_STATUS.BUS_RESET */ +#define RP2040_USBCTRL_REGS_INTR_VBUS_DETECT (1 << 11) /* Source: SIE_STATUS.VBUS_DETECT */ +#define RP2040_USBCTRL_REGS_INTR_STALL (1 << 10) /* Source: SIE_STATUS.STALL_REC */ +#define RP2040_USBCTRL_REGS_INTR_ERROR_CRC (1 << 9) /* Source: SIE_STATUS.CRC_ERROR */ +#define RP2040_USBCTRL_REGS_INTR_ERROR_BIT_STUFF (1 << 8) /* Source: SIE_STATUS.BIT_STUFF_ERROR */ +#define RP2040_USBCTRL_REGS_INTR_ERROR_RX_OVERFLOW (1 << 7) /* Source: SIE_STATUS.RX_OVERFLOW */ +#define RP2040_USBCTRL_REGS_INTR_ERROR_RX_TIMEOUT (1 << 6) /* Source: SIE_STATUS.RX_TIMEOUT */ +#define RP2040_USBCTRL_REGS_INTR_ERROR_DATA_SEQ (1 << 5) /* Source: SIE_STATUS.DATA_SEQ_ERROR */ +#define RP2040_USBCTRL_REGS_INTR_BUFF_STATUS (1 << 4) /* Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. */ +#define RP2040_USBCTRL_REGS_INTR_TRANS_COMPLETE (1 << 3) /* Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. */ +#define RP2040_USBCTRL_REGS_INTR_HOST_SOF (1 << 2) /* Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD */ +#define RP2040_USBCTRL_REGS_INTR_HOST_RESUME (1 << 1) /* Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME */ +#define RP2040_USBCTRL_REGS_INTR_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ + +#define RP2040_USBCTRL_REGS_INTE_EP_STALL_NAK (1 << 19) /* Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */ +#define RP2040_USBCTRL_REGS_INTE_ABORT_DONE (1 << 18) /* Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. */ +#define RP2040_USBCTRL_REGS_INTE_DEV_SOF (1 << 17) /* Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD */ +#define RP2040_USBCTRL_REGS_INTE_SETUP_REQ (1 << 16) /* Device. Source: SIE_STATUS.SETUP_REC */ +#define RP2040_USBCTRL_REGS_INTE_DEV_RESUME_FROM_HOST (1 << 15) /* Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME */ +#define RP2040_USBCTRL_REGS_INTE_DEV_SUSPEND (1 << 14) /* Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED */ +#define RP2040_USBCTRL_REGS_INTE_DEV_CONN_DIS (1 << 13) /* Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */ +#define RP2040_USBCTRL_REGS_INTE_BUS_RESET (1 << 12) /* Source: SIE_STATUS.BUS_RESET */ +#define RP2040_USBCTRL_REGS_INTE_VBUS_DETECT (1 << 11) /* Source: SIE_STATUS.VBUS_DETECT */ +#define RP2040_USBCTRL_REGS_INTE_STALL (1 << 10) /* Source: SIE_STATUS.STALL_REC */ +#define RP2040_USBCTRL_REGS_INTE_ERROR_CRC (1 << 9) /* Source: SIE_STATUS.CRC_ERROR */ +#define RP2040_USBCTRL_REGS_INTE_ERROR_BIT_STUFF (1 << 8) /* Source: SIE_STATUS.BIT_STUFF_ERROR */ +#define RP2040_USBCTRL_REGS_INTE_ERROR_RX_OVERFLOW (1 << 7) /* Source: SIE_STATUS.RX_OVERFLOW */ +#define RP2040_USBCTRL_REGS_INTE_ERROR_RX_TIMEOUT (1 << 6) /* Source: SIE_STATUS.RX_TIMEOUT */ +#define RP2040_USBCTRL_REGS_INTE_ERROR_DATA_SEQ (1 << 5) /* Source: SIE_STATUS.DATA_SEQ_ERROR */ +#define RP2040_USBCTRL_REGS_INTE_BUFF_STATUS (1 << 4) /* Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. */ +#define RP2040_USBCTRL_REGS_INTE_TRANS_COMPLETE (1 << 3) /* Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. */ +#define RP2040_USBCTRL_REGS_INTE_HOST_SOF (1 << 2) /* Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD */ +#define RP2040_USBCTRL_REGS_INTE_HOST_RESUME (1 << 1) /* Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME */ +#define RP2040_USBCTRL_REGS_INTE_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ + +#define RP2040_USBCTRL_REGS_INTF_EP_STALL_NAK (1 << 19) /* Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */ +#define RP2040_USBCTRL_REGS_INTF_ABORT_DONE (1 << 18) /* Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. */ +#define RP2040_USBCTRL_REGS_INTF_DEV_SOF (1 << 17) /* Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD */ +#define RP2040_USBCTRL_REGS_INTF_SETUP_REQ (1 << 16) /* Device. Source: SIE_STATUS.SETUP_REC */ +#define RP2040_USBCTRL_REGS_INTF_DEV_RESUME_FROM_HOST (1 << 15) /* Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME */ +#define RP2040_USBCTRL_REGS_INTF_DEV_SUSPEND (1 << 14) /* Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED */ +#define RP2040_USBCTRL_REGS_INTF_DEV_CONN_DIS (1 << 13) /* Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */ +#define RP2040_USBCTRL_REGS_INTF_BUS_RESET (1 << 12) /* Source: SIE_STATUS.BUS_RESET */ +#define RP2040_USBCTRL_REGS_INTF_VBUS_DETECT (1 << 11) /* Source: SIE_STATUS.VBUS_DETECT */ +#define RP2040_USBCTRL_REGS_INTF_STALL (1 << 10) /* Source: SIE_STATUS.STALL_REC */ +#define RP2040_USBCTRL_REGS_INTF_ERROR_CRC (1 << 9) /* Source: SIE_STATUS.CRC_ERROR */ +#define RP2040_USBCTRL_REGS_INTF_ERROR_BIT_STUFF (1 << 8) /* Source: SIE_STATUS.BIT_STUFF_ERROR */ +#define RP2040_USBCTRL_REGS_INTF_ERROR_RX_OVERFLOW (1 << 7) /* Source: SIE_STATUS.RX_OVERFLOW */ +#define RP2040_USBCTRL_REGS_INTF_ERROR_RX_TIMEOUT (1 << 6) /* Source: SIE_STATUS.RX_TIMEOUT */ +#define RP2040_USBCTRL_REGS_INTF_ERROR_DATA_SEQ (1 << 5) /* Source: SIE_STATUS.DATA_SEQ_ERROR */ +#define RP2040_USBCTRL_REGS_INTF_BUFF_STATUS (1 << 4) /* Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. */ +#define RP2040_USBCTRL_REGS_INTF_TRANS_COMPLETE (1 << 3) /* Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. */ +#define RP2040_USBCTRL_REGS_INTF_HOST_SOF (1 << 2) /* Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD */ +#define RP2040_USBCTRL_REGS_INTF_HOST_RESUME (1 << 1) /* Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME */ +#define RP2040_USBCTRL_REGS_INTF_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ + +#define RP2040_USBCTRL_REGS_INTS_EP_STALL_NAK (1 << 19) /* Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */ +#define RP2040_USBCTRL_REGS_INTS_ABORT_DONE (1 << 18) /* Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. */ +#define RP2040_USBCTRL_REGS_INTS_DEV_SOF (1 << 17) /* Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD */ +#define RP2040_USBCTRL_REGS_INTS_SETUP_REQ (1 << 16) /* Device. Source: SIE_STATUS.SETUP_REC */ +#define RP2040_USBCTRL_REGS_INTS_DEV_RESUME_FROM_HOST (1 << 15) /* Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME */ +#define RP2040_USBCTRL_REGS_INTS_DEV_SUSPEND (1 << 14) /* Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED */ +#define RP2040_USBCTRL_REGS_INTS_DEV_CONN_DIS (1 << 13) /* Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */ +#define RP2040_USBCTRL_REGS_INTS_BUS_RESET (1 << 12) /* Source: SIE_STATUS.BUS_RESET */ +#define RP2040_USBCTRL_REGS_INTS_VBUS_DETECT (1 << 11) /* Source: SIE_STATUS.VBUS_DETECT */ +#define RP2040_USBCTRL_REGS_INTS_STALL (1 << 10) /* Source: SIE_STATUS.STALL_REC */ +#define RP2040_USBCTRL_REGS_INTS_ERROR_CRC (1 << 9) /* Source: SIE_STATUS.CRC_ERROR */ +#define RP2040_USBCTRL_REGS_INTS_ERROR_BIT_STUFF (1 << 8) /* Source: SIE_STATUS.BIT_STUFF_ERROR */ +#define RP2040_USBCTRL_REGS_INTS_ERROR_RX_OVERFLOW (1 << 7) /* Source: SIE_STATUS.RX_OVERFLOW */ +#define RP2040_USBCTRL_REGS_INTS_ERROR_RX_TIMEOUT (1 << 6) /* Source: SIE_STATUS.RX_TIMEOUT */ +#define RP2040_USBCTRL_REGS_INTS_ERROR_DATA_SEQ (1 << 5) /* Source: SIE_STATUS.DATA_SEQ_ERROR */ +#define RP2040_USBCTRL_REGS_INTS_BUFF_STATUS (1 << 4) /* Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. */ +#define RP2040_USBCTRL_REGS_INTS_TRANS_COMPLETE (1 << 3) /* Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. */ +#define RP2040_USBCTRL_REGS_INTS_HOST_SOF (1 << 2) /* Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD */ +#define RP2040_USBCTRL_REGS_INTS_HOST_RESUME (1 << 1) /* Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME */ +#define RP2040_USBCTRL_REGS_INTS_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ + +#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_USBCTRL_REGS_H */ diff --git a/arch/arm/src/rp2040/rp2040_dmac.c b/arch/arm/src/rp2040/rp2040_dmac.c index b50423fb26b..d68ae2e4539 100644 --- a/arch/arm/src/rp2040/rp2040_dmac.c +++ b/arch/arm/src/rp2040/rp2040_dmac.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/rp2040/rp2040_irq.c b/arch/arm/src/rp2040/rp2040_irq.c index 9e59307d7fc..8cdd8382791 100644 --- a/arch/arm/src/rp2040/rp2040_irq.c +++ b/arch/arm/src/rp2040/rp2040_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/rp2040/rp2040_spi.c b/arch/arm/src/rp2040/rp2040_spi.c index 9d1e527224d..273bb87a4e1 100644 --- a/arch/arm/src/rp2040/rp2040_spi.c +++ b/arch/arm/src/rp2040/rp2040_spi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/rp2040/rp2040_start.c b/arch/arm/src/rp2040/rp2040_start.c index 8952e680408..48fe9b07337 100644 --- a/arch/arm/src/rp2040/rp2040_start.c +++ b/arch/arm/src/rp2040/rp2040_start.c @@ -51,14 +51,6 @@ const uintptr_t g_idle_topstack = IDLE_STACK; -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static inline void go_nx_start(void *pv, unsigned int nbytes); -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -77,51 +69,6 @@ static inline void go_nx_start(void *pv, unsigned int nbytes); # define showprogress(c) #endif -/**************************************************************************** - * Name: go_nx_start - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static inline void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - * NOTE: this function must be inlined so that SRAM boot can work. - */ - - __asm__ __volatile__ - ( - "\t.global nx_start\n" - "\tlsr %1, %1, #2\n" /* %1 = nwords = nbytes >> 2 */ - "\tcmp %1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tmov r2, #3\n" - "\tadd %0, %0, #3\n" - "\tbic %0, r2\n" /* %0 = Aligned stackptr */ - "\tldr r2, =0xdeadbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - - "1:\n" /* Top of the loop */ - "\tstr r2, [%0, #0]\n" /* Save stack color word */ - "\tadd %0, %0, #4\n" /* Increment stackptr */ - "\tsub %1, %1, #1\n" /* %1 nwords-- */ - "\tcmp %1, #0\n" /* Check (nwords == 0) */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r2, #0\n" - "\tmov r14, r2\n" /* LR = return address (none) */ - "\tbl nx_start\n" /* Branch to nx_start */ - : - : "r" (pv), "r" (nbytes) - : "r2" - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -223,13 +170,7 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else nx_start(); -#endif /* Shouldn't get here */ diff --git a/arch/arm/src/rp2040/rp2040_uart.c b/arch/arm/src/rp2040/rp2040_uart.c index f37e073cfe0..0ab20212f8b 100644 --- a/arch/arm/src/rp2040/rp2040_uart.c +++ b/arch/arm/src/rp2040/rp2040_uart.c @@ -64,30 +64,36 @@ /* Get word length setting for the console */ -#if CONSOLE_BITS >= 5 && CONSOLE_BITS <= 8 - #define CONSOLE_LCR_WLS RP2040_UART_LCR_H_WLEN(CONSOLE_BITS) -#elif defined(HAVE_CONSOLE) - #error "Invalid CONFIG_UARTn_BITS setting for console " +#if defined(HAVE_CONSOLE) + #if CONSOLE_BITS >= 5 && CONSOLE_BITS <= 8 + #define CONSOLE_LCR_WLS RP2040_UART_LCR_H_WLEN(CONSOLE_BITS) + #else + #error "Invalid CONFIG_UARTn_BITS setting for console " + #endif #endif /* Get parity setting for the console */ -#if CONSOLE_PARITY == 0 - #define CONSOLE_LCR_PAR 0 -#elif CONSOLE_PARITY == 1 - #define CONSOLE_LCR_PAR (RP2040_UART_UARTLCR_H_PEN) -#elif CONSOLE_PARITY == 2 - #define CONSOLE_LCR_PAR (RP2040_UART_UARTLCR_H_PEN | RP2040_UART_UARTLCR_H_EPS) -#elif defined(HAVE_CONSOLE) - #error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE" +#if defined(HAVE_CONSOLE) + #if CONSOLE_PARITY == 0 + #define CONSOLE_LCR_PAR 0 + #elif CONSOLE_PARITY == 1 + #define CONSOLE_LCR_PAR (RP2040_UART_UARTLCR_H_PEN) + #elif CONSOLE_PARITY == 2 + #define CONSOLE_LCR_PAR (RP2040_UART_UARTLCR_H_PEN | RP2040_UART_UARTLCR_H_EPS) + #else + #error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE" + #endif #endif -/* Get stop-bit setting for the console and UART0/1/2 */ +/* Get stop-bit setting for the console and UART0/1 */ -#if CONSOLE_2STOP != 0 - #define CONSOLE_LCR_STOP RP2040_UART_UARTLCR_H_STP2 -#else - #define CONSOLE_LCR_STOP 0 +#if defined(HAVE_CONSOLE) + #if CONSOLE_2STOP != 0 + #define CONSOLE_LCR_STOP RP2040_UART_UARTLCR_H_STP2 + #else + #define CONSOLE_LCR_STOP 0 + #endif #endif /* LCR and FCR values for the console */ diff --git a/arch/arm/src/rp2040/rp2040_usbdev.c b/arch/arm/src/rp2040/rp2040_usbdev.c new file mode 100644 index 00000000000..12f6e2d23b2 --- /dev/null +++ b/arch/arm/src/rp2040/rp2040_usbdev.c @@ -0,0 +1,2162 @@ +/**************************************************************************** + * arch/arm/src/rp2040/rp2040_usbdev.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "arm_arch.h" +#include "arm_internal.h" +#include "rp2040_usbdev.h" + +#include "hardware/rp2040_resets.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE (CONFIG_USBDEV_EP0_MAXSIZE * 4) +#endif + +/* Debug ********************************************************************/ + +/* Trace error codes */ + +#define RP2040_TRACEERR_ALLOCFAIL 0x0001 +#define RP2040_TRACEERR_BINDFAILED 0x0002 +#define RP2040_TRACEERR_DRIVER 0x0003 +#define RP2040_TRACEERR_EPREAD 0x0004 +#define RP2040_TRACEERR_EWRITE 0x0005 +#define RP2040_TRACEERR_INVALIDPARMS 0x0006 +#define RP2040_TRACEERR_IRQREGISTRATION 0x0007 +#define RP2040_TRACEERR_NULLPACKET 0x0008 +#define RP2040_TRACEERR_NULLREQUEST 0x0009 +#define RP2040_TRACEERR_REQABORTED 0x000a +#define RP2040_TRACEERR_STALLEDCLRFEATURE 0x000b +#define RP2040_TRACEERR_STALLEDISPATCH 0x000c +#define RP2040_TRACEERR_STALLEDGETST 0x000d +#define RP2040_TRACEERR_STALLEDGETSTEP 0x000e +#define RP2040_TRACEERR_STALLEDGETSTRECIP 0x000f +#define RP2040_TRACEERR_STALLEDREQUEST 0x0010 +#define RP2040_TRACEERR_STALLEDSETFEATURE 0x0011 +#define RP2040_TRACEERR_TXREQLOST 0x0012 +#define RP2040_TRACEERR_RXREQLOST 0x0013 + +/* Trace interrupt codes */ + +#define RP2040_TRACEINTID_GETSTATUS 1 +#define RP2040_TRACEINTID_GETIFDEV 2 +#define RP2040_TRACEINTID_CLEARFEATURE 3 +#define RP2040_TRACEINTID_SETFEATURE 4 +#define RP2040_TRACEINTID_TESTMODE 5 +#define RP2040_TRACEINTID_SETADDRESS 6 +#define RP2040_TRACEINTID_GETSETDESC 7 +#define RP2040_TRACEINTID_GETSETIFCONFIG 8 +#define RP2040_TRACEINTID_SYNCHFRAME 9 +#define RP2040_TRACEINTID_DISPATCH 10 +#define RP2040_TRACEINTID_GETENDPOINT 11 +#define RP2040_TRACEINTID_HANDLEZLP 12 +#define RP2040_TRACEINTID_USBINTERRUPT 13 +#define RP2040_TRACEINTID_INTR_BUSRESET 14 +#define RP2040_TRACEINTID_INTR_BUFFSTAT 15 +#define RP2040_TRACEINTID_INTR_SETUP 16 +#define RP2040_TRACEINTID_EPOUTQEMPTY 17 + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(RP2040_TRACEERR_ALLOCFAIL), + TRACE_STR(RP2040_TRACEERR_BINDFAILED), + TRACE_STR(RP2040_TRACEERR_DRIVER), + TRACE_STR(RP2040_TRACEERR_EPREAD), + TRACE_STR(RP2040_TRACEERR_EWRITE), + TRACE_STR(RP2040_TRACEERR_INVALIDPARMS), + TRACE_STR(RP2040_TRACEERR_IRQREGISTRATION), + TRACE_STR(RP2040_TRACEERR_NULLPACKET), + TRACE_STR(RP2040_TRACEERR_NULLREQUEST), + TRACE_STR(RP2040_TRACEERR_REQABORTED), + TRACE_STR(RP2040_TRACEERR_STALLEDCLRFEATURE), + TRACE_STR(RP2040_TRACEERR_STALLEDISPATCH), + TRACE_STR(RP2040_TRACEERR_STALLEDGETST), + TRACE_STR(RP2040_TRACEERR_STALLEDGETSTEP), + TRACE_STR(RP2040_TRACEERR_STALLEDGETSTRECIP), + TRACE_STR(RP2040_TRACEERR_STALLEDREQUEST), + TRACE_STR(RP2040_TRACEERR_STALLEDSETFEATURE), + TRACE_STR(RP2040_TRACEERR_TXREQLOST), + TRACE_STR(RP2040_TRACEERR_RXREQLOST), + TRACE_STR_END +}; + +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(RP2040_TRACEINTID_GETSTATUS), + TRACE_STR(RP2040_TRACEINTID_GETIFDEV), + TRACE_STR(RP2040_TRACEINTID_CLEARFEATURE), + TRACE_STR(RP2040_TRACEINTID_SETFEATURE), + TRACE_STR(RP2040_TRACEINTID_TESTMODE), + TRACE_STR(RP2040_TRACEINTID_SETADDRESS), + TRACE_STR(RP2040_TRACEINTID_GETSETDESC), + TRACE_STR(RP2040_TRACEINTID_GETSETIFCONFIG), + TRACE_STR(RP2040_TRACEINTID_SYNCHFRAME), + TRACE_STR(RP2040_TRACEINTID_DISPATCH), + TRACE_STR(RP2040_TRACEINTID_GETENDPOINT), + TRACE_STR(RP2040_TRACEINTID_HANDLEZLP), + TRACE_STR(RP2040_TRACEINTID_USBINTERRUPT), + TRACE_STR(RP2040_TRACEINTID_INTR_BUSRESET), + TRACE_STR(RP2040_TRACEINTID_INTR_BUFFSTAT), + TRACE_STR(RP2040_TRACEINTID_INTR_SETUP), + TRACE_STR(RP2040_TRACEINTID_EPOUTQEMPTY), + TRACE_STR_END +}; +#endif + +/* Hardware interface *******************************************************/ + +/* Hardware dependent sizes and numbers */ + +#define RP2040_EP0MAXPACKET 64 /* EP0 max packet size */ +#define RP2040_BULKMAXPACKET 64 /* Bulk endpoint max packet */ +#define RP2040_INTRMAXPACKET 64 /* Interrupt endpoint max packet */ +#define RP2040_ISOMAXPACKET 1023 /* Isochronous max packet size */ + +/* USB endpoint number conversion macros + * EPINDEX: eplist[] index (the endpoint list in rp2040_usbdev_s) + * 0 - Endpoint 0 IN + * 1 - Endpoint 0 OUT + * 2 - Endpoint 1 (IN or OUT - depends on the endpoint configuration) + * 3 - Endpoint 2 (IN or OUT - depends on the endpoint configuration) + * 4 - Endpoint 3 (IN or OUT - depends on the endpoint configuration) + * : + * 15 - Endpoint 14 (IN or OUT - depends on the endpoint configuration) + * 16 - Endpoint 15 (IN or OUT - depends on the endpoint configuration) + * + * DPINDEX: RP2040 DPSRAM control index + * 0 - Endpoint 0 IN + * 1 - Endpoint 0 OUT + * 2 - Endpoint 1 IN + * 3 - Endpoint 1 OUT + * 4 - Endpoint 2 IN + * 5 - Endpoint 2 OUT + * : + * 30 - Endpoint 15 IN + * 31 - Endpoint 15 OUT + */ + +#define RP2040_EPINDEX(eplog) (USB_EPNO(eplog) == 0 ? \ + (USB_ISEPIN(eplog) ? 0 : 1) : \ + (USB_EPNO(eplog) + 1)) +#define RP2040_DPINDEX(eplog) (USB_EPNO(eplog) * 2 + USB_ISEPOUT(eplog)) +#define RP2040_DPTOEP(index) ((index) < 2 ? (index) : (index) / 2 + 1) + +#define RP2040_NENDPOINTS (16 + 1) /* EP0 IN, EP0 OUT, EP1..EP15 */ + +/* Request queue operations *************************************************/ + +#define rp2040_rqempty(ep) ((ep)->head == NULL) +#define rp2040_rqpeek(ep) ((ep)->head) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* USB Zero Length Packet type */ + +enum rp2040_zlp_e +{ + RP2040_ZLP_NONE = 0, /* Don't send/receive Zero Length Packet */ + RP2040_ZLP_IN_REPLY, /* Receive ZLP to reply IN transfer */ + RP2040_ZLP_OUT_REPLY, /* Send ZLP to reply OUT transfer */ +}; + +/* A container for a request so that the request make be retained in a list */ + +struct rp2040_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct rp2040_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct rp2040_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct rp2040_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* RP2040-specific fields */ + + struct rp2040_usbdev_s *dev; /* Reference to private driver data */ + struct rp2040_req_s *head; /* Request list for this endpoint */ + struct rp2040_req_s *tail; + uint8_t *data_buf; /* DPSRAM buffer address */ + uint32_t ep_ctrl; /* DPSRAM EP control register address */ + uint32_t buf_ctrl; /* DPSRAM buffer control register address */ + int next_pid; /* Next PID 0:DATA0, 1:DATA1 */ + uint8_t type; /* 0:cont, 1:iso, 2:bulk, 3:int */ + uint8_t epphy; /* Physical EP address */ + bool txnullpkt; /* Null packet needed at end of transfer */ + bool in; /* in = true, out = false */ + bool stalled; /* The EP is stalled */ + bool pending_stall; /* Pending stall request */ +}; + +/* This structure encapsulates the overall driver state */ + +struct rp2040_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to struct rp2040_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* RP2040-specific fields */ + + uint16_t next_offset; /* Unused DPSRAM buffer offset */ + uint8_t dev_addr; /* USB device address */ + enum rp2040_zlp_e zlp_stat; /* Pending EP0 ZLP status */ + uint16_t used; /* used epphy */ + bool stalled; + bool selfpowered; /* 1: Device is self powered */ + + /* EP0 SETUP data buffering. + * + * ctrl + * The 8-byte SETUP request is received on the EP0 OUT endpoint and is + * saved. + * + * ep0data + * For OUT SETUP requests, the SETUP data phase must also complete before + * the SETUP command can be processed. + * + * ep0datlen + * Length of OUT DATA received in ep0data[] + */ + + struct usb_ctrlreq_s ctrl; /* Last EP0 request */ + + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; + uint16_t ep0reqlen; + + /* The endpoint list */ + + struct rp2040_ep_s eplist[RP2040_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Request queue operations *************************************************/ + +static FAR struct +rp2040_req_s *rp2040_rqdequeue(FAR struct rp2040_ep_s *privep); +static void rp2040_rqenqueue(FAR struct rp2040_ep_s *privep, + FAR struct rp2040_req_s *req); + +/* Low level data transfers and request operations */ + +static void rp2040_update_buffer_control(FAR struct rp2040_ep_s *privep, + uint32_t and_mask, + uint32_t or_mask); +static int rp2040_epwrite(FAR struct rp2040_ep_s *privep, FAR uint8_t *buf, + uint16_t nbytes); +static int rp2040_epread(FAR struct rp2040_ep_s *privep, uint16_t nbytes); +static void rp2040_abortrequest(struct rp2040_ep_s *privep, + struct rp2040_req_s *privreq, + int16_t result); +static void rp2040_reqcomplete(struct rp2040_ep_s *privep, int16_t result); +static void rp2040_txcomplete(FAR struct rp2040_ep_s *privep); +static int rp2040_wrrequest(struct rp2040_ep_s *privep); +static void rp2040_rxcomplete(FAR struct rp2040_ep_s *privep); +static int rp2040_rdrequest(FAR struct rp2040_ep_s *privep); + +static void rp2040_handle_zlp(FAR struct rp2040_usbdev_s *priv); + +static void rp2040_cancelrequests(FAR struct rp2040_ep_s *privep); +static FAR struct rp2040_ep_s * + rp2040_epfindbyaddr(FAR struct rp2040_usbdev_s *priv, uint16_t eplog); +static void rp2040_dispatchrequest(FAR struct rp2040_usbdev_s *priv); +static void rp2040_ep0setup(FAR struct rp2040_usbdev_s *priv); + +/* Interrupt handling */ + +static void rp2040_usbintr_setup(FAR struct rp2040_usbdev_s *priv); +static void rp2040_usbintr_ep0out(FAR struct rp2040_usbdev_s *priv, + FAR struct rp2040_ep_s *privep); +static bool rp2040_usbintr_buffstat(FAR struct rp2040_usbdev_s *priv); +static void rp2040_usbintr_busreset(FAR struct rp2040_usbdev_s *priv); +static int rp2040_usbinterrupt(int irq, FAR void *context, FAR void *arg); + +/* Endpoint methods */ + +static int rp2040_epconfigure(FAR struct usbdev_ep_s *ep, + FAR const struct usb_epdesc_s *desc, + bool last); + +static int rp2040_epdisable(FAR struct usbdev_ep_s *ep); +static FAR struct usbdev_req_s *rp2040_epallocreq(FAR struct usbdev_ep_s + *ep); +static void rp2040_epfreereq(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req); +static int rp2040_epsubmit(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *privreq); +static int rp2040_epcancel(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *privreq); +static int rp2040_epstall_exec(FAR struct usbdev_ep_s *ep); +static int rp2040_epstall(FAR struct usbdev_ep_s *ep, bool resume); + +/* USB device controller methods */ + +static FAR struct usbdev_ep_s *rp2040_allocep(FAR struct usbdev_s *dev, + uint8_t epno, bool in, + uint8_t eptype); +static void rp2040_freeep(FAR struct usbdev_s *dev, + FAR struct usbdev_ep_s *ep); +static int rp2040_getframe(FAR struct usbdev_s *dev); +static int rp2040_wakeup(FAR struct usbdev_s *dev); +static int rp2040_selfpowered(FAR struct usbdev_s *dev, bool selfpowered); +static int rp2040_pullup(FAR struct usbdev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Endpoint methods */ + +static const struct usbdev_epops_s g_epops = +{ + .configure = rp2040_epconfigure, + .disable = rp2040_epdisable, + .allocreq = rp2040_epallocreq, + .freereq = rp2040_epfreereq, + .submit = rp2040_epsubmit, + .cancel = rp2040_epcancel, + .stall = rp2040_epstall, +}; + +/* USB controller device methods */ + +static const struct usbdev_ops_s g_devops = +{ + .allocep = rp2040_allocep, + .freeep = rp2040_freeep, + .getframe = rp2040_getframe, + .wakeup = rp2040_wakeup, + .selfpowered = rp2040_selfpowered, + .pullup = rp2040_pullup, +}; + +static struct rp2040_usbdev_s g_usbdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_rqdequeue + * + * Description: + * Remove a request from an endpoint request queue + * + ****************************************************************************/ + +static FAR struct +rp2040_req_s *rp2040_rqdequeue(FAR struct rp2040_ep_s *privep) +{ + FAR struct rp2040_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: rp2040_rqenqueue + * + * Description: + * Add a request from an endpoint request queue + * + ****************************************************************************/ + +static void rp2040_rqenqueue(FAR struct rp2040_ep_s *privep, + FAR struct rp2040_req_s *req) +{ + req->flink = NULL; + if (!privep->head) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } +} + +/**************************************************************************** + * Name: rp2040_update_buffer_control + * + * Description: + * Update DPSRAM buffer control register + * + ****************************************************************************/ + +static void rp2040_update_buffer_control(FAR struct rp2040_ep_s *privep, + uint32_t and_mask, + uint32_t or_mask) +{ + uint32_t value = 0; + + if (and_mask) + { + value = getreg32(privep->buf_ctrl) & and_mask; + } + + if (or_mask) + { + value |= or_mask; + } + + putreg32(value, privep->buf_ctrl); +} + +/**************************************************************************** + * Name: rp2040_epwrite + * + * Description: + * Endpoint write (IN) + * + ****************************************************************************/ + +static int rp2040_epwrite(FAR struct rp2040_ep_s *privep, FAR uint8_t *buf, + uint16_t nbytes) +{ + uint32_t val; + irqstate_t flags; + + /* Copy the transmit data into DPSRAM */ + + memcpy(privep->data_buf, buf, nbytes); + + val = nbytes | + RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_AVAIL | + RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_FULL | + (privep->next_pid ? + RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA1_PID : 0); + + privep->next_pid = 1 - privep->next_pid; /* Invert DATA0 <-> DATA1 */ + + /* Start the transfer */ + + flags = spin_lock_irqsave(NULL); + rp2040_update_buffer_control(privep, 0, val); + spin_unlock_irqrestore(NULL, flags); + + return nbytes; +} + +/**************************************************************************** + * Name: rp2040_epread + * + * Description: + * Endpoint read (OUT) + * + ****************************************************************************/ + +static int rp2040_epread(FAR struct rp2040_ep_s *privep, uint16_t nbytes) +{ + uint32_t val; + irqstate_t flags; + + val = nbytes | + RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_AVAIL | + (privep->next_pid ? + RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA1_PID : 0); + + privep->next_pid = 1 - privep->next_pid; /* Invert DATA0 <-> DATA1 */ + + /* Start the transfer */ + + flags = spin_lock_irqsave(NULL); + rp2040_update_buffer_control(privep, 0, val); + spin_unlock_irqrestore(NULL, flags); + + return OK; +} + +/**************************************************************************** + * Name: rp2040_abortrequest + * + * Description: + * Discard a request + * + ****************************************************************************/ + +static void rp2040_abortrequest(struct rp2040_ep_s *privep, + struct rp2040_req_s *privreq, + int16_t result) +{ + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_REQABORTED), + (uint16_t)privep->epphy); + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); +} + +/**************************************************************************** + * Name: rp2040_reqcomplete + * + * Description: + * Handle termination of a request. + * + ****************************************************************************/ + +static void rp2040_reqcomplete(struct rp2040_ep_s *privep, int16_t result) +{ + FAR struct rp2040_req_s *privreq; + int stalled = privep->stalled; + irqstate_t flags; + + /* Remove the completed request at the head of the endpoint request list */ + + flags = enter_critical_section(); + privreq = rp2040_rqdequeue(privep); + leave_critical_section(flags); + + if (privreq) + { + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + if (privep->epphy == 0) + { + privep->stalled = privep->dev->stalled; + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->flink = NULL; + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; + } +} + +/**************************************************************************** + * Name: rp2040_txcomplete + * + * Description: + * Transfer is completed. + * + ****************************************************************************/ + +static void rp2040_txcomplete(FAR struct rp2040_ep_s *privep) +{ + FAR struct rp2040_req_s *privreq; + + privreq = rp2040_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_TXREQLOST), privep->epphy); + } + else + { + privreq->req.xfrd += getreg32(privep->buf_ctrl) + & RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_MASK; + + if (privreq->req.xfrd >= privreq->req.len && !privep->txnullpkt) + { + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + privep->txnullpkt = 0; + rp2040_reqcomplete(privep, OK); + } + } + + rp2040_wrrequest(privep); +} + +/**************************************************************************** + * Name: rp2040_wrrequest + * + * Description: + * Send from the next queued write request + * + ****************************************************************************/ + +static int rp2040_wrrequest(struct rp2040_ep_s *privep) +{ + FAR struct rp2040_req_s *privreq; + uint8_t *buf; + int nbytes; + int bytesleft; + + /* Check the request from the head of the endpoint request queue */ + + privreq = rp2040_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_NULLREQUEST), 0); + return OK; + } + + /* Ignore any attempt to send a zero length packet on anything but EP0IN */ + + if (privreq->req.len == 0) + { + if (privep->epphy == 0) + { + rp2040_epwrite(privep, NULL, 0); + } + else + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_NULLPACKET), 0); + } + + return OK; + } + + /* Get the number of bytes left to be sent in the packet */ + + bytesleft = privreq->req.len - privreq->req.xfrd; + + /* Send the next packet if (1) there are more bytes to be sent, or + * (2) the last packet sent was exactly maxpacketsize (bytesleft == 0) + */ + + usbtrace(TRACE_WRITE(privep->epphy), (uint16_t)bytesleft); + if (bytesleft > 0 || privep->txnullpkt) + { + /* Try to send maxpacketsize -- unless we don't have that many + * bytes to send. + */ + + privep->txnullpkt = 0; + if (bytesleft > privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + } + else + { + nbytes = bytesleft; + if ((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + privep->txnullpkt = (bytesleft == privep->ep.maxpacket); + } + } + + /* Send the largest number of bytes that we can in this packet */ + + buf = privreq->req.buf + privreq->req.xfrd; + rp2040_epwrite(privep, buf, nbytes); + } + + return OK; +} + +/**************************************************************************** + * Name: rp2040_rxcomplete + * + * Description: + * Notify the upper layer and continue to next receive request. + * + ****************************************************************************/ + +static void rp2040_rxcomplete(FAR struct rp2040_ep_s *privep) +{ + FAR struct rp2040_req_s *privreq; + uint16_t nrxbytes; + + nrxbytes = getreg32(privep->buf_ctrl) + & RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_MASK; + + privreq = rp2040_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_RXREQLOST), privep->epphy); + return; + } + + memcpy(privreq->req.buf + privreq->req.xfrd, privep->data_buf, nrxbytes); + + privreq->req.xfrd += nrxbytes; + + if (privreq->req.xfrd >= privreq->req.len || + nrxbytes < privep->ep.maxpacket) + { + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + rp2040_reqcomplete(privep, OK); + } + + rp2040_rdrequest(privep); +} + +/**************************************************************************** + * Name: rp2040_rdrequest + * + * Description: + * Receive to the next queued read request + * + ****************************************************************************/ + +static int rp2040_rdrequest(FAR struct rp2040_ep_s *privep) +{ + FAR struct rp2040_req_s *privreq; + + /* Check the request from the head of the endpoint request queue */ + + privreq = rp2040_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_EPOUTQEMPTY), 0); + return OK; + } + + /* Receive the next packet */ + + usbtrace(TRACE_READ(privep->epphy), privreq->req.len); + + return rp2040_epread(privep, privreq->req.len); +} + +/**************************************************************************** + * Name: rp2040_handle_zlp + * + * Description: + * Handle Zero Length Packet to reply to the control transfer + * + ****************************************************************************/ + +static void rp2040_handle_zlp(FAR struct rp2040_usbdev_s *priv) +{ + FAR struct rp2040_ep_s *privep = NULL; + + switch (priv->zlp_stat) + { + case RP2040_ZLP_NONE: + return; + + case RP2040_ZLP_IN_REPLY: + + /* Reply to control IN : receive ZLP from EP0 (0x00) */ + + privep = &priv->eplist[RP2040_EPINDEX(0x00)]; + break; + + case RP2040_ZLP_OUT_REPLY: + + /* Reply to control OUT : send ZLP to EP0 (0x80) */ + + privep = &priv->eplist[RP2040_EPINDEX(0x80)]; + break; + + default: + DEBUGASSERT(0); + } + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_HANDLEZLP), privep->ep.eplog); + privep->next_pid = 1; /* ZLP is always sent by DATA1 packet */ + + if (priv->zlp_stat == RP2040_ZLP_IN_REPLY) + { + rp2040_epread(privep, 0); + } + else + { + rp2040_epwrite(privep, NULL, 0); + } + + priv->zlp_stat = RP2040_ZLP_NONE; +} + +/**************************************************************************** + * Name: rp2040_cancelrequests + * + * Description: + * Cancel all pending requests for an endpoint + * + ****************************************************************************/ + +static void rp2040_cancelrequests(FAR struct rp2040_ep_s *privep) +{ + while (!rp2040_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(privep->epphy), + (rp2040_rqpeek(privep))->req.xfrd); + rp2040_reqcomplete(privep, -ESHUTDOWN); + } +} + +/**************************************************************************** + * Name: rp2040_epfindbyaddr + * + * Description: + * Find the physical endpoint structure corresponding to a logic endpoint + * address + * + ****************************************************************************/ + +static FAR struct rp2040_ep_s * +rp2040_epfindbyaddr(FAR struct rp2040_usbdev_s *priv, uint16_t eplog) +{ + return &priv->eplist[RP2040_EPINDEX(eplog)]; +} + +/**************************************************************************** + * Name: rp2040_dispatchrequest + * + * Description: + * Provide unhandled setup actions to the class driver + * + ****************************************************************************/ + +static void rp2040_dispatchrequest(FAR struct rp2040_usbdev_s *priv) +{ + int ret; + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_DISPATCH), 0); + if (priv && priv->driver) + { + ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, + priv->ep0data, priv->ep0datlen); + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_STALLEDISPATCH), + priv->ctrl.req); + priv->stalled = true; + } + + if (!priv->stalled && USB_REQ_ISOUT(priv->ctrl.type)) + { + priv->zlp_stat = RP2040_ZLP_NONE; /* already sent */ + } + } +} + +/**************************************************************************** + * Name: rp2040_ep0setup + * + * Description: + * USB control EP setup event + * + ****************************************************************************/ + +static void rp2040_ep0setup(FAR struct rp2040_usbdev_s *priv) +{ + FAR struct rp2040_ep_s *ep0 = &priv->eplist[0]; + FAR struct rp2040_ep_s *privep; + uint16_t index; + uint16_t value; + uint16_t len; + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_INTR_SETUP), 0); + + /* Assume NOT stalled */ + + ep0->stalled = 0; + priv->stalled = 0; + + /* Extract the little-endian 16-bit values to host order */ + + index = GETUINT16(priv->ctrl.index); + value = GETUINT16(priv->ctrl.value); + len = GETUINT16(priv->ctrl.len); + + uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", + priv->ctrl.type, priv->ctrl.req, value, index, len); + + /* Dispatch any non-standard requests */ + + if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + rp2040_dispatchrequest(priv); + } + else + { + /* Handle standard request. Pick off the things of interest to the + * USB device controller driver; pass what is left to the class driver + */ + + switch (priv->ctrl.req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; + * recipient = device, + * interface, + * endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_GETSTATUS), + priv->ctrl.req); + + if (len != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || + value != 0) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_STALLEDGETST), + priv->ctrl.req); + priv->stalled = true; + } + else + { + switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + usbtrace(TRACE_INTDECODE( + RP2040_TRACEINTID_GETENDPOINT), + 0); + privep = rp2040_epfindbyaddr(priv, index); + if (!privep) + { + usbtrace( + TRACE_DEVERROR( + RP2040_TRACEERR_STALLEDGETSTEP), + priv->ctrl.type); + priv->stalled = true; + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + case USB_REQ_RECIPIENT_INTERFACE: + usbtrace(TRACE_INTDECODE( + RP2040_TRACEINTID_GETIFDEV), + 0); + break; + + default: + { + usbtrace(TRACE_DEVERROR( + RP2040_TRACEERR_STALLEDGETSTRECIP), + priv->ctrl.type); + priv->stalled = true; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to device; + * recipient = device, + * interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_CLEARFEATURE), + (uint16_t)priv->ctrl.req); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + rp2040_dispatchrequest(priv); + } + else if (value == USB_FEATURE_ENDPOINTHALT && + len == 0 && + (privep = rp2040_epfindbyaddr(priv, index)) != NULL) + { + rp2040_epstall(&privep->ep, true); + rp2040_epwrite(ep0, NULL, 0); + } + else + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_STALLEDCLRFEATURE), + priv->ctrl.type); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; + * recipient = device, + * interface, + * endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_SETFEATURE), + priv->ctrl.req); + if (priv->ctrl.type == USB_REQ_RECIPIENT_DEVICE && + value == USB_FEATURE_TESTMODE) + { + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_TESTMODE), + index); + } + else if (priv->ctrl.type != USB_REQ_RECIPIENT_ENDPOINT) + { + rp2040_dispatchrequest(priv); + } + else if (value == USB_FEATURE_ENDPOINTHALT && len == 0 && + (privep = rp2040_epfindbyaddr(priv, index)) != NULL) + { + rp2040_epstall(&privep->ep, true); + rp2040_epwrite(ep0, NULL, 0); + } + else + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_STALLEDSETFEATURE), + priv->ctrl.type); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_SETADDRESS), value); + priv->dev_addr = value & 0xff; + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_GETSETDESC), + priv->ctrl.req); + rp2040_dispatchrequest(priv); + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_GETSETIFCONFIG), + priv->ctrl.req); + rp2040_dispatchrequest(priv); + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_SYNCHFRAME), 0); + break; + } + + default: + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_STALLEDREQUEST), + priv->ctrl.req); + priv->stalled = true; + } + break; + } + } + + /* Check if the setup processing resulted in a STALL */ + + if (priv->stalled) + { + rp2040_epstall(&priv->eplist[0].ep, false); + rp2040_epstall(&priv->eplist[1].ep, false); + } + else if (priv->zlp_stat != RP2040_ZLP_NONE) + { + rp2040_handle_zlp(priv); + } +} + +/**************************************************************************** + * Name: rp2040_usbintr_setup + * + * Description: + * Handle USB SETUP_REQ interrupt + * + ****************************************************************************/ + +static void rp2040_usbintr_setup(FAR struct rp2040_usbdev_s *priv) +{ + uint16_t len; + + /* Read USB control request data */ + + memcpy(&priv->ctrl, (void *)RP2040_USBCTRL_DPSRAM_SETUP_PACKET, + USB_SIZEOF_CTRLREQ); + len = GETUINT16(priv->ctrl.len); + + /* Reset PID and stall status in setup stage */ + + priv->eplist[0].next_pid = 1; + priv->eplist[1].next_pid = 1; + priv->eplist[0].stalled = false; + priv->eplist[1].stalled = false; + + /* ZLP type in status stage */ + + priv->zlp_stat = USB_REQ_ISIN(priv->ctrl.type) ? RP2040_ZLP_IN_REPLY : + RP2040_ZLP_OUT_REPLY; + + if (USB_REQ_ISOUT(priv->ctrl.type) && len != priv->ep0datlen) + { + /* Receive the subsequent OUT data for the setup */ + + priv->ep0reqlen = len; + rp2040_epread(&priv->eplist[RP2040_EPINDEX(0x00)], len); + } + else + { + /* Start the setup */ + + priv->ep0reqlen = 0; + rp2040_ep0setup(priv); + } +} + +/**************************************************************************** + * Name: rp2040_usbintr_ep0out + * + * Description: + * Handle the end of EP0OUT data transfer + * + ****************************************************************************/ + +static void rp2040_usbintr_ep0out(FAR struct rp2040_usbdev_s *priv, + FAR struct rp2040_ep_s *privep) +{ + int len; + + len = getreg32(privep->buf_ctrl) + & RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_MASK; + + if (len == 0) + { + privep->next_pid = 1; + priv->ep0datlen = 0; + return; + } + + memcpy(priv->ep0data + priv->ep0datlen, privep->data_buf, len); + priv->ep0datlen += len; + + if (priv->ep0datlen == priv->ep0reqlen) + { + priv->zlp_stat = RP2040_ZLP_NONE; + rp2040_ep0setup(priv); + priv->ep0datlen = 0; + } + else + { + rp2040_epread(privep, RP2040_EP0MAXPACKET); + } +} + +/**************************************************************************** + * Name: rp2040_usbintr_buffstat + * + * Description: + * Handle USB BUFF_STATUS interrupt + * + ****************************************************************************/ + +static bool rp2040_usbintr_buffstat(FAR struct rp2040_usbdev_s *priv) +{ + uint32_t stat = getreg32(RP2040_USBCTRL_REGS_BUFF_STATUS); + uint32_t bit; + int i; + FAR struct rp2040_ep_s *privep; + + if (stat == 0) + { + return false; + } + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_INTR_BUFFSTAT), stat & 0xffff); + + bit = 1; + for (i = 0; i < 32 && stat != 0; i++) + { + if (stat & bit) + { + clrbits_reg32(bit, RP2040_USBCTRL_REGS_BUFF_STATUS); + privep = &priv->eplist[RP2040_DPTOEP(i)]; + + if (i == 1) + { + rp2040_usbintr_ep0out(priv, privep); + } + else + { + if (i == 0 && priv->dev_addr != 0) + { + putreg32(priv->dev_addr, RP2040_USBCTRL_REGS_ADDR_ENDP); + priv->dev_addr = 0; + } + + if (privep->in) + { + if (!rp2040_rqempty(privep)) + { + rp2040_txcomplete(privep); + } + else if (privep->pending_stall) + { + rp2040_epstall_exec(&privep->ep); + } + } + else + { + rp2040_rxcomplete(privep); + } + } + + stat &= ~bit; + } + + bit <<= 1; + } + + return true; +} + +/**************************************************************************** + * Name: rp2040_usbintr_busreset + * + * Description: + * Handle USB BUS_RESET interrupt + * + ****************************************************************************/ + +static void rp2040_usbintr_busreset(FAR struct rp2040_usbdev_s *priv) +{ + int i; + + usbtrace(TRACE_INTDECODE(RP2040_TRACEINTID_INTR_BUSRESET), 0); + + putreg32(0, RP2040_USBCTRL_REGS_ADDR_ENDP); + priv->dev_addr = 0; + priv->zlp_stat = RP2040_ZLP_NONE; + priv->next_offset = RP2040_USBCTRL_DPSRAM_DATA_BUF_OFFSET; + + for (i = 0; i < RP2040_NENDPOINTS; i++) + { + FAR struct rp2040_ep_s *privep = &g_usbdev.eplist[i]; + + rp2040_cancelrequests(privep); + } + + rp2040_pullup(&g_usbdev.usbdev, false); + if (g_usbdev.driver) + { + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + } + + clrbits_reg32(RP2040_USBCTRL_REGS_SIE_STATUS_BUS_RESET, + RP2040_USBCTRL_REGS_SIE_STATUS); +} + +/**************************************************************************** + * Name: rp2040_usbinterrupt + * + * Description: + * USB interrupt handler + * + ****************************************************************************/ + +static int rp2040_usbinterrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct rp2040_usbdev_s *priv = (FAR struct rp2040_usbdev_s *)arg; + uint32_t stat; + + stat = getreg32(RP2040_USBCTRL_REGS_INTS); + + usbtrace(TRACE_INTENTRY(RP2040_TRACEINTID_USBINTERRUPT), 0); + + if (stat & RP2040_USBCTRL_REGS_INTR_BUFF_STATUS) + { + while (rp2040_usbintr_buffstat(priv)) + ; + } + + if (stat & RP2040_USBCTRL_REGS_INTR_SETUP_REQ) + { + clrbits_reg32(RP2040_USBCTRL_REGS_SIE_STATUS_SETUP_REC, + RP2040_USBCTRL_REGS_SIE_STATUS); + + rp2040_usbintr_setup(priv); + } + + if (stat & RP2040_USBCTRL_REGS_INTR_BUS_RESET) + { + clrbits_reg32(RP2040_USBCTRL_REGS_SIE_STATUS_BUS_RESET, + RP2040_USBCTRL_REGS_SIE_STATUS); + + rp2040_usbintr_busreset(priv); + } + + usbtrace(TRACE_INTEXIT(RP2040_TRACEINTID_USBINTERRUPT), 0); + + return OK; +} + +/**************************************************************************** + * Endpoint Methods + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_epconfigure + * + * Description: + * Configure endpoint, making it usable + * + * Input Parameters: + * ep - the struct usbdev_ep_s instance obtained from allocep() + * desc - A struct usb_epdesc_s instance describing the endpoint + * last - true if this is the last endpoint to be configured. Some + * hardware needs to take special action when all of the endpoints + * have been configured. + * + ****************************************************************************/ + +static int rp2040_epconfigure(FAR struct usbdev_ep_s *ep, + FAR const struct usb_epdesc_s *desc, bool last) +{ + FAR struct rp2040_ep_s *privep = (FAR struct rp2040_ep_s *)ep; + FAR struct rp2040_usbdev_s *priv = privep->dev; + int eptype; + uint16_t maxpacket; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + DEBUGASSERT(desc->addr == ep->eplog); + + eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; + maxpacket = GETUINT16(desc->mxpacketsize); + + uinfo("config: EP%d %s %d maxpacket=%d\n", privep->epphy, + privep->in ? "IN" : "OUT", eptype, maxpacket); + + if (desc) + { + privep->ep.maxpacket = GETUINT16(desc->mxpacketsize); + } + + if (privep->epphy != 0) + { + /* Configure the EP data buffer address + * (No need for EP0 because it has the dedicated buffer) + */ + + privep->data_buf = (uint8_t *)(RP2040_USBCTRL_DPSRAM_BASE + + priv->next_offset); + priv->next_offset = + (priv->next_offset + privep->ep.maxpacket + 63) & ~63; + + /* Enable EP */ + + putreg32(RP2040_USBCTRL_DPSRAM_EP_CTRL_ENABLE | + RP2040_USBCTRL_DPSRAM_EP_CTRL_INT_1BUF | + (eptype << RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT) | + ((uint32_t)privep->data_buf & + RP2040_USBCTRL_DPSRAM_EP_CTRL_EP_ADDR_MASK), + privep->ep_ctrl); + } + + return OK; +} + +/**************************************************************************** + * Name: rp2040_epdisable + * + * Description: + * The endpoint will no longer be used + * + ****************************************************************************/ + +static int rp2040_epdisable(FAR struct usbdev_ep_s *ep) +{ + FAR struct rp2040_ep_s *privep = (FAR struct rp2040_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPDISABLE, privep->epphy); + uinfo("EP%d\n", privep->epphy); + + flags = enter_critical_section(); + + privep->ep.maxpacket = 64; + privep->stalled = false; + privep->next_pid = 0; + putreg32(0, privep->buf_ctrl); + + /* Cancel all queued requests */ + + rp2040_cancelrequests(privep); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: rp2040_epallocreq + * + * Description: + * Allocate an I/O request + * + ****************************************************************************/ + +static FAR struct usbdev_req_s *rp2040_epallocreq(FAR struct usbdev_ep_s *ep) +{ + FAR struct rp2040_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + return NULL; + } +#endif + + usbtrace(TRACE_EPALLOCREQ, ((FAR struct rp2040_ep_s *)ep)->epphy); + + privreq = (FAR struct rp2040_req_s *) + kmm_malloc(sizeof(struct rp2040_req_s)); + + if (!privreq) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct rp2040_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: rp2040_epfreereq + * + * Description: + * Free an I/O request + * + ****************************************************************************/ + +static void rp2040_epfreereq(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) +{ + FAR struct rp2040_req_s *privreq = (FAR struct rp2040_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + + usbtrace(TRACE_EPFREEREQ, ((FAR struct rp2040_ep_s *)ep)->epphy); + kmm_free(privreq); +} + +/**************************************************************************** + * Name: rp2040_epsubmit + * + * Description: + * Submit an I/O request to the endpoint + * + ****************************************************************************/ + +static int rp2040_epsubmit(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) +{ + FAR struct rp2040_req_s *privreq = (FAR struct rp2040_req_s *)req; + FAR struct rp2040_ep_s *privep = (FAR struct rp2040_ep_s *)ep; + irqstate_t flags; + int ret = OK; + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, privep->ep.eplog); + + req->result = -EINPROGRESS; + req->xfrd = 0; + + flags = enter_critical_section(); + + if (privep->stalled && privep->in) + { + rp2040_abortrequest(privep, privreq, -EBUSY); + ret = -EBUSY; + } + + /* Handle IN (device-to-host) requests */ + + else if (privep->in) + { + /* Add the new request to the request queue for the IN endpoint */ + + bool empty = rp2040_rqempty(privep); + + rp2040_rqenqueue(privep, privreq); + usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); + + if (empty) + { + rp2040_wrrequest(privep); + } + } + + /* Handle OUT (host-to-device) requests */ + + else + { + /* Add the new request to the request queue for the OUT endpoint */ + + bool empty = rp2040_rqempty(privep); + + privep->txnullpkt = 0; + rp2040_rqenqueue(privep, privreq); + usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); + + /* This there a incoming data pending the availability of a request? */ + + if (empty) + { + ret = rp2040_rdrequest(privep); + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: rp2040_epcancel + * + * Description: + * Cancel an I/O request previously sent to an endpoint + * + ****************************************************************************/ + +static int rp2040_epcancel(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) +{ + FAR struct rp2040_ep_s *privep = (FAR struct rp2040_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPCANCEL, privep->epphy); + + /* Remove request from req_queue */ + + flags = enter_critical_section(); + rp2040_cancelrequests(privep); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: rp2040_epstall_exec + * + * Description: + * Stall endpoint immediately + * + ****************************************************************************/ + +static int rp2040_epstall_exec(FAR struct usbdev_ep_s *ep) +{ + FAR struct rp2040_ep_s *privep = (FAR struct rp2040_ep_s *)ep; + irqstate_t flags; + + usbtrace(TRACE_EPSTALL, privep->epphy); + + flags = spin_lock_irqsave(NULL); + + if (privep->epphy == 0) + { + setbits_reg32(privep->in ? + RP2040_USBCTRL_REGS_EP_STALL_ARM_EP0_IN : + RP2040_USBCTRL_REGS_EP_STALL_ARM_EP0_OUT, + RP2040_USBCTRL_REGS_EP_STALL_ARM); + } + + rp2040_update_buffer_control(privep, + 0, + RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_STALL); + + privep->pending_stall = false; + + spin_unlock_irqrestore(NULL, flags); + return OK; +} + +/**************************************************************************** + * Name: rp2040_epstall + * + * Description: + * Stall or resume and endpoint + * + ****************************************************************************/ + +static int rp2040_epstall(FAR struct usbdev_ep_s *ep, bool resume) +{ + FAR struct rp2040_ep_s *privep = (FAR struct rp2040_ep_s *)ep; + FAR struct rp2040_usbdev_s *priv = privep->dev; + irqstate_t flags; + + flags = spin_lock_irqsave(NULL); + + if (resume) + { + usbtrace(TRACE_EPRESUME, privep->epphy); + privep->stalled = false; + if (privep->epphy == 0) + { + clrbits_reg32(privep->in ? + RP2040_USBCTRL_REGS_EP_STALL_ARM_EP0_IN : + RP2040_USBCTRL_REGS_EP_STALL_ARM_EP0_OUT, + RP2040_USBCTRL_REGS_EP_STALL_ARM); + } + + rp2040_update_buffer_control(privep, + ~(RP2040_USBCTRL_DPSRAM_EP_BUFF_CTRL_STALL), + 0); + + privep->next_pid = 0; + priv->zlp_stat = RP2040_ZLP_NONE; + } + else + { + privep->stalled = true; + + if (privep->epphy == 0 && !rp2040_rqempty(privep)) + { + /* EP0 IN Transfer ongoing : postpone the stall until the end */ + + privep->pending_stall = true; + } + else + { + /* Stall immediately */ + + rp2040_epstall_exec(ep); + } + + priv->zlp_stat = RP2040_ZLP_NONE; + } + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} + +/**************************************************************************** + * Device Methods + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_allocep + * + * Description: + * Allocate an endpoint matching the parameters + * + * Input Parameters: + * eplog - 7-bit logical endpoint number (direction bit ignored). + * Zero means that any endpoint matching the other requirements + * will suffice. The assigned endpoint can be found in the eplog + * field. + * in - true: IN (device-to-host) endpoint requested + * eptype - Endpoint type. + * One of {USB_EP_ATTR_XFER_ISOC, + * USB_EP_ATTR_XFER_BULK, + * USB_EP_ATTR_XFER_INT} + * + ****************************************************************************/ + +static FAR struct usbdev_ep_s *rp2040_allocep(FAR struct usbdev_s *dev, + uint8_t eplog, bool in, + uint8_t eptype) +{ + struct rp2040_usbdev_s *priv = (FAR struct rp2040_usbdev_s *)dev; + struct rp2040_ep_s *privep; + int epphy; + int epindex; + int dpindex; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); + + /* Ignore any direction bits in the logical address */ + + epphy = USB_EPNO(eplog); + epindex = RP2040_EPINDEX(eplog); + dpindex = RP2040_DPINDEX(eplog); + + if ((priv->used & 1 << epphy) && (epphy != 0)) + { + uinfo("ep is still used\n"); + return NULL; + } + + priv->used |= 1 << epphy; + + privep = &priv->eplist[epindex]; + privep->in = in; + privep->type = eptype; + privep->epphy = epphy; + privep->ep.eplog = eplog; + + privep->next_pid = 0; + privep->stalled = false; + privep->buf_ctrl = RP2040_USBCTRL_DPSRAM_EP_BUF_CTRL(dpindex); + + if (epphy == 0) + { + privep->data_buf = (uint8_t *)RP2040_USBCTRL_DPSRAM_EP0_BUF_0; + privep->ep_ctrl = 0; + } + else + { + privep->ep_ctrl = RP2040_USBCTRL_DPSRAM_EP_CTRL(dpindex); + } + + return &privep->ep; +} + +/**************************************************************************** + * Name: rp2040_freeep + * + * Description: + * Free the previously allocated endpoint + * + ****************************************************************************/ + +static void rp2040_freeep(FAR struct usbdev_s *dev, + FAR struct usbdev_ep_s *ep) +{ + FAR struct rp2040_usbdev_s *priv = (FAR struct rp2040_usbdev_s *)dev; + FAR struct rp2040_ep_s *privep = (FAR struct rp2040_ep_s *)ep; + + usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); + + priv->used &= ~(1 << privep->epphy); +} + +/**************************************************************************** + * Name: rp2040_getframe + * + * Description: + * Returns the current frame number + * + ****************************************************************************/ + +static int rp2040_getframe(FAR struct usbdev_s *dev) +{ + usbtrace(TRACE_DEVGETFRAME, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (!dev) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + return (int)(getreg32(RP2040_USBCTRL_REGS_SOF_RD) & + RP2040_USBCTRL_REGS_SOF_RD_COUNT_MASK); +} + +/**************************************************************************** + * Name: rp2040_wakeup + * + * Description: + * Tries to wake up the host connected to this device + * + ****************************************************************************/ + +static int rp2040_wakeup(FAR struct usbdev_s *dev) +{ + usbtrace(TRACE_DEVWAKEUP, 0); + + setbits_reg32(RP2040_USBCTRL_REGS_SIE_CTRL_RESUME, + RP2040_USBCTRL_REGS_SIE_CTRL); + + return OK; +} + +/**************************************************************************** + * Name: rp2040_selfpowered + * + * Description: + * Sets/clears the device selfpowered feature + * + ****************************************************************************/ + +static int rp2040_selfpowered(FAR struct usbdev_s *dev, bool selfpowered) +{ + FAR struct rp2040_usbdev_s *priv = (FAR struct rp2040_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_FEATURES + if (!dev) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Name: rp2040_pullup + * + * Description: + * Software-controlled connect to/disconnect from USB host + * + ****************************************************************************/ + +static int rp2040_pullup(FAR struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + + if (enable) + { + setbits_reg32(RP2040_USBCTRL_REGS_SIE_CTRL_PULLUP_EN, + RP2040_USBCTRL_REGS_SIE_CTRL); + } + else + { + clrbits_reg32(RP2040_USBCTRL_REGS_SIE_CTRL_PULLUP_EN, + RP2040_USBCTRL_REGS_SIE_CTRL); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_usbinitialize + * + * Description: + * Initialize the USB driver + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arm_usbinitialize(void) +{ + int i; + + usbtrace(TRACE_DEVINIT, 0); + + putreg32(0, RP2040_USBCTRL_REGS_ADDR_ENDP); + + /* Initialize driver instance */ + + memset(&g_usbdev, 0, sizeof(struct rp2040_usbdev_s)); + + g_usbdev.usbdev.ops = &g_devops; + g_usbdev.usbdev.ep0 = &g_usbdev.eplist[0].ep; + + g_usbdev.dev_addr = 0; + g_usbdev.next_offset = RP2040_USBCTRL_DPSRAM_DATA_BUF_OFFSET; + + for (i = 0; i < RP2040_NENDPOINTS; i++) + { + g_usbdev.eplist[i].ep.ops = &g_epops; + g_usbdev.eplist[i].ep.maxpacket = 64; + g_usbdev.eplist[i].dev = &g_usbdev; + g_usbdev.eplist[i].epphy = 0; + g_usbdev.eplist[i].head = NULL; + g_usbdev.eplist[i].tail = NULL; + g_usbdev.eplist[i].ep.eplog = 0; + } + + if (irq_attach(RP2040_USBCTRL_IRQ, rp2040_usbinterrupt, &g_usbdev) != 0) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_IRQREGISTRATION), + (uint16_t)RP2040_USBCTRL_IRQ); + return; + } +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(FAR struct usbdevclass_driver_s *driver) +{ + int ret = -1; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (g_usbdev.driver) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* Hook up the driver */ + + g_usbdev.driver = driver; + + setbits_reg32(RP2040_RESETS_RESET_USBCTRL, RP2040_RESETS_RESET); + clrbits_reg32(RP2040_RESETS_RESET_USBCTRL, RP2040_RESETS_RESET); + + memset((void *)RP2040_USBCTRL_DPSRAM_BASE, 0, 0x1000); + + putreg32(RP2040_USBCTRL_REGS_USB_MUXING_SOFTCON | + RP2040_USBCTRL_REGS_USB_MUXING_TO_PHY, + RP2040_USBCTRL_REGS_USB_MUXING); + putreg32(RP2040_USBCTRL_REGS_USB_PWR_VBUS_DETECT | + RP2040_USBCTRL_REGS_USB_PWR_VBUS_DETECT_OVERRIDE_EN, + RP2040_USBCTRL_REGS_USB_PWR); + + rp2040_allocep(&g_usbdev.usbdev, 0x00, 0, USB_EP_ATTR_XFER_CONTROL); + rp2040_allocep(&g_usbdev.usbdev, 0x80, 1, USB_EP_ATTR_XFER_CONTROL); + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &g_usbdev.usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_BINDFAILED), (uint16_t)-ret); + g_usbdev.driver = NULL; + return ret; + } + + g_usbdev.usbdev.speed = USB_SPEED_FULL; + + putreg32(RP2040_USBCTRL_REGS_MAIN_CTRL_CONTROLLER_EN, + RP2040_USBCTRL_REGS_MAIN_CTRL); + + /* Enable interrupt */ + + putreg32(RP2040_USBCTRL_REGS_SIE_CTRL_EP0_INT_1BUF, + RP2040_USBCTRL_REGS_SIE_CTRL); + putreg32(RP2040_USBCTRL_REGS_INTR_BUFF_STATUS | + RP2040_USBCTRL_REGS_INTR_BUS_RESET | + RP2040_USBCTRL_REGS_INTR_SETUP_REQ, + RP2040_USBCTRL_REGS_INTE); + + up_enable_irq(RP2040_USBCTRL_IRQ); + + return OK; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver. If the USB device is connected to a + * USB host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. + * + ****************************************************************************/ + +int usbdev_unregister(FAR struct usbdevclass_driver_s *driver) +{ + FAR struct rp2040_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_DEVUNREGISTER, 0); + + flags = spin_lock_irqsave(NULL); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable interrupts */ + + up_disable_irq(RP2040_USBCTRL_IRQ); + + /* Disconnect device */ + + rp2040_pullup(&priv->usbdev, false); + + /* Unhook the driver */ + + priv->driver = NULL; + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} diff --git a/arch/arm/src/rp2040/rp2040_usbdev.h b/arch/arm/src/rp2040/rp2040_usbdev.h new file mode 100644 index 00000000000..601a7626b6c --- /dev/null +++ b/arch/arm/src/rp2040/rp2040_usbdev.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/rp2040/rp2040_usbdev.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RP2040_RP2040_USBDEV_H +#define __ARCH_ARM_SRC_RP2040_RP2040_USBDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "hardware/rp2040_usbctrl_regs.h" +#include "hardware/rp2040_usbctrl_dpsram.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_RP2040_RP2040_USBDEV_H */ diff --git a/arch/arm/src/rtl8720c/Kconfig b/arch/arm/src/rtl8720c/Kconfig new file mode 100644 index 00000000000..8553940d13f --- /dev/null +++ b/arch/arm/src/rtl8720c/Kconfig @@ -0,0 +1,395 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_CUSTOM + +comment "AMEBA Configuration Options" + +choice + prompt "AMEBA Chip Selection" + default ARCH_CHIP_AMEBAZ + +config ARCH_CHIP_AMEBAZ + bool "AmebaZ" + select ARCH_CORTEXM33 + +endchoice + +choice + prompt "AMEBAZ Chip Type Selection" + default ARCH_CHIP_AMEBAZ_C_CUT + depends on ARCH_CHIP_AMEBAZ + +config ARCH_CHIP_AMEBAZ_C_CUT + bool "AmebaZ_C_CUT" + +config ARCH_CHIP_AMEBAZ_D_CUT + bool "AmebaZ_D_CUT" + +endchoice + +config AMEBA_NR_IRQS + int "Interrupt Number" + +menuconfig AMEBA_UART + bool "AMEBA UART Chip support" + select ARCH_HAVE_SERIAL_TERMIOS + default n + +if AMEBA_UART + +config AMEBA_UART0 + bool "AMEBA UART0" + default n + +if AMEBA_UART0 + +config AMEBA_UART0_TX_PIN + int "AMEBA UART0 tx pin" + +config AMEBA_UART0_RX_PIN + int "AMEBA UART0 rx pin" + +config AMEBA_UART0_BAUD + int "AMEBA UART0 BAUD" + default 115200 + +config AMEBA_UART0_PARITY + int "AMEBA UART0 parity" + default 0 + range 0 2 + ---help--- + AMEBA UART0 parity. 0=None, 1=Odd, 2=Even. Default: None + +config AMEBA_UART0_BITS + int "AMEBA UART0 number of bits" + default 8 + ---help--- + AMEBA UART0 number of bits. Default: 8 + +config AMEBA_UART0_2STOP + int "AMEBA UART0 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config AMEBA_UART0_RXBUFSIZE + int "AMEBA UART0 Rx buffer size" + default 256 + ---help--- + AMEBA UART0 Rx buffer size. Default: 256 + +config AMEBA_UART0_TXBUFSIZE + int "AMEBA UART0 Tx buffer size" + default 256 + ---help--- + AMEBA UART0 Tx buffer size. Default: 256 + +config AMEBA_UART0_IFLOWCONTROL + bool "AMEBA UART0 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable AMEBA UART0 RTS flow control + +config AMEBA_UART0_OFLOWCONTROL + bool "AMEBA UART0 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable AMEBA UART0 CTS flow control + +endif # AMEBA_UART0 + +config AMEBA_UART1 + bool "AMEBA UART1" + default n + +if AMEBA_UART1 + +config AMEBA_UART1_TX_PIN + int "AMEBA UART1 tx pin" + +config AMEBA_UART1_RX_PIN + int "AMEBA UART1 rx pin" + +config AMEBA_UART1_BAUD + int "AMEBA UART1 BAUD" + default 115200 + +config AMEBA_UART1_PARITY + int "AMEBA UART1 parity" + default 0 + range 0 2 + ---help--- + AMEBA UART1 parity. 0=None, 1=Odd, 2=Even. Default: None + +config AMEBA_UART1_BITS + int "AMEBA UART1 number of bits" + default 8 + ---help--- + AMEBA UART1 number of bits. Default: 8 + +config AMEBA_UART1_2STOP + int "AMEBA UART1 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config AMEBA_UART1_RXBUFSIZE + int "AMEBA UART1 Rx buffer size" + default 256 + ---help--- + AMEBA UART1 Rx buffer size. Default: 256 + +config AMEBA_UART1_TXBUFSIZE + int "AMEBA UART1 Tx buffer size" + default 256 + ---help--- + AMEBA UART1 Tx buffer size. Default: 256 + +config AMEBA_UART1_IFLOWCONTROL + bool "AMEBA UART1 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable AMEBA UART1 RTS flow control + +config AMEBA_UART1_OFLOWCONTROL + bool "AMEBA UART1 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable AMEBA UART1 CTS flow control + +endif # AMEBA_UART1 + +config AMEBA_UART2 + bool "AMEBA UART2" + default n + +if AMEBA_UART2 + +config AMEBA_UART2_TX_PIN + int "AMEBA UART2 tx pin" + +config AMEBA_UART2_RX_PIN + int "AMEBA UART2 rx pin" + +config AMEBA_UART2_BAUD + int "AMEBA UART2 BAUD" + default 115200 + +config AMEBA_UART2_PARITY + int "AMEBA UART2 parity" + default 0 + range 0 2 + ---help--- + AMEBA UART2 parity. 0=None, 1=Odd, 2=Even. Default: None + +config AMEBA_UART2_BITS + int "AMEBA UART2 number of bits" + default 8 + ---help--- + AMEBA UART2 number of bits. Default: 8 + +config AMEBA_UART2_2STOP + int "AMEBA UART2 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config AMEBA_UART2_RXBUFSIZE + int "AMEBA UART2 Rx buffer size" + default 256 + ---help--- + AMEBA UART2 Rx buffer size. Default: 256 + +config AMEBA_UART2_TXBUFSIZE + int "AMEBA UART2 Tx buffer size" + default 256 + ---help--- + AMEBA UART2 Tx buffer size. Default: 256 + +config AMEBA_UART2_IFLOWCONTROL + bool "AMEBA UART2 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable AMEBA UART2 RTS flow control + +config AMEBA_UART2_OFLOWCONTROL + bool "AMEBA UART2 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable AMEBA UART2 CTS flow control + +endif # AMEBA_UART2 + +config AMEBA_UART3 + bool "AMEBA UART3" + default n + +if AMEBA_UART3 + +config AMEBA_UART3_TX_PIN + int "AMEBA UART3 tx pin" + +config AMEBA_UART3_RX_PIN + int "AMEBA UART3 rx pin" + +config AMEBA_UART3_BAUD + int "AMEBA UART3 BAUD" + default 115200 + +config AMEBA_UART3_PARITY + int "AMEBA UART3 parity" + default 0 + range 0 2 + ---help--- + AMEBA UART3 parity. 0=None, 1=Odd, 2=Even. Default: None + +config AMEBA_UART3_BITS + int "AMEBA UART3 number of bits" + default 8 + ---help--- + AMEBA UART3 number of bits. Default: 8 + +config AMEBA_UART3_2STOP + int "AMEBA UART3 two stop bits" + default 0 + ---help--- + 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit + +config AMEBA_UART3_RXBUFSIZE + int "AMEBA UART3 Rx buffer size" + default 256 + ---help--- + AMEBA UART3 Rx buffer size. Default: 256 + +config AMEBA_UART3_TXBUFSIZE + int "AMEBA UART3 Tx buffer size" + default 256 + ---help--- + AMEBA UART3 Tx buffer size. Default: 256 + +config AMEBA_UART3_IFLOWCONTROL + bool "AMEBA UART3 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable AMEBA UART3 RTS flow control + +config AMEBA_UART3_OFLOWCONTROL + bool "AMEBA UART3 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable AMEBA UART3 CTS flow control + +endif # AMEBA_UART3 + +choice + prompt "AMEBA Serial Console" + default AMEBA_NO_SERIAL_CONSOLE + depends on DEV_CONSOLE + +config AMEBA_UART0_SERIAL_CONSOLE + bool "AMEBA UART0 serial console" + depends on AMEBA_UART0 + select SERIAL_CONSOLE + +config AMEBA_UART1_SERIAL_CONSOLE + bool "AMEBA UART1 serial console" + depends on AMEBA_UART1 + select SERIAL_CONSOLE + +config AMEBA_UART2_SERIAL_CONSOLE + bool "AMEBA UART2 serial console" + depends on AMEBA_UART2 + select SERIAL_CONSOLE + +config AMEBA_UART3_SERIAL_CONSOLE + bool "AMEBA UART3 serial console" + depends on AMEBA_UART3 + select SERIAL_CONSOLE + +config AMEBA_NO_SERIAL_CONSOLE + bool "No AMEBA serial console" + +endchoice # AMEBA Serial Console + +config AMEBA_SUPRESS_CONFIG + bool "Suppress AMEBA configuration" + default n + +config AMEBA_SUPRESS_INITIAL_CONFIG + bool "Suppress initial AMEBA configuration" + depends on !AMEBA_SUPRESS_CONFIG + default n + ---help--- + This option is useful, for example, if you are using a bootloader + that configures the AMEBA_UART. In that case, you may want to + just leave the existing console configuration in place. Default: n + +config SERIAL_UART_ARCH_MMIO + bool "Platform access register through the memory mapping" + default n + +config SERIAL_UART_ARCH_IOCTL + bool "Platform has own custom IOCTL" + default n + +config AMEBA_REGINCR + int "Address increment between AMEBA registers" + default 1 + ---help--- + The address increment between AMEBA registers. Options are 1, 2, or 4. + Default: 1 + +config AMEBA_REGWIDTH + int "Bit width of AMEBA registers" + default 8 + ---help--- + The bit width of registers. Options are 8, 16, or 32. Default: 8 + +config AMEBA_ADDRWIDTH + int "Address width of AMEBA registers" + default 8 + ---help--- + The bit width of registers. Options are 8, 16, or 32. Default: 8 + +config AMEBA_HCI_DEV_NAME + string "Device Name of UART Device for Bluetooth" + default "/dev/ttyS2" + ---help--- + This option specifies the name of UART device to be used + for Bluetooth. + +config AMEBA_HCI_PROXY_DEV_NAME + string "Device Name of UART Device for Bluetooth" + default "/dev/ttyBT" + ---help--- + This option specifies the name of UART device to be used + for Bluetooth. + +endif # AMEBA_UART + +config IEEE80211_REALTEK_AMEBAZ + bool "Realtek amebaZ chip support" + default n + +if IEEE80211_REALTEK_AMEBAZ + +config IEEE80211_REALTEK_AMEBAZ_RECV_STACKSIZE + int "Realtek amebaZ recv stack size" + default 4096 + ---help--- + Default recv stack size + +endif + +endif # ARCH_CHIP_CUSTOM diff --git a/arch/arm/src/rtl8720c/Make.defs b/arch/arm/src/rtl8720c/Make.defs new file mode 100644 index 00000000000..ce08554a2b3 --- /dev/null +++ b/arch/arm/src/rtl8720c/Make.defs @@ -0,0 +1,76 @@ +############################################################################ +# arch/arm/src/rtl8720c/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# arch/arm/src/common +# +CMN_CSRCS += arm_checkstack.c arm_createstack.c arm_exit.c arm_hostfs.c +CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_modifyreg8.c +CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_pthread_start.c +CMN_CSRCS += arm_puts.c arm_releasestack.c arm_semi_syslog.c +CMN_CSRCS += arm_stackframe.c arm_task_start.c arm_usestack.c arm_vfork.c + +CMN_ASRCS += arm_exception.S + +# arch/arm/src/armv8-m +# +CMN_ASRCS += arm_fetchadd.S arm_fpu.S arm_setjmp.S +CMN_ASRCS += arm_fullcontextrestore.S arm_saveusercontext.S +CMN_ASRCS += arm_switchcontext.S arm_testset.S vfork.S + +CMN_UASRCS += arm_signal_handler.S + +CMN_CSRCS += arm_assert.c arm_blocktask.c arm_cache.c arm_copyarmstate.c +CMN_CSRCS += arm_copyfullstate.c arm_doirq.c arm_hardfault.c arm_initialstate.c +CMN_CSRCS += arm_itm_syslog.c arm_memfault.c arm_mpu.c arm_ramvec_attach.c +CMN_CSRCS += arm_ramvec_initialize.c arm_releasepending.c arm_reprioritizertr.c +CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_signal_dispatch.c +CMN_CSRCS += arm_stackcheck.c arm_svcall.c arm_systick.c arm_unblocktask.c + +# arch/arm/src/rtl8720c +# +CHIP_CSRCS += ameba_nvic.c ameba_heap.c ameba_idle.c ameba_uart.c ameba_start.c ameba_vectors.c +CHIP_CSRCS += ameba_efuse.c ameba_flash.c ameba_wdt.c ameba_hci.c + +CHIP_ASRCS += ameba_lto.S + +# arch/arm/src/rtl8720c/8710c/fwlib/source +# +CHIP_CSRCS += hal_efuse.c hal_flash.c hal_misc.c hal_spic.c hal_ssi.c hal_uart.c + +CFLAGS += -I$(TOPDIR)/arch/arm/include/rtl8720c +CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c +CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/cmsis/cmsis-core/include +CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/cmsis/rtl8710c/include +CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/app/rtl_printf/include +CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/app/stdio_port +CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/misc/utilities/include +CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/fwlib/include + +CFLAGS += -Wno-attributes + +ifeq ($(CONFIG_IEEE80211_REALTEK_AMEBAZ),y) +CHIP_CSRCS += amebaZ.c amebaz_driver.c amebaz_netdev.c amebaz_depend.c amebaz_wlan.c ameba_func.c +CHIP_CSRCS += amebaz_hci_board.c amebaz_coex.c amebaz_firmware.c +endif # CONFIG_IEEE80211_REALTEK_AMEBAZ + +VPATH += chip/8710c +VPATH += chip/8710c/fwlib/source/ram +VPATH += chip/8710c/fwlib/source/ram_s +VPATH += chip/8710c/fwlib/source/ram_ns diff --git a/arch/arm/src/rtl8720c/Toolchain.defs b/arch/arm/src/rtl8720c/Toolchain.defs new file mode 100644 index 00000000000..9be75a76442 --- /dev/null +++ b/arch/arm/src/rtl8720c/Toolchain.defs @@ -0,0 +1,101 @@ +############################################################################ +# arch/arm/src/rtl8720c/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT)}" +else + ARCHSCRIPT = -T$(LDSCRIPT) +endif + +include ${TOPDIR}/arch/arm/src/armv8-m/Toolchain.defs + +LD = $(CROSSDEV)gcc + +ARCHOPTIMIZATION = +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +# enable precise stack overflow tracking +ifeq ($(CONFIG_ARMV8M_STACKCHECK),y) + INSTRUMENTATIONDEFINES += -finstrument-functions -ffixed-r10 +endif + +ifeq ($(CONFIG_STACK_CANARIES),y) + ARCHOPTIMIZATION += -fstack-protector-all +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer + ARCHOPTIMIZATION += -ffunction-sections -fdata-sections +ifneq ($(CONFIG_ARMV8M_STACKCHECK),y) + #ARCHOPTIMIZATION += -flto -fuse-linker-plugin +endif +endif + +ARCHCFLAGS = -fno-builtin -march=armv8-m.main+dsp -mthumb -mfloat-abi=soft -D__thumb2__ -g -gdwarf-3 -Os -fno-tree-scev-cprop +ARCHCXXFLAGS = -fno-builtin -nostdinc++ -std=c++11 +ifneq ($(CONFIG_CXX_EXCEPTION),y) + ARCHCXXFLAGS += -fno-exceptions -fcheck-new -fno-rtti +endif +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CFLAGS += -I$(TOPDIR)/arch/$(CONFIG_ARCH)/src/rtl8720c +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mlong-calls -fno-common +CXXELFFLAGS = $(CXXFLAGS) -mlong-calls -fno-common +AELFFLAGS = $(AFLAGS) +LDELFFLAGS = -r -e main -Bstatic $(LDFLAGS) +LDELFFLAGS += -T $(TOPDIR)/binfmt/libelf/gnu-elf.ld + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls -fno-common + +LDMODULEFLAGS = -r -e module_initialize $(LDFLAGS) +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +LDSTARTGROUP = -Wl,--start-group +LDENDGROUP = -Wl,--end-group + +ifeq ($(filter -nuttx-, $(CROSSDEV)),) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + LDFLAGS += -Wl,--gc-sections +endif + +EXTRA_LIBS += -l_soc_is +EXTRA_LIBS += -l_wlan diff --git a/arch/arm/src/rtl8720c/amebaZ.c b/arch/arm/src/rtl8720c/amebaZ.c new file mode 100644 index 00000000000..adc9fce45c4 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaZ.c @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaZ.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "systick.h" +#include "hal_syson.h" +#include "hal_wdt.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_CHIP_AMEBAZ +void up_timer_initialize(void) +{ + up_timer_set_lowerhalf(systick_initialize(true, 100000000, -1)); +} + +void ameba_reset(int status) +{ + hal_sys_set_fast_boot(0, 0); + hal_misc_rst_by_wdt(); +} + +#endif /* CONFIG_ARCH_CHIP_AMEBAZ */ diff --git a/arch/arm/src/rtl8720c/ameba_efuse.c b/arch/arm/src/rtl8720c/ameba_efuse.c new file mode 100644 index 00000000000..2c44e476d03 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_efuse.c @@ -0,0 +1,224 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_efuse.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hal_api.h" +#include "hal_efuse.h" +#include "hal_efuse_nsc.h" +#include "platform_conf.h" +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if CONFIG_EFUSE_EN +/* #define EFUSE_LOGICAL_SIM */ + +#define EFUSE_LOGICAL_MAP_SIZE 512 +#define EFUSE_LOGICAL_MAP_HW_SIZE 0xd0 /* sync with EFUSE_OOB_PROTECT_BYTES */ +#define EFUSE_LOGICAL_SBLOCK_OFFSET 0x19 +#ifdef EFUSE_LOGICAL_SIM +uint8_t ameba_efuse_sim_map[256]; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int ameba_efuse_logical_read(uint16_t laddr, uint16_t size, uint8_t *pbuf) +{ + uint8_t offset; + uint8_t wden; + uint8_t header; + uint8_t extheader; + uint8_t data; + uint16_t phy_addr = 0; + uint16_t i; + uint32_t ret; + if (!pbuf) + { + return -EIO; + } + + rtw_memset(pbuf, 0xff, size); + while (phy_addr < EFUSE_LOGICAL_MAP_HW_SIZE) + { + /* First two bytes are reserved for physical */ + + if (phy_addr == 0 || phy_addr == 1) + { + phy_addr++; + continue; + } + +#ifdef EFUSE_LOGICAL_SIM + static int map_inited = 0; + if (!map_inited) + { + map_inited = 1; + for (i = 0; i < EFUSE_LOGICAL_MAP_HW_SIZE; i++) + { + hal_efuse_read(i, &ameba_efuse_sim_map[i], + LDO_OUT_DEFAULT_VOLT); + } + } + + ret = _TRUE; + header = ameba_efuse_sim_map[phy_addr++]; +#else + ret = hal_efuse_read(phy_addr++, &header, LDO_OUT_DEFAULT_VOLT); +#endif + if (ret != _TRUE) + { + return -EIO; + } + + if (header == 0xff) + { + break; + } + + /* Check PG header for section num. */ + + if ((header & 0x1f) == 0x0f) + { + /* extended header */ + + offset = (header & 0xe0) >> 5; +#ifdef EFUSE_LOGICAL_SIM + ret = _TRUE; + extheader = ameba_efuse_sim_map[phy_addr++]; +#else + ret = hal_efuse_read(phy_addr++, &extheader, LDO_OUT_DEFAULT_VOLT); +#endif + if (ret != _TRUE) + { + return -EIO; + } + + if (((extheader & 0x0f) == 0x0f)) + { + continue; + } + + offset |= ((extheader & 0xf0) >> 1); + wden = (extheader & 0x0f); + } + + else + { + offset = ((header >> 4) & 0x0f); + wden = (header & 0x0f); + } + + /* One section has 8 bytes data, logical map has 512/8 = 64 sections */ + + if (offset < (EFUSE_LOGICAL_MAP_SIZE >> 3)) + { + uint16_t addr = 0; + + /* Get word enable value from PG header */ + + addr = offset * 8; + + /* Each section has 4 words data */ + + for (i = 0; i < 4; i++) + { + /* Check word enable condition in the section */ + + if (!(wden & (0x01 << i))) + { +#ifdef EFUSE_LOGICAL_SIM + ret = _TRUE; + data = ameba_efuse_sim_map[phy_addr++]; +#else + ret = hal_efuse_read(phy_addr++, &data, + LDO_OUT_DEFAULT_VOLT); +#endif + if (ret != _TRUE) + { + return -EIO; + } + + if (addr >= laddr && addr < (laddr + size)) + { + pbuf[addr - laddr] = data; + } + +#ifdef EFUSE_LOGICAL_SIM + ret = _TRUE; + data = ameba_efuse_sim_map[phy_addr++]; +#else + ret = hal_efuse_read(phy_addr++, &data, + LDO_OUT_DEFAULT_VOLT); +#endif + if (ret != _TRUE) + { + return -EIO; + } + + if ((addr + 1) >= laddr && (addr + 1) < (laddr + size)) + { + pbuf[addr + 1 - laddr] = data; + } + } + + addr += 2; + } + } + + else + { + uint8_t word_cnts = 0; + if (!(wden & BIT(0))) + { + word_cnts++; /* 0 : write enable */ + } + + if (!(wden & BIT(1))) + { + word_cnts++; + } + + if (!(wden & BIT(2))) + { + word_cnts++; + } + + if (!(wden & BIT(3))) + { + word_cnts++; + } + + phy_addr += word_cnts * 2; + } + } + + /* return used bytes */ + + return phy_addr - EIO; +} + +#endif diff --git a/arch/arm/src/rtl8720c/ameba_efuse.h b/arch/arm/src/rtl8720c/ameba_efuse.h new file mode 100644 index 00000000000..bfa4c31f87f --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_efuse.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_AMEBA_HCI_EFUSE_H +#define __INCLUDE_AMEBA_HCI_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* #include "device.h" */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int ameba_efuse_logical_read(uint16_t laddr, uint16_t size, uint8_t *pbuf); +int ameba_efuse_logical_write(uint16_t addr, uint16_t cnts, uint8_t *data); +int ameba_efuse_fw_verify_enable(void); +int ameba_efuse_fw_verify_check(void); +int ameba_efuse_boot_message_disable(void); +int ameba_efuse_boot_message_enable(void); +#endif /* __INCLUDE_AMEBA_FLASH_H */ diff --git a/arch/arm/src/rtl8720c/ameba_flash.c b/arch/arm/src/rtl8720c/ameba_flash.c new file mode 100644 index 00000000000..70572953262 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_flash.c @@ -0,0 +1,335 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_flash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ameba_flash.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Identifies the flash sector and block size */ + +#define AMEBA_SECTOR_SHIFT (12) +#define AMEBA_SECTOR_SIZE (1 << 12) /* Sector size 1 << 12 = 4KB */ +#define AMEBA_PAGE_SHIFT (8) +#define AMEBA_PAGE_SIZE (1 << 8) /* Block size 1 << 8 = 256B */ + +/* Flash Layout */ + +#define AMEBA_SECTOR_TOTAL_SIZE (2048 * 1024) /* Total flash size */ +#define AMEBA_SECTOR_SYSTEM_SIZE (16 * 1024) +#define AMEBA_SECTOR_BOOT_SIZE (32 * 1024) +#define AMEBA_SECTOR_FIRMWARE1_SIZE (864 * 1024) +#define AMEBA_SECTOR_FIRMWARE2_SIZE (864 * 1024) +#define AMEBA_SECTOR_OTA_SIZE (236 * 1024) +#define AMEBA_SECTOR_DATA_SIZE (24 * 1024) +#define AMEBA_SECTOR_BLUETOOTH_SIZE (12 * 1024) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum +{ + SPICONEIOMODE = 0, /* !< Define One IO mode, 1-1-1 */ + SPICDUALOUTPUTMODE = 1, /* !< Define Dual Output mode, 1-1-2 */ + SPICDUALIOMODE = 2, /* !< Define Dual IO mode, 1-2-2 */ + SPICQUADOUTPUTMODE = 3, /* !< Define Quad Output mode, 1-1-4 */ + SPICQUADIOMODE = 4, /* !< Define Quad IO mode, 1-4-4 */ + SPICQPIMODE = 5, /* !< Define QPI mode, 4-4-4 */ +}; + +struct ameba_flash_dev_s +{ + struct mtd_dev_s mtd; + void *adaptor; + uint32_t baseaddr; + uint16_t nsectors; +}; + +extern const hal_flash_func_stubs_t hal_flash_stubs; +extern hal_spic_adaptor_t hal_spic_adaptor; +extern hal_spic_adaptor_t *pglob_spic_adaptor; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct partition_s ptable[5] = +{ + { + .name = "fw1", + .firstblock = AMEBA_SECTOR_SYSTEM_SIZE + + AMEBA_SECTOR_BOOT_SIZE, + .nblocks = AMEBA_SECTOR_FIRMWARE1_SIZE, + }, + { + .name = "fw2", + .firstblock = AMEBA_SECTOR_SYSTEM_SIZE + + AMEBA_SECTOR_BOOT_SIZE + + AMEBA_SECTOR_FIRMWARE1_SIZE, + .nblocks = AMEBA_SECTOR_FIRMWARE2_SIZE, + }, + { + .name = "ota", + .firstblock = AMEBA_SECTOR_SYSTEM_SIZE + + AMEBA_SECTOR_BOOT_SIZE + + AMEBA_SECTOR_FIRMWARE1_SIZE + + AMEBA_SECTOR_FIRMWARE2_SIZE, + .nblocks = AMEBA_SECTOR_OTA_SIZE, + }, + { + .name = "data", + .firstblock = AMEBA_SECTOR_SYSTEM_SIZE + + AMEBA_SECTOR_BOOT_SIZE + + AMEBA_SECTOR_FIRMWARE1_SIZE + + AMEBA_SECTOR_FIRMWARE2_SIZE + + AMEBA_SECTOR_OTA_SIZE, + .nblocks = AMEBA_SECTOR_DATA_SIZE, + }, + { + .name = "bt", + .firstblock = AMEBA_SECTOR_SYSTEM_SIZE + + AMEBA_SECTOR_BOOT_SIZE + + AMEBA_SECTOR_FIRMWARE1_SIZE + + AMEBA_SECTOR_FIRMWARE2_SIZE + + AMEBA_SECTOR_OTA_SIZE + + AMEBA_SECTOR_DATA_SIZE, + .nblocks = AMEBA_SECTOR_BLUETOOTH_SIZE, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static irqstate_t flash_resource_lock(void) +{ + irqstate_t state; + state = enter_critical_section(); + icache_disable(); + dcache_disable(); + return state; +} + +static void flash_resource_unlock(irqstate_t state) +{ + dcache_enable(); + icache_enable(); + icache_invalidate(); + leave_critical_section(state); +} + +static int ameba_flash_erase(FAR struct mtd_dev_s *dev, + off_t startblock, size_t nblocks) +{ + FAR struct ameba_flash_dev_s *priv = (FAR struct ameba_flash_dev_s *)dev; + uint32_t address = priv->baseaddr + (startblock << AMEBA_SECTOR_SHIFT); + irqstate_t state; + state = flash_resource_lock(); + hal_flash_stubs.hal_flash_sector_erase(priv->adaptor, address); + flash_resource_unlock(state); + return nblocks; +} + +static ssize_t ameba_flash_bread(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks, + FAR uint8_t *buf) +{ + FAR struct ameba_flash_dev_s *priv = (FAR struct ameba_flash_dev_s *)dev; + uint32_t address = priv->baseaddr + (startblock << AMEBA_PAGE_SHIFT); + uint32_t length = nblocks << AMEBA_PAGE_SHIFT; + irqstate_t state; + state = flash_resource_lock(); + dcache_invalidate_by_addr((uint32_t *)(SPI_FLASH_BASE + address), length); + hal_flash_stubs.hal_flash_stream_read(priv->adaptor, length, address, buf); + flash_resource_unlock(state); + return nblocks; +} + +static ssize_t ameba_flash_bwrite(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks, FAR const uint8_t *buf) +{ + FAR struct ameba_flash_dev_s *priv = (FAR struct ameba_flash_dev_s *)dev; + uint32_t address = priv->baseaddr + (startblock << AMEBA_PAGE_SHIFT); + uint32_t length = nblocks << AMEBA_PAGE_SHIFT; + irqstate_t state; + state = flash_resource_lock(); + hal_flash_stubs.hal_flash_burst_write(priv->adaptor, + length, address, (uint8_t *)buf); + flash_resource_unlock(state); + return nblocks; +} + +static int ameba_flash_spic_init(struct ameba_flash_dev_s *priv) +{ + hal_status_t status; + irqstate_t state; + if (pglob_spic_adaptor == NULL) + { + status = spic_init(&hal_spic_adaptor, SPICDUALIOMODE, + &(hal_spic_adaptor.flash_pin_sel)); + if (status != HAL_OK) + { + DBG_SPIF_ERR("flash_init err(%d)\r\n", status); + } + + return status; + } + + priv->adaptor = pglob_spic_adaptor; + state = flash_resource_lock(); + hal_flash_stubs.hal_flash_read_id(pglob_spic_adaptor); + flash_resource_unlock(state); + if ((pglob_spic_adaptor->flash_id[0] == 0x0) + || (pglob_spic_adaptor->flash_id[0] == 0xff)) + { + return -EPERM; + } + + return 0; +} + +static int ameba_flash_ioctl(FAR struct mtd_dev_s *dev, + int cmd, unsigned long arg) +{ + FAR struct ameba_flash_dev_s *priv = (FAR struct ameba_flash_dev_s *)dev; + irqstate_t state; + int ret = OK; + switch (cmd) + { + case MTDIOC_GEOMETRY: + { + FAR struct mtd_geometry_s *geo = + (FAR struct mtd_geometry_s *)((uintptr_t)arg); + if (geo) + { + geo->blocksize = AMEBA_PAGE_SIZE; + geo->erasesize = AMEBA_SECTOR_SIZE; + geo->neraseblocks = priv->nsectors; + finfo("blocksize: %d erasesize: %d neraseblocks: %d\n", + geo->blocksize, geo->erasesize, geo->neraseblocks); + } + } + + break; + case MTDIOC_BULKERASE: + { + state = flash_resource_lock(); + hal_flash_stubs.hal_flash_64k_block_erase(priv->adaptor, + priv->baseaddr); + flash_resource_unlock(state); + } + + break; + default: + { + ret = -ENOTTY; + } + + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ameba_flash_initialize + * + * Description: + * Create and initialize an ameba spic flash MTD device instance + * that can be used to access the userdata memory. + * + ****************************************************************************/ + +static FAR struct mtd_dev_s *ameba_flash_initialize(void) +{ + struct ameba_flash_dev_s *priv; + priv = kmm_zalloc(sizeof(struct ameba_flash_dev_s)); + if (priv == NULL) + { + return NULL; + } + + priv->mtd.erase = ameba_flash_erase; + priv->mtd.bread = ameba_flash_bread; + priv->mtd.bwrite = ameba_flash_bwrite; + priv->mtd.ioctl = ameba_flash_ioctl; + priv->mtd.name = "ameba_flash"; + priv->baseaddr = 0; + priv->nsectors = AMEBA_SECTOR_TOTAL_SIZE / + AMEBA_SECTOR_SIZE; + if (ameba_flash_spic_init(priv) < 0) + { + ferr("ERROR: Flash Type Unrecognized\n"); + kmm_free(priv); + priv = NULL; + } + + return (FAR struct mtd_dev_s *)priv; +} + +static void ameba_partition_init(FAR const struct partition_s *part, + FAR const void *path) +{ + char dev[32]; + snprintf(dev, sizeof(dev), "/dev/%s", part->name); + register_mtdpartition(dev, 0, path, + part->firstblock / AMEBA_PAGE_SIZE, + part->nblocks / AMEBA_PAGE_SIZE); +} + +void ameba_flash_init(void) +{ + const struct partition_s *table; + char *path = "/dev/ameba_flash"; + FAR struct mtd_dev_s *mtd; + mtd = ameba_flash_initialize(); + if (mtd == NULL) + { + return; + } + + register_mtddriver(path, mtd, 0, mtd); + for (table = &ptable[0]; table->nblocks; table++) + { + ameba_partition_init(table, path); + } +} + diff --git a/arch/arm/src/rtl8720c/ameba_flash.h b/arch/arm/src/rtl8720c/ameba_flash.h new file mode 100644 index 00000000000..2deebb7c719 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_flash.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_flash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_AMEBA_FLASH_H +#define __INCLUDE_AMEBA_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __INCLUDE_AMEBA_FLASH_H */ diff --git a/arch/arm/src/rtl8720c/ameba_hci.c b/arch/arm/src/rtl8720c/ameba_hci.c new file mode 100644 index 00000000000..f1c383f41e0 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_hci.c @@ -0,0 +1,509 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_hci.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include <../../../../net/netdev/netdev.h> +#include "amebaz_hci_board.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AMEBAZ_WIRELESS_NAME "wlan0" +#define H4_CMD 0x01 +#define H4_EVT 0x04 +#define HCI_H4_HDR_SIZE 1 +#define HCI_CMD_HDR_SIZE 3 +typedef struct +{ + struct file_operations i_ops; + struct file filep; +} hci_dev_t; +struct bt_hci_evt_hdr +{ + uint8_t evt; + uint8_t len; +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +static int hci_recv(FAR struct file *filep, FAR uint8_t *buf, size_t count) +{ + ssize_t ret; + ssize_t nread = 0; + while (count != nread) + { + ret = file_read(filep, buf + nread, count - nread); + if (ret < 0) + { + if (ret == -EAGAIN) + { + continue; + } + else + { + return ret; + } + } + + nread += ret; + } + + return nread; +} + +static int hci_send(FAR struct file *filep, FAR uint8_t *buf, size_t count) +{ + ssize_t ret; + ssize_t nwritten = 0; + while (nwritten != count) + { + ret = file_write(filep, buf + nwritten, count - nwritten); + if (ret < 0) + { + if (ret == -EAGAIN) + { + continue; + } + else + { + return ret; + } + } + + nwritten += ret; + } + + return nwritten; +} + +#ifdef HCI_START_IQK +static int hci_do_iqk(FAR struct file *filep) +{ + /* OpCode: 0xfd4a, h4 data_len: Cmd(8), Event(7) */ + + unsigned char command[8]; + struct t_data + { + uint8_t offset; + uint16_t value; + }; + + struct t_data data[4] = + { + {0x00, 0x4000}, + {0x01, 0x0f88}, + {0x02, 0x3400}, + {0x3f, 0x0700} + }; + + if (0 == hci_check_iqk()) + { + return 0; + } + + for (unsigned char i = 0; i < 4; i++) + { + command[0] = H4_CMD; + command[1] = 0x4a; + command[2] = 0xfd; + command[3] = 4; + command[4] = data[i].offset; + command[5] = (uint8_t)(data[i].value >> 0); + command[6] = (uint8_t)(data[i].value >> 8); + command[7] = 0; + if (hci_send(filep, command, 8) != 8) + { + return -EIO; + } + + hci_recv(filep, command, 1); + if (command[0] != H4_EVT) + { + return -EIO; + } + + hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr)); + hci_recv(filep, command + 3, command[2]); + + /* Check OpCode and Status */ + + if (!(command[4] == 0x4a && command[5] == 0xfd) || command[6] != 0x00) + { + return -EIO; + } + } + + if (hci_start_iqk()) + { + return -EIO; + } + + return 0; +} + +#endif +static int hci_check_local_ver(FAR struct file *filep) +{ + /* OpCode: 0x1001, h4 buf_len: Cmd(1+3=4), Event(1+14=15) */ + + unsigned char command[15]; + command[0] = H4_CMD; + command[1] = 0x01; + command[2] = 0x10; + command[3] = 0; + if (hci_send(filep, command, 4) != 4) + { + return -EIO; + } + + hci_recv(filep, command, 1); + if (command[0] != H4_EVT) + { + return -EIO; + } + + hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr)); + hci_recv(filep, command + 3, command[2]); + + /* Check OpCode and Status */ + + if (!(command[4] == 0x01 && command[5] == 0x10) || command[6] != 0x00) + { + return -EIO; + } + + /* Only Check LMP Subversion */ + + uint16_t lmp_sbuver = + ((uint16_t)command[13]) | (((uint16_t)command[14]) << 8); + if (BT_DEFAUT_LMP_SUBVER != lmp_sbuver) + { + return -EALREADY; + } + + return 0; +} + +static int hci_check_local_rom_ver(FAR struct file *filep) +{ + /* OpCode: 0xfc6d, h4 buf_len: Cmd(1+3=4), Event(1+7=8) */ + + unsigned char command[8]; + command[0] = H4_CMD; + command[1] = 0x6d; + command[2] = 0xfc; + command[3] = 0; + if (hci_send(filep, command, 4) != 4) + { + return -EIO; + } + + hci_recv(filep, command, 1); + if (command[0] != H4_EVT) + { + return -EIO; + } + + hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr)); + hci_recv(filep, command + 3, command[2]); + + /* Check OpCode and Status */ + + if (!(command[4] == 0x6d && command[5] == 0xfc) || command[6] != 0x00) + { + return -EIO; + } + + /* Get Chip Id (Rom_Ver+1) and Find Patch */ + + if (hci_find_fw_patch(command[7] + 1)) + { + return -EIO; + } + + return 0; +} + +static int hci_update_baudrate(FAR struct file *filep) +{ + /* OpCode: 0xfc17, h4 buf_len: Cmd(1+7=8), Event(1+6=7) */ + + unsigned char command[8]; + struct termios toptions; + uint32_t bt_baudrate; + uint32_t uart_baudrate; + command[0] = H4_CMD; + command[1] = 0x17; + command[2] = 0xfc; + command[3] = sizeof(uint32_t); + if (hci_get_baudrate(&bt_baudrate, &uart_baudrate)) + { + return -EIO; + } + + memcpy(&command[4], &bt_baudrate, sizeof(uint32_t)); + if (hci_send(filep, command, 8) != 8) + { + return -EIO; + } + + hci_recv(filep, command, 1); + if (command[0] != H4_EVT) + { + return -EIO; + } + + hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr)); + hci_recv(filep, command + 3, command[2]); + + /* Check OpCode and Status */ + + if (!(command[4] == 0x17 && command[5] == 0xfc) || command[6] != 0x00) + { + return -EIO; + } + + file_ioctl(filep, TCGETS, (unsigned long)&toptions); + cfsetispeed(&toptions, uart_baudrate); + cfsetospeed(&toptions, uart_baudrate); + return file_ioctl(filep, TCSETS, (unsigned long)&toptions); +} + +static int hci_load_firmware(FAR struct file *filep) +{ + int header_size = HCI_H4_HDR_SIZE + HCI_CMD_HDR_SIZE; + uint8_t command[AMEBAZ_COMMAND_FRAGMENT_SIZE + header_size]; + FAR struct net_driver_s *drv; + int buffer_size; + uint8_t *addr; + int i; + int ret; + drv = netdev_findbyname(AMEBAZ_WIRELESS_NAME); + if (drv == NULL) + { + return -EINVAL; + } + + addr = drv->d_mac.ether.ether_addr_octet; + if (hci_set_init_config_mac(addr, 1)) + { + return -EIO; + } + + while (hci_fetch_command(command) != AMEBAZ_COMMAND_DONE) + { + command[0] = H4_CMD; + command[1] = 0x20; + command[2] = 0xfc; + buffer_size = header_size + command[3]; + usleep(10); + ret = hci_send(filep, command, buffer_size); + if (ret != buffer_size) + { + return ret; + } + + hci_recv(filep, command, 1); + if (H4_EVT != command[0]) + { + return -EIO; + } + + hci_recv(filep, command + 1, 2); + hci_recv(filep, command + 3, command[2]); + + /* Check OpCode and Status */ + + if (!(command[4] == 0x20 && command[5] == 0xfc) || command[6] != 0x00) + { + return -EIO; + } + } + + return OK; +} + +static int hci_update_efuse_iqk(FAR struct file *filep) +{ + /* OpCode: 0xfd91, h4 buf_len: Cmd(1+15=16), Event(1+6=7) */ + + unsigned char command[16]; + command[0] = H4_CMD; + command[1] = 0x91; + command[2] = 0xfd; + if (hci_get_efuse_iqk_data(command + 3)) + { + return -EIO; + } + + if (hci_send(filep, command, sizeof(command)) != sizeof(command)) + { + return -EIO; + } + + hci_recv(filep, command, 1); + if (command[0] != H4_EVT) + { + return -EIO; + } + + hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr)); + hci_recv(filep, command + 3, command[2]); + return 0; +} + +static int hci_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR hci_dev_t *dev = inode->i_private; + int ret; + ret = file_open(&dev->filep, + CONFIG_AMEBA_HCI_DEV_NAME, O_RDWR | O_BINARY); + if (ret < 0) + { + return ret; + } + + if (hci_board_init()) + { + goto bail; + } + +#ifdef HCI_START_IQK + ret = hci_do_iqk(&dev->filep); + if (ret < 0) + { + goto bail; + } + +#endif + ret = hci_check_local_ver(&dev->filep); + if (ret < 0) + { + if (-EALREADY == ret) + { + ret = 0; + } + + goto bail; + } + + ret = hci_check_local_rom_ver(&dev->filep); + if (ret < 0) + { + goto bail; + } + + ret = hci_update_baudrate(&dev->filep); + if (ret < 0) + { + goto bail; + } + + ret = hci_load_firmware(&dev->filep); + if (ret < 0) + { + goto bail; + } + + ret = hci_update_efuse_iqk(&dev->filep); +bail: + ret = hci_board_init_done(); + if (ret < 0) + { + file_close(&dev->filep); + } + + return ret; +} + +static int hci_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR hci_dev_t *dev = inode->i_private; + + /* FIXME: BT PowerOff */ + + return file_close(&dev->filep); +} + +static ssize_t hci_read(FAR struct file *filep, + FAR char *buffer, size_t buflen) +{ + FAR struct inode *inode = filep->f_inode; + FAR hci_dev_t *dev = inode->i_private; + return file_read(&dev->filep, buffer, buflen); +} + +static ssize_t hci_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen) +{ + FAR struct inode *inode = filep->f_inode; + FAR hci_dev_t *dev = inode->i_private; + return file_write(&dev->filep, buffer, buflen); +} + +static int hci_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode = filep->f_inode; + FAR hci_dev_t *dev = inode->i_private; + return file_ioctl(&dev->filep, cmd, arg); +} + +static int hci_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup) +{ + FAR struct inode *inode = filep->f_inode; + FAR hci_dev_t *dev = inode->i_private; + return file_poll(&dev->filep, fds, setup); +} + +static hci_dev_t g_hcidev = +{ + .i_ops = + { + .open = hci_open, + .close = hci_close, + .read = hci_read, + .write = hci_write, + .ioctl = hci_ioctl, + .poll = hci_poll + }, +}; + +int amebaz_bt_hci_uart_register(FAR const char *path) +{ + return register_driver(path, &g_hcidev.i_ops, 0666, &g_hcidev); +} + diff --git a/arch/arm/src/rtl8720c/ameba_heap.c b/arch/arm/src/rtl8720c/ameba_heap.c new file mode 100644 index 00000000000..f4ae9714c5b --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_heap.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_heap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include "chip.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define _START_HEAP ((uintptr_t)&__bss_end__) +#define _END_HEAP ((uintptr_t)&__sram_end__) +#ifdef CONFIG_HEAP_COLORATION +# define song_heap_color(start, size) memset(start, HEAP_COLOR, size) +#else +# define song_heap_color(start, size) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern uint32_t __stack; +extern uint32_t __bss_end__; +extern uint32_t __sram_end__; +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ + +const uintptr_t __attribute__((weak)) g_idle_topstack = + ((uintptr_t)&__stack); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + /* Return the heap settings */ + + *heap_start = (FAR void *)_START_HEAP; + *heap_size = _END_HEAP - _START_HEAP; + + /* Colorize the heap for debug */ + + song_heap_color(*heap_start, *heap_size); +} + diff --git a/arch/arm/src/rtl8720c/ameba_idle.c b/arch/arm/src/rtl8720c/ameba_idle.c new file mode 100644 index 00000000000..274ff493585 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_idle.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +# define up_idlepm() up_cpu_idle() + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed + * when their is no other ready-to-run task. This is processor + * idle time and will continue until some interrupt occurs to + * cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., + * this is where power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +} + diff --git a/arch/arm/src/rtl8720c/ameba_lto.S b/arch/arm/src/rtl8720c/ameba_lto.S new file mode 100644 index 00000000000..30900f35f26 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_lto.S @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_lto.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .syntax unified + .arch armv8-m.main + .thumb + .file "ameba_lto.S" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + .thumb_func + .globl ameba_lto + .globl __aeabi_d2iz + .globl __aeabi_d2lz + .globl __aeabi_d2ulz + .globl __aeabi_dcmpeq + .globl __aeabi_dcmpge + .globl __aeabi_dcmplt + .globl __aeabi_ddiv + .globl __aeabi_fadd + .globl __aeabi_fcmpge + .globl __aeabi_fcmpgt + .globl __aeabi_fdiv + .globl __aeabi_fmul + .globl __aeabi_i2f + .globl __aeabi_idivmod + .globl __aeabi_ldivmod + .globl __aeabi_llsl + .globl __aeabi_llsr + .globl __aeabi_lmul + .globl __aeabi_uidiv + .globl __aeabi_uldivmod + .globl __bswapsi2 + .globl __clzsi2 + .globl __ctzsi2 + .globl __gnu_thumb1_case_shi + .globl __gnu_thumb1_case_si + .globl __gnu_thumb1_case_sqi + .globl __gnu_thumb1_case_uhi + .globl __gnu_thumb1_case_uqi + .globl __gnu_thumb1_case_uqi + .globl __popcountsi2 + .type ameba_lto, function +ameba_lto: + .size ameba_lto, .-ameba_lto + .end diff --git a/arch/arm/src/rtl8720c/ameba_nvic.c b/arch/arm/src/rtl8720c/ameba_nvic.c new file mode 100644 index 00000000000..6947a87f00c --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_nvic.c @@ -0,0 +1,458 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_nvic.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifdef CONFIG_ARCH_CORTEXM33 +#include +#include +#include +#include +#include "sched/sched.h" +#include "chip.h" +#include "nvic.h" +#include "ram_vectors.h" +#include "arm_arch.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROUND_DOWN(v, q) (((v) / (q)) * (q)) + +/* Get a 32-bit version of the default priority */ + +#define NVIC_PRIORITY_DEFAULT32 (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding NVIC CLEAR register. + */ +#define NVIC_ENABLE_OFFSET (NVIC_IRQ0_31_ENABLE - NVIC_IRQ0_31_ENABLE) +#define NVIC_CLEAR_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ +#ifdef CONFIG_SMP +volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; +#else +volatile uint32_t *g_current_regs[1]; +#endif + +/* extern int32_t __StackLimit; */ + +extern uint32_t _vectors[]; + +/**************************************************************************** + * Private Function Declarations + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static int (* __vectors[NR_IRQS - NVIC_IRQ_FIRST])(void); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_getsp + ****************************************************************************/ + +static inline uint32_t up_getsp(void) +{ + uint32_t sp; + __asm__ + ( + "\tmov %0, sp\n\t" + : "=r"(sp) + ); + return sp; +} + +/**************************************************************************** + * Name: nvic_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int nvic_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + DEBUGASSERT(irq >= NVIC_IRQ_MEMFAULT && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= NVIC_IRQ_FIRST) + { + irq = irq - NVIC_IRQ_FIRST; + *regaddr = NVIC_IRQ_ENABLE(irq) + offset; + *bit = (uint32_t)1 << (irq & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == NVIC_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + + else if (irq == NVIC_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + + else if (irq == NVIC_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + + else if (irq == NVIC_IRQ_DBGMONITOR) + { + *regaddr = NVIC_DEMCR; + *bit = NVIC_DEMCR_MONEN; + } + + else if (irq == NVIC_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_TICKINT; + } + + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void weak_function up_wic_initialize(void) +{ +} + +void weak_function up_wic_enable_irq(int irq) +{ +} + +void weak_function up_wic_disable_irq(int irq) +{ +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * This function implements disabling of the device specified by 'irq' + * at the interrupt controller level if supported by the architecture + * (up_irq_save() supports the global level, the device level is hardware + * specific). + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t bit; + if (nvic_irqinfo(irq, ®addr, &bit, NVIC_CLEAR_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= NVIC_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + + else + { + modifyreg32(regaddr, bit, 0); + } + + up_wic_disable_irq(irq); + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * On many architectures, there are three levels of interrupt enabling: (1) + * at the global level, (2) at the level of the interrupt controller, + * and (3) at the device level. In order to receive interrupts, they + * must be enabled at all three levels. + * + * This function implements enabling of the device specified by 'irq' + * at the interrupt controller level if supported by the architecture + * (up_irq_restore() supports the global level, the device level is + * hardware specific). + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t bit; + if (nvic_irqinfo(irq, ®addr, &bit, NVIC_ENABLE_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= NVIC_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + + else + { + modifyreg32(regaddr, 0, bit); + } + + up_wic_enable_irq(irq); + } +} + +/**************************************************************************** + * Name: up_trigger_irq + * + * Description: + * Trigger an IRQ by software. + * + ****************************************************************************/ + +void up_trigger_irq(int irq) +{ + uint32_t pend_bit = 0; + DEBUGASSERT(irq >= NVIC_IRQ_NMI && irq < NR_IRQS); + if (irq >= NVIC_IRQ_FIRST) + { + putreg32(irq - NVIC_IRQ_FIRST, NVIC_STIR); + } + + else + { + switch (irq) + { + case NVIC_IRQ_PENDSV: + pend_bit = NVIC_INTCTRL_PENDSVSET; + break; + case NVIC_IRQ_NMI: + pend_bit = NVIC_INTCTRL_NMIPENDSET; + break; + case NVIC_IRQ_SYSTICK: + pend_bit = NVIC_INTCTRL_PENDSTSET; + break; + } + + if (pend_bit) + { + modifyreg32(NVIC_INTCTRL, 0, pend_bit); + } + } +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + int shift; + DEBUGASSERT(irq >= NVIC_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_PRIORITY_MAX && + priority <= NVIC_SYSH_PRIORITY_MIN); + if (irq < NVIC_IRQ_FIRST) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= NVIC_IRQ_MEMFAULT; + } + + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= NVIC_IRQ_FIRST; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + shift = (irq & 3) << 3; + modifyreg32(regaddr, 0xff << shift, priority << shift); + return OK; +} + +/**************************************************************************** + * Name: _up_doirq + ****************************************************************************/ + +int _up_doirq(int irq, FAR void *context, FAR void *arg) +{ + if (irq < NVIC_IRQ_FIRST) + { + return ERROR; + } + + __vectors[irq - NVIC_IRQ_FIRST](); + return OK; +} + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + int i; + + /* Disable all interrupts */ + + for (i = 0; i < NR_IRQS - NVIC_IRQ_FIRST; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + /* Restore the NVIC vector location to local */ + + memcpy(&__vectors, (void *) * (volatile uint32_t *)(NVIC_VECTAB) + + NVIC_IRQ_FIRST * sizeof(uint32_t), sizeof(__vectors)); + + /* Set the NVIC vector location in case _vectors not equal zero. */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + /* Now bits[7-5] are available in each 8bits, + * Take bits[7-6] as group priority, take bit[5] as subpriorities. + */ + + modifyreg32(NVIC_AIRCR, NVIC_AIRCR_VECTKEY_MASK | NVIC_AIRCR_PRIGROUP_MASK, + (0x5fa << NVIC_AIRCR_VECTKEY_SHIFT) | (0x5 << NVIC_AIRCR_PRIGROUP_SHIFT)); + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(NVIC_PRIORITY_DEFAULT32, NVIC_SYSH4_7_PRIORITY); + putreg32(NVIC_PRIORITY_DEFAULT32, NVIC_SYSH8_11_PRIORITY); + putreg32(NVIC_PRIORITY_DEFAULT32, NVIC_SYSH12_15_PRIORITY); + for (i = 0; i < NR_IRQS - NVIC_IRQ_FIRST; i += 4) + { + putreg32(NVIC_PRIORITY_DEFAULT32, NVIC_IRQ_PRIORITY(i)); + } + + up_wic_initialize(); + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(NVIC_IRQ_SVCALL, arm_svcall, NULL); + up_prioritize_irq(NVIC_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + irq_attach(NVIC_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Attach and enable the Memory Management Fault handler */ + + irq_attach(NVIC_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(NVIC_IRQ_MEMFAULT); + + /* Attach and enable the external interrupts */ + + for (i = NVIC_IRQ_FIRST; i < NR_IRQS; i++) + { + irq_attach(i, _up_doirq, NULL); + } + + up_disable_irq(NVIC_IRQ_BUSFAULT); + up_disable_irq(NVIC_IRQ_USAGEFAULT); + + /* And finally, enable interrupts */ + + up_irq_enable(); +} + +void up_irq_attach_workaround(void) +{ + extern void exception_common(void); + __vectors[NVIC_IRQ_WLAN - NVIC_IRQ_FIRST] = + (void *) *((uint32_t *) *(volatile uint32_t *)NVIC_VECTAB + + NVIC_IRQ_WLAN); + *((uint32_t *) * (volatile uint32_t *)NVIC_VECTAB + NVIC_IRQ_WLAN) = + (unsigned)exception_common; + up_prioritize_irq(NVIC_IRQ_WLAN, NVIC_SYSH_PRIORITY_DEFAULT); +} + +#endif diff --git a/arch/arm/src/rtl8720c/ameba_start.c b/arch/arm/src/rtl8720c/ameba_start.c new file mode 100644 index 00000000000..813becd5aed --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_start.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "arm_internal.h" +#include "rtl8710c_irq.h" +#include + +extern void ram_start(void); +extern void ameba_lto(void); +const hal_irq_api_t sys_irq_api = +{ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_ARMV8M_STACKCHECK + +/* We need to get r10 set before we can allow instrumentation calls */ + +void __start(void) __attribute__((no_instrument_function)); +#endif +void __start(void) +{ +#ifdef CONFIG_ARMV8M_STACKCHECK + + /* Set the stack limit before we attempt to call any functions */ + + #define STACKSIZE_TEMP CONFIG_IDLETHREAD_STACKSIZE + __asm__ volatile("sub r10, sp, %0" : : "r" (STACKSIZE_TEMP - 64) :); +#endif + ram_start(); +} + +void mpu_init(void) +{ +} + +void promisc_deinit(void *padapter) +{ +} + +int promisc_recv_func(void *padapter, void *rframe) +{ + return 0; +} + +int promisc_recv_lens_func(void *padapter, uint8_t *payload, uint8_t plen) +{ + return 0; +} + +void app_start(void) +{ + __asm volatile("MSR msplim, %0" : : "r"(0)); + arm_earlyserialinit(); +#ifdef CONFIG_MBEDTLS240_AMEBAZ_HARDWARE_CRYPTO + extern int mbedtls_platform_set_calloc_free( + void *(*calloc_func)(size_t, size_t), void (*free_func)(void *)); + extern int chip_platform_set_malloc_free( + void *(*ssl_calloc)(unsigned int, unsigned int), + void (*ssl_free)(void *)); + mbedtls_platform_set_calloc_free(calloc, free); + chip_platform_set_malloc_free(calloc, free); +#endif + nx_start(); + ameba_lto(); +} + diff --git a/arch/arm/src/rtl8720c/ameba_uart.c b/arch/arm/src/rtl8720c/ameba_uart.c new file mode 100644 index 00000000000..377b60f3a10 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_uart.c @@ -0,0 +1,1097 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_uart.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ameba_uart.h" +#include +#ifdef CONFIG_AMEBA_UART + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum +{ + UART_0 = 0, /* !< 1-byte */ + UART_1 = 1, /* !< 4-byte/8-byte(for 8195B/8710C) */ + UART_2 = 2, /* !< 8-byte/16-byte(for 8195B/8710C) */ + UART_3 = 3, /* !< 14-byte/30-bytes(for 8195B/8710C) */ + MAX_UART_NUM = 4 +}; + +enum +{ + UART_PIN_TX = 0, + UART_PIN_RX = 1, + UART_PIN_RTS = 2, + UART_PIN_CTS = 3 +}; + +enum +{ + PIN_PULLNONE = 0, + PIN_PULLDOWN = 1, + PIN_PULLUP = 2, + PIN_PULLDEFAULT = PIN_PULLNONE +}; + +enum +{ + FIFOLV1BYTE = 0, /* !< 1-byte */ + FIFOLVQUARTER = 1, /* !< 4-byte/8-byte(for 8195B/8710C) */ + FIFOLVHALF = 2, /* !< 8-byte/16-byte(for 8195B/8710C) */ + FIFOLVFULL = 3 /* !< 14-byte/30-bytes(for 8195B/8710C) */ +}; + +enum +{ + FLOWCONTROLNONE, /* !priv; + int uart_idx; + uart_idx = hal_uart_stubs.hal_uart_pin_to_idx(priv->rx, UART_PIN_RX); + if (uart_idx != hal_uart_stubs.hal_uart_pin_to_idx(priv->tx, UART_PIN_TX) + || uart_idx > MAX_UART_PORT) + { + return -EINVAL; + } + + if (!priv->adapter.is_inited) + { + if (uart_idx <= UART_2) + { + hal_gpio_stubs.hal_gpio_pull_ctrl(priv->rx, PIN_PULLUP); + } + + if (uart_idx == UART_0) + { + hal_syson_wakeup_uart_func_reset(); + } + + else if (uart_idx == UART_2) + { + priv->adapter.is_inited = true; + } + + status = hal_uart_stubs.hal_uart_init(&priv->adapter, + priv->tx, priv->rx, NULL); + if (status != OK) + { + return status; + } + + if (uart_idx < UART_2) + { + hal_pinmux_register(priv->tx, (PID_UART0 + uart_idx)); + hal_pinmux_register(priv->rx, (PID_UART0 + uart_idx)); + } + + if (uart_idx == UART_3) + { + priv->adapter.base_addr->fcr_b.rxfifo_trigger_level = FIFOLVHALF; + hal_uart_stubs.hal_uart_set_flow_control(&priv->adapter, + FLOWCONTROLRTS); + } + + else + { + priv->adapter.base_addr->fcr_b.rxfifo_trigger_level = FIFOLV1BYTE; + hal_uart_stubs.hal_uart_set_flow_control(&priv->adapter, + FLOWCONTROLNONE); + } + } + + status = hal_uart_stubs.hal_uart_set_baudrate(&priv->adapter, priv->baud); + if (status != OK) + { + return status; + } + + status = hal_uart_stubs.hal_uart_set_format(&priv->adapter, + priv->bits, priv->parity, priv->stopbits2 ? 2 : 1); +#endif + return status; +} + +/**************************************************************************** + * Name: ameba_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void ameba_shutdown(struct uart_dev_s *dev) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + uint32_t uart_idx = priv->adapter.uart_idx; + if (uart_idx == UART_2) + { + priv->adapter.is_inited = false; + } + + hal_uart_stubs.hal_uart_deinit(&priv->adapter); + if (uart_idx > UART_2) + { + return; + } + + hal_pinmux_unregister(priv->adapter.tx_pin, (PID_UART0 + uart_idx)); + hal_pinmux_unregister(priv->adapter.rx_pin, (PID_UART0 + uart_idx)); +} + +/**************************************************************************** + * Name: ameba_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX and + * TX interrupts are not enabled until the txint() and rxint() methods are + * called + * + ****************************************************************************/ + +static int ameba_attach(struct uart_dev_s *dev) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + hal_uart_stubs.hal_uart_txtd_hook(&priv->adapter, + ameba_interrupt, (uintptr_t)dev, 0); + hal_uart_stubs.hal_uart_rxind_hook(&priv->adapter, + ameba_interrupt, (uintptr_t)dev, 1); + return OK; +} + +/**************************************************************************** + * Name: ameba_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void ameba_detach(FAR struct uart_dev_s *dev) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + hal_uart_stubs.hal_uart_txtd_hook(&priv->adapter, + NULL, (uintptr_t)NULL, 0); + hal_uart_stubs.hal_uart_rxind_hook(&priv->adapter, + NULL, (uintptr_t)NULL, 0); +} + +/**************************************************************************** + * Name: ameba_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate ameba_s structure in order to call these functions. + * + ****************************************************************************/ + +static void ameba_interrupt(uint32_t id, uint32_t event) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)id; + if (event == 0) + { + uart_xmitchars(dev); + } + + else + { + uart_recvchars(dev); + } +} + +/**************************************************************************** + * Name: ameba_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int ameba_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + int ret; +#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL + ret = uart_ioctl(filep, cmd, arg); + if (ret != -ENOTTY) + { + return ret; + } + +#else + ret = OK; +#endif + switch (cmd) + { +#if defined(CONFIG_SERIAL_TERMIOS) && !defined(CONFIG_AMEBA_SUPRESS_CONFIG) + case TCGETS: + { + FAR struct termios *termiosp = (FAR struct termios *)arg; + irqstate_t flags; + if (!termiosp) + { + ret = -EINVAL; + break; + } + + flags = enter_critical_section(); + cfsetispeed(termiosp, priv->baud); + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + termiosp->c_cflag |= priv->flow ? CRTSCTS : 0; +#endif + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + case 6: + termiosp->c_cflag |= CS6; + break; + case 7: + termiosp->c_cflag |= CS7; + break; + case 8: + default: + termiosp->c_cflag |= CS8; + break; + } + + leave_critical_section(flags); + } + + break; + case TCSETS: + { + FAR struct termios *termiosp = (FAR struct termios *)arg; + irqstate_t flags; + if (!termiosp) + { + ret = -EINVAL; + break; + } + + flags = enter_critical_section(); + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + priv->bits = 5; + break; + case CS6: + priv->bits = 6; + break; + case CS7: + priv->bits = 7; + break; + case CS8: + default: + priv->bits = 8; + break; + } + + if ((termiosp->c_cflag & PARENB) != 0) + { + priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + + else + { + priv->parity = 0; + } + + priv->baud = cfgetispeed(termiosp); + priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + priv->flow = (termiosp->c_cflag & CRTSCTS) != 0; +#endif + ameba_setup(dev); + leave_critical_section(flags); + } + + break; +#endif + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: ameba_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int ameba_receive(struct uart_dev_s *dev, uint32_t *status) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + return hal_uart_stubs.hal_uart_getc(&priv->adapter); +} + +/**************************************************************************** + * Name: ameba_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void ameba_rxint(struct uart_dev_s *dev, bool enable) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + hal_uart_stubs.hal_uart_set_rts(&priv->adapter, enable); +} + +/**************************************************************************** + * Name: ameba_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool ameba_rxavailable(struct uart_dev_s *dev) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + return hal_uart_stubs.hal_uart_readable(&priv->adapter); +} + +/**************************************************************************** + * Name: ameba_dma* + * + * Description: + * Stubbed out DMA-related methods + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool ameba_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, + bool upper) +{ + return false; +} + +#endif + +/**************************************************************************** + * Name: ameba_dma* + * + * Description: + * Stub functions used when serial DMA is enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_TXDMA +static void ameba_dmasend(FAR struct uart_dev_s *dev) +{ +} + +#endif +#ifdef CONFIG_SERIAL_RXDMA +static void ameba_dmareceive(FAR struct uart_dev_s *dev) +{ +} + +static void ameba_dmarxfree(FAR struct uart_dev_s *dev) +{ +} + +#endif +#ifdef CONFIG_SERIAL_TXDMA +static void ameba_dmatxavail(FAR struct uart_dev_s *dev) +{ +} + +#endif + +/**************************************************************************** + * Name: ameba_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void ameba_send(struct uart_dev_s *dev, int ch) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + while (hal_uart_stubs.hal_uart_writeable(&priv->adapter) == 0); + hal_uart_stubs.hal_uart_putc(&priv->adapter, ch); +} + +/**************************************************************************** + * Name: ameba_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void ameba_txint(struct uart_dev_s *dev, bool enable) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + priv->adapter.base_addr->ier_b.etbei = enable; + if (enable) + { + uart_xmitchars(dev); + } +} + +/**************************************************************************** + * Name: ameba_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool ameba_txready(struct uart_dev_s *dev) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + return hal_uart_stubs.hal_uart_writeable(&priv->adapter); +} + +/**************************************************************************** + * Name: ameba_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool ameba_txempty(struct uart_dev_s *dev) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)dev->priv; + return priv->adapter.base_addr->tflvr_b.tx_fifo_lv > 0 ? 0 : 1; +} + +/**************************************************************************** + * Name: ameba_putc + * + * Description: + * Write one character to the UART (polled) + * + ****************************************************************************/ + +#ifdef HAVE_AMEBA_CONSOLE +static void ameba_putc(FAR struct ameba_s *priv, int ch) +{ + while (hal_uart_stubs.hal_uart_writeable(&priv->adapter) == 0); + hal_uart_stubs.hal_uart_putc(&priv->adapter, ch); +} + +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before uart_serialinit. + * + * NOTE: Configuration of the CONSOLE UART was performed by uart_lowsetup() + * very early in the boot sequence. + * + ****************************************************************************/ + +void arm_earlyserialinit(void) +{ + /* Configuration whichever one is the console */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; +#ifndef CONFIG_AMEBA_SUPRESS_INITIAL_CONFIG + ameba_setup(&CONSOLE_DEV); +#endif +#endif +} + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * arm_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ +#ifdef CONSOLE_DEV + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif +#ifdef TTYS0_DEV + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + (void)uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_AMEBA_CONSOLE +int up_putc(int ch) +{ + FAR struct ameba_s *priv = (FAR struct ameba_s *)CONSOLE_DEV.priv; + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + ameba_putc(priv, '\r'); + } + + ameba_putc(priv, ch); + return ch; +} + +#endif +#endif /* CONFIG_AMEBA_UART */ diff --git a/arch/arm/src/rtl8720c/ameba_uart.h b/arch/arm/src/rtl8720c/ameba_uart.h new file mode 100644 index 00000000000..9dd0a15a6ab --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_uart.h @@ -0,0 +1,178 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SERIAL_UART_AMEBA_H +#define __INCLUDE_NUTTX_SERIAL_UART_AMEBA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#ifdef CONFIG_AMEBA_UART + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CONFIGURATION */ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART +#if defined(CONFIG_AMEBA_UART0) || defined(CONFIG_AMEBA_UART1) || \ + defined(CONFIG_AMEBA_UART2) || defined(CONFIG_AMEBA_UART3) +# define HAVE_UART 1 +#endif +/* We need to be told the address increment between registers and + * the register bit width. + */ +#ifndef CONFIG_AMEBA_REGINCR +# error "CONFIG_AMEBA_REGINCR not defined" +#endif + +#if CONFIG_AMEBA_REGINCR != 1 && CONFIG_AMEBA_REGINCR != 2 && CONFIG_AMEBA_REGINCR != 4 +# error "CONFIG_AMEBA_REGINCR not supported" +#endif +#ifndef CONFIG_AMEBA_REGWIDTH +# error "CONFIG_AMEBA_REGWIDTH not defined" +#endif + +#if CONFIG_AMEBA_REGWIDTH != 8 && CONFIG_AMEBA_REGWIDTH != 16 && CONFIG_AMEBA_REGWIDTH != 32 +# error "CONFIG_AMEBA_REGWIDTH not supported" +#endif +#ifndef CONFIG_AMEBA_ADDRWIDTH +# error "CONFIG_AMEBA_ADDRWIDTH not defined" +#endif + +#if CONFIG_AMEBA_ADDRWIDTH != 8 && CONFIG_AMEBA_ADDRWIDTH != 16 && CONFIG_AMEBA_ADDRWIDTH != 32 +# error "CONFIG_AMEBA_ADDRWIDTH not supported" +#endif + +/* If a UART is enabled, then its base address, + * clock, and IRQ must also be provided + */ + +#ifdef CONFIG_AMEBA_UART0 +# ifndef CONFIG_AMEBA_UART0_TX_PIN +# error "CONFIG_AMEBA_UART0_TX_PIN not provided" +# undef CONFIG_AMEBA_UART0 +# endif +# ifndef CONFIG_AMEBA_UART0_RX_PIN +# error "CONFIG_AMEBA_UART0_RX_PIN not provided" +# undef CONFIG_AMEBA_UART0 +# endif +#endif +#ifdef CONFIG_AMEBA_UART1 +# ifndef CONFIG_AMEBA_UART1_TX_PIN +# error "CONFIG_AMEBA_UART1_TX_PIN not provided" +# undef CONFIG_AMEBA_UART1 +# endif +# ifndef CONFIG_AMEBA_UART1_RX_PIN +# error "CONFIG_AMEBA_UART1_RX_PIN not provided" +# undef CONFIG_AMEBA_UART1 +# endif +#endif +#ifdef CONFIG_AMEBA_UART2 +# ifndef CONFIG_AMEBA_UART2_TX_PIN +# error "CONFIG_AMEBA_UART2_TX_PIN not provided" +# undef CONFIG_AMEBA_UART2 +# endif +# ifndef CONFIG_AMEBA_UART2_RX_PIN +# error "CONFIG_AMEBA_UART2_RX_PIN not provided" +# undef CONFIG_AMEBA_UART2 +# endif +#endif +#ifdef CONFIG_AMEBA_UART3 +# ifndef CONFIG_AMEBA_UART3_TX_PIN +# error "CONFIG_AMEBA_UART3_TX_PIN not provided" +# undef CONFIG_AMEBA_UART3 +# endif +# ifndef CONFIG_AMEBA_UART3_RX_PIN +# error "CONFIG_AMEBA_UART3_RX_PIN not provided" +# undef CONFIG_AMEBA_UART3 +# endif +#endif +/* Is there a serial console? There should be at most one defined. + * It could be on any UARTn, n=0,1,2,3 + */ + +#if defined(CONFIG_AMEBA_UART0_SERIAL_CONSOLE) && defined(CONFIG_AMEBA_UART0) +# undef CONFIG_AMEBA_UART1_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART2_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART3_SERIAL_CONSOLE +# define HAVE_AMEBA_CONSOLE 1 +#elif defined(CONFIG_AMEBA_UART1_SERIAL_CONSOLE) && defined(CONFIG_AMEBA_UART1) +# undef CONFIG_AMEBA_UART0_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART2_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART3_SERIAL_CONSOLE +# define HAVE_AMEBA_CONSOLE 1 +#elif defined(CONFIG_AMEBA_UART2_SERIAL_CONSOLE) && defined(CONFIG_AMEBA_UART2) +# undef CONFIG_AMEBA_UART0_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART1_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART3_SERIAL_CONSOLE +# define HAVE_AMEBA_CONSOLE 1 +#elif defined(CONFIG_AMEBA_UART3_SERIAL_CONSOLE) && defined(CONFIG_AMEBA_UART3) +# undef CONFIG_AMEBA_UART0_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART1_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART2_SERIAL_CONSOLE +# define HAVE_AMEBA_CONSOLE 1 +#else +# undef CONFIG_AMEBA_UART0_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART1_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART2_SERIAL_CONSOLE +# undef CONFIG_AMEBA_UART3_SERIAL_CONSOLE +# undef HAVE_AMEBA_CONSOLE +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#if CONFIG_AMEBA_REGWIDTH == 8 +typedef uint8_t uart_datawidth_t; +#elif CONFIG_AMEBA_REGWIDTH == 16 +typedef uint16_t uart_datawidth_t; +#elif CONFIG_AMEBA_REGWIDTH == 32 +typedef uint32_t uart_datawidth_t; +#endif +#if CONFIG_AMEBA_ADDRWIDTH == 8 +typedef uint8_t uart_addrwidth_t; +#elif CONFIG_AMEBA_ADDRWIDTH == 16 +typedef uint16_t uart_addrwidth_t; +#elif CONFIG_AMEBA_ADDRWIDTH == 32 +typedef uint32_t uart_addrwidth_t; +#endif + +/**************************************************************************** + * Name: uart_getreg(), uart_putreg(), uart_ioctl() + * + * Description: + * These functions must be provided by the processor-specific code in order + * to correctly access AMEBA registers + * uart_ioctl() is optional to provide custom IOCTLs + * + ****************************************************************************/ + +struct file; /* Forward reference */ +int uart_ioctl(struct file *filep, int cmd, unsigned long arg); +#endif /* CONFIG_AMEBA_UART */ +#endif /* __INCLUDE_NUTTX_SERIAL_UART_AMEBA_H */ diff --git a/arch/arm/src/rtl8720c/ameba_vectors.c b/arch/arm/src/rtl8720c/ameba_vectors.c new file mode 100644 index 00000000000..88561f2f266 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_vectors.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_vectors.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +extern uint32_t __stack; +#define IDLE_STACK ((unsigned)&__stack - 4) +#ifndef ARMV8M_PERIPHERAL_INTERRUPTS +# error ARMV8M_PERIPHERAL_INTERRUPTS must be defined to the number of I/O interrupts to be supported +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* Chip-specific entrypoint */ + +extern void ram_start(void); + +/* Common exception entrypoint */ + +extern void exception_common(void); + +/**************************************************************************** + * Public data + ****************************************************************************/ + +/* The v7m vector table consists of an array of function pointers, + * with the first + * slot (vector zero) used to hold the initial stack pointer. + * + * As all exceptions (interrupts) are routed via exception_common, + * we just need to + * fill this array with pointers to it. + * + * Note that the [ ... ] designated initialiser is a GCC extension. + */ + +unsigned _vectors[] __attribute__((section(".vectors"))) \ + __attribute__((aligned(0x100))) = +{ + /* Initial stack */ + + IDLE_STACK, + + /* Reset exception handler */ + + (unsigned) &ram_start, + + /* Vectors 2 - n point directly at the generic handler */ + + [2 ...(15 + ARMV8M_PERIPHERAL_INTERRUPTS)] = (unsigned) &exception_common +}; + diff --git a/arch/arm/src/rtl8720c/ameba_wdt.c b/arch/arm/src/rtl8720c/ameba_wdt.c new file mode 100644 index 00000000000..969a7070b33 --- /dev/null +++ b/arch/arm/src/rtl8720c/ameba_wdt.c @@ -0,0 +1,293 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/ameba_wdt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include "hal_wdt.h" +#if defined(CONFIG_WATCHDOG) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/** + * This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct ameba_lowerhalf_s +{ + FAR const struct watchdog_ops_s *ops; /* Lower half operations */ + uint32_t timeout; /* The (actual) selected timeout */ + uint32_t lastreset; /* The last reset time */ + bool started; /* true: The watchdog timer has + * been started + */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static int ameba_start(FAR struct watchdog_lowerhalf_s *lower); +static int ameba_stop(FAR struct watchdog_lowerhalf_s *lower); +static int ameba_keepalive(FAR struct watchdog_lowerhalf_s *lower); +static int ameba_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status); +static int ameba_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = ameba_start, + .stop = ameba_stop, + .keepalive = ameba_keepalive, + .getstatus = ameba_getstatus, + .settimeout = ameba_settimeout, + .capture = NULL, + .ioctl = NULL, +}; + +/* "Lower half" driver state */ + +static struct ameba_lowerhalf_s g_wdgdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ameba_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation + * of the "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int ameba_start(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower; + irqstate_t flags; + flags = enter_critical_section(); + priv->started = true; + priv->lastreset = clock_systime_ticks(); + hal_misc_wdt_enable(); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: ameba_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int ameba_stop(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower; + irqstate_t flags; + flags = enter_critical_section(); + hal_misc_wdt_disable(); + priv->started = false; + priv->timeout = 0; + priv->lastreset = 0; + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: ameba_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "petting the dog". + * + * The application program must write in the SAM_WDT_CLEAR register + * at regular intervals during normal operation to prevent an MCU reset. + * + * Input Parameters: + * lower - A pointer the publicly visible representation + * of the "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int ameba_keepalive(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower; + irqstate_t flags; + + /* Reload the WDT timer */ + + flags = enter_critical_section(); + priv->lastreset = clock_systime_ticks(); + hal_misc_wdt_refresh(); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: ameba_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int ameba_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status) +{ + FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower; + uint32_t elapsed; + uint32_t ticks; + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + /* Return the actual timeout in milliseconds */ + + status->timeout = priv->timeout; + + /* Get the elapsed time since the last ping */ + + ticks = clock_systime_ticks() - priv->lastreset; + elapsed = (int32_t)TICK2MSEC(ticks); + if (elapsed > priv->timeout) + { + elapsed = priv->timeout; + } + + /* Return the approximate time until the watchdog timer expiration */ + + status->timeleft = priv->timeout - elapsed; + return OK; +} + +/**************************************************************************** + * Name: ameba_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * timeout - The new timeout value in millisecnds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int ameba_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower; + irqstate_t flags; + flags = enter_critical_section(); + priv->timeout = timeout; + hal_misc_wdt_init(timeout * 1000); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ameba_wdt_initialize + * + * Description: + * Initialize the WDT watchdog timer. The watchdog timer + * is initialized and registers as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the watchdog. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void ameba_wdt_initialize(void) +{ + FAR struct ameba_lowerhalf_s *priv = &g_wdgdev; + + /* Initialize the driver state structure. */ + + priv->ops = &g_wdgops; + (void)watchdog_register(CONFIG_WATCHDOG_DEVPATH, + (FAR struct watchdog_lowerhalf_s *)priv); +} + +#endif /* CONFIG_WATCHDOG */ diff --git a/arch/arm/src/rtl8720c/amebaz_coex.c b/arch/arm/src/rtl8720c/amebaz_coex.c new file mode 100644 index 00000000000..5ff7613e6d7 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_coex.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_coex.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "amebaz_coex.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HCI_VENDOR_MAILBOX_CMD 0xfc8f + +/* static net_buf_simple *Xiaomi_buf; */ + +struct rtl_btinfo +{ + uint8_t cmd; + uint8_t len; + uint8_t data[6]; +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +unsigned int send_coex_mailbox_to_wifi_from_btapp(uint8_t state) +{ + uint8_t para[8]; + para[0] = 0x45; /* Mailbox ID */ + + para[1] = state; /* Data0 */ + + para[2] = 0; /* Data1 */ + + para[3] = 0; /* Data2 */ + + para[4] = 0; /* Data3 */ + + para[5] = 0; /* Data4 */ + + para[6] = 0; /* Data5 */ + + para[7] = 0; /* Data6 */ + + rltk_coex_mailbox_to_wifi(para, 8); + return 1; +} + +static void rtk_notify_info_to_wifi(uint8_t length, uint8_t *report_info) +{ + struct rtl_btinfo *report = (struct rtl_btinfo *)(report_info); + if (length) + { + printf("bt info: cmd %2.2X", report->cmd); + printf("bt info: len %2.2X", report->len); + printf("bt info: data %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X", + report->data[0], report->data[1], report->data[2], + report->data[3], report->data[4], report->data[5]); + } + + rltk_coex_mailbox_to_wifi(report_info, report->len + 2); + + /* send BT INFO to Wi-Fi driver */ +} + +void bt_coex_handle_cmd_complete_evt(uint16_t opcode, uint16_t cause, + uint8_t total_len, uint8_t *p) +{ + (void)cause; + if (opcode == HCI_VENDOR_MAILBOX_CMD) + { + uint8_t status; + status = *p++; /* jump the double subcmd */ + + total_len--; + if (total_len <= 1) + { + printf("bt_coex_handle_cmd_complete_evt: not reprot to wifi"); + return ; + } + + (void)status; + rltk_coex_mailbox_to_wifi(p, total_len); + + /* rtk_parse_vendor_mailbox_cmd_evt(p, total_len, status); */ + } +} + +void bt_coex_handle_specific_evt(uint8_t *p, uint8_t len) +{ + rltk_coex_mailbox_to_wifi(p, len); +} + +#ifndef MIN +# define MIN(a,b) (a < b ? a : b) +#endif +static const char *bt_hex_real(const void *buf, size_t len) +{ + static const char hex[] = "0123456789abcdef"; + static char str[129]; + const uint8_t *b = buf; + size_t i; + len = MIN(len, (sizeof(str) - 1) / 2); + for (i = 0; i < len; i++) + { + str[i * 2] = hex[b[i] >> 4]; + str[i * 2 + 1] = hex[b[i] & 0xf]; + } + + str[i * 2] = '\0'; + return str; +} + +static inline char *log_strdup(const char *str) +{ + return (char *)str; +} + +#define bt_hex(buf, len) log_strdup(bt_hex_real(buf, len)) +static void bt_coex_dump_buf(net_buf_simple *tmp_buf) +{ + printf("\n\r[%s] len=%d, buf = % s\n\r", __func__, + tmp_buf->len, + bt_hex(tmp_buf->data, + tmp_buf->len)); +} + +static int bt_coex_unpack_xiaomi_vendor_cmd(net_buf_simple *tmp_buf) +{ + if (tmp_buf-> data[0] == 0x25 && tmp_buf-> data[1] == 0x00) + { + tmp_buf -> data += 2; + tmp_buf -> len -= 2; + return 1; + } + + else + { + printf("[rtk_coex]Xiaomi vendor header not match.\n\r"); + return -1; + } +} + +bool bt_coex_handle_xiaomi_evt(net_buf_simple *xiaomi_buf) +{ + /* bt_coex_dump_buf(xiaomi_buf); */ + + bt_coex_unpack_xiaomi_vendor_cmd(xiaomi_buf); + + /* bt_coex_dump_buf(xiaomi_buf); */ + + rltk_coex_mailbox_to_wifi(xiaomi_buf->data, xiaomi_buf->len); + return true; +} + +typedef struct bt_sw_mailbox_info_s +{ + uint8_t data[8]; +}bt_sw_mailbox_info_t; + +static bt_sw_mailbox_info_t scan_enable; + +unsigned int bt_coex_sw_mailbox_set(unsigned int mailbox_control) +{ +#if 0 /* This function need to be removed */ + + uint8_t mailbox_len = 8; + memset(&scan_enable, 0, sizeof(scan_enable)); + switch (mailbox_control) + { + case BT_SW_MAILBOX_SCAN_OFF: + scan_enable.data[0] = 0x27; + scan_enable.data[1] = 6; + rtk_notify_info_to_wifi(mailbox_len, scan_enable.data); + break; + case BT_SW_MAILBOX_SCAN_ON: + scan_enable.data[0] = 0x27; + scan_enable.data[1] = 6; + scan_enable.data[5] = (0x0 | 0x1 << 5); /* BT scan EN bit */ + + rtk_notify_info_to_wifi(mailbox_len, scan_enable.data); + break; + default: + printf("[Err %s]No such sw mailbox command.\n\r", __func__); + break; + } + + return true; +#else + return true; +#endif +} + +void bt_coex_init(void) +{ + vendor_cmd_init(NULL); +} + diff --git a/arch/arm/src/rtl8720c/amebaz_coex.h b/arch/arm/src/rtl8720c/amebaz_coex.h new file mode 100644 index 00000000000..bac46e5c0c0 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_coex.h @@ -0,0 +1,75 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_coex.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +/* READ_ME + * Example usage + * \code{ble_app_main.c} + * + * void app_le_gap_init(void) + * { + * .... + * bt_coex_init(); + * } + * + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BT_SW_MAILBOX_SCAN_OFF 0x00 +#define BT_SW_MAILBOX_SCAN_ON 0x01 + +typedef struct net_buf_simple_s +{ + /* * Pointer to the start of data in the buffer. */ + + uint8_t *data; + + /* * Length of the data behind the data pointer. */ + + uint16_t len; + + /* * Amount of data that this buffer can store. */ + + uint16_t size; + /** Start of the data storage. Not to be accessed directly + * (the data pointer should be used instead). + */ + + uint8_t *__buf; +} net_buf_simple; + +void bt_coex_handle_cmd_complete_evt(uint16_t opcode, + uint16_t cause, + uint8_t total_len, + uint8_t *p); +void bt_coex_handle_specific_evt(uint8_t *p, uint8_t len); +bool bt_coex_handle_xiaomi_evt(net_buf_simple *xiaomi_buf); +unsigned int bt_coex_sw_mailbox_set(unsigned int mailbox_control); +void bt_coex_init(void); +unsigned int send_coex_mailbox_to_wifi_from_btapp(uint8_t state); + diff --git a/arch/arm/src/rtl8720c/amebaz_depend.c b/arch/arm/src/rtl8720c/amebaz_depend.c new file mode 100644 index 00000000000..a40c088a242 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_depend.c @@ -0,0 +1,1108 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_depend.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "amebaz_depend.h" +#include +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* stdio.h Wrapper Start */ + +int __wrap_printf(const char *fmt, ...) +{ + va_list ap; + int ret; + va_start(ap, fmt); + ret = nx_vsyslog(LOG_INFO, fmt, &ap); + va_end(ap); + return ret; +} + +/* stdio.h Wrapper End */ + +static int uxcriticalnesting = 0; + +/* Critical Opration Start */ + +void save_and_cli(void) +{ + enter_critical_section(); + uxcriticalnesting++; +} + +void restore_flags(void) +{ + ASSERT(uxcriticalnesting); + uxcriticalnesting--; + if (uxcriticalnesting == 0) + { + leave_critical_section(0); + } +} + +void rtw_enter_critical(void **plock, unsigned long *pirql) +{ + save_and_cli(); +} + +void rtw_exit_critical(void **plock, unsigned long *pirql) +{ + restore_flags(); +} + +void rtw_enter_critical_from_isr(void **plock, unsigned long *pirql) +{ + save_and_cli(); +} + +void rtw_exit_critical_from_isr(void **plock, unsigned long *pirql) +{ + restore_flags(); +} + +/* Critical Opration End */ + +/* arpa/inet.h Wrapper Start */ + +uint16_t _htons(uint16_t n) +{ + return htons(n); +} + +uint16_t _ntohs(uint16_t n) +{ + return _htons(n); +} + +/* arpa/inet.h Wrapper End */ + +/* stdlib.h Wrapper Start */ + +uint8_t *rtw_vmalloc(uint32_t n) +{ + return malloc(n); +} + +uint8_t *rtw_zvmalloc(uint32_t n) +{ + return calloc(1, n); +} + +void rtw_vmfree(uint8_t *pbuf, uint32_t n) +{ + return free(pbuf); +} + +uint8_t *rtw_malloc(uint32_t n) +{ + return rtw_vmalloc(n); +} + +uint8_t *rtw_zmalloc(uint32_t n) +{ + return rtw_zvmalloc(n); +} + +void rtw_mfree(uint8_t *pbuf, uint32_t n) +{ + return rtw_vmfree(pbuf, n); +} + +/* stdlib.h Wrapper End */ + +/* string.h Wrapper Start */ + +void rtw_memcpy(void *dst, void *src, uint32_t n) +{ + memcpy(dst, src, n); +} + +int rtw_memcmp(void *dst, void *src, uint32_t n) +{ + return memcmp(dst, src, n) ? 0 : 1; +} + +void rtw_memset(void *pbuf, int c, uint32_t n) +{ + memset(pbuf, c, n); +} + +/* string.h Wrapper End */ + +/* Semaphore Start */ + +void rtw_init_sema(void **sema, int init_val) +{ + sem_t *_sema; + _sema = calloc(1, sizeof(sem_t)); + if (!_sema) + { + return; + } + + if (sem_init(_sema, 0, init_val)) + { + free(_sema); + return; + } + + *sema = _sema; +} + +void rtw_free_sema(void **sema) +{ + sem_destroy(*sema); + free(*sema); + *sema = NULL; +} + +void rtw_up_sema(void **sema) +{ + sem_post(*sema); +} + +void rtw_up_sema_from_isr(void **sema) +{ + rtw_up_sema(sema); +} + +uint32_t rtw_down_timeout_sema(void **sema, uint32_t timeout) +{ + struct timespec abstime; + int ret; + if (timeout == 0xffffffff) + { + ret = sem_wait(*sema); + } + + else + { + clock_gettime(CLOCK_REALTIME, &abstime); + abstime.tv_sec += timeout / 1000; + abstime.tv_nsec += (timeout % 1000) * 1000 * 1000; + if (abstime.tv_nsec >= (1000 * 1000000)) + { + abstime.tv_sec += 1; + abstime.tv_nsec -= (1000 * 1000000); + } + + ret = sem_timedwait(*sema, &abstime); + } + + return !ret; +} + +uint32_t rtw_down_sema(void **sema) +{ + return rtw_down_timeout_sema(sema, 0xffffffff); +} + +/* Semaphore End */ + +/* MUTual EXclusion Start */ + +void rtw_mutex_init(void **pmutex) +{ + rtw_init_sema(pmutex, 1); +} + +void rtw_mutex_free(void **pmutex) +{ + rtw_free_sema(pmutex); +} + +void rtw_mutex_put(void **pmutex) +{ + rtw_up_sema(pmutex); +} + +void rtw_mutex_get(void **pmutex) +{ + rtw_down_sema(pmutex); +} + +int rtw_mutex_get_timeout(void **pmutex, uint32_t ms) +{ + return rtw_down_timeout_sema(pmutex, ms); +} + +int rtw_enter_critical_mutex(void **pmutex, unsigned long *pirql) +{ + return rtw_down_sema(pmutex); +} + +void rtw_exit_critical_mutex(void **pmutex, unsigned long *pirql) +{ + rtw_up_sema(pmutex); +} + +/* MUTual EXclusion End */ + +/* Spinlocks Start */ + +void rtw_spinlock_init(void **plock) +{ + rtw_init_sema(plock, 1); +} + +void rtw_spinlock_free(void **plock) +{ + rtw_free_sema(plock); +} + +void rtw_spin_lock(void **plock) +{ + rtw_down_sema(plock); +} + +void rtw_spin_unlock(void **plock) +{ + rtw_up_sema(plock); +} + +void rtw_spinlock_irqsave(void **plock, unsigned long *pirql) +{ + rtw_spin_lock(plock); +} + +void rtw_spinunlock_irqsave(void **plock, unsigned long *pirql) +{ + rtw_spin_unlock(plock); +} + +void rtw_enter_critical_bh(void **plock, unsigned long *pirql) +{ + rtw_spin_lock(plock); +} + +void rtw_exit_critical_bh(void **plock, unsigned long *pirql) +{ + rtw_spin_unlock(plock); +} + +/* Spinlocks End */ + +/* mqueue.h Wrapper Start */ + +int rtw_init_xqueue(void **queue, + const char *name, uint32_t size, uint32_t len) +{ + struct mq_attr attr; + struct file *mq; + int ret; + mq = malloc(sizeof(struct file)); + if (!mq) + { + return -ENOMEM; + } + + attr.mq_maxmsg = len; + attr.mq_msgsize = size; + attr.mq_curmsgs = 0; + attr.mq_flags = 0; + ret = file_mq_open(mq, name, O_RDWR | O_CREAT, 0644, &attr); + if (ret < 0) + { + free(mq); + return -ENOMEM; + } + + *queue = mq; + return 0; +} + +int rtw_push_to_xqueue(void **queue, void *message, uint32_t timeout_ms) +{ + struct file *mq = *queue; + struct mq_attr attr; + file_mq_getattr(mq, &attr); + return file_mq_send(mq, message, attr.mq_msgsize, 1); +} + +int rtw_pop_from_xqueue(void **queue, void *message, uint32_t timeout_ms) +{ + struct file *mq = *queue; + struct mq_attr attr; + unsigned int prio; + file_mq_getattr(mq, &attr); + return !file_mq_receive(mq, message, attr.mq_msgsize, &prio); +} + +int rtw_deinit_xqueue(void **queue) +{ + struct file *mq = *queue; + int ret; + ret = file_mq_close(mq); + if (ret >= 0) + { + free(mq); + } + + return ret; +} + +/* mqueue.h Wrapper End */ + +/* time.h Wrapper Start */ + +uint32_t rtw_get_current_time(void) +{ + return clock(); +} + +uint32_t rtw_systime_to_ms(uint32_t systime) +{ + return TICK2MSEC(systime); +} + +uint32_t rtw_systime_to_sec(uint32_t systime) +{ + return TICK2SEC(systime); +} + +uint32_t rtw_ms_to_systime(uint32_t ms) +{ + return MSEC2TICK(ms); +} + +uint32_t rtw_sec_to_systime(uint32_t sec) +{ + return SEC2TICK(sec); +} + +void rtw_yield_os(void) +{ + sched_yield(); +} + +void rtw_usleep_os(int us) +{ + usleep(us); +} + +void rtw_msleep_os(int ms) +{ + rtw_usleep_os(ms * 1000); +} + +void rtw_mdelay_os(int ms) +{ + rtw_msleep_os(ms); +} + +void rtw_udelay_os(int us) +{ + rtw_usleep_os(us); +} + +int32_t rtw_get_passing_time_ms(uint32_t start) +{ + return rtw_systime_to_ms(rtw_get_current_time() - start); +} + +int32_t rtw_get_time_interval_ms(uint32_t start, uint32_t end) +{ + return rtw_systime_to_ms(end - start); +} + +/* time.h Wrapper End */ + +/* Atomic Operation Start */ + +void ATOMIC_SET(atomic_t *v, int i) +{ + v->counter = i; +} + +int ATOMIC_READ(atomic_t *v) +{ + return v->counter; +} + +void ATOMIC_ADD(atomic_t *v, int i) +{ + save_and_cli(); + v->counter += i; + restore_flags(); +} + +void ATOMIC_SUB(atomic_t *v, int i) +{ + save_and_cli(); + v->counter -= i; + restore_flags(); +} + +void ATOMIC_INC(atomic_t *v) +{ + ATOMIC_ADD(v, 1); +} + +void ATOMIC_DEC(atomic_t *v) +{ + ATOMIC_SUB(v, 1); +} + +int ATOMIC_ADD_RETURN(atomic_t *v, int i) +{ + int temp; + save_and_cli(); + temp = v->counter; + temp += i; + v->counter = temp; + restore_flags(); + return temp; +} + +int ATOMIC_SUB_RETURN(atomic_t *v, int i) +{ + int temp; + save_and_cli(); + temp = v->counter; + temp -= i; + v->counter = temp; + restore_flags(); + return temp; +} + +int ATOMIC_INC_RETURN(atomic_t *v) +{ + return ATOMIC_ADD_RETURN(v, 1); +} + +int ATOMIC_DEC_RETURN(atomic_t *v) +{ + return ATOMIC_SUB_RETURN(v, 1); +} + +int ATOMIC_DEC_AND_TEST(atomic_t *v) +{ + return ATOMIC_DEC_RETURN(v) == 0; +} + +/* Atomic Operation End */ + +/* stdlib.h Wrapper Start */ + +static unsigned int __div64_32(uint64_t *n, unsigned int base) +{ + uint64_t rem = *n; + uint64_t b = base; + uint64_t res; + uint64_t d = 1; + unsigned int high = rem >> 32; + res = 0; + if (high >= base) + { + high /= base; + res = (uint64_t) high << 32; + rem -= (uint64_t)(high * base) << 32; + } + + while ((uint64_t)b > 0 && b < rem) + { + b = b + b; + d = d + d; + } + + do + { + if (rem >= b) + { + rem -= b; + res += d; + } + + b >>= 1; + d >>= 1; + } + while (d); + *n = res; + return rem; +} + +uint64_t rtw_modular64(uint64_t x, uint64_t y) +{ + unsigned int __base = (y); + unsigned int __rem; + if (((x) >> 32) == 0) + { + __rem = (unsigned int)(x) % __base; + (x) = (unsigned int)(x) / __base; + } + + else + { + __rem = __div64_32(&(x), __base); + } + + return __rem; +} + +static int arc4random(void) +{ + uint32_t res = rtw_get_current_time(); + static unsigned long rtw_seed = 0xdeadb00b; + rtw_seed = ((rtw_seed & 0x007f00ff) << 7) ^ + ((rtw_seed & 0x0f80ff00) >> 8) ^ + (res << 13) ^ (res >> 9); + return (int)rtw_seed; +} + +int rtw_get_random_bytes(void *dst, uint32_t size) +{ + unsigned int ranbuf; + unsigned int *lp; + int i; + int count; + count = size / sizeof(unsigned int); + lp = (unsigned int *)dst; + for (i = 0; i < count; i++) + { + lp[i] = arc4random(); + size -= sizeof(unsigned int); + } + + if (size > 0) + { + ranbuf = arc4random(); + memcpy(&lp[i], &ranbuf, size); + } + + return 0; +} + +/* stdlib.h Wrapper End */ + +/* Thread Wrapper Start */ + +static int nuttx_task_hook(int argc, FAR char *argv[]) +{ + struct task_struct *task; + struct nthread_wrapper *wrap; + task = (FAR struct task_struct *) + ((uintptr_t)strtoul(argv[1], NULL, 0)); + if (!task || !task->priv) + { + return 0; + } + + wrap = task->priv; + if (wrap->func) + { + wrap->func(wrap->thctx); + } + + return 0; +} + +int rtw_create_task(struct task_struct *task, const char *name, + uint32_t stack_size, uint32_t priority, + thread_func_t func, void *thctx) +{ + struct nthread_wrapper *wrap; + char *argv[2]; + char arg1[16]; + int pid; + snprintf(arg1, 16, "0x%" PRIxPTR, (uintptr_t)task); + argv[0] = arg1; + argv[1] = NULL; + wrap = malloc(sizeof(*wrap)); + if (!wrap) + { + return -ENOMEM; + } + + wrap->func = func; + wrap->thctx = thctx; + task->name = name; + task->priv = wrap; + if (!strcmp(name, "rtw_recv_tasklet")) + { + stack_size = + CONFIG_IEEE80211_REALTEK_AMEBAZ_RECV_STACKSIZE / sizeof(int); + } + + pid = kthread_create(name, + SCHED_PRIORITY_DEFAULT + priority, + stack_size * sizeof(int), + nuttx_task_hook, argv); + if (pid < 0) + { + free(wrap); + return pid; + } + + wrap->pid = pid; + return 1; +} + +void rtw_delete_task(struct task_struct *task) +{ + struct nthread_wrapper *wrap = task->priv; + if (kill(wrap->pid, SIGKILL)) + { + return; + } + + free(wrap); + task->priv = NULL; +} + +void rtw_set_priority_task(struct task_struct *task, + unsigned int newpriority) +{ +} + +int rtw_get_priority_task(struct task_struct *task) +{ +} + +void rtw_suspend_task(struct task_struct *task) +{ +} + +void rtw_resume_task(struct task_struct *task) +{ +} + +/* Thread Wrapper End */ + +/* Timer Wrapper Start */ + +void *rtw_timer_create(const signed char *pctimername, + unsigned long xtimerperiodinticks, + uint32_t uxautoreload, + void *pvtimerid, + thread_func_t pxcallbackfunction) +{ + struct ntimer_wrapper *wrap; + wrap = calloc(1, sizeof(*wrap)); + if (!wrap) + { + return NULL; + } + + wrap->callback = pxcallbackfunction; + return wrap; +} + +uint32_t rtw_timer_stop(void *xtimer, + unsigned long xblocktime) +{ + struct ntimer_wrapper *wrap = xtimer; + if (!work_available(&wrap->work)) + { + work_cancel(LPWORK, &wrap->work); + } + + return 1; +} + +uint32_t rtw_timer_delete(void *xtimer, + unsigned long xblocktime) +{ + struct ntimer_wrapper *wrap = xtimer; + rtw_timer_stop(xtimer, xblocktime); + free(wrap); + return 1; +} + +uint32_t rtw_timer_is_timer_active(void *xtimer) +{ + struct ntimer_wrapper *wrap = xtimer; + return !work_available(&wrap->work); +} + +uint32_t rtw_timer_change_period(void *xtimer, + unsigned long xnewperiod, + unsigned long xblocktime) +{ + struct ntimer_wrapper *wrap = xtimer; + if (work_available(&wrap->work)) + { + work_queue(LPWORK, &wrap->work, wrap->callback, wrap, xnewperiod); + } + + return 1; +} + +void *rtw_timer_get_id(void *xtimer) +{ + return xtimer; +} + +uint32_t rtw_timer_start(void *xtimer, unsigned long xblocktime) +{ + return rtw_timer_change_period(xtimer, 0, xblocktime); +} + +uint32_t rtw_timer_start_from_isr(void *xtimer, + long *pxhigherprioritytaskwoken) +{ + return rtw_timer_start(xtimer, 0); +} + +uint32_t rtw_timer_stop_from_isr(void *xtimer, + long *pxhigherprioritytaskwoken) +{ + return rtw_timer_stop(xtimer, 0); +} + +uint32_t rtw_timer_reset_from_isr(void *xtimer, + long *pxhigherprioritytaskwoken) +{ + return rtw_timer_start(xtimer, 0); +} + +uint32_t rtw_timer_change_period_from_isr(void *xtimer, + unsigned long xnewperiod, + long *pxhigherprioritytaskwoken) +{ + return rtw_timer_change_period(xtimer, xnewperiod, 0); +} + +uint32_t rtw_timer_reset(void *xtimer, unsigned long xblocktime) +{ + return rtw_timer_start(xtimer, 0); +} + +/* Timer Wrapper End */ + +/* List Wrapper Start */ + +static void _list_add(struct list_head *newitem, + struct list_head *prev, + struct list_head *next) +{ + next->prev = newitem; + newitem->next = next; + newitem->prev = prev; + prev->next = newitem; +} + +static void list_add(struct list_head *newitem, struct list_head *head) +{ + _list_add(newitem, head, head->next); +} + +static void list_add_tail(struct list_head *newitem, struct list_head *head) +{ + _list_add(newitem, head->prev, head); +} + +static void list_del(struct list_head *prev, struct list_head *next) +{ + next->prev = prev; + prev->next = next; +} + +void rtw_list_insert_head(struct list_head *plist, struct list_head *phead) +{ + list_add(plist, phead); +} + +void rtw_list_insert_tail(struct list_head *plist, struct list_head *phead) +{ + list_add_tail(plist, phead); +} + +void rtw_list_delete(struct list_head *plist) +{ + list_del(plist->prev, plist->next); + plist->next = plist->prev = plist; +} + +void rtw_init_listhead(struct list_head *list) +{ + list->next = list->prev = list; +} + +uint32_t rtw_is_list_empty(struct list_head *phead) +{ + return phead->next == phead; +} + +/* List Wrapper End */ + +/* Queue Wrapper Start */ + +void rtw_init_queue(_queue *pqueue) +{ + rtw_init_listhead(&(pqueue->queue)); + rtw_spinlock_init(&(pqueue->lock)); +} + +uint32_t rtw_queue_empty(_queue *pqueue) +{ + return (rtw_is_list_empty(&(pqueue->queue))); +} + +uint32_t rtw_end_of_queue_search(struct list_head *head, + struct list_head *plist) +{ + return (head == plist); +} + +/* Queue Wrapper End */ + +/* Device lock Wrapper Start */ + +static uint32_t mutex_init; +static void *device_mutex[5]; +static void device_mutex_init(uint32_t device) +{ + irqstate_t status; + if (!(mutex_init & (1 << device))) + { + status = enter_critical_section(); + if (!(mutex_init & (1 << device))) + { + rtw_mutex_init(&device_mutex[device]); + mutex_init |= (1 << device); + } + + leave_critical_section(status); + } +} + +void device_mutex_lock(uint32_t device) +{ + device_mutex_init(device); + rtw_mutex_get(&device_mutex[device]); +} + +void device_mutex_unlock(uint32_t device) +{ + device_mutex_init(device); + rtw_mutex_put(&device_mutex[device]); +} + +/* Device lock Wrapper End */ + +/* malloc.h Wrapper Start */ + +uint32_t rtw_get_free_heap_size(void) +{ + struct mallinfo mem; + mem = mallinfo(); + return mem.arena; +} + +/* malloc.h Wrapper End */ + +/* Unnecessary Start */ + +void init_mem_monitor(struct list_head *pmem_table, + int *used_num) +{ +} + +void deinit_mem_monitor(struct list_head *pmem_table, + int *used_num) +{ +} + +int rtw_netif_queue_stopped(void *pnetdev) +{ + return 0; +} + +void rtw_netif_wake_queue(void *pnetdev) +{ +} + +void rtw_netif_start_queue(void *pnetdev) +{ +} + +void rtw_netif_stop_queue(void *pnetdev) +{ +} + +void flush_signals_thread(void) +{ +} + +void rtw_wakeup_task(struct task_struct *task) +{ +} + +void rtw_thread_enter(char *name) +{ +} + +void rtw_thread_exit(void) +{ +} + +uint8_t rtw_get_scheduler_state(void) +{ + return 1; /* OS_SCHEDULER_RUNNING */ +} + +long xtask_get_scheduler_state(void) +{ + return 2; /* taskSCHEDULER_RUNNING */ +} + +void rtw_cpu_lock(void) +{ +} + +void rtw_cpu_unlock(void) +{ +} + +void rtw_create_secure_context(uint32_t n) +{ +} + +void rtw_acquire_wakelock(void) +{ +} + +void rtw_release_wakelock(void) +{ +} + +void rtw_wakelock_timeout(uint32_t ms) +{ +} + +void cli(void) +{ +} + +uint32_t xtask_get_tick_count(void) +{ + return rtw_get_current_time(); +} + +char *pctask_get_name(void *xtasktoquery) +{ + return NULL; +} + +/* Unnecessary End */ + +/* Legacy Start */ + +const struct osdep_service_ops osdep_service = +{ + .rtw_vmalloc = rtw_vmalloc, + .rtw_zvmalloc = rtw_zvmalloc, + .rtw_vmfree = rtw_vmfree, + .rtw_malloc = rtw_malloc, + .rtw_zmalloc = rtw_zmalloc, + .rtw_mfree = rtw_mfree, + .rtw_memcpy = rtw_memcpy, + .rtw_memcmp = rtw_memcmp, + .rtw_memset = rtw_memset, + .rtw_init_sema = rtw_init_sema, + .rtw_free_sema = rtw_free_sema, + .rtw_up_sema = rtw_up_sema, + .rtw_up_sema_from_isr = rtw_up_sema_from_isr, + .rtw_down_timeout_sema = rtw_down_timeout_sema, + .rtw_mutex_init = rtw_mutex_init, + .rtw_mutex_free = rtw_mutex_free, + .rtw_mutex_get = rtw_mutex_get, + .rtw_mutex_get_timeout = rtw_mutex_get_timeout, + .rtw_mutex_put = rtw_mutex_put, + .rtw_enter_critical = rtw_enter_critical, + .rtw_exit_critical = rtw_exit_critical, + .rtw_enter_critical_from_isr = rtw_enter_critical, + .rtw_exit_critical_from_isr = rtw_exit_critical, + .rtw_enter_critical_bh = NULL, + .rtw_exit_critical_bh = NULL, + .rtw_enter_critical_mutex = rtw_enter_critical_mutex, + .rtw_exit_critical_mutex = rtw_exit_critical_mutex, + .rtw_cpu_lock = rtw_cpu_lock, + .rtw_cpu_unlock = rtw_cpu_unlock, + .rtw_spinlock_init = rtw_spinlock_init, + .rtw_spinlock_free = rtw_spinlock_free, + .rtw_spin_lock = rtw_spin_lock, + .rtw_spin_unlock = rtw_spin_unlock, + .rtw_spinlock_irqsave = rtw_spinlock_irqsave, + .rtw_spinunlock_irqsave = rtw_spinunlock_irqsave, + .rtw_init_xqueue = rtw_init_xqueue, + .rtw_push_to_xqueue = rtw_push_to_xqueue, + .rtw_pop_from_xqueue = rtw_pop_from_xqueue, + .rtw_deinit_xqueue = rtw_deinit_xqueue, + .rtw_get_current_time = rtw_get_current_time, + .rtw_systime_to_ms = rtw_systime_to_ms, + .rtw_systime_to_sec = rtw_systime_to_sec, + .rtw_ms_to_systime = rtw_ms_to_systime, + .rtw_sec_to_systime = rtw_sec_to_systime, + .rtw_msleep_os = rtw_msleep_os, + .rtw_usleep_os = rtw_usleep_os, + .rtw_mdelay_os = rtw_msleep_os, + .rtw_udelay_os = rtw_usleep_os, + .rtw_yield_os = rtw_yield_os, + .ATOMIC_SET = ATOMIC_SET, + .ATOMIC_READ = ATOMIC_READ, + .ATOMIC_ADD = ATOMIC_ADD, + .ATOMIC_SUB = ATOMIC_SUB, + .ATOMIC_INC = ATOMIC_INC, + .ATOMIC_DEC = ATOMIC_DEC, + .ATOMIC_ADD_RETURN = ATOMIC_ADD_RETURN, + .ATOMIC_SUB_RETURN = ATOMIC_SUB_RETURN, + .ATOMIC_INC_RETURN = ATOMIC_INC_RETURN, + .ATOMIC_DEC_RETURN = ATOMIC_DEC_RETURN, + .rtw_modular64 = rtw_modular64, + .rtw_get_random_bytes = rtw_get_random_bytes, + .rtw_get_free_heap_size = rtw_get_free_heap_size, + .rtw_create_task = rtw_create_task, + .rtw_delete_task = rtw_delete_task, + .rtw_wakeup_task = NULL, + .rtw_thread_enter = rtw_thread_enter, + .rtw_thread_exit = rtw_thread_exit, + .rtw_timer_create = rtw_timer_create, + .rtw_timer_delete = rtw_timer_delete, + .rtw_timer_is_timer_active = rtw_timer_is_timer_active, + .rtw_timer_stop = rtw_timer_stop, + .rtw_timer_change_period = rtw_timer_change_period, + .rtw_timer_get_id = rtw_timer_get_id, + .rtw_timer_start = rtw_timer_start, + .rtw_timer_start_from_isr = rtw_timer_start_from_isr, + .rtw_timer_stop_from_isr = rtw_timer_stop_from_isr, + .rtw_timer_reset_from_isr = rtw_timer_reset_from_isr, + .rtw_timer_change_period_from_isr = rtw_timer_change_period_from_isr, + .rtw_timer_reset = rtw_timer_reset, + .rtw_acquire_wakelock = rtw_acquire_wakelock, + .rtw_release_wakelock = rtw_release_wakelock, + .rtw_wakelock_timeout = rtw_wakelock_timeout, + .rtw_get_scheduler_state = rtw_get_scheduler_state, + .rtw_create_secure_context = rtw_create_secure_context, +}; + +/* Legacy End */ + diff --git a/arch/arm/src/rtl8720c/amebaz_depend.h b/arch/arm/src/rtl8720c/amebaz_depend.h new file mode 100644 index 00000000000..ca5cf15e9e4 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_depend.h @@ -0,0 +1,181 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_depend.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DEPEND_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DEPEND_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +typedef struct __queue _queue; +typedef void (*thread_func_t)(void *context); +typedef struct +{ + volatile int counter; +} atomic_t; +struct list_head +{ + struct list_head *next; + struct list_head *prev; +}; +struct __queue +{ + struct list_head queue; + void *lock; +}; +struct task_struct +{ + const char *name; + void *priv; + void *wsema; + void *tsema; + uint32_t blocked; + uint32_t running; +}; +struct nthread_wrapper +{ + int pid; + thread_func_t func; + void *thctx; +}; +struct ntimer_wrapper +{ + struct work_s work; + void (*callback)(void *context); +}; +struct osdep_service_ops +{ + uint8_t *(*rtw_vmalloc)(uint32_t n); + uint8_t *(*rtw_zvmalloc)(uint32_t n); + void (*rtw_vmfree)(uint8_t *pbuf, uint32_t n); + uint8_t *(*rtw_malloc)(uint32_t n); + uint8_t *(*rtw_zmalloc)(uint32_t n); + void (*rtw_mfree)(uint8_t *pbuf, uint32_t n); + void (*rtw_memcpy)(void *dst, void *src, uint32_t n); + int (*rtw_memcmp)(void *dst, void *src, uint32_t n); + void (*rtw_memset)(void *pbuf, int c, uint32_t n); + void (*rtw_init_sema)(void **sema, int init_val); + void (*rtw_free_sema)(void **sema); + void (*rtw_up_sema)(void **sema); + void (*rtw_up_sema_from_isr)(void **sema); + uint32_t (*rtw_down_timeout_sema)(void **sema, uint32_t timeout); + void (*rtw_mutex_init)(void **pmutex); + void (*rtw_mutex_free)(void **pmutex); + void (*rtw_mutex_get)(void **pmutex); + int (*rtw_mutex_get_timeout)(void **pmutex, uint32_t timeout_ms); + void (*rtw_mutex_put)(void **pmutex); + void (*rtw_enter_critical)(void **plock, unsigned long *pirql); + void (*rtw_exit_critical)(void **plock, unsigned long *pirql); + void (*rtw_enter_critical_from_isr)(void **plock, unsigned long *pirql); + void (*rtw_exit_critical_from_isr)(void **plock, unsigned long *pirql); + void (*rtw_enter_critical_bh)(void **plock, unsigned long *pirql); + void (*rtw_exit_critical_bh)(void **plock, unsigned long *pirql); + int (*rtw_enter_critical_mutex)(void **pmutex, unsigned long *pirql); + void (*rtw_exit_critical_mutex)(void **pmutex, unsigned long *pirql); + void (*rtw_cpu_lock)(void); + void (*rtw_cpu_unlock)(void); + void (*rtw_spinlock_init)(void **plock); + void (*rtw_spinlock_free)(void **plock); + void (*rtw_spin_lock)(void **plock); + void (*rtw_spin_unlock)(void **plock); + void (*rtw_spinlock_irqsave)(void **plock, unsigned long *pirql); + void (*rtw_spinunlock_irqsave)(void **plock, unsigned long *pirql); + int (*rtw_init_xqueue)(void **queue, const char *name, uint32_t size, + uint32_t len); + int (*rtw_push_to_xqueue)(void **queue, void *message, + uint32_t timeout_ms); + int (*rtw_pop_from_xqueue)(void **queue, void *message, + uint32_t timeout_ms); + int (*rtw_deinit_xqueue)(void **queue); + uint32_t (*rtw_get_current_time)(void); + uint32_t (*rtw_systime_to_ms)(uint32_t systime); + uint32_t (*rtw_systime_to_sec)(uint32_t systime); + uint32_t (*rtw_ms_to_systime)(uint32_t ms); + uint32_t (*rtw_sec_to_systime)(uint32_t sec); + void (*rtw_msleep_os)(int ms); + void (*rtw_usleep_os)(int us); + void (*rtw_mdelay_os)(int ms); + void (*rtw_udelay_os)(int us); + void (*rtw_yield_os)(void); + void (*ATOMIC_SET)(atomic_t *v, int i); + int (*ATOMIC_READ)(atomic_t *v); + void (*ATOMIC_ADD)(atomic_t *v, int i); + void (*ATOMIC_SUB)(atomic_t *v, int i); + void (*ATOMIC_INC)(atomic_t *v); + void (*ATOMIC_DEC)(atomic_t *v); + int (*ATOMIC_ADD_RETURN)(atomic_t *v, int i); + int (*ATOMIC_SUB_RETURN)(atomic_t *v, int i); + int (*ATOMIC_INC_RETURN)(atomic_t *v); + int (*ATOMIC_DEC_RETURN)(atomic_t *v); + uint64_t (*rtw_modular64)(uint64_t x, uint64_t y); + int (*rtw_get_random_bytes)(void *dst, uint32_t size); + uint32_t (*rtw_get_free_heap_size)(void); + int (*rtw_create_task)(struct task_struct *task, const char *name, + uint32_t stack_size, + uint32_t priority, thread_func_t func, void *thctx); + void (*rtw_delete_task)(struct task_struct *task); + void (*rtw_wakeup_task)(struct task_struct *task); + void (*rtw_thread_enter)(char *name); + void (*rtw_thread_exit)(void); + void *(*rtw_timer_create)(const signed char *pctimername, + unsigned long xtimerperiodinticks, + uint32_t uxautoreload, + void *pvtimerid, + thread_func_t pxcallbackfunction); + uint32_t (*rtw_timer_delete)(void *xtimer, unsigned long xblocktime); + uint32_t (*rtw_timer_is_timer_active)(void *xtimer); + uint32_t (*rtw_timer_stop)(void *xtimer, unsigned long xblocktime); + uint32_t (*rtw_timer_change_period)(void *xtimer, unsigned long xnewperiod, + unsigned long xblocktime); + void *(*rtw_timer_get_id)(void *xtimer); + uint32_t (*rtw_timer_start)(void *xtimer, unsigned long xblocktime); + uint32_t (*rtw_timer_start_from_isr)(void *xtimer, + long *pxhigherprioritytaskwoken); + uint32_t (*rtw_timer_stop_from_isr)(void *xtimer, + long *pxhigherprioritytaskwoken); + uint32_t (*rtw_timer_reset_from_isr) (void *xtimer, + long *pxhigherprioritytaskwoken); + uint32_t (*rtw_timer_change_period_from_isr) (void *xtimer, + unsigned long xnewperiod, + long *pxhigherprioritytaskwoken); + uint32_t (*rtw_timer_reset)(void *xtimer, unsigned long xblocktime); + void (*rtw_acquire_wakelock)(void); + void (*rtw_release_wakelock)(void); + void (*rtw_wakelock_timeout)(uint32_t ms); + uint8_t (*rtw_get_scheduler_state)(void); + void (*rtw_create_secure_context)(uint32_t n); +}; +#endif diff --git a/arch/arm/src/rtl8720c/amebaz_driver.c b/arch/arm/src/rtl8720c/amebaz_driver.c new file mode 100644 index 00000000000..871a6847b02 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_driver.c @@ -0,0 +1,1195 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_driver.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include "amebaz_netdev.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AMEBAZ_SCAN_TIMEOUT_TICK (10 * CLOCKS_PER_SEC) +#define AMEBAZ_CONNECT_TIMEOUT_TICK (10 * CLOCKS_PER_SEC) +#define AMEBAZ_DEVICE_COUNT (2) +#define AMEBAZ_SCAN_ENTRY_COUNT (5) +#define AMEBAZ_DEFAULT_COUNTRY "CN" +#define SIOCDEVPRIVATE 0x89f0 +#define SIOCGIWPRIVPASSPHRASE 0x8bfc +#define SIOCSIWPRIVCOUNTRY 0x8bfd +#define SIOCSIWPRIVAPESSID 0x8bfe +#define SIOCSIWPRIVPASSPHRASE 0x8bff +struct _sockaddr_t +{ + uint8_t sa_len; + uint8_t sa_family; + char sa_data[14]; +}; + +static struct amebaz_dev_s *gp_wlan_dev[AMEBAZ_DEVICE_COUNT + 1]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +static void amebaz_state_timeout(wdparm_t arg) +{ + FAR struct amebaz_state_s *state = (FAR struct amebaz_state_s *)arg; + if (state->status < AMEBAZ_STATUS_RUN) + { + return; + } + + state->status = AMEBAZ_STATUS_TIMEOUT; + nxsem_post(&state->mutex); +} + +static int amebaz_state_run(FAR struct amebaz_state_s *state, int32_t delay) +{ + if (state->status == AMEBAZ_STATUS_RUN) + { + return -EBUSY; + } + + state->status = AMEBAZ_STATUS_RUN; + return wd_start(&state->timeout, delay, + amebaz_state_timeout, (wdparm_t)state); +} + +static int amebaz_state_wait(FAR struct amebaz_state_s *state) +{ + int ret = 0; + while (state->status == AMEBAZ_STATUS_RUN) + { + ret = nxsem_wait_uninterruptible(&state->mutex); + if (ret != 0) + { + break; + } + } + + return ret; +} + +static void amebaz_state_post(FAR struct amebaz_state_s *state, int status) +{ + int _status = state->status; + state->status = status; + if (_status == AMEBAZ_STATUS_RUN) + { + wd_cancel(&state->timeout); + nxsem_post(&state->mutex); + } +} + +static void amebaz_state_deinit(FAR struct amebaz_state_s *state) +{ + wd_cancel(&state->timeout); +} + +static int amebaz_state_init(FAR struct amebaz_state_s *state) +{ + if (nxsem_init(&state->mutex, 0, 0) != OK) + { + return -ENOMEM; + } + + state->status = AMEBAZ_STATUS_DISABLED; + return 0; +} + +void amebaz_wl_scan_handler(int index, union iwreq_data *wrqu, char *extra) +{ + FAR struct amebaz_dev_s *priv = gp_wlan_dev[index]; + FAR struct amebaz_state_s *state = &priv->scan; + rtw_scan_result_t *res, *cache, *tmp; + rtw_scan_result_t ap_res; + rtw_scan_ap_result_t *ap; + struct iwreq iwr; + int i; + int j; + if (state->status != AMEBAZ_STATUS_RUN) + { + return; + } + + if (wrqu->data.pointer == NULL) + { + memset(&iwr, 0, sizeof(iwr)); + snprintf(iwr.ifr_name, sizeof(iwr.ifr_name), "wlan%d", index); + iwr.u.data.pointer = priv->scan_data; + iwr.u.data.length = AMEBAZ_SCAN_AP_COUNT * sizeof(rtw_scan_result_t); + if (rltk_wlan_control(SIOCGIWSCAN, &iwr) != 0 || + iwr.u.data.flags != 1) + { + amebaz_state_post(state, AMEBAZ_STATUS_DONE); + return; + } + + ap = iwr.u.data.pointer; + ap_res.signal_strength = ap->signal_strength; + ap_res.bss_type = 0; + ap_res.security = ap->security; + ap_res.wps_type = ap->wps_type; + ap_res.channel = ap->channel; + ap_res.SSID.len = ap->len - sizeof(*ap) + 1; + memcpy(ap_res.SSID.val, ap->SSID, ap_res.SSID.len); + memcpy(ap_res.BSSID.octet, ap->BSSID, IFHWADDRLEN); + ap_res.SSID.val[ap_res.SSID.len - 1] = '\0'; + memcpy(priv->scan_data, &ap_res, sizeof(ap_res)); + priv->scan_count = 1; + amebaz_state_post(state, AMEBAZ_STATUS_DONE); + return; + } + + for (i = 0; i < wrqu->data.length / sizeof(rtw_scan_result_t); i++) + { + res = ((rtw_scan_result_t **)wrqu->data.pointer)[i]; + for (j = 0; j < priv->scan_count; j++) + { + cache = &priv->scan_data[j]; + if (memcmp(cache->BSSID.octet, res->BSSID.octet, IFHWADDRLEN)) + { + continue; + } + + if (cache->signal_strength < res->signal_strength) + { + memcpy(cache, res, sizeof(rtw_scan_result_t)); + } + + break; + } + + if (j != priv->scan_count) + { + continue; + } + + if (priv->scan_count >= AMEBAZ_SCAN_AP_COUNT) + { + tmp = NULL; + for (j = 0; j < priv->scan_count; j++) + { + cache = &priv->scan_data[j]; + if (!tmp || cache->signal_strength < tmp->signal_strength) + { + tmp = cache; + } + } + + memcpy(tmp, res, sizeof(rtw_scan_result_t)); + } + + else + { + cache = &priv->scan_data[priv->scan_count++]; + memcpy(cache, res, sizeof(rtw_scan_result_t)); + } + } +} + +static void amebaz_wl_post_connection_event(struct amebaz_dev_s *priv, + int status) +{ + FAR struct amebaz_state_s *state = &priv->conn; + if (status == AMEBAZ_STATUS_DONE) + { + netdev_carrier_on(&priv->dev); + } + + else + { + netdev_carrier_off(&priv->dev); + } + + amebaz_state_post(state, status); +} + +void amebaz_wl_connection_handler(int index, + union iwreq_data *wrqu, char *extra) +{ + const unsigned char fourway_done[] = "WPA/WPA2 handshake done"; + const unsigned char no_assoc_network[] = + "No Assoc Network After Scan Done"; + FAR struct amebaz_dev_s *priv = gp_wlan_dev[0]; + FAR struct amebaz_state_s *state = &priv->conn; + unsigned char null_mac[IFHWADDRLEN] = + { + }; + + bool mac_avalid; + if (gp_wlan_dev[1]->conn.status == AMEBAZ_STATUS_RUN) + { + priv = gp_wlan_dev[1]; + } + + mac_avalid = memcmp(wrqu->ap_addr.sa_data, null_mac, sizeof(null_mac)); + if (extra) + { + if (!memcmp(fourway_done, extra, sizeof(fourway_done))) + { + amebaz_wl_post_connection_event(priv, AMEBAZ_STATUS_DONE); + } + + else if (!memcmp(no_assoc_network, extra, sizeof(no_assoc_network)) || + !mac_avalid) + { + amebaz_wl_post_connection_event(priv, AMEBAZ_STATUS_DISABLED); + } + } + + else if (priv->assoc.alg == IW_ENCODE_ALG_NONE || + priv->mode == RTW_MODE_AP || priv->mode == RTW_MODE_STA_AP) + { + if (mac_avalid) + { + amebaz_wl_post_connection_event(priv, AMEBAZ_STATUS_DONE); + } + + else + { + amebaz_wl_post_connection_event(priv, AMEBAZ_STATUS_DISABLED); + } + } + + else if (state->status == AMEBAZ_STATUS_DONE && !mac_avalid) + { + amebaz_wl_post_connection_event(priv, AMEBAZ_STATUS_DISABLED); + } +} + +void amebaz_wl_netif_info_handler(int index, void *dev, unsigned char *addr) +{ + FAR struct amebaz_dev_s *priv = gp_wlan_dev[index]; + if (!priv || index != priv->devnum) + { + return; + } + + memcpy(priv->dev.d_mac.ether.ether_addr_octet, addr, IFHWADDRLEN); +} + +void amebaz_wl_notify_rx_handler(int index, unsigned int len) +{ + FAR struct amebaz_dev_s *priv = gp_wlan_dev[index]; + if (!priv || index != priv->devnum || !len) + { + return; + } + + amebaz_netdev_notify_receive(priv, index, len); +} + +static int amebaz_wl_set_channels(struct amebaz_dev_s *priv, + struct iw_freq *freqs, + uint8_t num_channels) +{ + uint8_t param[12 + 1 + 15 * 2] = + { + "PartialScan" + }; + + struct iwreq iwr = + { + }; + + int i; + if (!freqs || num_channels == 0) + { + return OK; + } + + if (num_channels > 15) + { + return -EINVAL; + } + + *(param + 12) = num_channels; + for (i = 0; i < num_channels; i++) + { + *(param + 13 + i) = freqs[i].m; + *(param + 13 + num_channels + i) = PSCAN_ENABLE; + } + + iwr.u.data.pointer = param; + iwr.u.data.length = 12 + 1 + num_channels * 2; + snprintf(iwr.ifr_name, IFNAMSIZ, "wlan%d", priv->devnum); + return rltk_wlan_control(SIOCDEVPRIVATE, &iwr); +} + +int amebaz_wl_start_scan(struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + enum + { + RTW_SCAN_COMMAMD = 0x01 + }; + + FAR struct amebaz_state_s *state = &priv->scan; + int scan_type = IW_SCAN_TYPE_ACTIVE; + int bss_type = RTW_BSS_TYPE_ANY; + struct iw_scan_req *req; + void *pointer = NULL; + uint16_t length; + int essid_len; + int ret; + iwr->u.data.flags = scan_type | (bss_type << 8); + if (iwr->u.data.pointer != NULL && + iwr->u.data.length == sizeof(*req)) + { + req = iwr->u.data.pointer; + ret = amebaz_wl_set_channels(priv, + req->channel_list, req->num_channels); + if (ret < 0) + { + return ret; + } + + essid_len = req->essid_len; + memcpy(priv->scan_data, &essid_len, sizeof(int)); + memcpy((char *)priv->scan_data + sizeof(int), + req->essid, req->essid_len); + pointer = iwr->u.data.pointer; + length = iwr->u.data.length; + iwr->u.data.pointer = priv->scan_data; + iwr->u.data.length = AMEBAZ_SCAN_AP_COUNT * sizeof(rtw_scan_result_t); + } + + else + { + iwr->u.data.flags |= RTW_SCAN_COMMAMD << 4; + } + + priv->scan_count = 0; + ret = amebaz_state_run(state, AMEBAZ_SCAN_TIMEOUT_TICK); + if (ret < 0) + { + return ret; + } + + ret = rltk_wlan_control(SIOCSIWSCAN, iwr); + if (pointer) + { + iwr->u.data.pointer = pointer; + iwr->u.data.length = length; + } + + if (ret < 0) + { + state->status = AMEBAZ_STATUS_DISABLED; + } + + return ret; +} + +static char *amebaz_wl_iwe_add_event(char *stream, char *stop, + struct iw_event *iwe, int event_len) +{ + if (stream + event_len > stop) + { + return stream; + } + + iwe->len = event_len; + return stream + event_len; +} + +static int amebaz_wl_format_scan_results(struct amebaz_dev_s *priv, + struct iwreq *iwr) +{ + rtw_scan_result_t *cache; + struct iw_event *iwe; + char *start; + char *stop; + int i; + start = iwr->u.data.pointer; + stop = (char *)iwr->u.data.pointer + iwr->u.data.length; + for (i = 0; i < priv->scan_count; i++) + { + cache = &priv->scan_data[i]; + iwe = (struct iw_event *)start; + iwe->cmd = SIOCGIWAP; + iwe->u.ap_addr.sa_family = ARPHRD_ETHER; + memcpy(&iwe->u.ap_addr.sa_data, cache->BSSID.octet, IFHWADDRLEN); + start = amebaz_wl_iwe_add_event(start, stop, iwe, IW_EV_LEN(ap_addr)); + iwe = (struct iw_event *)start; + iwe->cmd = SIOCGIWESSID; + iwe->u.essid.flags = 0; + iwe->u.essid.length = cache->SSID.len; + iwe->u.essid.pointer = (FAR void *)sizeof(iwe->u.essid); + memcpy(&iwe->u.essid + 1, cache->SSID.val, cache->SSID.len); + start = amebaz_wl_iwe_add_event(start, stop, iwe, + IW_EV_LEN(essid) + ((cache->SSID.len + 3) & -4)); + iwe = (struct iw_event *)start; + iwe->cmd = IWEVQUAL; + iwe->u.qual.qual = 0; + iwe->u.qual.level = cache->signal_strength; + iwe->u.qual.noise = 0; + iwe->u.qual.updated |= IW_QUAL_DBM; + start = amebaz_wl_iwe_add_event(start, stop, iwe, IW_EV_LEN(qual)); + iwe = (struct iw_event *)start; + iwe->cmd = SIOCGIWFREQ; + iwe->u.freq.e = 0; + iwe->u.freq.m = cache->channel; + start = amebaz_wl_iwe_add_event(start, stop, iwe, IW_EV_LEN(freq)); + iwe = (struct iw_event *)start; + iwe->cmd = SIOCGIWENCODE; + iwe->u.data.flags = IW_ENCODE_DISABLED; + iwe->u.data.length = 0; + iwe->u.essid.pointer = NULL; + start = amebaz_wl_iwe_add_event(start, stop, iwe, IW_EV_LEN(data)); + } + + return start - (char *)iwr->u.data.pointer; +} + +int amebaz_wl_get_scan_results(struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + FAR struct amebaz_state_s *state = &priv->scan; + int request_size; + int ret = OK; + if (state->status == AMEBAZ_STATUS_RUN) + { + ret = -EAGAIN; + goto exit_failed; + } + + if (state->status != AMEBAZ_STATUS_DONE) + { + ret = -EINVAL; + goto exit_failed; + } + + if ((ret = amebaz_state_wait(state)) < 0) + { + goto exit_failed; + } + + if (priv->scan_count <= 0) + { + ret = OK; + iwr->u.data.length = 0; + goto exit_sem_post; + } + + request_size = priv->scan_count * + AMEBAZ_SCAN_ENTRY_COUNT * + sizeof(struct iw_event); + if (iwr->u.data.pointer == NULL || + iwr->u.data.length < request_size) + { + ret = -E2BIG; + iwr->u.data.pointer = NULL; + iwr->u.data.length = request_size; + goto exit_sem_post; + } + + iwr->u.data.length = amebaz_wl_format_scan_results(priv, iwr); +exit_sem_post: + nxsem_post(&state->mutex); +exit_failed: + if (ret < 0) + { + iwr->u.data.length = 0; + } + + return ret; +} + +int amebaz_wl_process_command(struct amebaz_dev_s *priv, int cmd, void *req) +{ + return rltk_wlan_control(cmd, req); +} + +int amebaz_wl_set_encode_ext(struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + struct iw_encode_ext *ext; + struct iwreq _iwr = + { + }; + + int ret; + iwr->u.encoding.flags = IW_ENCODE_INDEX & 1; + iwr->u.encoding.flags |= IW_ENCODE_TEMP; + ret = rltk_wlan_control(SIOCSIWENCODEEXT, iwr); + if (ret < 0) + { + return ret; + } + + ext = iwr->u.encoding.pointer; + _iwr.u.data.pointer = (void *)ext->key; + _iwr.u.data.length = ext->key_len; + _iwr.u.data.flags = (ext->key_len != 0); + memcpy(_iwr.ifr_name, iwr->ifr_name, strlen(iwr->ifr_name)); + ret = rltk_wlan_control(SIOCSIWPRIVPASSPHRASE, &_iwr); + if (ret < 0) + { + return ret; + } + + priv->assoc.alg = ext->alg; + priv->assoc.mask |= AMEBAZ_ASSOCIATE_ALG; + return OK; +} + +int amebaz_wl_get_encode_ext(struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + struct iw_encode_ext *ext; + struct iwreq _iwr = + { + }; + + int ret; + ret = rltk_wlan_control(SIOCGIWENCODEEXT, iwr); + if (ret < 0) + { + return ret; + } + + ext = iwr->u.encoding.pointer; + _iwr.u.data.pointer = (void *)ext->key; + memcpy(_iwr.ifr_name, iwr->ifr_name, strlen(iwr->ifr_name)); + ret = rltk_wlan_control(SIOCGIWPRIVPASSPHRASE, &_iwr); + if (ret < 0) + { + return ret; + } + + ext->key_len = _iwr.u.data.length; + ext->key[ext->key_len] = '\0'; + return ret; +} + +static int amebaz_wl_add_custom_ie(FAR struct amebaz_dev_s *priv, + int devnum) +{ + struct rtw_custom_ie_t + { + uint8_t *ie; + uint8_t type; + }; + + enum + { + PROBE_REQ = 0x0001, + PROBE_RSP = 0x0002, + BEACON = 0x0004, + ASSOC_REQ = 0x0008, + }; + + uint8_t ie[8] = + { + 7, 6, 'C', 'N', '\0', 1, 13, 20 + }; + + struct rtw_custom_ie_t cie = + { + ie, PROBE_RSP | BEACON + }; + + char param[16] = "SetCusIE"; + uint32_t *cmd = (uint32_t *)(param + strlen(param) + 1); + struct iwreq iwr = + { + }; + + memcpy(&ie[2], priv->country, 2); + *cmd = (intptr_t)&cie; + *(cmd + 1) = (intptr_t)1; + iwr.u.data.pointer = param; + iwr.u.data.length = sizeof(param); + snprintf(iwr.ifr_name, IFNAMSIZ, "wlan%d", devnum); + return rltk_wlan_control(SIOCDEVPRIVATE, &iwr); +} + +int amebaz_wl_associate(FAR struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + FAR struct amebaz_state_s *state = &priv->conn; + rtw_network_info_t info = + { + }; + + rtw_network_info_t *pinfo; + struct iw_freq freq = + { + }; + + struct _sockaddr_t *addr; + bool bssid_conn = false; + struct iwreq _iwr = + { + }; + + char *data; + int ret; + if (priv->mode == RTW_MODE_STA) + { + if (priv->assoc.mask != + (AMEBAZ_ASSOCIATE_MASK & ~AMEBAZ_ASSOCIATE_ALG) && + priv->assoc.mask != AMEBAZ_ASSOCIATE_MASK) + { + return 0; + } + + if ((priv->assoc.mask & AMEBAZ_ASSOCIATE_ALG) == 0) + { + priv->assoc.alg = IW_ENCODE_ALG_NONE; + } + + snprintf(_iwr.ifr_name, IFNAMSIZ, "wlan%d", priv->devnum); + addr = (struct _sockaddr_t *)&_iwr.u.ap_addr; + addr->sa_family = ARPHRD_ETHER; + data = addr->sa_data; + memcpy(_iwr.u.ap_addr.sa_data, priv->assoc.mac.octet, IFHWADDRLEN); + freq.m = priv->assoc.channel; + if (amebaz_wl_set_channels(priv, &freq, 1) < 0) + { + return -EINVAL; + } + + data[IFHWADDRLEN] = '#'; + data[IFHWADDRLEN + 1] = '@'; + info.ssid.len = priv->assoc.ssid.len; + memcpy(info.ssid.val, priv->assoc.ssid.val, info.ssid.len); + memcpy(info.bssid.octet, priv->assoc.mac.octet, IFHWADDRLEN); + switch (priv->assoc.alg) + { + case IW_ENCODE_ALG_NONE: + info.security_type = RTW_SECURITY_OPEN; + break; + case IW_ENCODE_ALG_WEP: + info.security_type = RTW_SECURITY_WEP_PSK; + break; + case IW_ENCODE_ALG_CCMP: + default: + info.security_type = RTW_SECURITY_WPA2_MIXED_PSK; + } + + pinfo = &info; + memcpy(data + (IFHWADDRLEN + 2), &pinfo, sizeof(pinfo)); + bssid_conn = true; + } + + ret = amebaz_state_run(state, AMEBAZ_CONNECT_TIMEOUT_TICK); + if (ret < 0) + { + return ret; + } + + if ((priv->mode == RTW_MODE_AP && priv->devnum == 0) || + (priv->mode == RTW_MODE_STA_AP && priv->devnum == 1)) + { + ret = amebaz_wl_add_custom_ie(priv, priv->devnum); + if (ret < 0) + { + wlwarn("unable to update the custom ie\n"); + } + } + + if (priv->mode == RTW_MODE_AP || priv->mode == RTW_MODE_STA_AP) + { + ret = rltk_wlan_control(SIOCSIWPRIVAPESSID, iwr); + } + + else if (priv->mode == RTW_MODE_STA) + { + if (bssid_conn) + { + ret = rltk_wlan_control(SIOCSIWAP, &_iwr); + } + + else + { + ret = rltk_wlan_control(SIOCSIWESSID, iwr); + } + } + + else + { + ret = -EINVAL; + } + + if (ret < 0) + { + goto exit_failed; + } + + if ((ret = amebaz_state_wait(state)) < 0) + { + goto exit_failed; + } + + if (state->status == AMEBAZ_STATUS_TIMEOUT) + { + ret = -ETIME; + } + + else if (state->status != AMEBAZ_STATUS_DONE) + { + ret = -ENXIO; + } + +exit_failed: + if (ret < 0) + { + amebaz_state_post(state, AMEBAZ_STATUS_DISABLED); + priv->assoc.alg = IW_ENCODE_ALG_NONE; + } + + else + { + state->status = AMEBAZ_STATUS_DONE; + } + + priv->assoc.mask = 0; + return ret; +} + +int amebaz_wl_set_ssid(FAR struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + if (!iwr->u.essid.flags) + { + return rltk_wlan_control(SIOCSIWESSID, iwr); + } + + memcpy(priv->assoc.ssid.val, iwr->u.essid.pointer, iwr->u.essid.length); + priv->assoc.ssid.len = iwr->u.essid.length; + priv->assoc.mask |= AMEBAZ_ASSOCIATE_SSID; + return amebaz_wl_associate(priv, iwr); +} + +int amebaz_wl_set_bssid(FAR struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + struct _sockaddr_t *addr = (struct _sockaddr_t *)&iwr->u.ap_addr; + unsigned char null_mac[IFHWADDRLEN] = + { + }; + + char *data; + addr->sa_family = ARPHRD_ETHER; + data = addr->sa_data; + if (!memcmp(data, null_mac, sizeof(null_mac))) + { + /* set MAC address last byte to 1 + * since driver will filter the mac with all 0x00 or 0xff + */ + + data[IFHWADDRLEN - 1] = 1; + } + + else + { + memcpy(priv->assoc.mac.octet, data, IFHWADDRLEN); + priv->assoc.mask |= AMEBAZ_ASSOCIATE_BSSID; + return amebaz_wl_associate(priv, iwr); + } + + return rltk_wlan_control(SIOCSIWAP, iwr); +} + +static int amebaz_wl_disable_powersave(int devnum) +{ + char control[7 + 6] = "pm_set"; + struct iwreq iwr = + { + }; + + snprintf(iwr.ifr_name, IFNAMSIZ, "wlan%d", devnum); + /* Command format: + * Entry[0...n]: + * 1. Type + * 2. Set/Unset + * 3. Value + */ + + enum + { + AMEBA_PMSET_MODE_IPS, + AMEBA_PMSET_MODE_LPS, + AMEBA_PMSET_MODE_TDMA, + AMEBA_PMSET_MODE_DTIM, + AMEBA_PMSET_MODE_BEACON, + AMEBA_PMSET_MODE_LPS_LEVEL, + AMEBA_PMSET_MODE_LPS_THRESHOLD, + AMEBA_PMSET_MODE_LPS_RF, + AMEBA_PMSET_MODE_RESUME, + }; + + control[7] = AMEBA_PMSET_MODE_IPS; + control[8] = 1; + control[9] = 0; + control[10] = AMEBA_PMSET_MODE_LPS; + control[11] = 1; + control[12] = 0; + iwr.u.data.pointer = control; + iwr.u.data.length = sizeof(control); + return rltk_wlan_control(SIOCDEVPRIVATE, &iwr); +} + +int amebaz_wl_set_mode(FAR struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + int mode; + int ret; + int count; + int i; + if (priv->devnum == 1) + { + if (iwr->u.mode == IW_MODE_MASTER) + { + mode = RTW_MODE_STA_AP; + } + + else + { + return -EINVAL; + } + } + + else + { + if (rltk_wlan_running(1)) + { + mode = RTW_MODE_STA; + ret = 0; + goto errout; + } + + if (iwr->u.mode == IW_MODE_MASTER) + { + mode = RTW_MODE_AP; + } + + else if (iwr->u.mode == IW_MODE_INFRA) + { + mode = RTW_MODE_STA; + } + + else + { + return -EINVAL; + } + } + + if (priv->mode == mode) + { + return OK; + } + + if (priv->mode != RTW_MODE_NONE) + { + if (priv->mode == RTW_MODE_STA && mode == RTW_MODE_AP) + { + if (priv->conn.status == AMEBAZ_STATUS_DONE) + { + return -EINVAL; + } + } + + else if (priv->mode == RTW_MODE_AP && mode == RTW_MODE_STA) + { + return -EINVAL; + } + } + + if (priv->mode == RTW_MODE_NONE && + rltk_wlan_running(priv->devnum) == false) + { + if (priv->devnum == 1 && rltk_wlan_running(0) == true) + { + ret = rltk_set_mode_prehandle(RTW_MODE_STA, + RTW_MODE_STA_AP, "wlan0"); + if (ret < 0) + { + goto errout; + } + + rtw_msleep_os(50); + ret = rltk_set_mode_posthandle(RTW_MODE_STA, + RTW_MODE_STA_AP, "wlan0"); + if (ret < 0) + { + goto errout; + } + } + + else + { + count = (mode == RTW_MODE_STA_AP) ? AMEBAZ_DEVICE_COUNT : 1; + for (i = 0; i < count; i++) + { + ret = rltk_wlan_init(i, mode); + if (ret < 0) + { + goto errout; + } + + extern void up_irq_attach_workaround(void); + up_irq_attach_workaround(); + } + + for (i = 0; i < count; i++) + { + ret = rltk_wlan_start(i); + if (ret < 0) + { + goto errout; + } + } + + while (!rltk_wlan_running(priv->devnum)) + { + usleep(1000); + } + + ret = amebaz_wl_disable_powersave(0); + if (ret < 0) + { + goto errout; + } + } + } + + ret = rltk_wlan_control(SIOCSIWMODE, iwr); +errout: + if (ret) + { + rltk_wlan_deinit(); + mode = RTW_MODE_NONE; + } + + priv->mode = mode; + return ret; +} + +int amebaz_wl_set_country(FAR struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + const char *country = iwr->u.essid.pointer; + int32_t cc = RTW_COUNTRY_WORLD1; + int ret; + if (!strncmp(country, "CN", 2)) + { + } + + else if (!strncmp(country, "CA", 2)) + { + cc = RTW_COUNTRY_CA; + } + + else if (!strncmp(country, "CO", 2)) + { + cc = RTW_COUNTRY_CO; + } + + else if (!strncmp(country, "DO", 2)) + { + cc = RTW_COUNTRY_DO; + } + + else if (!strncmp(country, "GT", 2)) + { + cc = RTW_COUNTRY_GT; + } + + else if (!strncmp(country, "MX", 2)) + { + cc = RTW_COUNTRY_MX; + } + + else if (!strncmp(country, "PA", 2)) + { + cc = RTW_COUNTRY_PA; + } + + else if (!strncmp(country, "PR", 2)) + { + cc = RTW_COUNTRY_PR; + } + + else if (!strncmp(country, "US", 2)) + { + cc = RTW_COUNTRY_US; + } + + else if (!strncmp(country, "TW", 2)) + { + cc = RTW_COUNTRY_TW; + } + + else if (!strncmp(country, "JP", 2)) + { + cc = RTW_COUNTRY_JP; + } + + else if (!strncmp(country, "IL", 2)) + { + cc = RTW_COUNTRY_IL; + } + + iwr->u.essid.pointer = NULL; + iwr->u.param.value = cc; + ret = rltk_wlan_control(SIOCSIWPRIVCOUNTRY, iwr); + if (ret == 0) + { + memcpy(priv->country, country, 2); + } + + iwr->u.essid.pointer = (void *)country; + return ret; +} + +int amebaz_wl_set_freq(FAR struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + priv->assoc.channel = iwr->u.freq.m; + priv->assoc.mask |= AMEBAZ_ASSOCIATE_CHANNEL; + return 0; +} + +int amebaz_wl_get_freq(FAR struct amebaz_dev_s *priv, struct iwreq *iwr) +{ + int ret; + ret = rltk_wlan_control(SIOCGIWFREQ, iwr); + if (ret == 0) + { + iwr->u.freq.m = iwr->u.freq.i; + } + + return ret; +} + +static struct amebaz_dev_s *amebaz_allocate_device(int devnum) +{ + FAR struct amebaz_dev_s *priv; + int ret; + priv = (FAR struct amebaz_dev_s *)kmm_zalloc(sizeof(*priv)); + if (!priv) + { + return NULL; + } + + ret = amebaz_state_init(&priv->scan); + ret |= amebaz_state_init(&priv->conn); + if (ret) + { + kmm_free(priv); + return NULL; + } + + memcpy(priv->country, AMEBAZ_DEFAULT_COUNTRY, 2); + priv->devnum = devnum; + return priv; +} + +static void amebaz_free_device(FAR struct amebaz_dev_s *priv) +{ + amebaz_state_deinit(&priv->scan); + amebaz_state_deinit(&priv->conn); + kmm_free(priv); +} + +static int amebaz_wl_on(int mode) +{ + int ret = -1; + for (int i = 0; i < 2; i++) + { + ret = rltk_wlan_init(i, mode); + if (ret < 0) + { + return ret; + } + } + + extern void up_irq_attach_workaround(void); + up_irq_attach_workaround(); + for (int i = 0; i < 2; i++) + { + ret = rltk_wlan_start(i); + if (ret < 0) + { + return ret; + } + + while (!rltk_wlan_running(gp_wlan_dev[i]->devnum)) + { + usleep(1000); + } + } + + ret = amebaz_wl_disable_powersave(0); + return ret; +} + +int amebaz_wl_initialize(unsigned char mode) +{ + FAR struct amebaz_dev_s *priv; + struct iwreq wrq = + { + }; + + int ret; + int i; + for (i = 0; i < 2; i++) + { + priv = amebaz_allocate_device(i); + if (!priv) + { + ret = -ENOMEM; + goto free_dev; + } + + ret = amebaz_netdev_register(priv); + if (ret < 0) + { + amebaz_free_device(priv); + goto free_dev; + } + + gp_wlan_dev[i] = priv; + } + + if (mode == RTW_MODE_STA_AP) + { + return amebaz_wl_on(RTW_MODE_STA_AP); + } + + else + { + strncpy(wrq.ifr_name, "wlan0", IFNAMSIZ); + wrq.u.mode = IW_MODE_INFRA; + return amebaz_wl_set_mode(gp_wlan_dev[0], &wrq); + } + +free_dev: + for (i = 0; gp_wlan_dev[i]; i++) + { + netdev_unregister(&gp_wlan_dev[i]->dev); + amebaz_free_device(gp_wlan_dev[i]); + gp_wlan_dev[i] = NULL; + } + + return ret; +} + diff --git a/arch/arm/src/rtl8720c/amebaz_driver.h b/arch/arm/src/rtl8720c/amebaz_driver.h new file mode 100644 index 00000000000..ed97f0b681f --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_driver.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_driver.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DRIVER_H +#define __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DRIVER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include "amebaz_wlan.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AMEBAZ_SCAN_AP_COUNT (10) +enum +{ + AMEBAZ_STATUS_DONE = 0, + AMEBAZ_STATUS_DISABLED, + AMEBAZ_STATUS_RUN, + AMEBAZ_STATUS_TIMEOUT, +}; + +enum +{ + AMEBAZ_ASSOCIATE_SSID = 0x1, + AMEBAZ_ASSOCIATE_BSSID = 0x2, + AMEBAZ_ASSOCIATE_ALG = 0x4, + AMEBAZ_ASSOCIATE_CHANNEL = 0x8, + AMEBAZ_ASSOCIATE_MASK = 0xf, +}; + +struct amebaz_state_s +{ + sem_t mutex; + struct wdog_s timeout; + int status; +}; + +struct amebaz_associate_s +{ + rtw_ssid_t ssid; + rtw_mac_t mac; + uint8_t alg; + unsigned int channel; + uint8_t mask; +}; + +struct amebaz_dev_s +{ + struct net_driver_s dev; + int devnum; + struct amebaz_state_s scan; + struct amebaz_state_s conn; + struct work_s pollwork; + struct wdog_s txpoll; + struct sk_buff *curr; + int mode; + struct amebaz_associate_s assoc; + rtw_scan_result_t scan_data[AMEBAZ_SCAN_AP_COUNT]; + unsigned int scan_count; + unsigned char country[2]; +}; + +int amebaz_wl_start_scan(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_get_scan_results(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_set_encode_ext(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_get_encode_ext(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_set_ssid(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_set_bssid(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_set_mode(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_set_country(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_get_freq(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_set_freq(FAR struct amebaz_dev_s *priv, + struct iwreq *iwr); +int amebaz_wl_process_command(FAR struct amebaz_dev_s *priv, + int cmd, void *req); +void amebaz_wl_connection_handler(int index, + union iwreq_data *wrqu, char *extra); +void amebaz_wl_scan_handler(int index, + union iwreq_data *wrqu, char *extra); +void amebaz_wl_netif_info_handler(int index, void *dev, + unsigned char *addr); +void amebaz_wl_notify_rx_handler(int index, unsigned int len); + +#endif /* __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DRIVER_H */ diff --git a/arch/arm/src/rtl8720c/amebaz_firmware.c b/arch/arm/src/rtl8720c/amebaz_firmware.c new file mode 100644 index 00000000000..8a1b1eb4fb1 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_firmware.c @@ -0,0 +1,1405 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_firmware.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ARCH_CHIP_AMEBAZ_D_CUT +const unsigned char rtl_vendor_command[] = +{ + 0xfc, 0x63, 0x07, 0x62, 0x06, 0xd1, 0x05, 0xd0, 0x64, 0xb2, 0x40, 0x9a, + 0x64, 0xb3, 0x65, 0xb0, 0x42, 0x34, 0x82, 0x34, 0x80, 0xcb, 0x64, 0xb3, + 0x40, 0xcb, 0x64, 0xb2, 0x40, 0xea, 0x00, 0x69, 0x63, 0xb3, 0x64, 0xb2, + 0x60, 0xda, 0x64, 0xb3, 0x64, 0xb2, 0x60, 0xda, 0x64, 0xb3, 0x65, 0xb2, + 0x60, 0xda, 0x65, 0xb3, 0x65, 0xb2, 0x60, 0xda, 0x65, 0xb3, 0x66, 0xb2, + 0x60, 0xda, 0x66, 0xb3, 0x66, 0xb2, 0x60, 0xda, 0x66, 0xb3, 0x67, 0xb2, + 0x60, 0xda, 0x67, 0xb3, 0x67, 0xb2, 0x60, 0xda, 0xa0, 0xf0, 0x4b, 0xa0, + 0xa0, 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0xc0, 0x60, 0x02, 0x36, 0x21, + 0x62, 0x02, 0xce, 0x17, 0x08, 0x03, 0x29, 0x29, 0x42, 0x03, 0x01, 0x09, + 0x56, 0x03, 0x0d, 0x33, 0x5a, 0x03, 0x45, 0x00, 0x30, 0x06, 0x26, 0x67, + 0x32, 0x06, 0x12, 0x5d, 0x34, 0x06, 0x7f, 0xe8, 0x36, 0x06, 0xc8, 0x36, + 0x34, 0x01, 0x00, 0x00, 0x64, 0x01, 0x44, 0x3b, 0x66, 0x01, 0xd2, 0x76, + 0x08, 0x00, 0xb0, 0x00, 0x66, 0x00, 0x59, 0x40, 0x0a, 0x06, 0xdb, 0x50, + 0x0c, 0x06, 0xe2, 0x7b, 0x0e, 0x06, 0x6a, 0xc0, 0x10, 0x06, 0x8c, 0x55, + 0x12, 0x06, 0x0a, 0x28, 0x14, 0x06, 0x27, 0x01, 0x02, 0x02, 0x6a, 0x7c, + 0x6d, 0x61, 0x00, 0x00, 0xa4, 0x54, 0xa8, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0x10, 0x01, 0x00, 0x51, 0x04, 0xfd, 0x77 +}; + +unsigned int rtl_vendor_command_size = sizeof(rtl_vendor_command); +#endif + +#ifdef CONFIG_ARCH_CHIP_AMEBAZ_C_CUT +const unsigned char rtl_vendor_command[] = +{ + 0xfc, 0x63, 0x07, 0x62, 0x06, 0xd1, 0x05, 0xd0, 0x55, 0xb2, 0x40, 0x9a, + 0x55, 0xb3, 0x56, 0xb0, 0x42, 0x34, 0x82, 0x34, 0x80, 0xcb, 0x55, 0xb3, + 0x40, 0xcb, 0x55, 0xb2, 0x40, 0xea, 0x00, 0x69, 0x54, 0xb3, 0x55, 0xb2, + 0x60, 0xda, 0x55, 0xb3, 0x55, 0xb2, 0x60, 0xda, 0x55, 0xb3, 0x56, 0xb2, + 0x60, 0xda, 0x56, 0xb3, 0x56, 0xb2, 0x60, 0xda, 0x56, 0xb3, 0x57, 0xb2, + 0x60, 0xda, 0x57, 0xb3, 0x57, 0xb2, 0x60, 0xda, 0x57, 0xb3, 0x58, 0xb2, + 0x60, 0xda, 0xa0, 0xf0, 0x4b, 0xa0, 0xa0, 0xf0, 0x6a, 0xa0, 0x40, 0x32, + 0x6d, 0xea, 0xa0, 0xf0, 0x6c, 0xa0, 0x60, 0x33, 0x60, 0x33, 0x4d, 0xeb, + 0xa0, 0xf0, 0x4d, 0xa0, 0x00, 0xf6, 0x40, 0x32, 0x6d, 0xea, 0x08, 0xf0, + 0x01, 0x6b, 0x6b, 0xeb, 0x6c, 0xea, 0x42, 0x33, 0xa0, 0xf0, 0x4a, 0xc0, + 0xa0, 0xf0, 0x6b, 0xc0, 0x00, 0xf6, 0x42, 0x32, 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0x89, 0xe2, 0x40, 0xa2, + 0x0f, 0x22, 0x02, 0x6a, 0x04, 0xd2, 0x0b, 0xb2, 0x05, 0xd2, 0x06, 0xd4, + 0x07, 0xd5, 0x02, 0x6c, 0x60, 0xf2, 0x1a, 0x6e, 0x49, 0xf6, 0x16, 0x6f, + 0x07, 0xb2, 0x40, 0xea, 0xfd, 0x6d, 0x03, 0x10, 0x06, 0xb2, 0x40, 0xea, + 0x00, 0x65, 0x09, 0x97, 0x00, 0xef, 0x05, 0x63, 0x00, 0x3c, 0x12, 0x80, + 0xc4, 0x3e, 0x10, 0x80, 0x4d, 0x26, 0x01, 0x80, 0xe1, 0x9a, 0x00, 0x80, + 0xfd, 0x63, 0x05, 0x62, 0x0d, 0xb2, 0x40, 0xea, 0x00, 0x65, 0x0d, 0xb2, + 0x04, 0x6b, 0x65, 0xca, 0x61, 0xf4, 0x01, 0x6b, 0x66, 0xca, 0x21, 0x6b, + 0x0a, 0xb2, 0xe0, 0xf1, 0x63, 0xc2, 0x0a, 0xb2, 0x0a, 0xb3, 0x60, 0xda, + 0x48, 0x6b, 0x62, 0xca, 0x09, 0xb3, 0x66, 0xda, 0x18, 0x6b, 0x6e, 0xca, + 0x05, 0x97, 0x00, 0xef, 0x03, 0x63, 0x00, 0x65, 0x8d, 0x9d, 0x00, 0x80, + 0x68, 0x0c, 0x12, 0x80, 0x18, 0x01, 0x12, 0x80, 0x48, 0x0c, 0x12, 0x80, + 0x1c, 0x3f, 0x10, 0x80, 0xec, 0x3e, 0x10, 0x80, 0xfd, 0x63, 0x05, 0x62, + 0x06, 0xb2, 0x40, 0xea, 0x00, 0x65, 0x6c, 0x6b, 0x6b, 0xeb, 0x05, 0xb2, + 0x20, 0xf1, 0x71, 0xc2, 0x05, 0x97, 0x00, 0xef, 0x03, 0x63, 0x00, 0x65, + 0x05, 0x96, 0x00, 0x80, 0x18, 0x01, 0x12, 0x80, 0xfd, 0x63, 0x05, 0x62, + 0x05, 0xb2, 0x40, 0xea, 0x00, 0x65, 0x05, 0xb2, 0x40, 0xea, 0x00, 0x65, + 0x05, 0x97, 0x00, 0xef, 0x03, 0x63, 0x00, 0x65, 0x81, 0x96, 0x00, 0x80, + 0xf5, 0x38, 0x10, 0x80, 0xfc, 0x63, 0x07, 0x62, 0x06, 0xd1, 0x05, 0xd0, + 0xff, 0x6a, 0x24, 0x67, 0x4c, 0xe9, 0x67, 0x41, 0x4b, 0x4b, 0x0e, 0xb4, + 0x68, 0x33, 0x6d, 0xe4, 0x00, 0x9b, 0x04, 0x6b, 0x85, 0xa0, 0x8c, 0xeb, + 0x4c, 0xeb, 0x0b, 0x23, 0x0a, 0xb2, 0x40, 0x9a, 0x02, 0x6c, 0x78, 0x6d, + 0x40, 0xea, 0x01, 0x6e, 0x40, 0xf0, 0x5c, 0xc8, 0x07, 0xb2, 0x40, 0xea, + 0x91, 0x67, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x00, 0x6a, 0x00, 0xef, + 0x04, 0x63, 0x00, 0x65, 0x80, 0x22, 0x12, 0x80, 0x44, 0x00, 0x12, 0x80, + 0xe9, 0xce, 0x01, 0x80, 0x41, 0x00, 0x00, 0x00, 0x07, 0x00, 0xf8, 0x03, + 0x00, 0xe0, 0x07, 0x00, 0xc0, 0x7f, 0x00, 0x00, 0xad, 0x35, 0x10, 0x80, + 0x65, 0x34, 0x10, 0x80, 0x69, 0x34, 0x10, 0x80, 0xdd, 0x34, 0x10, 0x80, + 0x6d, 0x34, 0x10, 0x80, 0x71, 0x34, 0x10, 0x80, 0x00, 0xf0, 0x20, 0x00, + 0x00, 0x90, 0x4f, 0x03, 0x00, 0xf0, 0x20, 0x00, 0x00, 0x90, 0x6f, 0x03, + 0x00, 0xf0, 0x08, 0x00, 0x02, 0x90, 0x17, 0xf8, 0x34, 0x00, 0x03, 0x10, + 0x36, 0x00, 0x04, 0xe2, 0x38, 0x00, 0x01, 0x31, 0x3a, 0x00, 0xe0, 0x05, + 0x64, 0x00, 0x40, 0x2e, 0x1a, 0x01, 0x16, 0x36, 0x42, 0x02, 0xff, 0x04, + 0x44, 0x02, 0x33, 0x64, 0x16, 0x03, 0x53, 0x76, 0x14, 0x03, 0x00, 0x00, + 0x74, 0x03, 0x86, 0x06, 0x72, 0x03, 0xd1, 0x04, 0x70, 0x03, 0x57, 0x04, + 0x6e, 0x03, 0xde, 0x03, 0x6c, 0x03, 0x6b, 0x03, 0x6a, 0x03, 0x3f, 0x00, + 0x68, 0x03, 0x3f, 0x00, 0x66, 0x03, 0x3f, 0x00, 0x16, 0x00, 0xbe, 0xa6, + 0x40, 0x03, 0x8a, 0x03, 0x3a, 0x02, 0xa6, 0x00, 0x3c, 0x02, 0x7e, 0xc0, + 0x60, 0x02, 0x36, 0x21, 0x62, 0x02, 0xce, 0x17, 0x08, 0x03, 0x29, 0x29, + 0x42, 0x03, 0x01, 0x09, 0x56, 0x03, 0x0d, 0x33, 0x5a, 0x03, 0x45, 0x00, + 0x30, 0x06, 0x26, 0x67, 0x32, 0x06, 0x12, 0x5d, 0x34, 0x06, 0x7f, 0xe8, + 0x36, 0x06, 0xc8, 0x36, 0x34, 0x01, 0x00, 0x00, 0x64, 0x01, 0x44, 0x3b, + 0x66, 0x01, 0xd2, 0x76, 0x08, 0x00, 0xb0, 0x00, 0x66, 0x00, 0x59, 0x40, + 0x0a, 0x06, 0xdb, 0x50, 0x0c, 0x06, 0xf2, 0x7b, 0x10, 0x06, 0x8c, 0x55, + 0x12, 0x06, 0x0a, 0x28, 0x14, 0x06, 0x27, 0x01, 0x02, 0x02, 0x6a, 0x7c, + 0x6d, 0x61, 0x00, 0x00, 0xa4, 0x54, 0xa8, 0x42 +}; + +unsigned int rtl_vendor_command_size = sizeof(rtl_vendor_command); +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/rtl8720c/amebaz_hci_board.c b/arch/arm/src/rtl8720c/amebaz_hci_board.c new file mode 100644 index 00000000000..0015c4df843 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_hci_board.c @@ -0,0 +1,832 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_hci_board.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include "amebaz_hci_board.h" +#include "ameba_efuse.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BT_LGC_EFUSE_LEN 0x20 +#define BT_PHY_EFUSE_LEN 0x12 +#define BT_PHY_EFUSE_BASE 0x100 +#define BT_LGC_EFUSE_OFFSET 0x190 +#define BT_MAC_ADDR_LEN 6 +#define BT_CONFIG_SIGNATURE 0x8723ab55 +#define BT_CONFIG_HEADER_LEN 6 +#define EFUSE_SW_USE_FLASH_PATCH BIT0 +#define EFUSE_SW_BT_FW_LOG BIT1 +#define EFUSE_SW_RSVD BIT2 +#define EFUSE_SW_IQK_HCI_OUT BIT3 +#define EFUSE_SW_UPPERSTACK_SWITCH BIT4 +#define EFUSE_SW_TRACE_SWITCH BIT5 +#define EFUSE_SW_DRIVER_DEBUG_LOG BIT6 +#define EFUSE_SW_RSVD2 BIT7 +#define LEFUSE(x) (x-0x190) +#define FLASH_BT_PARA_ADDR (SYS_DATA_FLASH_BASE + 0xff0) +#define CHECK_SW(x) (HAL_READ32(SPI_FLASH_BASE, FLASH_BT_PARA_ADDR) &x) +#define MERGE_PATCH_ADDRESS 0x110000 +#define LE_ARRAY_TO_UINT16(u16, a) { \ + u16 = ((uint16_t)(*(a + 0)) << 0) + \ + ((uint16_t)(*(a + 1)) << 8); \ + } + +#define LE_ARRAY_TO_UINT32(u32, a) { \ + u32 = ((uint32_t)(*(a + 0)) << 0)+ \ + ((uint32_t)(*(a + 1)) << 8)+ \ + ((uint32_t)(*(a + 2)) << 16)+ \ + ((uint32_t)(*(a + 3)) << 24); \ + } + +#define LE_UINT32_TO_ARRAY(a, u32) { \ + *((uint8_t *)(a) + 0) = (uint8_t)((u32) >> 0); \ + *((uint8_t *)(a) + 1) = (uint8_t)((u32) >> 8); \ + *((uint8_t *)(a) + 2) = (uint8_t)((u32) >> 16); \ + *((uint8_t *)(a) + 3) = (uint8_t)((u32) >> 24); \ + } + +#define LE_STREAM_TO_UINT8(u8, s) { \ + u8 = (uint8_t)(*s); \ + s += 1; \ +} + +#define LE_STREAM_TO_UINT16(u16, s) { \ + u16 = ((uint16_t)(*(s + 0)) << 0) + \ + ((uint16_t)(*(s + 1)) << 8); \ + s += 2; \ +} + +#define LE_UINT16_TO_STREAM(s, u16) { \ + *s++ = (uint8_t)((u16) >> 0); \ + *s++ = (uint8_t)((u16) >> 8); \ +} + +#define LE_STREAM_TO_UINT32(u32, s) { \ + u32 = ((uint32_t)(*(s + 0)) << 0) + \ + ((uint32_t)(*(s + 1)) << 8) + \ + ((uint32_t)(*(s + 2)) << 16) + \ + ((uint32_t)(*(s + 3)) << 24); \ + s += 4; \ +} + +enum _RT_DEV_LOCK_E +{ + RT_DEV_LOCK_EFUSE = 0, + RT_DEV_LOCK_FLASH = 1, + RT_DEV_LOCK_CRYPTO = 2, + RT_DEV_LOCK_PTA = 3, + RT_DEV_LOCK_WLAN = 4, + RT_DEV_LOCK_MAX = 5 +}; + +typedef struct +{ + uint32_t IQK_XX; + uint32_t IQK_YY; + uint16_t IDAC; + uint16_t QDAC; + uint16_t IDAC2; + uint16_t QDAC2; +} IQK_T; + +extern void rtw_msleep_os(int ms); +extern void rtw_mfree(uint8_t *pbuf, uint32_t n); +extern void device_mutex_lock(uint32_t device); +extern void device_mutex_unlock(uint32_t device); +extern uint32_t bt_lok_write(uint16_t idac, + uint16_t qdac, uint16_t idac2, uint16_t qdac2); +extern uint32_t bt_dck_write(uint8_t q_dck, uint8_t i_dck); +extern uint32_t bt_iqk_8710c(IQK_T *cal_data, uint8_t store); +extern uint32_t bt_flatk_8710c(uint16_t txgain_flatk); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t hci_phy_efuse[BT_PHY_EFUSE_LEN] = +{ + 0 +}; + +static uint8_t hci_lgc_efuse[BT_LGC_EFUSE_LEN] = +{ + 0 +}; + +static IQK_T hci_iqk_data = +{ + 0x100, + 0x00, + 0x20, + 0x20, + 0x20, + 0x20 +}; + +static uint8_t *rtl_actual_command = NULL; +static uint32_t rtl_actual_command_size; +extern const uint8_t rtl_vendor_command[]; +extern uint32_t rtl_vendor_command_size; +static uint32_t hci_cfg_baudrate; +static uint8_t rtl_vendor_init_config[] = +{ + 0x55, 0xab, 0x23, 0x87, /* header */ + + 0x32, 0x00, /* Config length: header + len + preload */ + + 0x30, 0x00, 0x06, 0x99, 0x88, 0x77, 0x44, 0x55, 0x66, /* BT MAC address */ + + 0x0c, 0x00, 0x04, 0x04, 0x50, 0xf7, 0x05, /* Baudrate 921600 */ + + 0x18, 0x00, 0x01, 0x5c, /* flow control */ + + 0x94, 0x01, 0x06, 0x0a, 0x08, 0x00, 0x00, 0x2e, 0x07, /* phy flatk */ + + 0x9f, 0x01, 0x05, 0x2a, 0x2a, 0x2a, 0x2a, 0x1c, /* unknow 1 */ + + 0xa4, 0x01, 0x04, 0xfe, 0xfe, 0xfe, 0xfe, /* unknow 2 */ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +static uint32_t cal_bit_shift(uint32_t mask) +{ + uint32_t i; + for (i = 0; i < 31; i++) + { + if ((mask >> i) & 0x1) + { + break; + } + } + + return i; +} + +static void set_reg_val(uint32_t reg, uint32_t mask, uint32_t val) +{ + if (reg % 4) + { + return; + } + + uint32_t data = HAL_READ32(reg, 0); + data = ((data & (~mask)) | (val << cal_bit_shift(mask))); + HAL_WRITE32(reg, 0, data); +} + +static int hci_iqk_phy_efuse_valid(FAR IQK_T *iqk_data) +{ + if ((hci_phy_efuse[3] == 0xff) && + (hci_phy_efuse[4] == 0xff) && + (hci_phy_efuse[5] == 0xff) && + (hci_phy_efuse[6] == 0xff)) + { + /* No Phy Efuse Data */ + + return -EIO; + } + + else + { + /* Phy Efuse Has Data */ + + iqk_data->IQK_XX = hci_phy_efuse[3] | hci_phy_efuse[4] << 8; + iqk_data->IQK_YY = hci_phy_efuse[5] | hci_phy_efuse[6] << 8; + iqk_data->QDAC = hci_phy_efuse[0x0c]; + iqk_data->IDAC = hci_phy_efuse[0x0d]; + iqk_data->QDAC2 = hci_phy_efuse[0x0e]; + iqk_data->IDAC2 = hci_phy_efuse[0x0f]; + return 0; + } +} + +static int hci_iqk_lgc_efuse_valid(FAR IQK_T *iqk_data) +{ + if ((hci_lgc_efuse[0x16] == 0xff) && + (hci_lgc_efuse[0x17] == 0xff) && + (hci_lgc_efuse[0x18] == 0xff) && + (hci_lgc_efuse[0x19] == 0xff)) + { + /* No Lgc Efuse Data */ + + return -EIO; + } + else + { + /* Lgc Efuse Has Data */ + + iqk_data->IQK_XX = (uint32_t)(((uint32_t)hci_lgc_efuse[0x17]) << 8) | + hci_lgc_efuse[0x16]; + iqk_data->IQK_YY = (uint32_t)(((uint32_t)hci_lgc_efuse[0x19]) << 8) | + hci_lgc_efuse[0x18]; + iqk_data->QDAC = hci_lgc_efuse[0x1a]; + iqk_data->IDAC = hci_lgc_efuse[0x1b]; + iqk_data->QDAC2 = hci_lgc_efuse[0x1c]; + iqk_data->IDAC2 = hci_lgc_efuse[0x1d]; + return 0; + } +} + +int hci_check_iqk(void) +{ + IQK_T iqk_data; + + if (!hci_lgc_efuse[LEFUSE(0x1a1)] & BIT0) + { + /* Use Fix Logic Efuse */ + + if (0 == hci_iqk_lgc_efuse_valid(&iqk_data)) + { + bt_lok_write(iqk_data.IDAC, iqk_data.QDAC, iqk_data.IDAC2, + iqk_data.QDAC2); + hci_phy_efuse[0] = 0; + hci_phy_efuse[1] = hci_phy_efuse[1] & (~BIT0); + hci_phy_efuse[3] = iqk_data.IQK_XX & 0xff; + hci_phy_efuse[4] = (iqk_data.IQK_XX >> 8) & 0xff; + hci_phy_efuse[5] = iqk_data.IQK_YY & 0xff; + hci_phy_efuse[6] = (iqk_data.IQK_YY >> 8) & 0xff; + return 0; + } + + /* No Logic Efuse Data */ + + return -EIO; + } + + if (0 == hci_iqk_phy_efuse_valid(&iqk_data)) + { + if (hci_phy_efuse[0] != 0) + { + bt_dck_write(hci_phy_efuse[0x0e], hci_phy_efuse[0x0f]); + } + + bt_lok_write(iqk_data.IDAC, iqk_data.QDAC, iqk_data.IDAC2, + iqk_data.QDAC2); + return 0; + } + + else if (0 == hci_iqk_lgc_efuse_valid(&iqk_data)) + { + bt_lok_write(iqk_data.IDAC, iqk_data.QDAC, iqk_data.IDAC2, + iqk_data.QDAC2); + hci_phy_efuse[0] = 0; + hci_phy_efuse[1] = hci_phy_efuse[1] & (~BIT0); + hci_phy_efuse[3] = iqk_data.IQK_XX & 0xff; + hci_phy_efuse[4] = (iqk_data.IQK_XX >> 8) & 0xff; + hci_phy_efuse[5] = iqk_data.IQK_YY & 0xff; + hci_phy_efuse[6] = (iqk_data.IQK_YY >> 8) & 0xff; + hci_phy_efuse[0x0e] = hci_lgc_efuse[0x1e]; + hci_phy_efuse[0x0f] = hci_lgc_efuse[0x1f]; + bt_dck_write(hci_phy_efuse[0x0e], hci_phy_efuse[0x0f]); + return 0; + } + + else + { + /* No IQK LOK Data, Need Start LOK */ + + return -EIO; + } +} + +int hci_start_iqk(void) +{ + if (_FAIL == bt_iqk_8710c(&hci_iqk_data, 0)) + { + /* IQK Fail, Ensure Connected */ + + return -EIO; + } + + bt_lok_write(hci_iqk_data.IDAC, hci_iqk_data.QDAC, hci_iqk_data.IDAC2, + hci_iqk_data.QDAC2); + hci_phy_efuse[0] = 0; + hci_phy_efuse[1] = hci_phy_efuse[1] & (~BIT0); + hci_phy_efuse[3] = hci_iqk_data.IQK_XX & 0xff; + hci_phy_efuse[4] = (hci_iqk_data.IQK_XX >> 8) & 0xff; + hci_phy_efuse[5] = hci_iqk_data.IQK_YY & 0xff; + hci_phy_efuse[6] = (hci_iqk_data.IQK_YY >> 8) & 0xff; + return 0; +} + +int hci_set_init_config_mac(FAR uint8_t *addr, uint8_t diffvalue) +{ + for (uint8_t i = 0; i < BT_MAC_ADDR_LEN; i++) + { + rtl_vendor_init_config[9 + i] = addr[(BT_MAC_ADDR_LEN - 1) - i]; + } + + rtl_vendor_init_config[9] -= diffvalue; + return 0; +} + +int hci_get_baudrate(FAR uint32_t *bt_baudrate, FAR uint32_t *uart_baudrate) +{ + typedef struct + { + uint32_t bt_baudrate; + uint32_t uart_baudrate; + }baudrate_map; + + const baudrate_map maps[] = + { + {0x0000701d, 115200}, + {0x0252c00a, 230400}, + {0x05f75004, 921600}, + {0x00005004, 1000000}, + {0x04928002, 1500000}, + {0x00005002, 2000000}, + {0x0000b001, 2500000}, + {0x04928001, 3000000}, + {0x052a6001, 3500000}, + {0x00005001, 4000000}, + }; + + uint32_t i; + *bt_baudrate = hci_cfg_baudrate; + for (i = 0; i < sizeof(maps); i++) + { + if (*bt_baudrate == maps[i].bt_baudrate) + { + break; + } + } + + if (i == sizeof(maps)) + { + return -EINVAL; + } + + *uart_baudrate = maps[i].uart_baudrate; + return 0; +} + +int hci_find_fw_patch(uint8_t chipid) +{ +#if 0 + const uint8_t single_patch_signature[4] = + { + 0xfd, + 0x63, + 0x05, + 0x62 + }; + + const uint8_t merged_patch_signature[8] = + { + 0x52, + 0x65, + 0x61, + 0x6c, + 0x74, + 0x65, + 0x63, + 0x68 + }; + + phal_spic_adaptor_t flash; + + /* FIXME: Distiguish Normal and MP Ptach (rltk_bt_get_patch_code) */ + + const uint8_t *fw_patch = rtl_vendor_command; + uint32_t fw_patch_len = rtl_vendor_command_size; + uint32_t fw_patch_offset = 0; + uint32_t lmp_subversion = 0; + uint16_t num_of_patch = 0; + uint16_t chipid_in_fw = 0; + uint8_t i; + if (!CHECK_SW(EFUSE_SW_USE_FLASH_PATCH)) + { + /* Check flash img */ + + uint8_t tmp_patch_head[8]; + hal_flash_stream_read(&flash, MERGE_PATCH_ADDRESS, 8, tmp_patch_head); + if (!memcmp(tmp_patch_head, merged_patch_signature, + sizeof(merged_patch_signature))) + { + /* use the changed patch */ + + hal_flash_stream_read(&flash, MERGE_PATCH_ADDRESS + 8, 4, + (uint8_t *)&lmp_subversion); + hal_flash_stream_read(&flash, MERGE_PATCH_ADDRESS + 12, 2, + (uint8_t *)&num_of_patch); + for (i = 0 ; i < num_of_patch; i++) + { + hal_flash_stream_read(&flash, + MERGE_PATCH_ADDRESS + 0x0e + 2 * i, 2, + (uint8_t *)&chipid_in_fw); + if (chipid_in_fw == chipid) + { + hal_flash_stream_read(&flash, + MERGE_PATCH_ADDRESS + 0x0e \ + + 2 * num_of_patch + 2 * i, + 2, (uint8_t *)&fw_patch_len); + hal_flash_stream_read(&flash, + MERGE_PATCH_ADDRESS + 0x0e \ + + 4 * num_of_patch + 4 * i, + 4, (uint8_t *)&fw_patch_offset); + break; + } + } + + rtl_actual_command = (uint8_t *)rtw_zmalloc(fw_patch_len); + if (!rtl_actual_command) + { + return -EIO; + } + + hal_flash_stream_read(&flash, + MERGE_PATCH_ADDRESS + fw_patch_offset, + fw_patch_len, rtl_actual_command); + LE_UINT32_TO_ARRAY(rtl_actual_command + fw_patch_len - 4, + lmp_subversion); + return 0; + } + } + + if (!memcmp(fw_patch, single_patch_signature, + sizeof(single_patch_signature))) + { + /* Use Single Patch, Do Nothing */ + + rtl_actual_command = fw_patch; + rtl_actual_command_size = fw_patch_len; + } + + else if (!memcmp(fw_patch, merged_patch_signature, + sizeof(merged_patch_signature))) + { + /* Use Merged Patch */ + + LE_ARRAY_TO_UINT32(lmp_subversion, fw_patch + 0x08); + LE_ARRAY_TO_UINT16(num_of_patch, fw_patch + 0x0c); + for (i = 0; i < num_of_patch; i++) + { + LE_ARRAY_TO_UINT16(chipid_in_fw, fw_patch + 0x0e + 2 * i); + if (chipid_in_fw == chipid) + { + LE_ARRAY_TO_UINT16(fw_patch_len, + fw_patch + 0x0e + 2 * num_of_patch + 2 * i); + LE_ARRAY_TO_UINT32(fw_patch_offset, + fw_patch + 0x0e + 4 * num_of_patch + 4 * i); + break; + } + } + + if (i >= num_of_patch) + { + /* No Match Patch Found */ + + return -EIO; + } + + else + { + rtl_actual_command = (uint8_t *)rtw_zmalloc(fw_patch_len); + rtl_actual_command_size = fw_patch_len; + if (!rtl_actual_command) + { + /* Malloc rtl_actual_command failed */ + + return -EIO; + } + + else + { + rtw_memcpy(rtl_actual_command, fw_patch + fw_patch_offset, + fw_patch_len); + LE_UINT32_TO_ARRAY(rtl_actual_command + fw_patch_len - 4, + lmp_subversion); + } + } + } + + else + { + /* Something is Wrong with the Patch */ + + return -EIO; + } + +#else + + /* FIXME: Dummy Here */ + + rtl_actual_command = (uint8_t *)&rtl_vendor_command[0]; + rtl_actual_command_size = rtl_vendor_command_size; +#endif + return 0; +} + +int hci_fetch_command(FAR uint8_t *command) +{ + unsigned int config_size = sizeof(rtl_vendor_init_config); + static unsigned int command_offset; + int fragment_size = 0; + int index; + if (command_offset >= config_size + rtl_actual_command_size) + { + if (rtl_actual_command && rtl_actual_command != rtl_vendor_command) + { + rtw_mfree(rtl_actual_command, rtl_actual_command_size); + } + + return AMEBAZ_COMMAND_DONE; + } + + if (command_offset < rtl_actual_command_size) + { + if (command_offset + AMEBAZ_COMMAND_FRAGMENT_SIZE + > rtl_actual_command_size) + { + fragment_size = rtl_actual_command_size - command_offset; + } + + else + { + fragment_size = AMEBAZ_COMMAND_FRAGMENT_SIZE; + } + + memcpy(command + 5, rtl_actual_command + command_offset, + fragment_size); + command_offset += fragment_size; + } + + if (command_offset >= rtl_actual_command_size) + { + int config_offset = command_offset - rtl_actual_command_size; + int config_len = config_size - config_offset; + if (fragment_size < AMEBAZ_COMMAND_FRAGMENT_SIZE) + { + int free = AMEBAZ_COMMAND_FRAGMENT_SIZE - fragment_size; + int copy_size; + if (config_len > free) + { + copy_size = free; + } + + else + { + copy_size = config_len; + } + + memcpy(command + 5 + fragment_size, + rtl_vendor_init_config + config_offset, copy_size); + command_offset += copy_size; + fragment_size += copy_size; + } + } + + index = (command_offset / AMEBAZ_COMMAND_FRAGMENT_SIZE) - 1; + if (command_offset % AMEBAZ_COMMAND_FRAGMENT_SIZE > 0) + { + index++; + } + + if (command_offset >= config_size + rtl_actual_command_size) + { + index |= 0x80; + } + + command[3] = fragment_size + 1; + command[4] = index; + return AMEBAZ_COMMAND_VALID; +} + +int hci_get_efuse_iqk_data(uint8_t *data) +{ + data[0] = 0x0c; + uint8_t *iqk_data = data + 1; + memcpy(iqk_data, hci_phy_efuse, data[0]); + return 0; +} + +static void hci_read_efuse(void) +{ + uint16_t bt_phy_efuse_base = 0x100; + device_mutex_lock(RT_DEV_LOCK_EFUSE); + + /* Read Phy Efuse */ + + for (int i = 0; i < 16; i++) + { + hal_efuse_read(bt_phy_efuse_base + i, hci_phy_efuse + i, + LDO_OUT_DEFAULT_VOLT); + } + + hal_efuse_read(0xf8, hci_phy_efuse + 16, LDO_OUT_DEFAULT_VOLT); + hal_efuse_read(0xf9, hci_phy_efuse + 17, LDO_OUT_DEFAULT_VOLT); + + /* Read Logic Efuse */ + + ameba_efuse_logical_read(BT_LGC_EFUSE_OFFSET, BT_LGC_EFUSE_LEN, + hci_lgc_efuse); + + device_mutex_unlock(RT_DEV_LOCK_EFUSE); +} + +static int hci_parse_config(void) +{ + uint32_t signature; + uint16_t payload_len; + uint16_t entry_offset; + uint16_t entry_len; + uint8_t *p_entry; + uint8_t *p; + uint8_t *p_len; + uint8_t i; + uint16_t tx_flatk; + p = rtl_vendor_init_config; + p_len = rtl_vendor_init_config + 4; + LE_STREAM_TO_UINT32(signature, p); + LE_STREAM_TO_UINT16(payload_len, p); + if (signature != BT_CONFIG_SIGNATURE) + { + /* Invalid Signature */ + + return -EIO; + } + + if (payload_len != sizeof(rtl_vendor_init_config) - BT_CONFIG_HEADER_LEN) + { + /* Fix the len, just avoid the length is not corect */ + + LE_UINT16_TO_STREAM(p_len, + sizeof(rtl_vendor_init_config) - BT_CONFIG_HEADER_LEN); + } + + p_entry = rtl_vendor_init_config + BT_CONFIG_HEADER_LEN; + while (p_entry < rtl_vendor_init_config + sizeof(rtl_vendor_init_config)) + { + p = p_entry; + LE_STREAM_TO_UINT16(entry_offset, p); + LE_STREAM_TO_UINT8(entry_len, p); + p_entry = p + entry_len; + switch (entry_offset) + { + case 0x000c: + + /* FIXME: MP (If use mp, Set badurate 115200 + * in rtl_vendor_init_config) + */ + + LE_STREAM_TO_UINT32(hci_cfg_baudrate, p); + break; + case 0x0018: + + /* FIXME: MP (If use mp, Clear flowctl in rtl_vendor_init_config) */ + + break; + case 0x0030: + + /* FIXME: Customer use Wi-Fi MAC - 1 as BT ADDR, + * so ignore action here + */ + +#if 0 + if (entry_len == 6) + { + if ((hci_lgc_efuse[0] != 0xff) && (hci_lgc_efuse[1] != 0xff)) + { + for (uint8_t i = 0 ; i < 6; i++) + { + p[i] = hci_lgc_efuse[5 - i]; + } + } + } + +#endif + break; + case 0x194: + if (hci_lgc_efuse[LEFUSE(0x196)] == 0xff) + { + if (!(hci_phy_efuse[2] & BIT0)) + { + tx_flatk = hci_phy_efuse[0xa] | hci_phy_efuse[0xb] << 8; + bt_flatk_8710c(tx_flatk); + } + + break; + } + + else + { + p[0] = hci_lgc_efuse[LEFUSE(0x196)]; + if (hci_lgc_efuse[LEFUSE(0x196)] & BIT1) + { + p[1] = hci_lgc_efuse[LEFUSE(0x197)]; + } + + if (hci_lgc_efuse[LEFUSE(0x196)] & BIT2) + { + p[2] = hci_lgc_efuse[LEFUSE(0x198)]; + p[3] = hci_lgc_efuse[LEFUSE(0x199)]; + tx_flatk = hci_lgc_efuse[LEFUSE(0x198)] + | hci_lgc_efuse[LEFUSE(0x199)] << 8; + bt_flatk_8710c(tx_flatk); + } + + else + { + if (!(hci_phy_efuse[2] & BIT0)) + { + tx_flatk = hci_phy_efuse[0xa] + | hci_phy_efuse[0xb] << 8; + bt_flatk_8710c(tx_flatk); + } + } + + if (hci_lgc_efuse[LEFUSE(0x196)] & BIT5) + { + p[4] = hci_lgc_efuse[LEFUSE(0x19a)]; + p[5] = hci_lgc_efuse[LEFUSE(0x19b)]; + } + } + + break; + case 0x19f: + for (i = 0; i < entry_len; i ++) + { + if (hci_lgc_efuse[LEFUSE(0x19c + i)] != 0xff) + { + p[i] = hci_lgc_efuse[LEFUSE(0x19c + i)]; + } + } + + break; + case 0x1a4: + for (i = 0; i < entry_len; i ++) + { + if (hci_lgc_efuse[LEFUSE(0x1a2 + i)] != 0xff) + { + p[i] = hci_lgc_efuse[LEFUSE(0x1a2 + i)]; + } + } + + break; + default: + break; + } + } + + return 0; +} + +int hci_board_init(void) +{ + /* FIXME: Wi-Fi Coexist, MP, Trace_Setting */ + + hci_read_efuse(); + if (!CHECK_SW(EFUSE_SW_BT_FW_LOG)) + { + set_reg_val(0x400000cc, BIT2 | BIT1 | BIT0, 6); + rtw_msleep_os(5); + set_reg_val(0x400000cc, BIT8, 1); + rtw_msleep_os(5); + } + + if (hci_parse_config()) + { + return -EIO; + } + + return 0; +} + +int hci_board_init_done(void) +{ + /* FIXME: MP */ + + return 0; +} + diff --git a/arch/arm/src/rtl8720c/amebaz_hci_board.h b/arch/arm/src/rtl8720c/amebaz_hci_board.h new file mode 100644 index 00000000000..96133870f69 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_hci_board.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_hci_board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_AMEBA_HCI_BOARD_H +#define __INCLUDE_AMEBA_HCI_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HCI_START_IQK +#define AMEBAZ_COMMAND_FRAGMENT_SIZE (252) +#define AMEBAZ_COMMAND_DONE (0) +#define AMEBAZ_COMMAND_VALID (1) +#define BT_DEFAUT_LMP_SUBVER 0x8710 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int hci_check_iqk(void); +int hci_start_iqk(void); +int hci_set_init_config_mac(FAR uint8_t *addr, uint8_t diffvalue); +int hci_get_baudrate(FAR uint32_t *bt_baudrate, + FAR uint32_t *uart_baudrate); +int hci_find_fw_patch(uint8_t chipid); +int hci_get_efuse_iqk_data(uint8_t *data); +int hci_board_init(void); +int hci_board_init_done(void); + +#endif /* __INCLUDE_AMEBA_FLASH_H */ + diff --git a/arch/arm/src/rtl8720c/amebaz_netdev.c b/arch/arm/src/rtl8720c/amebaz_netdev.c new file mode 100644 index 00000000000..43f30ebf4ce --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_netdev.c @@ -0,0 +1,432 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_netdev.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include "amebaz_netdev.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define WDDELAY (1 * CLK_TCK / 2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +static void amebaz_poll_work(FAR void *arg); +static void amebaz_netdev_notify_tx_done(FAR struct amebaz_dev_s *priv) +{ + work_queue(LPWORK, &priv->pollwork, amebaz_poll_work, priv, 0); +} + +static int amebaz_txpoll(FAR struct net_driver_s *dev) +{ + FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)dev->d_private; + if (priv->dev.d_len > 0) + { +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->dev.d_flags)) +#endif + { + arp_out(&priv->dev); + } + +#endif /* CONFIG_NET_IPv4 */ +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + else +#endif + { + neighbor_out(&priv->dev); + } + +#endif /* CONFIG_NET_IPv6 */ + if (!devif_loopback(&priv->dev)) + { + net_lock(); + if (!priv->curr) + { + net_unlock(); + amebaz_netdev_notify_tx_done(priv); + return false; + } + + DEBUGASSERT(priv->curr->tail == priv->dev.d_buf); + skb_put(priv->curr, priv->dev.d_len); + rltk_wlan_send_skb(priv->devnum, priv->curr); + priv->dev.d_buf = NULL; + priv->curr = NULL; + net_unlock(); + NETDEV_TXPACKETS(&priv->dev); + amebaz_netdev_notify_tx_done(priv); + return true; + } + } + + return false; +} + +static int amebaz_transmit(FAR struct amebaz_dev_s *priv) +{ + struct sk_buff *skb; + skb = rltk_wlan_alloc_skb(priv->dev.d_len); + if (!skb) + { + NETDEV_TXERRORS(&priv->dev); + return -ENOMEM; + } + + NETDEV_TXPACKETS(&priv->dev); + memcpy(skb->tail, priv->dev.d_buf, priv->dev.d_len); + skb_put(skb, priv->dev.d_len); + rltk_wlan_send_skb(priv->devnum, skb); + NETDEV_TXDONE(&priv->dev); + return OK; +} + +static void amebaz_reply(FAR struct amebaz_dev_s *priv) +{ + if (priv->dev.d_len > 0) + { +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->dev.d_flags)) +#endif + { + arp_out(&priv->dev); + } + +#ifdef CONFIG_NET_IPv6 + else + { + neighbor_out(&priv->dev); + } + +#endif + amebaz_transmit(priv); + } +} + +void amebaz_netdev_notify_receive(FAR struct amebaz_dev_s *priv, + int index, unsigned int len) +{ + FAR struct net_driver_s *dev = &priv->dev; + FAR struct eth_hdr_s *hdr; + FAR struct sk_buff *skb; + FAR void *oldbuf; + skb = rltk_wlan_get_recv_skb(index); + if (skb == NULL) + { + return; + } + + if (!IFF_IS_UP(dev->d_flags)) + { + skb_pull(skb, len); + return; + } + + NETDEV_RXPACKETS(&priv->dev); + net_lock(); + oldbuf = priv->dev.d_buf; + hdr = (struct eth_hdr_s *)skb->data; + priv->dev.d_buf = (void *)skb->data; + priv->dev.d_len = len; +#ifdef CONFIG_NET_PKT + pkt_input(&priv->dev); +#endif + if (hdr->type == HTONS(TPID_8021QVLAN)) + { + uint8_t temp_buffer[12]; + memcpy(temp_buffer, skb->data, 12); + memcpy(skb->data + 4, temp_buffer, 12); + priv->dev.d_buf = skb->data = skb->data + 4; + priv->dev.d_len -= 4; + } + +#ifdef CONFIG_NET_IPv4 + if (hdr->type == HTONS(ETHTYPE_IP)) + { + NETDEV_RXIPV4(&priv->dev); + arp_ipin(&priv->dev); + ipv4_input(&priv->dev); + amebaz_reply(priv); + } + + else + { +#endif +#ifdef CONFIG_NET_IPv6 + if (hdr->type == HTONS(ETHTYPE_IP6)) + { + NETDEV_RXIPV6(&priv->dev); + ipv6_input(&priv->dev); + amebaz_reply(priv); + } + + else + { +#endif +#ifdef CONFIG_NET_ARP + if (hdr->type == htons(ETHTYPE_ARP)) + { + arp_arpin(&priv->dev); + NETDEV_RXARP(&priv->dev); + if (priv->dev.d_len > 0) + { + amebaz_transmit(priv); + } + } + + else +#endif + { + NETDEV_RXDROPPED(&priv->dev); + } +#ifdef CONFIG_NET_IPv6 + } +#endif +#ifdef CONFIG_NET_IPv4 + } +#endif + + skb_pull(skb, len); + priv->dev.d_buf = oldbuf; + net_unlock(); +} + +static void amebaz_poll_expiry(wdparm_t arg) +{ + FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)arg; + work_queue(LPWORK, &priv->pollwork, amebaz_poll_work, priv, 0); +} + +static void amebaz_txavail_work(FAR void *arg) +{ + FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)arg; + FAR struct net_driver_s *dev = &priv->dev; + net_lock(); + if (IFF_IS_UP(dev->d_flags)) + { + if (!priv->curr && rltk_wlan_check_isup(priv->devnum)) + { + priv->curr = rltk_wlan_alloc_skb(MAX_NETDEV_PKTSIZE); + if (priv->curr) + { + priv->dev.d_buf = priv->curr->tail; + priv->dev.d_len = 0; + } + } + + if (priv->dev.d_buf) + { + devif_timer(&priv->dev, 0, amebaz_txpoll); + } + } + + net_unlock(); +} + +static void amebaz_poll_work(FAR void *arg) +{ + FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)arg; + FAR struct net_driver_s *dev = &priv->dev; + net_lock(); + if (IFF_IS_UP(dev->d_flags)) + { + if (!priv->curr && rltk_wlan_check_isup(priv->devnum)) + { + priv->curr = rltk_wlan_alloc_skb(MAX_NETDEV_PKTSIZE); + if (priv->curr) + { + priv->dev.d_buf = priv->curr->tail; + priv->dev.d_len = 0; + } + } + + if (priv->dev.d_buf) + { + devif_timer(&priv->dev, WDDELAY, amebaz_txpoll); + } + } + + wd_start(&priv->txpoll, WDDELAY, amebaz_poll_expiry, (wdparm_t)priv); + net_unlock(); +} + +static int amebaz_txavail(FAR struct net_driver_s *dev) +{ + FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)dev->d_private; + if (work_available(&priv->pollwork)) + { + work_queue(LPWORK, &priv->pollwork, amebaz_txavail_work, priv, 0); + } + + return OK; +} + +int amebaz_ioctl(FAR struct net_driver_s *dev, int cmd, + unsigned long arg) +{ + FAR struct amebaz_dev_s *priv = (struct amebaz_dev_s *)dev->d_private; + int ret; + if (!IFF_IS_UP(dev->d_flags) || + (!rltk_wlan_running(priv->devnum) && cmd != SIOCSIWMODE)) + { + return -EINVAL; + } + + switch (cmd) + { + case SIOCSIWSCAN: + ret = amebaz_wl_start_scan(priv, (void *)arg); + break; + case SIOCGIWSCAN: + ret = amebaz_wl_get_scan_results(priv, (void *)arg); + break; + case SIOCSIWENCODEEXT: + ret = amebaz_wl_set_encode_ext(priv, (void *)arg); + break; + case SIOCGIWENCODEEXT: + ret = amebaz_wl_get_encode_ext(priv, (void *)arg); + break; + case SIOCSIWESSID: + ret = amebaz_wl_set_ssid(priv, (void *)arg); + break; + case SIOCSIWAP: + ret = amebaz_wl_set_bssid(priv, (void *)arg); + break; + case SIOCSIWMODE: + ret = amebaz_wl_set_mode(priv, (void *)arg); + break; + case SIOCSIWCOUNTRY: + ret = amebaz_wl_set_country(priv, (void *)arg); + break; + case SIOCGIWFREQ: + ret = amebaz_wl_get_freq(priv, (void *)arg); + break; + case SIOCSIWFREQ: + ret = amebaz_wl_set_freq(priv, (void *)arg); + break; + case SIOCGIWAP: + case SIOCGIWMODE: + case SIOCGIWESSID: + case SIOCGIWSENS: + case SIOCSIWAUTH: + case SIOCGIWAUTH: + case SIOCSIFHWADDR: + case SIOCGIFHWADDR: + case SIOCSIWRATE: + case SIOCGIWRATE: + case SIOCSIWTXPOW: + case SIOCGIWTXPOW: + ret = amebaz_wl_process_command(priv, cmd, (void *)arg); + break; + default: + wlwarn("ERROR: Unrecognized IOCTL command: %d\n", cmd); + ret = -ENOTTY; /* Special return value for this case */ + break; + } + + return ret; +} + +static int amebaz_ifup(FAR struct net_driver_s *dev) +{ + FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)dev->d_private; + if (!IFF_IS_UP(dev->d_flags)) + { + priv->mode = RTW_MODE_NONE; + priv->conn.status = AMEBAZ_STATUS_DISABLED; + wd_start(&priv->txpoll, WDDELAY, amebaz_poll_expiry, (wdparm_t)dev); + } + + return OK; +} + +static int amebaz_ifdown(FAR struct net_driver_s *dev) +{ + int ret = 0; + FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)dev->d_private; + irqstate_t flags; + if (priv->devnum == 0 && rltk_wlan_running(1)) + { + printf("must ifdown wlan 1 first\r\n"); + return ERROR; + } + + flags = enter_critical_section(); + if (IFF_IS_UP(dev->d_flags)) + { + if (priv->curr) + { + skb_put(priv->curr, 0); + rltk_wlan_send_skb(priv->devnum, priv->curr); + + priv->curr = NULL; + } + + wd_cancel(&priv->txpoll); + if (priv->devnum == 0) + { + rltk_wlan_deinit(); + } + + else if (priv->mode == RTW_MODE_STA_AP) + { + ret = rltk_set_mode_prehandle(RTW_MODE_STA_AP, + RTW_MODE_STA, "wlan0"); + rtw_msleep_os(50); + ret = rltk_set_mode_posthandle(RTW_MODE_STA_AP, + RTW_MODE_STA, "wlan0"); + while (rltk_wlan_running(1)) + { + rtw_msleep_os(50); + } + } + } + + leave_critical_section(flags); + return ret; +} + +int amebaz_netdev_register(FAR struct amebaz_dev_s *priv) +{ + struct net_driver_s *dev = &priv->dev; + dev->d_ifup = amebaz_ifup; + dev->d_ifdown = amebaz_ifdown; + dev->d_txavail = amebaz_txavail; +#ifdef CONFIG_NETDEV_IOCTL + dev->d_ioctl = amebaz_ioctl; +#endif + dev->d_private = priv; + return netdev_register(dev, NET_LL_IEEE80211); +} + diff --git a/arch/arm/src/rtl8720c/amebaz_netdev.h b/arch/arm/src/rtl8720c/amebaz_netdev.h new file mode 100644 index 00000000000..7aa45706035 --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_netdev.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_netdev.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_NETDEV_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_NETDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "amebaz_driver.h" +#include "amebaz_wlan.h" + +int amebaz_netdev_register(FAR struct amebaz_dev_s *priv); +void amebaz_netdev_notify_receive(FAR struct amebaz_dev_s *priv, + int index, unsigned int len); +#endif /* __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_NETDEV_H */ diff --git a/arch/arm/src/rtl8720c/amebaz_wlan.c b/arch/arm/src/rtl8720c/amebaz_wlan.c new file mode 100644 index 00000000000..8446a1c8c8a --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_wlan.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_wlan.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "amebaz_netdev.h" + +enum _WIFI_EVENT_INDICATE +{ + WIFI_EVENT_CONNECT = 0, + WIFI_EVENT_DISCONNECT = 1, + WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, + WIFI_EVENT_SCAN_RESULT_REPORT = 3, + WIFI_EVENT_SCAN_DONE = 4, + WIFI_EVENT_RECONNECTION_FAIL = 5, + WIFI_EVENT_SEND_ACTION_DONE = 6, + WIFI_EVENT_RX_MGNT = 7, + WIFI_EVENT_STA_ASSOC = 8, + WIFI_EVENT_STA_DISASSOC = 9, + WIFI_EVENT_STA_WPS_START = 10, + WIFI_EVENT_WPS_FINISH = 11, + WIFI_EVENT_EAPOL_START = 12, + WIFI_EVENT_EAPOL_RECVD = 13, + WIFI_EVENT_NO_NETWORK = 14, + WIFI_EVENT_BEACON_AFTER_DHCP = 15, + WIFI_EVENT_IP_CHANGED = 16, + WIFI_EVENT_ICV_ERROR = 17, + WIFI_EVENT_CHALLENGE_FAIL = 18, + WIFI_EVENT_STA_START = 19, + WIFI_EVENT_STA_STOP = 20, + WIFI_EVENT_AP_START = 21, + WIFI_EVENT_AP_STOP = 22, + WIFI_EVENT_STA_GOT_IP = 23, + WIFI_EVENT_STA_LOST_IP = 24, + WIFI_EVENT_MAX, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void wifi_set_country_code(void) +{ + /* wifi_set_country(RTW_COUNTRY_US); */ +} + +void wifi_indication(unsigned long event, char *buf, int buf_len, int flags) +{ + if (event != WIFI_EVENT_BEACON_AFTER_DHCP) + { + syslog(1, "%s: %d, event: %x\n", __func__, __LINE__, event); + } +} + +void wext_wlan_indicate(unsigned int cmd, union iwreq_data *wrqu, + char *extra) +{ + int index = 0; + if (cmd == IWEVCUSTOM) + { + amebaz_wl_connection_handler(index, wrqu, extra); + } + + else if (cmd == SIOCGIWAP) + { + amebaz_wl_connection_handler(index, wrqu, extra); + } + + else if (cmd == SIOCGIWSCAN) + { + amebaz_wl_scan_handler(index, wrqu, extra); + } + + else + { + syslog(1, "%s: %d, event: %x\n", __func__, __LINE__, cmd); + } +} + +void netif_post_sleep_processing(void) +{ +} + +int netif_is_valid_ip(int index, unsigned char *ip_dest) +{ + return true; +} + +unsigned char *rltk_wlan_get_ip(int index) +{ + return NULL; +} + +void netif_rx(int index, unsigned int len) +{ + amebaz_wl_notify_rx_handler(index, len); +} + +void rltk_wlan_set_netif_info(int index, void *dev, unsigned char *addr) +{ + amebaz_wl_netif_info_handler(index, dev, addr); +} + diff --git a/arch/arm/src/rtl8720c/amebaz_wlan.h b/arch/arm/src/rtl8720c/amebaz_wlan.h new file mode 100644 index 00000000000..57bc670e57c --- /dev/null +++ b/arch/arm/src/rtl8720c/amebaz_wlan.h @@ -0,0 +1,416 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/amebaz_wlan.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_WLAN_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_WLAN_H +#define WEP_ENABLED 0x0001 +#define TKIP_ENABLED 0x0002 +#define AES_ENABLED 0x0004 +#define WSEC_SWFLAG 0x0008 +#define AES_CMAC_ENABLED 0x0010 +#define SHARED_ENABLED 0x00008000 +#define WPA_SECURITY 0x00200000 +#define WPA2_SECURITY 0x00400000 +#define WPS_ENABLED 0x10000000 +#define PSCAN_ENABLE 0x01 /* enable for partial channel scan */ +#define PSCAN_FAST_SURVEY 0x02 /* set to select scan time to FAST_SURVEY_TO, otherwise SURVEY_TO */ +#define PSCAN_SIMPLE_CONFIG 0x04 /* set to select scan time to FAST_SURVEY_TO and resend probe request */ + +enum +{ + /* CHANNEL PLAN */ + + RTW_COUNTRY_WORLD1, /* 0x20 */ + RTW_COUNTRY_ETSI1, /* 0x21 */ + RTW_COUNTRY_FCC1, /* 0x22 */ + RTW_COUNTRY_MKK1, /* 0x23 */ + RTW_COUNTRY_ETSI2, /* 0x24 */ + RTW_COUNTRY_FCC2, /* 0x2a */ + RTW_COUNTRY_WORLD2, /* 0x47 */ + RTW_COUNTRY_MKK2, /* 0x58 */ + RTW_COUNTRY_GLOBAL, /* 0x41 */ + + /* SPECIAL */ + + RTW_COUNTRY_WORLD, /* WORLD1 */ + RTW_COUNTRY_EU, /* ETSI1 */ + + /* JAPANESE */ + + RTW_COUNTRY_JP, /* MKK1 */ + + /* FCC , 19 countries */ + + RTW_COUNTRY_AS, /* FCC2 */ + RTW_COUNTRY_BM, + RTW_COUNTRY_CA, + RTW_COUNTRY_DM, + RTW_COUNTRY_DO, + RTW_COUNTRY_FM, + RTW_COUNTRY_GD, + RTW_COUNTRY_GT, + RTW_COUNTRY_GU, + RTW_COUNTRY_HT, + RTW_COUNTRY_MH, + RTW_COUNTRY_MP, + RTW_COUNTRY_NI, + RTW_COUNTRY_PA, + RTW_COUNTRY_PR, + RTW_COUNTRY_PW, + RTW_COUNTRY_TW, + RTW_COUNTRY_US, + RTW_COUNTRY_VI, + + /* others, ETSI */ + + RTW_COUNTRY_AD, /* ETSI1 */ + RTW_COUNTRY_AE, + RTW_COUNTRY_AF, + RTW_COUNTRY_AI, + RTW_COUNTRY_AL, + RTW_COUNTRY_AM, + RTW_COUNTRY_AN, + RTW_COUNTRY_AR, + RTW_COUNTRY_AT, + RTW_COUNTRY_AU, + RTW_COUNTRY_AW, + RTW_COUNTRY_AZ, + RTW_COUNTRY_BA, + RTW_COUNTRY_BB, + RTW_COUNTRY_BD, + RTW_COUNTRY_BE, + RTW_COUNTRY_BF, + RTW_COUNTRY_BG, + RTW_COUNTRY_BH, + RTW_COUNTRY_BL, + RTW_COUNTRY_BN, + RTW_COUNTRY_BO, + RTW_COUNTRY_BR, + RTW_COUNTRY_BS, + RTW_COUNTRY_BT, + RTW_COUNTRY_BY, + RTW_COUNTRY_BZ, + RTW_COUNTRY_CF, + RTW_COUNTRY_CH, + RTW_COUNTRY_CI, + RTW_COUNTRY_CL, + RTW_COUNTRY_CN, + RTW_COUNTRY_CO, + RTW_COUNTRY_CR, + RTW_COUNTRY_CX, + RTW_COUNTRY_CY, + RTW_COUNTRY_CZ, + RTW_COUNTRY_DE, + RTW_COUNTRY_DK, + RTW_COUNTRY_DZ, + RTW_COUNTRY_EC, + RTW_COUNTRY_EE, + RTW_COUNTRY_EG, + RTW_COUNTRY_ES, + RTW_COUNTRY_ET, + RTW_COUNTRY_FI, + RTW_COUNTRY_FR, + RTW_COUNTRY_GB, + RTW_COUNTRY_GE, + RTW_COUNTRY_GF, + RTW_COUNTRY_GH, + RTW_COUNTRY_GL, + RTW_COUNTRY_GP, + RTW_COUNTRY_GR, + RTW_COUNTRY_GY, + RTW_COUNTRY_HK, + RTW_COUNTRY_HN, + RTW_COUNTRY_HR, + RTW_COUNTRY_HU, + RTW_COUNTRY_ID, + RTW_COUNTRY_IE, + RTW_COUNTRY_IL, + RTW_COUNTRY_IN, + RTW_COUNTRY_IQ, + RTW_COUNTRY_IR, + RTW_COUNTRY_IS, + RTW_COUNTRY_IT, + RTW_COUNTRY_JM, + RTW_COUNTRY_JO, + RTW_COUNTRY_KE, + RTW_COUNTRY_KH, + RTW_COUNTRY_KN, + RTW_COUNTRY_KP, + RTW_COUNTRY_KR, + RTW_COUNTRY_KW, + RTW_COUNTRY_KY, + RTW_COUNTRY_KZ, + RTW_COUNTRY_LA, + RTW_COUNTRY_LB, + RTW_COUNTRY_LC, + RTW_COUNTRY_LI, + RTW_COUNTRY_LK, + RTW_COUNTRY_LR, + RTW_COUNTRY_LS, + RTW_COUNTRY_LT, + RTW_COUNTRY_LU, + RTW_COUNTRY_LV, + RTW_COUNTRY_MA, + RTW_COUNTRY_MC, + RTW_COUNTRY_MD, + RTW_COUNTRY_ME, + RTW_COUNTRY_MF, + RTW_COUNTRY_MK, + RTW_COUNTRY_MN, + RTW_COUNTRY_MO, + RTW_COUNTRY_MQ, + RTW_COUNTRY_MR, + RTW_COUNTRY_MT, + RTW_COUNTRY_MU, + RTW_COUNTRY_MV, + RTW_COUNTRY_MW, + RTW_COUNTRY_MX, + RTW_COUNTRY_MY, + RTW_COUNTRY_NG, + RTW_COUNTRY_NL, + RTW_COUNTRY_NO, + RTW_COUNTRY_NP, + RTW_COUNTRY_NZ, + RTW_COUNTRY_OM, + RTW_COUNTRY_PE, + RTW_COUNTRY_PF, + RTW_COUNTRY_PG, + RTW_COUNTRY_PH, + RTW_COUNTRY_PK, + RTW_COUNTRY_PL, + RTW_COUNTRY_PM, + RTW_COUNTRY_PT, + RTW_COUNTRY_PY, + RTW_COUNTRY_QA, + RTW_COUNTRY_RS, + RTW_COUNTRY_RU, + RTW_COUNTRY_RW, + RTW_COUNTRY_SA, + RTW_COUNTRY_SE, + RTW_COUNTRY_SG, + RTW_COUNTRY_SI, + RTW_COUNTRY_SK, + RTW_COUNTRY_SN, + RTW_COUNTRY_SR, + RTW_COUNTRY_SV, + RTW_COUNTRY_SY, + RTW_COUNTRY_TC, + RTW_COUNTRY_TD, + RTW_COUNTRY_TG, + RTW_COUNTRY_TH, + RTW_COUNTRY_TN, + RTW_COUNTRY_TR, + RTW_COUNTRY_TT, + RTW_COUNTRY_TZ, + RTW_COUNTRY_UA, + RTW_COUNTRY_UG, + RTW_COUNTRY_UY, + RTW_COUNTRY_UZ, + RTW_COUNTRY_VC, + RTW_COUNTRY_VE, + RTW_COUNTRY_VN, + RTW_COUNTRY_VU, + RTW_COUNTRY_WF, + RTW_COUNTRY_WS, + RTW_COUNTRY_YE, + RTW_COUNTRY_YT, + RTW_COUNTRY_ZA, + RTW_COUNTRY_ZW, + RTW_COUNTRY_MAX +}; + +enum +{ + RTW_BSS_TYPE_INFRASTRUCTURE = 0, /* *< Denotes infrastructure network */ + RTW_BSS_TYPE_ADHOC = 1, /* *< Denotes an 802.11 ad-hoc IBSS network */ + RTW_BSS_TYPE_ANY = 2, /* *< Denotes either infrastructure or ad-hoc network */ + RTW_BSS_TYPE_UNKNOWN = -1 /* *< May be returned by scan function if BSS type is unknown. Do not pass this to the Join function */ +}; + +enum +{ + RTW_SECURITY_OPEN = 0, /* *< Open security */ + RTW_SECURITY_WEP_PSK = WEP_ENABLED, /* *< WEP Security with open authentication */ + RTW_SECURITY_WEP_SHARED = (WEP_ENABLED | SHARED_ENABLED), /* *< WEP Security with shared authentication */ + RTW_SECURITY_WPA_TKIP_PSK = (WPA_SECURITY | TKIP_ENABLED), /* *< WPA Security with TKIP */ + RTW_SECURITY_WPA_AES_PSK = (WPA_SECURITY | AES_ENABLED), /* *< WPA Security with AES */ + RTW_SECURITY_WPA2_AES_PSK = (WPA2_SECURITY | AES_ENABLED), /* *< WPA2 Security with AES */ + RTW_SECURITY_WPA2_TKIP_PSK = (WPA2_SECURITY | TKIP_ENABLED), /* *< WPA2 Security with TKIP */ + RTW_SECURITY_WPA2_MIXED_PSK = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /* *< WPA2 Security with AES & TKIP */ + RTW_SECURITY_WPA_WPA2_MIXED = (WPA_SECURITY | WPA2_SECURITY), /* *< WPA/WPA2 Security */ + RTW_SECURITY_WPA2_AES_CMAC = (WPA2_SECURITY | AES_CMAC_ENABLED), /* *< WPA2 Security with AES and Management Frame Protection */ + RTW_SECURITY_WPS_OPEN = WPS_ENABLED, /* *< WPS with open security */ + RTW_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /* *< WPS with AES security */ + RTW_SECURITY_UNKNOWN = -1, /* *< May be returned by scan function if security is unknown. Do not pass this to the join function! */ + RTW_SECURITY_FORCE_32_BIT = 0x7fffffff /* *< Exists only to force rtw_security_t type to 32 bits */ +}; + +enum +{ + RTW_WPS_TYPE_DEFAULT = 0x0000, + RTW_WPS_TYPE_USER_SPECIFIED = 0x0001, + RTW_WPS_TYPE_MACHINE_SPECIFIED = 0x0002, + RTW_WPS_TYPE_REKEY = 0x0003, + RTW_WPS_TYPE_PUSHBUTTON = 0x0004, + RTW_WPS_TYPE_REGISTRAR_SPECIFIED = 0x0005, + RTW_WPS_TYPE_NONE = 0x0006, + RTW_WPS_TYPE_WSC = 0x0007 +}; + +enum +{ + RTW_802_11_BAND_5GHZ = 0, /* *< Denotes 5GHz radio band */ + RTW_802_11_BAND_2_4GHZ = 1 /* *< Denotes 2.4GHz radio band */ +}; + +begin_packed_struct struct rtw_ssid +{ + unsigned char len; /* *< SSID length */ + unsigned char val[33]; /* *< SSID name (AP name) */ +} end_packed_struct; + +begin_packed_struct struct rtw_mac +{ + unsigned char octet[6]; /* *< Unique 6-byte MAC address */ +} end_packed_struct; + +typedef unsigned long rtw_bss_type_t; +typedef unsigned long rtw_security_t; +typedef unsigned long rtw_wps_type_t; +typedef unsigned long rtw_802_11_band_t; +typedef struct rtw_ssid rtw_ssid_t; +typedef struct rtw_mac rtw_mac_t; +typedef struct rtw_scan_result rtw_scan_result_t; +typedef struct rtw_network_info rtw_network_info_t; +typedef struct rtw_scan_ap_result rtw_scan_ap_result_t; + +begin_packed_struct struct rtw_network_info +{ + rtw_ssid_t ssid; + rtw_mac_t bssid; + rtw_security_t security_type; + unsigned char *password; + int password_len; + int key_id; +} end_packed_struct; + +begin_packed_struct struct rtw_scan_result +{ + rtw_ssid_t SSID; /* *< Service Set Identification (i.e. Name of Access Point) */ + rtw_mac_t BSSID; /* *< Basic Service Set Identification (i.e. MAC address of Access Point) */ + signed short signal_strength; /* *< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */ + rtw_bss_type_t bss_type; /* *< Network type */ + rtw_security_t security; /* *< Security type */ + rtw_wps_type_t wps_type; /* *< WPS type */ + unsigned int channel; /* *< Radio channel that the AP beacon was received on */ + rtw_802_11_band_t band; /* *< Radio band */ +} end_packed_struct; + +begin_packed_struct struct rtw_scan_ap_result +{ + char len; + uint8_t BSSID[IFHWADDRLEN]; + int signal_strength; + char security; + char wps_type; + char channel; + char SSID[0]; +} end_packed_struct; + +enum +{ + RTW_MODE_NONE = 0, + RTW_MODE_STA, + RTW_MODE_AP, + RTW_MODE_STA_AP, + RTW_MODE_PROMISC, + RTW_MODE_P2P +}; + +struct sk_buff_head +{ + struct list_head *next; + struct list_head *prev; + unsigned int qlen; +}; + +struct sk_buff +{ + struct sk_buff *next; + struct sk_buff *prev; + struct sk_buff_head *list; + unsigned char *head; + unsigned char *data; + unsigned char *tail; + unsigned char *end; + void *dev; + unsigned int len; + int dyalloc_flag; +}; + +unsigned char *skb_put(struct sk_buff *skb, + unsigned int len); +unsigned char *skb_pull(struct sk_buff *skb, + unsigned int len); +int rltk_wlan_init(int index, unsigned long mode); +void rltk_wlan_deinit(void); +void rltk_wlan_deinit_fastly(void); +int rltk_wlan_start(int index); +void rltk_wlan_statistic(unsigned char index); +unsigned char rltk_wlan_running(unsigned char index); +int rltk_wlan_control(unsigned long cmd, void *data); +int rltk_wlan_handshake_done(void); +int rltk_wlan_rf_on(void); +int rltk_wlan_rf_off(void); +int rltk_wlan_check_bus(void); +int rltk_wlan_wireless_mode(unsigned char mode); +int rltk_wlan_get_wireless_mode(unsigned char *pmode); +int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps); +int rtw_ps_enable(int enable); +int rltk_wlan_is_connected_to_ap(void); +int rltk_set_mode_prehandle(unsigned char curr_mode, + unsigned char next_mode, + const char *ifname); +int rltk_set_mode_posthandle(unsigned char curr_mode, + unsigned char next_mode, + const char *ifname); +int rltk_remove_softap_in_concurrent_mode(const char *ifname); +unsigned char rltk_wlan_check_isup(int index); +void rltk_wlan_tx_inc(int index); +void rltk_wlan_tx_dec(int index); +struct sk_buff *rltk_wlan_get_recv_skb(int index); +struct sk_buff *rltk_wlan_alloc_skb(unsigned int len); +void rltk_wlan_set_netif_info(int index_wlan, void *dev, + unsigned char *addr); +void rltk_wlan_send_skb(int index, struct sk_buff *skb); +unsigned char *rltk_wlan_get_ip(int index); +int netif_is_valid_ip(int index, unsigned char *ip_dest); +unsigned char *netif_get_hwaddr(int index); +void netif_rx(int index, unsigned int len); +void netif_post_sleep_processing(void); +void netif_pre_sleep_processing(void); + +#endif /* __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_WLAN_H */ + diff --git a/arch/arm/src/rtl8720c/chip.h b/arch/arm/src/rtl8720c/chip.h new file mode 100644 index 00000000000..072d37d4631 --- /dev/null +++ b/arch/arm/src/rtl8720c/chip.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_AMEBA_CHIP_H +#define __ARCH_ARM_SRC_AMEBA_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +# include +#endif +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef ARRAY_SIZE +# define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif +/* If the common ARMv7-M vector handling logic is used, + * then it expects the following + * definition in this file that provides the number of + * supported external interrupts. + */ +#define ARMV8M_PERIPHERAL_INTERRUPTS (CONFIG_AMEBA_NR_IRQS - 16) + +#endif /* __ARCH_ARM_SRC_AMEBA_CHIP_H */ diff --git a/arch/arm/src/rtl8720c/include/chip.h b/arch/arm/src/rtl8720c/include/chip.h new file mode 100644 index 00000000000..ef9a8249dae --- /dev/null +++ b/arch/arm/src/rtl8720c/include/chip.h @@ -0,0 +1,20 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/include/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + diff --git a/arch/arm/src/rtl8720c/include/irq.h b/arch/arm/src/rtl8720c/include/irq.h new file mode 100644 index 00000000000..cd0992457ee --- /dev/null +++ b/arch/arm/src/rtl8720c/include/irq.h @@ -0,0 +1,118 @@ +/**************************************************************************** + * arch/arm/src/rtl8720c/include/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_SONG_IRQ_H +#define __ARCH_ARM_INCLUDE_SONG_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Exception/interrupt vector numbers */ + +/* Vector 0: Reset stack pointer value */ + +/* Vector 1: Reset */ + +#define NVIC_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ + +#define NVIC_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + +#define NVIC_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ + +#define NVIC_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ + +#define NVIC_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + +/* Vectors 7-10: Reserved */ + +#define NVIC_IRQ_SVCALL (11) /* Vector 11: SVC call */ + +#define NVIC_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + +/* Vector 13: Reserved */ + +#define NVIC_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ + +#define NVIC_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). These definitions are chip-specific */ + +#define NVIC_IRQ_FIRST (16) /* Vector number of the first interrupt */ + +#define NVIC_IRQ_WLAN (28) /* Vector 28: Wireless Lan */ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the INTC. This does, however, waste several + * words of memory in the IRQ to handle mapping tables. + */ + +#define NR_IRQS CONFIG_AMEBA_NR_IRQS + +/* NVIC priority levels */ + +#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */ + +#define NVIC_SYSH_PRIORITY_DEFAULT 0x40 /* Midpoint is the default */ + +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ + +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Three bits priority used, bits[7-6] as group */ + +#define NVIC_SYSH_PRIORITY_SUBSTEP 0x20 /* Three bits priority used, bit[5] as sub */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN + +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_INCLUDE_SONG_IRQ_H */ + diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig index a37c8bc1ecc..6ce1ea92581 100644 --- a/arch/arm/src/s32k1xx/Kconfig +++ b/arch/arm/src/s32k1xx/Kconfig @@ -618,6 +618,15 @@ config S32K1XX_EDMA_EDBG endmenu # eDMA Global Configuration +menu "LPSPI Configuration" + depends on S32K1XX_LPSPI + +config S32K1XX_LPSPI_DWORD + bool "DWORD up to 64 bit transfer support" + default n + +endmenu # LPSPI Configuration + menu "LPI2C0 Configuration" depends on S32K1XX_LPI2C0 diff --git a/arch/arm/src/s32k1xx/Make.defs b/arch/arm/src/s32k1xx/Make.defs index b9efbae12af..f2cf13047b5 100644 --- a/arch/arm/src/s32k1xx/Make.defs +++ b/arch/arm/src/s32k1xx/Make.defs @@ -31,6 +31,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c endif # Source files common to all S32K1xx chip families. diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h index 5ebeb77e84e..0750d94f020 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Pavlina Koleva - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c b/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c index 920c5a347e8..277e2acb696 100644 --- a/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c +++ b/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c b/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c index b273497efc3..c0c8f1734a8 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/s32k1xx/s32k1xx_edma.c b/arch/arm/src/s32k1xx/s32k1xx_edma.c index 5e9360253ba..90d32dd081c 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_edma.c +++ b/arch/arm/src/s32k1xx/s32k1xx_edma.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c b/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c index 750deb19a90..eefe421ebaf 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c +++ b/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "arm_arch.h" diff --git a/arch/arm/src/s32k1xx/s32k1xx_enet.c b/arch/arm/src/s32k1xx/s32k1xx_enet.c index 65dc59a00bb..5313c835a34 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_enet.c +++ b/arch/arm/src/s32k1xx/s32k1xx_enet.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/s32k1xx/s32k1xx_flexcan.c b/arch/arm/src/s32k1xx/s32k1xx_flexcan.c index 40c2bf2bc7e..5e8a894e0b9 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_flexcan.c +++ b/arch/arm/src/s32k1xx/s32k1xx_flexcan.c @@ -636,7 +636,7 @@ static int s32k1xx_transmit(FAR struct s32k1xx_driver_s *priv) if (mbi == TXMBCOUNT) { - nwarn("No TX MB available mbi %" PRIi32 "\n", mbi); + nwarn("No TX MB available mbi %" PRIu32 "\n", mbi); NETDEV_TXERRORS(&priv->dev); return 0; /* No transmission for you! */ } @@ -1006,10 +1006,13 @@ static void s32k1xx_txdone(FAR struct s32k1xx_driver_s *priv) NETDEV_TXDONE(&priv->dev); #ifdef TX_TIMEOUT_WQ /* We are here because a transmission completed, so the - * corresponding watchdog can be canceled. + * corresponding watchdog can be canceled + * mailbox be set to inactive */ wd_cancel(&priv->txtimeout[mbi]); + struct mb_s *mb = &priv->tx[mbi]; + mb->cs.code = CAN_TXMB_INACTIVE; #endif } @@ -1129,7 +1132,9 @@ static int s32k1xx_flexcan_interrupt(int irq, FAR void *context, static void s32k1xx_txtimeout_work(FAR void *arg) { FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg; + uint32_t flags; uint32_t mbi; + uint32_t mb_bit; struct timespec ts; struct timeval *now = (struct timeval *)&ts; @@ -1140,6 +1145,8 @@ static void s32k1xx_txtimeout_work(FAR void *arg) * transmit function transmitted a new frame */ + flags = getreg32(priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + for (mbi = 0; mbi < TXMBCOUNT; mbi++) { if (priv->txmb[mbi].deadline.tv_sec != 0 @@ -1147,6 +1154,14 @@ static void s32k1xx_txtimeout_work(FAR void *arg) || now->tv_usec > priv->txmb[mbi].deadline.tv_usec)) { NETDEV_TXTIMEOUTS(&priv->dev); + + mb_bit = 1 << (RXMBCOUNT + mbi); + + if (flags & mb_bit) + { + putreg32(mb_bit, priv->base + S32K1XX_CAN_IFLAG1_OFFSET); + } + struct mb_s *mb = &priv->tx[mbi]; mb->cs.code = CAN_TXMB_ABORT; priv->txmb[mbi].pending = TX_ABORT; @@ -1658,7 +1673,7 @@ static int s32k1xx_initialize(struct s32k1xx_driver_s *priv) for (i = 0; i < RXMBCOUNT; i++) { - ninfo("Set MB%" PRIi32 " to receive %p\n", i, &priv->rx[i]); + ninfo("Set MB%" PRIu32 " to receive %p\n", i, &priv->rx[i]); priv->rx[i].cs.edl = 0x1; priv->rx[i].cs.brs = 0x1; priv->rx[i].cs.esi = 0x0; @@ -1722,8 +1737,8 @@ static void s32k1xx_reset(struct s32k1xx_driver_s *priv) for (i = 0; i < TOTALMBCOUNT; i++) { - ninfo("MB %" PRIi32 " %p\n", i, &priv->rx[i]); - ninfo("MB %" PRIi32 " %p\n", i, &priv->rx[i].id.w); + ninfo("MB %" PRIu32 " %p\n", i, &priv->rx[i]); + ninfo("MB %" PRIu32 " %p\n", i, &priv->rx[i].id.w); priv->rx[i].cs.cs = 0x0; priv->rx[i].id.w = 0x0; priv->rx[i].data[0].w00 = 0x0; diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c b/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c index 460ecfc8a08..2095d6d821e 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c index 5ecf4357b6e..2f9000461da 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_lpspi.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Authors: Teodora Kireva - * Ivan Ucherdzhiev + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -68,6 +52,7 @@ #include #include #include +#include #include #include @@ -156,9 +141,9 @@ static inline uint32_t s32k1xx_lpspi_readword(FAR struct s32k1xx_lpspidev_s *priv); static inline void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, - uint16_t byte); + uint32_t byte); static inline -bool s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *priv); +uint16_t s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *priv); static uint32_t s32k1xx_lpspi_pckfreq(uintptr_t base); static inline void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, @@ -475,7 +460,7 @@ uint32_t s32k1xx_lpspi_readword(FAR struct s32k1xx_lpspidev_s *priv) static inline void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, - uint16_t word) + uint32_t word) { /* Wait until the transmit buffer is empty */ @@ -489,6 +474,43 @@ void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, s32k1xx_lpspi_putreg32(priv, S32K1XX_LPSPI_TDR_OFFSET, word); } +/**************************************************************************** + * Name: s32k1xx_lpspi_write_dword + * + * Description: + * Write two words to SPI + * + * Input Parameters: + * priv - Device-specific state data + * word0, word1 - words to send + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + +static inline void s32k1xx_lpspi_write_dword(FAR struct s32k1xx_lpspidev_s + *priv, + uint32_t word0, + uint32_t word1) +{ + /* Wait until the transmit buffer is empty */ + + while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) + & LPSPI_SR_TDF) == 0) + { + } + + /* Then send the words, use the FIFO */ + + s32k1xx_lpspi_putreg32(priv, S32K1XX_LPSPI_TDR_OFFSET, word0); + s32k1xx_lpspi_putreg32(priv, S32K1XX_LPSPI_TDR_OFFSET, word1); +} + +#endif + /**************************************************************************** * Name: s32k1xx_lpspi_readbyte * @@ -554,30 +576,23 @@ void s32k1xx_lpspi_writebyte(FAR struct s32k1xx_lpspidev_s *priv, * * Description: * Check if the SPI is operating in more then 8 bit mode + * On the S32K the frame size can grow to 4096 bit/frame * * Input Parameters: * priv - Device-specific state data * * Returned Value: - * true: >8 bit mode-bit mode, false: <= 8-bit mode + * value: frame size * ****************************************************************************/ -static inline -bool s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *priv) +static inline uint16_t s32k1xx_lpspi_9to16bitmode( + FAR struct s32k1xx_lpspidev_s *priv) { - bool ret; - - if (((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_TCR_OFFSET) & - LPSPI_TCR_FRAMESZ_MASK) + 1) < 9) - { - ret = false; - } - else - { - ret = true; - } + uint16_t ret; + ret = ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_TCR_OFFSET) & + LPSPI_TCR_FRAMESZ_MASK) + 1); return ret; } @@ -1119,6 +1134,7 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) FAR struct s32k1xx_lpspidev_s *priv = (FAR struct s32k1xx_lpspidev_s *)dev; uint32_t regval; uint32_t men; + int savbits = nbits; spiinfo("nbits=%d\n", nbits); @@ -1151,7 +1167,8 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) * be faster. */ - priv->nbits = nbits; + priv->nbits = savbits; /* nbits has been clobbered... save the signed + * value. */ /* Re-enable LPSPI if it was enabled previously */ @@ -1187,6 +1204,7 @@ static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev, FAR struct s32k1xx_lpspidev_s *priv = (FAR struct s32k1xx_lpspidev_s *)dev; uint32_t setbits; uint32_t clrbits; + int savbits = nbits; spiinfo("features=%08x\n", features); @@ -1259,6 +1277,66 @@ static uint32_t s32k1xx_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) return ret; } +/**************************************************************************** + * Name: s32k1xx_lpspi_send_dword + * + * Description: + * Exchange two words on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd0, wd1 - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + +static uint32_t s32k1xx_lpspi_send_dword(FAR struct spi_dev_s *dev, + uint32_t wd0, uint32_t wd1, + uint32_t *rw1) +{ + FAR struct s32k1xx_lpspidev_s *priv = (FAR struct s32k1xx_lpspidev_s *)dev; + uint32_t regval; + uint32_t ret; + + DEBUGASSERT(priv && priv->spibase); + + /* check if the receive buffer is empty, if not clear it */ + + while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) + & LPSPI_SR_RDF)) + { + s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_RDR_OFFSET); + } + + s32k1xx_lpspi_write_dword(priv, wd0, wd1); + + while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) + & LPSPI_SR_RDF) != LPSPI_SR_RDF); + + ret = s32k1xx_lpspi_readword(priv); + *rw1 = s32k1xx_lpspi_readword(priv); + + /* Check and clear any error flags (Reading from the SR clears the error + * flags). + */ + + regval = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET); + + spiinfo("Sent: %04" PRIx32 " %04" PRIx32 " Return: %04" + PRIx32 " %04" PRIx32 " Status: %02" PRIx32 "\n", + wd0, wd1, ret, *rw1, regval); + + UNUSED(regval); + return ret; +} + +#endif + /**************************************************************************** * Name: s32k1xx_lpspi_exchange (no DMA). aka s32k1xx_lpspi_exchange_nodma * @@ -1269,7 +1347,7 @@ static uint32_t s32k1xx_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into @@ -1293,13 +1371,176 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, #endif { FAR struct s32k1xx_lpspidev_s *priv = (FAR struct s32k1xx_lpspidev_s *)dev; + uint16_t framesize; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); - /* 8- or 16-bit mode? */ + /* bit mode? */ - if (s32k1xx_lpspi_9to16bitmode(priv)) + framesize = s32k1xx_lpspi_9to16bitmode(priv); + if (framesize > 16 && framesize % 32 != 0) + { + /* 17-bit or higher, byte transfer due to padding + * take care of big endian mode of hardware !! + */ + + const uint8_t *src = (const uint8_t *)txbuffer; + uint8_t *dest = (uint8_t *) rxbuffer; + uint32_t word = 0x0; +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + uint32_t word1 = 0x0; + uint32_t rword1; + bool dwords = false; +#endif + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + /* read the required number of bytes */ + + switch (framesize) + { +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + case 40: + word = (src[0] << 24) + (src[1] << 16) + + (src[2] << 8) + src[3]; + word1 = src[4]; + src += 5; + dwords = true; + break; +#endif + default: + break; + } + } + else + { + word = 0xffffffff; + } + +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + /* Exchange 2 words */ + + if (dwords) + { + word = s32k1xx_lpspi_send_dword(dev, word, word1, &rword1); + } + else +#endif + { + word = s32k1xx_lpspi_send(dev, word); + } + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + switch (framesize) + { +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + case 40: + dest[0] = (word >> 24) & 0xff; + dest[1] = (word >> 16) & 0xff; + dest[2] = (word >> 8) & 0xff; + dest[3] = word & 0xff; + dest[4] = rword1 & 0xff; + dest += 5; + break; +#endif + + default: + + break; + } + } + } + } + else if (framesize > 16) + { + /* 32-bit or 64 bit, word size memory transfers */ + + const uint32_t *src = (const uint32_t *)txbuffer; + uint32_t *dest = (uint32_t *) rxbuffer; + uint32_t word = 0x0; +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + uint32_t word1 = 0x0; + uint32_t rword1; + bool dwords = false; +#endif + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + /* read the required number of bytes */ + + switch (framesize) + { + case 32: + word = __builtin_bswap32(*src); + src += 4; + break; +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + case 64: + word = __builtin_bswap32(src[0]); + word1 = __builtin_bswap32(src[1]); + src += 8; + dwords = true; +#endif + default: + break; + } + } + else + { + word = 0xffffffff; + } + +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + /* Exchange 2 words */ + + if (dwords) + { + word = s32k1xx_lpspi_send_dword(dev, word, word1, &rword1); + } + else +#endif + { + word = s32k1xx_lpspi_send(dev, word); + } + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + switch (framesize) + { + case 32: + *dest = __builtin_bswap32(word); + dest += 4; + break; +#ifdef CONFIG_S32K1XX_LPSPI_DWORD + case 64: + dest[0] = __builtin_bswap32(word); + dest[1] = __builtin_bswap32(rword1); + dest += 8; + break; +#endif + + default: + + break; + } + } + } + } + else if (framesize > 8) { /* 16-bit mode */ @@ -1313,7 +1554,9 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, if (src) { - word = *src++; + word = __builtin_bswap16(*src++); + + /* read the required number of bytes */ } else { @@ -1328,7 +1571,7 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, if (dest) { - *dest++ = word; + *dest++ = __builtin_bswap16(word); } } } diff --git a/arch/arm/src/s32k1xx/s32k1xx_pindma.c b/arch/arm/src/s32k1xx/s32k1xx_pindma.c index b43abee3795..6347a242665 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pindma.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pindma.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/s32k1xx/s32k1xx_pindump.c b/arch/arm/src/s32k1xx/s32k1xx_pindump.c index aee347af224..b638ad6ce94 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pindump.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pindump.c @@ -25,6 +25,7 @@ #include #include +#include #include #include @@ -78,7 +79,7 @@ static const char g_portchar[S32K1XX_NPORTS] = * * Description: * Dump all GPIO registers associated with the provided pin description - * along with a descriptive messasge. + * along with a descriptive message. * ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k1xx_pwm.c b/arch/arm/src/s32k1xx/s32k1xx_pwm.c index b5785a0d23b..29eda4b0d70 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pwm.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pwm.c @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_pwm.c * - * Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Alan Carvalho de Assis - * Ken Fazzone - * David Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k1xx_pwm.h b/arch/arm/src/s32k1xx/s32k1xx_pwm.h index 1a452531bfc..534851e7c2a 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pwm.h +++ b/arch/arm/src/s32k1xx/s32k1xx_pwm.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_pwm.h * - * Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Alan Carvalho de Assis - * Ken Fazzone - * David Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k1xx_rtc.c b/arch/arm/src/s32k1xx/s32k1xx_rtc.c index 596ba81db0c..415bef3a944 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_rtc.c +++ b/arch/arm/src/s32k1xx/s32k1xx_rtc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/s32k1xx/s32k1xx_serial.c b/arch/arm/src/s32k1xx/s32k1xx_serial.c index 400896a02e8..6f8c37933aa 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_serial.c +++ b/arch/arm/src/s32k1xx/s32k1xx_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs index 2aa370ec183..8f321eee4fc 100644 --- a/arch/arm/src/sam34/Make.defs +++ b/arch/arm/src/sam34/Make.defs @@ -59,6 +59,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/sam34/sam4cm_supc.h b/arch/arm/src/sam34/sam4cm_supc.h index 91d51838d6f..c9666316791 100644 --- a/arch/arm/src/sam34/sam4cm_supc.h +++ b/arch/arm/src/sam34/sam4cm_supc.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam4cm_supc.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam4cm_tickless.c b/arch/arm/src/sam34/sam4cm_tickless.c index 5fb1214558a..3d92334e51d 100644 --- a/arch/arm/src/sam34/sam4cm_tickless.c +++ b/arch/arm/src/sam34/sam4cm_tickless.c @@ -71,6 +71,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_aes.c b/arch/arm/src/sam34/sam_aes.c index 2147a9a7383..0fbb37cbcce 100644 --- a/arch/arm/src/sam34/sam_aes.c +++ b/arch/arm/src/sam34/sam_aes.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_aes.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Max Nekludov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_aes.h b/arch/arm/src/sam34/sam_aes.h index 8d983e1e34c..c9aa4f10364 100644 --- a/arch/arm/src/sam34/sam_aes.h +++ b/arch/arm/src/sam34/sam_aes.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_aes.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Max Nekludov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_allocateheap.c b/arch/arm/src/sam34/sam_allocateheap.c index 2b58ef75a07..750983b03b1 100644 --- a/arch/arm/src/sam34/sam_allocateheap.c +++ b/arch/arm/src/sam34/sam_allocateheap.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c index 292f87e650b..f56279dd39d 100644 --- a/arch/arm/src/sam34/sam_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -1148,7 +1149,7 @@ static inline int sam_single(struct sam_dma_s *dmach) putreg32(dmach->cfg, dmach->base + SAM_DMACHAN_CFG_OFFSET); - /* Enable the channel by writing a 1 to the CHER enable bit */ + /* Enable the channel by writing a �1� to the CHER enable bit */ putreg32(DMAC_CHER_ENA(dmach->chan), SAM_DMAC_CHER); @@ -1212,7 +1213,7 @@ static inline int sam_multiple(struct sam_dma_s *dmach) putreg32((uint32_t)llhead, dmach->base + SAM_DMACHAN_DSCR_OFFSET); - /* Finally, enable the channel by writing a 1 to the CHER enable */ + /* Finally, enable the channel by writing a �1� to the CHER enable */ putreg32(DMAC_CHER_ENA(dmach->chan), SAM_DMAC_CHER); diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 5f86f12d4c6..0a3eab015b2 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 0a67e3f6021..018e0c5112a 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index bba3bd5cfc1..d3a622f62cd 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_rtc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -41,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_rtc.h b/arch/arm/src/sam34/sam_rtc.h index 27ef853beed..1f8676cc1ec 100644 --- a/arch/arm/src/sam34/sam_rtc.h +++ b/arch/arm/src/sam34/sam_rtc.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_rtc.h * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index b4cbc9f256d..06c74401181 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_rtt.c * - * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Dioron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -44,6 +28,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_rtt.h b/arch/arm/src/sam34/sam_rtt.h index 43965e9cc08..1b1d3dad808 100644 --- a/arch/arm/src/sam34/sam_rtt.h +++ b/arch/arm/src/sam34/sam_rtt.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_rtt.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index e9438f2406c..c77be962f7e 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 50ff5060230..c280eaba81d 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_spi.c * - * Copyright (C) 2011, 2013-2014, 2016-2017 Gregory Nutt. All rights - * reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c index 2cbca1c1592..c251498f012 100644 --- a/arch/arm/src/sam34/sam_start.c +++ b/arch/arm/src/sam34/sam_start.c @@ -75,10 +75,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void sam_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif #ifdef CONFIG_ARMV7M_STACKCHECK /* We need to get r10 set before we can allow instrumentation calls */ @@ -194,47 +190,6 @@ static inline void sam_fpuconfig(void) # define sam_fpuconfig() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -346,18 +301,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); - -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index 6cc6014504a..2ad533283ce 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_tc.c * - * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Dioron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -44,6 +28,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_tc.h b/arch/arm/src/sam34/sam_tc.h index ccf4335a67d..7870d63e70f 100644 --- a/arch/arm/src/sam34/sam_tc.h +++ b/arch/arm/src/sam34/sam_tc.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_tc.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index 69ed0b2eb63..79e536884d8 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index a54decbe674..3f765c9b756 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index c4273446d05..7dd1fa89fa8 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_wdt.c * - * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -45,6 +29,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sam34/sam_wdt.h b/arch/arm/src/sam34/sam_wdt.h index a6371776d7a..2ad57a47835 100644 --- a/arch/arm/src/sam34/sam_wdt.h +++ b/arch/arm/src/sam34/sam_wdt.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/sam34/sam_wdt.h * - * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs index 9d9f9d22462..99c58d348ea 100644 --- a/arch/arm/src/sama5/Make.defs +++ b/arch/arm/src/sama5/Make.defs @@ -76,6 +76,7 @@ endif ifeq ($(CONFIG_BUILD_KERNEL),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c +CMN_CSRCS += arm_pthread_exit.c endif ifeq ($(CONFIG_ARCH_ADDRENV),y) diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index f2616730b1c..426c4969f9f 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_dbgu.c b/arch/arm/src/sama5/sam_dbgu.c index 9fc9a47c816..ad9dd51abbb 100644 --- a/arch/arm/src/sama5/sam_dbgu.c +++ b/arch/arm/src/sama5/sam_dbgu.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index 523a0c82ce2..a1f31ec457b 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index b659683d3dd..b1da50a685a 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index b77f2c49a98..0ac2d0a2881 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/sama5/sam_flexcom_serial.c b/arch/arm/src/sama5/sam_flexcom_serial.c index ba2df869699..210661d9c7e 100644 --- a/arch/arm/src/sama5/sam_flexcom_serial.c +++ b/arch/arm/src/sama5/sam_flexcom_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index 73f30c52aef..42808812677 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c index b4e21158765..a7b7ff530a8 100644 --- a/arch/arm/src/sama5/sam_irq.c +++ b/arch/arm/src/sama5/sam_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index b58aa296d97..dc6ccee5324 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index f4e849d1e01..791e608758e 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c index ab7cec3926a..6a5fadeeb59 100644 --- a/arch/arm/src/sama5/sam_rtc.c +++ b/arch/arm/src/sama5/sam_rtc.c @@ -28,6 +28,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index b8a198214ac..5a9676bb6aa 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index 657c1979e84..4bb9ae743e7 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -1,40 +1,20 @@ /**************************************************************************** * arch/arm/src/sama5/sam_spi.c * - * Copyright (C) 2013-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * This derives from SAM3/4 SPI driver: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Authors: Gregory Nutt - * Diego Sanchez - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_tickless.c b/arch/arm/src/sama5/sam_tickless.c index 0345a213c73..be12d5fe765 100644 --- a/arch/arm/src/sama5/sam_tickless.c +++ b/arch/arm/src/sama5/sam_tickless.c @@ -71,6 +71,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_timerisr.c b/arch/arm/src/sama5/sam_timerisr.c index c75ee57e1bc..c4e01f42407 100644 --- a/arch/arm/src/sama5/sam_timerisr.c +++ b/arch/arm/src/sama5/sam_timerisr.c @@ -26,6 +26,7 @@ #include #include +#include #include diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index b2627458bce..4800eefd8db 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index a24bc567d26..0cb544e8672 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index b7773730514..61146194b8c 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c index 63039b7a9e3..8817203f39d 100644 --- a/arch/arm/src/sama5/sam_xdmac.c +++ b/arch/arm/src/sama5/sam_xdmac.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd2l2/Make.defs b/arch/arm/src/samd2l2/Make.defs index 7fcf0f3045d..9e30a0eb0ad 100644 --- a/arch/arm/src/samd2l2/Make.defs +++ b/arch/arm/src/samd2l2/Make.defs @@ -32,6 +32,7 @@ CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/samd2l2/hardware/samd_ac.h b/arch/arm/src/samd2l2/hardware/samd_ac.h index b26a25610d8..3928dabc8dc 100644 --- a/arch/arm/src/samd2l2/hardware/samd_ac.h +++ b/arch/arm/src/samd2l2/hardware/samd_ac.h @@ -1,42 +1,28 @@ /**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_ac.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller - * Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15 + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller + * Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15 + */ + #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H diff --git a/arch/arm/src/samd2l2/hardware/samd_adc.h b/arch/arm/src/samd2l2/hardware/samd_adc.h index cef587fc1fa..c4d49661d49 100644 --- a/arch/arm/src/samd2l2/hardware/samd_adc.h +++ b/arch/arm/src/samd2l2/hardware/samd_adc.h @@ -1,41 +1,27 @@ /**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_adc.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Alexander Vasiljev + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * "Microchip SAM D21 Family Datasheet", Rev D - 9/2018 + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * "Microchip SAM D21 Family Datasheet", Rev D - 9/2018 + */ + #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H diff --git a/arch/arm/src/samd2l2/hardware/samd_i2s.h b/arch/arm/src/samd2l2/hardware/samd_i2s.h index e753262c075..12a537d53d0 100644 --- a/arch/arm/src/samd2l2/hardware/samd_i2s.h +++ b/arch/arm/src/samd2l2/hardware/samd_i2s.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_i2s.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/hardware/samd_tc.h b/arch/arm/src/samd2l2/hardware/samd_tc.h index 4c1f47f90a9..c91db467319 100644 --- a/arch/arm/src/samd2l2/hardware/samd_tc.h +++ b/arch/arm/src/samd2l2/hardware/samd_tc.h @@ -1,41 +1,27 @@ /**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_tc.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * "Microchip SAMD21 datasheet" + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * "Microchip SAMD21 datasheet" + */ + #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H diff --git a/arch/arm/src/samd2l2/hardware/samd_tcc.h b/arch/arm/src/samd2l2/hardware/samd_tcc.h index 14895a73860..25cd59ee728 100644 --- a/arch/arm/src/samd2l2/hardware/samd_tcc.h +++ b/arch/arm/src/samd2l2/hardware/samd_tcc.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_tcc.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/hardware/saml_adc.h b/arch/arm/src/samd2l2/hardware/saml_adc.h index af3b2cd8539..e2d8e3fc43f 100644 --- a/arch/arm/src/samd2l2/hardware/saml_adc.h +++ b/arch/arm/src/samd2l2/hardware/saml_adc.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_adc.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Alexander Vasiljev + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_ac.c b/arch/arm/src/samd2l2/sam_ac.c index 0a60a25b94b..a8b8479158c 100644 --- a/arch/arm/src/samd2l2/sam_ac.c +++ b/arch/arm/src/samd2l2/sam_ac.c @@ -1,41 +1,27 @@ /**************************************************************************** * arch/arm/src/samd2l2/sam_ac.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * 1. "Microchip SAM D21E / SAM D21G / SAM D21J Datasheet" + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * 1. "Microchip SAM D21E / SAM D21G / SAM D21J Datasheet" + */ + /**************************************************************************** * Included Files ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_ac.h b/arch/arm/src/samd2l2/sam_ac.h index 3863a764854..18b2fe5a96c 100644 --- a/arch/arm/src/samd2l2/sam_ac.h +++ b/arch/arm/src/samd2l2/sam_ac.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd2l2/sam_ac.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_adc.h b/arch/arm/src/samd2l2/sam_adc.h index 011fc34dd46..697867c69a8 100644 --- a/arch/arm/src/samd2l2/sam_adc.h +++ b/arch/arm/src/samd2l2/sam_adc.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd2l2/sam_adc.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Alexander Vasiljev + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_dac.h b/arch/arm/src/samd2l2/sam_dac.h index 4f433acf3af..b0ce04f1638 100644 --- a/arch/arm/src/samd2l2/sam_dac.h +++ b/arch/arm/src/samd2l2/sam_dac.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd2l2/sam_dac.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_dmac.c b/arch/arm/src/samd2l2/sam_dmac.c index c04e61633a8..6569135f57b 100644 --- a/arch/arm/src/samd2l2/sam_dmac.c +++ b/arch/arm/src/samd2l2/sam_dmac.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd2l2/sam_eic.c b/arch/arm/src/samd2l2/sam_eic.c index 8fe99d8d5a7..6b947870109 100644 --- a/arch/arm/src/samd2l2/sam_eic.c +++ b/arch/arm/src/samd2l2/sam_eic.c @@ -1,41 +1,27 @@ /**************************************************************************** * arch/arm/src/samd2l2/sam_eic.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * 1. "Microchip SAM D21E / SAM D21G / SAM D21J Datasheet" + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * 1. "Microchip SAM D21E / SAM D21G / SAM D21J Datasheet" + */ + /**************************************************************************** * Included Files ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_eic.h b/arch/arm/src/samd2l2/sam_eic.h index d1cffca0828..25679f161ec 100644 --- a/arch/arm/src/samd2l2/sam_eic.h +++ b/arch/arm/src/samd2l2/sam_eic.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd2l2/sam_eic.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_evsys.h b/arch/arm/src/samd2l2/sam_evsys.h index eee072ce36c..9ad57ec29b3 100644 --- a/arch/arm/src/samd2l2/sam_evsys.h +++ b/arch/arm/src/samd2l2/sam_evsys.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd2l2/sam_evsys.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_i2c_master.c b/arch/arm/src/samd2l2/sam_i2c_master.c index e61fac98dd3..3ea3db39186 100644 --- a/arch/arm/src/samd2l2/sam_i2c_master.c +++ b/arch/arm/src/samd2l2/sam_i2c_master.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd2l2/sam_idle.c b/arch/arm/src/samd2l2/sam_idle.c index a89cd819c69..7bb728db1fa 100644 --- a/arch/arm/src/samd2l2/sam_idle.c +++ b/arch/arm/src/samd2l2/sam_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/samd2l2/sam_irq.c b/arch/arm/src/samd2l2/sam_irq.c index 7a8a60d0f8d..2a0c0591143 100644 --- a/arch/arm/src/samd2l2/sam_irq.c +++ b/arch/arm/src/samd2l2/sam_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samd2l2/sam_serial.c b/arch/arm/src/samd2l2/sam_serial.c index 85049609961..a34605a7c77 100644 --- a/arch/arm/src/samd2l2/sam_serial.c +++ b/arch/arm/src/samd2l2/sam_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd2l2/sam_usb.c b/arch/arm/src/samd2l2/sam_usb.c index 829465ffb9b..d7802b82c70 100644 --- a/arch/arm/src/samd2l2/sam_usb.c +++ b/arch/arm/src/samd2l2/sam_usb.c @@ -91,6 +91,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd5e5/Make.defs b/arch/arm/src/samd5e5/Make.defs index 1750513a0d3..70371810f39 100644 --- a/arch/arm/src/samd5e5/Make.defs +++ b/arch/arm/src/samd5e5/Make.defs @@ -49,6 +49,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/samd5e5/sam_dmac.c b/arch/arm/src/samd5e5/sam_dmac.c index d44b15f6342..8f156a3de74 100644 --- a/arch/arm/src/samd5e5/sam_dmac.c +++ b/arch/arm/src/samd5e5/sam_dmac.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd5e5/sam_eic.c b/arch/arm/src/samd5e5/sam_eic.c index 1fd9ae7d7b1..3a45a8f6ea0 100644 --- a/arch/arm/src/samd5e5/sam_eic.c +++ b/arch/arm/src/samd5e5/sam_eic.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd5e5/sam_eic.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd5e5/sam_eic.h b/arch/arm/src/samd5e5/sam_eic.h index be64b7e5f1e..28df49ce5ce 100644 --- a/arch/arm/src/samd5e5/sam_eic.h +++ b/arch/arm/src/samd5e5/sam_eic.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/samd5e5/sam_eic.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samd5e5/sam_gmac.c b/arch/arm/src/samd5e5/sam_gmac.c index 097320a2930..b9231674001 100644 --- a/arch/arm/src/samd5e5/sam_gmac.c +++ b/arch/arm/src/samd5e5/sam_gmac.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/samd5e5/sam_i2c_master.c b/arch/arm/src/samd5e5/sam_i2c_master.c index 138047225ec..cd0b7b8de80 100644 --- a/arch/arm/src/samd5e5/sam_i2c_master.c +++ b/arch/arm/src/samd5e5/sam_i2c_master.c @@ -48,6 +48,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd5e5/sam_idle.c b/arch/arm/src/samd5e5/sam_idle.c index 3bed171f581..03af3e34bd5 100644 --- a/arch/arm/src/samd5e5/sam_idle.c +++ b/arch/arm/src/samd5e5/sam_idle.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/src/samd5e5/sam_irq.c b/arch/arm/src/samd5e5/sam_irq.c index 23f5dcc9d81..506038fa385 100644 --- a/arch/arm/src/samd5e5/sam_irq.c +++ b/arch/arm/src/samd5e5/sam_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samd5e5/sam_progmem.c b/arch/arm/src/samd5e5/sam_progmem.c index 0d17ee230b2..927b665e3b5 100644 --- a/arch/arm/src/samd5e5/sam_progmem.c +++ b/arch/arm/src/samd5e5/sam_progmem.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samd5e5/sam_serial.c b/arch/arm/src/samd5e5/sam_serial.c index 7a2e7e662b1..855b7dc3f31 100644 --- a/arch/arm/src/samd5e5/sam_serial.c +++ b/arch/arm/src/samd5e5/sam_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd5e5/sam_start.c b/arch/arm/src/samd5e5/sam_start.c index fbabe0c0c96..5dc64767dbb 100644 --- a/arch/arm/src/samd5e5/sam_start.c +++ b/arch/arm/src/samd5e5/sam_start.c @@ -77,10 +77,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void sam_fpu_configure(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif #ifdef CONFIG_ARMV7M_STACKCHECK /* We need to get r10 set before we can allow instrumentation calls */ @@ -196,47 +192,6 @@ static inline void sam_fpu_configure(void) # define sam_fpu_configure() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -342,18 +297,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); - -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/samd5e5/sam_tickless.c b/arch/arm/src/samd5e5/sam_tickless.c index a94640df90b..9bfeb4e24ae 100644 --- a/arch/arm/src/samd5e5/sam_tickless.c +++ b/arch/arm/src/samd5e5/sam_tickless.c @@ -71,6 +71,7 @@ #include #include +#include #include #include "arm_arch.h" diff --git a/arch/arm/src/samd5e5/sam_usb.c b/arch/arm/src/samd5e5/sam_usb.c index a2ad5fd84b9..b74579b3a1c 100644 --- a/arch/arm/src/samd5e5/sam_usb.c +++ b/arch/arm/src/samd5e5/sam_usb.c @@ -94,6 +94,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samd5e5/sam_wdt.c b/arch/arm/src/samd5e5/sam_wdt.c index ee2b340c6a6..86e2e69bffc 100644 --- a/arch/arm/src/samd5e5/sam_wdt.c +++ b/arch/arm/src/samd5e5/sam_wdt.c @@ -28,6 +28,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index a49c36982d2..7be09383c91 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -67,6 +67,7 @@ ifeq ($(CONFIG_ARM_MPU),y) CMN_CSRCS += arm_mpu.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/samv7/hardware/sam_chipid.h b/arch/arm/src/samv7/hardware/sam_chipid.h index cda948bae7b..a87893dc819 100644 --- a/arch/arm/src/samv7/hardware/sam_chipid.h +++ b/arch/arm/src/samv7/hardware/sam_chipid.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/samv7/hardware/sam_chipid.h - * CHIPID Register Definitions for the SAMV7 * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Michael Spahlinger + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/hardware/sam_rstc.h b/arch/arm/src/samv7/hardware/sam_rstc.h index 6a6acf3edfa..18960b978e8 100644 --- a/arch/arm/src/samv7/hardware/sam_rstc.h +++ b/arch/arm/src/samv7/hardware/sam_rstc.h @@ -1,37 +1,21 @@ /**************************************************************************** * arch/arm/src/samv7/hardware/sam_rstc.h - * Reset Controller (RSTC) definitions for the SAMV71 * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Michael Spahlinger + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * http://www.apache.org/licenses/LICENSE-2.0 * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. +y * ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RSTC_H diff --git a/arch/arm/src/samv7/sam_allocateheap.c b/arch/arm/src/samv7/sam_allocateheap.c index 9dc861a3f4e..c40d109f1ad 100644 --- a/arch/arm/src/samv7/sam_allocateheap.c +++ b/arch/arm/src/samv7/sam_allocateheap.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_dac.c b/arch/arm/src/samv7/sam_dac.c index 15ab4f7799e..865023dd455 100644 --- a/arch/arm/src/samv7/sam_dac.c +++ b/arch/arm/src/samv7/sam_dac.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index fea5986dbde..a70bf042069 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c index 2e75cfb54a2..70412a37ca0 100644 --- a/arch/arm/src/samv7/sam_irq.c +++ b/arch/arm/src/samv7/sam_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index d7c563a1a94..ae455c65201 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index a670f0bbc3d..3cd291cc2f6 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index e8f87369116..a8be404699e 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index b8ea53fba15..99e05a2900d 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/samv7/sam_spi.c * - * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -1437,20 +1421,31 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - uint8_t txbyte; - uint8_t rxbyte; + struct sam_spics_s *spics = (struct sam_spics_s *)dev; + if (spics->nbits <= 8) + { + uint8_t txbyte; + uint8_t rxbyte; - /* spi_exchange can do this. Note: right now, this only deals with 8-bit - * words. If the SPI interface were configured for words of other sizes, - * this would fail. - */ + txbyte = (uint8_t)wd; + rxbyte = (uint8_t)0; + spi_exchange(dev, &txbyte, &rxbyte, 1); - txbyte = (uint8_t)wd; - rxbyte = (uint8_t)0; - spi_exchange(dev, &txbyte, &rxbyte, 1); + spiinfo("Sent %02x received %02x\n", txbyte, rxbyte); + return (uint32_t)rxbyte; + } + else + { + uint16_t txword; + uint16_t rxword; - spiinfo("Sent %02x received %02x\n", txbyte, rxbyte); - return (uint32_t)rxbyte; + txword = (uint16_t)wd; + rxword = (uint16_t)0; + spi_exchange(dev, &txword, &rxword, 1); + + spiinfo("Sent %02x received %02x\n", txword, rxword); + return (uint32_t)rxword; + } } /**************************************************************************** diff --git a/arch/arm/src/samv7/sam_spi.h b/arch/arm/src/samv7/sam_spi.h index 22374e2f2cf..93592b5c775 100644 --- a/arch/arm/src/samv7/sam_spi.h +++ b/arch/arm/src/samv7/sam_spi.h @@ -142,8 +142,8 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -struct spi_dev_s; /* Forward reference */ -struct spi_sctrlr_s; /* Forward reference */ +struct spi_dev_s; /* Forward reference */ +struct spi_slave_ctrlr_s; /* Forward reference */ /**************************************************************************** * Name: sam_spibus_initialize @@ -176,7 +176,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port); * ****************************************************************************/ -FAR struct spi_sctrlr_s *sam_spi_slave_initialize(int port); +FAR struct spi_slave_ctrlr_s *sam_spi_slave_initialize(int port); /**************************************************************************** * Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index a950dbfd143..6465800a4a8 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -72,9 +72,13 @@ struct sam_spidev_s { - struct spi_sctrlr_s sctrlr; /* Externally visible part of the SPI slave - * controller interface */ - struct spi_sdev_s *sdev; /* Bound SPI slave device interface */ + /* Externally visible part of the SPI slave controller interface */ + + struct spi_slave_ctrlr_s ctrlr; + + /* Bound SPI slave device interface */ + + struct spi_slave_dev_s *dev; xcpt_t handler; /* SPI interrupt handler */ uint32_t base; /* SPI controller register base address */ sem_t spisem; /* Assures mutually exclusive access to SPI */ @@ -111,15 +115,15 @@ struct sam_spidev_s #ifdef CONFIG_SAMV7_SPI_REGDEBUG static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, - uint32_t value, uint32_t address); + uint32_t value, uint32_t address); #else # define spi_checkreg(priv,wr,value,address) (false) #endif static uint32_t spi_getreg(struct sam_spidev_s *priv, - unsigned int offset); + unsigned int offset); static void spi_putreg(struct sam_spidev_s *priv, uint32_t value, - unsigned int offset); + unsigned int offset); #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg); @@ -139,20 +143,21 @@ static int spi_interrupt(int irq, void *context, FAR void *arg); static uint16_t spi_dequeue(struct sam_spidev_s *priv); static void spi_setmode(struct sam_spidev_s *priv, - enum spi_smode_e mode); + enum spi_slave_mode_e mode); static void spi_setbits(struct sam_spidev_s *priv, - int nbits); + int nbits); /* SPI slave controller methods */ -static void spi_bind(struct spi_sctrlr_s *sctrlr, - struct spi_sdev_s *sdev, enum spi_smode_e mode, - int nbits); -static void spi_unbind(struct spi_sctrlr_s *sctrlr); -static int spi_enqueue(struct spi_sctrlr_s *sctrlr, - FAR const void *data, size_t nwords); -static bool spi_qfull(struct spi_sctrlr_s *sctrlr); -static void spi_qflush(struct spi_sctrlr_s *sctrlr); +static void spi_bind(struct spi_slave_ctrlr_s *ctrlr, + struct spi_slave_dev_s *dev, + enum spi_slave_mode_e mode, + int nbits); +static void spi_unbind(struct spi_slave_ctrlr_s *ctrlr); +static int spi_enqueue(struct spi_slave_ctrlr_s *ctrlr, + FAR const void *data, size_t len); +static bool spi_qfull(struct spi_slave_ctrlr_s *ctrlr); +static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr); /**************************************************************************** * Private Data @@ -168,7 +173,7 @@ static const uint8_t g_csroffset[4] = /* SPI slave controller driver operations */ -static const struct spi_sctrlrops_s g_sctrlr_ops = +static const struct spi_slave_ctrlrops_s g_ctrlr_ops = { .bind = spi_bind, .unbind = spi_unbind, @@ -180,13 +185,13 @@ static const struct spi_sctrlrops_s g_sctrlr_ops = #ifdef CONFIG_SAMV7_SPI0_SLAVE /* This is the overall state of the SPI0 controller */ -static struct sam_spidev_s g_spi0_sctrlr; +static struct sam_spidev_s g_spi0_ctrlr; #endif #ifdef CONFIG_SAMV7_SPI1_SLAVE /* This is the overall state of the SPI0 controller */ -static struct sam_spidev_s g_spi1_sctrlr; +static struct sam_spidev_s g_spi1_ctrlr; #endif /**************************************************************************** @@ -468,7 +473,7 @@ static int spi_interrupt(int irq, void *context, FAR void *arg) if (priv->nss) { priv->nss = false; - SPI_SDEV_SELECT(priv->sdev, true); + SPIS_DEV_SELECT(priv->dev, true); } /* Read the RDR to get the data and to clear the pending RDRF @@ -486,7 +491,7 @@ static int spi_interrupt(int irq, void *context, FAR void *arg) /* Report the receipt of data to the SPI device driver */ - SPI_SDEV_RECEIVE(priv->sdev, (const uint16_t *)&data, + SPIS_DEV_RECEIVE(priv->dev, (const uint16_t *)&data, sizeof(data)); } @@ -552,7 +557,7 @@ static int spi_interrupt(int irq, void *context, FAR void *arg) /* Report the state change to the SPI device driver */ priv->nss = true; - SPI_SDEV_SELECT(priv->sdev, false); + SPIS_DEV_SELECT(priv->dev, false); } } @@ -630,7 +635,7 @@ static uint16_t spi_dequeue(struct sam_spidev_s *priv) * Name: spi_setmode * * Description: - * Set the SPI mode. See enum spi_smode_e for mode definitions + * Set the SPI mode. See enum spi_slave_mode_e for mode definitions * * Input Parameters: * priv - SPI device data structure @@ -641,7 +646,8 @@ static uint16_t spi_dequeue(struct sam_spidev_s *priv) * ****************************************************************************/ -static void spi_setmode(struct sam_spidev_s *priv, enum spi_smode_e mode) +static void spi_setmode(struct sam_spidev_s *priv, + enum spi_slave_mode_e mode) { uint32_t regval; @@ -743,35 +749,36 @@ static void spi_setbits(struct sam_spidev_s *priv, int nbits) * * Description: * Bind the SPI slave device interface to the SPI slave controller - * interface and configure the SPI interface. Upon return, the SPI + * interface and configure the SPI interface. Upon return, the SPI * slave controller driver is fully operational and ready to perform * transfers. * * Input Parameters: - * sctrlr - SPI slave controller interface instance - * sdev - SPI slave device interface instance - * mode - The SPI mode requested - * nbits - The number of bits requests. - * If value is greater > 0 then it implies MSB first - * If value is below < 0, then it implies LSB first with -nbits + * ctrlr - SPI Slave controller interface instance + * dev - SPI Slave device interface instance + * mode - The SPI Slave mode requested + * nbits - The number of bits requested. + * If value is greater than 0, then it implies MSB first + * If value is less than 0, then it implies LSB first with -nbits * * Returned Value: - * none + * None. * ****************************************************************************/ -static void spi_bind(struct spi_sctrlr_s *sctrlr, - struct spi_sdev_s *sdev, enum spi_smode_e mode, +static void spi_bind(struct spi_slave_ctrlr_s *ctrlr, + struct spi_slave_dev_s *dev, + enum spi_slave_mode_e mode, int nbits) { - struct sam_spidev_s *priv = (struct sam_spidev_s *)sctrlr; + struct sam_spidev_s *priv = (struct sam_spidev_s *)ctrlr; uint32_t regval; int ret; FAR const void *data; - spiinfo("sdev=%p mode=%d nbits=%d\n", sdv, mode, nbits); + spiinfo("dev=%p mode=%d nbits=%d\n", sdv, mode, nbits); - DEBUGASSERT(priv != NULL && priv->sdev == NULL && sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev == NULL && dev != NULL); /* Get exclusive access to the SPI device */ @@ -790,7 +797,7 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr, * controller interface. */ - priv->sdev = sdev; + priv->dev = dev; /* Call the slaved device's select() and cmddata() methods to indicate * the initial state of the chip select and command/data discretes. @@ -804,9 +811,9 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr, * the Command/Data indication (not yet impklemented). */ - SPI_SDEV_SELECT(sdev, false); + SPIS_DEV_SELECT(dev, false); #warning Missing logic - SPI_SDEV_CMDDATA(sdev, false); + SPIS_DEV_CMDDATA(dev, false); /* Discard any queued data */ @@ -817,7 +824,7 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr, * be shifted out the SPI clock is detected. */ - SPI_SDEV_GETDATA(sdev, &data); + SPIS_DEV_GETDATA(dev, &data); priv->outval = *(const uint16_t *)data; spi_putreg(priv, priv->outval, SAM_SPI_TDR_OFFSET); @@ -865,25 +872,25 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr, * * Description: * Un-bind the SPI slave device interface from the SPI slave controller - * interface. Reset the SPI interface and restore the SPI slave - * controller driver to its initial state, + * interface. Reset the SPI interface and restore the SPI slave + * controller driver to its initial state. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * none + * None. * ****************************************************************************/ -static void spi_unbind(struct spi_sctrlr_s *sctrlr) +static void spi_unbind(struct spi_slave_ctrlr_s *ctrlr) { - struct sam_spidev_s *priv = (struct sam_spidev_s *)sctrlr; + struct sam_spidev_s *priv = (struct sam_spidev_s *)ctrlr; DEBUGASSERT(priv != NULL); - spiinfo("Unbinding %p\n", priv->sdev); + spiinfo("Unbinding %p\n", priv->dev); - DEBUGASSERT(priv->sdev != NULL); + DEBUGASSERT(priv->dev != NULL); /* Get exclusive access to the SPI device */ @@ -895,7 +902,7 @@ static void spi_unbind(struct spi_sctrlr_s *sctrlr) /* Unbind the SPI slave interface */ - priv->sdev = NULL; + priv->dev = NULL; /* Disable the SPI peripheral */ @@ -913,15 +920,18 @@ static void spi_unbind(struct spi_sctrlr_s *sctrlr) * Name: spi_enqueue * * Description: - * Enqueue the next value to be shifted out from the interface. This adds + * Enqueue the next value to be shifted out from the interface. This adds * the word the controller driver for a subsequent transfer but has no - * effect on anyin-process or currently "committed" transfers + * effect on any in-process or currently "committed" transfers. * * Input Parameters: - * sctrlr - SPI slave controller interface instance - * data - Command/data mode data value to be shifted out. The width of - * the data must be the same as the nbits parameter previously - * provided to the bind() methods. + * ctrlr - SPI Slave controller interface instance + * data - Pointer to the command/data mode data to be shifted out. + * The data width must be aligned to the nbits parameter which was + * previously provided to the bind() method. + * len - Number of units of "nbits" wide to enqueue, + * "nbits" being the data width previously provided to the bind() + * method. * * Returned Value: * Zero if the word was successfully queue; A negated errno valid is @@ -930,17 +940,17 @@ static void spi_unbind(struct spi_sctrlr_s *sctrlr) * ****************************************************************************/ -static int spi_enqueue(struct spi_sctrlr_s *sctrlr, FAR const void *data, - size_t nwords) +static int spi_enqueue(struct spi_slave_ctrlr_s *ctrlr, + FAR const void *data, size_t len) { - struct sam_spidev_s *priv = (struct sam_spidev_s *)sctrlr; + struct sam_spidev_s *priv = (struct sam_spidev_s *)ctrlr; irqstate_t flags; uint32_t regval; int next; int ret; spiinfo("data=%04x\n", *(const uint16_t *)data); - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev != NULL); /* Get exclusive access to the SPI device */ @@ -1001,22 +1011,22 @@ static int spi_enqueue(struct spi_sctrlr_s *sctrlr, FAR const void *data, * additional word to the queue. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * true if the output wueue is full + * true if the output queue is full, false otherwise. * ****************************************************************************/ -static bool spi_qfull(struct spi_sctrlr_s *sctrlr) +static bool spi_qfull(struct spi_slave_ctrlr_s *ctrlr) { - struct sam_spidev_s *priv = (struct sam_spidev_s *)sctrlr; + struct sam_spidev_s *priv = (struct sam_spidev_s *)ctrlr; irqstate_t flags; bool bret; int ret; int next; - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev != NULL); /* Get exclusive access to the SPI device */ @@ -1053,26 +1063,26 @@ static bool spi_qfull(struct spi_sctrlr_s *sctrlr) * Name: spi_qflush * * Description: - * Discard all saved values in the output queue. On return from this - * function the output queue will be empty. Any in-progress or otherwise + * Discard all saved values in the output queue. On return from this + * function the output queue will be empty. Any in-progress or otherwise * "committed" output values may not be flushed. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * None + * None. * ****************************************************************************/ -static void spi_qflush(struct spi_sctrlr_s *sctrlr) +static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) { - struct sam_spidev_s *priv = (struct sam_spidev_s *)sctrlr; + struct sam_spidev_s *priv = (struct sam_spidev_s *)ctrlr; irqstate_t flags; spiinfo("data=%04x\n", data); - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev != NULL); /* Get exclusive access to the SPI device */ @@ -1106,7 +1116,7 @@ static void spi_qflush(struct spi_sctrlr_s *sctrlr) * ****************************************************************************/ -struct spi_sctrlr_s *sam_spi_slave_initialize(int port) +struct spi_slave_ctrlr_s *sam_spi_slave_initialize(int port) { struct sam_spidev_s *priv; int spino = (port & __SPI_SPI_MASK) >> __SPI_SPI_SHIFT; @@ -1128,18 +1138,18 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port) #if defined(CONFIG_SAMV7_SPI0_SLAVE) && defined(CONFIG_SAMV7_SPI1_SLAVE) if (spino == 0) { - priv = &g_spi0_sctrlr; + priv = &g_spi0_ctrlr; } else { - priv = &g_spi1_sctrlr; + priv = &g_spi1_ctrlr; } #elif defined(CONFIG_SAMV7_SPI0_SLAVE) - priv = &g_spi0_sctrlr; + priv = &g_spi0_ctrlr; #elif defined(CONFIG_SAMV7_SPI1_SLAVE) - priv = &g_spi1_sctrlr; + priv = &g_spi1_ctrlr; #endif /* Set up the initial state for this chip select structure. Other fields @@ -1150,7 +1160,7 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port) /* Initialize the SPI operations */ - priv->sctrlr.ops = &g_sctrlr_ops; + priv->ctrlr.ops = &g_ctrlr_ops; /* Save the SPI controller number */ @@ -1262,6 +1272,6 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port) priv->nbits = 8; spiinfo("csr[offset=%02x]=%08x\n", offset, regval); - return &priv->sctrlr; + return &priv->ctrlr; } #endif /* CONFIG_SAMV7_SPI_SLAVE */ diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index baa596b697b..f20eb01f7f6 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -86,10 +86,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void sam_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Private Functions @@ -240,47 +236,6 @@ static inline void sam_tcmenable(void) #endif } -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -386,17 +341,9 @@ void __start(void) /* Then start NuttX */ -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/samv7/sam_tickless.c b/arch/arm/src/samv7/sam_tickless.c index a47d3de8802..ae567fb807d 100644 --- a/arch/arm/src/samv7/sam_tickless.c +++ b/arch/arm/src/samv7/sam_tickless.c @@ -71,6 +71,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index 11e71233df4..eb13292e405 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index f6b927bd162..70367a8b621 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index 9898134a057..6de17957b8c 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index 0cafcbbcdf3..0c24ec03d47 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 070928a4b7b..64da99a6411 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1553,6 +1553,7 @@ config STM32_STM32F33XX select STM32_HAVE_IP_DBGMCU_V2 select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_IP_ADC_V2 + select STM32_HAVE_IP_COMP_V1 select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V2 @@ -1932,6 +1933,7 @@ config STM32_STM32G4XXX select STM32_HAVE_DMAMUX select STM32_HAVE_IP_DBGMCU_V3 select STM32_HAVE_IP_ADC_V2 + select STM32_HAVE_IP_COMP_V2 select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V2 select STM32_HAVE_IP_TIMERS_V3 @@ -2616,6 +2618,14 @@ config STM32_HAVE_IP_ADC_V2_BASIC default n select STM32_HAVE_IP_ADC_V2 +config STM32_HAVE_IP_COMP_V1 + bool + default n + +config STM32_HAVE_IP_COMP_V2 + bool + default n + # These are the peripheral selections proper config STM32_ADC1 @@ -3347,7 +3357,7 @@ config STM32_PWM config STM32_COMP bool default n - depends on STM32_STM32L15XX || STM32_STM32F33XX + depends on STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX config STM32_OPAMP bool @@ -3915,7 +3925,7 @@ config STM32_TIM1_CHANNEL5 default n depends on STM32_HAVE_IP_TIMERS_V2 ---help--- - Enables channel 5 (no available externaly) + Enables channel 5 (not available externally) if STM32_TIM1_CHANNEL5 @@ -3939,7 +3949,7 @@ config STM32_TIM1_CHANNEL6 default n depends on STM32_HAVE_IP_TIMERS_V2 ---help--- - Enables channel 6 (no available externaly) + Enables channel 6 (not available externally) if STM32_TIM1_CHANNEL6 @@ -4945,7 +4955,7 @@ config STM32_TIM8_CHANNEL5 default n depends on STM32_HAVE_IP_TIMERS_V2 ---help--- - Enables channel 5 (no available externaly) + Enables channel 5 (not available externally) if STM32_TIM8_CHANNEL5 @@ -4969,7 +4979,7 @@ config STM32_TIM8_CHANNEL6 default n depends on STM32_HAVE_IP_TIMERS_V2 ---help--- - Enables channel 6 (no available externaly) + Enables channel 6 (not available externally) if STM32_TIM8_CHANNEL6 @@ -8500,6 +8510,403 @@ config STM32_ADC5_JEXTSEL endmenu +menu "COMP Configuration" + depends on STM32_COMP && STM32_HAVE_IP_COMP_V2 + +config STM32_COMP1_OUT + bool "COMP1 GPIO Output" + depends on STM32_COMP1 + default n + ---help--- + Enables COMP1 output. + +config STM32_COMP1_INM + int "COMP1 inverting input assignment" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects COMP1 inverting input pin. + +config STM32_COMP1_INP + int "COMP1 non-inverting input assignment" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 non-inverting input pin. + +config STM32_COMP1_POL + int "COMP1 polarity" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 output polarity. + +config STM32_COMP1_HYST + int "COMP1 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP1. + +config STM32_COMP1_BLANKSEL + int "COMP1 blanking signal select" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP1. + +config STM32_COMP1_LOCK + int "COMP1 COMP_CxCSR register lock" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP2_OUT + bool "COMP2 GPIO Output" + depends on STM32_COMP2 + default n + ---help--- + Enables COMP2 output. + +config STM32_COMP2_INM + int "COMP2 inverting input assignment" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects COMP2 inverting input pin. + +config STM32_COMP2_INP + int "COMP2 non-inverting input assignment" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Selects COMP2 non-inverting input pin. + +config STM32_COMP2_POL + int "COMP2 polarity" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Selects COMP2 output polarity. + +config STM32_COMP2_HYST + int "COMP2 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP2. + +config STM32_COMP2_BLANKSEL + int "COMP2 blanking signal select" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP2. + +config STM32_COMP2_LOCK + int "COMP2 COMP_CxCSR register lock" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP3_OUT + bool "COMP3 GPIO Output" + depends on STM32_COMP3 + default n + ---help--- + Enables COMP3 output. + +config STM32_COMP3_INM + int "COMP3 inverting input assignment" + depends on STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects COMP3 inverting input pin. + +config STM32_COMP3_INP + int "COMP3 non-inverting input assignment" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 non-inverting input pin. + +config STM32_COMP3_POL + int "COMP3 polarity" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 output polarity. + +config STM32_COMP3_HYST + int "COMP3 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP3. + +config STM32_COMP3_BLANKSEL + int "COMP3 blanking signal select" + depends on STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP3. + +config STM32_COMP3_LOCK + int "COMP3 COMP_CxCSR register lock" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP4_OUT + bool "COMP4 GPIO Output" + depends on STM32_COMP4 + default n + ---help--- + Enables COMP4 output. + +config STM32_COMP4_INM + int "COMP4 inverting input assignment" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects COMP4 inverting input pin. + +config STM32_COMP4_INP + int "COMP4 non-inverting input assignment" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Selects COMP4 non-inverting input pin. + +config STM32_COMP4_POL + int "COMP4 polarity" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Selects COMP4 output polarity. + +config STM32_COMP4_HYST + int "COMP4 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP4. + +config STM32_COMP4_BLANKSEL + int "COMP4 blanking signal select" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP4. + +config STM32_COMP4_LOCK + int "COMP4 COMP_CxCSR register lock" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP5_OUT + bool "COMP5 GPIO Output" + depends on STM32_COMP5 + default n + ---help--- + Enables COMP5 output. + +config STM32_COMP5_INM + int "COMP5 inverting input assignment" + depends on STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects COMP5 inverting input pin. + +config STM32_COMP5_INP + int "COMP5 non-inverting input assignment" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Selects COMP5 non-inverting input pin. + +config STM32_COMP5_POL + int "COMP5 polarity" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Selects COMP5 output polarity. + +config STM32_COMP5_HYST + int "COMP5 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP5. + +config STM32_COMP5_BLANKSEL + int "COMP5 blanking signal select" + depends on STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP5. + +config STM32_COMP5_LOCK + int "COMP5 COMP_CxCSR register lock" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP6_OUT + bool "COMP6 GPIO Output" + depends on STM32_COMP6 + default n + ---help--- + Enables COMP6 output. + +config STM32_COMP6_INM + int "COMP6 inverting input assignment" + depends on STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects COMP6 inverting input pin. + +config STM32_COMP6_INP + int "COMP6 non-inverting input assignment" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Selects COMP6 non-inverting input pin. + +config STM32_COMP6_POL + int "COMP6 polarity" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Selects COMP6 output polarity. + +config STM32_COMP6_HYST + int "COMP6 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP6. + +config STM32_COMP6_BLANKSEL + int "COMP6 blanking signal select" + depends on STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP6. + +config STM32_COMP6_LOCK + int "COMP6 COMP_CxCSR register lock" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP7_OUT + bool "COMP7 GPIO Output" + depends on STM32_COMP7 + default n + ---help--- + Enables COMP7 output. + +config STM32_COMP7_INM + int "COMP7 inverting input assignment" + depends on STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects COMP7 inverting input pin. + +config STM32_COMP7_INP + int "COMP7 non-inverting input assignment" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Selects COMP7 non-inverting input pin. + +config STM32_COMP7_POL + int "COMP7 polarity" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Selects COMP7 output polarity. + +config STM32_COMP7_HYST + int "COMP7 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP7. + +config STM32_COMP7_BLANKSEL + int "COMP7 blanking signal select" + depends on STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP7. + +config STM32_COMP7_LOCK + int "COMP7 COMP_CxCSR register lock" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endmenu + menu "SDADC Configuration" depends on STM32_SDADC @@ -10902,4 +11309,19 @@ config STM32_FOC_USE_ADC4 select STM32_ADC4 select STM32_ADC3_JEXTSEL +config STM32_FOC_G4_ADCCHAN0_WORKAROUND + bool "FOC G4 ADC channel 0 unwanted conversion workaround" + default n + ---help--- + Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 + conversion when a regular conversion is interrupted by an injected conversion. + This FOC implementation uses injected conversion to sample phase currents + and allows user to use regular conversion as an auxiliary analog conversion. + In this case, there is a certain probability that regular conversion will be + interrupted by an injected conversion that will lead to an incorrect reading + of phase currents. + + This workaround inserts a dummy conversion at the beginning of the injected + sequence. For more details look at the chip errata documents. + endif #STM32_FOC diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 9364bb75abb..c013fd08da0 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -58,7 +58,7 @@ CMN_CSRCS += arm_mpu.c endif ifeq ($(CONFIG_BUILD_PROTECTED),y) -CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/stm32/hardware/stm32_comp.h b/arch/arm/src/stm32/hardware/stm32_comp.h new file mode 100644 index 00000000000..ec007445431 --- /dev/null +++ b/arch/arm/src/stm32/hardware/stm32_comp.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/arm/src/stm32/hardware/stm32_comp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H +#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#ifdef CONFIG_STM32_COMP + +/* Include the correct COMP register definitions for + * selected STM32 COMP IP core: + */ + +/* If more than one COMP IP ensure that only one is selected */ + +#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +# if defined(CONFIG_STM32_STM32F33XX) +# include "stm32f33xxx_comp.h" +# else +# error "Device not supported." +# endif +#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +# if defined(CONFIG_STM32_STM32G4XXX) +# include "stm32g4xxxx_comp.h" +# else +# error "Device not supported." +# endif +#else +# error "STM32 COMP IP not supported." +#endif + +#endif /* CONFIG_STM32_COMP */ + +#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fmc.h b/arch/arm/src/stm32/hardware/stm32_fmc.h index dfb157e34ba..0a5203d7899 100644 --- a/arch/arm/src/stm32/hardware/stm32_fmc.h +++ b/arch/arm/src/stm32/hardware/stm32_fmc.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/hardware/stm32_fmc.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Jason T. Harris + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h index dabccee4119..a1ffa58776a 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h @@ -826,6 +826,7 @@ # define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ # define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ #endif +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1198,7 +1199,6 @@ #define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ #define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */ #ifdef HAVE_GTIM_CCXNP # define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ #endif @@ -1222,6 +1222,7 @@ * no CC4N output, so it does not make sense! */ #endif +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v3.h b/arch/arm/src/stm32/hardware/stm32_tim_v3.h index 61a77c516c7..f5e546b771c 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v3.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v3.h @@ -769,6 +769,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 Output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 Output Enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 Output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* ATIM Counter (CNT) */ @@ -1236,6 +1237,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 Output Enable */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 Output Polarity */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary Output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* GTIM Counter (CNT) */ diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h b/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h index 82b742d7d14..9ed17ed2915 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h +++ b/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_COMP_H +#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_COMP_H /**************************************************************************** * Included Files @@ -33,6 +33,14 @@ * Pre-processor Definitions ****************************************************************************/ +/* This is implementation for STM32 COMP IP version 1. Supported devices + * - STM32F33XX + */ + +#define HAVE_IP_COMP_V1 1 + +/* TODO: Undef other STM32 COMP IP versions */ + /* Register Offsets *********************************************************/ #define STM32_COMP2_CSR_OFFSET 0x0020 /* COMP2 Control register */ @@ -105,4 +113,4 @@ #define COMP_CSR_OUT (1 << 30) /* Bit 30: comparator output */ #define COMP_CSR_LOCK (1 << 31) /* Bit 31: comparator lock */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_COMP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h index 58bee462918..4993271b46f 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h +++ b/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Modified for STM32F373 by Marten Svanfeldt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h index fafb1dee556..f054f8c3ef8 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Modified for STM32F373 by Marten Svanfeldt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h index a099f20c204..288f67c815a 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h +++ b/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h - * For STM32F37xx advanced ARM-based 32-bit MCUs * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Modified for STM32F373 by Marten Svanfeldt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h b/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h index fcb3001e4e0..b9ac642ac73 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h +++ b/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Modified for STM32F373 by Marten Svanfeldt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h b/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h index 48a9ae47aff..a0d306a51fd 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h @@ -313,82 +313,50 @@ #define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) #define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13) -/* OPAMP ********************************************************************/ +/* OPAMP (Table 200 from Reference Manual) **********************************/ -#define GPIO_OPAMP1_VINM (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) #define GPIO_OPAMP1_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM_SEC (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP1_VINP_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP1_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP1_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP1_VINM1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_OPAMP1_VINP0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP1_VINP1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINP2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) #define GPIO_OPAMP1_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) -#define GPIO_OPAMP2_VINM (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) #define GPIO_OPAMP2_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_SEC (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP2_VINP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP2_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP2_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP2_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) +#define GPIO_OPAMP2_VINM1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_OPAMP2_VINP0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP2_VINP1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) +#define GPIO_OPAMP2_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP2_VINP3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN14) #define GPIO_OPAMP2_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#define GPIO_OPAMP3_VINM0_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM1_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP3_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP3_VINP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP3_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP3_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP3_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP3_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) +#define GPIO_OPAMP3_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) +#define GPIO_OPAMP3_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP3_VINP1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP3_VINP2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_OPAMP3_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP4_VINM (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) #define GPIO_OPAMP4_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM_SEC (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP4_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP4_VINM1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) + +#define GPIO_OPAMP4_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP4_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP4_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) #define GPIO_OPAMP4_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP5_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINP (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP5_VINP_SEC (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) +#define GPIO_OPAMP5_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) +#define GPIO_OPAMP5_VINM1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP5_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP5_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP5_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) #define GPIO_OPAMP5_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) -#define GPIO_OPAMP6_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP6_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP6_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP6_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP6_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP6_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_OPAMP6_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) +#define GPIO_OPAMP6_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN9) +#define GPIO_OPAMP6_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) #define GPIO_OPAMP6_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) /* QUADSPI ******************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h b/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h index 88f5cd8e746..0cf23f8dbc4 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h @@ -25,6 +25,421 @@ * Pre-processor Definitions ****************************************************************************/ -#error missing pinmap for STM32G4XXK +/* Alternate Pin Functions. All members of the STM32G4xxxx family share the + * same pin multiplexing (although they differ in the pins physically + * available). + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if CAN1_RX connects via PA11 on some board, then the following + * definitions should appear in the board.h header file for that board: + * + * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 + * + * The driver will then automatically configure PA11 as the CAN1 RX pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. + */ + +/* ADC - Analog Digital Converter *******************************************/ + +#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_ADC1_IN10 (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN0) +#define GPIO_ADC1_IN15 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) + +#define GPIO_ADC2_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC2_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_ADC2_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) +#define GPIO_ADC2_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_ADC2_IN10 (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN1) +#define GPIO_ADC2_IN13 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_ADC2_IN17 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) + +/* COMP - Comparator ********************************************************/ + +/* Comparator Outputs */ + +#define GPIO_COMP1_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN0) +#define GPIO_COMP1_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_COMP1_OUT_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_COMP1_OUT_4 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN8) + +#define GPIO_COMP2_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN2) +#define GPIO_COMP2_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_COMP2_OUT_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN12) + +#define GPIO_COMP3_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN7) + +#define GPIO_COMP4_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN6) + +/* Comparator Inputs non inverting */ + +#define GPIO_COMP1_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_COMP1_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) + +#define GPIO_COMP2_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_COMP2_INP_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) + +/* Comparator Inputs non inverting */ + +#define GPIO_COMP1_INM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_COMP1_INM_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) + +#define GPIO_COMP2_INM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_COMP2_INM_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) + +/* DAC **********************************************************************/ + +#define GPIO_DAC1_OUT1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_DAC1_OUT2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) + +/* Clocks outputs ***********************************************************/ + +/* MCU clock output */ + +#define GPIO_MCO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_MCO_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTG | GPIO_PIN10) + +/* Event outputs ************************************************************/ + +#define GPIO_PA0_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN0) +#define GPIO_PA1_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_PA2_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN2) +#define GPIO_PA3_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_PA4_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_PA5_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN5) +#define GPIO_PA6_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_PA7_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_PA8_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_PA9_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_PA10_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_PA11_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_PA12_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_PA13_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN13) +#define GPIO_PA14_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_PA15_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN15) + +#define GPIO_PB0_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_PB3_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_PB4_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_PB5_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_PB6_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_PB7_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_PB8_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN8) + +#define GPIO_PF0_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN0) +#define GPIO_PF1_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN1) + +#define GPIO_PG10_EVENTOUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN10) + +/* FDCAN ********************************************************************/ + +#define GPIO_FDCAN1_RX_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) +#define GPIO_FDCAN1_RX_2 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8) +#define GPIO_FDCAN1_TX_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12) + +#define GPIO_FDCAN2_RX_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN5) +#define GPIO_FDCAN2_TX_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) + +/* I2C **********************************************************************/ + +#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN13) +#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN15) +#define GPIO_I2C1_SCL_3 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN8) +#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN14) +#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN7) +#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN5) + +#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN9) +#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN8) +#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTF | GPIO_PIN0) +#define GPIO_I2C2_SMBA_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10) + +#define GPIO_I2C3_SCL (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN8) +#define GPIO_I2C3_SDA_1 (GPIO_ALT | GPIO_AF8 | GPIO_SPEED_50MHz | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN5) +#define GPIO_I2C3_SMBA_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9) + +/* I2S **********************************************************************/ + +#define GPIO_I2S_CKIN (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN12) + +#define GPIO_I2S2_CK (GPIO_ALT | GPIO_AF5 | GPIO_PORTF | GPIO_PIN1) +#define GPIO_I2S2_MCK (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_I2S2_SD (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_I2S2_WS (GPIO_ALT | GPIO_AF5 | GPIO_PORTF | GPIO_PIN0) + +#define GPIO_I2S3_CK (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_I2S3_MCK (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_I2S3_SD (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_I2S3_WS_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_I2S3_WS_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN15) + +/* IR - Infrared with TIM16 channel 1 and TIM17 channel 1 *******************/ + +#define GPIO_IR_OUT (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN13) + +/* LPTIM - Low Power Timer **************************************************/ + +#define GPIO_LPTIM1_ETR (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_LPTIM1_IN1 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_LPTIM1_IN2 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_LPTIM1_OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14) + +/* LPUART - Low-Power Universal Asynchronous Receiver Transmitter ***********/ + +#define GPIO_LPUART1_CTS (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_LPUART1_RX (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_LPUART1_TX (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN2) + +/* JTAG *********************************************************************/ + +#define GPIO_JTCK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_JTDI (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_JTDO (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_JTMS (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13) +#define GPIO_NJTRST (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13) + +/* OPAMP ********************************************************************/ + +#define GPIO_OPAMP1_VINM (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP1_VINP_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINP_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP1_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) + +#define GPIO_OPAMP2_VINM (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_OPAMP2_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP2_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) + +#define GPIO_OPAMP3_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP3_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) + +#define GPIO_OPAMP6_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) + +/* QUADSPI ******************************************************************/ + +#define GPIO_QUADSPI1_BK1_IO1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_QUADSPI1_BK1_IO2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_QUADSPI1_BK1_IO3 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_QUADSPI1_BK1_NCS_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN2) +#define GPIO_QUADSPI1_CLK_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN3) + +/* RTC **********************************************************************/ + +#define GPIO_RTC_REFIN (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN1) + +/* SAI - Serial Audio Interface *********************************************/ + +#define GPIO_SAI1_CK1_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_SAI1_CK1_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_SAI1_CK2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_SAI1_D1 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_SAI1_FS_A_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_SAI1_FS_B_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_SAI1_FS_B_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_SAI1_FS_B_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_SAI1_MCLK_B (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_SAI1_SCK_A_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_SAI1_SCK_B (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_SAI1_SD_A (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_SAI1_SD_B_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN13) +#define GPIO_SAI1_SD_B_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN5) + +/* SPI - Serial Peripheral Interface ****************************************/ + +#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN4) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN5) +#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN4) +#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN15) +#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN5) +#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN3) + +#define GPIO_SPI2_MISO (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN10) +#define GPIO_SPI2_MOSI (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN11) +#define GPIO_SPI2_NSS (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTF | GPIO_PIN0) +#define GPIO_SPI2_SCK (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PORTF | GPIO_PIN1) + +#define GPIO_SPI3_MISO (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN4) +#define GPIO_SPI3_MOSI (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN5) +#define GPIO_SPI3_NSS_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN4) +#define GPIO_SPI3_NSS_2 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN15) +#define GPIO_SPI3_SCK (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN3) + +/* TIM - Timers *************************************************************/ + +#define GPIO_TIM1_BKIN2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TIM1_BKIN_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM1_BKIN_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_TIM1_BKIN_3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_TIM1_BKIN_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TIM1_CH1IN_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN8) +#define GPIO_TIM1_CH1NIN_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM1_CH1NIN_2 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TIM1_CH1NOUT_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM1_CH1NOUT_2 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN8) +#define GPIO_TIM1_CH2IN_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM1_CH2NIN_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN12) +#define GPIO_TIM1_CH2NIN_2 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM1_CH2NOUT_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12) +#define GPIO_TIM1_CH2NOUT_2 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM1_CH3IN_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM1_CH3NIN_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN1) +#define GPIO_TIM1_CH3NOUT_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN1) +#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM1_CH4IN_1 (GPIO_ALT | GPIO_AF11 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT | GPIO_AF11 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TIM1_ETR_1 (GPIO_ALT | GPIO_AF11 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN12) + +#define GPIO_TIM2_CH1IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN0) +#define GPIO_TIM2_CH1IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN5) +#define GPIO_TIM2_CH1IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN15) +#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0) +#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN5) +#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN3) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN3) +#define GPIO_TIM2_CH3IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN2) +#define GPIO_TIM2_CH3IN_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM2_CH4IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN3) +#define GPIO_TIM2_CH4IN_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM2_ETR_1 (GPIO_ALT | GPIO_AF14 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN0) +#define GPIO_TIM2_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN5) +#define GPIO_TIM2_ETR_3 (GPIO_ALT | GPIO_AF14 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN15) + +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN4) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN4) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM3_CH3IN_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM3_CH4IN_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN7) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) +#define GPIO_TIM3_ETR_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN3) + +#define GPIO_TIM4_CH1IN_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TIM4_CH1IN_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN6) +#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) +#define GPIO_TIM4_CH2IN_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN12) +#define GPIO_TIM4_CH2IN_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN7) +#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12) +#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) +#define GPIO_TIM4_CH3IN_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN13) +#define GPIO_TIM4_CH3IN_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN13) +#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TIM4_ETR_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN8) +#define GPIO_TIM4_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN3) + +#define GPIO_TIM8_BKIN2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_TIM8_BKIN_1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN0) +#define GPIO_TIM8_BKIN_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM8_BKIN_3 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM8_BKIN_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_TIM8_CH1IN_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN15) +#define GPIO_TIM8_CH1IN_2 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN6) +#define GPIO_TIM8_CH1NIN_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM8_CH1NIN_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN3) +#define GPIO_TIM8_CH1NOUT_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM8_CH1NOUT_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN3) +#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15) +#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) +#define GPIO_TIM8_CH2IN_1 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN14) +#define GPIO_TIM8_CH2IN_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TIM8_CH2NIN_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM8_CH2NIN_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM8_CH2NOUT_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM8_CH2NOUT_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN14) +#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TIM8_CH3NIN_2 (GPIO_ALT | GPIO_AF3 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM8_CH3NOUT_2 (GPIO_ALT | GPIO_AF3 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM8_ETR_1 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN0) +#define GPIO_TIM8_ETR_2 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN6) + +#define GPIO_TIM15_BKIN_1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM15_CH1IN_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN2) +#define GPIO_TIM15_CH1NIN_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN1) +#define GPIO_TIM15_CH1NOUT_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN1) +#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2) +#define GPIO_TIM15_CH2IN_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN3) +#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3) + +#define GPIO_TIM16_BKIN_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM16_CH1IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM16_CH1IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN12) +#define GPIO_TIM16_CH1IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM16_CH1IN_4 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TIM16_CH1NIN_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN13) +#define GPIO_TIM16_CH1NIN_2 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN6) +#define GPIO_TIM16_CH1NOUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN13) +#define GPIO_TIM16_CH1NOUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) +#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12) +#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM16_CH1OUT_4 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8) + +#define GPIO_TIM17_BKIN_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM17_BKIN_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM17_CH1IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM17_CH1IN_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM17_CH1NIN_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN7) +#define GPIO_TIM17_CH1NOUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) +#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_50MHz | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN5) + +/* UARTs/USARTs *************************************************************/ + +#define GPIO_USART1_CK (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_USART1_CTS (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_USART1_DE (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_USART1_NSS (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_USART1_RTS (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN6) + +#define GPIO_USART2_CK_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_USART2_CK_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_USART2_CTS (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN0) +#define GPIO_USART2_DE (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_USART2_NSS (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN0) +#define GPIO_USART2_RTS (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_USART2_RX_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN2) +#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_USART2_TX_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN3) #endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXK_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h b/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h index 4391578bfe6..19029139dba 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h @@ -543,104 +543,50 @@ #define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) #define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13) -/* OPAMP ********************************************************************/ +/* OPAMP (Table 200 from Reference Manual) **********************************/ -#define GPIO_OPAMP1_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM0_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM1_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP1_VINP_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP1_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP1_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP1_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINM1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_OPAMP1_VINP0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP1_VINP1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINP2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) #define GPIO_OPAMP1_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) -#define GPIO_OPAMP2_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM0_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM1_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP2_VINP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP2_VINP_4 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN14) -#define GPIO_OPAMP2_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP2_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP2_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP2_VINP_SEC_4 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN14) +#define GPIO_OPAMP2_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_OPAMP2_VINM1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_OPAMP2_VINP0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP2_VINP1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) +#define GPIO_OPAMP2_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP2_VINP3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN14) #define GPIO_OPAMP2_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#define GPIO_OPAMP3_VINM0_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM1_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP3_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP3_VINP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP3_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP3_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP3_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP3_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) +#define GPIO_OPAMP3_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) +#define GPIO_OPAMP3_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP3_VINP1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP3_VINP2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_OPAMP3_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP4_VINM0_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM0_2 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) -#define GPIO_OPAMP4_VINM1_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM1_2 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) -#define GPIO_OPAMP4_VINM_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM_2 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) -#define GPIO_OPAMP4_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) -#define GPIO_OPAMP4_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP4_VINP_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP4_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP4_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) +#define GPIO_OPAMP4_VINM1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) + +#define GPIO_OPAMP4_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP4_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP4_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) #define GPIO_OPAMP4_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP5_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP5_VINP_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) -#define GPIO_OPAMP5_VINP_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN12) -#define GPIO_OPAMP5_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP5_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) -#define GPIO_OPAMP5_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN12) +#define GPIO_OPAMP5_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) +#define GPIO_OPAMP5_VINM1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP5_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP5_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP5_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) #define GPIO_OPAMP5_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) -#define GPIO_OPAMP6_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP6_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP6_VINP_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN9) -#define GPIO_OPAMP6_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP6_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP6_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN9) +#define GPIO_OPAMP6_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP6_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_OPAMP6_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) +#define GPIO_OPAMP6_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN9) +#define GPIO_OPAMP6_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) #define GPIO_OPAMP6_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) /* QUADSPI ******************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h b/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h index 5db5d634944..e1f7734af02 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h @@ -354,92 +354,50 @@ #define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) #define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13) -/* OPAMP ********************************************************************/ +/* OPAMP (Table 200 from Reference Manual) **********************************/ -#define GPIO_OPAMP1_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM0_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM1_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP1_VINP_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP1_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP1_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP1_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINM1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_OPAMP1_VINP0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP1_VINP1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINP2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) #define GPIO_OPAMP1_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) -#define GPIO_OPAMP2_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM0_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM1_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP2_VINP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP2_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP2_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP2_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) +#define GPIO_OPAMP2_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_OPAMP2_VINM1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_OPAMP2_VINP0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP2_VINP1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) +#define GPIO_OPAMP2_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP2_VINP3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN14) #define GPIO_OPAMP2_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#define GPIO_OPAMP3_VINM0_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM1_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP3_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP3_VINP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP3_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP3_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP3_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP3_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) +#define GPIO_OPAMP3_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) +#define GPIO_OPAMP3_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP3_VINP1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP3_VINP2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_OPAMP3_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP4_VINM (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) #define GPIO_OPAMP4_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM_SEC (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP4_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP4_VINM1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) + +#define GPIO_OPAMP4_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP4_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP4_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) #define GPIO_OPAMP4_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP5_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP5_VINP_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) -#define GPIO_OPAMP5_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP5_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) +#define GPIO_OPAMP5_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) +#define GPIO_OPAMP5_VINM1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP5_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP5_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP5_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) #define GPIO_OPAMP5_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) -#define GPIO_OPAMP6_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP6_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP6_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP6_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP6_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP6_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_OPAMP6_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) +#define GPIO_OPAMP6_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN9) +#define GPIO_OPAMP6_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) #define GPIO_OPAMP6_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) /* QUADSPI ******************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h b/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h index 8e961967df1..669221e5fe8 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h @@ -48,7 +48,7 @@ /* ADC - Analog Digital Converter *******************************************/ -#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) #define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) #define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) @@ -480,104 +480,50 @@ #define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) #define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13) -/* OPAMP ********************************************************************/ +/* OPAMP (Table 200 from Reference Manual) **********************************/ -#define GPIO_OPAMP1_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM0_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM1_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP1_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP1_VINP_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP1_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP1_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP1_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP1_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINM1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_OPAMP1_VINP0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP1_VINP1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP1_VINP2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) #define GPIO_OPAMP1_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) -#define GPIO_OPAMP2_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM0_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM1_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_OPAMP2_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -#define GPIO_OPAMP2_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP2_VINP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP2_VINP_4 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN14) -#define GPIO_OPAMP2_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_OPAMP2_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP2_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP2_VINP_SEC_4 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN14) +#define GPIO_OPAMP2_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_OPAMP2_VINM1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_OPAMP2_VINP0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_OPAMP2_VINP1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) +#define GPIO_OPAMP2_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP2_VINP3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN14) #define GPIO_OPAMP2_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#define GPIO_OPAMP3_VINM0_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM1_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) -#define GPIO_OPAMP3_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP3_VINP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP3_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP3_VINP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP3_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP3_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_OPAMP3_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP3_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) +#define GPIO_OPAMP3_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) +#define GPIO_OPAMP3_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_OPAMP3_VINP1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP3_VINP2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_OPAMP3_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP4_VINM0_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM0_2 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) -#define GPIO_OPAMP4_VINM1_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM1_2 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) -#define GPIO_OPAMP4_VINM_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM_2 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) -#define GPIO_OPAMP4_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) -#define GPIO_OPAMP4_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) -#define GPIO_OPAMP4_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP4_VINP_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) -#define GPIO_OPAMP4_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP4_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP4_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN10) +#define GPIO_OPAMP4_VINM1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN8) + +#define GPIO_OPAMP4_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP4_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP4_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) #define GPIO_OPAMP4_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP5_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_OPAMP5_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) -#define GPIO_OPAMP5_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP5_VINP_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) -#define GPIO_OPAMP5_VINP_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN12) -#define GPIO_OPAMP5_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN14) -#define GPIO_OPAMP5_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) -#define GPIO_OPAMP5_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN12) +#define GPIO_OPAMP5_VINM0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN15) +#define GPIO_OPAMP5_VINM1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_OPAMP5_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) +#define GPIO_OPAMP5_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN11) +#define GPIO_OPAMP5_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) #define GPIO_OPAMP5_VOUT (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) -#define GPIO_OPAMP6_VINM0_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM0_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM1_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_SEC_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_OPAMP6_VINM_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_OPAMP6_VINP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP6_VINP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP6_VINP_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN9) -#define GPIO_OPAMP6_VINP_SEC_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) -#define GPIO_OPAMP6_VINP_SEC_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) -#define GPIO_OPAMP6_VINP_SEC_3 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN9) +#define GPIO_OPAMP6_VINM0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_OPAMP6_VINM1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_OPAMP6_VINP0 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN12) +#define GPIO_OPAMP6_VINP1 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN9) +#define GPIO_OPAMP6_VINP2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN13) #define GPIO_OPAMP6_VOUT (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN11) /* QUADSPI ******************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h b/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h new file mode 100644 index 00000000000..51d37fe3f23 --- /dev/null +++ b/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h @@ -0,0 +1,167 @@ +/**************************************************************************** + * arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_COMP_H +#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_COMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +#define STM32_COMP1_CSR STM32_COMP1_BASE +#define STM32_COMP2_CSR STM32_COMP2_BASE +#define STM32_COMP3_CSR STM32_COMP3_BASE +#define STM32_COMP4_CSR STM32_COMP4_BASE +#define STM32_COMP5_CSR STM32_COMP5_BASE +#define STM32_COMP6_CSR STM32_COMP6_BASE +#define STM32_COMP7_CSR STM32_COMP7_BASE + +/* Register Bitfield Definitions ********************************************/ + +/* COMP control and status register */ + +#define COMP_CSR_COMPEN (1 << 0) /* Bit 0: Comparator enable */ + /* Bits 3-1: Reserved */ +#define COMP_CSR_INMSEL_SHIFT (4) /* Bits 7-4: Comparator inverting input selection */ +#define COMP_CSR_INMSEL_MASK (15 << COMP_CSR_INMSEL_SHIFT) +# define COMP_CSR_INMSEL_1P4VREF (0 << COMP_CSR_INMSEL_SHIFT) /* 0000: 1/4 of Vrefint */ +# define COMP_CSR_INMSEL_1P2VREF (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: 1/2 of Vrefint */ +# define COMP_CSR_INMSEL_3P4VREF (2 << COMP_CSR_INMSEL_SHIFT) /* 0010: 3/4 of Vrefint */ +# define COMP_CSR_INMSEL_VREF (3 << COMP_CSR_INMSEL_SHIFT) /* 0011: Vrefint */ +# define COMP_CSR_INMSEL_DAC3CH1 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC3_CH1 (COMP1 and COMP3 only) */ +# define COMP_CSR_INMSEL_DAC3CH2 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC3_CH2 (COMP2 and COMP4 only) */ +# define COMP_CSR_INMSEL_DAC4CH1 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC4_CH1 (COMP5 and COMP7 only) */ +# define COMP_CSR_INMSEL_DAC4CH2 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC4_CH2 (COMP6 only) */ +# define COMP_CSR_INMSEL_DAC1CH1 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC1_CH1 (COMP1, COMP3 and COMP4 only) */ +# define COMP_CSR_INMSEL_DAC1CH2 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC1_CH2 (COMP2 and COMP5 only) */ +# define COMP_CSR_INMSEL_DAC2CH1 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC2_CH1 (COMP6 and COMP7 only) */ +# define COMP_CSR_INMSEL_PA4 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PA4 (COMP1 only) */ +# define COMP_CSR_INMSEL_PA5 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PA5 (COMP2 only) */ +# define COMP_CSR_INMSEL_PF1 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PF1 (COMP3 only) */ +# define COMP_CSR_INMSEL_PE8 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PE8 (COMP4 only) */ +# define COMP_CSR_INMSEL_PB10 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PB10 (COMP5 only) */ +# define COMP_CSR_INMSEL_PD10 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PD10 (COMP6 only) */ +# define COMP_CSR_INMSEL_PD15 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PD15 (COMP7 only) */ +# define COMP_CSR_INMSEL_PA0 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PA0 (COMP1 only) */ +# define COMP_CSR_INMSEL_PA2 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PA2 (COMP2 only) */ +# define COMP_CSR_INMSEL_PC0 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PC0 (COMP3 only) */ +# define COMP_CSR_INMSEL_PB2 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */ +# define COMP_CSR_INMSEL_PD13 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PD13 (COMP5 only) */ +# define COMP_CSR_INMSEL_PB15 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB15 (COMP6 only) */ +# define COMP_CSR_INMSEL_PB12 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB12 (COMP7 only) */ + +#define COMP_CSR_INPSEL_SHIFT (8) /* Bit 8: Comparator non-inverting input selection */ +# define COMP_CSR_INPSEL_PA1 (0 << COMP_CSR_INPSEL_SHIFT) /* PA1 (COMP1 only) */ +# define COMP_CSR_INPSEL_PB1 (1 << COMP_CSR_INPSEL_SHIFT) /* PB1 (COMP1 only) */ +# define COMP_CSR_INPSEL_PA7 (0 << COMP_CSR_INPSEL_SHIFT) /* PA7 (COMP2 only) */ +# define COMP_CSR_INPSEL_PA3 (1 << COMP_CSR_INPSEL_SHIFT) /* PA3 (COMP2 only) */ +# define COMP_CSR_INPSEL_PA0 (0 << COMP_CSR_INPSEL_SHIFT) /* PA0 (COMP3 only) */ +# define COMP_CSR_INPSEL_PC1 (1 << COMP_CSR_INPSEL_SHIFT) /* PC1 (COMP3 only) */ +# define COMP_CSR_INPSEL_PB0 (0 << COMP_CSR_INPSEL_SHIFT) /* PB0 (COMP4 only) */ +# define COMP_CSR_INPSEL_PE7 (1 << COMP_CSR_INPSEL_SHIFT) /* PE7 (COMP4 only) */ +# define COMP_CSR_INPSEL_PB13 (0 << COMP_CSR_INPSEL_SHIFT) /* PB13 (COMP5 only) */ +# define COMP_CSR_INPSEL_PD12 (1 << COMP_CSR_INPSEL_SHIFT) /* PD12 (COMP5 only) */ +# define COMP_CSR_INPSEL_PB11 (0 << COMP_CSR_INPSEL_SHIFT) /* PB11 (COMP6 only) */ +# define COMP_CSR_INPSEL_PD11 (1 << COMP_CSR_INPSEL_SHIFT) /* PD11 (COMP6 only) */ +# define COMP_CSR_INPSEL_PB14 (0 << COMP_CSR_INPSEL_SHIFT) /* PB14 (COMP7 only) */ +# define COMP_CSR_INPSEL_PD14 (1 << COMP_CSR_INPSEL_SHIFT) /* PD14 (COMP7 only) */ + /* Bits 14-9: Reserved */ +#define COMP_CSR_POL (1 << 15) /* Bit 15: comparator output polarity */ + +#define COMP_CSR_HYST_SHIFT (16) /* Bits 18-16: Comparator hysteresis */ +#define COMP_CSR_HYST_MASK (7 << COMP_CSR_HYST_SHIFT) +# define COMP_CSR_HYST_0MV (0 << COMP_CSR_HYST_SHIFT) /* No hysteresis */ +# define COMP_CSR_HYST_10MV (1 << COMP_CSR_HYST_SHIFT) /* 10mV hysteresis */ +# define COMP_CSR_HYST_20MV (2 << COMP_CSR_HYST_SHIFT) /* 20mV hysteresis */ +# define COMP_CSR_HYST_30MV (3 << COMP_CSR_HYST_SHIFT) /* 30mV hysteresis */ +# define COMP_CSR_HYST_40MV (4 << COMP_CSR_HYST_SHIFT) /* 40mV hysteresis */ +# define COMP_CSR_HYST_50MV (5 << COMP_CSR_HYST_SHIFT) /* 50mV hysteresis */ +# define COMP_CSR_HYST_60MV (6 << COMP_CSR_HYST_SHIFT) /* 60mV hysteresis */ +# define COMP_CSR_HYST_70MV (7 << COMP_CSR_HYST_SHIFT) /* 70mV hysteresis */ + +#define COMP_CSR_BLANKING_SHIFT (19) /* Bit 21-19: Comparator blanking signal select */ +#define COMP_CSR_BLANKING_MASK (7 << COMP_CSR_BLANKING_SHIFT) +# define COMP_CSR_BLANKING_DIS (0 << COMP_CSR_BLANKING_SHIFT) /* 000: No blanking */ +# define COMP1_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1_OC5 */ +# define COMP2_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1_OC5 */ +# define COMP3_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1_OC5 */ +# define COMP4_CSR_BLANKING_T3OC4 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM3_OC4 */ +# define COMP5_CSR_BLANKING_T2OC3 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM2_OC3 */ +# define COMP6_CSR_BLANKING_T8OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM8_OC5 */ +# define COMP7_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1_OC5 */ +# define COMP1_CSR_BLANKING_T2OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2_OC3 */ +# define COMP2_CSR_BLANKING_T2OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2_OC3 */ +# define COMP3_CSR_BLANKING_T3OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM3_OC3 */ +# define COMP4_CSR_BLANKING_T8OC5 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM8_OC5 */ +# define COMP5_CSR_BLANKING_T8OC5 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM8_OC5 */ +# define COMP6_CSR_BLANKING_T2OC4 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2_OC4 */ +# define COMP7_CSR_BLANKING_T8OC5 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM8_OC5 */ +# define COMP1_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3_OC3 */ +# define COMP2_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3_OC3 */ +# define COMP3_CSR_BLANKING_T2OC4 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM2_OC4 */ +# define COMP4_CSR_BLANKING_T15OC1 (3 << COMP_CSR_BLANKING_SHIFT) /* 011 or 110: TIM15_OC1 */ +# define COMP5_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3_OC3 */ +# define COMP6_CSR_BLANKING_T15OC2 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM15_OC2 */ +# define COMP7_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3_OC3 */ +# define COMP1_CSR_BLANKING_T8OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM8_OC5 */ +# define COMP2_CSR_BLANKING_T8OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM8_OC5 */ +# define COMP3_CSR_BLANKING_T8OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM8_OC5 */ +# define COMP4_CSR_BLANKING_T1OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM1_OC5 */ +# define COMP5_CSR_BLANKING_T1OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM1_OC5 */ +# define COMP6_CSR_BLANKING_T1OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM1_OC5 */ +# define COMP7_CSR_BLANKING_T15OC2 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM15_OC2 */ +# define COMP1_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP2_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP3_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP4_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP5_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP6_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP7_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP1_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP2_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP3_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP5_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP6_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP7_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP1_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP2_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP3_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP4_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP5_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP6_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP7_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ + +#define COMP_CSR_BRGEN (1 << 22) /* Bit 22: Scaler resistor bridge enable */ +#define COMP_CSR_SCALEN (1 << 23) /* Bit 22: scaler enable */ + /* Bits 29-24: Reserved */ +#define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status */ +#define COMP_CSR_LOCK (1 << 31) /* Bit 31: Register lock */ + +#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_COMP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h index bb3e0cea056..2ced9d421c1 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h +++ b/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h @@ -126,12 +126,6 @@ #define STM32_COMP6_BASE 0x40010214 /* 0x40010214-0x40010217: COMP6 */ #define STM32_COMP7_BASE 0x40010218 /* 0x40010218-0x400102ff: COMP7 */ #define STM32_OPAMP_BASE 0x40010300 /* 0x40010300-0x40010303: OPAMP */ -#define STM32_OPAMP1_BASE 0x40010300 /* 0x40010300-0x40010303: OPAMP1 */ -#define STM32_OPAMP2_BASE 0x40010304 /* 0x40010304-0x40010307: OPAMP2 */ -#define STM32_OPAMP3_BASE 0x40010308 /* 0x40010308-0x4001030b: OPAMP3 */ -#define STM32_OPAMP4_BASE 0x4001030c /* 0x4001030c-0x4001030f: OPAMP4 */ -#define STM32_OPAMP5_BASE 0x40010310 /* 0x40010310-0x40010313: OPAMP5 */ -#define STM32_OPAMP6_BASE 0x40010314 /* 0x40010314-0x400103ff: OPAMP6 */ #define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff: EXTI */ #define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: TIM1 */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h b/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h new file mode 100644 index 00000000000..408f59fbffb --- /dev/null +++ b/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_OPAMP_H +#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_OPAMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_OPAMP1_CSR_OFFSET 0x0000 /* OPAMP1 Control register */ +#define STM32_OPAMP2_CSR_OFFSET 0x0004 /* OPAMP2 Control register */ +#define STM32_OPAMP3_CSR_OFFSET 0x0008 /* OPAMP3 Control register */ +#define STM32_OPAMP4_CSR_OFFSET 0x000c /* OPAMP4 Control register */ +#define STM32_OPAMP5_CSR_OFFSET 0x0010 /* OPAMP5 Control register */ +#define STM32_OPAMP6_CSR_OFFSET 0x0014 /* OPAMP6 Control register */ +#define STM32_OPAMP1_TCMR_OFFSET 0x0018 /* OPAMP1 timer controlled mode register */ +#define STM32_OPAMP2_TCMR_OFFSET 0x001c /* OPAMP2 timer controlled mode register */ +#define STM32_OPAMP3_TCMR_OFFSET 0x0020 /* OPAMP3 timer controlled mode register */ +#define STM32_OPAMP4_TCMR_OFFSET 0x0024 /* OPAMP4 timer controlled mode register */ +#define STM32_OPAMP5_TCMR_OFFSET 0x0028 /* OPAMP5 timer controlled mode register */ +#define STM32_OPAMP6_TCMR_OFFSET 0x002c /* OPAMP6 timer controlled mode register */ + +/* Register Addresses *******************************************************/ + +#define STM32_OPAMP1_CSR (STM32_OPAMP_BASE+STM32_OPAMP1_CSR_OFFSET) +#define STM32_OPAMP2_CSR (STM32_OPAMP_BASE+STM32_OPAMP2_CSR_OFFSET) +#define STM32_OPAMP3_CSR (STM32_OPAMP_BASE+STM32_OPAMP3_CSR_OFFSET) +#define STM32_OPAMP4_CSR (STM32_OPAMP_BASE+STM32_OPAMP4_CSR_OFFSET) +#define STM32_OPAMP5_CSR (STM32_OPAMP_BASE+STM32_OPAMP5_CSR_OFFSET) +#define STM32_OPAMP6_CSR (STM32_OPAMP_BASE+STM32_OPAMP6_CSR_OFFSET) +#define STM32_OPAMP1_TCMR (STM32_OPAMP_BASE+STM32_OPAMP1_TCMR_OFFSET) +#define STM32_OPAMP2_TCMR (STM32_OPAMP_BASE+STM32_OPAMP2_TCMR_OFFSET) +#define STM32_OPAMP3_TCMR (STM32_OPAMP_BASE+STM32_OPAMP3_TCMR_OFFSET) +#define STM32_OPAMP4_TCMR (STM32_OPAMP_BASE+STM32_OPAMP4_TCMR_OFFSET) +#define STM32_OPAMP5_TCMR (STM32_OPAMP_BASE+STM32_OPAMP5_TCMR_OFFSET) +#define STM32_OPAMP6_TCMR (STM32_OPAMP_BASE+STM32_OPAMP6_TCMR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* OPAMP control and status register */ + +#define OPAMP_CSR_OPAMPEN (1 << 0) /* Bit 0: OPAMP enable */ +#define OPAMP_CSR_FORCE_VP (1 << 1) /* Bit 1: FORCE_VP */ +#define OPAMP_CSR_VPSEL_SHIFT (2) /* Bits 2-3: OPAMP non inverting input selection */ +#define OPAMP_CSR_VPSEL_MASK (3 << OPAMP_CSR_VPSEL_SHIFT) +# define OPAMP_CSR_VPSEL_VINP0 (0 << OPAMP_CSR_VPSEL_SHIFT) +# define OPAMP_CSR_VPSEL_VINP1 (1 << OPAMP_CSR_VPSEL_SHIFT) +# define OPAMP_CSR_VPSEL_VINP2 (2 << OPAMP_CSR_VPSEL_SHIFT) +# define OPAMP_CSR_VPSEL_VINP3 (3 << OPAMP_CSR_VPSEL_SHIFT) /* Only for OPAMP2 */ +# define OPAMP_CSR_VPSEL_DAC3CH1 (3 << OPAMP_CSR_VPSEL_SHIFT) /* Only for OPAMP1 and OPAMP6 */ +# define OPAMP_CSR_VPSEL_DAC3CH2 (3 << OPAMP_CSR_VPSEL_SHIFT) /* Only for OPAMP3 */ +# define OPAMP_CSR_VPSEL_DAC4CH1 (3 << OPAMP_CSR_VPSEL_SHIFT) /* Only for OPAMP4 */ +# define OPAMP_CSR_VPSEL_DAC4CH2 (3 << OPAMP_CSR_VPSEL_SHIFT) /* Only for OPAMP5 */ +#define OPAMP_CSR_USERTRIM (1 << 4) /* Bit 4: User trimming enable */ +#define OPAMP_CSR_VMSEL_SHIFT (5) /* Bits 5-6: OPAMP inverting input selection */ +#define OPAMP_CSR_VMSEL_MASK (3 << OPAMP_CSR_VMSEL_SHIFT) +# define OPAMP_CSR_VMSEL_VINM0 (0 << OPAMP_CSR_VMSEL_SHIFT) +# define OPAMP_CSR_VMSEL_VINM1 (1 << OPAMP_CSR_VMSEL_SHIFT) +# define OPAMP_CSR_VMSEL_PGA (2 << OPAMP_CSR_VMSEL_SHIFT) +# define OPAMP_CSR_VMSEL_FOLLOWER (3 << OPAMP_CSR_VMSEL_SHIFT) +#define OPAMP_CSR_OPAHSM (1 << 7) /* Bit 7: OPAMP high-speed mode */ + +#define OPAMP_CSR_OPAINTOEN (1 << 8) /* Bit 8: OPAMP internal output enable */ + /* Bits 9-10: Reserved */ +#define OPAMP_CSR_CALON (1 << 11) /* Bit 11: Calibration mode enable */ +#define OPAMP_CSR_CALSEL_SHIFT (12) /* Bits 12-13: Calibration selection */ +#define OPAMP_CSR_CALSEL_MASK (3 << OPAMP_CSR_CALSEL_SHIFT) +# define OPAMP_CSR_CALSEL_3P3 (0 << OPAMP_CSR_CALSEL_SHIFT) /* 00 V_REFOPAMP = 3.3% V_DDA */ +# define OPAMP_CSR_CALSEL_10 (1 << OPAMP_CSR_CALSEL_SHIFT) /* 01 V_REFOPAMP = 10% V_DDA */ +# define OPAMP_CSR_CALSEL_50 (2 << OPAMP_CSR_CALSEL_SHIFT) /* 10 V_REFOPAMP = 50% V_DDA */ +# define OPAMP_CSR_CALSEL_90 (3 << OPAMP_CSR_CALSEL_SHIFT) /* 11 V_REFOPAMP = 90% V_DDA */ +#define OPAMP_CSR_PGAGAIN_SHIFT (14) /* Bits 14-18: Gain in PGA mode */ +#define OPAMP_CSR_PGAGAIN_MASK (31 << OPAMP_CSR_PGAGAIN_SHIFT) +#define OPAMP_CSR_TRIMOFFSETP_SHIFT (19) /* Bits 19-23: Offset trimming value (PMOS)*/ +#define OPAMP_CSR_TRIMOFFSETP_MASK (31 << OPAMP_CSR_TRIMOFFSETP_SHIFT) +#define OPAMP_CSR_TRIMOFFSETN_SHIFT (24) /* Bits 24-28: Offset trimming value (NMOS) */ +#define OPAMP_CSR_TRIMOFFSETN_MASK (31 << OPAMP_CSR_TRIMOFFSETN_SHIFT) + /* Bit 29: Reserved */ +#define OPAMP_CSR_OUTCAL (1 << 30) /* Bit 30: OPAMP output status flag */ +#define OPAMP_CSR_LOCK (1 << 31) /* Bit 31: OPAMP lock */ + +/* OPAMP timer controlled mode register */ + +#define OPAMP_TCMR_VMSSEL (1 << 0) /* Bit 0: OPAMP inverting input secondary selection */ +#define OPAMP_TCMR_VPSEL_SHIFT (1 << 1) /* Bits 1-2: OPAMP non inverting input secondary selection */ +#define OPAMP_TCMR_VPSEL_MASK (3 << OPAMP_TCMR_VPSEL_SHIFT) +# define OPAMP_TCMR_VPSEL_VINP0 (0 << OPAMP_TCMR_VPSEL_SHIFT) +# define OPAMP_TCMR_VPSEL_VINP1 (1 << OPAMP_TCMR_VPSEL_SHIFT) +# define OPAMP_TCMR_VPSEL_VINP2 (2 << OPAMP_TCMR_VPSEL_SHIFT) +# define OPAMP_TCMR_VPSEL_VINP3 (3 << OPAMP_TCMR_VPSEL_SHIFT) /* Only for OPAMP2 */ +# define OPAMP_TCMR_VPSEL_DAC3CH1 (3 << OPAMP_TCMR_VPSEL_SHIFT) /* Only for OPAMP1 and OPAMP6 */ +# define OPAMP_TCMR_VPSEL_DAC3CH2 (3 << OPAMP_TCMR_VPSEL_SHIFT) /* Only for OPAMP3 */ +# define OPAMP_TCMR_VPSEL_DAC4CH1 (3 << OPAMP_TCMR_VPSEL_SHIFT) /* Only for OPAMP4 */ +# define OPAMP_TCMR_VPSEL_DAC4CH2 (3 << OPAMP_TCMR_VPSEL_SHIFT) /* Only for OPAMP5 */ +#define OPAMP_TCMR_T1CMEN (1 << 2) /* Bit 2: TIM1 controlled mux mode enable */ +#define OPAMP_TCMR_T8CMEN (1 << 3) /* Bit 3: TIM8 controlled mux mode enable */ +#define OPAMP_TCMR_T20CMEN (1 << 4) /* Bit 4: TIM20 controlled mux mode enable */ + /* Bits 6-30: Reserved */ +#define OPAMP_TCMR_LOCK (1 << 31) /* Bit 31: OPAMP_TCMR lock */ + +#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c index 3c34fbae92e..297eb05ca9c 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/stm32/stm32_1wire.c @@ -48,6 +48,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 4bb544ea950..0c176885933 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -101,7 +101,7 @@ /* Supported ADC modes: * - SW triggering with/without DMA transfer - * - TIM triggering with/without DMA tranfer + * - TIM triggering with/without DMA transfer * - external triggering with/without DMA transfer * * (tested with ADC example app from NuttX apps repo). @@ -403,8 +403,8 @@ #ifdef HAVE_ADC_CMN_DATA struct adccmn_data_s { - uint8_t initialized; /* How many ADC instances are currently in use */ - sem_t lock; /* Exclusive access to common ADC data */ + uint8_t refcount; /* How many ADC instances are currently in use */ + sem_t lock; /* Exclusive access to common ADC data */ }; #endif @@ -726,7 +726,7 @@ static const struct stm32_adc_ops_s g_adc_llops = struct adccmn_data_s g_adc123_cmn = { - .initialized = 0 + .refcount = 0 }; # elif defined(HAVE_IP_ADC_V2) @@ -740,7 +740,7 @@ struct adccmn_data_s g_adc123_cmn = struct adccmn_data_s g_adc12_cmn = { - .initialized = 0 + .refcount = 0 }; # endif @@ -750,7 +750,7 @@ struct adccmn_data_s g_adc12_cmn = struct adccmn_data_s g_adc34_cmn = { - .initialized = 0 + .refcount = 0 }; # endif @@ -2863,7 +2863,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) goto out; } - if (priv->cmn->initialized == 0) + if (priv->cmn->refcount == 0) #endif { /* Enable ADC reset state */ @@ -2994,7 +2994,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) return ret; } - if (priv->cmn->initialized == 0) + if (priv->cmn->refcount == 0) #endif { /* Enable the ADC interrupt */ @@ -3006,7 +3006,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) } #ifdef HAVE_ADC_CMN_DATA - priv->cmn->initialized += 1; + priv->cmn->refcount += 1; adccmn_lock(priv, false); #endif @@ -3062,7 +3062,7 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) return; } - if (priv->cmn->initialized <= 1) + if (priv->cmn->refcount <= 1) #endif { #ifndef CONFIG_STM32_ADC_NOIRQ @@ -3096,9 +3096,9 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) #ifdef HAVE_ADC_CMN_DATA /* Decrease instances counter */ - if (priv->cmn->initialized > 0) + if (priv->cmn->refcount > 0) { - priv->cmn->initialized -= 1; + priv->cmn->refcount -= 1; } adccmn_lock(priv, false); diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c index 5c8c7be4ae6..c8306be7f17 100644 --- a/arch/arm/src/stm32/stm32_bbsram.c +++ b/arch/arm/src/stm32/stm32_bbsram.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c index 0d481973ff1..2547bf33a67 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/stm32/stm32_can.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c index 3ff5419230a..dae27aa63ec 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/stm32/stm32_capture.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -963,9 +964,9 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, /* Shift all CCER bits to corresponding channel */ mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - mask <<= (channel << 2); - regval <<= (channel << 2); - ccer_en_bit <<= (channel << 2); + mask <<= GTIM_CCER_CCXBASE(channel); + regval <<= GTIM_CCER_CCXBASE(channel); + ccer_en_bit <<= GTIM_CCER_CCXBASE(channel); stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval); diff --git a/arch/arm/src/stm32/stm32_ccm.c b/arch/arm/src/stm32/stm32_ccm.c index 1da8f3fbce4..60a8baaa57b 100644 --- a/arch/arm/src/stm32/stm32_ccm.c +++ b/arch/arm/src/stm32/stm32_ccm.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_ccm.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Based on a prototype by Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_ccm.h b/arch/arm/src/stm32/stm32_ccm.h index a9b24de8a89..d16d020273c 100644 --- a/arch/arm/src/stm32/stm32_ccm.h +++ b/arch/arm/src/stm32/stm32_ccm.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_ccm.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Based on a prototype by Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c index 6b379ae1fe8..6988630f37e 100644 --- a/arch/arm/src/stm32/stm32_comp.c +++ b/arch/arm/src/stm32/stm32_comp.c @@ -33,1046 +33,26 @@ #include #include +#include "arm_arch.h" #include "chip.h" -#include "stm32_gpio.h" #include "stm32_comp.h" +#include "stm32_gpio.h" -/* Some COMP peripheral must be enabled */ +/* This file is only a thin shell that includes the correct COMP + * implementation. At this moment STM32 COMP IP versions 1 and 2 are + * supported. + * - STM32 COMP IP version 1: SMT32F33XX + * - STM32 COMP IP version 2: SMT32G4XXX + */ -/* Up to 7 comparators in STM32F3 Series */ - -#if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) || defined(CONFIG_STM32_COMP4) || \ - defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ - defined(CONFIG_STM32_COMP7) - -#ifndef CONFIG_STM32_SYSCFG -# error "SYSCFG clock enable must be set" -#endif - -/* @TODO: support for STM32F30XX and STM32F37XX comparators */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) - -/* Currently only STM32F33XX supported */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -# error "Not supported yet" -#endif - -#if defined(CONFIG_STM32_STM32F33XX) -# if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP7) -# error "STM32F33 supports only COMP2, COMP4 and COMP6" -# endif -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* COMP2 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP2 -# ifndef COMP2_BLANLKING -# define COMP2_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP2_POL -# define COMP2_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP2_INM -# define COMP2_INM COMP_INM_DEFAULT -# endif -# ifndef COMP2_OUTSEL -# define COMP2_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP2_LOCK -# define COMP2_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP2_INM -# warning "GPIO_COMP2_INM not selected. Set default value to GPIO_COMP2_INM1" -# define GPIO_COMP2_INM GPIO_COMP4_INM_1 -# endif -#endif - -/* COMP4 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP4 -# ifndef COMP4_BLANLKING -# define COMP4_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP4_POL -# define COMP4_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP4_INM -# define COMP4_INM COMP_INM_DEFAULT -# endif -# ifndef COMP4_OUTSEL -# define COMP4_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP4_LOCK -# define COMP4_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP4_INM -# warning "GPIO_COMP4_INM not selected. Set default value to GPIO_COMP4_INM1" -# define GPIO_COMP4_INM GPIO_COMP4_INM_1 -# endif -#endif - -/* COMP6 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP6 -# ifndef COMP6_BLANLKING -# define COMP6_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP6_POL -# define COMP6_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP6_INM -# define COMP6_INM COMP_INM_DEFAULT -# endif -# ifndef COMP6_OUTSEL -# define COMP6_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP6_LOCK -# define COMP6_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP6_INM -# warning "GPIO_COMP6_INM not selected. Set default value to GPIO_COMP6_INM1" -# define GPIO_COMP6_INM GPIO_COMP6_INM_1 -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the configuration of one COMP device */ - -struct stm32_comp_s -{ - uint8_t blanking; /* Blanking source */ - uint8_t pol; /* Output polarity */ - uint8_t inm; /* Inverting input selection */ - uint8_t out; /* Comparator output */ - uint8_t lock; /* Comparator Lock */ - uint32_t csr; /* Control and status register */ -#ifndef CONFIG_STM32_STM32F33XX - uint8_t mode; /* Comparator mode */ - uint8_t hyst; /* Comparator hysteresis */ - /* @TODO: Window mode + INP selection */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* COMP Register access */ - -static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, - uint32_t clearbits, uint32_t setbits); -static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv); -static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, - uint32_t value); -static bool stm32_complock_get(FAR struct stm32_comp_s *priv); -static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock); - -/* COMP Driver Methods */ - -static void comp_shutdown(FAR struct comp_dev_s *dev); -static int comp_setup(FAR struct comp_dev_s *dev); -static int comp_read(FAR struct comp_dev_s *dev); -static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, - unsigned long arg); - -/* Initialization */ - -static int stm32_compconfig(FAR struct stm32_comp_s *priv); -static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct comp_ops_s g_compops = -{ - .ao_shutdown = comp_shutdown, - .ao_setup = comp_setup, - .ao_read = comp_read, - .ao_ioctl = comp_ioctl, -}; - -#ifdef CONFIG_STM32_COMP1 -static struct stm32_comp_s g_comp1priv = -{ - .blanking = COMP1_BLANKING, - .pol = COMP1_POL, - .inm = COMP1_INM, - .out = COMP1_OUTSEL, - .lock = COMP1_LOCK, - .csr = STM32_COMP1_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP1_MODE, - .hyst = COMP1_HYST, -#endif -}; - -static struct comp_dev_s g_comp1dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp1priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP2 -static struct stm32_comp_s g_comp2priv = -{ - .blanking = COMP2_BLANKING, - .pol = COMP2_POL, - .inm = COMP2_INM, - .out = COMP2_OUTSEL, - .lock = COMP2_LOCK, - .csr = STM32_COMP2_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP2_MODE, - .hyst = COMP2_HYST, -#endif -}; - -static struct comp_dev_s g_comp2dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp2priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP3 -static struct stm32_comp_s g_comp3priv = -{ - .blanking = COMP3_BLANKING, - .pol = COMP3_POL, - .inm = COMP3_INM, - .out = COMP3_OUTSEL, - .lock = COMP3_LOCK, - .csr = STM32_COMP3_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP3_MODE, - .hyst = COMP3_HYST, -#endif -}; - -static struct comp_dev_s g_comp3dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp3priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP4 -static struct stm32_comp_s g_comp4priv = -{ - .blanking = COMP4_BLANKING, - .pol = COMP4_POL, - .inm = COMP4_INM, - .out = COMP4_OUTSEL, - .lock = COMP4_LOCK, - .csr = STM32_COMP4_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP4_MODE, - .hyst = COMP4_HYST, -#endif -}; - -static struct comp_dev_s g_comp4dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp4priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP5 -static struct stm32_comp_s g_comp5priv = -{ - .blanking = COMP5_BLANKING, - .pol = COMP5_POL, - .inm = COMP5_INM, - .out = COMP5_OUTSEL, - .lock = COMP5_LOCK, - .csr = STM32_COMP5_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP5_MODE, - .hyst = COMP5_HYST, -#endif -}; - -static struct comp_dev_s g_comp5dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp5priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP6 -static struct stm32_comp_s g_comp6priv = -{ - .blanking = COMP6_BLANKING, - .pol = COMP6_POL, - .inm = COMP6_INM, - .out = COMP6_OUTSEL, - .lock = COMP6_LOCK, - .csr = STM32_COMP6_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP6_MODE, - .hyst = COMP6_HYST, -#endif -}; - -static struct comp_dev_s g_comp6dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp6priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP7 -static struct stm32_comp_s g_comp7priv = -{ - .blanking = COMP7_BLANKING, - .pol = COMP7_POL, - .inm = COMP7_INM, - .out = COMP7_OUTSEL, - .lock = COMP7_LOCK, - .csr = STM32_COMP7_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP7_MODE, - .hyst = COMP7_HYST, -#endif -}; - -static struct comp_dev_s g_comp7dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp7priv, -}; +#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +# include "stm32_comp_v1.c" +#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +# include "stm32_comp_v2.c" +#else +# error "STM32 COMP IP version not supported." #endif /**************************************************************************** * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: comp_modify_csr - * - * Description: - * Modify the value of a 32-bit COMP CSR register (not atomic). - * - * Input Parameters: - * priv - A reference to the COMP structure - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, - uint32_t clearbits, uint32_t setbits) -{ - uint32_t csr = priv->csr; - - modifyreg32(csr, clearbits, setbits); -} - -/**************************************************************************** - * Name: comp_getreg_csr - * - * Description: - * Read the value of an COMP CSR register - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * The current contents of the COMP CSR register - * - ****************************************************************************/ - -static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv) -{ - uint32_t csr = priv->csr; - - return getreg32(csr); -} - -/**************************************************************************** - * Name: comp_putreg_csr - * - * Description: - * Write a value to an COMP register. - * - * Input Parameters: - * priv - A reference to the COMP structure - * value - The value to write to the COMP CSR register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, - uint32_t value) -{ - uint32_t csr = priv->csr; - - putreg32(value, csr); -} - -/**************************************************************************** - * Name: stm32_comp_complock_get - * - * Description: - * Get COMP lock bit state - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * True if COMP locked, false if not locked - * - ****************************************************************************/ - -static bool stm32_complock_get(FAR struct stm32_comp_s *priv) -{ - uint32_t regval; - - regval = comp_getreg_csr(priv); - - return (((regval & COMP_CSR_LOCK) == 0) ? false : true); -} - -/**************************************************************************** - * Name: stm32_complock - * - * Description: - * Lock comparator CSR register - * - * Input Parameters: - * priv - A reference to the COMP structure - * enable - lock flag - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock) -{ - bool current; - - current = stm32_complock_get(priv); - - if (current) - { - if (lock == false) - { - aerr("ERROR: COMP LOCK can be cleared only by a system reset\n"); - - return -EPERM; - } - } - else - { - if (lock == true) - { - comp_modify_csr(priv, 0, COMP_CSR_LOCK); - - priv->lock = COMP_LOCK_RO; - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_compconfig - * - * Description: - * Configure comparator and used I/Os - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - * REVISIT: Where to config comparator output pin ? - * - ****************************************************************************/ - -static int stm32_compconfig(FAR struct stm32_comp_s *priv) -{ - uint32_t regval = 0; - int index; - - /* Get comparator index */ - - switch (priv->csr) - { -#ifdef CONFIG_STM32_COMP1 - case STM32_COMP1_CSR: - index = 1; - break; -#endif - -#ifdef CONFIG_STM32_COMP2 - case STM32_COMP2_CSR: - index = 2; - break; -#endif - -#ifdef CONFIG_STM32_COMP3 - case STM32_COMP3_CSR: - index = 3; - break; -#endif - -#ifdef CONFIG_STM32_COMP4 - case STM32_COMP4_CSR: - index = 4; - break; -#endif - -#ifdef CONFIG_STM32_COMP5 - case STM32_COMP5_CSR: - index = 5; - break; -#endif - -#ifdef CONFIG_STM32_COMP6 - case STM32_COMP6_CSR: - index = 6; - break; -#endif - -#ifdef CONFIG_STM32_COMP7 - case STM32_COMP7_CSR: - index = 7; - break; -#endif - - default: - return -EINVAL; - } - - /* Configure non inverting input */ - - switch (index) - { -#ifdef CONFIG_STM32_COMP1 - case 1: - stm32_configgpio(GPIO_COMP1_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP2 - case 2: - stm32_configgpio(GPIO_COMP2_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP3 - case 3: - stm32_configgpio(GPIO_COMP3_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP4 - case 4: - stm32_configgpio(GPIO_COMP4_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP5 - case 5: - stm32_configgpio(GPIO_COMP5_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP6 - case 6: - stm32_configgpio(GPIO_COMP6_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP7 - case 7: - stm32_configgpio(GPIO_COMP7_INP); - break; -#endif - - default: - return -EINVAL; - } - - /* Set Comparator inverting input */ - - switch (priv->inm) - { - case COMP_INMSEL_1P4VREF: - regval |= COMP_CSR_INMSEL_1P4VREF; - break; - - case COMP_INMSEL_1P2VREF: - regval |= COMP_CSR_INMSEL_1P2VREF; - break; - - case COMP_INMSEL_3P4VREF: - regval |= COMP_CSR_INMSEL_3P4VREF; - break; - - case COMP_INMSEL_VREF: - regval |= COMP_CSR_INMSEL_VREF; - break; - - case COMP_INMSEL_DAC1CH1: - regval |= COMP_CSR_INMSEL_DAC1CH1; - break; - - case COMP_INMSEL_DAC1CH2: - regval |= COMP_CSR_INMSEL_DAC1CH2; - break; - - case COMP_INMSEL_PIN: - { - /* INMSEL PIN configuration dependent on COMP index */ - - switch (index) - { - /* TODO: Inverting input pin configuration for COMP1/3/5/7 */ - -#ifdef CONFIG_STM32_COMP2 - case 2: - { - /* COMP2_INM can be PA2 or PA4 */ - - stm32_configgpio(GPIO_COMP2_INM); - regval |= (GPIO_COMP2_INM == GPIO_COMP2_INM_1 ? - COMP_CSR_INMSEL_PA2 : COMP_CSR_INMSEL_PA4); - break; - } -#endif - -#ifdef CONFIG_STM32_COMP4 - case 4: - { - /* COMP4_INM can be PB2 or PA4 */ - - stm32_configgpio(GPIO_COMP4_INM); - regval |= (GPIO_COMP4_INM == GPIO_COMP4_INM_1 ? - COMP_CSR_INMSEL_PB2 : COMP_CSR_INMSEL_PA4); - break; - } -#endif - -#ifdef CONFIG_STM32_COMP6 - case 6: - { - /* COMP6_INM can be PB15 or PA4 */ - - stm32_configgpio(GPIO_COMP6_INM); - regval |= (GPIO_COMP6_INM == GPIO_COMP6_INM_1 ? - COMP_CSR_INMSEL_PB15 : COMP_CSR_INMSEL_PA4); - break; - } -#endif - - default : - return -EINVAL; - } - - break; - } - - default: - return -EINVAL; - } - - /* Set Comparator output selection */ - - switch (priv->out) - { - case COMP_OUTSEL_NOSEL: - regval |= COMP_CSR_OUTSEL_NOSEL; - break; - - case COMP_OUTSEL_BRKACTH: - regval |= COMP_CSR_OUTSEL_BRKACTH; - break; - - case COMP_OUTSEL_BRK2: - regval |= COMP_CSR_OUTSEL_BRK2; - break; - - case COMP_OUTSEL_T1OCC: - regval |= COMP_CSR_OUTSEL_T1OCC; - break; - - case COMP_OUTSEL_T3CAP3: - regval |= COMP_CSR_OUTSEL_T3CAP3; - break; - - case COMP_OUTSEL_T2CAP2: - regval |= COMP_CSR_OUTSEL_T2CAP2; - break; - - case COMP_OUTSEL_T1CAP1: - regval |= COMP_CSR_OUTSEL_T1CAP1; - break; - - case COMP_OUTSEL_T2CAP4: - regval |= COMP_CSR_OUTSEL_T2CAP4; - break; - - case COMP_OUTSEL_T15CAP2: - regval |= COMP_CSR_OUTSEL_T15CAP2; - break; - - case COMP_OUTSEL_T2OCC: - if (index == 2) - { - regval |= COMP2_CSR_OUTSEL_T2OCC; - } - else if (index == 6) - { - regval |= COMP6_CSR_OUTSEL_T2OCC; - } - - break; - - case COMP_OUTSEL_T16OCC: - regval |= COMP_CSR_OUTSEL_T16OCC; - break; - - case COMP_OUTSEL_T3CAP1: - regval |= COMP_CSR_OUTSEL_T3CAP1; - break; - - case COMP_OUTSEL_T15OCC: - regval |= COMP_CSR_OUTSEL_T15OCC; - break; - - case COMP_OUTSEL_T16CAP1: - regval |= COMP_CSR_OUTSEL_T16CAP1; - break; - - case COMP_OUTSEL_T3OCC: - regval |= COMP_CSR_OUTSEL_T3OCC; - break; - - default: - return -EINVAL; - } - - /* Set Comparator output polarity */ - - regval |= (priv->pol == COMP_POL_INVERTED ? COMP_CSR_POL : 0); - - /* Set Comparator output blanking source */ - - switch (priv->blanking) - { - case COMP_BLANKING_DIS: - regval |= COMP_CSR_BLANKING_DIS; - break; - - case COMP_BLANKING_T1OC5: - regval |= COMP_CSR_BLANKING_T1OC5; - break; - - case COMP_BLANKING_T3OC4: - regval |= COMP_CSR_BLANKING_T3OC4; - break; - - case COMP_BLANKING_T2OC3: - regval |= COMP_CSR_BLANKING_T2OC3; - break; - - case COMP_BLANKING_T15OC1: - regval |= COMP_CSR_BLANKING_T15OC1; - break; - - case COMP_BLANKING_T2OC4: - regval |= COMP_CSR_BLANKING_T2OC4; - break; - - case COMP_BLANKING_T15OC2: - regval |= COMP_CSR_BLANKING_T15OC1; - break; - - default: - return -EINVAL; - } - - /* Save CSR register */ - - comp_putreg_csr(priv, regval); - - /* Enable Comparator */ - - stm32_compenable(priv, true); - - /* Lock Comparator if needed */ - - if (priv->lock == COMP_LOCK_RO) - { - stm32_complock(priv, true); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_compenable - * - * Description: - * Enable/disable comparator - * - * Input Parameters: - * priv - A reference to the COMP structure - * enable - enable/disable flag - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable) -{ - bool lock; - - ainfo("enable: %d\n", enable ? 1 : 0); - - lock = stm32_complock_get(priv); - - if (lock) - { - aerr("ERROR: Comparator locked!\n"); - - return -EPERM; - } - else - { - if (enable) - { - /* Enable the COMP */ - - comp_modify_csr(priv, 0, COMP_CSR_COMPEN); - } - else - { - /* Disable the COMP */ - - comp_modify_csr(priv, COMP_CSR_COMPEN, 0); - } - } - - return OK; -} - -/**************************************************************************** - * Name: adc_setup - * - * Description: - * Configure the COMP. This method is called the first time that the COMP - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching COMP interrupts. - * Interrupts are all disabled upon return. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int comp_setup(FAR struct comp_dev_s *dev) -{ -#warning "Missing logic" - - return OK; -} - -/**************************************************************************** - * Name: comp_shutdown - * - * Description: - * Disable the COMP. This method is called when the COMP device is closed. - * This method reverses the operation the setup method. - * Works only if COMP device is not locked. - * - * Input Parameters: - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void comp_shutdown(FAR struct comp_dev_s *dev) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: comp_read - * - * Description: - * Get the COMP output state. - * - * Input Parameters: - * - * Returned Value: - * 0 if output is low (non-inverting input below inverting input), - * 1 if output is high (non inverting input above inverting input). - * - ****************************************************************************/ - -static int comp_read(FAR struct comp_dev_s *dev) -{ - FAR struct stm32_comp_s *priv; - uint32_t regval; - - priv = dev->ad_priv; - regval = comp_getreg_csr(priv); - - return (((regval & COMP_CSR_OUT) == 0) ? 0 : 1); -} - -/**************************************************************************** - * Name: comp_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, unsigned long arg) -{ -#warning "Missing logic" - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_compinitialize - * - * Description: - * Initialize the COMP. - * - * Input Parameters: - * intf - The COMP interface number. - * - * Returned Value: - * Valid COMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the COMP block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -FAR struct comp_dev_s *stm32_compinitialize(int intf) -{ - FAR struct comp_dev_s *dev; - FAR struct stm32_comp_s *comp; - int ret; - - switch (intf) - { -#ifdef CONFIG_STM32_COMP1 - case 1: - ainfo("COMP1 selected\n"); - dev = &g_comp1dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP2 - case 2: - ainfo("COMP2 selected\n"); - dev = &g_comp2dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP3 - case 3: - ainfo("COMP3 selected\n"); - dev = &g_comp3dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP4 - case 4: - ainfo("COMP4 selected\n"); - dev = &g_comp4dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP5 - case 5: - ainfo("COMP5 selected\n"); - dev = &g_comp5dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP6 - case 6: - ainfo("COMP6 selected\n"); - dev = &g_comp6dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP7 - case 7: - ainfo("COMP7 selected\n"); - dev = &g_comp7dev; - break; -#endif - - default: - aerr("ERROR: No COMP interface defined\n"); - return NULL; - } - - /* Configure selected comparator */ - - comp = dev->ad_priv; - - ret = stm32_compconfig(comp); - if (ret < 0) - { - aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); - return NULL; - } - - return dev; -} - -#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX || - * CONFIG_STM32_STM32F37XX - */ - -#endif /* CONFIG_STM32_COMP2 || CONFIG_STM32_COMP4 || - * CONFIG_STM32_COMP6 - */ + ****************************************************************************/ \ No newline at end of file diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h index 5bf7be8fd97..54732bfd516 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/stm32/stm32_comp.h @@ -29,136 +29,22 @@ #include "chip.h" -#ifdef CONFIG_STM32_COMP +#include "hardware/stm32_comp.h" -#if defined(CONFIG_STM32_STM32F30XX) -# error "COMP support for STM32F30XX not implemented yet" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_comp.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# error "COMP support for STM32F37XX not implemented yet" +#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +# include "stm32_comp_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +# include "stm32_comp_v2.h" #endif /**************************************************************************** * Pre-processor definitions ****************************************************************************/ -#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */ -#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */ -#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */ -#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */ -#define COMP_LOCK_DEFAULT COMP_LOCK_RW /* Do not lock CSR register */ - -#ifndef CONFIG_STM32_STM32F33XX -#define COMP_MODE_DEFAULT -#define COMP_HYST_DEFAULT -#define COMP_WINMODE_DEFAULT -#endif - /**************************************************************************** * Public Types ****************************************************************************/ -/* Blanking source */ - -enum stm32_comp_blanking_e -{ - COMP_BLANKING_DIS, -#if defined(CONFIG_STM32_STM32F33XX) - COMP_BLANKING_T1OC5, - COMP_BLANKING_T3OC4, - COMP_BLANKING_T2OC3, - COMP_BLANKING_T3OC3, - COMP_BLANKING_T15OC1, - COMP_BLANKING_T2OC4, - COMP_BLANKING_T15OC2, -#endif -}; - -/* Output polarisation */ - -enum stm32_comp_pol_e -{ - COMP_POL_NONINVERT, - COMP_POL_INVERTED -}; - -/* Inverting input */ - -enum stm32_comp_inm_e -{ - COMP_INMSEL_1P4VREF, - COMP_INMSEL_1P2VREF, - COMP_INMSEL_3P4VREF, - COMP_INMSEL_VREF, - COMP_INMSEL_DAC1CH1, - COMP_INMSEL_DAC1CH2, - COMP_INMSEL_PIN -}; - -/* Output selection */ - -enum stm32_comp_outsel_e -{ - COMP_OUTSEL_NOSEL, -#if defined(CONFIG_STM32_STM32F33XX) - COMP_OUTSEL_BRKACTH, - COMP_OUTSEL_BRK2, - COMP_OUTSEL_T1OCC, /* COMP2 only */ - COMP_OUTSEL_T3CAP3, /* COMP4 only */ - COMP_OUTSEL_T2CAP2, /* COMP6 only */ - COMP_OUTSEL_T1CAP1, /* COMP2 only */ - COMP_OUTSEL_T2CAP4, /* COMP2 only */ - COMP_OUTSEL_T15CAP2, /* COMP4 only */ - COMP_OUTSEL_T2OCC, /* COMP6 only */ - COMP_OUTSEL_T16OCC, /* COMP2 only */ - COMP_OUTSEL_T3CAP1, /* COMP2 only */ - COMP_OUTSEL_T15OCC, /* COMP4 only */ - COMP_OUTSEL_T16CAP1, /* COMP6 only */ - COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ -#endif -}; - -/* CSR register lock state */ - -enum stm32_comp_lock_e -{ - COMP_LOCK_RW, - COMP_LOCK_RO -}; - -#ifndef CONFIG_STM32_STM32F33XX - -/* Hysteresis */ - -enum stm32_comp_hyst_e -{ - COMP_HYST_DIS, - COMP_HYST_LOW, - COMP_HYST_MEDIUM, - COMP_HYST_HIGH -}; - -/* Power/Speed Modes */ - -enum stm32_comp_mode_e -{ - COMP_MODE_HIGHSPEED, - COMP_MODE_MEDIUMSPEED, - COMP_MODE_LOWPOWER, - COMP_MODE_ULTRALOWPOWER -}; - -/* Window mode */ - -enum stm32_comp_winmode_e -{ - COMP_WINMODE_DIS, - COMP_WINMODE_EN -}; - -#endif - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -198,5 +84,4 @@ FAR struct comp_dev_s *stm32_compinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM23_COMP */ #endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.c b/arch/arm/src/stm32/stm32_comp_v1.c new file mode 100644 index 00000000000..988c1f6b807 --- /dev/null +++ b/arch/arm/src/stm32/stm32_comp_v1.c @@ -0,0 +1,1063 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_comp_v1.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some COMP peripheral must be enabled */ + +/* Up to 7 comparators in STM32F3 Series */ + +#if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || defined(CONFIG_STM32_COMP4) || \ + defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ + defined(CONFIG_STM32_COMP7) + +#ifndef CONFIG_STM32_SYSCFG +# error "SYSCFG clock enable must be set" +#endif + +/* @TODO: support for STM32F30XX and STM32F37XX comparators */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) + +/* Currently only STM32F33XX supported */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# error "Not supported yet" +#endif + +#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP7) +# error "STM32F33 supports only COMP2, COMP4 and COMP6" +# endif +#endif + +/* COMP2 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP2 +# ifndef COMP2_BLANLKING +# define COMP2_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP2_POL +# define COMP2_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP2_INM +# define COMP2_INM COMP_INM_DEFAULT +# endif +# ifndef COMP2_OUTSEL +# define COMP2_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP2_LOCK +# define COMP2_LOCK COMP_LOCK_DEFAULT +# endif +# ifndef GPIO_COMP2_INM +# warning "GPIO_COMP2_INM not selected. Set default value to GPIO_COMP2_INM1" +# define GPIO_COMP2_INM GPIO_COMP2_INM_1 +# endif +#endif + +/* COMP4 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP4 +# ifndef COMP4_BLANLKING +# define COMP4_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP4_POL +# define COMP4_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP4_INM +# define COMP4_INM COMP_INM_DEFAULT +# endif +# ifndef COMP4_OUTSEL +# define COMP4_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP4_LOCK +# define COMP4_LOCK COMP_LOCK_DEFAULT +# endif +# ifndef GPIO_COMP4_INM +# warning "GPIO_COMP4_INM not selected. Set default value to GPIO_COMP4_INM1" +# define GPIO_COMP4_INM GPIO_COMP4_INM_1 +# endif +#endif + +/* COMP6 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP6 +# ifndef COMP6_BLANLKING +# define COMP6_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP6_POL +# define COMP6_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP6_INM +# define COMP6_INM COMP_INM_DEFAULT +# endif +# ifndef COMP6_OUTSEL +# define COMP6_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP6_LOCK +# define COMP6_LOCK COMP_LOCK_DEFAULT +# endif +# ifndef GPIO_COMP6_INM +# warning "GPIO_COMP6_INM not selected. Set default value to GPIO_COMP6_INM1" +# define GPIO_COMP6_INM GPIO_COMP6_INM_1 +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the configuration of one COMP device */ + +struct stm32_comp_s +{ + uint8_t blanking; /* Blanking source */ + uint8_t pol; /* Output polarity */ + uint8_t inm; /* Inverting input selection */ + uint8_t out; /* Comparator output */ + uint8_t lock; /* Comparator Lock */ + uint32_t csr; /* Control and status register */ +#ifndef CONFIG_STM32_STM32F33XX + uint8_t mode; /* Comparator mode */ + uint8_t hyst; /* Comparator hysteresis */ + /* @TODO: Window mode + INP selection */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* COMP Register access */ + +static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits); +static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv); +static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, + uint32_t value); +static bool stm32_complock_get(FAR struct stm32_comp_s *priv); +static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock); + +/* COMP Driver Methods */ + +static void comp_shutdown(FAR struct comp_dev_s *dev); +static int comp_setup(FAR struct comp_dev_s *dev); +static int comp_read(FAR struct comp_dev_s *dev); +static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, + unsigned long arg); + +/* Initialization */ + +static int stm32_compconfig(FAR struct stm32_comp_s *priv); +static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct comp_ops_s g_compops = +{ + .ao_shutdown = comp_shutdown, + .ao_setup = comp_setup, + .ao_read = comp_read, + .ao_ioctl = comp_ioctl, +}; + +#ifdef CONFIG_STM32_COMP1 +static struct stm32_comp_s g_comp1priv = +{ + .blanking = COMP1_BLANKING, + .pol = COMP1_POL, + .inm = COMP1_INM, + .out = COMP1_OUTSEL, + .lock = COMP1_LOCK, + .csr = STM32_COMP1_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP1_MODE, + .hyst = COMP1_HYST, +#endif +}; + +static struct comp_dev_s g_comp1dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp1priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP2 +static struct stm32_comp_s g_comp2priv = +{ + .blanking = COMP2_BLANKING, + .pol = COMP2_POL, + .inm = COMP2_INM, + .out = COMP2_OUTSEL, + .lock = COMP2_LOCK, + .csr = STM32_COMP2_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP2_MODE, + .hyst = COMP2_HYST, +#endif +}; + +static struct comp_dev_s g_comp2dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp2priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP3 +static struct stm32_comp_s g_comp3priv = +{ + .blanking = COMP3_BLANKING, + .pol = COMP3_POL, + .inm = COMP3_INM, + .out = COMP3_OUTSEL, + .lock = COMP3_LOCK, + .csr = STM32_COMP3_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP3_MODE, + .hyst = COMP3_HYST, +#endif +}; + +static struct comp_dev_s g_comp3dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp3priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP4 +static struct stm32_comp_s g_comp4priv = +{ + .blanking = COMP4_BLANKING, + .pol = COMP4_POL, + .inm = COMP4_INM, + .out = COMP4_OUTSEL, + .lock = COMP4_LOCK, + .csr = STM32_COMP4_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP4_MODE, + .hyst = COMP4_HYST, +#endif +}; + +static struct comp_dev_s g_comp4dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp4priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP5 +static struct stm32_comp_s g_comp5priv = +{ + .blanking = COMP5_BLANKING, + .pol = COMP5_POL, + .inm = COMP5_INM, + .out = COMP5_OUTSEL, + .lock = COMP5_LOCK, + .csr = STM32_COMP5_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP5_MODE, + .hyst = COMP5_HYST, +#endif +}; + +static struct comp_dev_s g_comp5dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp5priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP6 +static struct stm32_comp_s g_comp6priv = +{ + .blanking = COMP6_BLANKING, + .pol = COMP6_POL, + .inm = COMP6_INM, + .out = COMP6_OUTSEL, + .lock = COMP6_LOCK, + .csr = STM32_COMP6_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP6_MODE, + .hyst = COMP6_HYST, +#endif +}; + +static struct comp_dev_s g_comp6dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp6priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP7 +static struct stm32_comp_s g_comp7priv = +{ + .blanking = COMP7_BLANKING, + .pol = COMP7_POL, + .inm = COMP7_INM, + .out = COMP7_OUTSEL, + .lock = COMP7_LOCK, + .csr = STM32_COMP7_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP7_MODE, + .hyst = COMP7_HYST, +#endif +}; + +static struct comp_dev_s g_comp7dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp7priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: comp_modify_csr + * + * Description: + * Modify the value of a 32-bit COMP CSR register (not atomic). + * + * Input Parameters: + * priv - A reference to the COMP structure + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits) +{ + uint32_t csr = priv->csr; + + modifyreg32(csr, clearbits, setbits); +} + +/**************************************************************************** + * Name: comp_getreg_csr + * + * Description: + * Read the value of an COMP CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * The current contents of the COMP CSR register + * + ****************************************************************************/ + +static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv) +{ + uint32_t csr = priv->csr; + + return getreg32(csr); +} + +/**************************************************************************** + * Name: comp_putreg_csr + * + * Description: + * Write a value to an COMP register. + * + * Input Parameters: + * priv - A reference to the COMP structure + * value - The value to write to the COMP CSR register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, + uint32_t value) +{ + uint32_t csr = priv->csr; + + putreg32(value, csr); +} + +/**************************************************************************** + * Name: stm32_comp_complock_get + * + * Description: + * Get COMP lock bit state + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * True if COMP locked, false if not locked + * + ****************************************************************************/ + +static bool stm32_complock_get(FAR struct stm32_comp_s *priv) +{ + uint32_t regval; + + regval = comp_getreg_csr(priv); + + return (((regval & COMP_CSR_LOCK) == 0) ? false : true); +} + +/**************************************************************************** + * Name: stm32_complock + * + * Description: + * Lock comparator CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - lock flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock) +{ + bool current; + + current = stm32_complock_get(priv); + + if (current) + { + if (lock == false) + { + aerr("ERROR: COMP LOCK can be cleared only by a system reset\n"); + + return -EPERM; + } + } + else + { + if (lock == true) + { + comp_modify_csr(priv, 0, COMP_CSR_LOCK); + + priv->lock = COMP_LOCK_RO; + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_compconfig + * + * Description: + * Configure comparator and used I/Os + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + * REVISIT: Where to config comparator output pin ? + * + ****************************************************************************/ + +static int stm32_compconfig(FAR struct stm32_comp_s *priv) +{ + uint32_t regval = 0; + int index; + + /* Get comparator index */ + + switch (priv->csr) + { +#ifdef CONFIG_STM32_COMP1 + case STM32_COMP1_CSR: + index = 1; + break; +#endif + +#ifdef CONFIG_STM32_COMP2 + case STM32_COMP2_CSR: + index = 2; + break; +#endif + +#ifdef CONFIG_STM32_COMP3 + case STM32_COMP3_CSR: + index = 3; + break; +#endif + +#ifdef CONFIG_STM32_COMP4 + case STM32_COMP4_CSR: + index = 4; + break; +#endif + +#ifdef CONFIG_STM32_COMP5 + case STM32_COMP5_CSR: + index = 5; + break; +#endif + +#ifdef CONFIG_STM32_COMP6 + case STM32_COMP6_CSR: + index = 6; + break; +#endif + +#ifdef CONFIG_STM32_COMP7 + case STM32_COMP7_CSR: + index = 7; + break; +#endif + + default: + return -EINVAL; + } + + /* Configure non inverting input */ + + switch (index) + { +#ifdef CONFIG_STM32_COMP1 + case 1: + stm32_configgpio(GPIO_COMP1_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP2 + case 2: + stm32_configgpio(GPIO_COMP2_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP3 + case 3: + stm32_configgpio(GPIO_COMP3_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP4 + case 4: + stm32_configgpio(GPIO_COMP4_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP5 + case 5: + stm32_configgpio(GPIO_COMP5_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP6 + case 6: + stm32_configgpio(GPIO_COMP6_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP7 + case 7: + stm32_configgpio(GPIO_COMP7_INP); + break; +#endif + + default: + return -EINVAL; + } + + /* Set Comparator inverting input */ + + switch (priv->inm) + { + case COMP_INMSEL_1P4VREF: + regval |= COMP_CSR_INMSEL_1P4VREF; + break; + + case COMP_INMSEL_1P2VREF: + regval |= COMP_CSR_INMSEL_1P2VREF; + break; + + case COMP_INMSEL_3P4VREF: + regval |= COMP_CSR_INMSEL_3P4VREF; + break; + + case COMP_INMSEL_VREF: + regval |= COMP_CSR_INMSEL_VREF; + break; + + case COMP_INMSEL_DAC1CH1: + regval |= COMP_CSR_INMSEL_DAC1CH1; + break; + + case COMP_INMSEL_DAC1CH2: + regval |= COMP_CSR_INMSEL_DAC1CH2; + break; + + case COMP_INMSEL_PIN: + { + /* INMSEL PIN configuration dependent on COMP index */ + + switch (index) + { + /* TODO: Inverting input pin configuration for COMP1/3/5/7 */ + +#ifdef CONFIG_STM32_COMP2 + case 2: + { + /* COMP2_INM can be PA2 or PA4 */ + + stm32_configgpio(GPIO_COMP2_INM); + regval |= (GPIO_COMP2_INM == GPIO_COMP2_INM_1 ? + COMP_CSR_INMSEL_PA2 : COMP_CSR_INMSEL_PA4); + break; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + case 4: + { + /* COMP4_INM can be PB2 or PA4 */ + + stm32_configgpio(GPIO_COMP4_INM); + regval |= (GPIO_COMP4_INM == GPIO_COMP4_INM_1 ? + COMP_CSR_INMSEL_PB2 : COMP_CSR_INMSEL_PA4); + break; + } +#endif + +#ifdef CONFIG_STM32_COMP6 + case 6: + { + /* COMP6_INM can be PB15 or PA4 */ + + stm32_configgpio(GPIO_COMP6_INM); + regval |= (GPIO_COMP6_INM == GPIO_COMP6_INM_1 ? + COMP_CSR_INMSEL_PB15 : COMP_CSR_INMSEL_PA4); + break; + } +#endif + + default : + return -EINVAL; + } + + break; + } + + default: + return -EINVAL; + } + + /* Set Comparator output selection */ + + switch (priv->out) + { + case COMP_OUTSEL_NOSEL: + regval |= COMP_CSR_OUTSEL_NOSEL; + break; + + case COMP_OUTSEL_BRKACTH: + regval |= COMP_CSR_OUTSEL_BRKACTH; + break; + + case COMP_OUTSEL_BRK2: + regval |= COMP_CSR_OUTSEL_BRK2; + break; + + case COMP_OUTSEL_T1OCC: + regval |= COMP_CSR_OUTSEL_T1OCC; + break; + + case COMP_OUTSEL_T3CAP3: + regval |= COMP_CSR_OUTSEL_T3CAP3; + break; + + case COMP_OUTSEL_T2CAP2: + regval |= COMP_CSR_OUTSEL_T2CAP2; + break; + + case COMP_OUTSEL_T1CAP1: + regval |= COMP_CSR_OUTSEL_T1CAP1; + break; + + case COMP_OUTSEL_T2CAP4: + regval |= COMP_CSR_OUTSEL_T2CAP4; + break; + + case COMP_OUTSEL_T15CAP2: + regval |= COMP_CSR_OUTSEL_T15CAP2; + break; + + case COMP_OUTSEL_T2OCC: + if (index == 2) + { + regval |= COMP2_CSR_OUTSEL_T2OCC; + } + else if (index == 6) + { + regval |= COMP6_CSR_OUTSEL_T2OCC; + } + + break; + + case COMP_OUTSEL_T16OCC: + regval |= COMP_CSR_OUTSEL_T16OCC; + break; + + case COMP_OUTSEL_T3CAP1: + regval |= COMP_CSR_OUTSEL_T3CAP1; + break; + + case COMP_OUTSEL_T15OCC: + regval |= COMP_CSR_OUTSEL_T15OCC; + break; + + case COMP_OUTSEL_T16CAP1: + regval |= COMP_CSR_OUTSEL_T16CAP1; + break; + + case COMP_OUTSEL_T3OCC: + regval |= COMP_CSR_OUTSEL_T3OCC; + break; + + default: + return -EINVAL; + } + + /* Set Comparator output polarity */ + + regval |= (priv->pol == COMP_POL_INVERTED ? COMP_CSR_POL : 0); + + /* Set Comparator output blanking source */ + + switch (priv->blanking) + { + case COMP_BLANKING_DIS: + regval |= COMP_CSR_BLANKING_DIS; + break; + + case COMP_BLANKING_T1OC5: + regval |= COMP_CSR_BLANKING_T1OC5; + break; + + case COMP_BLANKING_T3OC4: + regval |= COMP_CSR_BLANKING_T3OC4; + break; + + case COMP_BLANKING_T2OC3: + regval |= COMP_CSR_BLANKING_T2OC3; + break; + + case COMP_BLANKING_T15OC1: + regval |= COMP_CSR_BLANKING_T15OC1; + break; + + case COMP_BLANKING_T2OC4: + regval |= COMP_CSR_BLANKING_T2OC4; + break; + + case COMP_BLANKING_T15OC2: + regval |= COMP_CSR_BLANKING_T15OC1; + break; + + default: + return -EINVAL; + } + + /* Save CSR register */ + + comp_putreg_csr(priv, regval); + + /* Enable Comparator */ + + stm32_compenable(priv, true); + + /* Lock Comparator if needed */ + + if (priv->lock == COMP_LOCK_RO) + { + stm32_complock(priv, true); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_compenable + * + * Description: + * Enable/disable comparator + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - enable/disable flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable) +{ + bool lock; + + ainfo("enable: %d\n", enable ? 1 : 0); + + lock = stm32_complock_get(priv); + + if (lock) + { + aerr("ERROR: Comparator locked!\n"); + + return -EPERM; + } + else + { + if (enable) + { + /* Enable the COMP */ + + comp_modify_csr(priv, 0, COMP_CSR_COMPEN); + } + else + { + /* Disable the COMP */ + + comp_modify_csr(priv, COMP_CSR_COMPEN, 0); + } + } + + return OK; +} + +/**************************************************************************** + * Name: adc_setup + * + * Description: + * Configure the COMP. This method is called the first time that the COMP + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching COMP interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int comp_setup(FAR struct comp_dev_s *dev) +{ +#warning "Missing logic" + + return OK; +} + +/**************************************************************************** + * Name: comp_shutdown + * + * Description: + * Disable the COMP. This method is called when the COMP device is closed. + * This method reverses the operation the setup method. + * Works only if COMP device is not locked. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void comp_shutdown(FAR struct comp_dev_s *dev) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: comp_read + * + * Description: + * Get the COMP output state. + * + * Input Parameters: + * + * Returned Value: + * 0 if output is low (non-inverting input below inverting input), + * 1 if output is high (non inverting input above inverting input). + * + ****************************************************************************/ + +static int comp_read(FAR struct comp_dev_s *dev) +{ + FAR struct stm32_comp_s *priv; + uint32_t regval; + + priv = dev->ad_priv; + regval = comp_getreg_csr(priv); + + return (((regval & COMP_CSR_OUT) == 0) ? 0 : 1); +} + +/**************************************************************************** + * Name: comp_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, unsigned long arg) +{ +#warning "Missing logic" + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +FAR struct comp_dev_s *stm32_compinitialize(int intf) +{ + FAR struct comp_dev_s *dev; + FAR struct stm32_comp_s *comp; + int ret; + + switch (intf) + { +#ifdef CONFIG_STM32_COMP1 + case 1: + ainfo("COMP1 selected\n"); + dev = &g_comp1dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP2 + case 2: + ainfo("COMP2 selected\n"); + dev = &g_comp2dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP3 + case 3: + ainfo("COMP3 selected\n"); + dev = &g_comp3dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP4 + case 4: + ainfo("COMP4 selected\n"); + dev = &g_comp4dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP5 + case 5: + ainfo("COMP5 selected\n"); + dev = &g_comp5dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP6 + case 6: + ainfo("COMP6 selected\n"); + dev = &g_comp6dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP7 + case 7: + ainfo("COMP7 selected\n"); + dev = &g_comp7dev; + break; +#endif + + default: + aerr("ERROR: No COMP interface defined\n"); + return NULL; + } + + /* Configure selected comparator */ + + comp = dev->ad_priv; + + ret = stm32_compconfig(comp); + if (ret < 0) + { + aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); + return NULL; + } + + return dev; +} + +#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX || + * CONFIG_STM32_STM32F37XX + */ + +#endif /* CONFIG_STM32_COMP2 || CONFIG_STM32_COMP4 || + * CONFIG_STM32_COMP6 + */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.h b/arch/arm/src/stm32/stm32_comp_v1.h new file mode 100644 index 00000000000..1239f97bd30 --- /dev/null +++ b/arch/arm/src/stm32/stm32_comp_v1.h @@ -0,0 +1,151 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_comp_v1.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H +#define __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifdef CONFIG_STM32_COMP + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */ +#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */ +#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */ +#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */ +#define COMP_LOCK_DEFAULT COMP_LOCK_RW /* Do not lock CSR register */ + +#ifndef CONFIG_STM32_STM32F33XX +#define COMP_MODE_DEFAULT +#define COMP_HYST_DEFAULT +#define COMP_WINMODE_DEFAULT +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Blanking source */ + +enum stm32_comp_blanking_e +{ + COMP_BLANKING_DIS, +#if defined(CONFIG_STM32_STM32F33XX) + COMP_BLANKING_T1OC5, + COMP_BLANKING_T3OC4, + COMP_BLANKING_T2OC3, + COMP_BLANKING_T3OC3, + COMP_BLANKING_T15OC1, + COMP_BLANKING_T2OC4, + COMP_BLANKING_T15OC2, +#endif +}; + +/* Output polarisation */ + +enum stm32_comp_pol_e +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; + +/* Inverting input */ + +enum stm32_comp_inm_e +{ + COMP_INMSEL_1P4VREF, + COMP_INMSEL_1P2VREF, + COMP_INMSEL_3P4VREF, + COMP_INMSEL_VREF, + COMP_INMSEL_DAC1CH1, + COMP_INMSEL_DAC1CH2, + COMP_INMSEL_PIN +}; + +/* Output selection */ + +enum stm32_comp_outsel_e +{ + COMP_OUTSEL_NOSEL, +#if defined(CONFIG_STM32_STM32F33XX) + COMP_OUTSEL_BRKACTH, + COMP_OUTSEL_BRK2, + COMP_OUTSEL_T1OCC, /* COMP2 only */ + COMP_OUTSEL_T3CAP3, /* COMP4 only */ + COMP_OUTSEL_T2CAP2, /* COMP6 only */ + COMP_OUTSEL_T1CAP1, /* COMP2 only */ + COMP_OUTSEL_T2CAP4, /* COMP2 only */ + COMP_OUTSEL_T15CAP2, /* COMP4 only */ + COMP_OUTSEL_T2OCC, /* COMP6 only */ + COMP_OUTSEL_T16OCC, /* COMP2 only */ + COMP_OUTSEL_T3CAP1, /* COMP2 only */ + COMP_OUTSEL_T15OCC, /* COMP4 only */ + COMP_OUTSEL_T16CAP1, /* COMP6 only */ + COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ +#endif +}; + +/* CSR register lock state */ + +enum stm32_comp_lock_e +{ + COMP_LOCK_RW, + COMP_LOCK_RO +}; + +#ifndef CONFIG_STM32_STM32F33XX + +/* Hysteresis */ + +enum stm32_comp_hyst_e +{ + COMP_HYST_DIS, + COMP_HYST_LOW, + COMP_HYST_MEDIUM, + COMP_HYST_HIGH +}; + +/* Power/Speed Modes */ + +enum stm32_comp_mode_e +{ + COMP_MODE_HIGHSPEED, + COMP_MODE_MEDIUMSPEED, + COMP_MODE_LOWPOWER, + COMP_MODE_ULTRALOWPOWER +}; + +/* Window mode */ + +enum stm32_comp_winmode_e +{ + COMP_WINMODE_DIS, + COMP_WINMODE_EN +}; + +#endif + +#endif /* CONFIG_STM23_COMP */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v2.c b/arch/arm/src/stm32/stm32_comp_v2.c new file mode 100644 index 00000000000..47a47eec3c1 --- /dev/null +++ b/arch/arm/src/stm32/stm32_comp_v2.c @@ -0,0 +1,1005 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_comp_v2.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some COMP peripheral must be enabled and the device must be supported */ + +#define DEVICE_NOT_SUPPORTED + +#if defined(CONFIG_STM32_COMP) + +#ifndef CONFIG_STM32_SYSCFG +# error "SYSCFG clock enable must be set" +#endif + +#if defined(CONFIG_STM32_STM32G43XX) +# undef DEVICE_NOT_SUPPORTED +# if defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ + defined(CONFIG_STM32_COMP7) +# error "STM32G43XX supports only COMP1, COMP2, COMP3 and COMP4" +# endif +#endif + +#if defined(DEVICE_NOT_SUPPORTED) +# error "Device not supported" +#endif + +#if defined(CONFIG_STM32_COMP1_OUT) || defined(CONFIG_STM32_COMP2_OUT) || \ + defined(CONFIG_STM32_COMP3_OUT) || defined(CONFIG_STM32_COMP4_OUT) || \ + defined(CONFIG_STM32_COMP5_OUT) || defined(CONFIG_STM32_COMP6_OUT) || \ + defined(CONFIG_STM32_COMP7_OUT) +# define COMP_OUT_GPIO +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the configuration of one COMP device */ + +struct stm32_comp_s +{ + uint8_t inm; /* Inverting input selection */ + uint32_t gpio_inm; /* Inverting input pin */ + uint8_t inp; /* Non inverting input selection */ + uint32_t gpio_inp; /* Non-inverting input pin */ + uint8_t pol; /* Output polarity */ + uint8_t hyst; /* Comparator hysteresis */ + uint8_t blanking; /* Blanking source */ + uint8_t lock; /* Comparator Lock */ + uint32_t csr; /* Control and status register */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* COMP Register access */ + +static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits); +static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv); +static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, + uint32_t value); + +/* COMP Driver Methods */ + +#if defined (CONFIG_COMP) +static void comp_shutdown(FAR struct comp_dev_s *dev); +static int comp_setup(FAR struct comp_dev_s *dev); +static int comp_read(FAR struct comp_dev_s *dev); +static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, + unsigned long arg); +#endif + +static int comp_config(FAR struct stm32_comp_s *priv); +static int comp_enable(FAR struct stm32_comp_s *priv, bool enable); +static bool comp_lock_get(FAR struct stm32_comp_s *priv); +static int comp_lock_set(FAR struct stm32_comp_s *priv, bool lock); + +static int comp_config_inmpin(FAR struct stm32_comp_s *priv); +static int comp_config_inppin(FAR struct stm32_comp_s *priv); +#if defined(COMP_OUT_GPIO) +static int comp_config_outpin(FAR struct stm32_comp_s *priv); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_COMP +static const struct comp_ops_s g_compops = +{ + .ao_shutdown = comp_shutdown, + .ao_setup = comp_setup, + .ao_read = comp_read, + .ao_ioctl = comp_ioctl, +}; +#endif + +#ifdef CONFIG_STM32_COMP1 +static struct stm32_comp_s g_comp1priv = +{ + .inm = CONFIG_STM32_COMP1_INM, + .inp = CONFIG_STM32_COMP1_INP, + .pol = CONFIG_STM32_COMP1_POL, + .hyst = CONFIG_STM32_COMP1_HYST, + .blanking = CONFIG_STM32_COMP1_BLANKSEL, + .lock = CONFIG_STM32_COMP1_LOCK, + .gpio_inp = GPIO_COMP1_INP, + .csr = STM32_COMP1_CSR +}; + +static struct comp_dev_s g_comp1dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp1priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP2 +static struct stm32_comp_s g_comp2priv = +{ + .inm = CONFIG_STM32_COMP2_INM, + .inp = CONFIG_STM32_COMP2_INP, + .pol = CONFIG_STM32_COMP2_POL, + .hyst = CONFIG_STM32_COMP2_HYST, + .blanking = CONFIG_STM32_COMP2_BLANKSEL, + .lock = CONFIG_STM32_COMP2_LOCK, + .gpio_inp = GPIO_COMP2_INP, + .csr = STM32_COMP2_CSR +}; + +static struct comp_dev_s g_comp2dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp2priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP3 +static struct stm32_comp_s g_comp3priv = +{ + .inm = CONFIG_STM32_COMP3_INM, + .inp = CONFIG_STM32_COMP3_INP, + .pol = CONFIG_STM32_COMP3_POL, + .hyst = CONFIG_STM32_COMP3_HYST, + .blanking = CONFIG_STM32_COMP3_BLANKSEL, + .lock = CONFIG_STM32_COMP3_LOCK, + .gpio_inp = GPIO_COMP3_INP, + .csr = STM32_COMP3_CSR +}; + +static struct comp_dev_s g_comp3dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp3priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP4 +static struct stm32_comp_s g_comp4priv = +{ + .inm = CONFIG_STM32_COMP4_INM, + .inp = CONFIG_STM32_COMP4_INP, + .pol = CONFIG_STM32_COMP4_POL, + .hyst = CONFIG_STM32_COMP4_HYST, + .blanking = CONFIG_STM32_COMP4_BLANKSEL, + .lock = CONFIG_STM32_COMP4_LOCK, + .gpio_inp = GPIO_COMP4_INP, + .csr = STM32_COMP4_CSR +}; + +static struct comp_dev_s g_comp4dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp4priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP5 +static struct stm32_comp_s g_comp5priv = +{ + .inm = CONFIG_STM32_COMP5_INM, + .inp = CONFIG_STM32_COMP5_INP, + .pol = CONFIG_STM32_COMP5_POL, + .hyst = CONFIG_STM32_COMP5_HYST, + .blanking = CONFIG_STM32_COMP5_BLANKSEL, + .lock = CONFIG_STM32_COMP5_LOCK, + .gpio_inp = GPIO_COMP5_INP, + .csr = STM32_COMP5_CSR +}; + +static struct comp_dev_s g_comp5dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp5priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP6 +static struct stm32_comp_s g_comp6priv = +{ + .inm = CONFIG_STM32_COMP6_INM, + .inp = CONFIG_STM32_COMP6_INP, + .pol = CONFIG_STM32_COMP6_POL, + .hyst = CONFIG_STM32_COMP6_HYST, + .blanking = CONFIG_STM32_COMP6_BLANKSEL, + .lock = CONFIG_STM32_COMP6_LOCK, + .gpio_inp = GPIO_COMP6_INP, + .csr = STM32_COMP6_CSR +}; + +static struct comp_dev_s g_comp6dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp6priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP7 +static struct stm32_comp_s g_comp7priv = +{ + .inm = CONFIG_STM32_COMP7_INM, + .inp = CONFIG_STM32_COMP7_INP, + .pol = CONFIG_STM32_COMP7_POL, + .hyst = CONFIG_STM32_COMP7_HYST, + .blanking = CONFIG_STM32_COMP7_BLANKSEL, + .lock = CONFIG_STM32_COMP7_LOCK, + .gpio_inp = GPIO_COMP7_INP, + .csr = STM32_COMP7_CSR +}; + +static struct comp_dev_s g_comp7dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp7priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: comp_modify_csr + * + * Description: + * Modify the value of a 32-bit COMP CSR register (not atomic). + * + * Input Parameters: + * priv - A reference to the COMP structure + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits) +{ + uint32_t csr = priv->csr; + + modifyreg32(csr, clearbits, setbits); +} + +/**************************************************************************** + * Name: comp_getreg_csr + * + * Description: + * Read the value of an COMP CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * The current contents of the COMP CSR register + * + ****************************************************************************/ + +static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv) +{ + uint32_t csr = priv->csr; + + return getreg32(csr); +} + +/**************************************************************************** + * Name: comp_putreg_csr + * + * Description: + * Write a value to an COMP register. + * + * Input Parameters: + * priv - A reference to the COMP structure + * value - The value to write to the COMP CSR register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, + uint32_t value) +{ + uint32_t csr = priv->csr; + + putreg32(value, csr); +} + +/**************************************************************************** + * Name: comp_lock_get + * + * Description: + * Get COMP lock bit state + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * True if COMP locked, false if not locked + * + ****************************************************************************/ + +static bool comp_lock_get(FAR struct stm32_comp_s *priv) +{ + uint32_t regval; + + regval = comp_getreg_csr(priv); + + return (((regval & COMP_CSR_LOCK) == 0) ? false : true); +} + +/**************************************************************************** + * Name: comp_lock_set + * + * Description: + * Lock comparator CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - lock flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_lock_set(FAR struct stm32_comp_s *priv, bool lock) +{ + if (comp_lock_get(priv)) + { + if (lock == false) + { + aerr("ERROR: COMP LOCK can be cleared only by a system reset\n"); + + return -EPERM; + } + } + else + { + if (lock == true) + { + comp_modify_csr(priv, 0, COMP_CSR_LOCK); + + priv->lock = 1; + } + } + + return OK; +} + +/**************************************************************************** + * Name: comp_config_inmpin + * + * Description: + * Configure comparator inverting input pin. The GPIO that COMPx inverting + * input will be assigned is dependent of comparator number and must be + * defined in board.h file. See table 196 in RM0440. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_config_inmpin(FAR struct stm32_comp_s *priv) +{ +# if defined(CONFIG_STM32_COMP1) + if (priv->csr == STM32_COMP1_CSR) + { + stm32_configgpio(GPIO_COMP1_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP2) + if (priv->csr == STM32_COMP2_CSR) + { + stm32_configgpio(GPIO_COMP2_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP3) + if (priv->csr == STM32_COMP3_CSR) + { + stm32_configgpio(GPIO_COMP3_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP4) + if (priv->csr == STM32_COMP4_CSR) + { + stm32_configgpio(GPIO_COMP4_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP5) + if (priv->csr == STM32_COMP5_CSR) + { + stm32_configgpio(GPIO_COMP5_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP6) + if (priv->csr == STM32_COMP6_CSR) + { + stm32_configgpio(GPIO_COMP6_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP7) + if (priv->csr == STM32_COMP7_CSR) + { + stm32_configgpio(GPIO_COMP7_INM); + } +# endif + + return OK; +} + +/**************************************************************************** + * Name: comp_config_inppin + * + * Description: + * Configure comparator non-inverting input pin. The IO pin that COMPx + * non-inverting input will be assigned is dependent of comparator number + * and must be defined in board.h file. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_config_inppin(FAR struct stm32_comp_s *priv) +{ +# if defined(CONFIG_STM32_COMP1) + if (priv->csr == STM32_COMP1_CSR) + { + stm32_configgpio(GPIO_COMP1_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP2) + if (priv->csr == STM32_COMP2_CSR) + { + stm32_configgpio(GPIO_COMP2_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP3) + if (priv->csr == STM32_COMP3_CSR) + { + stm32_configgpio(GPIO_COMP3_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP4) + if (priv->csr == STM32_COMP4_CSR) + { + stm32_configgpio(GPIO_COMP4_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP5) + if (priv->csr == STM32_COMP5_CSR) + { + stm32_configgpio(GPIO_COMP5_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP6) + if (priv->csr == STM32_COMP6_CSR) + { + stm32_configgpio(GPIO_COMP6_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP7) + if (priv->csr == STM32_COMP7_CSR) + { + stm32_configgpio(GPIO_COMP7_INP); + } +# endif + + return OK; +} + +/**************************************************************************** + * Name: comp_config_outpin + * + * Description: + * Configure comparator output GPIO pin. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(COMP_OUT_GPIO) +static int comp_config_outpin(FAR struct stm32_comp_s *priv) +{ +# if defined(CONFIG_STM32_COMP1_OUT) + if (priv->csr == STM32_COMP1_CSR) + { + stm32_configgpio(GPIO_COMP1_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP2_OUT) + if (priv->csr == STM32_COMP2_CSR) + { + ainfo("\tOUT assigned to: GPIO\n"); + stm32_configgpio(GPIO_COMP2_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP3_OUT) + if (priv->csr == STM32_COMP3_CSR) + { + stm32_configgpio(GPIO_COMP3_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP4_OUT) + if (priv->csr == STM32_COMP4_CSR) + { + stm32_configgpio(GPIO_COMP4_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP5_OUT) + if (priv->csr == STM32_COMP5_CSR) + { + stm32_configgpio(GPIO_COMP5_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP6_OUT) + if (priv->csr == STM32_COMP6_CSR) + { + stm32_configgpio(GPIO_COMP6_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP7_OUT) + if (priv->csr == STM32_COMP7_CSR) + { + stm32_configgpio(GPIO_COMP7_OUT); + } +# endif + + return OK; +} +#endif /* COMP_OUT_GPIO */ + +/**************************************************************************** + * Name: comp_config + * + * Description: + * Configure comparator and used I/Os. The pin configuration and the input + * assignments are COMP index dependent. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + * REVISIT: Where to config comparator output pin ? + * + ****************************************************************************/ + +static int comp_config(FAR struct stm32_comp_s *priv) +{ + uint32_t regval = 0; + uint32_t value = 0; + + /* Configure COMPx inverting input. */ + + value = priv->inm << COMP_CSR_INMSEL_SHIFT; + + switch (priv->inm) + { + case COMP_INM_1_4_VREF: + case COMP_INM_1_2_VREF: + case COMP_INM_3_4_VREF: + + value |= COMP_CSR_BRGEN; /* scaler resistor bridge enable */ + + case COMP_INM_VREF: + + value |= COMP_CSR_SCALEN; /* VREFINT scaler enable */ + break; + + case COMP_INM_DAC_1: + case COMP_INM_DAC_2: + + break; + + case COMP_INM_PIN_1: + case COMP_INM_PIN_2: + + comp_config_inmpin(priv); + break; + + default: + return -EINVAL; + } + + regval |= value; + + /* Configure COMPx non-inverting input. */ + + ainfo("\tINP assigned to GPIO%d\n", priv->inp); + + value = priv->inp << COMP_CSR_INPSEL_SHIFT; + regval |= value; + + comp_config_inppin(priv); + + /* Configure COMPx polarity */ + + if (priv->pol == COMP_POL_INVERTED) + { + value = COMP_CSR_POL; + regval |= value; + } + + /* Configure COMPx hysteresis */ + + switch (priv->hyst) + { + case COMP_HYST_DIS: + case COMP_HYST_10MV: + case COMP_HYST_20MV: + case COMP_HYST_30MV: + case COMP_HYST_40MV: + case COMP_HYST_50MV: + case COMP_HYST_60MV: + case COMP_HYST_70MV: + + value = priv->hyst << COMP_CSR_HYST_SHIFT; + regval |= value; + break; + + default: + return -EINVAL; + } + + /* Configure COMPx blanking signal source */ + + switch (priv->blanking) + { + case COMP_BLANKING_DIS: + case COMP_BLANKING_TIMX_OCY_1: + case COMP_BLANKING_TIMX_OCY_2: + case COMP_BLANKING_TIMX_OCY_3: + case COMP_BLANKING_TIMX_OCY_4: + case COMP_BLANKING_TIMX_OCY_5: + case COMP_BLANKING_TIMX_OCY_6: + case COMP_BLANKING_TIMX_OCY_7: + + value = priv->blanking << COMP_CSR_BLANKING_SHIFT; + regval |= value; + break; + + default: + return -EINVAL; + } + + /* Set Comparator output selection */ + +#if defined(COMP_OUT_GPIO) + comp_config_outpin(priv); +#endif + + /* Save CSR register */ + + comp_putreg_csr(priv, regval); + + /* Enable Comparator */ + + comp_enable(priv, true); + + /* Lock Comparator if needed */ + + if (priv->lock) + { + comp_lock_set(priv, true); + } + + return OK; +} + +/**************************************************************************** + * Name: comp_enable + * + * Description: + * Enable/disable comparator + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - enable/disable flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_enable(FAR struct stm32_comp_s *priv, bool enable) +{ + bool lock; + + ainfo("enable: %d\n", enable ? 1 : 0); + + lock = comp_lock_get(priv); + + if (lock) + { + aerr("ERROR: Comparator locked!\n"); + + return -EPERM; + } + else + { + if (enable) + { + /* Enable the COMP */ + + comp_modify_csr(priv, 0, COMP_CSR_COMPEN); + } + else + { + /* Disable the COMP */ + + comp_modify_csr(priv, COMP_CSR_COMPEN, 0); + } + } + + return OK; +} + +/**************************************************************************** + * Name: comp_setup + * + * Description: + * Configure the COMP. This method is called the first time that the COMP + * device is opened. This will occur when the port is first opened. This + * setup includes configuring and attaching COMP interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +static int comp_setup(FAR struct comp_dev_s *dev) +{ +#warning "Missing logic" + + return OK; +} +#endif + +/**************************************************************************** + * Name: comp_shutdown + * + * Description: + * Disable the COMP. This method is called when the COMP device is closed. + * This method reverses the operation the setup method. + * Works only if COMP device is not locked. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +static void comp_shutdown(FAR struct comp_dev_s *dev) +{ +# warning "Missing logic" +} +#endif + +/**************************************************************************** + * Name: comp_read + * + * Description: + * Get the COMP output state. + * + * Input Parameters: + * + * Returned Value: + * 0 if output is low (non-inverting input below inverting input), + * 1 if output is high (non inverting input above inverting input). + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +static int comp_read(FAR struct comp_dev_s *dev) +{ + FAR struct stm32_comp_s *priv; + uint32_t regval; + + priv = dev->ad_priv; + regval = comp_getreg_csr(priv); + + return (((regval & COMP_CSR_VALUE) == 0) ? 0 : 1); +} +#endif + +/**************************************************************************** + * Name: comp_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, unsigned long arg) +{ +#warning "Missing logic" + return -ENOTTY; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +FAR struct comp_dev_s *stm32_compinitialize(int intf) +{ + FAR struct comp_dev_s *dev; + FAR struct stm32_comp_s *comp; + int ret; + + switch (intf) + { +#ifdef CONFIG_STM32_COMP1 + case 1: + ainfo("COMP1 selected\n"); + dev = &g_comp1dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP2 + case 2: + ainfo("COMP2 selected\n"); + dev = &g_comp2dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP3 + case 3: + ainfo("COMP3 selected\n"); + dev = &g_comp3dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP4 + case 4: + ainfo("COMP4 selected\n"); + dev = &g_comp4dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP5 + case 5: + ainfo("COMP5 selected\n"); + dev = &g_comp5dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP6 + case 6: + ainfo("COMP6 selected\n"); + dev = &g_comp6dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP7 + case 7: + ainfo("COMP7 selected\n"); + dev = &g_comp7dev; + break; +#endif + + default: + aerr("ERROR: No COMP interface defined\n"); + return NULL; + } + + /* Configure selected comparator */ + + comp = dev->ad_priv; + + ret = comp_config(comp); + if (ret < 0) + { + aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); + return NULL; + } + + return dev; +} + +#endif /* CONFIG_STM32_COMP */ diff --git a/arch/arm/src/stm32/stm32_comp_v2.h b/arch/arm/src/stm32/stm32_comp_v2.h new file mode 100644 index 00000000000..7ad1e744ec1 --- /dev/null +++ b/arch/arm/src/stm32/stm32_comp_v2.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_comp_v2.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H +#define __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifdef CONFIG_STM32_COMP + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Inverting input. See Table 196 in RM0440 */ + +enum stm32_comp_inm_e +{ + COMP_INM_1_4_VREF, + COMP_INM_1_2_VREF, + COMP_INM_3_4_VREF, + COMP_INM_VREF, + COMP_INM_DAC_1, + COMP_INM_DAC_2, + COMP_INM_PIN_1, + COMP_INM_PIN_2, +}; + +/* Non-inverting input. See Table 195 in RM0440 */ + +enum stm32_comp_inp_e +{ + COMP_INP_PIN_1, + COMP_INP_PIN_2, +}; + +/* Output polarity */ + +enum stm32_comp_pol_e +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; + +/* Hysteresis */ + +enum stm32_comp_hyst_e +{ + COMP_HYST_DIS, + COMP_HYST_10MV, + COMP_HYST_20MV, + COMP_HYST_30MV, + COMP_HYST_40MV, + COMP_HYST_50MV, + COMP_HYST_60MV, + COMP_HYST_70MV, +}; + +/* Blanking source */ + +enum stm32_comp_blanking_e +{ + COMP_BLANKING_DIS, + COMP_BLANKING_TIMX_OCY_1, + COMP_BLANKING_TIMX_OCY_2, + COMP_BLANKING_TIMX_OCY_3, + COMP_BLANKING_TIMX_OCY_4, + COMP_BLANKING_TIMX_OCY_5, + COMP_BLANKING_TIMX_OCY_6, + COMP_BLANKING_TIMX_OCY_7, +}; + +#endif /* CONFIG_STM32_COMP */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H */ diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index 7964a06c5d5..95c190e175d 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -1056,7 +1056,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) #ifdef HAVE_TIMER if (chan->timer != TIM_INDEX_HRTIM) { - tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG); + tim_modifyreg(chan, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); } #endif @@ -1336,26 +1336,26 @@ static int dac_timinit(FAR struct stm32_chan_s *chan) /* Set the reload and prescaler values */ - tim_putreg(chan, STM32_BTIM_ARR_OFFSET, (uint16_t)reload); - tim_putreg(chan, STM32_BTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + tim_putreg(chan, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); + tim_putreg(chan, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); /* Count mode up, auto reload */ - tim_modifyreg(chan, STM32_BTIM_CR1_OFFSET, 0, ATIM_CR1_ARPE); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Selection TRGO selection: update */ - tim_modifyreg(chan, STM32_BTIM_CR2_OFFSET, ATIM_CR2_MMS_MASK, - ATIM_CR2_MMS_UPDATE); + tim_modifyreg(chan, STM32_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, + GTIM_CR2_MMS_UPDATE); /* Update DMA request enable ???? */ #if 0 - tim_modifyreg(chan, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UDE); + tim_modifyreg(chan, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); #endif /* Enable the counter */ - tim_modifyreg(chan, STM32_BTIM_CR1_OFFSET, 0, ATIM_CR1_CEN); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); return OK; } #endif diff --git a/arch/arm/src/stm32/stm32_dfumode.c b/arch/arm/src/stm32/stm32_dfumode.c index b71ec2f480e..ddd065573fa 100644 --- a/arch/arm/src/stm32/stm32_dfumode.c +++ b/arch/arm/src/stm32/stm32_dfumode.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_dfumode.c * - * Copyright (C) 2019 Bill Gatliff. All rights reserved. - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Bill Gatliff - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h index f978141a980..825408a1da9 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/stm32/stm32_dma.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_dma.h * - * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c index 99d955d9289..b18593669d2 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/stm32/stm32_dma2d.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/stm32/stm32_dma_v1.c index da94ffa98f7..f8bd428a317 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/stm32/stm32_dma_v1.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_dma_v1mux.c b/arch/arm/src/stm32/stm32_dma_v1mux.c index 809831b4d23..300fc1c77ee 100644 --- a/arch/arm/src/stm32/stm32_dma_v1mux.c +++ b/arch/arm/src/stm32/stm32_dma_v1mux.c @@ -1,43 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_dma_v1mux.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jussi Kivilinna + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on STM32H7 DMAMUX/DMA driver: - * Author: Mateusz Szafoni + * http://www.apache.org/licenses/LICENSE-2.0 * - * Based on STM32X6XX DMA driver: - * Author: Gregory Nutt - * Author: Sebastien Lorquet - * Author: dev@ziggurat29.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -50,6 +27,7 @@ #include #include #include +#include #include #include @@ -1066,13 +1044,13 @@ void weak_function arm_dma_initialize(void) * in hardware/stm32g4xxxx_dmamux.h * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * * Assumptions: * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no + * - The caller can wait for the DMA channel to be freed if it is not * available. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/stm32/stm32_dma_v2.c index 6f63e019c31..6abebd89117 100644 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ b/arch/arm/src/stm32/stm32_dma_v2.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c index 2c7c9585177..01f8745da4a 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/stm32/stm32_dumpgpio.c @@ -30,6 +30,7 @@ #define CONFIG_DEBUG_INFO 1 #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index ea38cac9ccc..3da261c10a2 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -30,7 +30,9 @@ #include #include #include +#include #include +#include #include #include @@ -404,7 +406,6 @@ /* The following bits are set or left zero unconditionally in all modes. * - * ETH_MACFFR_PM Promiscuous mode 0 (disabled) * ETH_MACFFR_HU Hash unicast 0 (perfect dest filtering) * ETH_MACFFR_HM Hash multicast 0 (perfect dest filtering) * ETH_MACFFR_DAIF Destination address 0 (normal) @@ -419,7 +420,11 @@ * ETH_MACFFR_RA Receive all 0 (disabled) */ -#define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE) +#ifdef CONFIG_NET_PROMISCUOUS +# define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE | ETH_MACFFR_PM) +#else +# define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE) +#endif /* Clear the MACFCR bits that will be setup during MAC initialization (or * that are cleared unconditionally). Per the reference manual, all reserved diff --git a/arch/arm/src/stm32/stm32_exti_alarm.c b/arch/arm/src/stm32/stm32_exti_alarm.c index c228736ab03..edeff8b77cf 100644 --- a/arch/arm/src/stm32/stm32_exti_alarm.c +++ b/arch/arm/src/stm32/stm32_exti_alarm.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_exti_alarm.c * - * Copyright (C) 2009, 2012, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_exti_wakeup.c b/arch/arm/src/stm32/stm32_exti_wakeup.c index 9deef84e167..ca6c05538a9 100644 --- a/arch/arm/src/stm32/stm32_exti_wakeup.c +++ b/arch/arm/src/stm32/stm32_exti_wakeup.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_exti_wakeup.c * - * Copyright (C) 2009, 2012, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/stm32/stm32_fmc.c index a81a3a8c50e..287ab22b0a3 100644 --- a/arch/arm/src/stm32/stm32_fmc.c +++ b/arch/arm/src/stm32/stm32_fmc.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_fmc.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jason T. Harris + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -39,6 +24,8 @@ #include +#include + #include "stm32.h" #if defined(CONFIG_STM32_FMC) diff --git a/arch/arm/src/stm32/stm32_fmc.h b/arch/arm/src/stm32/stm32_fmc.h index 8df79ac0a86..7aa63007009 100644 --- a/arch/arm/src/stm32/stm32_fmc.h +++ b/arch/arm/src/stm32/stm32_fmc.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_fmc.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jason T. Harris + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/stm32/stm32_foc.c index 2dc77ca9b1a..2ceb104f363 100644 --- a/arch/arm/src/stm32/stm32_foc.c +++ b/arch/arm/src/stm32/stm32_foc.c @@ -263,7 +263,7 @@ # error Not supported # endif -/* ADC trigger offset - must be greather than 0! */ +/* ADC trigger offset - must be greater than 0! */ # define ADC_TRIGGER_OFFSET (1) @@ -377,6 +377,14 @@ # endif #endif +/* The number of required injected channels */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# define FOC_ADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_SHUNTS + 1) +#else +# define FOC_ADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_SHUNTS) +#endif + /* Validate ADC configuration: * 1. ADC must be supported by chip, * 2. ADC support for injected channels must be enabled, @@ -393,8 +401,8 @@ # if CONFIG_STM32_ADC1_ANIOC_TRIGGER != 1 # error CONFIG_STM32_ADC1_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32_ADC1_INJECTED_CHAN != CONFIG_MOTOR_FOC_SHUNTS -# error Invalid configuration for ADC1 injected channles +# if CONFIG_STM32_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC1 injected channels # endif #endif #ifdef CONFIG_STM32_FOC_USE_ADC2 @@ -407,8 +415,8 @@ # if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 # error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32_ADC2_INJECTED_CHAN != CONFIG_MOTOR_FOC_SHUNTS -# error Invalid configuration for ADC2 injected channles +# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC2 injected channels # endif #endif #ifdef CONFIG_STM32_FOC_USE_ADC3 @@ -421,8 +429,8 @@ # if CONFIG_STM32_ADC3_ANIOC_TRIGGER != 1 # error CONFIG_STM32_ADC3_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32_ADC3_INJECTED_CHAN != CONFIG_MOTOR_FOC_SHUNTS -# error Invalid configuration for ADC3 injected channles +# if CONFIG_STM32_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC3 injected channels # endif #endif #ifdef CONFIG_STM32_FOC_USE_ADC4 @@ -435,8 +443,16 @@ # if CONFIG_STM32_ADC4_ANIOC_TRIGGER != 1 # error CONFIG_STM32_ADC4_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32_ADC4_INJECTED_CHAN != CONFIG_MOTOR_FOC_SHUNTS -# error Invalid configuration for ADC4 injected channles +# if CONFIG_STM32_ADC4_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC4 injected channels +# endif +#endif + +/* Max 3 shunts supported if STM32G4 ADC CHAN0 workaround enabled */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# if CONFIG_MOTOR_FOC_SHUNTS > 3 +# error # endif #endif @@ -449,7 +465,7 @@ # define FOC1_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC1_ADC_JEXTSEL) #endif -/* Generalize ADC interupt flags */ +/* Generalize ADC interrupt flags */ #if defined(CONFIG_STM32_HAVE_IP_ADC_V2) # define FOC_ADC_ISR_FOC ADC_ISR_JEOS @@ -767,6 +783,8 @@ static int stm32_foc_worker_handler(FAR struct foc_dev_s *dev); /* Helpers */ +static void stm32_foc_curr_get(FAR struct foc_dev_s *dev, + FAR int16_t *curr, int shunts); static int stm32_foc_notifier_cfg(FAR struct foc_dev_s *dev, uint32_t freq); static int stm32_foc_pwm_cfg(FAR struct foc_dev_s *dev, uint32_t freq); static int stm32_foc_adc_cfg(FAR struct foc_dev_s *dev); @@ -895,7 +913,7 @@ void stm32_foc_sync_all(void) { /* Force update event to reset CNTR */ - putreg32(ATIM_EGR_UG, egr_reg[i]); + putreg32(GTIM_EGR_UG, egr_reg[i]); } } #endif @@ -1521,21 +1539,16 @@ static int stm32_foc_ioctl(FAR struct foc_dev_s *dev, int cmd, static int stm32_foc_adc_calibration_handler(FAR struct foc_dev_s *dev) { FAR struct stm32_foc_priv_s *priv = STM32_FOC_PRIV_FROM_DEV_GET(dev); - FAR struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); int i = 0; DEBUGASSERT(dev); DEBUGASSERT(priv); - DEBUGASSERT(adc); if (priv->data.adcint_cntr < CAL_SAMPLES) { - /* Get raw currents */ + /* Get raw current samples */ - for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) - { - priv->data.curr_raw[i] = (int16_t)STM32_ADC_INJDATA_GET(adc, i); - } + stm32_foc_curr_get(dev, priv->data.curr_raw, CONFIG_MOTOR_FOC_SHUNTS); /* Get sum */ @@ -1677,7 +1690,6 @@ static int stm32_foc_worker_handler(FAR struct foc_dev_s *dev) FAR struct stm32_foc_priv_s *priv = STM32_FOC_PRIV_FROM_DEV_GET(dev); FAR struct stm32_foc_board_s *board = STM32_FOC_BOARD_FROM_DEV_GET(dev); FAR struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); - int i = 0; int ret = OK; DEBUGASSERT(dev); @@ -1689,16 +1701,9 @@ static int stm32_foc_worker_handler(FAR struct foc_dev_s *dev) if (priv->data.adcint_cntr % priv->data.notifier_div == 0) { - for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) - { - /* Get raw current samples. - * We have ADC offset enabled for injected channels so this - * gives us signed values. - * NOTE: ADC value is 11 bits + sign. - */ + /* Get raw current samples */ - priv->data.curr_raw[i] = (int16_t)STM32_ADC_INJDATA_GET(adc, i); - } + stm32_foc_curr_get(dev, priv->data.curr_raw, CONFIG_MOTOR_FOC_SHUNTS); /* Get phase currents */ @@ -1922,6 +1927,44 @@ static void stm32_foc_hw_config_get(FAR struct foc_dev_s *dev) dev->info.hw_cfg.pwm_max = board->data->duty_max; } +/**************************************************************************** + * Name: stm32_foc_curr_get + * + * Description: + * Get current samples from ADC + * + ****************************************************************************/ + +static void stm32_foc_curr_get(FAR struct foc_dev_s *dev, + FAR int16_t *curr, int shunts) +{ + FAR struct stm32_foc_priv_s *priv = STM32_FOC_PRIV_FROM_DEV_GET(dev); + FAR struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); + int i = 0; + + DEBUGASSERT(dev); + DEBUGASSERT(priv); + DEBUGASSERT(adc); + DEBUGASSERT(curr); + + for (i = 0; i < shunts; i += 1) + { + /* Get raw current samples. + * We have ADC offset enabled for injected channels so this + * gives us signed values. + * NOTE: ADC value is 11 bits + sign. + */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + /* Ignore first channel */ + + curr[i] = (int16_t)STM32_ADC_INJDATA_GET(adc, (i + 1)); +#else + curr[i] = (int16_t)STM32_ADC_INJDATA_GET(adc, i); +#endif + } +} + /**************************************************************************** * Name: stm32_foc_notifier_cfg * @@ -2086,11 +2129,11 @@ void stm32_foc_trace(FAR struct foc_dev_s *dev, int type, bool state) * Initialize the FOC lower-half. * * Input Parameters: - * inst - FOC instnace number + * inst - FOC instance number * board - FOC board-specific data * * Returned Value: - * Valid lower-half FOC controller structure reference on succes; + * Valid lower-half FOC controller structure reference on success; * NULL on failure * ****************************************************************************/ @@ -2112,7 +2155,11 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board) uint8_t pwm_inst = 0; uint8_t adc_inst = 0; uint32_t pwmfzbit = 0; - int j = 0; + int i = 0; +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + FAR uint8_t *adc_chan = NULL; + uint8_t adc_nchan = 0; +#endif DEBUGASSERT(board != NULL); DEBUGASSERT(board->ops != NULL); @@ -2208,7 +2255,7 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board) foc_priv->adc_cmn = adc_cmn; #endif - /* Get archspecific devive */ + /* Get arch-specific device */ foc_dev = (struct stm32_foc_dev_s *)foc_priv->dev; DEBUGASSERT(foc_dev); @@ -2237,9 +2284,9 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board) DEBUGASSERT(adc_cfg->pins != NULL); DEBUGASSERT(adc_cfg->chan != NULL); - for (j = 0; j < adc_cfg->nchan; j++) + for (i = 0; i < adc_cfg->nchan; i++) { - stm32_configgpio(adc_cfg->pins[j]); + stm32_configgpio(adc_cfg->pins[i]); } /* Make sure that we are using the appropriate ADC interface */ @@ -2252,11 +2299,55 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board) goto errout; } + /* STM32G4 ADC channel 0 unwanted conversion workaround */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + /* Add one dummy channel to conversion */ + + adc_nchan = (adc_cfg->nchan + 1); + + /* Allocate memory for the extended list of channels */ + + adc_chan = zalloc(adc_nchan); + if (adc_chan == NULL) + { + goto errout; + } + + /* Copy regular channels first */ + + for (i = 0; i < adc_cfg->regch; i += 1) + { + adc_chan[i] = adc_cfg->chan[i]; + } + + /* Add dummy channel at the beginning of injected channels */ + + adc_chan[adc_cfg->regch] = 0; + + /* Copy injected channels */ + + for (i = (adc_cfg->regch + 1); i < adc_nchan; i += 1) + { + adc_chan[i] = adc_cfg->chan[i - 1]; + } + +#endif /* CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND */ + /* Get the ADC interface */ +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + foc_dev->adc_dev = stm32_adcinitialize(adc_inst, + adc_chan, + adc_nchan); + + free(adc_chan); +#else foc_dev->adc_dev = stm32_adcinitialize(adc_inst, adc_cfg->chan, adc_cfg->nchan); +#endif + if (foc_dev->adc_dev == NULL) { mtrerr("Failed to get ADC%d interface\n", adc_cfg->intf); diff --git a/arch/arm/src/stm32/stm32_foc.h b/arch/arm/src/stm32/stm32_foc.h index a637d142e54..72863b85ef1 100644 --- a/arch/arm/src/stm32/stm32_foc.h +++ b/arch/arm/src/stm32/stm32_foc.h @@ -56,7 +56,7 @@ struct stm32_foc_adc_s uint8_t nchan; - /* The number of auxliary regular channles (only for DMA transfer) */ + /* The number of auxiliary regular channels (only for DMA transfer) */ uint8_t regch; diff --git a/arch/arm/src/stm32/stm32_fsmc.c b/arch/arm/src/stm32/stm32_fsmc.c index 93fd9cdd91c..f6941b675b8 100644 --- a/arch/arm/src/stm32/stm32_fsmc.c +++ b/arch/arm/src/stm32/stm32_fsmc.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_fsmc.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jason T. Harris + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_fsmc.h b/arch/arm/src/stm32/stm32_fsmc.h index 620ace3955b..273a90496bb 100644 --- a/arch/arm/src/stm32/stm32_fsmc.h +++ b/arch/arm/src/stm32/stm32_fsmc.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_fsmc.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jason T. Harris + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_hciuart.c b/arch/arm/src/stm32/stm32_hciuart.c index 0bcc8ee8ae6..923728aaa9c 100644 --- a/arch/arm/src/stm32/stm32_hciuart.c +++ b/arch/arm/src/stm32/stm32_hciuart.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c index 037970b2f97..62990bbe660 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/stm32/stm32_i2c.c @@ -59,6 +59,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c index ce55c2eeaa0..733ef866d9d 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/stm32/stm32_i2c_alt.c @@ -87,6 +87,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_i2c_v2.c b/arch/arm/src/stm32/stm32_i2c_v2.c index 06b40b8f010..0780122982a 100644 --- a/arch/arm/src/stm32/stm32_i2c_v2.c +++ b/arch/arm/src/stm32/stm32_i2c_v2.c @@ -227,6 +227,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/stm32/stm32_i2s.c index 5995faef06a..7ff175a4285 100644 --- a/arch/arm/src/stm32/stm32_i2s.c +++ b/arch/arm/src/stm32/stm32_i2s.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_i2s.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Taras Drozdovskiy + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index 28b24b080a2..9fea7a2fbe9 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/stm32/stm32_iwdg.c index 15dabbca985..f0042c24da9 100644 --- a/arch/arm/src/stm32/stm32_iwdg.c +++ b/arch/arm/src/stm32/stm32_iwdg.c @@ -27,6 +27,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c index 203dd4c8c52..05b2225be48 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/stm32/stm32_ltdc.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index 5836a9cbbaf..8c6e24a3fa4 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index 6587c867904..52049f57ba2 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index fb515faae0b..d0d8575ada1 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index db0dc21673b..2cc3de71b39 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_pmsleep.c b/arch/arm/src/stm32/stm32_pmsleep.c index c70cb5243c6..6907b404eaf 100644 --- a/arch/arm/src/stm32/stm32_pmsleep.c +++ b/arch/arm/src/stm32/stm32_pmsleep.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_pmsleep.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * http://www.apache.org/licenses/LICENSE-2.0 * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 318fb6b81dc..e3f959bdb6c 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -410,9 +410,8 @@ struct stm32_pwmtimer_s uint8_t prev; /* The previous value of the RCR (pre-loaded) */ uint8_t curr; /* The current value of the RCR (pre-loaded) */ uint32_t count; /* Remaining pulse count */ -#else - uint32_t frequency; /* Current frequency setting */ #endif + uint32_t frequency; /* Current frequency setting */ uint32_t base; /* The base address of the timer */ uint32_t pclk; /* The frequency of the peripheral * clock that drives the timer module @@ -488,10 +487,9 @@ static int pwm_configure(FAR struct pwm_lowerhalf_s *dev); #ifdef CONFIG_PWM_PULSECOUNT static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info); -#else +#endif static int pwm_timer(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info); -#endif #ifdef HAVE_PWM_INTERRUPT static int pwm_interrupt(FAR struct pwm_lowerhalf_s *dev); # ifdef CONFIG_STM32_TIM1_PWM @@ -509,13 +507,12 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev); static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev); #ifdef CONFIG_PWM_PULSECOUNT -static int pwm_start(FAR struct pwm_lowerhalf_s *dev, - FAR const struct pwm_info_s *info, - FAR void *handle); -#else +static int pwm_start_pulsecount(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info, + FAR void *handle); +#endif static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info); -#endif static int pwm_stop(FAR struct pwm_lowerhalf_s *dev); static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, @@ -533,7 +530,11 @@ static const struct pwm_ops_s g_pwmops = { .setup = pwm_setup, .shutdown = pwm_shutdown, +#ifdef CONFIG_PWM_PULSECOUNT + .start = pwm_start_pulsecount, +#else .start = pwm_start, +#endif .stop = pwm_stop, .ioctl = pwm_ioctl, }; @@ -683,7 +684,7 @@ static struct stm32_pwmchan_s g_pwm1channels[] = .in_use = 1, .pol = CONFIG_STM32_TIM1_CH5POL, .idle = CONFIG_STM32_TIM1_CH5IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif }, @@ -698,7 +699,7 @@ static struct stm32_pwmchan_s g_pwm1channels[] = .in_use = 1, .pol = CONFIG_STM32_TIM1_CH6POL, .idle = CONFIG_STM32_TIM1_CH6IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif } @@ -1243,7 +1244,7 @@ static struct stm32_pwmchan_s g_pwm8channels[] = .in_use = 1, .pol = CONFIG_STM32_TIM8_CH5POL, .idle = CONFIG_STM32_TIM8_CH5IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif }, @@ -1258,7 +1259,7 @@ static struct stm32_pwmchan_s g_pwm8channels[] = .in_use = 1, .pol = CONFIG_STM32_TIM8_CH6POL, .idle = CONFIG_STM32_TIM8_CH6IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif } @@ -2646,13 +2647,13 @@ static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, case STM32_CHANMODE_PWM1: { - chanmode = ATIM_CCMR_MODE_PWM1; + chanmode = GTIM_CCMR_MODE_PWM1; break; } case STM32_CHANMODE_PWM2: { - chanmode = ATIM_CCMR_MODE_PWM2; + chanmode = GTIM_CCMR_MODE_PWM2; break; } @@ -2973,13 +2974,13 @@ static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev, /* Get outputs configuration */ - regval |= ((outputs & STM32_PWM_OUT1) ? ATIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0); regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32_PWM_OUT2) ? ATIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0); regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32_PWM_OUT3) ? ATIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0); regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32_PWM_OUT4) ? ATIM_CCER_CC4E : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0); /* NOTE: CC4N doesn't exist, but some docs show configuration bits for it */ @@ -3093,7 +3094,7 @@ static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev) { FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; - pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); return OK; } @@ -3376,7 +3377,6 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; ub16_t duty = 0; uint8_t channel = 0; - uint32_t mode = 0; uint16_t outputs = 0; int ret = OK; @@ -3384,7 +3384,8 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); - pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n", + pwminfo("TIM%u channel: %u frequency: %" PRIx32 " duty: %08" PRIx32 + " count: %" PRIx32 "\n", priv->timid, priv->channels[0].channel, info->frequency, info->duty, info->count); @@ -3394,7 +3395,6 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, duty = info->duty; channel = priv->channels[0].channel; - mode = priv->channels[0].mode; /* Disable all interrupts and DMA requests, clear all pending status */ @@ -3486,7 +3486,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, /* Clear all pending interrupts and enable the update interrupt. */ pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, ATIM_DIER_UIE); + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ @@ -3503,7 +3503,7 @@ errout: return ret; } -#else /* !CONFIG_PWM_PULSECOUNT */ +#endif /* CONFIG_PWM_PULSECOUNT */ /**************************************************************************** * Name: pwm_configure @@ -3795,7 +3795,6 @@ static int pwm_timer(FAR struct pwm_lowerhalf_s *dev, errout: return ret; } -#endif /* CONFIG_PWM_PULSECOUNT */ #ifdef HAVE_PWM_INTERRUPT @@ -3875,7 +3874,7 @@ static int pwm_interrupt(FAR struct pwm_lowerhalf_s *dev) * output. */ - pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n", + pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %" PRIx32 "\n", regval, priv->prev, priv->curr, priv->count); return OK; @@ -4230,10 +4229,16 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) */ #ifdef CONFIG_PWM_PULSECOUNT - ret = pwm_pulsecount_configure(dev); -#else - ret = pwm_configure(dev); + if (priv->timtype == TIMTYPE_ADVANCED) + { + ret = pwm_pulsecount_configure(dev); + } + else #endif + { + ret = pwm_configure(dev); + } + if (ret < 0) { pwmerr("failed to configure PWM %d\n", priv->timid); @@ -4331,12 +4336,19 @@ errout: ****************************************************************************/ #ifdef CONFIG_PWM_PULSECOUNT -static int pwm_start(FAR struct pwm_lowerhalf_s *dev, - FAR const struct pwm_info_s *info, - FAR void *handle) +static int pwm_start_pulsecount(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info, + FAR void *handle) { FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + /* Generate an indefinite number of pulses */ + + if (info->count == 0) + { + return pwm_start(dev, info); + } + /* Check if a pulsecount has been selected */ if (info->count > 0) @@ -4347,7 +4359,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, if (priv->timtype != TIMTYPE_ADVANCED) { - pwmerr("ERROR: TIM%u cannot support pulse count: %u\n", + pwmerr("ERROR: TIM%u cannot support pulse count: %" PRIx32 "\n", priv->timid, info->count); return -EPERM; } @@ -4361,7 +4373,8 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, return pwm_pulsecount_timer(dev, info); } -#else /* !CONFIG_PWM_PULSECOUNT */ +#endif /* CONFIG_PWM_PULSECOUNT */ + static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info) { @@ -4403,7 +4416,6 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, return ret; } -#endif /* CONFIG_PWM_PULSECOUNT */ /**************************************************************************** * Name: pwm_stop @@ -4587,11 +4599,9 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) flags = enter_critical_section(); -#ifndef CONFIG_PWM_PULSECOUNT /* Stopped so frequency is zero */ priv->frequency = 0; -#endif /* Disable further interrupts and stop the timer */ diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/stm32/stm32_pwr.c index 5fcfb83b08d..82bc75a0391 100644 --- a/arch/arm/src/stm32/stm32_pwr.c +++ b/arch/arm/src/stm32/stm32_pwr.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index 14b4c998fef..6cc783e4aa6 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_qencoder.c * - * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c index 1d1e40ac0ab..9b3ed1cf120 100644 --- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 898e32bf12f..3b38f7dbe29 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -153,7 +153,7 @@ # define SDIO_CLKCR_EDGE SDIO_CLKCR_RISINGEDGE #endif -/* Mode dependent settings. These depend on clock devisor settings that must +/* Mode dependent settings. These depend on clock divisor settings that must * be defined in the board-specific board.h header file: SDIO_INIT_CLKDIV, * SDIO_MMCXFR_CLKDIV, and SDIO_SDXFR_CLKDIV. */ @@ -172,9 +172,12 @@ #define SDIO_CMDTIMEOUT (100000) #define SDIO_LONGTIMEOUT (0x7fffffff) -/* Big DTIMER setting */ +/* DTIMER setting */ -#define SDIO_DTIMER_DATATIMEOUT (0x000fffff) +/* Assuming Max timeout in bypass 48 Mhz */ + +#define IP_CLCK_FREQ UINT32_C(48000000) +#define SDIO_DTIMER_DATATIMEOUT_MS 250 /* DMA channel/stream configuration register settings. The following * must be selected. The DMA driver will select the remaining fields. @@ -659,12 +662,8 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, flags = enter_critical_section(); #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE - if ((waitmask & SDIOWAIT_WRCOMPLETE) != 0) + if ((waitevents & SDIOWAIT_WRCOMPLETE) != 0) { - /* Do not use this in STM32_SDIO_MASK register */ - - waitmask &= ~SDIOWAIT_WRCOMPLETE; - pinset = GPIO_SDIO_D0 & (GPIO_PORT_MASK | GPIO_PIN_MASK); pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI); @@ -1016,9 +1015,24 @@ static uint8_t stm32_log2(uint16_t value) static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) { - uint32_t regval = 0; + uint32_t clkdiv; + uint32_t regval; + uint32_t sdio_clk = IP_CLCK_FREQ; - /* Enable data path */ + /* Enable data path using a timeout scaled to the SD_CLOCK (the card + * clock). + */ + + regval = getreg32(STM32_SDIO_CLKCR); + clkdiv = (regval & SDIO_CLKCR_CLKDIV_MASK) >> SDIO_CLKCR_CLKDIV_SHIFT; + if ((regval & SDIO_CLKCR_BYPASS) == 0) + { + sdio_clk = sdio_clk / (2 + clkdiv); + } + + /* Convert Timeout in Ms to SD_CLK counts */ + + timeout = timeout * (sdio_clk / 1000); putreg32(timeout, STM32_SDIO_DTIMER); /* Set DTIMER */ putreg32(dlen, STM32_SDIO_DLEN); /* Set DLEN */ @@ -1049,10 +1063,15 @@ static void stm32_datadisable(void) { uint32_t regval; - /* Disable the data path */ + /* Disable the data path */ - putreg32(SDIO_DTIMER_DATATIMEOUT, STM32_SDIO_DTIMER); /* Reset DTIMER */ - putreg32(0, STM32_SDIO_DLEN); /* Reset DLEN */ + /* Reset DTIMER */ + + putreg32(UINT32_MAX, STM32_SDIO_DTIMER); + + /* Reset DLEN */ + + putreg32(0, STM32_SDIO_DLEN); /* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */ @@ -1209,14 +1228,23 @@ static void stm32_eventtimeout(wdparm_t arg) DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || priv->wkupevent != 0); + mcinfo("sta: %08" PRIx32 " enabled irq: %08" PRIx32 "\n", + getreg32(STM32_SDIO_STA), + getreg32(STM32_SDIO_MASK)); + /* Is a data transfer complete event expected? */ if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) { /* Yes.. wake up any waiting threads */ +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + stm32_endwait(priv, SDIOWAIT_TIMEOUT | + (priv->waitevents & SDIOWAIT_WRCOMPLETE)); +#else stm32_endwait(priv, SDIOWAIT_TIMEOUT); - mcerr("ERROR: Timeout, remaining: %d\n", priv->remaining); +#endif + mcerr("Timeout: remaining: %d\n", priv->remaining); } } @@ -1335,7 +1363,14 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, static int stm32_rdyinterrupt(int irq, void *context, FAR void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; - stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); + + /* Avoid noise, check the state */ + + if (stm32_gpioread(GPIO_SDIO_D0)) + { + stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); + } + return OK; } #endif @@ -1894,8 +1929,9 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; regval |= cmdidx | SDIO_CMD_CPSMEN; - mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 " regval: %08" PRIx32 "\n", - cmd, arg, regval); + mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 " regval: %08" PRIx32 + " enabled irq: %08" PRIx32 "\n", + cmd, arg, regval, getreg32(STM32_SDIO_MASK)); /* Write the SDIO CMD */ @@ -1975,7 +2011,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32_STM32_SDIO_DMA +#ifdef CONFIG_STM32_SDIO_DMA priv->dmamode = false; #endif @@ -1992,7 +2028,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; } - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, nbytes, dblocksize | SDIO_DCTRL_DTDIR); /* And enable interrupts */ @@ -2040,7 +2076,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32_STM32_SDIO_DMA +#ifdef CONFIG_STM32_SDIO_DMA priv->dmamode = false; #endif @@ -2057,7 +2093,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; } - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize); + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, nbytes, dblocksize); /* Enable TX interrupts */ @@ -2446,7 +2482,9 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev, #if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) if ((eventset & SDIOWAIT_WRCOMPLETE) != 0) { - waitmask = SDIOWAIT_WRCOMPLETE; + /* eventset carries this */ + + waitmask = 0; } else #endif @@ -2800,7 +2838,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; } - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, buflen, dblocksize | SDIO_DCTRL_DTDIR); /* Configure the RX DMA */ @@ -2880,7 +2918,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; } - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize); + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, buflen, dblocksize); /* Configure the TX DMA */ diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index eb60995758b..584215e5c8d 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c index ff1f3e25083..915fe970cdc 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/stm32/stm32_spi.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -1675,7 +1676,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c index 1618eea7acf..38c0330aa5f 100644 --- a/arch/arm/src/stm32/stm32_start.c +++ b/arch/arm/src/stm32/stm32_start.c @@ -74,10 +74,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void stm32_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Private Functions @@ -197,47 +193,6 @@ static inline void stm32_fpuconfig(void) # define stm32_fpuconfig() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -328,17 +283,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/stm32/stm32_tickless.c index a5acb3e46ad..ac7f6783d7e 100644 --- a/arch/arm/src/stm32/stm32_tickless.c +++ b/arch/arm/src/stm32/stm32_tickless.c @@ -124,9 +124,6 @@ struct stm32_tickless_s uint8_t channel; /* The timer channel to use for intervals */ FAR struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ uint32_t frequency; -#ifdef CONFIG_CLOCK_TIMEKEEPING - uint64_t counter_mask; -#endif uint32_t overflow; /* Timer counter overflow */ volatile bool pending; /* True: pending task */ uint32_t period; /* Interval period */ @@ -240,7 +237,8 @@ static int stm32_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -267,7 +265,7 @@ static int stm32_tickless_setchannel(uint8_t channel) /* Set polarity */ - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); /* Define its position (shift) and get register offset */ @@ -538,13 +536,6 @@ void up_timer_initialize(void) STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); -#ifdef CONFIG_CLOCK_TIMEKEEPING - - /* Should this be changed to 0xffff because we use 16 bit timers? */ - - g_tickless.counter_mask = 0xffffffffull; -#endif - /* Set up to receive the callback when the counter overflow occurs */ STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0); @@ -731,7 +722,11 @@ int up_timer_getcounter(FAR uint64_t *cycles) void up_timer_getmask(FAR uint64_t *mask) { DEBUGASSERT(mask != NULL); - *mask = g_tickless.counter_mask; +#ifdef HAVE_32BIT_TICKLESS + *mask = UINT32_MAX; +#else + *mask = UINT16_MAX; +#endif } #endif /* CONFIG_CLOCK_TIMEKEEPING */ diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 27b3fa96998..4608fe72f02 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -599,9 +600,9 @@ static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET); - val |= ATIM_EGR_UG; - stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); + val |= GTIM_EGR_UG; + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -610,10 +611,10 @@ static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev) static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); - val |= ATIM_CR1_CEN; + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -622,9 +623,9 @@ static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev) static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); - val &= ~ATIM_CR1_CEN; - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val &= ~GTIM_CR1_CEN; + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -669,7 +670,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode) { - uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; DEBUGASSERT(dev != NULL); @@ -699,7 +700,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_MODE_DOWN: - val |= ATIM_CR1_DIR; + val |= GTIM_CR1_DIR; case STM32_TIM_MODE_UP: break; @@ -709,11 +710,11 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, * Interrupts are generated on compare, when counting down */ - val |= ATIM_CR1_CENTER1; + val |= GTIM_CR1_CENTER1; break; case STM32_TIM_MODE_PULSE: - val |= ATIM_CR1_OPM; + val |= GTIM_CR1_OPM; break; default: @@ -721,7 +722,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); #if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ @@ -878,7 +879,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -892,7 +893,7 @@ static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -903,8 +904,8 @@ static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET); + stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : + (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); } /**************************************************************************** @@ -918,11 +919,11 @@ static void stm32_tim_setcounter(FAR struct stm32_tim_dev_s *dev, if (stm32_tim_getwidth(dev) > 16) { - stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count); + stm32_putreg32(dev, STM32_GTIM_CNT_OFFSET, count); } else { - stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count); + stm32_putreg16(dev, STM32_GTIM_CNT_OFFSET, (uint16_t)count); } } @@ -985,7 +986,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -1012,9 +1014,9 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_CH_OUTPWM: - ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + - ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -1025,7 +1027,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, if (mode & STM32_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ @@ -1671,7 +1673,7 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, source); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); } /**************************************************************************** @@ -1681,7 +1683,7 @@ static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, source, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); } /**************************************************************************** @@ -1690,7 +1692,7 @@ static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~source); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); } /**************************************************************************** @@ -1699,7 +1701,7 @@ static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & source) ? 1 : 0; } diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c index 3ad5db191f1..c0ed42fb4ca 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/stm32/stm32_usbdev.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c index aad12e9a3c8..002049384f1 100644 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ b/arch/arm/src/stm32/stm32_wwdg.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32/stm32f37xxx_rcc.c index 51302c7c888..c3d2ded4f6a 100644 --- a/arch/arm/src/stm32/stm32f37xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f37xxx_rcc.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32f37xxx_rcc.c * - * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Modified for STM32F373 by Marten Svanfeldt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32f40xxx_alarm.h b/arch/arm/src/stm32/stm32f40xxx_alarm.h index f6711e3e36a..f73badd0987 100644 --- a/arch/arm/src/stm32/stm32f40xxx_alarm.h +++ b/arch/arm/src/stm32/stm32f40xxx_alarm.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32f40xxx_alarm.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Neil hancock - delegated to Gregory Nutt Mar 30, 2016 + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c index 3d09b225ba3..7b9b072e87a 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f40xxx_i2c.c @@ -58,6 +58,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index 5ffb11d5884..af42ab9d847 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32l15xx_flash.c b/arch/arm/src/stm32/stm32l15xx_flash.c index 17d4894dc27..ec0fb3edcb7 100644 --- a/arch/arm/src/stm32/stm32l15xx_flash.c +++ b/arch/arm/src/stm32/stm32l15xx_flash.c @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32l15xx_flash.c * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * STM32L1 support: - * Author: Juha Niskanen + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -56,6 +38,7 @@ #include #include #include +#include #include #include "stm32_flash.h" diff --git a/arch/arm/src/stm32/stm32l15xxx_alarm.h b/arch/arm/src/stm32/stm32l15xxx_alarm.h index 6c72cf8d591..e7077b638c1 100644 --- a/arch/arm/src/stm32/stm32l15xxx_alarm.h +++ b/arch/arm/src/stm32/stm32l15xxx_alarm.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32l15xxx_alarm.h * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32l15xxx_rtcc.c b/arch/arm/src/stm32/stm32l15xxx_rtcc.c index 11e558f0da5..c028a1db214 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32l15xxx_rtcc.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32/stm32l15xxx_rtcc.c * - * Copyright (C) 2012-2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs index 7ad308c0421..a1084592963 100644 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ b/arch/arm/src/stm32f0l0g0/Make.defs @@ -32,6 +32,7 @@ CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h index e356e220e80..ceb057d5725 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * Daniel Pereira Volpato + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -611,6 +594,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1030,6 +1014,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM3 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM3 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity (TIM3 only) */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c index a6df97160ef..d0c303f25c5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/stm32f0l0g0/stm32_i2c.c index 96c512bbe3e..80dc64b4a26 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.c @@ -228,6 +228,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/stm32f0l0g0/stm32_irq.c index e522271e54e..7eb3c62a655 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ b/arch/arm/src/stm32f0l0g0/stm32_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/stm32f0l0g0/stm32_pwm.c index d76424d4a55..8efb04b73b9 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.c @@ -551,30 +551,30 @@ static struct stm32_pwmtimer_s g_pwm17dev = static bool stm32pwm_reg_is_32bit(uint8_t timtype, uint32_t offset) { - if (offset == STM32_ATIM_CCMR1_OFFSET || - offset == STM32_ATIM_SMCR_OFFSET || - offset == STM32_ATIM_BDTR_OFFSET) + if (offset == STM32_GTIM_CCMR1_OFFSET || + offset == STM32_GTIM_SMCR_OFFSET || + offset == STM32_GTIM_BDTR_OFFSET) { return true; } if (timtype == TIMTYPE_GENERAL16) { - if (offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_AF1_OFFSET || - offset == STM32_ATIM_TISEL_OFFSET) + if (offset == STM32_GTIM_CCMR2_OFFSET || + offset == STM32_GTIM_AF1_OFFSET || + offset == STM32_GTIM_TISEL_OFFSET) { return true; } } else if (timtype == TIMTYPE_GENERAL32) { - if (offset == STM32_ATIM_CNT_OFFSET || - offset == STM32_ATIM_ARR_OFFSET || - offset == STM32_ATIM_CCR1_OFFSET || - offset == STM32_ATIM_CCR2_OFFSET || - offset == STM32_ATIM_CCR3_OFFSET || - offset == STM32_ATIM_CCR4_OFFSET) + if (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET) { return true; } @@ -751,17 +751,17 @@ static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv, stm32pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); pwminfo(" AF1: %04x TISEL: %04x\n", - stm32pwm_getreg(priv, STM32_GTIM_AF1_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_TISEL_OFFSET)); + stm32pwm_getreg(priv, STM32_ATIM_AF1_OFFSET), + stm32pwm_getreg(priv, STM32_ATIM_TISEL_OFFSET)); } else #endif { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), - stm32pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET), - stm32pwm_getreg(priv, STM32_ATIM_DCR_OFFSET), - stm32pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); + stm32pwm_getreg(priv, STM32_GTIM_RCR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_BDTR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); pwminfo(" AF1: %04x TISEL: %04x\n", stm32pwm_getreg(priv, STM32_GTIM_AF1_OFFSET), stm32pwm_getreg(priv, STM32_GTIM_TISEL_OFFSET)); @@ -1101,7 +1101,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, * preload the RCR into active repetition counter. */ - stm32pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + stm32pwm_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); /* Now set the value of the RCR that will be loaded on the next * update event. @@ -1123,7 +1123,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Generate an update event to reload the prescaler */ - stm32pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + stm32pwm_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); } } else @@ -1131,7 +1131,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, { /* Generate an update event to reload the prescaler (all timers) */ - stm32pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + stm32pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); } /* Handle channel specific setup */ @@ -1199,30 +1199,30 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, switch (mode) { case STM32_CHANMODE_PWM1: - chanmode = ATIM_CCMR_MODE_PWM1; + chanmode = GTIM_CCMR_MODE_PWM1; break; case STM32_CHANMODE_PWM2: - chanmode = ATIM_CCMR_MODE_PWM2; + chanmode = GTIM_CCMR_MODE_PWM2; break; case STM32_CHANMODE_COMBINED1: - chanmode = ATIM_CCMR_MODE_COMBINED1; + chanmode = GTIM_CCMR_MODE_COMBINED1; ocmbit = true; break; case STM32_CHANMODE_COMBINED2: - chanmode = ATIM_CCMR_MODE_COMBINED2; + chanmode = GTIM_CCMR_MODE_COMBINED2; ocmbit = true; break; case STM32_CHANMODE_ASYMMETRIC1: - chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; + chanmode = GTIM_CCMR_MODE_ASYMMETRIC1; ocmbit = true; break; case STM32_CHANMODE_ASYMMETRIC2: - chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; + chanmode = GTIM_CCMR_MODE_ASYMMETRIC2; ocmbit = true; break; @@ -1237,13 +1237,13 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, { /* Set the CCMR1 mode values (leave CCMR2 zero) */ - ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | - (chanmode << ATIM_CCMR1_OC1M_SHIFT) | - ATIM_CCMR1_OC1PE; + ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC1S_SHIFT) | + (chanmode << GTIM_CCMR1_OC1M_SHIFT) | + GTIM_CCMR1_OC1PE; if (ocmbit) { - ocmode1 |= ATIM_CCMR1_OC1M; + ocmode1 |= GTIM_CCMR1_OC1M; } /* Set the duty cycle by writing to the CCR register for this @@ -1256,8 +1256,8 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, * output compare mode. */ - ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE | ATIM_CCMR1_OC1M); + ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_OC1M_MASK | + GTIM_CCMR1_OC1PE | GTIM_CCMR1_OC1M); stm32pwm_output_configure(priv, channel); } break; @@ -1266,13 +1266,13 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, { /* Set the CCMR1 mode values (leave CCMR2 zero) */ - ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | - (chanmode << ATIM_CCMR1_OC2M_SHIFT) | - ATIM_CCMR1_OC2PE; + ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC2S_SHIFT) | + (chanmode << GTIM_CCMR1_OC2M_SHIFT) | + GTIM_CCMR1_OC2PE; if (ocmbit) { - ocmode1 |= ATIM_CCMR1_OC2M; + ocmode1 |= GTIM_CCMR1_OC2M; } /* Set the duty cycle by writing to the CCR register for this @@ -1285,8 +1285,8 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, * output compare mode. */ - ccmr1 &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE | ATIM_CCMR1_OC2M); + ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_OC2M_MASK | + GTIM_CCMR1_OC2PE | GTIM_CCMR1_OC2M); stm32pwm_output_configure(priv, channel); } break; @@ -1309,7 +1309,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, * channel. */ - stm32pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, ccr); + stm32pwm_putreg(priv, STM32_ATIM_CCR3_OFFSET, ccr); /* Reset the Output Compare Mode Bits and set the select * output compare mode. @@ -1338,7 +1338,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, * channel. */ - stm32pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, ccr); + stm32pwm_putreg(priv, STM32_ATIM_CCR4_OFFSET, ccr); /* Reset the Output Compare Mode Bits and set the select * output compare mode. @@ -1371,14 +1371,14 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Get current register state */ - bdtr = stm32pwm_getreg(priv, STM32_GTIM_BDTR_OFFSET); + bdtr = stm32pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); /* Update deadtime */ - bdtr &= ~(GTIM_BDTR_OSSI | GTIM_BDTR_OSSR); - bdtr |= GTIM_BDTR_MOE; + bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); + bdtr |= ATIM_BDTR_MOE; - stm32pwm_putreg(priv, STM32_GTIM_BDTR_OFFSET, bdtr); + stm32pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); } #endif @@ -1386,7 +1386,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET); #if defined(HAVE_CCMR2) - putreg32(ccmr2, priv->base + STM32_GTIM_CCMR2_OFFSET); + putreg32(ccmr2, priv->base + STM32_ATIM_CCMR2_OFFSET); #endif /* Set the ARR Preload Bit */ @@ -1406,7 +1406,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Clear all pending interrupts and enable the update interrupt. */ stm32pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - stm32pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, ATIM_DIER_UIE); + stm32pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.c b/arch/arm/src/stm32f0l0g0/stm32_pwr.c index f45aad72377..29376d2b73e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f0l0g0/stm32_pwr.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Daniel Pereira Volpato + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/stm32_pwr.h index 092e8c6a100..8c322d128e5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.h +++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f0l0g0/stm32_pwr.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Daniel Pereira Volpato + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c index e48bd746b7c..30b14fe287d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c index d085ff8f10a..e248ef3596a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c index 902a72adbc3..6b3cbd6392c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c @@ -60,6 +60,7 @@ #include #include #include +#include #include #include @@ -1284,7 +1285,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/stm32f0l0g0/stm32_tim.c index 993a549830e..a2e081b73ef 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -490,24 +491,24 @@ static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET); - val |= ATIM_EGR_UG; - stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); + val |= GTIM_EGR_UG; + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); - val |= ATIM_CR1_CEN; + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); - val &= ~ATIM_CR1_CEN; - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val &= ~GTIM_CR1_CEN; + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /* Reset timer into system default state, but do not affect output/input @@ -648,7 +649,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) /* PSC_OFFSET is the same for ATIM, BTIM or GTIM */ - stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -718,7 +719,7 @@ static uint32_t stm32_tim_getclock(FAR struct stm32_tim_dev_s *dev) return -EINVAL; } - prescaler = stm32_getreg16(dev, STM32_BTIM_PSC_OFFSET); + prescaler = stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET); clock = freqin / (prescaler + 1); return clock; } @@ -731,13 +732,13 @@ static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, /* ARR_OFFSET is the same for ATIM, BTIM or GTIM */ - stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } static uint32_t stm32_tim_getperiod (FAR struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_BTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev) @@ -752,7 +753,7 @@ static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev) * reset it it result when not TIM2 or TIM5. */ - uint32_t counter = stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); counter &= 0xffff; return counter; } @@ -853,7 +854,7 @@ static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, source); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); } static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) @@ -862,14 +863,14 @@ static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, source, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); } static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) { /* SR_OFFSET is the same for ATIM, BTIM or GTIM */ - stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~source); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); } /**************************************************************************** @@ -880,7 +881,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode) { tmrinfo("Set mode=%d\n", mode); - uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; DEBUGASSERT(dev != NULL); @@ -903,13 +904,13 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_MODE_DOWN: - val |= ATIM_CR1_DIR; + val |= GTIM_CR1_DIR; case STM32_TIM_MODE_UP: break; case STM32_TIM_MODE_UPDOWN: - val |= ATIM_CR1_CENTER1; + val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting * down @@ -918,7 +919,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_MODE_PULSE: - val |= ATIM_CR1_OPM; + val |= GTIM_CR1_OPM; break; default: @@ -929,7 +930,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, /* CR1_OFFSET is the same for ATIM, BTIM or GTIM */ - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); /* Advanced registers require Main Output Enable */ #if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM8) @@ -969,7 +970,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -989,9 +991,9 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_CH_OUTPWM: - ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + - ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -1002,7 +1004,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, if (mode & STM32_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c index 562373be5cd..cd1ec62cc12 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c index 51b72aba9a7..6c75c46dc33 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c +++ b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c index 10e85481c45..d34160d25c4 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c index 7b0a4098d4e..a7944158101 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f0l0g0/stm32g0_pwr.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Daniel Pereira Volpato + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on: arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c - * Authors: Gregory Nutt + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c index 5219fe23b39..b6364411b3d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f0l0g0/stm32g0_rcc.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Mateusz Szafoni - * Daniel Pereira Volpato + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING INANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index b8197440f81..d052860f626 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1734,6 +1734,19 @@ config STM32F7_SYSCFG_IOCOMPENSATION The I/O compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 V. +menu "OTG Configuration" + depends on STM32F7_OTGFS + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + default n + ---help--- + Disables/Enabled the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +endmenu + menu "U[S]ART Configuration" depends on STM32F7_USART @@ -2569,7 +2582,7 @@ endchoice #"RTC clock source" if STM32F7_RTC_LSECLOCK config STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automaticaly boost the LSE oscillator drive capability level until it starts-up" + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" default n ---help--- This will cycle through the values from low to high. To avoid @@ -2647,7 +2660,8 @@ config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED ---help--- This option configures the stm32_dmacapable to not disqualify DMA operations on memory that is not dcache aligned based solely - on the starting addresss and byte count. + on the starting address and byte count. + Use this when ALL buffer extents are known to be aligned, but the the count does not use the complete buffer. diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index b542b844951..ad69a86c85f 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -73,6 +73,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/stm32f7/hardware/stm32_qspi.h b/arch/arm/src/stm32f7/hardware/stm32_qspi.h index a43932b0ebe..aa6e0c998a4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_qspi.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32_qspi.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h index 1cd4fdcc31f..c0065f28131 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h @@ -28,13 +28,196 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# include "stm32f72xx73xx_sdmmc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# include "stm32f74xx77xx_sdmmc.h" +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ + defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) #else # error "Unsupported STM32 F7 part" #endif +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */ +#define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */ +#define STM32_SDMMC_ARG_OFFSET 0x0008 /* SDMMC argument register */ +#define STM32_SDMMC_CMD_OFFSET 0x000c /* SDMMC command register */ +#define STM32_SDMMC_RESPCMD_OFFSET 0x0010 /* SDMMC command response register */ +#define STM32_SDMMC_RESP_OFFSET(n) (0x0010 + 4 * (n)) +#define STM32_SDMMC_RESP1_OFFSET 0x0014 /* SDMMC response 1 register */ +#define STM32_SDMMC_RESP2_OFFSET 0x0018 /* SDMMC response 2 register */ +#define STM32_SDMMC_RESP3_OFFSET 0x001c /* SDMMC response 3 register */ +#define STM32_SDMMC_RESP4_OFFSET 0x0020 /* SDMMC response 4 register */ +#define STM32_SDMMC_DTIMER_OFFSET 0x0024 /* SDMMC data timer register */ +#define STM32_SDMMC_DLEN_OFFSET 0x0028 /* SDMMC data length register */ +#define STM32_SDMMC_DCTRL_OFFSET 0x002c /* SDMMC data control register */ +#define STM32_SDMMC_DCOUNT_OFFSET 0x0030 /* SDMMC data counter register */ +#define STM32_SDMMC_STA_OFFSET 0x0034 /* SDMMC status register */ +#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */ +#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */ +#define STM32_SDMMC_FIFOCNT_OFFSET 0x0048 /* SDMMC FIFO counter register */ +#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */ + +/* Register Bitfield Definitions ********************************************/ + +#define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ +#define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) +# define STM32_SDMMC_POWER_PWRCTRL_OFF (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ +# define STM32_SDMMC_POWER_PWRCTRL_PWRUP (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ +# define STM32_SDMMC_POWER_PWRCTRL_ON (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ + +#define STM32_SDMMC_POWER_RESET (0) /* Reset value */ + +#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ +#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0xff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ +#define STM32_SDMMC_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ +#define STM32_SDMMC_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ +#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ +#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) +# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */ +# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */ +# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */ + +#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */ +#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ + +#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */ + +#define STM32_SDMMC_ARG_RESET (0) /* Reset value */ + +#define STM32_SDMMC_CMD_CMDINDEX_SHIFT (0) +#define STM32_SDMMC_CMD_CMDINDEX_MASK (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT) +#define STM32_SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ +#define STM32_SDMMC_CMD_WAITRESP_MASK (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) +# define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */ +# define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */ +# define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */ + +#define STM32_SDMMC_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ +#define STM32_SDMMC_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ +#define STM32_SDMMC_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ +#define STM32_SDMMC_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ +#define STM32_SDMMC_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ +#define STM32_SDMMC_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ +#define STM32_SDMMC_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ + +#define STM32_SDMMC_CMD_RESET (0) /* Reset value */ + +#define STM32_SDMMC_RESPCMD_SHIFT (0) +#define STM32_SDMMC_RESPCMD_MASK (0x3f << STM32_SDMMC_RESPCMD_SHIFT) + +#define STM32_SDMMC_DTIMER_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DLEN_SHIFT (0) +#define STM32_SDMMC_DLEN_MASK (0x01ffffff << STM32_SDMMC_DLEN_SHIFT) + +#define STM32_SDMMC_DLEN_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ +#define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ +#define STM32_SDMMC_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ +#define STM32_SDMMC_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ +#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ +#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (15 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_1BYTE (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_2BYTES (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_4BYTES (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_8BYTES (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_16BYTES (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_32BYTES (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_64BYTES (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_128BYTES (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_256BYTES (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_512BYTES (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_1KBYTE (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_2KBYTES (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_4KBYTES (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_8KBYTES (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_16KBYTES (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +#define STM32_SDMMC_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ +#define STM32_SDMMC_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ +#define STM32_SDMMC_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ +#define STM32_SDMMC_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ + +#define STM32_SDMMC_DCTRL_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DCOUNT_SHIFT (0) +#define STM32_SDMMC_DCOUNT_MASK (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT) + +#define STM32_SDMMC_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ +#define STM32_SDMMC_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ +#define STM32_SDMMC_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ +#define STM32_SDMMC_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ +#define STM32_SDMMC_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ +#define STM32_SDMMC_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ +#define STM32_SDMMC_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ +#define STM32_SDMMC_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ +#define STM32_SDMMC_STA_DATAEND (1 << 8) /* Bit 8: Data end */ + /* Bit 9: Reserved */ +#define STM32_SDMMC_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ +#define STM32_SDMMC_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ +#define STM32_SDMMC_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ +#define STM32_SDMMC_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ +#define STM32_SDMMC_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ +#define STM32_SDMMC_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ +#define STM32_SDMMC_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ +#define STM32_SDMMC_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ +#define STM32_SDMMC_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ +#define STM32_SDMMC_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ +#define STM32_SDMMC_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ +#define STM32_SDMMC_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ +#define STM32_SDMMC_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ +#define STM32_SDMMC_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ + +#define STM32_SDMMC_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ +#define STM32_SDMMC_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ +#define STM32_SDMMC_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ +#define STM32_SDMMC_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ +#define STM32_SDMMC_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ +#define STM32_SDMMC_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ +#define STM32_SDMMC_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ +#define STM32_SDMMC_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ +#define STM32_SDMMC_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ + /* Bit 9: Reserved */ +#define STM32_SDMMC_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ +#define STM32_SDMMC_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ +#define STM32_SDMMC_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ + +#define STM32_SDMMC_ICR_RESET 0x00c007ff +#define STM32_SDMMC_ICR_STATICFLAGS 0x000005ff + +#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ +#define STM32_SDMMC_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ +#define STM32_SDMMC_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ +#define STM32_SDMMC_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ +#define STM32_SDMMC_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ +#define STM32_SDMMC_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ +#define STM32_SDMMC_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ +#define STM32_SDMMC_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ +#define STM32_SDMMC_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ + /* Bit 9: Reserved */ +#define STM32_SDMMC_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ +#define STM32_SDMMC_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ +#define STM32_SDMMC_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ +#define STM32_SDMMC_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ +#define STM32_SDMMC_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ +#define STM32_SDMMC_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ +#define STM32_SDMMC_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ +#define STM32_SDMMC_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ + +#define STM32_SDMMC_MASK_RESET (0) + +#define STM32_SDMMC_FIFOCNT_SHIFT (0) +#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT) + #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SDMMC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_sdmmc.h deleted file mode 100644 index e4eb3b1d962..00000000000 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_sdmmc.h +++ /dev/null @@ -1,209 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_sdmmc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SDMMC_H -#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SDMMC_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */ -#define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */ -#define STM32_SDMMC_ARG_OFFSET 0x0008 /* SDMMC argument register */ -#define STM32_SDMMC_CMD_OFFSET 0x000c /* SDMMC command register */ -#define STM32_SDMMC_RESPCMD_OFFSET 0x0010 /* SDMMC command response register */ -#define STM32_SDMMC_RESP_OFFSET(n) (0x0010+4*(n)) -#define STM32_SDMMC_RESP1_OFFSET 0x0014 /* SDMMC response 1 register */ -#define STM32_SDMMC_RESP2_OFFSET 0x0018 /* SDMMC response 2 register */ -#define STM32_SDMMC_RESP3_OFFSET 0x001c /* SDMMC response 3 register */ -#define STM32_SDMMC_RESP4_OFFSET 0x0020 /* SDMMC response 4 register */ -#define STM32_SDMMC_DTIMER_OFFSET 0x0024 /* SDMMC data timer register */ -#define STM32_SDMMC_DLEN_OFFSET 0x0028 /* SDMMC data length register */ -#define STM32_SDMMC_DCTRL_OFFSET 0x002c /* SDMMC data control register */ -#define STM32_SDMMC_DCOUNT_OFFSET 0x0030 /* SDMMC data counter register */ -#define STM32_SDMMC_STA_OFFSET 0x0034 /* SDMMC status register */ -#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */ -#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */ -#define STM32_SDMMC_FIFOCNT_OFFSET 0x0048 /* SDMMC FIFO counter register */ -#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */ - -/* Register Bitfield Definitions ********************************************/ - -#define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ -#define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) -# define STM32_SDMMC_POWER_PWRCTRL_OFF (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ -# define STM32_SDMMC_POWER_PWRCTRL_PWRUP (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ -# define STM32_SDMMC_POWER_PWRCTRL_ON (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ - -#define STM32_SDMMC_POWER_RESET (0) /* Reset value */ - -#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ -#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0xff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#define STM32_SDMMC_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ -#define STM32_SDMMC_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ -#define STM32_SDMMC_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ -#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ -#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) -# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */ -# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */ -# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */ - -#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */ -#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ - -#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */ - -#define STM32_SDMMC_ARG_RESET (0) /* Reset value */ - -#define STM32_SDMMC_CMD_CMDINDEX_SHIFT (0) -#define STM32_SDMMC_CMD_CMDINDEX_MASK (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT) -#define STM32_SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ -#define STM32_SDMMC_CMD_WAITRESP_MASK (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) -# define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */ -# define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */ -# define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */ - -#define STM32_SDMMC_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ -#define STM32_SDMMC_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ -#define STM32_SDMMC_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ -#define STM32_SDMMC_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ -#define STM32_SDMMC_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ -#define STM32_SDMMC_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ -#define STM32_SDMMC_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ - -#define STM32_SDMMC_CMD_RESET (0) /* Reset value */ - -#define STM32_SDMMC_RESPCMD_SHIFT (0) -#define STM32_SDMMC_RESPCMD_MASK (0x3f << STM32_SDMMC_RESPCMD_SHIFT) - -#define STM32_SDMMC_DTIMER_RESET (0) /* Reset value */ - -#define STM32_SDMMC_DLEN_SHIFT (0) -#define STM32_SDMMC_DLEN_MASK (0x01ffffff << STM32_SDMMC_DLEN_SHIFT) - -#define STM32_SDMMC_DLEN_RESET (0) /* Reset value */ - -#define STM32_SDMMC_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ -#define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ -#define STM32_SDMMC_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ -#define STM32_SDMMC_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ -#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ -#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (15 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_1BYTE (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_2BYTES (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_4BYTES (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_8BYTES (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_16BYTES (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_32BYTES (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_64BYTES (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_128BYTES (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_256BYTES (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_512BYTES (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_1KBYTE (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_2KBYTES (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_4KBYTES (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_8KBYTES (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_16KBYTES (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -#define STM32_SDMMC_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ -#define STM32_SDMMC_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ -#define STM32_SDMMC_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ -#define STM32_SDMMC_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ - -#define STM32_SDMMC_DCTRL_RESET (0) /* Reset value */ - -#define STM32_SDMMC_DCOUNT_SHIFT (0) -#define STM32_SDMMC_DCOUNT_MASK (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT) - -#define STM32_SDMMC_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ -#define STM32_SDMMC_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ -#define STM32_SDMMC_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ -#define STM32_SDMMC_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ -#define STM32_SDMMC_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ -#define STM32_SDMMC_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ -#define STM32_SDMMC_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ -#define STM32_SDMMC_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ -#define STM32_SDMMC_STA_DATAEND (1 << 8) /* Bit 8: Data end */ -#define STM32_SDMMC_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ -#define STM32_SDMMC_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ -#define STM32_SDMMC_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ -#define STM32_SDMMC_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ -#define STM32_SDMMC_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ -#define STM32_SDMMC_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ -#define STM32_SDMMC_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ -#define STM32_SDMMC_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ -#define STM32_SDMMC_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ -#define STM32_SDMMC_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ -#define STM32_SDMMC_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ -#define STM32_SDMMC_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ -#define STM32_SDMMC_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ -#define STM32_SDMMC_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ -#define STM32_SDMMC_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ - -#define STM32_SDMMC_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ -#define STM32_SDMMC_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ -#define STM32_SDMMC_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ -#define STM32_SDMMC_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ -#define STM32_SDMMC_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ -#define STM32_SDMMC_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ -#define STM32_SDMMC_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ -#define STM32_SDMMC_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ -#define STM32_SDMMC_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ -#define STM32_SDMMC_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ -#define STM32_SDMMC_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ -#define STM32_SDMMC_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ -#define STM32_SDMMC_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ - -#define STM32_SDMMC_ICR_RESET 0x00c007ff -#define STM32_SDMMC_ICR_STATICFLAGS 0x000005ff - -#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ -#define STM32_SDMMC_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ -#define STM32_SDMMC_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ -#define STM32_SDMMC_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ -#define STM32_SDMMC_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ -#define STM32_SDMMC_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ -#define STM32_SDMMC_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ -#define STM32_SDMMC_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ -#define STM32_SDMMC_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ -#define STM32_SDMMC_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ -#define STM32_SDMMC_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ -#define STM32_SDMMC_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ -#define STM32_SDMMC_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ -#define STM32_SDMMC_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ -#define STM32_SDMMC_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ -#define STM32_SDMMC_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ -#define STM32_SDMMC_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ -#define STM32_SDMMC_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ -#define STM32_SDMMC_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ -#define STM32_SDMMC_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ -#define STM32_SDMMC_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ -#define STM32_SDMMC_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ -#define STM32_SDMMC_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ -#define STM32_SDMMC_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ - -#define STM32_SDMMC_MASK_RESET (0) - -#define STM32_SDMMC_FIFOCNT_SHIFT (0) -#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SDMMC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h index 048a4697ec6..a0266da3bb0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h @@ -694,6 +694,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1073,6 +1074,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 46e89338df2..0cc21659e60 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -696,6 +696,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1075,6 +1076,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h deleted file mode 100644 index 1a3d56785c2..00000000000 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h +++ /dev/null @@ -1,209 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SDMMC_H -#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SDMMC_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */ -#define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */ -#define STM32_SDMMC_ARG_OFFSET 0x0008 /* SDMMC argument register */ -#define STM32_SDMMC_CMD_OFFSET 0x000c /* SDMMC command register */ -#define STM32_SDMMC_RESPCMD_OFFSET 0x0010 /* SDMMC command response register */ -#define STM32_SDMMC_RESP_OFFSET(n) (0x0010+4*(n)) -#define STM32_SDMMC_RESP1_OFFSET 0x0014 /* SDMMC response 1 register */ -#define STM32_SDMMC_RESP2_OFFSET 0x0018 /* SDMMC response 2 register */ -#define STM32_SDMMC_RESP3_OFFSET 0x001c /* SDMMC response 3 register */ -#define STM32_SDMMC_RESP4_OFFSET 0x0020 /* SDMMC response 4 register */ -#define STM32_SDMMC_DTIMER_OFFSET 0x0024 /* SDMMC data timer register */ -#define STM32_SDMMC_DLEN_OFFSET 0x0028 /* SDMMC data length register */ -#define STM32_SDMMC_DCTRL_OFFSET 0x002c /* SDMMC data control register */ -#define STM32_SDMMC_DCOUNT_OFFSET 0x0030 /* SDMMC data counter register */ -#define STM32_SDMMC_STA_OFFSET 0x0034 /* SDMMC status register */ -#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */ -#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */ -#define STM32_SDMMC_FIFOCNT_OFFSET 0x0048 /* SDMMC FIFO counter register */ -#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */ - -/* Register Bitfield Definitions ********************************************/ - -#define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ -#define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) -# define STM32_SDMMC_POWER_PWRCTRL_OFF (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ -# define STM32_SDMMC_POWER_PWRCTRL_PWRUP (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ -# define STM32_SDMMC_POWER_PWRCTRL_ON (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ - -#define STM32_SDMMC_POWER_RESET (0) /* Reset value */ - -#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ -#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0xff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#define STM32_SDMMC_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ -#define STM32_SDMMC_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ -#define STM32_SDMMC_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ -#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ -#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) -# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */ -# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */ -# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */ - -#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */ -#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ - -#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */ - -#define STM32_SDMMC_ARG_RESET (0) /* Reset value */ - -#define STM32_SDMMC_CMD_CMDINDEX_SHIFT (0) -#define STM32_SDMMC_CMD_CMDINDEX_MASK (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT) -#define STM32_SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ -#define STM32_SDMMC_CMD_WAITRESP_MASK (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) -# define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */ -# define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */ -# define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */ - -#define STM32_SDMMC_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ -#define STM32_SDMMC_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ -#define STM32_SDMMC_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ -#define STM32_SDMMC_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ -#define STM32_SDMMC_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ -#define STM32_SDMMC_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ -#define STM32_SDMMC_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ - -#define STM32_SDMMC_CMD_RESET (0) /* Reset value */ - -#define STM32_SDMMC_RESPCMD_SHIFT (0) -#define STM32_SDMMC_RESPCMD_MASK (0x3f << STM32_SDMMC_RESPCMD_SHIFT) - -#define STM32_SDMMC_DTIMER_RESET (0) /* Reset value */ - -#define STM32_SDMMC_DLEN_SHIFT (0) -#define STM32_SDMMC_DLEN_MASK (0x01ffffff << STM32_SDMMC_DLEN_SHIFT) - -#define STM32_SDMMC_DLEN_RESET (0) /* Reset value */ - -#define STM32_SDMMC_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ -#define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ -#define STM32_SDMMC_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ -#define STM32_SDMMC_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ -#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ -#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (15 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_1BYTE (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_2BYTES (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_4BYTES (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_8BYTES (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_16BYTES (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_32BYTES (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_64BYTES (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_128BYTES (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_256BYTES (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_512BYTES (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_1KBYTE (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_2KBYTES (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_4KBYTES (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_8KBYTES (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -# define STM32_SDMMC_DCTRL_16KBYTES (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) -#define STM32_SDMMC_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ -#define STM32_SDMMC_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ -#define STM32_SDMMC_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ -#define STM32_SDMMC_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ - -#define STM32_SDMMC_DCTRL_RESET (0) /* Reset value */ - -#define STM32_SDMMC_DCOUNT_SHIFT (0) -#define STM32_SDMMC_DCOUNT_MASK (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT) - -#define STM32_SDMMC_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ -#define STM32_SDMMC_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ -#define STM32_SDMMC_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ -#define STM32_SDMMC_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ -#define STM32_SDMMC_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ -#define STM32_SDMMC_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ -#define STM32_SDMMC_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ -#define STM32_SDMMC_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ -#define STM32_SDMMC_STA_DATAEND (1 << 8) /* Bit 8: Data end */ -#define STM32_SDMMC_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ -#define STM32_SDMMC_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ -#define STM32_SDMMC_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ -#define STM32_SDMMC_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ -#define STM32_SDMMC_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ -#define STM32_SDMMC_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ -#define STM32_SDMMC_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ -#define STM32_SDMMC_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ -#define STM32_SDMMC_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ -#define STM32_SDMMC_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ -#define STM32_SDMMC_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ -#define STM32_SDMMC_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ -#define STM32_SDMMC_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ -#define STM32_SDMMC_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ -#define STM32_SDMMC_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ - -#define STM32_SDMMC_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ -#define STM32_SDMMC_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ -#define STM32_SDMMC_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ -#define STM32_SDMMC_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ -#define STM32_SDMMC_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ -#define STM32_SDMMC_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ -#define STM32_SDMMC_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ -#define STM32_SDMMC_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ -#define STM32_SDMMC_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ -#define STM32_SDMMC_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ -#define STM32_SDMMC_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ -#define STM32_SDMMC_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ -#define STM32_SDMMC_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ - -#define STM32_SDMMC_ICR_RESET 0x00c007ff -#define STM32_SDMMC_ICR_STATICFLAGS 0x000005ff - -#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ -#define STM32_SDMMC_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ -#define STM32_SDMMC_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ -#define STM32_SDMMC_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ -#define STM32_SDMMC_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ -#define STM32_SDMMC_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ -#define STM32_SDMMC_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ -#define STM32_SDMMC_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ -#define STM32_SDMMC_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ -#define STM32_SDMMC_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ -#define STM32_SDMMC_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ -#define STM32_SDMMC_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ -#define STM32_SDMMC_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ -#define STM32_SDMMC_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ -#define STM32_SDMMC_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ -#define STM32_SDMMC_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ -#define STM32_SDMMC_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ -#define STM32_SDMMC_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ -#define STM32_SDMMC_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ -#define STM32_SDMMC_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ -#define STM32_SDMMC_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ -#define STM32_SDMMC_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ -#define STM32_SDMMC_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ -#define STM32_SDMMC_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ - -#define STM32_SDMMC_MASK_RESET (0) - -#define STM32_SDMMC_FIFOCNT_SHIFT (0) -#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SDMMC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h index c3ab91bb699..df392e6f7ed 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Davod Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index c701d1353cf..947ceaffd68 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -702,6 +702,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1093,6 +1094,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c index b609f0a6223..1239ae5c049 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.c +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/stm32f7/stm32_can.c b/arch/arm/src/stm32f7/stm32_can.c index 31f2f80d0d4..727aaaaa3ec 100644 --- a/arch/arm/src/stm32f7/stm32_can.c +++ b/arch/arm/src/stm32f7/stm32_can.c @@ -43,10 +43,12 @@ #include +#include #include #include #include #include +#include #include #include @@ -322,7 +324,7 @@ static uint32_t stm32can_vgetreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - caninfo("[repeats %d more times]\n", count - 3); + caninfo("[repeats %" PRIu32 " more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -334,7 +336,7 @@ static uint32_t stm32can_vgetreg(uint32_t addr) /* Show the register value read */ - caninfo("%08x->%08x\n", addr, val); + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); return val; } @@ -383,7 +385,7 @@ static void stm32can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ - caninfo("%08x<-%08x\n", addr, value); + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); /* Write the value */ @@ -445,16 +447,16 @@ static void stm32can_dumpctrlregs(FAR struct stm32_can_s *priv, /* CAN control and status registers */ - caninfo(" MCR: %08x MSR: %08x TSR: %08x\n", + caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_MCR_OFFSET), getreg32(priv->base + STM32_CAN_MSR_OFFSET), getreg32(priv->base + STM32_CAN_TSR_OFFSET)); - caninfo(" RF0R: %08x RF1R: %08x\n", + caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_RF0R_OFFSET), getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); - caninfo(" IER: %08x ESR: %08x BTR: %08x\n", + caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_IER_OFFSET), getreg32(priv->base + STM32_CAN_ESR_OFFSET), getreg32(priv->base + STM32_CAN_BTR_OFFSET)); @@ -490,31 +492,36 @@ static void stm32can_dumpmbregs(FAR struct stm32_can_s *priv, /* CAN mailbox registers (3 TX and 2 RX) */ - caninfo(" TI0R: %08x TDT0R: %08x TDL0R: %08x TDH0R: %08x\n", + caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" + PRIx32 " TDH0R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_TI0R_OFFSET), getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); - caninfo(" TI1R: %08x TDT1R: %08x TDL1R: %08x TDH1R: %08x\n", + caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" + PRIx32 " TDH1R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_TI1R_OFFSET), getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); - caninfo(" TI2R: %08x TDT2R: %08x TDL2R: %08x TDH2R: %08x\n", + caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" + PRIx32 " TDH2R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_TI2R_OFFSET), getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); - caninfo(" RI0R: %08x RDT0R: %08x RDL0R: %08x RDH0R: %08x\n", + caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" + PRIx32 " RDH0R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_RI0R_OFFSET), getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); - caninfo(" RI1R: %08x RDT1R: %08x RDL1R: %08x RDH1R: %08x\n", + caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" + PRIx32 " RDH1R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_RI1R_OFFSET), getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), @@ -551,7 +558,8 @@ static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv, caninfo("Filter Registers:\n"); } - caninfo(" FMR: %08x FM1R: %08x FS1R: %08x FFA1R: %08x FA1R: %08x\n", + caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" + PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_FMR_OFFSET), getreg32(priv->base + STM32_CAN_FM1R_OFFSET), getreg32(priv->base + STM32_CAN_FS1R_OFFSET), @@ -560,7 +568,7 @@ static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv, for (i = 0; i < CAN_NFILTERS; i++) { - caninfo(" F%dR1: %08x F%dR2: %08x\n", + caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); } @@ -589,7 +597,7 @@ static void stm32can_reset(FAR struct can_dev_s *dev) uint32_t regbit = 0; irqstate_t flags; - caninfo("CAN%d\n", priv->port); + caninfo("CAN%" PRIu8 "\n", priv->port); /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ @@ -615,7 +623,7 @@ static void stm32can_reset(FAR struct can_dev_s *dev) else #endif { - canerr("ERROR: Unsupported port %d\n", priv->port); + canerr("ERROR: Unsupported port %" PRIu8 "\n", priv->port); return; } @@ -658,7 +666,8 @@ static int stm32can_setup(FAR struct can_dev_s *dev) FAR struct stm32_can_s *priv = dev->cd_priv; int ret; - caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n", + caninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 + " TX irq: %" PRIu8 "\n", priv->port, priv->canrx[0], priv->canrx[1], priv->cantx); /* CAN cell initialization */ @@ -666,7 +675,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = stm32can_cellinit(priv); if (ret < 0) { - canerr("ERROR: CAN%d cell initialization failed: %d\n", + canerr("ERROR: CAN%" PRId8 " cell initialization failed: %d\n", priv->port, ret); return ret; } @@ -679,7 +688,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = stm32can_filterinit(priv); if (ret < 0) { - canerr("ERROR: CAN%d filter initialization failed: %d\n", + canerr("ERROR: CAN%" PRIu8 " filter initialization failed: %d\n", priv->port, ret); return ret; } @@ -693,7 +702,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt, dev); if (ret < 0) { - canerr("ERROR: Failed to attach CAN%d RX0 IRQ (%d)", + canerr("ERROR: Failed to attach CAN%" PRIu8 " RX0 IRQ (%" PRIu8 ")", priv->port, priv->canrx[0]); return ret; } @@ -701,7 +710,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt, dev); if (ret < 0) { - canerr("ERROR: Failed to attach CAN%d RX1 IRQ (%d)", + canerr("ERROR: Failed to attach CAN%" PRIu8 " RX1 IRQ (%" PRIu8 ")", priv->port, priv->canrx[1]); return ret; } @@ -709,7 +718,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = irq_attach(priv->cantx, stm32can_txinterrupt, dev); if (ret < 0) { - canerr("ERROR: Failed to attach CAN%d TX IRQ (%d)", + canerr("ERROR: Failed to attach CAN%" PRIu8 " TX IRQ (%" PRIu8 ")", priv->port, priv->cantx); return ret; } @@ -744,7 +753,7 @@ static void stm32can_shutdown(FAR struct can_dev_s *dev) { FAR struct stm32_can_s *priv = dev->cd_priv; - caninfo("CAN%d\n", priv->port); + caninfo("CAN%" PRIu8 "\n", priv->port); /* Disable the RX FIFO 0/1 and TX interrupts */ @@ -782,7 +791,7 @@ static void stm32can_rxint(FAR struct can_dev_s *dev, bool enable) FAR struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; - caninfo("CAN%d enable: %d\n", priv->port, enable); + caninfo("CAN%" PRIu8 " enable: %d\n", priv->port, enable); /* Enable/disable the FIFO 0/1 message pending interrupt */ @@ -818,7 +827,7 @@ static void stm32can_txint(FAR struct can_dev_s *dev, bool enable) FAR struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; - caninfo("CAN%d enable: %d\n", priv->port, enable); + caninfo("CAN%" PRIu8 " enable: %d\n", priv->port, enable); /* Support only disabling the transmit mailbox interrupt */ @@ -850,7 +859,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, FAR struct stm32_can_s *priv; int ret = -ENOTTY; - caninfo("cmd=%04x arg=%" PRIu32 "\n", cmd, arg); + caninfo("cmd=%04x arg=%lu\n", cmd, arg); DEBUGASSERT(dev && dev->cd_priv); priv = dev->cd_priv; @@ -956,7 +965,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } - caninfo("TS1: %"PRId8 " TS2: %" PRId8 " BRP: %" PRIu32 "\n", + caninfo("TS1: %"PRIu8 " TS2: %" PRIu8 " BRP: %" PRIu32 "\n", bt->bt_tseg1, bt->bt_tseg2, brp); /* Configure bit timing. */ @@ -1252,8 +1261,8 @@ static int stm32can_send(FAR struct can_dev_s *dev, int dlc; int txmb; - caninfo("CAN%d ID: %d DLC: %d\n", - priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); + caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", + priv->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); /* Select one empty transmit mailbox */ @@ -1414,7 +1423,7 @@ static bool stm32can_txready(FAR struct can_dev_s *dev) /* Return true if any mailbox is available */ regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); + caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); return stm32can_txmb0empty(regval) || stm32can_txmb1empty(regval) || stm32can_txmb2empty(regval); @@ -1446,7 +1455,7 @@ static bool stm32can_txempty(FAR struct can_dev_s *dev) /* Return true if all mailboxes are available */ regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); + caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); return stm32can_txmb0empty(regval) && stm32can_txmb1empty(regval) && stm32can_txmb2empty(regval); @@ -1752,8 +1761,8 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv) uint32_t ts1; uint32_t ts2; - caninfo("CAN%d PCLK1: %" PRId32 " baud: %" PRId32 "\n", - priv->port, STM32_PCLK1_FREQUENCY, priv->baud); + caninfo("CAN%" PRIu8 " PCLK1: %lu baud: %" PRIu32 "\n", + priv->port, (unsigned long) STM32_PCLK1_FREQUENCY, priv->baud); /* Try to get CAN_BIT_QUANTA quanta in one bit_time. * @@ -1805,7 +1814,7 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv) DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } - caninfo("TS1: %" PRId32 " TS2: %" PRId32 " BRP: %" PRId32 "\n", + caninfo("TS1: %" PRIu32 " TS2: %" PRIu32 " BRP: %" PRIu32 "\n", ts1, ts2, brp); /* Configure bit timing. This also does the following, less obvious @@ -1851,7 +1860,7 @@ static int stm32can_enterinitmode(FAR struct stm32_can_s *priv) uint32_t regval; volatile uint32_t timeout; - caninfo("CAN%d\n", priv->port); + caninfo("CAN%" PRIu8 "\n", priv->port); /* Enter initialization mode */ @@ -1952,7 +1961,7 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv) uint32_t regval; int ret; - caninfo("CAN%d\n", priv->port); + caninfo("CAN%" PRIu8 "\n", priv->port); /* Exit from sleep mode */ @@ -2035,7 +2044,7 @@ static int stm32can_filterinit(FAR struct stm32_can_s *priv) uint32_t regval; uint32_t bitmask; - caninfo("CAN%d filter: %d\n", priv->port, priv->filter); + caninfo("CAN%" PRIu8 " filter: %" PRIu8 "\n", priv->port, priv->filter); /* Get the bitmask associated with the filter used by this CAN block */ @@ -2268,7 +2277,7 @@ FAR struct can_dev_s *stm32_caninitialize(int port) { FAR struct can_dev_s *dev = NULL; - caninfo("CAN%d\n", port); + caninfo("CAN%" PRIu8 "\n", port); /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided * by stm32_clockconfig() early in the reset sequence. diff --git a/arch/arm/src/stm32f7/stm32_capture.c b/arch/arm/src/stm32f7/stm32_capture.c index c3f1b82b576..7b17db99c27 100644 --- a/arch/arm/src/stm32f7/stm32_capture.c +++ b/arch/arm/src/stm32f7/stm32_capture.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -969,9 +970,9 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, /* Shift all CCER bits to corresponding channel */ mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - mask <<= (channel << 2); - regval <<= (channel << 2); - ccer_en_bit <<= (channel << 2); + mask <<= GTIM_CCER_CCXBASE(channel); + regval <<= GTIM_CCER_CCXBASE(channel); + ccer_en_bit <<= GTIM_CCER_CCXBASE(channel); stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval); diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 96a4a9ed55c..03969c64c9c 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -921,8 +922,8 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) ((mend + 1) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0) { dmawarn("stm32_dmacapable:" - " dcache unaligned maddr:0x%08x mend:0x%08x\n", - maddr, mend); + " dcache unaligned maddr:0x%08" PRIxPTR " mend:0x%08" + PRIx32 "\n", maddr, mend); #if !defined(CONFIG_STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c index cba3c767ddc..e6bc1eebb3c 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.c +++ b/arch/arm/src/stm32f7/stm32_dma2d.c @@ -30,6 +30,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index 4713bf181f7..19b187950c8 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index b62c5583e30..fd8bfa62795 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -399,7 +400,6 @@ /* The following bits are set or left zero unconditionally in all modes. * - * ETH_MACFFR_PM Promiscuous mode 0 (disabled) * ETH_MACFFR_HU Hash unicast 0 (perfect dest filtering) * ETH_MACFFR_HM Hash multicast 0 (perfect dest filtering) * ETH_MACFFR_DAIF Destination address 0 (normal) @@ -414,7 +414,11 @@ * ETH_MACFFR_RA Receive all 0 (disabled) */ -#define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE) +#ifdef CONFIG_NET_PROMISCUOUS +# define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE | ETH_MACFFR_PM) +#else +# define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE) +#endif /* Clear the MACFCR bits that will be setup during MAC initialization (or * that are cleared unconditionally). Per the reference manual, all reserved diff --git a/arch/arm/src/stm32f7/stm32_exti_alarm.c b/arch/arm/src/stm32f7/stm32_exti_alarm.c index c957a01e684..53de0bd3034 100644 --- a/arch/arm/src/stm32f7/stm32_exti_alarm.c +++ b/arch/arm/src/stm32f7/stm32_exti_alarm.c @@ -1,41 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_exti_alarm.c * - * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * This file derives from similar logic for the STM32 F1: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Diego Sanchez - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32_exti_wakeup.c b/arch/arm/src/stm32f7/stm32_exti_wakeup.c index 0f12fb54ba2..10e13301433 100644 --- a/arch/arm/src/stm32f7/stm32_exti_wakeup.c +++ b/arch/arm/src/stm32f7/stm32_exti_wakeup.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_exti_wakeup.c * - * Copyright (C) 2009, 2012, 2017-2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32_fmc.c b/arch/arm/src/stm32f7/stm32_fmc.c index 20b53978538..c9855aec754 100644 --- a/arch/arm/src/stm32f7/stm32_fmc.c +++ b/arch/arm/src/stm32f7/stm32_fmc.c @@ -26,6 +26,7 @@ #if defined(CONFIG_STM32F7_FMC) +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index 6b8b90a7411..00573864e1a 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -240,6 +240,7 @@ #include #include #include +#include #include #include @@ -927,8 +928,8 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: 0x%08x\n", - priv->intstate, (long)elapsed, (long)timeout, priv->status); + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: 0x%08" PRIx32 + "\n", priv->intstate, (long)elapsed, (long)timeout, priv->status); /* Set the interrupt state back to IDLE */ diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index e15997a134a..04d403c8df1 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index b89f429bc25..19b58d77611 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -46,6 +46,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index c7191572c19..22a2e49cfe2 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -5726,7 +5727,11 @@ void arm_usbinitialize(void) stm32_configgpio(GPIO_OTG_DM); stm32_configgpio(GPIO_OTG_DP); - stm32_configgpio(GPIO_OTG_ID); /* Only needed for OTG */ + + /* Only needed for OTG */ +# ifndef CONFIG_OTG_ID_GPIO_DISABLE + stm32_configgpio(GPIO_OTG_ID); +# endif /* SOF output pin configuration is configurable. */ diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 15aa84736a1..23e0b6c62ff 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_pmsleep.c b/arch/arm/src/stm32f7/stm32_pmsleep.c index d6221877910..d5776a69b0d 100644 --- a/arch/arm/src/stm32f7/stm32_pmsleep.c +++ b/arch/arm/src/stm32f7/stm32_pmsleep.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_pmsleep.c * - * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index bca3c8a6115..a0c8cd3de16 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -1345,7 +1345,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Generate an update event to reload the prescaler */ - pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + pwm_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); } } else @@ -1353,7 +1353,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, { /* Generate an update event to reload the prescaler (all timers) */ - pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); } /* Handle channel specific setup */ @@ -1419,11 +1419,11 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, switch (mode) { case STM32_CHANMODE_PWM1: - chanmode = ATIM_CCMR_MODE_PWM1; + chanmode = GTIM_CCMR_MODE_PWM1; break; case STM32_CHANMODE_PWM2: - chanmode = ATIM_CCMR_MODE_PWM2; + chanmode = GTIM_CCMR_MODE_PWM2; break; default: @@ -1437,13 +1437,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, { /* Select the CCER enable bit for this channel */ - ccenable |= ATIM_CCER_CC1E; + ccenable |= GTIM_CCER_CC1E; /* Set the CCMR1 mode values (leave CCMR2 zero) */ - ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | - (chanmode << ATIM_CCMR1_OC1M_SHIFT) | - ATIM_CCMR1_OC1PE; + ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC1S_SHIFT) | + (chanmode << GTIM_CCMR1_OC1M_SHIFT) | + GTIM_CCMR1_OC1PE; /* Set the duty cycle by writing to the CCR register for this * channel @@ -1457,13 +1457,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, { /* Select the CCER enable bit for this channel */ - ccenable |= ATIM_CCER_CC2E; + ccenable |= GTIM_CCER_CC2E; /* Set the CCMR1 mode values (leave CCMR2 zero) */ - ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | - (chanmode << ATIM_CCMR1_OC2M_SHIFT) | - ATIM_CCMR1_OC2PE; + ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC2S_SHIFT) | + (chanmode << GTIM_CCMR1_OC2M_SHIFT) | + GTIM_CCMR1_OC2PE; /* Set the duty cycle by writing to the CCR register for this * channel @@ -1477,13 +1477,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, { /* Select the CCER enable bit for this channel */ - ccenable |= ATIM_CCER_CC3E; + ccenable |= GTIM_CCER_CC3E; /* Set the CCMR2 mode values (leave CCMR1 zero) */ - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | - (chanmode << ATIM_CCMR2_OC3M_SHIFT) | - ATIM_CCMR2_OC3PE; + ocmode2 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR2_CC3S_SHIFT) | + (chanmode << GTIM_CCMR2_OC3M_SHIFT) | + GTIM_CCMR2_OC3PE; /* Set the duty cycle by writing to the CCR register for this * channel @@ -1497,13 +1497,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, { /* Select the CCER enable bit for this channel */ - ccenable |= ATIM_CCER_CC4E; + ccenable |= GTIM_CCER_CC4E; /* Set the CCMR2 mode values (leave CCMR1 zero) */ - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | - (chanmode << ATIM_CCMR2_OC4M_SHIFT) | - ATIM_CCMR2_OC4PE; + ocmode2 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR2_CC4S_SHIFT) | + (chanmode << GTIM_CCMR2_OC4M_SHIFT) | + GTIM_CCMR2_OC4PE; /* Set the duty cycle by writing to the CCR register for this * channel @@ -1535,10 +1535,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, * mode */ - ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | - ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); - ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE | - ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE); + ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_OC1M_MASK | GTIM_CCMR1_OC1PE | + GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_OC2M_MASK | GTIM_CCMR1_OC2PE); + ccmr2 &= ~(GTIM_CCMR2_CC3S_MASK | GTIM_CCMR2_OC3M_MASK | GTIM_CCMR2_OC3PE | + GTIM_CCMR2_CC4S_MASK | GTIM_CCMR2_OC4M_MASK | GTIM_CCMR2_OC4PE); ccmr1 |= ocmode1; ccmr2 |= ocmode2; @@ -1546,13 +1546,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, * polarity) */ - ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P | - ATIM_CCER_CC4P); + ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC2P | GTIM_CCER_CC3P | + GTIM_CCER_CC4P); /* Enable the output state of the selected channels */ - ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | ATIM_CCER_CC3E | - ATIM_CCER_CC4E); + ccer &= ~(GTIM_CCER_CC1E | GTIM_CCER_CC2E | GTIM_CCER_CC3E | + GTIM_CCER_CC4E); ccer |= ccenable; /* Some special setup for advanced timers */ @@ -1621,7 +1621,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Clear all pending interrupts and enable the update interrupt. */ pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, ATIM_DIER_UIE); + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ diff --git a/arch/arm/src/stm32f7/stm32_pwr.c b/arch/arm/src/stm32f7/stm32_pwr.c index d4703d20c4f..0579e205b79 100644 --- a/arch/arm/src/stm32f7/stm32_pwr.c +++ b/arch/arm/src/stm32f7/stm32_pwr.c @@ -27,6 +27,7 @@ #include #include +#include #include #include "arm_arch.h" diff --git a/arch/arm/src/stm32f7/stm32_qencoder.c b/arch/arm/src/stm32f7/stm32_qencoder.c index dfafe1d211b..b8238da6bb2 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.c +++ b/arch/arm/src/stm32f7/stm32_qencoder.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_qencoder.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index c2279821f3e..129e8a85a4a 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_qspi.c * - * Copyright (C) 2016-2017, 2019 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index d63a27fd91c..bf3c967128a 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_qspi.h * - * Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c index c38e5e2b4ec..6ec1cb56bef 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.c +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c index 4edfc6ff4dd..f78db23167d 100644 --- a/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index e4d28aef7ba..920a02a9f03 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -49,6 +49,7 @@ #include "stm32_dtcm.h" #include "stm32_dma.h" #include "stm32_gpio.h" +#include "stm32_rcc.h" #include "stm32_sdmmc.h" #if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) @@ -130,6 +131,11 @@ # else # undef CONFIG_STM32F7_SDMMC1_DMAPRIO # endif +# if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ +# define STM32_SDMMC1_CLK UINT32_C(48000000) +# else +# define STM32_SDMMC1_CLK STM32_SYSCLK_FREQUENCY +# endif #endif #ifdef CONFIG_STM32F7_SDMMC2 @@ -143,6 +149,11 @@ # else # undef CONFIG_STM32F7_SDMMC2_DMAPRIO # endif +# if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ +# define STM32_SDMMC2_CLK UINT32_C(48000000) +# else +# define STM32_SDMMC2_CLK STM32_SYSCLK_FREQUENCY +# endif #endif #undef HAVE_SDMMC_SDIO_MODE @@ -214,9 +225,9 @@ #define SDMMC_CMDTIMEOUT (100000) #define SDMMC_LONGTIMEOUT (0x7fffffff) -/* Big DTIMER setting */ +/* DTIMER setting */ -#define SDMMC_DTIMER_DATATIMEOUT (0x003d0900) /* 250 ms @ 16 MHz */ +#define SDMMC_DTIMER_DATATIMEOUT_MS 250 /* DMA channel/stream configuration register settings. The following * must be selected. The DMA driver will select the remaining fields. @@ -269,27 +280,23 @@ STM32_SDMMC_MASK_DTIMEOUTIE | \ STM32_SDMMC_MASK_DATAENDIE | \ STM32_SDMMC_MASK_RXOVERRIE | \ - STM32_SDMMC_MASK_RXFIFOHFIE | \ - STM32_SDMMC_MASK_STBITERRIE) + STM32_SDMMC_MASK_RXFIFOHFIE) #define STM32_SDMMC_SEND_MASK (STM32_SDMMC_MASK_DCRCFAILIE | \ STM32_SDMMC_MASK_DTIMEOUTIE | \ STM32_SDMMC_MASK_DATAENDIE | \ STM32_SDMMC_MASK_TXUNDERRIE | \ - STM32_SDMMC_MASK_TXFIFOHEIE | \ - STM32_SDMMC_MASK_STBITERRIE) + STM32_SDMMC_MASK_TXFIFOHEIE) #define STM32_SDMMC_DMARECV_MASK (STM32_SDMMC_MASK_DCRCFAILIE | \ STM32_SDMMC_MASK_DTIMEOUTIE | \ STM32_SDMMC_MASK_DATAENDIE | \ - STM32_SDMMC_MASK_RXOVERRIE | \ - STM32_SDMMC_MASK_STBITERRIE) + STM32_SDMMC_MASK_RXOVERRIE) #define STM32_SDMMC_DMASEND_MASK (STM32_SDMMC_MASK_DCRCFAILIE | \ STM32_SDMMC_MASK_DTIMEOUTIE | \ STM32_SDMMC_MASK_DATAENDIE | \ - STM32_SDMMC_MASK_TXUNDERRIE | \ - STM32_SDMMC_MASK_STBITERRIE) + STM32_SDMMC_MASK_TXUNDERRIE) /* Event waiting interrupt mask bits */ @@ -322,7 +329,6 @@ STM32_SDMMC_ICR_DTIMEOUTC | \ STM32_SDMMC_ICR_RXOVERRC | \ STM32_SDMMC_ICR_TXUNDERRC | \ - STM32_SDMMC_ICR_STBITERRC | \ STM32_SDMMC_ICR_DBCKENDC) #define STM32_SDMMC_WAITALL_ICR (STM32_SDMMC_CMDDONE_ICR | \ @@ -368,6 +374,7 @@ struct stm32_dev_s uint32_t base; int nirq; + uint32_t sdio_clk; #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif @@ -625,6 +632,7 @@ struct stm32_dev_s g_sdmmcdev1 = }, .base = STM32_SDMMC1_BASE, .nirq = STM32_IRQ_SDMMC1, + .sdio_clk = STM32_SDMMC1_CLK, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0), #endif @@ -684,6 +692,7 @@ struct stm32_dev_s g_sdmmcdev2 = }, .base = STM32_SDMMC2_BASE, .nirq = STM32_IRQ_SDMMC2, + .sdio_clk = STM32_SDMMC2_CLK, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0), #endif @@ -846,13 +855,9 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, flags = enter_critical_section(); -#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE - if ((waitmask & SDIOWAIT_WRCOMPLETE) != 0) +#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) + if ((waitevents & SDIOWAIT_WRCOMPLETE) != 0) { - /* Do not use this in STM32_SDMMC_MASK register */ - - waitmask &= ~SDIOWAIT_WRCOMPLETE; - pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK | \ GPIO_PUPD_MASK); pinset |= (GPIO_INPUT | GPIO_EXTI); @@ -1223,9 +1228,26 @@ static uint8_t stm32_log2(uint16_t value) static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, uint32_t dlen, uint32_t dctrl) { - uint32_t regval = 0; + uint32_t clkdiv; + uint32_t regval; + uint32_t sdio_clk = priv->sdio_clk; - /* Enable data path */ + /* Enable data path using a timeout scaled to the SD_CLOCK (the card + * clock). + */ + + regval = sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET); + clkdiv = (regval & STM32_SDMMC_CLKCR_CLKDIV_MASK) >> + STM32_SDMMC_CLKCR_CLKDIV_SHIFT; + + if ((regval & STM32_SDMMC_CLKCR_BYPASS) == 0) + { + sdio_clk = sdio_clk / (2 + clkdiv); + } + + /* Convert Timeout in Ms to SD_CLK counts */ + + timeout = timeout * (sdio_clk / 1000); sdmmc_putreg32(priv, timeout, STM32_SDMMC_DTIMER_OFFSET); /* Set DTIMER */ sdmmc_putreg32(priv, dlen, STM32_SDMMC_DLEN_OFFSET); /* Set DLEN */ @@ -1271,8 +1293,11 @@ static void stm32_datadisable(struct stm32_dev_s *priv) /* Reset DTIMER */ - sdmmc_putreg32(priv, SDMMC_DTIMER_DATATIMEOUT, STM32_SDMMC_DTIMER_OFFSET); - sdmmc_putreg32(priv, 0, STM32_SDMMC_DLEN_OFFSET); /* Reset DLEN */ + sdmmc_putreg32(priv, UINT32_MAX, STM32_SDMMC_DTIMER_OFFSET); + + /* Reset DLEN */ + + sdmmc_putreg32(priv, 0, STM32_SDMMC_DLEN_OFFSET); /* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */ @@ -1438,8 +1463,13 @@ static void stm32_eventtimeout(wdparm_t arg) { /* Yes.. wake up any waiting threads */ +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + stm32_endwait(priv, SDIOWAIT_TIMEOUT | + (priv->waitevents & SDIOWAIT_WRCOMPLETE)); +#else stm32_endwait(priv, SDIOWAIT_TIMEOUT); - mcerr("Timeout: remaining: %d\n", priv->remaining); +#endif + mcerr("Timeout: remaining: %zu\n", priv->remaining); } } @@ -1745,18 +1775,6 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } - - /* Handle start bit error */ - - else if ((pending & STM32_SDMMC_STA_STBITERR) != 0) - { - /* Terminate the transfer with an error */ - - mcerr("ERROR: Start bit, remaining: %d\n", - priv->remaining); - stm32_endtransfer(priv, - SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); - } } /* Handle wait events *************************************************/ @@ -2254,8 +2272,8 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, dblksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT; - stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((nbytes + 511) >> 9), - nbytes, dblksize | STM32_SDMMC_DCTRL_DTDIR); + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT_MS, nbytes, + dblksize | STM32_SDMMC_DCTRL_DTDIR); /* And enable interrupts */ @@ -2310,8 +2328,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const dblksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT; - stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((nbytes + 511) >> 9), - nbytes, dblksize); + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT_MS, nbytes, dblksize); /* Enable TX interrupts */ @@ -2510,7 +2527,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) { - mcerr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); ret = -EINVAL; } else @@ -2538,7 +2555,8 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((uint8_t)(respcmd & STM32_SDMMC_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) { - mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); + mcerr("ERROR: RESCMD=%02" PRIx32 " CMD=%08" PRIx32 "\n", + respcmd, cmd); ret = -EINVAL; } } @@ -2576,7 +2594,7 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - mcerr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); ret = -EINVAL; } else @@ -2706,7 +2724,9 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev, #if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) if ((eventset & SDIOWAIT_WRCOMPLETE) != 0) { - waitmask = SDIOWAIT_WRCOMPLETE; + /* eventset carries this */ + + waitmask = 0; } else #endif @@ -2817,11 +2837,11 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev) if ((priv->waitevents & SDIOWAIT_WRCOMPLETE) != 0) { /* Atomically read pin to see if ready (true) and determine if ISR - * fired. If Pin is ready and if ISR did NOT fire end the wait here. + * fired. If Pin is ready and if ISR did NOT fire end the wait here. */ if (stm32_gpioread(priv->d0_gpio) && - (priv->wkupevent & SDIOWAIT_WRCOMPLETE) == 0) + (priv->wkupevent & SDIOWAIT_WRCOMPLETE) == 0) { stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); } @@ -2909,7 +2929,7 @@ static void stm32_callbackenable(FAR struct sdio_dev_s *dev, { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - mcinfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02" PRIx8 "\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -3060,8 +3080,8 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, dblksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT; - stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((buflen + 511) >> 9), - buflen, dblksize | STM32_SDMMC_DCTRL_DTDIR); + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT_MS, buflen, + dblksize | STM32_SDMMC_DCTRL_DTDIR); /* Configure the RX DMA */ @@ -3164,8 +3184,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, dblksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT; - stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((buflen + 511) >> 9), - buflen, dblksize); + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT_MS, buflen, dblksize); /* Configure the TX DMA */ diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index 6091a1807d4..6b02a86a9b4 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -3641,10 +3642,10 @@ void arm_serialinit(void) #if !defined(SERIAL_HAVE_ONLY_DMA) # if defined(SERIAL_HAVE_RXDMA) - UNUSED(g_uart_rxdma_ops); + UNUSED(&g_uart_rxdma_ops); # endif # if defined(SERIAL_HAVE_TXDMA) - UNUSED(g_uart_txdma_ops); + UNUSED(&g_uart_txdma_ops); # endif #endif diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index f5433199c0e..91665b8461f 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include @@ -1661,7 +1662,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into diff --git a/arch/arm/src/stm32f7/stm32_start.c b/arch/arm/src/stm32f7/stm32_start.c index 280771f0488..f5753f1b84c 100644 --- a/arch/arm/src/stm32f7/stm32_start.c +++ b/arch/arm/src/stm32f7/stm32_start.c @@ -86,10 +86,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void stm32_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Private Functions @@ -241,47 +237,6 @@ static inline void stm32_tcmenable(void) #endif } -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -383,17 +338,9 @@ void __start(void) /* Then start NuttX */ -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/stm32f7/stm32_tickless.c b/arch/arm/src/stm32f7/stm32_tickless.c index ddfd7cdcf16..8e127788f60 100644 --- a/arch/arm/src/stm32f7/stm32_tickless.c +++ b/arch/arm/src/stm32f7/stm32_tickless.c @@ -113,13 +113,13 @@ #endif #if CONFIG_STM32F7_TICKLESS_CHANNEL == 1 -#define DIER_CAPT_IE ATIM_DIER_CC1IE +#define DIER_CAPT_IE GTIM_DIER_CC1IE #elif CONFIG_STM32F7_TICKLESS_CHANNEL == 2 -#define DIER_CAPT_IE ATIM_DIER_CC2IE +#define DIER_CAPT_IE GTIM_DIER_CC2IE #elif CONFIG_STM32F7_TICKLESS_CHANNEL == 3 -#define DIER_CAPT_IE ATIM_DIER_CC3IE +#define DIER_CAPT_IE GTIM_DIER_CC3IE #elif CONFIG_STM32F7_TICKLESS_CHANNEL == 4 -#define DIER_CAPT_IE ATIM_DIER_CC4IE +#define DIER_CAPT_IE GTIM_DIER_CC4IE #endif /**************************************************************************** @@ -132,9 +132,6 @@ struct stm32_tickless_s uint8_t channel; /* The timer channel to use for intervals */ FAR struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ uint32_t frequency; -#ifdef CONFIG_CLOCK_TIMEKEEPING - uint64_t counter_mask; -#endif uint32_t overflow; /* Timer counter overflow */ volatile bool pending; /* True: pending task */ uint32_t period; /* Interval period */ @@ -251,7 +248,8 @@ static int stm32_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -267,11 +265,11 @@ static int stm32_tickless_setchannel(uint8_t channel) * disabled. */ - ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT); + ccmr_val = (GTIM_CCMR_MODE_FRZN << GTIM_CCMR1_OC1M_SHIFT); /* Set polarity */ - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); /* Define its position (shift) and get register offset */ @@ -354,7 +352,7 @@ static void stm32_timing_handler(void) { g_tickless.overflow++; - STM32_TIM_ACKINT(g_tickless.tch, ATIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); } /**************************************************************************** @@ -376,7 +374,7 @@ static int stm32_tickless_handler(int irq, void *context, void *arg) { int interrupt_flags = stm32_tickless_getint(); - if (interrupt_flags & ATIM_SR_UIF) + if (interrupt_flags & GTIM_SR_UIF) { stm32_timing_handler(); } @@ -587,13 +585,6 @@ void up_timer_initialize(void) STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); -#ifdef CONFIG_CLOCK_TIMEKEEPING - - /* Should this be changed to 0xffff because we use 16 bit timers? */ - - g_tickless.counter_mask = 0xffffffffull; -#endif - /* Set up to receive the callback when the counter overflow occurs */ STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0); @@ -694,7 +685,7 @@ int up_timer_gettime(FAR struct timespec *ts) overflow = g_tickless.overflow; counter = STM32_TIM_GETCOUNTER(g_tickless.tch); - pending = STM32_TIM_CHECKINT(g_tickless.tch, ATIM_SR_UIF); + pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); verify = STM32_TIM_GETCOUNTER(g_tickless.tch); /* If an interrupt was pending before we re-enabled interrupts, @@ -703,7 +694,7 @@ int up_timer_gettime(FAR struct timespec *ts) if (pending) { - STM32_TIM_ACKINT(g_tickless.tch, ATIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -789,7 +780,11 @@ int up_timer_getcounter(FAR uint64_t *cycles) void up_timer_getmask(FAR uint64_t *mask) { DEBUGASSERT(mask != NULL); - *mask = g_tickless.counter_mask; +#ifdef HAVE_32BIT_TICKLESS + *mask = UINT32_MAX; +#else + *mask = UINT16_MAX; +#endif } #endif /* CONFIG_CLOCK_TIMEKEEPING */ diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index 0b6d1647e44..4016e7a4484 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -289,24 +290,24 @@ static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET); - val |= ATIM_EGR_UG; - stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); + val |= GTIM_EGR_UG; + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); - val |= ATIM_CR1_CEN; + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); - val &= ~ATIM_CR1_CEN; - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val &= ~GTIM_CR1_CEN; + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -351,8 +352,8 @@ static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET); + stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : + (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); } /**************************************************************************** @@ -366,11 +367,11 @@ static void stm32_tim_setcounter(FAR struct stm32_tim_dev_s *dev, if (stm32_tim_getwidth(dev) > 16) { - stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count); + stm32_putreg32(dev, STM32_GTIM_CNT_OFFSET, count); } else { - stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count); + stm32_putreg16(dev, STM32_GTIM_CNT_OFFSET, (uint16_t)count); } } @@ -525,7 +526,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -535,7 +536,7 @@ static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, @@ -643,24 +644,24 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & source) ? 1 : 0; } static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~source); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); } /**************************************************************************** @@ -670,7 +671,7 @@ static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode) { - uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; DEBUGASSERT(dev != NULL); @@ -693,7 +694,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_MODE_DOWN: - val |= ATIM_CR1_DIR; + val |= GTIM_CR1_DIR; case STM32_TIM_MODE_UP: break; @@ -704,11 +705,11 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, * Interrupts are generated on compare, when counting down */ - val |= ATIM_CR1_CENTER1; + val |= GTIM_CR1_CENTER1; break; case STM32_TIM_MODE_PULSE: - val |= ATIM_CR1_OPM; + val |= GTIM_CR1_OPM; break; default: @@ -716,7 +717,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); /* Advanced registers require Main Output Enable */ @@ -750,7 +751,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -770,15 +772,15 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_CH_OUTPWM: - ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + - ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; case STM32_TIM_CH_OUTTOGGLE: - ccmr_val = (ATIM_CCMR_MODE_OCREFTOG << ATIM_CCMR1_OC1M_SHIFT) + - ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -789,7 +791,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, if (mode & STM32_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index d724d4f25bf..589488ee78e 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -211,7 +211,9 @@ static inline void rcc_enableahb1(void) #endif #ifdef CONFIG_STM32F7_OTGFSHS -#if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || + defined(CONFIG_STM32F7_EXTERNAL_ULPI) + /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index 86438011124..e288291d888 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -215,12 +215,13 @@ static inline void rcc_enableahb1(void) #endif #ifdef CONFIG_STM32F7_OTGFSHS - #if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ + defined(CONFIG_STM32F7_EXTERNAL_ULPI) + /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); #else - /* Enable only clocking for USB OTG HS */ regval |= RCC_AHB1ENR_OTGHSEN; diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index ed1bc937138..32f2a62eb6a 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -221,7 +221,9 @@ static inline void rcc_enableahb1(void) #endif #ifdef CONFIG_STM32F7_OTGFSHS -#ifdef BOARD_ENABLE_USBOTG_HSULPI +# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ + defined(CONFIG_STM32F7_EXTERNAL_ULPI) + /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 64d518fc035..29a9e858180 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -843,6 +843,19 @@ config STM32H7_I2CTIMEOTICKS endmenu # "I2C Configuration" +menu "OTG Configuration" + depends on STM32H7_OTGFS + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + default n + ---help--- + Disables/Enabled the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +endmenu + menu "SPI Configuration" depends on STM32H7_SPI @@ -1549,7 +1562,7 @@ endchoice #"RTC clock source" if STM32H7_RTC_LSECLOCK config STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automaticaly boost the LSE oscillator drive capability level until it starts-up" + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" default n ---help--- This will cycle through the correct* values from low to high. To avoid @@ -1787,7 +1800,8 @@ config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED ---help--- This option configures the stm32_dmacapable to not disqualify DMA operations on memory that is not dcache aligned based solely - on the starting addresss and byte count. + on the starting address and byte count. + Use this when ALL buffer extents are known to be aligned, but the the count does not use the complete buffer. @@ -1977,7 +1991,7 @@ config STM32H7_TIM1_CHANNEL5 bool "TIM1 Channel 5 (internal)" default n ---help--- - Enables channel 5 (no available externaly) + Enables channel 5 (not available externally) if STM32H7_TIM1_CHANNEL5 @@ -2000,7 +2014,7 @@ config STM32H7_TIM1_CHANNEL6 bool "TIM1 Channel 6 (internal)" default n ---help--- - Enables channel 6 (no available externaly) + Enables channel 6 (not available externally) if STM32H7_TIM1_CHANNEL6 @@ -2980,7 +2994,7 @@ config STM32H7_TIM8_CHANNEL5 bool "TIM8 Channel 5 (internal)" default n ---help--- - Enables channel 5 (no available externaly) + Enables channel 5 (not available externally) if STM32H7_TIM8_CHANNEL5 @@ -3003,7 +3017,7 @@ config STM32H7_TIM8_CHANNEL6 bool "TIM8 Channel 6 (internal)" default n ---help--- - Enables channel 6 (no available externaly) + Enables channel 6 (not available externally) if STM32H7_TIM8_CHANNEL6 diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index a7090cbfa90..6b6801bbcc0 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -72,6 +72,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_adc.h b/arch/arm/src/stm32h7/hardware/stm32_adc.h index 0136afe86cb..3d4e3cfbd52 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_adc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_adc.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/hardware/stm32_adc.h * - * Copyright (C) 2017,2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Juha Niskanen - * David Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h index 9ac891a7d04..4abdd0f4c91 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h @@ -196,11 +196,11 @@ /* Ethernet MAC frame filter register */ -#define ETH_MACPFR_PR (1 << 0) /* Bit 0: Promiscuous mode */ +#define ETH_MACPFR_PM (1 << 0) /* Bit 0: Promiscuous mode */ #define ETH_MACPFR_HUC (1 << 1) /* Bit 1: Hash unicast */ #define ETH_MACPFR_HMC (1 << 2) /* Bit 2: Hash multicast */ #define ETH_MACPFR_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */ -#define ETH_MACPFR_PM (1 << 4) /* Bit 4: Pass all multicast */ +#define ETH_MACPFR_PAM (1 << 4) /* Bit 4: Pass all multicast */ #define ETH_MACPFR_DBF (1 << 5) /* Bit 5: Disable broadcast packets */ #define ETH_MACPFR_PCF_SHIFT (6) /* Bits 6-7: Pass control frames */ #define ETH_MACPFR_PCF_MASK (3 << ETH_MACPFR_PCF_SHIFT) diff --git a/arch/arm/src/stm32h7/hardware/stm32_qspi.h b/arch/arm/src/stm32h7/hardware/stm32_qspi.h index ba48573e091..8a1ccf6ff8e 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_qspi.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/hardware/stm32_qspi.h * - * Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_sdmmc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_sdmmc.h index 41ea2130a68..71a96ac77b8 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_sdmmc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_sdmmc.h @@ -119,10 +119,10 @@ #define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ #define STM32_SDMMC_DCTRL_DTMODE_SHIFT (2) /* Bits 2-3: Data transfer mode */ #define STM32_SDMMC_DCTRL_DTMODE_MASK (3 << STM32_SDMMC_DCTRL_DTMODE_SHIFT) -# define STM32_SDMMC_DCTRL_DTMODE_END (0 << STM32_SDMMC_DCTRL_DTMODE_SHIFT) +# define STM32_SDMMC_DCTRL_DTMODE_BLOCK (0 << STM32_SDMMC_DCTRL_DTMODE_SHIFT) # define STM32_SDMMC_DCTRL_DTMODE_SDIO (1 << STM32_SDMMC_DCTRL_DTMODE_SHIFT) # define STM32_SDMMC_DCTRL_DTMODE_EMMC (2 << STM32_SDMMC_DCTRL_DTMODE_SHIFT) -# define STM32_SDMMC_DCTRL_DTMODE_BLOCK (3 << STM32_SDMMC_DCTRL_DTMODE_SHIFT) +# define STM32_SDMMC_DCTRL_DTMODE_BLKSTOP (3 << STM32_SDMMC_DCTRL_DTMODE_SHIFT) #define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ #define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (0xf << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index 4609111ebaf..166714da2b5 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -1389,6 +1389,10 @@ static int adc_setup(FAR struct adc_dev_s *dev) clrbits |= ADC_CFGR_EXTEN_MASK; setbits |= ADC_CFGR_EXTEN_NONE; + /* Set overrun mode to preserve the data register */ + + clrbits |= ADC_CFGR_OVRMOD; + /* Set CFGR configuration */ adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); @@ -1551,9 +1555,9 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); if (enable) { - /* Enable end of conversion interrupt */ + /* Enable end of conversion and overrun interrupts */ - regval |= ADC_INT_EOC; + regval |= ADC_INT_EOC | ADC_INT_OVR; } else { @@ -1833,7 +1837,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev, uint32_t adcisr) FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; int32_t value; - /* Identifies the interruption AWD or OVR */ + /* Identifies the AWD interrupt */ if ((adcisr & ADC_INT_AWD1) != 0) { @@ -1848,50 +1852,87 @@ static int adc_interrupt(FAR struct adc_dev_s *dev, uint32_t adcisr) adc_startconv(priv, false); } + /* OVR: Overrun */ + if ((adcisr & ADC_INT_OVR) != 0) { + /* In case of a missed ISR - due to interrupt saturation - + * the upper half needs to be informed to terminate properly. + */ + awarn("WARNING: Overrun has occurred!\n"); + + /* To make use of already sampled data the conversion needs to be + * stopped first before reading out the data register. + */ + + adc_startconv(priv, false); + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADSTART) != 0); + + /* Verify that the upper-half driver has bound its callback functions */ + + if ((priv->cb != NULL) && (priv->cb->au_reset != NULL)) + { + /* Notify upper-half driver about the overrun */ + + priv->cb->au_reset(dev); + } + + adc_putreg(priv, STM32_ADC_ISR_OFFSET, ADC_INT_OVR); } /* EOC: End of conversion */ if ((adcisr & ADC_INT_EOC) != 0) { - /* Read the converted value and clear EOC bit - * (It is cleared by reading the ADC_DR) + /* Read from the ADC_DR register until 8 stage FIFO is empty. + * The FIFO is first mentioned in STM32H7 Reference Manual + * rev. 7, though, not yet indicated in the block diagram! */ - value = adc_getreg(priv, STM32_ADC_DR_OFFSET); - value &= ADC_DR_MASK; - - /* Verify that the upper-half driver has bound its callback functions */ - - if (priv->cb != NULL) + do { - /* Give the ADC data to the ADC driver. The ADC receive() method - * accepts 3 parameters: - * - * 1) The first is the ADC device instance for this ADC block. - * 2) The second is the channel number for the data, and - * 3) The third is the converted data for the channel. + /* Read the converted value and clear EOC bit + * (It is cleared by reading the ADC_DR) */ - DEBUGASSERT(priv->cb->au_receive != NULL); - priv->cb->au_receive(dev, priv->chanlist[priv->current], value); - } - - /* Set the channel number of the next channel that will complete - * conversion - */ - - priv->current++; - - if (priv->current >= priv->nchannels) - { - /* Restart the conversion sequence from the beginning */ - - priv->current = 0; + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); + value &= ADC_DR_MASK; + + /* Verify that the upper-half driver has bound its + * callback functions + */ + + if (priv->cb != NULL) + { + /* Hand the ADC data to the ADC driver. The ADC receive() + * method accepts 3 parameters: + * + * 1) The first is the ADC device instance for this ADC block. + * 2) The second is the channel number for the data, and + * 3) The third is the converted data for the channel. + */ + + DEBUGASSERT(priv->cb->au_receive != NULL); + priv->cb->au_receive(dev, priv->chanlist[priv->current], + value); + } + + /* Set the channel number of the next channel that will + * complete conversion + */ + + priv->current++; + + if (priv->current >= priv->nchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } } + while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_EOC) != 0); } return OK; diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index 5ed4373e450..f74d7497b56 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -79,7 +79,7 @@ * Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap. * +1 to CONFIG_MM_REGIONS if you want to use DTCM. * - * - External SDRAM can be connected to the FMC peripherial. Initialization + * - External SDRAM can be connected to the FMC peripheral. Initialization * of FMC is done as arm_addregion() will invoke stm32_fmc_init(). * Please read the comment in stm32_fmc.c how to initialize FMC * correctly. diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index 2c581367241..f25557bd624 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/stm32h7/stm32_dma.c b/arch/arm/src/stm32h7/stm32_dma.c index 20b74ef2aed..eaf5003c889 100644 --- a/arch/arm/src/stm32h7/stm32_dma.c +++ b/arch/arm/src/stm32h7/stm32_dma.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -2054,7 +2055,7 @@ static bool stm32_bdma_capable(FAR stm32_dmacfg_t *cfg) ((mend + 1) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0) { dmainfo("stm32_dmacapable: dcache unaligned " - "maddr:0x%08" PRIx32 " mend:0x%08x\n", + "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); #if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; @@ -2270,9 +2271,9 @@ void weak_function arm_dma_initialize(void) * in chip/stm32h7xxxxxxx_dmamux.h * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * * Assumptions: * - The caller does not hold he DMA channel. diff --git a/arch/arm/src/stm32h7/stm32_dma.h b/arch/arm/src/stm32h7/stm32_dma.h index 9843b9d2db8..03ff83dde15 100644 --- a/arch/arm/src/stm32h7/stm32_dma.h +++ b/arch/arm/src/stm32h7/stm32_dma.h @@ -125,9 +125,9 @@ extern "C" * in chip/stm32h7xxxxxxx_dmamux.h * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * * Assumptions: * - The caller does not hold he DMA channel. diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 1d3c821d7fb..49a3eae706a 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -294,7 +296,11 @@ #define PHY_READ_TIMEOUT (0x0004ffff) #define PHY_WRITE_TIMEOUT (0x0004ffff) -#define PHY_RETRY_TIMEOUT (0x0004ffff) +#define PHY_RETRY_TIMEOUT (0x0001998) + +/* MAC reset ready delays in loop counts */ + +#define MAC_READY_USTIMEOUT (200) /* Register values **********************************************************/ @@ -370,11 +376,11 @@ * that are cleared unconditionally). Per the reference manual, all reserved * bits must be retained at their reset value. * - * ETH_MACPFR_PR Bit 0: Promiscuous mode + * ETH_MACPFR_PM Bit 0: Promiscuous mode * ETH_MACPFR_HUC Bit 1: Hash unicast * ETH_MACPFR_HMC Bit 2: Hash multicast * ETH_MACPFR_DAIF Bit 3: Destination address inverse filtering - * ETH_MACPFR_PM Bit 4: Pass all multicast + * ETH_MACPFR_PAM Bit 4: Pass all multicast * ETH_MACPFR_DBF Bit 5: Broadcast frames disable * ETH_MACPFR_PCF Bits 6-7: Pass control frames * ETH_MACPFR_SAIF Bit 8: Source address inverse filtering @@ -387,20 +393,19 @@ */ #define MACPFR_CLEAR_BITS \ - (ETH_MACPFR_PR | ETH_MACPFR_HUC | ETH_MACPFR_HMC | ETH_MACPFR_DAIF | \ - ETH_MACPFR_PM | ETH_MACPFR_DBF | ETH_MACPFR_PCF_MASK | ETH_MACPFR_SAIF | \ + (ETH_MACPFR_PM | ETH_MACPFR_HUC | ETH_MACPFR_HMC | ETH_MACPFR_DAIF | \ + ETH_MACPFR_PAM | ETH_MACPFR_DBF | ETH_MACPFR_PCF_MASK | ETH_MACPFR_SAIF | \ ETH_MACPFR_SAF | ETH_MACPFR_HPF | ETH_MACPFR_VTFE | ETH_MACPFR_IPFE | \ ETH_MACPFR_DNTU | ETH_MACPFR_RA) /* The following bits are set or left zero unconditionally in all modes. * - * ETH_MACPFR_PR Promiscuous mode 0 (disabled) * ETH_MACPFR_HUC Hash unicast 0 (perfect * dest filtering) * ETH_MACPFR_HMC Hash multicast 0 (perfect * dest filtering) * ETH_MACPFR_DAIF Destination address inverse filtering 0 (normal) - * ETH_MACPFR_PM Pass all multicast 0 (Depends on HMC + * ETH_MACPFR_PAM Pass all multicast 0 (Depends on HMC * bit) * ETH_MACPFR_DBF Broadcast frames disable 0 (enabled) * ETH_MACPFR_PCF Pass control frames 1 (block all but @@ -412,7 +417,11 @@ * ETH_MACPFR_RA Receive all 0 (disabled) */ -#define MACPFR_SET_BITS (ETH_MACPFR_PCF_PAUSE) +#ifdef CONFIG_NET_PROMISCUOUS +# define MACPFR_SET_BITS (ETH_MACPFR_PCF_PAUSE | ETH_MACPFR_PM) +#else +# define MACPFR_SET_BITS (ETH_MACPFR_PCF_PAUSE) +#endif /* Clear the MACQTXFCR and MACRXFCR bits that will be setup during MAC * initialization (or that are cleared unconditionally). Per the reference @@ -3545,6 +3554,8 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) { break; } + + nxsig_usleep(100); } if (timeout >= PHY_RETRY_TIMEOUT) @@ -3577,6 +3588,8 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) { break; } + + nxsig_usleep(100); } if (timeout >= PHY_RETRY_TIMEOUT) @@ -3767,7 +3780,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the MII interface */ -#if defined(CONFIG_STM32H7_MII) +# if defined(CONFIG_STM32H7_MII) /* Select the MII interface */ @@ -3782,7 +3795,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_MII_MCO1) +# if defined(CONFIG_STM32H7_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3790,7 +3803,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO2) +# elif defined(CONFIG_STM32H7_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3798,12 +3811,12 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO) +# elif defined(CONFIG_STM32H7_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE); -# endif +# endif /* MII interface pins (17): * @@ -3829,7 +3842,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -#elif defined(CONFIG_STM32H7_RMII) +# elif defined(CONFIG_STM32H7_RMII) /* Select the RMII interface */ @@ -3844,7 +3857,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_RMII_MCO1) +# if defined(CONFIG_STM32H7_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3852,7 +3865,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO2) +# elif defined(CONFIG_STM32H7_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3860,12 +3873,12 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO) +# elif defined(CONFIG_STM32H7_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE); -# endif +# endif /* RMII interface pins (7): * @@ -3880,7 +3893,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_ETH_RMII_TXD0); stm32_configgpio(GPIO_ETH_RMII_TXD1); stm32_configgpio(GPIO_ETH_RMII_TX_EN); -#endif +# endif #endif #ifdef CONFIG_STM32H7_ETH_PTP @@ -3909,6 +3922,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) static void stm32_ethreset(struct stm32_ethmac_s *priv) { uint32_t regval; + volatile uint32_t timeout; /* Reset the Ethernet on the AHB1 bus */ @@ -3933,7 +3947,11 @@ static void stm32_ethreset(struct stm32_ethmac_s *priv) * core clock domains. */ - while ((stm32_getreg(STM32_ETH_DMAMR) & ETH_DMAMR_SWR) != 0); + timeout = MAC_READY_USTIMEOUT; + while (timeout-- && (stm32_getreg(STM32_ETH_DMAMR) & ETH_DMAMR_SWR) != 0) + { + up_udelay(1); + } /* According to the spec, these need to be done before creating * the descriptor lists, so initialize these already here diff --git a/arch/arm/src/stm32h7/stm32_exti_alarm.c b/arch/arm/src/stm32h7/stm32_exti_alarm.c index 32ce108d918..a4ed9ff808e 100644 --- a/arch/arm/src/stm32h7/stm32_exti_alarm.c +++ b/arch/arm/src/stm32h7/stm32_exti_alarm.c @@ -1,42 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/stm32_exti_alarm.c * - * Copyright (C) 2015, 2017, 2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * This file derives from similar logic for the STM32 F1: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Diego Sanchez - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/stm32_exti_wakeup.c b/arch/arm/src/stm32h7/stm32_exti_wakeup.c index 12e15108278..81a28f9d63c 100644 --- a/arch/arm/src/stm32h7/stm32_exti_wakeup.c +++ b/arch/arm/src/stm32h7/stm32_exti_wakeup.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/stm32_exti_wakeup.c * - * Copyright (C) 2009, 2012, 2017-2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Juha Niskanen - * David Sidrane + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/stm32_fmc.c b/arch/arm/src/stm32h7/stm32_fmc.c index 3631093b628..19bcf2d0ef5 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.c +++ b/arch/arm/src/stm32h7/stm32_fmc.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/stm32_fmc.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jason T. Harris + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +28,7 @@ #include "stm32.h" +#include #include #include @@ -250,7 +236,7 @@ static int stm32_fmc_sdram_wait(unsigned timeout); * Name: stm32_fmc_init * * Description: - * Initialize the FMC peripherial. Because FMC initialization is highly + * Initialize the FMC peripheral. Because FMC initialization is highly * dependent on the used parts, definition of the initial values for FMC * registers is mostly left to board designer. * @@ -298,7 +284,7 @@ void stm32_fmc_init(void) modreg32(BOARD_FMC_SDTR2, FMC_SDTR_MASK, STM32_FMC_SDTR2); #endif - /* Enable the FMC peripherial */ + /* Enable the FMC peripheral */ modreg32(FMC_BCR_FMCEN, FMC_BCR_FMCEN, STM32_FMC_BCR1); diff --git a/arch/arm/src/stm32h7/stm32_fmc.h b/arch/arm/src/stm32h7/stm32_fmc.h index 6207775dc88..938e8c6ab54 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.h +++ b/arch/arm/src/stm32h7/stm32_fmc.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/stm32_fmc.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jason T. Harris + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -64,7 +49,7 @@ extern "C" * Name: stm32_fmc_init * * Description: - * Initialize the FMC peripherial. Because FMC initialization is highly + * Initialize the FMC peripheral. Because FMC initialization is highly * dependent on the used parts, definition of the initial values for FMC * registers is mostly left to board designer. * diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c index c0b30647831..3e5b40f6a6f 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.c +++ b/arch/arm/src/stm32h7/stm32_i2c.c @@ -210,6 +210,7 @@ #include #include #include +#include #include #include @@ -886,8 +887,8 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: 0x%08x\n", - priv->intstate, (long)elapsed, (long)timeout, priv->status); + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: 0x%08" PRIx32 + "\n", priv->intstate, (long)elapsed, (long)timeout, priv->status); /* Set the interrupt state back to IDLE */ diff --git a/arch/arm/src/stm32h7/stm32_irq.c b/arch/arm/src/stm32h7/stm32_irq.c index 6ba43c61e56..c4edc414f49 100644 --- a/arch/arm/src/stm32h7/stm32_irq.c +++ b/arch/arm/src/stm32h7/stm32_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32h7/stm32_iwdg.c b/arch/arm/src/stm32h7/stm32_iwdg.c index 56d121940a6..859c346188f 100644 --- a/arch/arm/src/stm32h7/stm32_iwdg.c +++ b/arch/arm/src/stm32h7/stm32_iwdg.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c index c5e38b7a337..56c5d8fe2c3 100644 --- a/arch/arm/src/stm32h7/stm32_otgdev.c +++ b/arch/arm/src/stm32h7/stm32_otgdev.c @@ -25,10 +25,12 @@ #include #include +#include #include #include #include #include +#include #include #include @@ -905,7 +907,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - uinfo("[repeats %d more times]\n", count - 3); + uinfo("[repeats %" PRId32 " more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -917,7 +919,7 @@ static uint32_t stm32_getreg(uint32_t addr) /* Show the register value read */ - uinfo("%08x->%08x\n", addr, val); + uinfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); return val; } #endif @@ -935,7 +937,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - uinfo("%08x<-%08x\n", addr, val); + uinfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); /* Write the value */ @@ -1289,8 +1291,8 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, return; } - uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n", - privep->epphy, privreq, privreq->req.len, + uinfo("EP%" PRId8 " req=%p: len=%" PRId16 " xfrd=%" PRId16" zlp=%" + PRId8 "\n", privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->zlp); /* Check for a special case: If we are just starting a request (xfrd==0) @@ -2731,7 +2733,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) if ((daint & 1) != 0) { regval = stm32_getreg(STM32_OTG_DOEPINT(epno)); - uerr("DOEPINT(%d) = %08x\n", epno, regval); + uerr("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); stm32_putreg(0xff, STM32_OTG_DOEPINT(epno)); } @@ -2970,7 +2972,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) { if ((daint & 1) != 0) { - uerr("DIEPINT(%d) = %08x\n", + uerr("DIEPINT(%d) = %08" PRIx32 "\n", epno, stm32_getreg(STM32_OTG_DIEPINT(epno))); stm32_putreg(0xff, STM32_OTG_DIEPINT(epno)); } @@ -5585,7 +5587,11 @@ void arm_usbinitialize(void) stm32_configgpio(GPIO_OTG_DM); stm32_configgpio(GPIO_OTG_DP); - stm32_configgpio(GPIO_OTG_ID); /* Only needed for OTG */ + + /* Only needed for OTG */ +# ifndef CONFIG_OTG_ID_GPIO_DISABLE + stm32_configgpio(GPIO_OTG_ID); +# endif /* SOF output pin configuration is configurable. */ @@ -5608,7 +5614,7 @@ void arm_usbinitialize(void) ret = irq_attach(STM32_IRQ_OTG, stm32_usbinterrupt, NULL); if (ret < 0) { - uerr("irq_attach failed\n", ret); + uerr("ERROR: irq_attach failed: %d\n", ret); goto errout; } diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index e83eb4c0045..1125a935e24 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32h7/stm32_pmsleep.c b/arch/arm/src/stm32h7/stm32_pmsleep.c index fbe07ff798b..1d307bc80f8 100644 --- a/arch/arm/src/stm32h7/stm32_pmsleep.c +++ b/arch/arm/src/stm32h7/stm32_pmsleep.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/stm32_pmsleep.c * - * Copyright (C) 2012, 2017, 2020 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index cddb733f0e3..145d7ca38dc 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -560,7 +560,7 @@ static struct stm32_pwmchan_s g_pwm1channels[] = .in_use = 1, .pol = CONFIG_STM32H7_TIM1_CH5POL, .idle = CONFIG_STM32H7_TIM1_CH5IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif }, @@ -575,7 +575,7 @@ static struct stm32_pwmchan_s g_pwm1channels[] = .in_use = 1, .pol = CONFIG_STM32H7_TIM1_CH6POL, .idle = CONFIG_STM32H7_TIM1_CH6IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif } @@ -1120,7 +1120,7 @@ static struct stm32_pwmchan_s g_pwm8channels[] = .in_use = 1, .pol = CONFIG_STM32H7_TIM8_CH5POL, .idle = CONFIG_STM32H7_TIM8_CH5IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif }, @@ -1135,7 +1135,7 @@ static struct stm32_pwmchan_s g_pwm8channels[] = .in_use = 1, .pol = CONFIG_STM32H7_TIM8_CH6POL, .idle = CONFIG_STM32H7_TIM8_CH6IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif } @@ -1725,7 +1725,7 @@ static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, ****************************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO -static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) +static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, FAR const char *msg) { FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; @@ -2324,13 +2324,13 @@ static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, case STM32_CHANMODE_PWM1: { - chanmode = ATIM_CCMR_MODE_PWM1; + chanmode = GTIM_CCMR_MODE_PWM1; break; } case STM32_CHANMODE_PWM2: { - chanmode = ATIM_CCMR_MODE_PWM2; + chanmode = GTIM_CCMR_MODE_PWM2; break; } @@ -2651,13 +2651,13 @@ static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev, /* Get outputs configuration */ - regval |= ((outputs & STM32_PWM_OUT1) ? ATIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0); regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32_PWM_OUT2) ? ATIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0); regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32_PWM_OUT3) ? ATIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0); regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32_PWM_OUT4) ? ATIM_CCER_CC4E : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0); /* NOTE: CC4N doesn't exist, but some docs show configuration bits for it */ @@ -2770,7 +2770,7 @@ static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev) { FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; - pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); return OK; } @@ -3113,7 +3113,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, */ priv->prev = pwm_pulsecount(info->count); - pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->prev - 1); + pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should * preload the RCR into active repetition counter. @@ -3127,7 +3127,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, priv->count = info->count; priv->curr = pwm_pulsecount(info->count - priv->prev); - pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); + pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } /* Otherwise, just clear the repetition counter */ @@ -3136,7 +3136,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, { /* Set the repetition counter to zero */ - pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ @@ -3165,7 +3165,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, /* Clear all pending interrupts and enable the update interrupt. */ pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, ATIM_DIER_UIE); + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ diff --git a/arch/arm/src/stm32h7/stm32_pwr.c b/arch/arm/src/stm32h7/stm32_pwr.c index 674ae7e617f..26a3786a8f2 100644 --- a/arch/arm/src/stm32h7/stm32_pwr.c +++ b/arch/arm/src/stm32h7/stm32_pwr.c @@ -27,6 +27,7 @@ #include #include +#include #include #include "barriers.h" diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index a7ce9704601..0d9cd01ddc1 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/stm32_qspi.c * - * Copyright (C) 2016-2017, 2019 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -160,7 +145,7 @@ /* Clocking *****************************************************************/ /* The board.h file may choose a different clock source for QUADSPI - * peripherial by defining the BOARD_QSPI_CLK macro to one of the + * peripheral by defining the BOARD_QSPI_CLK macro to one of the * RCC_D1CCIPR_QSPISEL_XXX values (XXX = HCLK, PLL1, PLL2, PER). * QUADSPI clock defaults to HCLK. */ @@ -2162,7 +2147,7 @@ static int qspi_command(struct qspi_dev_s *dev, * info */ - qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD); + qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDWR); } /* Wait for the interrupt routine to finish it's magic */ diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index bbb774c5778..1ec6bffc380 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32h7/stm32_qspi.h * - * Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/stm32_rtc.c b/arch/arm/src/stm32h7/stm32_rtc.c index 65465d8685c..63b52413496 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.c +++ b/arch/arm/src/stm32h7/stm32_rtc.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c index bc855cd10b6..4166c958428 100644 --- a/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 34369281319..7336859b9ec 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -166,7 +167,21 @@ #define FIFO_SIZE_IN_BYTES 64 -/* Friendly CLKCR bit re-definitions ****************************************/ +/* Friendly Clock source & CLKCR bit re-definitions *************************/ + +/* If not set in board use default pll1_q_ck clock is selected as + * kernel peripheral clock (default after reset) + */ + +#if !defined(STM32_RCC_D1CCIPR_SDMMCSEL) +# define STM32_RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMC_PLL1 +#endif + +#if STM32_RCC_D1CCIPR_SDMMCSEL == RCC_D1CCIPR_SDMMC_PLL1 +# define STM32_SDMMC_CLK STM32_PLL1Q_FREQUENCY +#else +# define STM32_SDMMC_CLK STM32_PLL2R_FREQUENCY +#endif #define STM32_CLKCR_RISINGEDGE (0) #define STM32_CLKCR_FALLINGEDGE STM32_SDMMC_CLKCR_NEGEDGE @@ -207,9 +222,9 @@ #define SDMMC_CMDTIMEOUT (100000) #define SDMMC_LONGTIMEOUT (0x7fffffff) -/* Big DTIMER setting */ +/* DTIMER setting */ -#define SDMMC_DTIMER_DATATIMEOUT (6250000) /* 250 ms @ 25 MHz */ +#define SDMMC_DTIMER_DATATIMEOUT_MS 250 /* Block size for multi-block transfers */ @@ -742,7 +757,7 @@ static inline void stm32_setclkcr(struct stm32_dev_s *priv, uint32_t clkcr) sdmmc_putreg32(priv, regval, STM32_SDMMC_CLKCR_OFFSET); - mcinfo("CLKCR: %08x PWR: %08x\n", + mcinfo("CLKCR: %08" PRIx32 " PWR: %08" PRIx32 "\n", sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET), sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET)); } @@ -780,12 +795,8 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, flags = enter_critical_section(); #if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) - if ((waitmask & SDIOWAIT_WRCOMPLETE) != 0) + if ((waitevents & SDIOWAIT_WRCOMPLETE) != 0) { - /* Do not use this in STM32_SDMMC_MASK register */ - - waitmask &= ~SDIOWAIT_WRCOMPLETE; - pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK | \ GPIO_PUPD_MASK); pinset |= (GPIO_INPUT | GPIO_EXTI); @@ -981,14 +992,22 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); - mcinfo(" POWER[%08x]: %08x\n", STM32_SDMMC_POWER_OFFSET, regs->power); - mcinfo(" CLKCR[%08x]: %08x\n", STM32_SDMMC_CLKCR_OFFSET, regs->clkcr); - mcinfo(" DCTRL[%08x]: %08x\n", STM32_SDMMC_DCTRL_OFFSET, regs->dctrl); - mcinfo(" DTIMER[%08x]: %08x\n", STM32_SDMMC_DTIMER_OFFSET, regs->dtimer); - mcinfo(" DLEN[%08x]: %08x\n", STM32_SDMMC_DLEN_OFFSET, regs->dlen); - mcinfo(" DCOUNT[%08x]: %08x\n", STM32_SDMMC_DCOUNT_OFFSET, regs->dcount); - mcinfo(" STA[%08x]: %08x\n", STM32_SDMMC_STA_OFFSET, regs->sta); - mcinfo(" MASK[%08x]: %08x\n", STM32_SDMMC_MASK_OFFSET, regs->mask); + mcinfo(" POWER[%08x]: %08" PRIx8 "\n", STM32_SDMMC_POWER_OFFSET, + regs->power); + mcinfo(" CLKCR[%08x]: %08" PRIx16 "\n", STM32_SDMMC_CLKCR_OFFSET, + regs->clkcr); + mcinfo(" DCTRL[%08x]: %08" PRIx16 "\n", STM32_SDMMC_DCTRL_OFFSET, + regs->dctrl); + mcinfo(" DTIMER[%08x]: %08" PRIx32 "\n", STM32_SDMMC_DTIMER_OFFSET, + regs->dtimer); + mcinfo(" DLEN[%08x]: %08" PRIx32 "\n", STM32_SDMMC_DLEN_OFFSET, + regs->dlen); + mcinfo(" DCOUNT[%08x]: %08" PRIx32 "\n", STM32_SDMMC_DCOUNT_OFFSET, + regs->dcount); + mcinfo(" STA[%08x]: %08" PRIx32 "\n", STM32_SDMMC_STA_OFFSET, + regs->sta); + mcinfo(" MASK[%08x]: %08" PRIx32 "\n", STM32_SDMMC_MASK_OFFSET, + regs->mask); } #endif @@ -1071,7 +1090,10 @@ static uint8_t stm32_log2(uint16_t value) static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, uint32_t dlen, bool receive) { - uint32_t dctrl = 0; + uint32_t clkdiv; + uint32_t regval; + uint32_t dctrl; + uint32_t sdio_clk = STM32_SDMMC_CLK; DEBUGASSERT((sdmmc_getreg32(priv, STM32_SDMMC_IDMACTRLR_OFFSET) & STM32_SDMMC_IDMACTRLR_IDMAEN) == 0); @@ -1102,10 +1124,12 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, #if defined(HAVE_SDMMC_SDIO_MODE) if (priv->sdiomode == true) { - dctrl |= STM32_SDMMC_DCTRL_SDIOEN | STM32_SDMMC_DCTRL_DTMODE_SDIO; + dctrl |= STM32_SDMMC_DCTRL_SDIOEN; } #endif + dctrl |= STM32_SDMMC_DCTRL_DTMODE_BLOCK; + /* if dlen > priv->blocksize we assume that this is a multi-block transfer * and that the len is multiple of priv->blocksize. */ @@ -1131,7 +1155,26 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, /* Enable data path */ - /* Set DTIMER */ + /* Set DTIMER + * + * Enable data path using a timeout scaled to the SD_CLOCK (the card + * clock). + */ + + regval = sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET); + clkdiv = (regval & STM32_SDMMC_CLKCR_CLKDIV_MASK) >> + STM32_SDMMC_CLKCR_CLKDIV_SHIFT; + + /* CLKDIV_ of 0x000: is Bypass */ + + if (clkdiv != 0) + { + sdio_clk = sdio_clk / (2 * clkdiv); + } + + /* Convert Timeout in Ms to SD_CLK counts */ + + timeout = timeout * (sdio_clk / 1000); sdmmc_putreg32(priv, timeout, STM32_SDMMC_DTIMER_OFFSET); @@ -1165,8 +1208,11 @@ static void stm32_datadisable(struct stm32_dev_s *priv) /* Reset DTIMER */ - sdmmc_putreg32(priv, SDMMC_DTIMER_DATATIMEOUT, STM32_SDMMC_DTIMER_OFFSET); - sdmmc_putreg32(priv, 0, STM32_SDMMC_DLEN_OFFSET); /* Reset DLEN */ + sdmmc_putreg32(priv, UINT32_MAX, STM32_SDMMC_DTIMER_OFFSET); + + /* Reset DLEN */ + + sdmmc_putreg32(priv, 0, STM32_SDMMC_DLEN_OFFSET); /* Reset DCTRL DTEN, DTDIR, DTMODE, and DBLOCKSIZE fields */ @@ -1403,7 +1449,7 @@ static void stm32_eventtimeout(wdparm_t arg) DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || priv->wkupevent != 0); - mcinfo("sta: %08x enabled irq: %08x\n", + mcinfo("sta: %08" PRIx32 " enabled irq: %08" PRIx32 "\n", sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET), sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET)); @@ -1413,8 +1459,13 @@ static void stm32_eventtimeout(wdparm_t arg) { /* Yes.. wake up any waiting threads */ +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + stm32_endwait(priv, SDIOWAIT_TIMEOUT | + (priv->waitevents & SDIOWAIT_WRCOMPLETE)); +#else stm32_endwait(priv, SDIOWAIT_TIMEOUT); - mcerr("Timeout: remaining: %d\n", priv->remaining); +#endif + mcerr("Timeout: remaining: %zu\n", priv->remaining); } } @@ -1712,7 +1763,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) * Sets STM32_SDMMC_ICR_DCRCFAILC */ - mcerr("ERROR: Data block CRC failure, remaining: %d\n", + mcerr("ERROR: Data block CRC failure, remaining: %u\n", priv->remaining); stm32_endtransfer(priv, @@ -1727,7 +1778,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) * Sets STM32_SDMMC_ICR_DTIMEOUTC */ - mcerr("ERROR: Data timeout, remaining: %d\n", + mcerr("ERROR: Data timeout, remaining: %u\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | @@ -1742,7 +1793,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) * Sets STM32_SDMMC_ICR_RXOVERRC */ - mcerr("ERROR: RX FIFO overrun, remaining: %d\n", + mcerr("ERROR: RX FIFO overrun, remaining: %u\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | @@ -1757,7 +1808,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) * Sets STM32_SDMMC_ICR_TXUNDERRC */ - mcerr("ERROR: TX FIFO underrun, remaining: %d\n", + mcerr("ERROR: TX FIFO underrun, remaining: %u\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | @@ -1943,7 +1994,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) leave_critical_section(flags); - mcinfo("CLCKR: %08x POWER: %08x\n", + mcinfo("CLCKR: %08" PRIx32 " POWER: %08" PRIx32 "\n", sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET), sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET)); } @@ -2202,9 +2253,22 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; regval |= cmdidx | STM32_SDMMC_CMD_CPSMEN; - if (cmd & MMCSD_DATAXFR_MASK) + switch (cmd & MMCSD_DATAXFR_MASK) { - regval |= STM32_SDMMC_CMD_CMDTRANS; + case MMCSD_RDDATAXFR: /* Read block transfer */ + case MMCSD_WRDATAXFR: /* Write block transfer */ + case MMCSD_RDSTREAM: /* MMC Read stream */ + case MMCSD_WRSTREAM: /* MMC Write stream */ + regval |= STM32_SDMMC_CMD_CMDTRANS; + break; + + case MMCSD_NODATAXFR: + default: + if ((cmd & MMCSD_STOPXFR) != 0) + { + regval |= STM32_SDMMC_CMD_CMDSTOP; + } + break; } /* Clear interrupts */ @@ -2212,7 +2276,8 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR | STM32_SDMMC_RESPDONE_ICR, STM32_SDMMC_ICR_OFFSET); - mcinfo("cmd: %08x arg: %08x regval: %08x enabled irq: %08x\n", + mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 " regval: %08" PRIx32 + " enabled irq: %08" PRIx32 "\n", cmd, arg, regval, sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET)); /* Write the SDIO CMD */ @@ -2295,8 +2360,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Then set up the SDIO data path */ - stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((nbytes + 511) >> 9), - nbytes, true); + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT_MS, nbytes, true); /* Workaround the FIFO data available issue */ @@ -2370,8 +2434,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const /* Then set up the SDIO data path */ - stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((nbytes + 511) >> 9), - nbytes, false); + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT_MS, nbytes, false); /* Enable TX interrupts */ @@ -2486,7 +2549,8 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { if (--timeout <= 0) { - mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", + mcerr("ERROR: Timeout cmd: %08" PRIx32 " events: %08" PRIx32 + " STA: %08" PRIx32 "\n", cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET)); return -ETIMEDOUT; @@ -2565,7 +2629,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) { - mcerr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); ret = -EINVAL; } else @@ -2576,12 +2640,12 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); if ((regval & STM32_SDMMC_STA_CTIMEOUT) != 0) { - mcerr("ERROR: Command timeout: %08x\n", regval); + mcerr("ERROR: Command timeout: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } else if ((regval & STM32_SDMMC_STA_CCRCFAIL) != 0) { - mcerr("ERROR: CRC failure: %08x\n", regval); + mcerr("ERROR: CRC failure: %08" PRIx32 "\n", regval); ret = -EIO; } #if defined(CONFIG_DEBUG_FEATURES) @@ -2593,7 +2657,8 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((uint8_t)(respcmd & STM32_SDMMC_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) { - mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); + mcerr("ERROR: RESCMD=%02" PRIx32 " CMD=%08" PRIx32 + "\n", respcmd, cmd); ret = -EINVAL; } } @@ -2631,7 +2696,7 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - mcerr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); ret = -EINVAL; } else @@ -2642,12 +2707,12 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); if (regval & STM32_SDMMC_STA_CTIMEOUT) { - mcerr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } else if (regval & STM32_SDMMC_STA_CCRCFAIL) { - mcerr("ERROR: CRC fail STA: %08x\n", regval); + mcerr("ERROR: CRC fail STA: %08" PRIx32 "\n", regval); ret = -EIO; } } @@ -2690,7 +2755,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - mcerr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); ret = -EINVAL; } else @@ -2703,7 +2768,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); if (regval & STM32_SDMMC_STA_CTIMEOUT) { - mcerr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } } @@ -2765,11 +2830,7 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev, if (stm32_gpioread(priv->d0_gpio)) { - eventset &= ~SDIOWAIT_TIMEOUT; - } - else - { - waitmask = SDIOWAIT_WRCOMPLETE; + eventset &= ~(SDIOWAIT_TIMEOUT | SDIOWAIT_WRCOMPLETE); } } else @@ -2880,7 +2941,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev) if ((priv->waitevents & SDIOWAIT_WRCOMPLETE) != 0) { /* Atomically read pin to see if ready (true) and determine if ISR - * fired. If Pin is ready and if ISR did NOT fire end the wait here + * fired. If Pin is ready and if ISR did NOT fire end the wait here. */ if (stm32_gpioread(priv->d0_gpio) && @@ -2969,7 +3030,7 @@ static void stm32_callbackenable(FAR struct sdio_dev_s *dev, { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - mcinfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02" PRIx8 "\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -3050,8 +3111,8 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, (uintptr_t)buffer + buflen <= SRAM4_END)) { mcerr("invalid IDMA address " - "buffer:0x%08x end:0x%08x\n", - buffer, buffer + buflen - 1); + "buffer:0x%08" PRIxPTR " end:0x%08" PRIxPTR "\n", + (uintptr_t)buffer, (uintptr_t)(buffer + buflen - 1)); return -EFAULT; } } @@ -3070,7 +3131,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, ((uintptr_t)(buffer + buflen) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0)) { mcerr("dcache unaligned " - "buffer:0x%08x end:0x%08x\n", + "buffer:%p end:%p\n", buffer, buffer + buflen - 1); return -EFAULT; } @@ -3151,8 +3212,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, /* Then set up the SDIO data path */ - stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((buflen + 511) >> 9), - buflen, true); + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT_MS, buflen, true); /* Configure the RX DMA */ @@ -3243,8 +3303,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Then set up the SDIO data path */ - stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((buflen + 511) >> 9), - buflen, false); + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT_MS, buflen, false); /* Configure the TX DMA */ @@ -3282,7 +3341,7 @@ static void stm32_callback(void *arg) /* Is a callback registered? */ DEBUGASSERT(priv != NULL); - mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + mcinfo("Callback %p(%p) cbevents: %02" PRIx8 " cdstatus: %02" PRIx8 "\n", priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); if (priv->callback) @@ -3518,7 +3577,8 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) leave_critical_section(flags); - mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + mcinfo("cdstatus OLD: %02" PRIx8 " NEW: %02" PRIx8 "\n", + cdstatus, priv->cdstatus); /* Perform any requested callback if the status has changed */ @@ -3561,7 +3621,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - mcinfo("cdstatus: %02x\n", priv->cdstatus); + mcinfo("cdstatus: %02" PRIx8 "\n", priv->cdstatus); leave_critical_section(flags); } #endif /* CONFIG_STM32H7_SDMMC1 || CONFIG_STM32H7_SDMMC2 */ diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index f747879c3a1..e5c4e38d4fd 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -2220,7 +2221,7 @@ static int up_dma_setup(struct uart_dev_s *dev) { priv->txdma = stm32_dmachannel(priv->txdma_channel); - nxsem_init(&priv->txdmasem, 0, 0); + nxsem_init(&priv->txdmasem, 0, 1); nxsem_set_protocol(&priv->txdmasem, SEM_PRIO_NONE); /* Enable receive Tx DMA for the UART */ @@ -3369,16 +3370,10 @@ static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg) static void up_dma_txavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - size_t resid = 0; - - resid = stm32_dmaresidual(priv->txdma); /* Only send when the DMA is idle */ - if (resid != 0) - { - nxsem_wait(&priv->txdmasem); - } + nxsem_wait(&priv->txdmasem); uart_xmitchars_dma(dev); } diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index 4b4d2ce5de0..5a23adf57b9 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -48,10 +48,12 @@ #include #include +#include #include #include #include #include +#include #include #include @@ -1026,11 +1028,13 @@ static inline void spi_writebyte(FAR struct stm32_spidev_s *priv, #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(FAR struct stm32_spidev_s *priv) { - spiinfo("CR1: 0x%08x CFG1: 0x%08x CFG2: 0x%08x\n", + spiinfo("CR1: 0x%08" PRIx32 " CFG1: 0x%08" PRIx32 + " CFG2: 0x%08" PRIx32 "\n", spi_getreg(priv, STM32_SPI_CR1_OFFSET), spi_getreg(priv, STM32_SPI_CFG1_OFFSET), spi_getreg(priv, STM32_SPI_CFG2_OFFSET)); - spiinfo("IER: 0x%08x SR: 0x%08x I2SCFGR: 0x%08x\n", + spiinfo("IER: 0x%08" PRIx32 " SR: 0x%08" PRIx32 + " I2SCFGR: 0x%08" PRIx32 "\n", spi_getreg(priv, STM32_SPI_IER_OFFSET), spi_getreg(priv, STM32_SPI_SR_OFFSET), spi_getreg(priv, STM32_SPI_I2SCFGR_OFFSET)); @@ -1527,7 +1531,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, * will be faster. */ - spiinfo("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %" PRId32 "->%" PRId32 "\n", frequency, actual); priv->frequency = frequency; priv->actual = actual; @@ -1557,7 +1561,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) uint32_t setbits = 0; uint32_t clrbits = 0; - spiinfo("mode=%d\n", mode); + spiinfo("mode=%" PRIx32 "\n", (uint32_t) mode); /* Has the mode changed? */ @@ -1697,7 +1701,7 @@ static int spi_hwfeatures(FAR struct spi_dev_s *dev, uint32_t setbits = 0; uint32_t clrbits = 0; - spiinfo("features=%08x\n", features); + spiinfo("features=%08" PRIx8 "\n", features); /* Transfer data LSB first? */ @@ -1802,11 +1806,13 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) if (priv->nbits > 8) { - spiinfo("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval); + spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 + "\n", wd, ret, regval); } else { - spiinfo("Sent: %02x Return: %02x Status: %02x\n", wd, ret, regval); + spiinfo("Sent: %02" PRIx32 " Return: %02" PRIx32 " Status: %02" PRIx32 + "\n", wd, ret, regval); } UNUSED(regval); @@ -1823,7 +1829,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into diff --git a/arch/arm/src/stm32h7/stm32_spi.h b/arch/arm/src/stm32h7/stm32_spi.h index 069336d4029..45babad4101 100644 --- a/arch/arm/src/stm32h7/stm32_spi.h +++ b/arch/arm/src/stm32h7/stm32_spi.h @@ -79,7 +79,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -FAR struct spi_sctrlr_s *stm32_spi_slave_initialize(int bus); +FAR struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); /**************************************************************************** * Name: stm32_spi1/2/...select and stm32_spi1/2/...status diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c b/arch/arm/src/stm32h7/stm32_spi_slave.c index c31893ac531..193153cb09e 100644 --- a/arch/arm/src/stm32h7/stm32_spi_slave.c +++ b/arch/arm/src/stm32h7/stm32_spi_slave.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -178,9 +179,10 @@ enum spi_config_e struct stm32_spidev_s { - struct spi_sctrlr_s sctrlr; /* Externally visible part of the - * SPI slave interface */ - struct spi_sdev_s *sdev; /* Bound SPI slave device interface */ + /* Externally visible part of the SPI slave interface */ + + struct spi_slave_ctrlr_s ctrlr; + struct spi_slave_dev_s *dev; /* Bound SPI slave device interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t irq; /* SPI IRQ number */ @@ -267,16 +269,17 @@ static int spi_nssinterrupt(int irq, void *context, void *arg); /* SPI slave methods */ -static void spi_bind(struct spi_sctrlr_s *sctrlr, - struct spi_sdev_s *sdev, enum spi_smode_e mode, - int nbits); -static void spi_unbind(struct spi_sctrlr_s *sctrlr); -static int spi_enqueue(struct spi_sctrlr_s *sctrlr, +static void spi_bind(struct spi_slave_ctrlr_s *ctrlr, + struct spi_slave_dev_s *dev, + enum spi_slave_mode_e mode, + int nbits); +static void spi_unbind(struct spi_slave_ctrlr_s *ctrlr); +static int spi_enqueue(struct spi_slave_ctrlr_s *ctrlr, FAR const void *data, size_t len); -static bool spi_qfull(struct spi_sctrlr_s *sctrlr); -static void spi_qflush(struct spi_sctrlr_s *sctrlr); -static size_t spi_qpoll(struct spi_sctrlr_s *sctrlr); +static bool spi_qfull(struct spi_slave_ctrlr_s *ctrlr); +static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr); +static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr); /* Initialization */ @@ -295,7 +298,7 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain, /* SPI slave controller driver operations */ -static const struct spi_sctrlrops_s g_sctrlr_ops = +static const struct spi_slave_ctrlrops_s g_ctrlr_ops = { .bind = spi_bind, .unbind = spi_unbind, @@ -326,8 +329,8 @@ static const struct spi_sctrlrops_s g_sctrlr_ops = #define SPI_SLAVE_INIT(x) \ { \ - .sctrlr.ops = &g_sctrlr_ops, \ - .sdev = NULL, \ + .ctrlr.ops = &g_ctrlr_ops, \ + .dev = NULL, \ .spibase = STM32_SPI##x##_BASE, \ .spiclock = SPI45_KERNEL_CLOCK_FREQ, \ .irq = STM32_IRQ_SPI##x, \ @@ -345,7 +348,7 @@ __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); static uint8_t SPI_SLAVE_INQ(1)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); -static struct stm32_spidev_s g_spi1sctrlr = SPI_SLAVE_INIT(1); +static struct stm32_spidev_s g_spi1ctrlr = SPI_SLAVE_INIT(1); #endif @@ -357,7 +360,7 @@ __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); static uint8_t SPI_SLAVE_INQ(2)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); -static struct stm32_spidev_s g_spi2sctrlr = SPI_SLAVE_INIT(2); +static struct stm32_spidev_s g_spi2ctrlr = SPI_SLAVE_INIT(2); #endif @@ -369,7 +372,7 @@ __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); static uint8_t SPI_SLAVE_INQ(3)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); -static struct stm32_spidev_s g_spi3sctrlr = SPI_SLAVE_INIT(3); +static struct stm32_spidev_s g_spi3ctrlr = SPI_SLAVE_INIT(3); #endif @@ -381,7 +384,7 @@ __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); static uint8_t SPI_SLAVE_INQ(4)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); -static struct stm32_spidev_s g_spi4sctrlr = SPI_SLAVE_INIT(4); +static struct stm32_spidev_s g_spi4ctrlr = SPI_SLAVE_INIT(4); #endif @@ -393,7 +396,7 @@ __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); static uint8_t SPI_SLAVE_INQ(5)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); -static struct stm32_spidev_s g_spi5sctrlr = SPI_SLAVE_INIT(5); +static struct stm32_spidev_s g_spi5ctrlr = SPI_SLAVE_INIT(5); #endif @@ -407,7 +410,7 @@ __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); static uint8_t SPI_SLAVE_INQ(6)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] __attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); -static struct stm32_spidev_s g_spi6sctrlr = SPI_SLAVE_INIT(6); +static struct stm32_spidev_s g_spi6ctrlr = SPI_SLAVE_INIT(6); #endif @@ -897,9 +900,9 @@ static void spi_dmatxstart(FAR struct stm32_spidev_s *priv) * ****************************************************************************/ -static int spi_lock(FAR struct spi_sctrlr_s *sctrlr, bool lock) +static int spi_lock(FAR struct spi_slave_ctrlr_s *ctrlr, bool lock) { - FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)sctrlr; + FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)ctrlr; int ret; if (lock) @@ -970,10 +973,10 @@ static inline void spi_enable(FAR struct stm32_spidev_s *priv, bool state) * ****************************************************************************/ -static void spi_setmode(FAR struct spi_sctrlr_s *sctrlr, +static void spi_setmode(FAR struct spi_slave_ctrlr_s *ctrlr, enum spi_mode_e mode) { - FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)sctrlr; + FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)ctrlr; uint32_t setbits = 0; uint32_t clrbits = 0; @@ -1036,9 +1039,9 @@ static void spi_setmode(FAR struct spi_sctrlr_s *sctrlr, * ****************************************************************************/ -static void spi_setbits(FAR struct spi_sctrlr_s *sctrlr, int nbits) +static void spi_setbits(FAR struct spi_slave_ctrlr_s *ctrlr, int nbits) { - FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)sctrlr; + FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)ctrlr; uint32_t setbits = 0; uint32_t clrbits = 0; @@ -1086,37 +1089,37 @@ static void spi_setbits(FAR struct spi_sctrlr_s *sctrlr, int nbits) * * Description: * Bind the SPI slave device interface to the SPI slave controller - * interface and configure the SPI interface. Upon return, the SPI + * interface and configure the SPI interface. Upon return, the SPI * slave controller driver is fully operational and ready to perform * transfers. * * Input Parameters: - * sctrlr - SPI slave controller interface instance - * sdev - SPI slave device interface instance - * mode - The SPI mode requested - * nbits - The number of bits requests. - * If value is greater > 0 then it implies MSB first - * If value is below < 0, then it implies LSB first with -nbits + * ctrlr - SPI Slave controller interface instance + * dev - SPI Slave device interface instance + * mode - The SPI Slave mode requested + * nbits - The number of bits requested. + * If value is greater than 0, then it implies MSB first + * If value is less than 0, then it implies LSB first with -nbits * * Returned Value: - * none + * None. * ****************************************************************************/ -static void spi_bind(struct spi_sctrlr_s *sctrlr, - struct spi_sdev_s *sdev, enum spi_smode_e mode, +static void spi_bind(struct spi_slave_ctrlr_s *ctrlr, + struct spi_slave_dev_s *dev, enum spi_slave_mode_e mode, int nbits) { - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)sctrlr; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)ctrlr; uint32_t nss_gpio; - spiinfo("sdev=%p mode=%d nbits=%d\n", sdv, mode, nbits); + spiinfo("dev=%p mode=%d nbits=%d\n", sdv, mode, nbits); - DEBUGASSERT(priv != NULL && priv->sdev == NULL && sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev == NULL && dev != NULL); /* Get exclusive access to the SPI device */ - spi_lock(sctrlr, true); + spi_lock(ctrlr, true); /* Make sure the spi is disabled */ @@ -1136,7 +1139,7 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr, * controller interface. */ - priv->sdev = sdev; + priv->dev = dev; /* Initialize the circular buffer head */ @@ -1144,8 +1147,8 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr, /* Setup to begin normal SPI operation */ - spi_setmode(sctrlr, mode); - spi_setbits(sctrlr, nbits); + spi_setmode(ctrlr, mode); + spi_setbits(ctrlr, nbits); /* First, configure NSS as GPIO EXTI input */ @@ -1166,7 +1169,7 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr, UNUSED(ret); #endif - spi_lock(sctrlr, false); + spi_lock(ctrlr, false); } /**************************************************************************** @@ -1251,33 +1254,33 @@ static int spi_nssinterrupt(int irq, void *context, void *arg) * * Description: * Un-bind the SPI slave device interface from the SPI slave controller - * interface. Reset the SPI interface and restore the SPI slave - * controller driver to its initial state, + * interface. Reset the SPI interface and restore the SPI slave + * controller driver to its initial state. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * none + * None. * ****************************************************************************/ -static void spi_unbind(struct spi_sctrlr_s *sctrlr) +static void spi_unbind(struct spi_slave_ctrlr_s *ctrlr) { - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)sctrlr; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)ctrlr; DEBUGASSERT(priv != NULL); - spiinfo("Unbinding %p\n", priv->sdev); + spiinfo("Unbinding %p\n", priv->dev); - DEBUGASSERT(priv->sdev != NULL); + DEBUGASSERT(priv->dev != NULL); /* Get exclusive access to the SPI device */ - spi_lock(sctrlr, true); + spi_lock(ctrlr, true); /* Unbind the SPI slave interface */ - priv->sdev = NULL; + priv->dev = NULL; /* Disable DMA */ @@ -1288,22 +1291,25 @@ static void spi_unbind(struct spi_sctrlr_s *sctrlr) spi_enable(priv, false); - spi_lock(sctrlr, false); + spi_lock(ctrlr, false); } /**************************************************************************** * Name: spi_enqueue * * Description: - * Enqueue the next value to be shifted out from the interface. This adds + * Enqueue the next value to be shifted out from the interface. This adds * the word the controller driver for a subsequent transfer but has no - * effect on anyin-process or currently "committed" transfers + * effect on any in-process or currently "committed" transfers. * * Input Parameters: - * sctrlr - SPI slave controller interface instance - * data - Command/data mode data value to be shifted out. The width of - * the data must be the same as the nbits parameter previously - * provided to the bind() methods. + * ctrlr - SPI Slave controller interface instance + * data - Pointer to the command/data mode data to be shifted out. + * The data width must be aligned to the nbits parameter which was + * previously provided to the bind() method. + * len - Number of units of "nbits" wide to enqueue, + * "nbits" being the data width previously provided to the bind() + * method. * * Returned Value: * Zero if the word was successfully queue; A negated errno valid is @@ -1312,8 +1318,8 @@ static void spi_unbind(struct spi_sctrlr_s *sctrlr) * ****************************************************************************/ -static int spi_enqueue(struct spi_sctrlr_s *sctrlr, FAR const void *data, - size_t len) +static int spi_enqueue(struct spi_slave_ctrlr_s *ctrlr, + FAR const void *data, size_t len) { return 0; } @@ -1326,14 +1332,14 @@ static int spi_enqueue(struct spi_sctrlr_s *sctrlr, FAR const void *data, * additional word to the queue. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * true if the output wueue is full + * true if the output queue is full, false otherwise. * ****************************************************************************/ -static bool spi_qfull(struct spi_sctrlr_s *sctrlr) +static bool spi_qfull(struct spi_slave_ctrlr_s *ctrlr) { return false; } @@ -1342,24 +1348,24 @@ static bool spi_qfull(struct spi_sctrlr_s *sctrlr) * Name: spi_qflush * * Description: - * Discard all saved values in the output queue. On return from this - * function the output queue will be empty. Any in-progress or otherwise + * Discard all saved values in the output queue. On return from this + * function the output queue will be empty. Any in-progress or otherwise * "committed" output values may not be flushed. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * None + * None. * ****************************************************************************/ -static void spi_qflush(struct spi_sctrlr_s *sctrlr) +static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) { - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)sctrlr; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)ctrlr; irqstate_t flags; - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev != NULL); #ifdef CONFIG_STM32H7_SPI_DMA if (!priv->dmarunning) @@ -1370,7 +1376,7 @@ static void spi_qflush(struct spi_sctrlr_s *sctrlr) /* Get exclusive access to the SPI device */ - spi_lock(sctrlr, true); + spi_lock(ctrlr, true); flags = enter_critical_section(); /* Flush the input buffers */ @@ -1388,7 +1394,7 @@ static void spi_qflush(struct spi_sctrlr_s *sctrlr) priv->ohead = 0; priv->otail = 0; leave_critical_section(flags); - spi_lock(sctrlr, false); + spi_lock(ctrlr, false); } /**************************************************************************** @@ -1435,21 +1441,21 @@ static inline int spi_rx_buffer_free(uint8_t *ptr, int start, int end) * Tell the controller to output all the receive queue data. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: * Number of bytes left in the rx queue. If the device accepted all the * ****************************************************************************/ -static size_t spi_qpoll(struct spi_sctrlr_s *sctrlr) +static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) { - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)sctrlr; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)ctrlr; int itail; int ihead; uint16_t bytes_left; - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev != NULL); DEBUGASSERT(priv->ihead < CONFIG_STM32H7_SPI_SLAVE_QSIZE); #ifdef CONFIG_STM32H7_SPI_DMA @@ -1461,7 +1467,7 @@ static size_t spi_qpoll(struct spi_sctrlr_s *sctrlr) /* Get exclusive access to the SPI device */ - spi_lock(sctrlr, true); + spi_lock(ctrlr, true); #ifdef CONFIG_STM32H7_SPI_DMA itail = CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); @@ -1476,7 +1482,7 @@ static size_t spi_qpoll(struct spi_sctrlr_s *sctrlr) { /* Receive the end of receive buffer */ - priv->ihead += SPI_SDEV_RECEIVE(priv->sdev, + priv->ihead += SPIS_DEV_RECEIVE(priv->dev, (const uint16_t *)&priv->inq[ihead], CONFIG_STM32H7_SPI_SLAVE_QSIZE - ihead); @@ -1491,7 +1497,7 @@ static size_t spi_qpoll(struct spi_sctrlr_s *sctrlr) { /* Receive the data between ihead and itail */ - priv->ihead += SPI_SDEV_RECEIVE(priv->sdev, + priv->ihead += SPIS_DEV_RECEIVE(priv->dev, (const uint16_t *)&priv->inq[ihead], itail - ihead); @@ -1506,7 +1512,7 @@ static size_t spi_qpoll(struct spi_sctrlr_s *sctrlr) ? CONFIG_STM32H7_SPI_SLAVE_QSIZE - priv->ihead + itail : itail - priv->ihead; - spi_lock(sctrlr, false); + spi_lock(ctrlr, false); return bytes_left; } @@ -1731,7 +1737,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) #define GPIO_SPI_NSS(x) GPIO_SPI##x##_NSS #define SPI_SLAVE_INIT_BUS(x) \ - priv = &g_spi##x##sctrlr; \ + priv = &g_spi##x##ctrlr; \ \ /* Only configure if the bus is not already configured */ \ \ @@ -1750,7 +1756,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) priv->initialized = true; \ } -FAR struct spi_sctrlr_s *stm32_spi_slave_initialize(int bus) +FAR struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) { FAR struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1809,10 +1815,10 @@ FAR struct spi_sctrlr_s *stm32_spi_slave_initialize(int bus) /* Initialize the SPI operations */ - priv->sctrlr.ops = &g_sctrlr_ops; + priv->ctrlr.ops = &g_ctrlr_ops; leave_critical_section(flags); - return (FAR struct spi_sctrlr_s *)priv; + return (FAR struct spi_slave_ctrlr_s *)priv; } #endif /* CONFIG_STM32H7_SPI1..6_SLAVE */ diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index b42cb3f5cae..9da6a4dfa09 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -87,10 +87,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void stm32_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Name: showprogress @@ -256,47 +252,6 @@ static inline void stm32_tcmenable(void) #endif } -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -400,17 +355,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c index 2db88e6abd4..aec9c46e2a2 100644 --- a/arch/arm/src/stm32h7/stm32_tim.c +++ b/arch/arm/src/stm32h7/stm32_tim.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -466,24 +467,24 @@ static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET); - val |= ATIM_EGR_UG; - stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); + val |= GTIM_EGR_UG; + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); - val |= ATIM_CR1_CEN; + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); - val &= ~ATIM_CR1_CEN; - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val &= ~GTIM_CR1_CEN; + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /* Reset timer into system default state, but do not affect output/input @@ -641,7 +642,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -651,7 +652,7 @@ static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, @@ -765,18 +766,18 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, source); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); } static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, source, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); } static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~source); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); } /**************************************************************************** @@ -786,7 +787,7 @@ static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode) { - uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; DEBUGASSERT(dev != NULL); @@ -809,13 +810,13 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_MODE_DOWN: - val |= ATIM_CR1_DIR; + val |= GTIM_CR1_DIR; case STM32_TIM_MODE_UP: break; case STM32_TIM_MODE_UPDOWN: - val |= ATIM_CR1_CENTER1; + val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting * down @@ -824,7 +825,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_MODE_PULSE: - val |= ATIM_CR1_OPM; + val |= GTIM_CR1_OPM; break; default: @@ -832,7 +833,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); /* Advanced registers require Main Output Enable */ @@ -885,14 +886,14 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, break; case STM32_TIM_CH_OUTTOGGLE: - ccmr_val = (ATIM_CCMR_MODE_OCREFTOG << ATIM_CCMR1_OC1M_SHIFT); - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT); + ccer_val |= GTIM_CCER_CC1E << (channel << 2); break; case STM32_TIM_CH_OUTPWM: - ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + - ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << (channel << 2); break; default: @@ -903,7 +904,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, if (mode & STM32_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= GTIM_CCER_CC1P << (channel << 2); } /* Define its position (shift) and get register offset */ diff --git a/arch/arm/src/stm32h7/stm32_wwdg.c b/arch/arm/src/stm32h7/stm32_wwdg.c index 1716db6c7ba..28c84cbb01c 100644 --- a/arch/arm/src/stm32h7/stm32_wwdg.c +++ b/arch/arm/src/stm32h7/stm32_wwdg.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index c9e0dd2eec8..9218861409c 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -247,11 +247,17 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); #ifdef CONFIG_STM32H7_SDMMC2 - /* SDMMC clock enable */ + /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif +#ifdef CONFIG_STM32H7_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHB2ENR_RNGEN; +#endif + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } @@ -473,6 +479,18 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SPI5EN; #endif +#ifdef CONFIG_STM32H7_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32H7_USART6 + /* USART6 clock enable */ + + regval |= RCC_APB2ENR_USART6EN; +#endif + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 13464adaf7b..81e7e8a6273 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -246,7 +246,17 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); - /* TODO: ... */ +#ifdef CONFIG_STM32H7_SDMMC2 + /* SDMMC2 clock enable */ + + regval |= RCC_AHB2ENR_SDMMC2EN; +#endif + +#ifdef CONFIG_STM32H7_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHB2ENR_RNGEN; +#endif putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } @@ -469,12 +479,6 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_SDMMC2 - /* SDMMC2 clock enable */ - - regval |= RCC_APB2ENR_SDMMC2EN; -#endif - #ifdef CONFIG_STM32H7_USART1 /* USART1 clock enable */ @@ -482,7 +486,7 @@ static inline void rcc_enableapb2(void) #endif #ifdef CONFIG_STM32H7_USART6 - /* USART1 clock enable */ + /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif @@ -826,8 +830,6 @@ void stm32_stdclockconfig(void) regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_LDOESCUEN; putreg32(regval, STM32_PWR_CR3); -#if 0 - /* Set the voltage output scale */ regval = getreg32(STM32_PWR_D3CR); @@ -839,6 +841,12 @@ void stm32_stdclockconfig(void) { } + /* See Reference manual Section 5.4.1, System supply startup */ + + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) + { + } + /* Over-drive is needed if * - Voltage output scale 1 mode is selected and SYSCLK frequency is * over 400 MHz. @@ -863,7 +871,6 @@ void stm32_stdclockconfig(void) { } } -#endif /* Configure FLASH wait states */ @@ -952,6 +959,15 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D3CCIPR); #endif + /* Configure FDCAN source clock */ + +#if defined(STM32_RCC_D2CCIP1R_FDCANSEL) + regval = getreg32(STM32_RCC_D2CCIP1R); + regval &= ~RCC_D2CCIP1R_FDCANSEL_MASK; + regval |= STM32_RCC_D2CCIP1R_FDCANSEL; + putreg32(regval, STM32_RCC_D2CCIP1R); +#endif + #if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) /* Low speed internal clock source LSI */ diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 59051e66e5e..ca695c82d25 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -63,6 +63,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h index 9780e1e50b0..f136fd465bf 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_adc.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h index 9f1995b1529..570c0e7e741 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_dac.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h index 3438429a8bc..8b6e7ee1dc2 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_flash.h * - * Copyright (C) 2009, 2011, 2015, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h index e9fccd70d05..5c8b7f5a787 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_qspi.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h index c3324083f87..aa04f2ad7df 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h b/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h index 60fec57c252..2e7c7f7ed52 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h * - * Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Miha Vrhovnik + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h index 29fd6d1fec7..022f85b46a0 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_tim.h * - * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -674,6 +658,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1049,6 +1034,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h index 91df0ac382e..99c2797eef7 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_wdg.h * - * Copyright (C) 2009, 2011-2013, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h index f4ce46bd548..70b41aef39f 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h index 4cc1d3300d9..853017ba763 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h * - * Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved. - * Authors: Sebastien Lorquet - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h index 64ac0149d72..ac8e85913d7 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. - * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. - * Author: Gregory Nutt - * Author: Sebastien Lorquet - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h index 5c89eee3194..a05b44c105d 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h index 4e8acff1baf..a70665db86a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h index 2e92797159c..413f4f40bd6 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h index 14f840c614e..32d5c32b3d9 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jussi Kivilinna + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on STM32H7 DMAMUX: - * Author: Mateusz Szafoni + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap.h index 9519b9c3e7f..dbb69c87033 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap.h @@ -465,15 +465,19 @@ #define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN9) #define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN12) #define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN0) +#define GPIO_SPI2_NSS_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN0) #define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN10) #define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN13) #define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN1) +#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN1) #define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN15) #define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN3) #define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN4) +#define GPIO_SPI2_MOSI_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN3) #define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN14) #define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN2) #define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN3) +#define GPIO_SPI2_MISO_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN2) #define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN4) #define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN15) diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h index ae9c021c591..e0fb5350400 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. - * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. - * Author: Gregory Nutt - * Author: Sebastien Lorquet - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index 14938c2a5c8..8769c1d078b 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index c1162ff5bd3..3c986f61590 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -959,12 +959,13 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* Assume that channel is disabled and polarity is active high */ ccer_val = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); if (channel & 1) { diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 5d1890b4d7b..74823337f29 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index 57db13d310f..3932efb01b1 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -41,6 +41,7 @@ ****************************************************************************/ #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index 624f35d0402..07abc3cfad4 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_dac.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -44,6 +28,7 @@ #include #include #include +#include #include #include @@ -809,7 +794,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) /* Reset counters (generate an update) */ #ifdef HAVE_DMA - tim_modifyreg(chan, STM32L4_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG); + tim_modifyreg(chan, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); #endif return OK; } @@ -978,26 +963,26 @@ static int dac_timinit(FAR struct stm32_chan_s *chan) /* Set the reload and prescaler values */ - tim_putreg(chan, STM32L4_BTIM_ARR_OFFSET, (uint16_t)reload); - tim_putreg(chan, STM32L4_BTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + tim_putreg(chan, STM32L4_GTIM_ARR_OFFSET, (uint16_t)reload); + tim_putreg(chan, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); /* Count mode up, auto reload */ - tim_modifyreg(chan, STM32L4_BTIM_CR1_OFFSET, 0, ATIM_CR1_ARPE); + tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Selection TRGO selection: update */ - tim_modifyreg(chan, STM32L4_BTIM_CR2_OFFSET, ATIM_CR2_MMS_MASK, - ATIM_CR2_MMS_UPDATE); + tim_modifyreg(chan, STM32L4_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, + GTIM_CR2_MMS_UPDATE); /* Update DMA request enable ???? */ #if 0 - tim_modifyreg(chan, STM32L4_BTIM_DIER_OFFSET, 0, ATIM_DIER_UDE); + tim_modifyreg(chan, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); #endif /* Enable the counter */ - tim_modifyreg(chan, STM32L4_BTIM_CR1_OFFSET, 0, ATIM_CR1_CEN); + tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); return OK; } #endif diff --git a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h index 2dbb6792b70..95b3a1897c2 100644 --- a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h +++ b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_dbgmcu.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index 7834f50967a..293525edf5d 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_dma.h * - * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Sebastien Lorquet - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -199,9 +182,9 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chan); * hardware/stm32l4xrxx_dmamux.h * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * * Assumptions: * - The caller does not hold he DMA channel. diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index c0d6426481d..adb62ec42ce 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -30,6 +30,7 @@ #define CONFIG_DEBUG_INFO 1 #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index c4a4295b50b..834e9394f0b 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_exti_alarm.c * - * Copyright (C) 2009, 2012, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Diego Sanchez - * dev@ziggurat29.com (adaptation to stm32l4) + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c index 43ed0adc7b0..f50b794b766 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_exti_wakeup.c * - * Copyright (C) 2009, 2012, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index 6445b7d9246..041ad5f5c2e 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -54,6 +54,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_flash.h b/arch/arm/src/stm32l4/stm32l4_flash.h index 9a4886d3806..a4247e92cb8 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/stm32l4_flash.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_flash.h * - * Copyright (C) 2009, 2011, 2015, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c index d3ceb346fb8..f5b7fde1dc8 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ b/arch/arm/src/stm32l4/stm32l4_freerun.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_freerun.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the names NuttX nor Atmel nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h index fac8072574a..fdf63d1e366 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ b/arch/arm/src/stm32l4/stm32l4_freerun.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_freerun.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index aa21991ffce..7e44ac24cc8 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -267,6 +267,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index cf79a57f1dc..5e8997edcba 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index 1fcd9bd57cd..266ed39f6eb 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_iwdg.c * - * Copyright (C) 2012, 2016, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -41,7 +25,8 @@ #include #include -#include +#include +#include #include #include @@ -329,7 +314,7 @@ static int stm32l4_start(FAR struct watchdog_lowerhalf_s *lower) (FAR struct stm32l4_lowerhalf_s *)lower; irqstate_t flags; - wdinfo("Entry: started=%d\n"); + wdinfo("Entry: started\n"); DEBUGASSERT(priv); /* Have we already been started? */ @@ -469,9 +454,9 @@ static int stm32l4_getstatus(FAR struct watchdog_lowerhalf_s *lower, status->timeleft = priv->timeout - elapsed; wdinfo("Status :\n"); - wdinfo(" flags : %08x\n", status->flags); - wdinfo(" timeout : %d\n", status->timeout); - wdinfo(" timeleft : %d\n", status->timeleft); + wdinfo(" flags : %08" PRIx32 "\n", status->flags); + wdinfo(" timeout : %" PRId32 "\n", status->timeout); + wdinfo(" timeleft : %" PRId32 "\n", status->timeleft); return OK; } @@ -501,14 +486,14 @@ static int stm32l4_settimeout(FAR struct watchdog_lowerhalf_s *lower, int prescaler; int shift; - wdinfo("Entry: timeout=%d\n", timeout); + wdinfo("Entry: timeout=%" PRId32 "\n", timeout); DEBUGASSERT(priv); /* Can this timeout be represented? */ if (timeout < 1 || timeout > IWDG_MAXTIMEOUT) { - wderr("ERROR: Cannot represent timeout=%d > %d\n", + wderr("ERROR: Cannot represent timeout=%" PRId32 " > %d\n", timeout, IWDG_MAXTIMEOUT); return -ERANGE; } @@ -590,7 +575,8 @@ static int stm32l4_settimeout(FAR struct watchdog_lowerhalf_s *lower, stm32l4_setprescaler(priv); } - wdinfo("prescaler=%d fiwdg=%d reload=%d\n", prescaler, fiwdg, reload); + wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n", + prescaler, fiwdg, reload); return OK; } @@ -621,7 +607,7 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq) { FAR struct stm32l4_lowerhalf_s *priv = &g_wdgdev; - wdinfo("Entry: devpath=%s lsifreq=%d\n", devpath, lsifreq); + wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq); /* NOTE we assume that clocking to the IWDG has already been provided by * the RCC initialization logic. @@ -641,7 +627,7 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq) */ stm32l4_rcc_enablelsi(); - wdinfo("RCC CSR: %08x\n", getreg32(STM32L4_RCC_CSR)); + wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32L4_RCC_CSR)); /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index 3dff839e07d..3a8f7445d97 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -76,6 +76,7 @@ #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index d550caa3e4a..6d73202a9b6 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_lse.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c index aa9905b17c0..b10398f8e3c 100644 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ b/arch/arm/src/stm32l4/stm32l4_lsi.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_lsi.c * - * Copyright (C) 2012, 2015-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index 5bd7e3a8083..63541b8af92 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_oneshot.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the names NuttX nor Atmel nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h index 9a36ec02ad6..475023b8573 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_oneshot.h * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c index f256e31a95a..28374bbfe79 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index f827feb02fb..a92066e5bf2 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_otgfs.h * - * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index 93ed1a58ef5..89b98923ac3 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_otgfsdev.c * - * Copyright (C) 2012-2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -41,10 +25,11 @@ #include #include -#include +#include #include #include #include +#include #include #include @@ -2805,7 +2790,7 @@ static inline void stm32l4_epout_interrupt(FAR struct stm32l4_usbdev_s *priv) if ((daint & 1) != 0) { regval = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); - uinfo("DOEPINT(%d) = %08x\n", epno, regval); + uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(epno)); } @@ -3049,7 +3034,7 @@ static inline void stm32l4_epin_interrupt(FAR struct stm32l4_usbdev_s *priv) { if ((daint & 1) != 0) { - uerr("DIEPINT(%d) = %08x\n", + uerr("DIEPINT(%d) = %08" PRIx32 "\n", epno, stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno))); stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(epno)); } @@ -5725,7 +5710,7 @@ void arm_usbinitialize(void) ret = irq_attach(STM32L4_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); if (ret < 0) { - uerr("irq_attach failed\n", ret); + uerr("ERROR: irq_attach failed: %d\n", ret); goto errout; } diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index d158a63e38e..b365d419863 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_otgfshost.c * - * Copyright (C) 2012-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -46,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_pmsleep.c b/arch/arm/src/stm32l4/stm32l4_pmsleep.c index e3b49d30092..7e448a9fa97 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmsleep.c +++ b/arch/arm/src/stm32l4/stm32l4_pmsleep.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_pmsleep.c * - * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index f16856077fc..2e4c8c8d079 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -473,7 +473,7 @@ static struct stm32l4_pwmchan_s g_pwm1channels[] = .in_use = 1, .pol = CONFIG_STM32L4_TIM1_CH5POL, .idle = CONFIG_STM32L4_TIM1_CH5IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif }, @@ -488,7 +488,7 @@ static struct stm32l4_pwmchan_s g_pwm1channels[] = .in_use = 1, .pol = CONFIG_STM32L4_TIM1_CH6POL, .idle = CONFIG_STM32L4_TIM1_CH6IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif } @@ -1034,7 +1034,7 @@ static struct stm32l4_pwmchan_s g_pwm8channels[] = .in_use = 1, .pol = CONFIG_STM32L4_TIM8_CH5POL, .idle = CONFIG_STM32L4_TIM8_CH5IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif }, @@ -1049,7 +1049,7 @@ static struct stm32l4_pwmchan_s g_pwm8channels[] = .in_use = 1, .pol = CONFIG_STM32L4_TIM8_CH6POL, .idle = CONFIG_STM32L4_TIM8_CH6IDLE, - .pincfg = 0, /* No available externaly */ + .pincfg = 0, /* Not available externally */ } #endif } @@ -2240,13 +2240,13 @@ static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, case STM32L4_CHANMODE_PWM1: { - chanmode = ATIM_CCMR_MODE_PWM1; + chanmode = GTIM_CCMR_MODE_PWM1; break; } case STM32L4_CHANMODE_PWM2: { - chanmode = ATIM_CCMR_MODE_PWM2; + chanmode = GTIM_CCMR_MODE_PWM2; break; } @@ -2339,30 +2339,30 @@ static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, { /* Reset current channel 1/3/5 mode configuration */ - ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE); + ccmr &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_OC1M_MASK | + GTIM_CCMR1_OC1PE); /* Configure CC1/3/5 as output */ - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); + ocmode |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC1S_SHIFT); /* Configure Compare 1/3/5 mode */ - ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); + ocmode |= (chanmode << GTIM_CCMR1_OC1M_SHIFT); /* Enable CCR1/3/5 preload */ - ocmode |= ATIM_CCMR1_OC1PE; + ocmode |= GTIM_CCMR1_OC1PE; /* Reset current OC bit */ - ccmr &= ~(ATIM_CCMR1_OC1M); + ccmr &= ~(GTIM_CCMR1_OC1M); /* Set an additional OC1/3/5M bit */ if (ocmbit) { - ocmode |= ATIM_CCMR1_OC1M; + ocmode |= GTIM_CCMR1_OC1M; } break; } @@ -2375,30 +2375,30 @@ static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, { /* Reset current channel 2/4/6 mode configuration */ - ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE); + ccmr &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_OC2M_MASK | + GTIM_CCMR1_OC2PE); /* Configure CC2/4/6 as output */ - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); + ocmode |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC2S_SHIFT); /* Configure Compare 2/4/6 mode */ - ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); + ocmode |= (chanmode << GTIM_CCMR1_OC2M_SHIFT); /* Enable CCR2/4/6 preload */ - ocmode |= ATIM_CCMR1_OC2PE; + ocmode |= GTIM_CCMR1_OC2PE; /* Reset current OC bit */ - ccmr &= ~(ATIM_CCMR1_OC2M); + ccmr &= ~(GTIM_CCMR1_OC2M); /* Set an additioneal OC2/4/6M bit */ if (ocmbit) { - ocmode |= ATIM_CCMR1_OC2M; + ocmode |= GTIM_CCMR1_OC2M; } break; } @@ -2550,13 +2550,13 @@ static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev, /* Get outputs configuration */ - regval |= ((outputs & STM32L4_PWM_OUT1) ? ATIM_CCER_CC1E : 0); + regval |= ((outputs & STM32L4_PWM_OUT1) ? GTIM_CCER_CC1E : 0); regval |= ((outputs & STM32L4_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT2) ? ATIM_CCER_CC2E : 0); + regval |= ((outputs & STM32L4_PWM_OUT2) ? GTIM_CCER_CC2E : 0); regval |= ((outputs & STM32L4_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT3) ? ATIM_CCER_CC3E : 0); + regval |= ((outputs & STM32L4_PWM_OUT3) ? GTIM_CCER_CC3E : 0); regval |= ((outputs & STM32L4_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT4) ? ATIM_CCER_CC4E : 0); + regval |= ((outputs & STM32L4_PWM_OUT4) ? GTIM_CCER_CC4E : 0); /* NOTE: CC4N does not exist, but some docs show configuration bits for it */ @@ -2636,7 +2636,7 @@ static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev) { FAR struct stm32l4_pwmtimer_s *priv = (FAR struct stm32l4_pwmtimer_s *)dev; - pwm_putreg(priv, STM32L4_GTIM_EGR_OFFSET, ATIM_EGR_UG); + pwm_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); return OK; } @@ -3009,7 +3009,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, */ priv->prev = pwm_pulsecount(info->count); - pwm_putreg(priv, STM32L4_ATIM_RCR_OFFSET, (uint16_t)priv->prev - 1); + pwm_putreg(priv, STM32L4_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should * preload the RCR into active repetition counter. @@ -3023,7 +3023,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, priv->count = info->count; priv->curr = pwm_pulsecount(info->count - priv->prev); - pwm_putreg(priv, STM32L4_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); + pwm_putreg(priv, STM32L4_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } /* Otherwise, just clear the repetition counter */ @@ -3032,7 +3032,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, { /* Set the repetition counter to zero */ - pwm_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); + pwm_putreg(priv, STM32L4_GTIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ @@ -3061,7 +3061,7 @@ static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, /* Clear all pending interrupts and enable the update interrupt. */ pwm_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); - pwm_putreg(priv, STM32L4_GTIM_DIER_OFFSET, ATIM_DIER_UIE); + pwm_putreg(priv, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index 46ff34ece47..a51e4ae8296 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_pwr.c * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved. - * Authors: Uros Platise - * Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h index f1f7a8de1ff..dafe535d977 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_pwr.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_pwr.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 26a5d1aa888..20620dea11b 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_qencoder.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index e5b4f21a80f..0c3128193d8 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_qspi.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.h b/arch/arm/src/stm32l4/stm32l4_qspi.h index 85a7aae4211..a0255ba8969 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/stm32l4_qspi.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_qspi.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index 32efca02971..57ec9e1d6f3 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_rtc.c * - * Copyright (C) 2012-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com (adaptations to stm32l4) - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -45,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index 128415924e8..e58a5bf66ed 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -1,39 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_rtc.h * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved. - * Author: Uros Platise (Original for the F1) - * Gregory Nutt (On-going support and - * development) - * dev@ziggurat29.com (adaptations for STM32L4) + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index e36bd0b16b8..9a934c5570b 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com (adaptations for stm32l4) + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index ec09890a4f2..77f6d70eddb 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_sdmmc.c * - * Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Miha Vrhovnik + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.h b/arch/arm/src/stm32l4/stm32l4_sdmmc.h index 1fa6c7aefe4..476fa314dbf 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.h +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_sdmmc.h * - * Copyright (C) 2009, 2011, 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Miha Vrhovnik + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index fc474bdf815..78d0d2a340e 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index 7c5ad8951ee..a29e98ea1a3 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -59,6 +59,7 @@ #include #include #include +#include #include #include @@ -1333,7 +1334,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index bbd38b6ee1d..eacb5bd4c5c 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -83,10 +83,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void stm32l4_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Private Functions @@ -206,47 +202,6 @@ static inline void stm32l4_fpuconfig(void) # define stm32l4_fpuconfig() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -349,17 +304,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index 0cd5007ba38..0be9e7c1946 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_tickless.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -89,6 +73,7 @@ #include #include +#include #include #include "stm32l4_oneshot.h" diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index f1e62e9b680..f6ca85ff76b 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -1,41 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_tim.c * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * With modifications and updates by: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2011-2012, 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -50,6 +29,7 @@ #include #include #include +#include #include #include @@ -507,9 +487,9 @@ static inline void stm32l4_putreg32(FAR struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_reload_counter(FAR struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_BTIM_EGR_OFFSET); - val |= ATIM_EGR_UG; - stm32l4_putreg16(dev, STM32L4_BTIM_EGR_OFFSET, val); + uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_EGR_OFFSET); + val |= GTIM_EGR_UG; + stm32l4_putreg16(dev, STM32L4_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -518,11 +498,11 @@ static void stm32l4_tim_reload_counter(FAR struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_BTIM_CR1_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); - val |= ATIM_CR1_CEN; + val |= GTIM_CR1_CEN; stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_BTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -531,9 +511,9 @@ static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_disable(FAR struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_BTIM_CR1_OFFSET); - val &= ~ATIM_CR1_CEN; - stm32l4_putreg16(dev, STM32L4_BTIM_CR1_OFFSET, val); + uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + val &= ~GTIM_CR1_CEN; + stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -633,7 +613,7 @@ static void stm32l4_tim_dumpregs(FAR struct stm32l4_tim_dev_s *dev) static int stm32l4_tim_setmode(FAR struct stm32l4_tim_dev_s *dev, enum stm32l4_tim_mode_e mode) { - uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; DEBUGASSERT(dev != NULL); @@ -663,15 +643,15 @@ static int stm32l4_tim_setmode(FAR struct stm32l4_tim_dev_s *dev, break; case STM32L4_TIM_MODE_DOWN: - val |= ATIM_CR1_DIR; + val |= GTIM_CR1_DIR; break; case STM32L4_TIM_MODE_UP: - val &= ~ATIM_CR1_DIR; + val &= ~GTIM_CR1_DIR; break; case STM32L4_TIM_MODE_UPDOWN: - val |= ATIM_CR1_CENTER1; + val |= GTIM_CR1_CENTER1; /* Our default: * Interrupts are generated on compare, when counting down @@ -680,7 +660,7 @@ static int stm32l4_tim_setmode(FAR struct stm32l4_tim_dev_s *dev, break; case STM32L4_TIM_MODE_PULSE: - val |= ATIM_CR1_OPM; + val |= GTIM_CR1_OPM; break; default: @@ -688,7 +668,7 @@ static int stm32l4_tim_setmode(FAR struct stm32l4_tim_dev_s *dev, } stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_BTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); #if STM32L4_NATIM > 0 /* Advanced registers require Main Output Enable */ @@ -983,7 +963,7 @@ static int stm32l4_tim_setclock(FAR struct stm32l4_tim_dev_s *dev, prescaler = 0xffff; } - stm32l4_putreg16(dev, STM32L4_BTIM_PSC_OFFSET, prescaler); + stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler); return prescaler; } @@ -1074,7 +1054,7 @@ static uint32_t stm32l4_tim_getclock(FAR struct stm32l4_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l4_getreg16(dev, STM32L4_BTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET) + 1); return clock; } @@ -1086,7 +1066,7 @@ static void stm32l4_tim_setperiod(FAR struct stm32l4_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l4_putreg32(dev, STM32L4_BTIM_ARR_OFFSET, period); + stm32l4_putreg32(dev, STM32L4_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -1096,7 +1076,7 @@ static void stm32l4_tim_setperiod(FAR struct stm32l4_tim_dev_s *dev, static uint32_t stm32l4_tim_getperiod (FAR struct stm32l4_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l4_getreg32 (dev, STM32L4_BTIM_ARR_OFFSET); + return stm32l4_getreg32 (dev, STM32L4_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -1106,7 +1086,7 @@ static uint32_t stm32l4_tim_getperiod (FAR struct stm32l4_tim_dev_s *dev) static uint32_t stm32l4_tim_getcounter(FAR struct stm32l4_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l4_getreg32(dev, STM32L4_BTIM_CNT_OFFSET); + uint32_t counter = stm32l4_getreg32(dev, STM32L4_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -1157,7 +1137,8 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET); - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -1184,9 +1165,9 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev, break; case STM32L4_TIM_CH_OUTPWM: - ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + - ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -1197,7 +1178,7 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev, if (mode & STM32L4_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ @@ -1695,7 +1676,7 @@ static void stm32l4_tim_enableint(FAR struct stm32l4_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); + stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1706,7 +1687,7 @@ static void stm32l4_tim_disableint(FAR struct stm32l4_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); + stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1715,7 +1696,7 @@ static void stm32l4_tim_disableint(FAR struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_ackint(FAR struct stm32l4_tim_dev_s *dev, int source) { - stm32l4_putreg16(dev, STM32L4_BTIM_SR_OFFSET, ~ATIM_SR_UIF); + stm32l4_putreg16(dev, STM32L4_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1725,8 +1706,8 @@ static void stm32l4_tim_ackint(FAR struct stm32l4_tim_dev_s *dev, int source) static int stm32l4_tim_checkint(FAR struct stm32l4_tim_dev_s *dev, int source) { - uint16_t regval = stm32l4_getreg16(dev, STM32L4_BTIM_SR_OFFSET); - return (regval & ATIM_SR_UIF) ? 1 : 0; + uint16_t regval = stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET); + return (regval & GTIM_SR_UIF) ? 1 : 0; } /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index d887ec61d17..feda212b0a1 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -1,42 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_tim.h * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * With modifications and updates by: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2011-2012, 2016, 2018 Gregory Nutt. - * All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index 3cf016b86e5..e31ee5d085e 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -48,6 +48,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index e2416bc1b69..7beab90a531 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h index ac604e4fd5d..be1695408ea 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost.h +++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_usbhost.h * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c index e7154c5b323..ce9330d9b45 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c +++ b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4_usbhost_trace.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index b4b2653cd62..88265af5016 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4x3xx_rcc.c * - * Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved. - * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. - * Authors: Gregory Nutt - * Sebastien Lorquet - * Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index b1b52d3be49..62e8120dcbc 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4x6xx_dma.c * - * Copyright (C) 2009, 2011-2013, 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Sebastien Lorquet - * dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index b45a1f74266..6b10fe50177 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -1,43 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l4/stm32l4xrxx_dma.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Jussi Kivilinna + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on STM32H7 DMAMUX/DMA driver: - * Author: Mateusz Szafoni + * http://www.apache.org/licenses/LICENSE-2.0 * - * Based on STM32L4X6XX DMA driver: - * Author: Gregory Nutt - * Author: Sebastien Lorquet - * Author: dev@ziggurat29.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -50,6 +27,7 @@ #include #include #include +#include #include #include @@ -1022,9 +1000,9 @@ void weak_function arm_dma_initialize(void) * in hardware/stm32l4xrxx_dmamux.h * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * * Assumptions: * - The caller does not hold he DMA channel. diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index 32a6b637da5..5c60d10e9f4 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -416,7 +416,7 @@ endchoice if STM32L5_RTC_LSECLOCK config STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automaticaly boost the LSE oscillator drive capability level until it starts-up" + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" default n ---help--- This will cycle through the values from low to high. To avoid diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index ec53d494b9e..0ce8155a11d 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -64,6 +64,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h index 0675e025d7d..e673f9c0af7 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h @@ -625,6 +625,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -970,6 +971,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index 1258bc30b05..7f3a1f2ba05 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -30,6 +30,7 @@ #define CONFIG_DEBUG_INFO 1 #include +#include #include #include diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c index f1495e04207..98b9f6a172f 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c @@ -28,6 +28,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index e0b76f02c6a..91aa0df3e8e 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -37,6 +37,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index 18d3fabc68c..db1d6f63fbf 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index 50f8fd448f8..026afecf24d 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -1,40 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l5/stm32l5_lse.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Michael Jung + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on arch/arm/src/stm32l4/stm32l4_lse.c + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c index 4c991f2a3d0..7da5d1ee7b6 100644 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ b/arch/arm/src/stm32l5/stm32l5_lsi.c @@ -1,41 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l5/stm32l5_lsi.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Authors: Michael Jung + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on arch/arm/src/stm32l4/stm32l4_lsi.c + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2012, 2015-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Juha Niskanen - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index b4cb5b8e94d..b994415980b 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index f8b2456d870..b679c151b58 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -60,6 +60,7 @@ #include #include #include +#include #include #include @@ -1342,7 +1343,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchaned in units of words. + * nwords - the length of data to be exchanged in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 715e8bea4ff..689fb2bc515 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -85,10 +85,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE; #ifdef CONFIG_ARCH_FPU static inline void stm32l5_fpuconfig(void); #endif -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Private Functions @@ -209,47 +205,6 @@ static inline void stm32l5_fpuconfig(void) # define stm32l5_fpuconfig() #endif -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -352,17 +307,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shoulnd't get here */ for (; ; ); -#endif } diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index 93009cdfbe6..c2379d90428 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -1,46 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l5/stm32l5_tim.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Michael Jung + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on arm/arm/src/stm32l4/stm32l4_tim.c + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise - * - * With modifications and updates by: - * - * Copyright (C) 2011-2012, 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -56,6 +30,7 @@ #include #include #include +#include #include #include @@ -506,9 +481,9 @@ static inline void stm32l5_putreg32(FAR struct stm32l5_tim_dev_s *dev, static void stm32l5_tim_reload_counter(FAR struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_BTIM_EGR_OFFSET); - val |= ATIM_EGR_UG; - stm32l5_putreg16(dev, STM32L5_BTIM_EGR_OFFSET, val); + uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_EGR_OFFSET); + val |= GTIM_EGR_UG; + stm32l5_putreg16(dev, STM32L5_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -517,10 +492,10 @@ static void stm32l5_tim_reload_counter(FAR struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_enable(FAR struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_BTIM_CR1_OFFSET); - val |= ATIM_CR1_CEN; + uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + val |= GTIM_CR1_CEN; stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_BTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -529,9 +504,9 @@ static void stm32l5_tim_enable(FAR struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_disable(FAR struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_BTIM_CR1_OFFSET); - val &= ~ATIM_CR1_CEN; - stm32l5_putreg16(dev, STM32L5_BTIM_CR1_OFFSET, val); + uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + val &= ~GTIM_CR1_CEN; + stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -581,7 +556,7 @@ static void stm32l5_tim_gpioconfig(uint32_t cfg, static int stm32l5_tim_setmode(FAR struct stm32l5_tim_dev_s *dev, enum stm32l5_tim_mode_e mode) { - uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; DEBUGASSERT(dev != NULL); @@ -611,13 +586,13 @@ static int stm32l5_tim_setmode(FAR struct stm32l5_tim_dev_s *dev, break; case STM32L5_TIM_MODE_DOWN: - val |= ATIM_CR1_DIR; + val |= GTIM_CR1_DIR; case STM32L5_TIM_MODE_UP: break; case STM32L5_TIM_MODE_UPDOWN: - val |= ATIM_CR1_CENTER1; + val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting * down @@ -626,7 +601,7 @@ static int stm32l5_tim_setmode(FAR struct stm32l5_tim_dev_s *dev, break; case STM32L5_TIM_MODE_PULSE: - val |= ATIM_CR1_OPM; + val |= GTIM_CR1_OPM; break; default: @@ -634,7 +609,7 @@ static int stm32l5_tim_setmode(FAR struct stm32l5_tim_dev_s *dev, } stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_BTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); #if STM32L5_NATIM > 0 /* Advanced registers require Main Output Enable */ @@ -768,7 +743,7 @@ static int stm32l5_tim_setclock(FAR struct stm32l5_tim_dev_s *dev, prescaler = 0xffff; } - stm32l5_putreg16(dev, STM32L5_BTIM_PSC_OFFSET, prescaler); + stm32l5_putreg16(dev, STM32L5_GTIM_PSC_OFFSET, prescaler); stm32l5_tim_enable(dev); return prescaler; @@ -860,7 +835,7 @@ static uint32_t stm32l5_tim_getclock(FAR struct stm32l5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l5_getreg16(dev, STM32L5_BTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32l5_getreg16(dev, STM32L5_GTIM_PSC_OFFSET) + 1); return clock; } @@ -872,7 +847,7 @@ static void stm32l5_tim_setperiod(FAR struct stm32l5_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l5_putreg32(dev, STM32L5_BTIM_ARR_OFFSET, period); + stm32l5_putreg32(dev, STM32L5_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -882,7 +857,7 @@ static void stm32l5_tim_setperiod(FAR struct stm32l5_tim_dev_s *dev, static uint32_t stm32l5_tim_getperiod (FAR struct stm32l5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l5_getreg32 (dev, STM32L5_BTIM_ARR_OFFSET); + return stm32l5_getreg32 (dev, STM32L5_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -892,7 +867,7 @@ static uint32_t stm32l5_tim_getperiod (FAR struct stm32l5_tim_dev_s *dev) static uint32_t stm32l5_tim_getcounter(FAR struct stm32l5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l5_getreg32(dev, STM32L5_BTIM_CNT_OFFSET); + uint32_t counter = stm32l5_getreg32(dev, STM32L5_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -943,7 +918,8 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ ccer_val = stm32l5_getreg16(dev, STM32L5_GTIM_CCER_OFFSET); - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -970,9 +946,9 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev, break; case STM32L5_TIM_CH_OUTPWM: - ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + - ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -983,7 +959,7 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev, if (mode & STM32L5_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ @@ -1481,7 +1457,7 @@ static void stm32l5_tim_enableint(FAR struct stm32l5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); + stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1492,7 +1468,7 @@ static void stm32l5_tim_disableint(FAR struct stm32l5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); + stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1501,7 +1477,7 @@ static void stm32l5_tim_disableint(FAR struct stm32l5_tim_dev_s *dev, static void stm32l5_tim_ackint(FAR struct stm32l5_tim_dev_s *dev, int source) { - stm32l5_putreg16(dev, STM32L5_BTIM_SR_OFFSET, ~ATIM_SR_UIF); + stm32l5_putreg16(dev, STM32L5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1511,8 +1487,8 @@ static void stm32l5_tim_ackint(FAR struct stm32l5_tim_dev_s *dev, int source) static int stm32l5_tim_checkint(FAR struct stm32l5_tim_dev_s *dev, int source) { - uint16_t regval = stm32l5_getreg16(dev, STM32L5_BTIM_SR_OFFSET); - return (regval & ATIM_SR_UIF) ? 1 : 0; + uint16_t regval = stm32l5_getreg16(dev, STM32L5_GTIM_SR_OFFSET); + return (regval & GTIM_SR_UIF) ? 1 : 0; } /**************************************************************************** diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h index 91cefca898c..820c5b92a91 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/stm32l5_tim.h @@ -1,46 +1,20 @@ /**************************************************************************** * arch/arm/src/stm32l5/stm32l5_tim.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Michael Jung + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on arch/arm/src/stm32l4/stm32l4_tim.h + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise - * - * With modifications and updates by: - * - * Copyright (C) 2011-2012, 2016, 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * dev@ziggurat29.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index 9952e2baae8..199d5a8fb3d 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/str71x/str71x_serial.c b/arch/arm/src/str71x/str71x_serial.c index 820df0b516c..7f91160ea6c 100644 --- a/arch/arm/src/str71x/str71x_serial.c +++ b/arch/arm/src/str71x/str71x_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs index 272de114aa8..2483799a861 100644 --- a/arch/arm/src/tiva/Make.defs +++ b/arch/arm/src/tiva/Make.defs @@ -65,6 +65,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c + CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S else diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_gpio.h b/arch/arm/src/tiva/cc13xx/cc13xx_gpio.h index f10f8962866..0b495b3f35d 100644 --- a/arch/arm/src/tiva/cc13xx/cc13xx_gpio.h +++ b/arch/arm/src/tiva/cc13xx/cc13xx_gpio.h @@ -1,37 +1,20 @@ /**************************************************************************** * arch/arm/src/tiva/cc13xx/cc13xx_gpio.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * With modifications from Calvin Maguranis + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/common/tiva_dumpgpio.c b/arch/arm/src/tiva/common/tiva_dumpgpio.c index 2f4dfa14a9e..6e9fa7cc85b 100644 --- a/arch/arm/src/tiva/common/tiva_dumpgpio.c +++ b/arch/arm/src/tiva/common/tiva_dumpgpio.c @@ -24,6 +24,8 @@ #include +#include + /* Output debug info even if debug output is not selected. */ #undef CONFIG_DEBUG_INFO diff --git a/arch/arm/src/tiva/common/tiva_eeprom.c b/arch/arm/src/tiva/common/tiva_eeprom.c index 491f8b4d344..16fadbce84e 100644 --- a/arch/arm/src/tiva/common/tiva_eeprom.c +++ b/arch/arm/src/tiva/common/tiva_eeprom.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/tiva/common/tiva_eeprom.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Shirshak Sengupta - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/common/tiva_hciuart.c b/arch/arm/src/tiva/common/tiva_hciuart.c index 1e1fd238311..33b67088018 100644 --- a/arch/arm/src/tiva/common/tiva_hciuart.c +++ b/arch/arm/src/tiva/common/tiva_hciuart.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/tiva/common/tiva_irq.c b/arch/arm/src/tiva/common/tiva_irq.c index 4abbf99df03..f8d86d317f6 100644 --- a/arch/arm/src/tiva/common/tiva_irq.c +++ b/arch/arm/src/tiva/common/tiva_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/tiva/common/tiva_serial.c b/arch/arm/src/tiva/common/tiva_serial.c index ffbd617cb51..5ae6c4d260b 100644 --- a/arch/arm/src/tiva/common/tiva_serial.c +++ b/arch/arm/src/tiva/common/tiva_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/tiva/common/tiva_ssi.c b/arch/arm/src/tiva/common/tiva_ssi.c index a0cd2952505..e497f6122e7 100644 --- a/arch/arm/src/tiva/common/tiva_ssi.c +++ b/arch/arm/src/tiva/common/tiva_ssi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -1250,19 +1251,19 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv, switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = SSI_CR0_SPH; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = SSI_CR0_SPO; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = SSI_CR0_SPH | SSI_CR0_SPO; break; diff --git a/arch/arm/src/tiva/hardware/tiva_eeprom.h b/arch/arm/src/tiva/hardware/tiva_eeprom.h index 4c6a1e0692d..380ef1ab9f6 100644 --- a/arch/arm/src/tiva/hardware/tiva_eeprom.h +++ b/arch/arm/src/tiva/hardware/tiva_eeprom.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/tiva/hardware/tiva_eeprom.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Shirshak Sengupta - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/lm/lm3s_ethernet.c b/arch/arm/src/tiva/lm/lm3s_ethernet.c index 2a7cff13a14..68c95ad47f6 100644 --- a/arch/arm/src/tiva/lm/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm/lm3s_ethernet.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/tiva/lm/lm3s_gpio.h b/arch/arm/src/tiva/lm/lm3s_gpio.h index a79b2d21000..aa83bc294d0 100644 --- a/arch/arm/src/tiva/lm/lm3s_gpio.h +++ b/arch/arm/src/tiva/lm/lm3s_gpio.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/tiva/lm/lm3s_gpio.h * - * Copyright (C) 2009-2010, 2013-2015, 2017-2018 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * With modifications from Calvin Maguranis + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/lm/lm4f_gpio.h b/arch/arm/src/tiva/lm/lm4f_gpio.h index e1194042e70..3239cc3c98c 100644 --- a/arch/arm/src/tiva/lm/lm4f_gpio.h +++ b/arch/arm/src/tiva/lm/lm4f_gpio.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/tiva/lm/lm4f_gpio.h * - * Copyright (C) 2009-2010, 2013-2015, 2017-2018 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * With modifications from Calvin Maguranis + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/tiva_eeprom.h b/arch/arm/src/tiva/tiva_eeprom.h index da6e1c4aacf..add33f15fbe 100644 --- a/arch/arm/src/tiva/tiva_eeprom.h +++ b/arch/arm/src/tiva/tiva_eeprom.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/arm/src/tiva/tiva_eeprom.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Shirshak Sengupta - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/tiva_gpio.h b/arch/arm/src/tiva/tiva_gpio.h index 608b8a43d47..4ac0730b2a2 100644 --- a/arch/arm/src/tiva/tiva_gpio.h +++ b/arch/arm/src/tiva/tiva_gpio.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/tiva/tiva_gpio.h * - * Copyright (C) 2009-2010, 2013-2015, 2017-2018 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * With modifications from Calvin Maguranis + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/tm4c/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c/tm4c_ethernet.c index 0e5e1454224..9d48a6b0e39 100644 --- a/arch/arm/src/tiva/tm4c/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c/tm4c_ethernet.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/tiva/tm4c/tm4c_gpio.h b/arch/arm/src/tiva/tm4c/tm4c_gpio.h index 849aaf1674e..a7e0b3bcd80 100644 --- a/arch/arm/src/tiva/tm4c/tm4c_gpio.h +++ b/arch/arm/src/tiva/tm4c/tm4c_gpio.h @@ -1,38 +1,20 @@ /**************************************************************************** * arch/arm/src/tiva/tm4c/tm4c_gpio.h * - * Copyright (C) 2009-2010, 2013-2015, 2017-2018 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * With modifications from Calvin Maguranis + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs index 98d5ce56674..6899d55786a 100644 --- a/arch/arm/src/tms570/Make.defs +++ b/arch/arm/src/tms570/Make.defs @@ -59,6 +59,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index f83f6803538..3b1f1ec972c 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -203,69 +203,6 @@ static void tms570_memory_initialize(uint32_t ramset) putreg32(SYS_MINITGCR_DISABLE, TMS570_SYS_MINITGCR); } -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Re-initialize the stack and frame pointers and branch to OS start. - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - naked_function noreturn_function; - -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tldr ip, =g_idle_topstack\n" /* IP=address of g_idle_topstack */ - "\tldr sp, [ip]\n" /* Reset the stack pointer */ - "\tmov fp, #0\n" /* Reset the frame pointer */ - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} - -#else -static void go_nx_start(void) naked_function noreturn_function; - -static void go_nx_start(void) -{ - /* Reset the stack/frame pointer and jump to nx_start(). */ - - __asm__ __volatile__ - ( - "\tldr ip, =g_idle_topstack\n" /* IP=address of g_idle_topstack */ - "\tldr sp, [ip]\n" /* Reset the stack pointer */ - "\tmov fp, #0\n" /* Reset the frame pointer */ - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -478,13 +415,5 @@ void arm_boot(void) /* Then start NuttX */ -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Branch to nx_start(), resetting the stack and frame pointers. */ - - go_nx_start(); -#endif + nx_start(); } diff --git a/arch/arm/src/tms570/tms570_esm.c b/arch/arm/src/tms570/tms570_esm.c index 48c7224f0e1..63a6c556582 100644 --- a/arch/arm/src/tms570/tms570_esm.c +++ b/arch/arm/src/tms570/tms570_esm.c @@ -48,6 +48,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/tms570/tms570_lowputc.c b/arch/arm/src/tms570/tms570_lowputc.c index e80e05c37fe..4da39da855d 100644 --- a/arch/arm/src/tms570/tms570_lowputc.c +++ b/arch/arm/src/tms570/tms570_lowputc.c @@ -46,6 +46,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/tms570/tms570_serial.c b/arch/arm/src/tms570/tms570_serial.c index a6f2ef11cb6..11d9f65b2aa 100644 --- a/arch/arm/src/tms570/tms570_serial.c +++ b/arch/arm/src/tms570/tms570_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs index f9ea0450d1e..66d7669c317 100644 --- a/arch/arm/src/xmc4/Make.defs +++ b/arch/arm/src/xmc4/Make.defs @@ -51,6 +51,7 @@ endif ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += arm_task_start.c arm_pthread_start.c +CMN_CSRCS += arm_pthread_exit.c CMN_CSRCS += arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif diff --git a/arch/arm/src/xmc4/xmc4_dma.h b/arch/arm/src/xmc4/xmc4_dma.h index ee8e05eb8c7..dd11f4ef786 100644 --- a/arch/arm/src/xmc4/xmc4_dma.h +++ b/arch/arm/src/xmc4/xmc4_dma.h @@ -110,9 +110,9 @@ void xmc4_dmainitilaize(void); * gives the caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ****************************************************************************/ diff --git a/arch/arm/src/xmc4/xmc4_irq.c b/arch/arm/src/xmc4/xmc4_irq.c index 74868c4778e..4295a675efb 100644 --- a/arch/arm/src/xmc4/xmc4_irq.c +++ b/arch/arm/src/xmc4/xmc4_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index bf0123dd2f0..703f547b6af 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -32,6 +32,8 @@ #include "arm_internal.h" #include "arm_arch.h" + +#include #include #include "xmc4_config.h" diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 5a235038f68..024b9fd2eee 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index 2de7700c132..5b400704a81 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -50,10 +50,6 @@ static inline void xmc4_fpu_config(void); #endif static inline void xmc4_unaligned(void); static inline void xmc4_flash_waitstates(void); -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) - __attribute__ ((naked, no_instrument_function, noreturn)); -#endif /**************************************************************************** * Pre-processor Definitions @@ -250,47 +246,6 @@ static inline void xmc4_flash_waitstates(void) putreg32(regval, XMC4_FLASH_FCON); } -/**************************************************************************** - * Name: go_nx_start - * - * Description: - * Set the IDLE stack to the coloration value and jump into nx_start() - * - ****************************************************************************/ - -#ifdef CONFIG_STACK_COLORATION -static void go_nx_start(void *pv, unsigned int nbytes) -{ - /* Set the IDLE stack to the stack coloration value then jump to - * nx_start(). We take extreme care here because were currently - * executing on this stack. - * - * We want to avoid sneak stack access generated by the compiler. - */ - - __asm__ __volatile__ - ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tbeq 2f\n" /* (should not happen) */ - - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ - "\tmovt r2, #0xdead\n" - - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ - - "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb nx_start\n" /* Branch to nx_start */ - ); -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -405,17 +360,9 @@ void __start(void) /* Then start NuttX */ -#ifdef CONFIG_STACK_COLORATION - /* Set the IDLE stack to the coloration value and jump into nx_start() */ - - go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); -#else - /* Call nx_start() */ - nx_start(); /* Shouldn't get here */ for (; ; ); -#endif } diff --git a/arch/avr/src/Makefile b/arch/avr/src/Makefile index 7d0d04e693d..51784174b76 100644 --- a/arch/avr/src/Makefile +++ b/arch/avr/src/Makefile @@ -59,8 +59,8 @@ OBJS = $(AOBJS) $(COBJS) # Override in Make.defs if linker is not 'ld' -LDSTARTGROUP ?= --start-group -LDENDGROUP ?= --end-group +LDSTARTGROUP ?= -Wl,--start-group +LDENDGROUP ?= -Wl,--end-group LDFLAGS += $(ARCHSCRIPT) BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,) @@ -104,7 +104,7 @@ board/libboard$(LIBEXT): nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) @echo "LD: nuttx" - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + $(Q) $(LD) -Wl,--entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(filter-out board/libboard$(LIBEXT), $^) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) diff --git a/arch/avr/src/at32uc3/at32uc3_gpioirq.c b/arch/avr/src/at32uc3/at32uc3_gpioirq.c index e37fd3a2b51..9cfb0c2dc1a 100644 --- a/arch/avr/src/at32uc3/at32uc3_gpioirq.c +++ b/arch/avr/src/at32uc3/at32uc3_gpioirq.c @@ -211,7 +211,7 @@ static void gpio_porthandler(uint32_t regbase, int irqbase, xcpt_t handler = g_gpiohandler[irq].handler; if (handler != NULL) { - handler(irq, contex, g_gpiohandler[irq].arg); + handler(irq, context, g_gpiohandler[irq].arg); } else { diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c index 8e9a87ebf0c..1324a063372 100644 --- a/arch/avr/src/at32uc3/at32uc3_irq.c +++ b/arch/avr/src/at32uc3/at32uc3_irq.c @@ -26,6 +26,7 @@ #include "at32uc3_config.h" #include +#include #include #include diff --git a/arch/avr/src/at32uc3/at32uc3_serial.c b/arch/avr/src/at32uc3/at32uc3_serial.c index 40babe94881..a7141196256 100644 --- a/arch/avr/src/at32uc3/at32uc3_serial.c +++ b/arch/avr/src/at32uc3/at32uc3_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/avr/src/at90usb/at90usb_usbdev.c b/arch/avr/src/at90usb/at90usb_usbdev.c index eebdc2bb7a8..f40b42fef07 100644 --- a/arch/avr/src/at90usb/at90usb_usbdev.c +++ b/arch/avr/src/at90usb/at90usb_usbdev.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -1961,7 +1962,7 @@ static void avr_genvbus(void) UDCON |= (1 << DETACH); - /* Disable the clock inputs (the Resume Detection is still active). + /* Disable the clock inputs (the Resume Detection is still active). * This reduces the power consumption. Clear to enable the clock * inputs. */ diff --git a/arch/avr/src/avr/Toolchain.defs b/arch/avr/src/avr/Toolchain.defs index 74e93a8cfec..f8c60d39dde 100644 --- a/arch/avr/src/avr/Toolchain.defs +++ b/arch/avr/src/avr/Toolchain.defs @@ -61,38 +61,39 @@ endif ifeq ($(CONFIG_ARCH_CHIP_ATMEGA128),y) ARCHCPUFLAGS += -mmcu=atmega128 - LDFLAGS += -mavr51 + LDFLAGS += -Wl,-mavr51 else ifeq ($(CONFIG_ARCH_CHIP_ATMEGA1284P),y) ARCHCPUFLAGS += -mmcu=atmega1284p - LDFLAGS += -mavr51 + LDFLAGS += -Wl,-mavr51 else ifeq ($(CONFIG_ARCH_CHIP_AT90USB646),y) ARCHCPUFLAGS += -mmcu=at90usb646 - LDFLAGS += -mavr5 + LDFLAGS += -Wl,-mavr5 else ifeq ($(CONFIG_ARCH_CHIP_AT90USB647),y) ARCHCPUFLAGS += -mmcu=at90usb647 - LDFLAGS += -mavr5 + LDFLAGS += -Wl,-mavr5 else ifeq ($(CONFIG_ARCH_CHIP_AT90USB1286),y) ARCHCPUFLAGS += -mmcu=at90usb1286 - LDFLAGS += -mavr51 + LDFLAGS += -Wl,-mavr51 else ifeq ($(CONFIG_ARCH_CHIP_AT90USB1287),y) ARCHCPUFLAGS += -mmcu=at90usb1287 - LDFLAGS += -mavr51 + LDFLAGS += -Wl,-mavr51 else ifeq ($(CONFIG_ARCH_CHIP_ATMEGA2560),y) ARCHCPUFLAGS += -mmcu=atmega2560 - LDFLAGS += -mavr6 + LDFLAGS += -Wl,-mavr6 else $(error "No valid CONFIG_ARCH_CHIP_ set in the configuration") endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -O2 endif # NuttX buildroot GCC toolchain under Linux or Cygwin ifeq ($(CONFIG_AVR_TOOLCHAIN),BUILDROOT) CROSSDEV ?= avr-nuttx-elf- - MAXOPTIMIZATION ?= -O2 LDFLAGS += -nostartfiles -nodefaultlibs endif @@ -100,7 +101,6 @@ endif ifeq ($(CONFIG_AVR_TOOLCHAIN),CROSSPACK) CROSSDEV ?= avr- - MAXOPTIMIZATION ?= -O2 LDFLAGS += -nostartfiles -nodefaultlibs endif @@ -108,13 +108,11 @@ endif ifeq ($(CONFIG_AVR_TOOLCHAIN),LINUXGCC) CROSSDEV ?= avr- - MAXOPTIMIZATION ?= -O2 LDFLAGS += -nostartfiles -nodefaultlibs endif ifeq ($(CONFIG_AVR_TOOLCHAIN),WINAVR) CROSSDEV ?= avr- - MAXOPTIMIZATION ?= -O2 LDFLAGS += -nostartfiles -nodefaultlibs endif @@ -123,7 +121,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/avr/src/avr/up_blocktask.c b/arch/avr/src/avr/up_blocktask.c index 1ca34a3e157..1be4c6751f5 100644 --- a/arch/avr/src/avr/up_blocktask.c +++ b/arch/avr/src/avr/up_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/avr/src/avr/up_createstack.c b/arch/avr/src/avr/up_createstack.c index 2e99d3d361d..1f697bf8d56 100644 --- a/arch/avr/src/avr/up_createstack.c +++ b/arch/avr/src/avr/up_createstack.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/avr/src/avr/up_reprioritizertr.c b/arch/avr/src/avr/up_reprioritizertr.c index 6ae1b668ed3..c876b2a3918 100644 --- a/arch/avr/src/avr/up_reprioritizertr.c +++ b/arch/avr/src/avr/up_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/avr/src/avr/up_sigdeliver.c b/arch/avr/src/avr/up_sigdeliver.c index 713bbb52d61..1e9a327c224 100644 --- a/arch/avr/src/avr/up_sigdeliver.c +++ b/arch/avr/src/avr/up_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/avr/src/avr/up_spi.c b/arch/avr/src/avr/up_spi.c index 6c741b776f7..41cd0484c61 100644 --- a/arch/avr/src/avr/up_spi.c +++ b/arch/avr/src/avr/up_spi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/avr/src/avr/up_unblocktask.c b/arch/avr/src/avr/up_unblocktask.c index 7201161932d..8e54f5008cf 100644 --- a/arch/avr/src/avr/up_unblocktask.c +++ b/arch/avr/src/avr/up_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/avr/src/avr/up_usestack.c b/arch/avr/src/avr/up_usestack.c index c16b29ef5a1..1ab016b840c 100644 --- a/arch/avr/src/avr/up_usestack.c +++ b/arch/avr/src/avr/up_usestack.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/avr/src/avr32/Toolchain.defs b/arch/avr/src/avr32/Toolchain.defs index 3e081292e42..9b3206e037b 100644 --- a/arch/avr/src/avr32/Toolchain.defs +++ b/arch/avr/src/avr32/Toolchain.defs @@ -41,7 +41,7 @@ ARCHCPUFLAGS = -mpart=uc3b0256 CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/avr/src/avr32/up_blocktask.c b/arch/avr/src/avr32/up_blocktask.c index fe6eabe84f2..f789aa022b4 100644 --- a/arch/avr/src/avr32/up_blocktask.c +++ b/arch/avr/src/avr32/up_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/avr/src/avr32/up_createstack.c b/arch/avr/src/avr32/up_createstack.c index 1e75a56e95f..0ab6201a302 100644 --- a/arch/avr/src/avr32/up_createstack.c +++ b/arch/avr/src/avr32/up_createstack.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/avr/src/avr32/up_reprioritizertr.c b/arch/avr/src/avr32/up_reprioritizertr.c index fb5be67018f..a3d26a4d359 100644 --- a/arch/avr/src/avr32/up_reprioritizertr.c +++ b/arch/avr/src/avr32/up_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/avr/src/avr32/up_sigdeliver.c b/arch/avr/src/avr32/up_sigdeliver.c index f6681dbded2..78863c55471 100644 --- a/arch/avr/src/avr32/up_sigdeliver.c +++ b/arch/avr/src/avr32/up_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/avr/src/avr32/up_unblocktask.c b/arch/avr/src/avr32/up_unblocktask.c index d47fcfd1fa1..486bca0d7b6 100644 --- a/arch/avr/src/avr32/up_unblocktask.c +++ b/arch/avr/src/avr32/up_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/avr/src/avr32/up_usestack.c b/arch/avr/src/avr32/up_usestack.c index 7aac1b57fb0..e6a1661764b 100644 --- a/arch/avr/src/avr32/up_usestack.c +++ b/arch/avr/src/avr32/up_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/hc/src/Makefile b/arch/hc/src/Makefile index fd9f06cd7ce..8fc1c732381 100644 --- a/arch/hc/src/Makefile +++ b/arch/hc/src/Makefile @@ -60,8 +60,8 @@ OBJS = $(AOBJS) $(COBJS) # Override in Make.defs if linker is not 'ld' -LDSTARTGROUP ?= --start-group -LDENDGROUP ?= --end-group +LDSTARTGROUP ?= -Wl,--start-group +LDENDGROUP ?= -Wl,--end-group LDFLAGS += $(ARCHSCRIPT) BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,) @@ -119,7 +119,7 @@ board/libboard$(LIBEXT): nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) $(Q) echo "LD: nuttx" - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + $(Q) $(LD) -Wl,--entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(filter-out board/libboard$(LIBEXT), $^) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) diff --git a/arch/hc/src/common/up_blocktask.c b/arch/hc/src/common/up_blocktask.c index 5ce5c6fed7a..768d5429fdd 100644 --- a/arch/hc/src/common/up_blocktask.c +++ b/arch/hc/src/common/up_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/hc/src/common/up_createstack.c b/arch/hc/src/common/up_createstack.c index 0b5b7f83def..f98dd4ab6c0 100644 --- a/arch/hc/src/common/up_createstack.c +++ b/arch/hc/src/common/up_createstack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/hc/src/common/up_reprioritizertr.c b/arch/hc/src/common/up_reprioritizertr.c index 0d6a3c93576..bdd111f8481 100644 --- a/arch/hc/src/common/up_reprioritizertr.c +++ b/arch/hc/src/common/up_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/hc/src/common/up_unblocktask.c b/arch/hc/src/common/up_unblocktask.c index 58e9ae5a4f9..94609a1744e 100644 --- a/arch/hc/src/common/up_unblocktask.c +++ b/arch/hc/src/common/up_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/hc/src/common/up_usestack.c b/arch/hc/src/common/up_usestack.c index d7173b8ffda..23eadfb7d65 100644 --- a/arch/hc/src/common/up_usestack.c +++ b/arch/hc/src/common/up_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c index 9d67484e070..b20b3ac68f8 100644 --- a/arch/hc/src/m9s12/m9s12_ethernet.c +++ b/arch/hc/src/m9s12/m9s12_ethernet.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/hc/src/m9s12/m9s12_serial.c b/arch/hc/src/m9s12/m9s12_serial.c index 13d9e530060..be884b6e486 100644 --- a/arch/hc/src/m9s12/m9s12_serial.c +++ b/arch/hc/src/m9s12/m9s12_serial.c @@ -25,6 +25,8 @@ #include #include +#include + #include "up_internal.h" #include "m9s12_serial.h" diff --git a/arch/mips/src/common/mips_createstack.c b/arch/mips/src/common/mips_createstack.c index 4fa89ee7b6d..b16110f4ea8 100644 --- a/arch/mips/src/common/mips_createstack.c +++ b/arch/mips/src/common/mips_createstack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/common/mips_usestack.c b/arch/mips/src/common/mips_usestack.c index faedc452512..a2223b66337 100644 --- a/arch/mips/src/common/mips_usestack.c +++ b/arch/mips/src/common/mips_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/mips32/mips_blocktask.c b/arch/mips/src/mips32/mips_blocktask.c index 909b6948faa..24496ab9f76 100644 --- a/arch/mips/src/mips32/mips_blocktask.c +++ b/arch/mips/src/mips32/mips_blocktask.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/mips32/mips_reprioritizertr.c b/arch/mips/src/mips32/mips_reprioritizertr.c index 79c93c22832..f5088c51071 100644 --- a/arch/mips/src/mips32/mips_reprioritizertr.c +++ b/arch/mips/src/mips32/mips_reprioritizertr.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/mips32/mips_sigdeliver.c b/arch/mips/src/mips32/mips_sigdeliver.c index a66ef29bf2e..4bd28e91637 100644 --- a/arch/mips/src/mips32/mips_sigdeliver.c +++ b/arch/mips/src/mips32/mips_sigdeliver.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/mips32/mips_unblocktask.c b/arch/mips/src/mips32/mips_unblocktask.c index 34eeac53024..c822d2ee0ca 100644 --- a/arch/mips/src/mips32/mips_unblocktask.c +++ b/arch/mips/src/mips32/mips_unblocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/mips/src/pic32mx/pic32mx.h b/arch/mips/src/pic32mx/pic32mx.h index 9deff0bdf8c..ca5e8bcbc00 100644 --- a/arch/mips/src/pic32mx/pic32mx.h +++ b/arch/mips/src/pic32mx/pic32mx.h @@ -477,9 +477,9 @@ void pic32mx_dmainitilaize(void); * caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel handle. NULL - * is returned on any failure. This function can fail only if no DMA channel is - * available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ************************************************************************************/ diff --git a/arch/mips/src/pic32mx/pic32mx_irq.c b/arch/mips/src/pic32mx/pic32mx_irq.c index 3d465a7d62c..5d24be729d1 100644 --- a/arch/mips/src/pic32mx/pic32mx_irq.c +++ b/arch/mips/src/pic32mx/pic32mx_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/mips/src/pic32mx/pic32mx_serial.c b/arch/mips/src/pic32mx/pic32mx_serial.c index c4421f48071..b510aaa7110 100644 --- a/arch/mips/src/pic32mx/pic32mx_serial.c +++ b/arch/mips/src/pic32mx/pic32mx_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/pic32mx/pic32mx_spi.c b/arch/mips/src/pic32mx/pic32mx_spi.c index 5e58e6c0cd4..238a74d4f5e 100644 --- a/arch/mips/src/pic32mx/pic32mx_spi.c +++ b/arch/mips/src/pic32mx/pic32mx_spi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/pic32mx/pic32mx_usbdev.c b/arch/mips/src/pic32mx/pic32mx_usbdev.c index 641aef9d8bb..20ec742cd12 100644 --- a/arch/mips/src/pic32mx/pic32mx_usbdev.c +++ b/arch/mips/src/pic32mx/pic32mx_usbdev.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/pic32mz/pic32mz_dma.c b/arch/mips/src/pic32mz/pic32mz_dma.c index 77dfbec77db..da7b1b90566 100644 --- a/arch/mips/src/pic32mz/pic32mz_dma.c +++ b/arch/mips/src/pic32mz/pic32mz_dma.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/mips/src/pic32mz/pic32mz_i2c.c b/arch/mips/src/pic32mz/pic32mz_i2c.c index d931cf374b0..e40b803625c 100644 --- a/arch/mips/src/pic32mz/pic32mz_i2c.c +++ b/arch/mips/src/pic32mz/pic32mz_i2c.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/pic32mz/pic32mz_irq.c b/arch/mips/src/pic32mz/pic32mz_irq.c index 44769e06593..c1e5dcaaf62 100644 --- a/arch/mips/src/pic32mz/pic32mz_irq.c +++ b/arch/mips/src/pic32mz/pic32mz_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/mips/src/pic32mz/pic32mz_serial.c b/arch/mips/src/pic32mz/pic32mz_serial.c index 30d19bf0dca..d224b458c15 100644 --- a/arch/mips/src/pic32mz/pic32mz_serial.c +++ b/arch/mips/src/pic32mz/pic32mz_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/pic32mz/pic32mz_spi.c b/arch/mips/src/pic32mz/pic32mz_spi.c index 07f771d31bc..7a16b97fac6 100644 --- a/arch/mips/src/pic32mz/pic32mz_spi.c +++ b/arch/mips/src/pic32mz/pic32mz_spi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/src/pic32mz/pic32mz_timer.c b/arch/mips/src/pic32mz/pic32mz_timer.c index bdeea888d73..95ed9903e02 100644 --- a/arch/mips/src/pic32mz/pic32mz_timer.c +++ b/arch/mips/src/pic32mz/pic32mz_timer.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/include/lm32/irq.h b/arch/misoc/include/lm32/irq.h index 91742394659..69bdd8a271f 100644 --- a/arch/misoc/include/lm32/irq.h +++ b/arch/misoc/include/lm32/irq.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/include/lm32/irq.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/include/lm32/syscall.h b/arch/misoc/include/lm32/syscall.h index 17591efe5d8..a7a549c9e9f 100644 --- a/arch/misoc/include/lm32/syscall.h +++ b/arch/misoc/include/lm32/syscall.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/include/lm32/syscall.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/include/minerva/csrdefs.h b/arch/misoc/include/minerva/csrdefs.h index 40f8bcb1b43..ef7b4604924 100644 --- a/arch/misoc/include/minerva/csrdefs.h +++ b/arch/misoc/include/minerva/csrdefs.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/include/minerva/csrdefs.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/include/minerva/syscall.h b/arch/misoc/include/minerva/syscall.h index 0e24fc594ab..7e27993b575 100644 --- a/arch/misoc/include/minerva/syscall.h +++ b/arch/misoc/include/minerva/syscall.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/include/minerva/syscall.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/Makefile b/arch/misoc/src/Makefile index 794e902f80b..a00a2b3500f 100644 --- a/arch/misoc/src/Makefile +++ b/arch/misoc/src/Makefile @@ -61,8 +61,8 @@ OBJS = $(AOBJS) $(COBJS) # Override in Make.defs if linker is not 'ld' -LDSTARTGROUP ?= --start-group -LDENDGROUP ?= --end-group +LDSTARTGROUP ?= -Wl,--start-group +LDENDGROUP ?= -Wl,--end-group LDFLAGS += $(ARCHSCRIPT) BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,) @@ -105,7 +105,7 @@ board/libboard$(LIBEXT): $(Q) $(MAKE) -C board libboard$(LIBEXT) EXTRAFLAGS="$(EXTRAFLAGS)" nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + $(Q) $(LD) -Wl,--entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(filter-out board/libboard$(LIBEXT), $^) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) diff --git a/arch/misoc/src/common/hw/common.h b/arch/misoc/src/common/hw/common.h index 602902700d9..9690da7e2c8 100644 --- a/arch/misoc/src/common/hw/common.h +++ b/arch/misoc/src/common/hw/common.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/common/hw/common.h * - * Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/common/hw/ethmac_mem.h b/arch/misoc/src/common/hw/ethmac_mem.h index 1f381c6cf95..cf9ed87538b 100644 --- a/arch/misoc/src/common/hw/ethmac_mem.h +++ b/arch/misoc/src/common/hw/ethmac_mem.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/common/hw/ethmac_mem.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/common/hw/flags.h b/arch/misoc/src/common/hw/flags.h index e2e2f978c49..54bc42d0301 100644 --- a/arch/misoc/src/common/hw/flags.h +++ b/arch/misoc/src/common/hw/flags.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/common/hw/flags.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/common/misoc.h b/arch/misoc/src/common/misoc.h index 128a6e8b3b6..e2ae9c27b67 100644 --- a/arch/misoc/src/common/misoc.h +++ b/arch/misoc/src/common/misoc.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/common/misoc.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/common/misoc_flushcache.c b/arch/misoc/src/common/misoc_flushcache.c index 655ba8ab358..2927d7824ba 100644 --- a/arch/misoc/src/common/misoc_flushcache.c +++ b/arch/misoc/src/common/misoc_flushcache.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/common/misoc_flushcache.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c index 53eebe88288..1f8e07e73bb 100644 --- a/arch/misoc/src/common/misoc_net.c +++ b/arch/misoc/src/common/misoc_net.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/common/misoc_net.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c index 045dbe1d912..7db014df2c0 100644 --- a/arch/misoc/src/common/misoc_serial.c +++ b/arch/misoc/src/common/misoc_serial.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/common/misoc_serial.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -44,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/common/misoc_timerisr.c b/arch/misoc/src/common/misoc_timerisr.c index 98f35c7c6c2..43f9052f431 100644 --- a/arch/misoc/src/common/misoc_timerisr.c +++ b/arch/misoc/src/common/misoc_timerisr.c @@ -1,40 +1,20 @@ /**************************************************************************** * arch/misoc/src/common/misoc_timerisr.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Modified for MISOC: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2016 Ramtin Amin. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index 96757a68099..5ac7df4c9fb 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -1,36 +1,20 @@ ############################################################################ # arch/misoc/src/lm32/Make.defs # -# Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# Ramtin Amin +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: +# http://www.apache.org/licenses/LICENSE-2.0 # -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. # ############################################################################ diff --git a/arch/misoc/src/lm32/Toolchain.defs b/arch/misoc/src/lm32/Toolchain.defs index 5e264e833ef..e5ec0a46d8e 100644 --- a/arch/misoc/src/lm32/Toolchain.defs +++ b/arch/misoc/src/lm32/Toolchain.defs @@ -57,20 +57,20 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif # NuttX buildroot under Linux or Cygwin ifeq ($(CONFIG_LM32_TOOLCHAIN),BUILDROOT) CROSSDEV ?= lm32-nuttx-elf- - MAXOPTIMIZATION ?= -Os endif # Generic GNU toolchain ifeq ($(CONFIG_LM32_TOOLCHAIN),GNUL) CROSSDEV ?= lm32-elf- - MAXOPTIMIZATION ?= -Os endif # Default toolchain @@ -78,7 +78,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/misoc/src/lm32/chip.h b/arch/misoc/src/lm32/chip.h index 4a400aaad98..509e3d72d33 100644 --- a/arch/misoc/src/lm32/chip.h +++ b/arch/misoc/src/lm32/chip.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/chip.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index 74642daadf3..7715d30f42a 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -53,14 +37,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* This is the value used to mark the stack for subsequent stack monitoring - * logic. - */ - -#define STACK_COLOR 0xdeadbeef -#define INTSTACK_COLOR 0xdeadbeef -#define HEAP_COLOR 'h' - /* In the LM32 model, the state is copied from the stack to the TCB, but * only a referenced is passed to get the state from the TCB. */ diff --git a/arch/misoc/src/lm32/lm32_allocateheap.c b/arch/misoc/src/lm32/lm32_allocateheap.c index 882bed891aa..429751dfa18 100644 --- a/arch/misoc/src/lm32/lm32_allocateheap.c +++ b/arch/misoc/src/lm32/lm32_allocateheap.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_allocateheap.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_assert.c b/arch/misoc/src/lm32/lm32_assert.c index 286a170e962..e8d47efb936 100644 --- a/arch/misoc/src/lm32/lm32_assert.c +++ b/arch/misoc/src/lm32/lm32_assert.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_assert.c * - * Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_blocktask.c b/arch/misoc/src/lm32/lm32_blocktask.c index 08c94a479b7..97f3d5a4ff0 100644 --- a/arch/misoc/src/lm32/lm32_blocktask.c +++ b/arch/misoc/src/lm32/lm32_blocktask.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_blocktask.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/lm32/lm32_config.h b/arch/misoc/src/lm32/lm32_config.h index c78b4d3402d..9bce5ae88c2 100644 --- a/arch/misoc/src/lm32/lm32_config.h +++ b/arch/misoc/src/lm32/lm32_config.h @@ -1,40 +1,20 @@ /************************************************************************************ * arch/misoc/src/lm32/lm32_config.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Modified for LM32: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2016 Ramin Amin. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ************************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_copystate.c b/arch/misoc/src/lm32/lm32_copystate.c index d8b4a0529b3..5bf855430b7 100644 --- a/arch/misoc/src/lm32/lm32_copystate.c +++ b/arch/misoc/src/lm32/lm32_copystate.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_copystate.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_createstack.c b/arch/misoc/src/lm32/lm32_createstack.c index ff40cf6e72e..87cdbccba0e 100644 --- a/arch/misoc/src/lm32/lm32_createstack.c +++ b/arch/misoc/src/lm32/lm32_createstack.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_createstack.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/lm32/lm32_doirq.c b/arch/misoc/src/lm32/lm32_doirq.c index c5d6bb6527e..87a3cddeb8c 100644 --- a/arch/misoc/src/lm32/lm32_doirq.c +++ b/arch/misoc/src/lm32/lm32_doirq.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_doirq.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_dumpstate.c b/arch/misoc/src/lm32/lm32_dumpstate.c index c9db94e0b8b..06b3ab8ea5f 100644 --- a/arch/misoc/src/lm32/lm32_dumpstate.c +++ b/arch/misoc/src/lm32/lm32_dumpstate.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_dumpstate.c * - * Copyright (C) 2011, 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_exit.c b/arch/misoc/src/lm32/lm32_exit.c index 8715dbe4f20..dc9f2cfdf77 100644 --- a/arch/misoc/src/lm32/lm32_exit.c +++ b/arch/misoc/src/lm32/lm32_exit.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_exit.c * - * Copyright (C) 2010, 2013-2014, 2017-2018 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_flushcache.c b/arch/misoc/src/lm32/lm32_flushcache.c index eecaf1cd0f4..e71de29024c 100644 --- a/arch/misoc/src/lm32/lm32_flushcache.c +++ b/arch/misoc/src/lm32/lm32_flushcache.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_flushcache.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_idle.c b/arch/misoc/src/lm32/lm32_idle.c index 627de0945fb..d6cd4d592ad 100644 --- a/arch/misoc/src/lm32/lm32_idle.c +++ b/arch/misoc/src/lm32/lm32_idle.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_idle.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_initialize.c b/arch/misoc/src/lm32/lm32_initialize.c index cfcb7c45121..98c73b35e3b 100644 --- a/arch/misoc/src/lm32/lm32_initialize.c +++ b/arch/misoc/src/lm32/lm32_initialize.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_initialize.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_initialstate.c b/arch/misoc/src/lm32/lm32_initialstate.c index 9e7a4151fc5..da5a2281b3e 100644 --- a/arch/misoc/src/lm32/lm32_initialstate.c +++ b/arch/misoc/src/lm32/lm32_initialstate.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_initialstate.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_interruptcontext.c b/arch/misoc/src/lm32/lm32_interruptcontext.c index 35a774bc5a9..055368e5a09 100644 --- a/arch/misoc/src/lm32/lm32_interruptcontext.c +++ b/arch/misoc/src/lm32/lm32_interruptcontext.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_interruptcontext.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index dcb4c1bcb9b..09ae3154c75 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_irq.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -39,6 +24,7 @@ #include #include +#include #include #include diff --git a/arch/misoc/src/lm32/lm32_releasepending.c b/arch/misoc/src/lm32/lm32_releasepending.c index b400f82d5d4..f36f46ab58f 100644 --- a/arch/misoc/src/lm32/lm32_releasepending.c +++ b/arch/misoc/src/lm32/lm32_releasepending.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_releasepending.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_releasestack.c b/arch/misoc/src/lm32/lm32_releasestack.c index d940d8507cf..64af00eb34e 100644 --- a/arch/misoc/src/lm32/lm32_releasestack.c +++ b/arch/misoc/src/lm32/lm32_releasestack.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_releasestack.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_reprioritizertr.c b/arch/misoc/src/lm32/lm32_reprioritizertr.c index 3cb34d3bee7..11c5cc7f1a8 100644 --- a/arch/misoc/src/lm32/lm32_reprioritizertr.c +++ b/arch/misoc/src/lm32/lm32_reprioritizertr.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/lm32/lm32_schedulesigaction.c b/arch/misoc/src/lm32/lm32_schedulesigaction.c index b73d45dc8ff..88a23435895 100644 --- a/arch/misoc/src/lm32/lm32_schedulesigaction.c +++ b/arch/misoc/src/lm32/lm32_schedulesigaction.c @@ -1,40 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_schedulesigaction.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Modified for MISOC: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2016 Ramtin Amin. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_sigdeliver.c b/arch/misoc/src/lm32/lm32_sigdeliver.c index 7912a9c2542..558425fe99a 100644 --- a/arch/misoc/src/lm32/lm32_sigdeliver.c +++ b/arch/misoc/src/lm32/lm32_sigdeliver.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/lm32/lm32_stackframe.c b/arch/misoc/src/lm32/lm32_stackframe.c index 624c6fed072..f8fa3c8c292 100644 --- a/arch/misoc/src/lm32/lm32_stackframe.c +++ b/arch/misoc/src/lm32/lm32_stackframe.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_stackframe.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_swint.c b/arch/misoc/src/lm32/lm32_swint.c index c88007ae5ed..cff92be8e33 100644 --- a/arch/misoc/src/lm32/lm32_swint.c +++ b/arch/misoc/src/lm32/lm32_swint.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_swint.c * - * Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_syscall.S b/arch/misoc/src/lm32/lm32_syscall.S index 61b0b6ca7cf..4f274a984a5 100644 --- a/arch/misoc/src/lm32/lm32_syscall.S +++ b/arch/misoc/src/lm32/lm32_syscall.S @@ -1,40 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_syscall.S * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Derives from RISC-V version: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2016 Ken Pettit. All rights reserved. - * Author: Ken Pettit - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_unblocktask.c b/arch/misoc/src/lm32/lm32_unblocktask.c index 52ddc6545ec..bdd6ade3bdd 100644 --- a/arch/misoc/src/lm32/lm32_unblocktask.c +++ b/arch/misoc/src/lm32/lm32_unblocktask.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/lm32/lm32_unblocktask.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -42,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/misoc/src/lm32/lm32_usestack.c b/arch/misoc/src/lm32/lm32_usestack.c index 457b0aea84c..ffc13c9cb30 100644 --- a/arch/misoc/src/lm32/lm32_usestack.c +++ b/arch/misoc/src/lm32/lm32_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/minerva/Make.defs b/arch/misoc/src/minerva/Make.defs index a17f46061e5..0d3c6882252 100644 --- a/arch/misoc/src/minerva/Make.defs +++ b/arch/misoc/src/minerva/Make.defs @@ -1,36 +1,20 @@ ############################################################################ # arch/misoc/src/minerva/Make.defs # -# Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# Ramtin Amin +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: +# http://www.apache.org/licenses/LICENSE-2.0 # -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. # ############################################################################ diff --git a/arch/misoc/src/minerva/Toolchain.defs b/arch/misoc/src/minerva/Toolchain.defs index fc223bcbae7..5f01a9b96d2 100644 --- a/arch/misoc/src/minerva/Toolchain.defs +++ b/arch/misoc/src/minerva/Toolchain.defs @@ -21,8 +21,10 @@ CROSSDEV = riscv32-unknown-elf- ARCHCPUFLAGS = -march=rv32i -ifeq ($(CONFIG_DEBUG_SYMBOLS),) -MAXOPTIMIZATION ?= -Os +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif # Default toolchain @@ -30,7 +32,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/misoc/src/minerva/chip.h b/arch/misoc/src/minerva/chip.h index 16d61278e6d..af85a04af38 100644 --- a/arch/misoc/src/minerva/chip.h +++ b/arch/misoc/src/minerva/chip.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/chip.h * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva.h b/arch/misoc/src/minerva/minerva.h index 8d9a43fb642..6754ad1c019 100644 --- a/arch/misoc/src/minerva/minerva.h +++ b/arch/misoc/src/minerva/minerva.h @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -53,14 +37,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* This is the value used to mark the stack for subsequent stack monitoring - * logic. - */ - -#define STACK_COLOR 0xdeadbeef -#define INTSTACK_COLOR 0xdeadbeef -#define HEAP_COLOR 'h' - /* In the MINERVA model, the state is copied from the stack to the TCB, but * only a referenced is passed to get the state from the TCB. */ diff --git a/arch/misoc/src/minerva/minerva_allocateheap.c b/arch/misoc/src/minerva/minerva_allocateheap.c index 4efcce966ce..315c5d9e13f 100644 --- a/arch/misoc/src/minerva/minerva_allocateheap.c +++ b/arch/misoc/src/minerva/minerva_allocateheap.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_allocateheap.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_assert.c b/arch/misoc/src/minerva/minerva_assert.c index 7c39539f335..e4e4d085d02 100644 --- a/arch/misoc/src/minerva/minerva_assert.c +++ b/arch/misoc/src/minerva/minerva_assert.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_assert.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_blocktask.c b/arch/misoc/src/minerva/minerva_blocktask.c index 772ef883785..8390b00c2bf 100644 --- a/arch/misoc/src/minerva/minerva_blocktask.c +++ b/arch/misoc/src/minerva/minerva_blocktask.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_blocktask.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/minerva/minerva_config.h b/arch/misoc/src/minerva/minerva_config.h index f03c4a8fba8..043471286bd 100644 --- a/arch/misoc/src/minerva/minerva_config.h +++ b/arch/misoc/src/minerva/minerva_config.h @@ -1,40 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_config.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Modified for MINERVA: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2016 Ramin Amin. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_copystate.c b/arch/misoc/src/minerva/minerva_copystate.c index 5c9b5207d6e..1d55a8d3d4b 100644 --- a/arch/misoc/src/minerva/minerva_copystate.c +++ b/arch/misoc/src/minerva/minerva_copystate.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_copystate.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_createstack.c b/arch/misoc/src/minerva/minerva_createstack.c index 8f3880ffa7b..1168eb1b7ec 100644 --- a/arch/misoc/src/minerva/minerva_createstack.c +++ b/arch/misoc/src/minerva/minerva_createstack.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_createstack.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/minerva/minerva_doexceptions.c b/arch/misoc/src/minerva/minerva_doexceptions.c index 84c23604dff..ab7d63e4369 100644 --- a/arch/misoc/src/minerva/minerva_doexceptions.c +++ b/arch/misoc/src/minerva/minerva_doexceptions.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_doexceptions.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_doirq.c b/arch/misoc/src/minerva/minerva_doirq.c index f64a210d5f8..b997f917f72 100644 --- a/arch/misoc/src/minerva/minerva_doirq.c +++ b/arch/misoc/src/minerva/minerva_doirq.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_doirq.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_dumpstate.c b/arch/misoc/src/minerva/minerva_dumpstate.c index 77c0ec9deb0..46f133cfa24 100644 --- a/arch/misoc/src/minerva/minerva_dumpstate.c +++ b/arch/misoc/src/minerva/minerva_dumpstate.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_dumpstate.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_exit.c b/arch/misoc/src/minerva/minerva_exit.c index da3feb687df..c4730c79171 100644 --- a/arch/misoc/src/minerva/minerva_exit.c +++ b/arch/misoc/src/minerva/minerva_exit.c @@ -1,37 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_exit.c * - * Copyright (C) 2010, 2013-2014, 2017-2018 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_flushcache.c b/arch/misoc/src/minerva/minerva_flushcache.c index a395134ef70..87cbcb84c50 100644 --- a/arch/misoc/src/minerva/minerva_flushcache.c +++ b/arch/misoc/src/minerva/minerva_flushcache.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_flushcache.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_idle.c b/arch/misoc/src/minerva/minerva_idle.c index 21ea0af2c65..3d2667bca3e 100644 --- a/arch/misoc/src/minerva/minerva_idle.c +++ b/arch/misoc/src/minerva/minerva_idle.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_idle.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_initialize.c b/arch/misoc/src/minerva/minerva_initialize.c index d6c753c4fb9..11d3d8f941b 100644 --- a/arch/misoc/src/minerva/minerva_initialize.c +++ b/arch/misoc/src/minerva/minerva_initialize.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_initialize.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_initialstate.c b/arch/misoc/src/minerva/minerva_initialstate.c index 4c47aeab3a4..e0f5d974f2a 100644 --- a/arch/misoc/src/minerva/minerva_initialstate.c +++ b/arch/misoc/src/minerva/minerva_initialstate.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_initialstate.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_interruptcontext.c b/arch/misoc/src/minerva/minerva_interruptcontext.c index 66dee68f26a..7fe6c70cb9a 100644 --- a/arch/misoc/src/minerva/minerva_interruptcontext.c +++ b/arch/misoc/src/minerva/minerva_interruptcontext.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_interruptcontext.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_irq.c b/arch/misoc/src/minerva/minerva_irq.c index 2fbd580daa9..83ed522c4c7 100644 --- a/arch/misoc/src/minerva/minerva_irq.c +++ b/arch/misoc/src/minerva/minerva_irq.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_irq.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -39,6 +24,7 @@ #include #include +#include #include #include diff --git a/arch/misoc/src/minerva/minerva_releasepending.c b/arch/misoc/src/minerva/minerva_releasepending.c index 93b6ad64f2b..5623831c918 100644 --- a/arch/misoc/src/minerva/minerva_releasepending.c +++ b/arch/misoc/src/minerva/minerva_releasepending.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_releasepending.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_releasestack.c b/arch/misoc/src/minerva/minerva_releasestack.c index 113568c24e1..d43f76efc42 100644 --- a/arch/misoc/src/minerva/minerva_releasestack.c +++ b/arch/misoc/src/minerva/minerva_releasestack.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_releasestack.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_reprioritizertr.c b/arch/misoc/src/minerva/minerva_reprioritizertr.c index 8da50490d54..565d3ffdf01 100644 --- a/arch/misoc/src/minerva/minerva_reprioritizertr.c +++ b/arch/misoc/src/minerva/minerva_reprioritizertr.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/minerva/minerva_schedulesigaction.c b/arch/misoc/src/minerva/minerva_schedulesigaction.c index ce66e18a003..d41efc497bd 100644 --- a/arch/misoc/src/minerva/minerva_schedulesigaction.c +++ b/arch/misoc/src/minerva/minerva_schedulesigaction.c @@ -1,40 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_schedulesigaction.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Modified for MISOC: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2016 Ramtin Amin. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_sigdeliver.c b/arch/misoc/src/minerva/minerva_sigdeliver.c index acf8f28a182..4b3f1e967ea 100644 --- a/arch/misoc/src/minerva/minerva_sigdeliver.c +++ b/arch/misoc/src/minerva/minerva_sigdeliver.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/minerva/minerva_stackframe.c b/arch/misoc/src/minerva/minerva_stackframe.c index 3dc536ee4b1..41cfaf0b964 100644 --- a/arch/misoc/src/minerva/minerva_stackframe.c +++ b/arch/misoc/src/minerva/minerva_stackframe.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_stackframe.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_swint.c b/arch/misoc/src/minerva/minerva_swint.c index b934d8eb889..2ec3d4b1893 100644 --- a/arch/misoc/src/minerva/minerva_swint.c +++ b/arch/misoc/src/minerva/minerva_swint.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_swint.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_syscall.S b/arch/misoc/src/minerva/minerva_syscall.S index de51e727939..03ca7d57844 100644 --- a/arch/misoc/src/minerva/minerva_syscall.S +++ b/arch/misoc/src/minerva/minerva_syscall.S @@ -1,40 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_syscall.S * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Derives from RISC-V version: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (C) 2016 Ken Pettit. All rights reserved. - * Author: Ken Pettit - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/misoc/src/minerva/minerva_unblocktask.c b/arch/misoc/src/minerva/minerva_unblocktask.c index a427e90e099..44916489c68 100644 --- a/arch/misoc/src/minerva/minerva_unblocktask.c +++ b/arch/misoc/src/minerva/minerva_unblocktask.c @@ -1,36 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_unblocktask.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -42,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/misoc/src/minerva/minerva_usestack.c b/arch/misoc/src/minerva/minerva_usestack.c index 193a8f2d9c6..6f306474641 100644 --- a/arch/misoc/src/minerva/minerva_usestack.c +++ b/arch/misoc/src/minerva/minerva_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/misoc/src/minerva/minerva_vectors.S b/arch/misoc/src/minerva/minerva_vectors.S index fbfa3b17052..753d9f8b57e 100644 --- a/arch/misoc/src/minerva/minerva_vectors.S +++ b/arch/misoc/src/minerva/minerva_vectors.S @@ -1,35 +1,20 @@ /**************************************************************************** * arch/misoc/src/minerva/minerva_vectors.S * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/or1k/src/Makefile b/arch/or1k/src/Makefile index 74c3ed472a0..a822d1eb1da 100644 --- a/arch/or1k/src/Makefile +++ b/arch/or1k/src/Makefile @@ -79,8 +79,8 @@ LDFLAGS += $(ARCHSCRIPT) # Override in Make.defs if linker is not 'ld' -LDSTARTGROUP ?= --start-group -LDENDGROUP ?= --end-group +LDSTARTGROUP ?= -Wl,--start-group +LDENDGROUP ?= -Wl,--end-group BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,) @@ -141,7 +141,7 @@ board$(DELIM)libboard$(LIBEXT): nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT) $(Q) echo "LD: nuttx" - $(Q) $(LD) --entry=0x100 $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + $(Q) $(LD) -Wl,--entry=0x100 $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(filter-out board/libboard$(LIBEXT), $^) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) diff --git a/arch/or1k/src/common/up_blocktask.c b/arch/or1k/src/common/up_blocktask.c index ae412117d9f..e710fc96424 100644 --- a/arch/or1k/src/common/up_blocktask.c +++ b/arch/or1k/src/common/up_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/or1k/src/common/up_fullcontextrestore.S b/arch/or1k/src/common/up_fullcontextrestore.S index 7fcf05721da..e3d3a5aeca9 100644 --- a/arch/or1k/src/common/up_fullcontextrestore.S +++ b/arch/or1k/src/common/up_fullcontextrestore.S @@ -1,35 +1,20 @@ /************************************************************************** * arch/or1k/src/common/up_fullcontextrestore.S * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * **************************************************************************/ diff --git a/arch/or1k/src/common/up_pthread_start.c b/arch/or1k/src/common/up_pthread_start.c index f32c4bb1c90..31a85417400 100644 --- a/arch/or1k/src/common/up_pthread_start.c +++ b/arch/or1k/src/common/up_pthread_start.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "svcall.h" #include "up_internal.h" @@ -47,9 +48,10 @@ * pthread. * * Normally the a user-mode start-up stub will also execute before the - * pthread actually starts. See libc/pthread/pthread_startup.c + * pthread actually starts. See libc/pthread/pthread_create.c * * Input Parameters: + * startup - The user-space pthread startup function * entrypt - The user-space address of the pthread entry point * arg - Standard argument for the pthread entry point * @@ -62,11 +64,12 @@ void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) { - /* Let sys_call2() do all of the work */ + /* Let sys_call3() do all of the work */ sinfo("entry %p arg %p\n", entrypt, arg); - sys_call2(SYS_pthread_start, (uintptr_t)entrypt, (uintptr_t)arg); + sys_call3(SYS_pthread_start, (uintptr_t)startup, (uintptr_t)entrypt, + (uintptr_t)arg); PANIC(); } diff --git a/arch/or1k/src/common/up_reprioritizertr.c b/arch/or1k/src/common/up_reprioritizertr.c index 1c1ebd932ad..bf22ea41a7b 100644 --- a/arch/or1k/src/common/up_reprioritizertr.c +++ b/arch/or1k/src/common/up_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/or1k/src/common/up_saveusercontext.S b/arch/or1k/src/common/up_saveusercontext.S index 2cce3e3163a..4e92a6d2ffb 100644 --- a/arch/or1k/src/common/up_saveusercontext.S +++ b/arch/or1k/src/common/up_saveusercontext.S @@ -1,35 +1,20 @@ /************************************************************************** * arch/or1k/src/common/up_saveusercontext.S * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * **************************************************************************/ diff --git a/arch/or1k/src/common/up_task_start.c b/arch/or1k/src/common/up_task_start.c index d68cd27997a..f059611d73d 100644 --- a/arch/or1k/src/common/up_task_start.c +++ b/arch/or1k/src/common/up_task_start.c @@ -24,6 +24,7 @@ #include #include +#include #include "svcall.h" #include "up_internal.h" diff --git a/arch/or1k/src/common/up_uart.c b/arch/or1k/src/common/up_uart.c index 51c5989e516..c1f8eaa07cd 100644 --- a/arch/or1k/src/common/up_uart.c +++ b/arch/or1k/src/common/up_uart.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/or1k/src/common/up_uart.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/or1k/src/common/up_unblocktask.c b/arch/or1k/src/common/up_unblocktask.c index b66bc6186da..be26e53062b 100644 --- a/arch/or1k/src/common/up_unblocktask.c +++ b/arch/or1k/src/common/up_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/or1k/src/common/up_usestack.c b/arch/or1k/src/common/up_usestack.c index bf38cb7ae23..e2740db43b5 100644 --- a/arch/or1k/src/common/up_usestack.c +++ b/arch/or1k/src/common/up_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/or1k/src/mor1kx/Make.defs b/arch/or1k/src/mor1kx/Make.defs index d272b4d17b8..392820a9b25 100644 --- a/arch/or1k/src/mor1kx/Make.defs +++ b/arch/or1k/src/mor1kx/Make.defs @@ -1,35 +1,20 @@ ############################################################################ # arch/or1k/src/mor1kx/Make.defs # -# Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved. -# Author: Matt Thompson +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: +# http://www.apache.org/licenses/LICENSE-2.0 # -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. # ############################################################################ diff --git a/arch/or1k/src/mor1kx/Toolchain.defs b/arch/or1k/src/mor1kx/Toolchain.defs index 95fe2ceeee2..7fe32479a52 100644 --- a/arch/or1k/src/mor1kx/Toolchain.defs +++ b/arch/or1k/src/mor1kx/Toolchain.defs @@ -1,35 +1,20 @@ ############################################################################ # arch/or1k/src/mor1kx/Toolchain.defs # -# Copyright (C) 2018 Gregory Nutt. All rights reserved. -# Author: Matt Thompson +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: +# http://www.apache.org/licenses/LICENSE-2.0 # -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. # ############################################################################ @@ -49,6 +34,8 @@ ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -O2 endif # Pick correct or1k architecture selection @@ -61,7 +48,6 @@ endif #ifeq ($(CONFIG_OR1K_TOOLCHAIN),GNU_ELF) CROSSDEV ?= or1k-elf- -MAXOPTIMIZATION ?= -O2 ARCHCPUFLAGS = -mboard=de0_nano ARCHPICFLAGS = -fpic -membedded-pic LDFLAGS += -nostartfiles -nodefaultlibs @@ -73,7 +59,7 @@ LDSCRIPT = or1k-elf-debug.ld CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm diff --git a/arch/or1k/src/mor1kx/mor1kx_serial.c b/arch/or1k/src/mor1kx/mor1kx_serial.c index 8312f2284a7..627ee36d8bb 100644 --- a/arch/or1k/src/mor1kx/mor1kx_serial.c +++ b/arch/or1k/src/mor1kx/mor1kx_serial.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/or1k/src/mor1kx/mor1kx_serial.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/or1k/src/mor1kx/up_irq.c b/arch/or1k/src/mor1kx/up_irq.c index a3fd837db1f..34b4f37aea0 100644 --- a/arch/or1k/src/mor1kx/up_irq.c +++ b/arch/or1k/src/mor1kx/up_irq.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/or1k/src/mor1kx/up_irq.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Matt Thompson + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -40,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/renesas/Kconfig b/arch/renesas/Kconfig index 470e4f4ecb1..9c341de7642 100644 --- a/arch/renesas/Kconfig +++ b/arch/renesas/Kconfig @@ -57,25 +57,32 @@ config ARCH_SH1 bool default n +config ARCH_RENESAS_RX + bool + default n + select ARCH_HAVE_SETJMP + select CYGWIN_WINTOOL if WINDOWS_CYGWIN + config ARCH_RX65N bool default n - select CYGWIN_WINTOOL if WINDOWS_CYGWIN + select ARCH_RENESAS_RX config ARCH_RX65N_RSK1MB bool default n - select CYGWIN_WINTOOL if WINDOWS_CYGWIN + select ARCH_RENESAS_RX config ARCH_RX65N_RSK2MB bool default n - select CYGWIN_WINTOOL if WINDOWS_CYGWIN + select ARCH_RENESAS_RX + config ARCH_RX65N_GRROSE bool default n - select CYGWIN_WINTOOL if WINDOWS_CYGWIN + select ARCH_RENESAS_RX config ARCH_M16C bool @@ -85,10 +92,7 @@ config ARCH_CHIP string default "sh1" if ARCH_SH1 default "m16c" if ARCH_M16C - default "rx65n" if ARCH_RX65N - default "rx65n" if ARCH_RX65N_RSK1MB - default "rx65n" if ARCH_RX65N_RSK2MB - default "rx65n" if ARCH_RX65N_GRROSE + default "rx65n" if ARCH_RENESAS_RX source arch/renesas/src/common/Kconfig source arch/renesas/src/m16c/Kconfig diff --git a/arch/renesas/include/rx65n/inttypes.h b/arch/renesas/include/rx65n/inttypes.h index 0dc7bba2f2f..47e30b592f1 100644 --- a/arch/renesas/include/rx65n/inttypes.h +++ b/arch/renesas/include/rx65n/inttypes.h @@ -1,35 +1,21 @@ /**************************************************************************** * arch/renesas/include/rx65n/inttypes.h * - * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. - * Author: Anjana + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ #ifndef __ARCH_RENESAS_INCLUDE_RX65N_INTTYPES_H diff --git a/arch/renesas/include/setjmp.h b/arch/renesas/include/setjmp.h new file mode 100644 index 00000000000..5c288b78cdc --- /dev/null +++ b/arch/renesas/include/setjmp.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/renesas/include/setjmp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RENESAS_INCLUDE_SETJUMP_H +#define __ARCH_RENESAS_INCLUDE_SETJUMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#if defined(CONFIG_ARCH_RENESAS_RX) +struct setjmp_buf_s +{ + unsigned regs[10]; +}; + +/* Traditional typedef for setjmp_buf */ + +typedef struct setjmp_buf_s jmp_buf[1]; + +#else +# error "setjmp() not compiled!" +#endif /* CONFIG_ARCH_RX... */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int setjmp(jmp_buf env); +void longjmp(jmp_buf env, int val) noreturn_function; + +#endif /* __ARCH_RENESAS_INCLUDE_SETJUMP_H */ diff --git a/arch/renesas/src/common/up_blocktask.c b/arch/renesas/src/common/up_blocktask.c index 7dd31451ef8..7b8ac5276ac 100644 --- a/arch/renesas/src/common/up_blocktask.c +++ b/arch/renesas/src/common/up_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/arch/renesas/src/common/up_createstack.c b/arch/renesas/src/common/up_createstack.c index bf0ad9e3120..673a192b023 100644 --- a/arch/renesas/src/common/up_createstack.c +++ b/arch/renesas/src/common/up_createstack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/renesas/src/common/up_reprioritizertr.c b/arch/renesas/src/common/up_reprioritizertr.c index aaf2c52cbc5..75d3fcf9eb8 100644 --- a/arch/renesas/src/common/up_reprioritizertr.c +++ b/arch/renesas/src/common/up_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/renesas/src/common/up_unblocktask.c b/arch/renesas/src/common/up_unblocktask.c index a5401ea3e7c..a7df03de61c 100644 --- a/arch/renesas/src/common/up_unblocktask.c +++ b/arch/renesas/src/common/up_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/renesas/src/common/up_usestack.c b/arch/renesas/src/common/up_usestack.c index f35166db903..db2987a7650 100644 --- a/arch/renesas/src/common/up_usestack.c +++ b/arch/renesas/src/common/up_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/renesas/src/m16c/m16c_serial.c b/arch/renesas/src/m16c/m16c_serial.c index 5a517aab99b..37543fa0ce3 100644 --- a/arch/renesas/src/m16c/m16c_serial.c +++ b/arch/renesas/src/m16c/m16c_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/renesas/src/m16c/m16c_sigdeliver.c b/arch/renesas/src/m16c/m16c_sigdeliver.c index 6b2ba268528..561261ca89e 100644 --- a/arch/renesas/src/m16c/m16c_sigdeliver.c +++ b/arch/renesas/src/m16c/m16c_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/renesas/src/rx65n/rx65n_cmt.h b/arch/renesas/src/rx65n/rx65n_cmt.h index de7b04fa328..b2acae06754 100644 --- a/arch/renesas/src/rx65n/rx65n_cmt.h +++ b/arch/renesas/src/rx65n/rx65n_cmt.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/renesas/src/rx65n/rx65n_cmt.h * - * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. - * Author: Anjana + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_copystate.c b/arch/renesas/src/rx65n/rx65n_copystate.c index d1a9cd32f5e..e1a331b8cda 100644 --- a/arch/renesas/src/rx65n/rx65n_copystate.c +++ b/arch/renesas/src/rx65n/rx65n_copystate.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/renesas/src/rx65n/rx65n_copystate.c * - * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. - * Author: Anjana + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_dtc.c b/arch/renesas/src/rx65n/rx65n_dtc.c index c627f7b909e..1968ba91969 100644 --- a/arch/renesas/src/rx65n/rx65n_dtc.c +++ b/arch/renesas/src/rx65n/rx65n_dtc.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -1751,7 +1752,7 @@ void rx65n_dtc_initialize(void) #if defined(CONFIG_RX65N_DTC_SEQUENCE_TRANSFER_MODE) - /* In sequence transfer mode, set full addresss mode */ + /* In sequence transfer mode, set full address mode */ DTC.DTCADMOD.BIT.SHORT = 0; dtchandle->addmode = 0; diff --git a/arch/renesas/src/rx65n/rx65n_eth.c b/arch/renesas/src/rx65n/rx65n_eth.c index b41d5efdcd9..cba34aedf2c 100644 --- a/arch/renesas/src/rx65n/rx65n_eth.c +++ b/arch/renesas/src/rx65n/rx65n_eth.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/renesas/src/rx65n/rx65n_head.S b/arch/renesas/src/rx65n/rx65n_head.S index c9d2365e005..905a06fa98c 100644 --- a/arch/renesas/src/rx65n/rx65n_head.S +++ b/arch/renesas/src/rx65n/rx65n_head.S @@ -1,35 +1,20 @@ /**************************************************************************** * arch/renesas/src/rx65n/rx65n_head.S * - * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. - * Author: Anjana + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_icu.c b/arch/renesas/src/rx65n/rx65n_icu.c index fe7fd7e252d..912008aa1a8 100644 --- a/arch/renesas/src/rx65n/rx65n_icu.c +++ b/arch/renesas/src/rx65n/rx65n_icu.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/renesas/src/rx65n/rx65n_icu.c * - * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. - * Author: Anjana + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_riic.c b/arch/renesas/src/rx65n/rx65n_riic.c index ee2d225e138..2fdd7578156 100644 --- a/arch/renesas/src/rx65n/rx65n_riic.c +++ b/arch/renesas/src/rx65n/rx65n_riic.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include diff --git a/arch/renesas/src/rx65n/rx65n_rspi.c b/arch/renesas/src/rx65n/rx65n_rspi.c index e91c77f0363..df7ff615e31 100644 --- a/arch/renesas/src/rx65n/rx65n_rspi.c +++ b/arch/renesas/src/rx65n/rx65n_rspi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -1841,19 +1842,19 @@ static void rspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = RSPI_SPCMD_PHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = RSPI_SPCMD_POL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = RSPI_SPCMD_PHA | RSPI_SPCMD_POL; break; diff --git a/arch/renesas/src/rx65n/rx65n_rspi_sw.c b/arch/renesas/src/rx65n/rx65n_rspi_sw.c index b530043dd6e..2a66d216741 100644 --- a/arch/renesas/src/rx65n/rx65n_rspi_sw.c +++ b/arch/renesas/src/rx65n/rx65n_rspi_sw.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -1476,19 +1477,19 @@ static void rspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = RSPI_SPCMD_PHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = RSPI_SPCMD_POL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = RSPI_SPCMD_PHA | RSPI_SPCMD_POL; break; diff --git a/arch/renesas/src/rx65n/rx65n_rtc.c b/arch/renesas/src/rx65n/rx65n_rtc.c index c1aefa9ba43..9a675b7710f 100644 --- a/arch/renesas/src/rx65n/rx65n_rtc.c +++ b/arch/renesas/src/rx65n/rx65n_rtc.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c b/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c index e545848608c..bb5cfa04ce3 100644 --- a/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c +++ b/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/renesas/src/rx65n/rx65n_sbram.c b/arch/renesas/src/rx65n/rx65n_sbram.c index f9c7d2093c6..a8c62235dd2 100644 --- a/arch/renesas/src/rx65n/rx65n_sbram.c +++ b/arch/renesas/src/rx65n/rx65n_sbram.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/renesas/src/rx65n/rx65n_serial.c b/arch/renesas/src/rx65n/rx65n_serial.c index 82f10881d1f..41f79c41435 100644 --- a/arch/renesas/src/rx65n/rx65n_serial.c +++ b/arch/renesas/src/rx65n/rx65n_serial.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -280,6 +281,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_xmtinterrupt(int irq, void *context, FAR void *arg); static int up_rcvinterrupt(int irq, void *context, FAR void *arg); static int up_eriinterrupt(int irq, void *context, FAR void *arg); @@ -364,6 +366,7 @@ struct uart_ops_s g_sci_ops = .attach = up_attach, .detach = up_detach, .receive = up_receive, + .ioctl = up_ioctl, .rxint = up_rxint, .rxavailable = up_rxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL @@ -1281,6 +1284,31 @@ static int up_xmtinterrupt(int irq, void *context, FAR void *arg) return OK; } +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TERMIOS +#error CONFIG_SERIAL_TERMIOS NOT IMPLEMENTED +#endif /* CONFIG_SERIAL_TERMIOS */ + default: + ret = -ENOTTY; + break; + } + + return ret; +} + /**************************************************************************** * Name: up_receive * diff --git a/arch/renesas/src/rx65n/rx65n_sigdeliver.c b/arch/renesas/src/rx65n/rx65n_sigdeliver.c index 2b288dc72d9..1c405f7720d 100644 --- a/arch/renesas/src/rx65n/rx65n_sigdeliver.c +++ b/arch/renesas/src/rx65n/rx65n_sigdeliver.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/renesas/src/rx65n/rx65n_sigdeliver.c * - * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. - * Author: Anjana + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -41,6 +26,7 @@ #include #include +#include #include #include @@ -67,7 +53,6 @@ void up_sigdeliver(void) { -#ifndef CONFIG_DISABLE_SIGNALS struct tcb_s *rtcb = this_task(); uint32_t regs[XCPTCONTEXT_REGS]; sig_deliver_t sigdeliver; @@ -127,5 +112,4 @@ void up_sigdeliver(void) board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); -#endif } diff --git a/arch/renesas/src/rx65n/rx65n_usbdev.c b/arch/renesas/src/rx65n/rx65n_usbdev.c index 0098232dcb3..5f5570b8844 100644 --- a/arch/renesas/src/rx65n/rx65n_usbdev.c +++ b/arch/renesas/src/rx65n/rx65n_usbdev.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -2888,7 +2889,7 @@ static int rx65n_epconfigure(FAR struct usbdev_ep_s *ep, if (!ep || !desc) { usbtrace(TRACE_DEVERROR(RX65N_TRACEERR_INVALIDPARMS), 0); - printf("ERROR: ep=%p desc=%p\n"); + printf("ERROR: ep=%p desc=%p\n", ep, desc); return -EINVAL; } #endif @@ -5425,7 +5426,7 @@ void usb_pstd_brdy_pipe_process(uint16_t bitsts) * Name: usb_pstd_brdy_pipe * * Description: - * Handle BRDY Interupt + * Handle BRDY Interrupt * ****************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_usbhost.c b/arch/renesas/src/rx65n/rx65n_usbhost.c index ca057ba2111..cff082f7189 100644 --- a/arch/renesas/src/rx65n/rx65n_usbhost.c +++ b/arch/renesas/src/rx65n/rx65n_usbhost.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/arch/renesas/src/sh1/sh1_serial.c b/arch/renesas/src/sh1/sh1_serial.c index 818f0f1b2f7..46324829134 100644 --- a/arch/renesas/src/sh1/sh1_serial.c +++ b/arch/renesas/src/sh1/sh1_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/renesas/src/sh1/sh1_sigdeliver.c b/arch/renesas/src/sh1/sh1_sigdeliver.c index dfca5b616c8..584157325c2 100644 --- a/arch/renesas/src/sh1/sh1_sigdeliver.c +++ b/arch/renesas/src/sh1/sh1_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index 074827444e2..9d2281d0b36 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -50,6 +50,7 @@ config ARCH_CHIP_ESP32C3 select LIBC_ARCH_MEMCCMP select LIBC_ARCH_MEMMOVE select LIBC_ARCH_MEMSET + select ARCH_HAVE_TEXT_HEAP ---help--- Espressif ESP32-C3 (RV32IMC). @@ -60,6 +61,20 @@ config ARCH_CHIP_C906 ---help--- THEAD C906 processor (RISC-V 64bit core with GCVX extensions). +config ARCH_CHIP_MPFS + bool "MicroChip Polarfire (MPFS)" + select ARCH_RV64GC + select ARCH_HAVE_MPU + select ARCH_HAVE_RESET + ---help--- + MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions). + +config ARCH_CHIP_RV32M1 + bool "NXP RV32M1" + select ARCH_RV32IM + ---help--- + NXP RV32M1 processor (RISC-V Core with PULP extensions). + config ARCH_CHIP_RISCV_CUSTOM bool "Custom RISC-V chip" select ARCH_CHIP_CUSTOM @@ -97,6 +112,23 @@ config ARCH_CHIP default "bl602" if ARCH_CHIP_BL602 default "esp32c3" if ARCH_CHIP_ESP32C3 default "c906" if ARCH_CHIP_C906 + default "mpfs" if ARCH_CHIP_MPFS + default "rv32m1" if ARCH_CHIP_RV32M1 + +config ARCH_RISCV_INTXCPT_EXTENSIONS + bool "RISC-V Integer Context Extensions" + default n + ---help--- + RISC-V could be customized with extensions. Some Integer Context + Registers have to be saved and restored when Contexts switch. + +if ARCH_RISCV_INTXCPT_EXTENSIONS + +config ARCH_RISCV_INTXCPT_EXTREGS + int "Number of Extral RISC-V Integer Context Registers" + default 0 + +endif if ARCH_RV32IM source arch/risc-v/src/rv32im/Kconfig @@ -122,4 +154,10 @@ endif if ARCH_CHIP_C906 source arch/risc-v/src/c906/Kconfig endif +if ARCH_CHIP_MPFS +source arch/risc-v/src/mpfs/Kconfig +endif +if ARCH_CHIP_RV32M1 +source arch/risc-v/src/rv32m1/Kconfig +endif endif diff --git a/arch/risc-v/include/c906/irq.h b/arch/risc-v/include/c906/irq.h index a670d7c3b10..b6f852bbc2d 100644 --- a/arch/risc-v/include/c906/irq.h +++ b/arch/risc-v/include/c906/irq.h @@ -72,36 +72,4 @@ #define NR_IRQS (C906_IRQ_UART0 + 1) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -EXTERN irqstate_t up_irq_save(void); -EXTERN void up_irq_restore(irqstate_t); -EXTERN irqstate_t up_irq_enable(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_RISCV_INCLUDE_C906_IRQ_H */ diff --git a/arch/risc-v/include/esp32c3/esp_efuse_table.h b/arch/risc-v/include/esp32c3/esp_efuse_table.h new file mode 100644 index 00000000000..a8a7d5d69e8 --- /dev/null +++ b/arch/risc-v/include/esp32c3/esp_efuse_table.h @@ -0,0 +1,130 @@ +/**************************************************************************** + * arch/risc-v/include/esp32c3/esp_efuse_table.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_1[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK1[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_USER_DATA[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY0[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY1[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY2[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY3[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY4[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY5[]; +extern const efuse_desc_t *ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY0[]; +extern const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY1[]; +extern const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY2[]; +extern const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY3[]; +extern const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY4[]; +extern const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY5[]; +extern const efuse_desc_t *ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_RTC_RAM_BOOT[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_ICACHE[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_USB_JTAG[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_USB_DEVICE[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_USB[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_CAN[]; +extern const efuse_desc_t *ESP_EFUSE_JTAG_SEL_ENABLE[]; +extern const efuse_desc_t *ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_PAD_JTAG[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const efuse_desc_t *ESP_EFUSE_USB_DREFH[]; +extern const efuse_desc_t *ESP_EFUSE_USB_DREFL[]; +extern const efuse_desc_t *ESP_EFUSE_USB_EXCHG_PINS[]; +extern const efuse_desc_t *ESP_EFUSE_VDD_SPI_AS_GPIO[]; +extern const efuse_desc_t *ESP_EFUSE_BTLC_GPIO_ENABLE[]; +extern const efuse_desc_t *ESP_EFUSE_POWERGLITCH_EN[]; +extern const efuse_desc_t *ESP_EFUSE_POWER_GLITCH_DSENSE[]; +extern const efuse_desc_t *ESP_EFUSE_WDT_DELAY_SEL[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_0[]; +extern const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_1[]; +extern const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_2[]; +extern const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_3[]; +extern const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_4[]; +extern const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_5[]; +extern const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_EN[]; +extern const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const efuse_desc_t *ESP_EFUSE_FLASH_TPUW[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_LEGACY_SPI_BOOT[]; +extern const efuse_desc_t *ESP_EFUSE_UART_PRINT_CHANNEL[]; +extern const efuse_desc_t *ESP_EFUSE_FLASH_ECC_MODE[]; +extern const efuse_desc_t *ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[]; +extern const efuse_desc_t *ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const efuse_desc_t *ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const efuse_desc_t *ESP_EFUSE_PIN_POWER_SELECTION[]; +extern const efuse_desc_t *ESP_EFUSE_FLASH_TYPE[]; +extern const efuse_desc_t *ESP_EFUSE_FLASH_PAGE_SIZE[]; +extern const efuse_desc_t *ESP_EFUSE_FLASH_ECC_EN[]; +extern const efuse_desc_t *ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const efuse_desc_t *ESP_EFUSE_SECURE_VERSION[]; +extern const efuse_desc_t *ESP_EFUSE_MAC_FACTORY[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_CS[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D4[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D5[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D6[]; +extern const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D7[]; +extern const efuse_desc_t *ESP_EFUSE_SYS_DATA_PART1[]; +extern const efuse_desc_t *ESP_EFUSE_USER_DATA[]; +extern const efuse_desc_t *ESP_EFUSE_KEY0[]; +extern const efuse_desc_t *ESP_EFUSE_KEY1[]; +extern const efuse_desc_t *ESP_EFUSE_KEY2[]; +extern const efuse_desc_t *ESP_EFUSE_KEY3[]; +extern const efuse_desc_t *ESP_EFUSE_KEY4[]; +extern const efuse_desc_t *ESP_EFUSE_KEY5[]; +extern const efuse_desc_t *ESP_EFUSE_SYS_DATA_PART2[]; + +#ifdef __cplusplus +} +#endif + diff --git a/arch/risc-v/include/esp32c3/irq.h b/arch/risc-v/include/esp32c3/irq.h index a6ec2a744d8..1b4475872a2 100644 --- a/arch/risc-v/include/esp32c3/irq.h +++ b/arch/risc-v/include/esp32c3/irq.h @@ -27,8 +27,11 @@ #ifndef __ASSEMBLY__ # include +# include #endif +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -95,8 +98,8 @@ #define ESP32C3_PERIPH_ICACHE_SYNC0 42 #define ESP32C3_PERIPH_APB_ADC 43 #define ESP32C3_PERIPH_DMA_CH0 44 -#define ESP32C3_PERIPH_DMA_CH0 45 -#define ESP32C3_PERIPH_DMA_CH0 46 +#define ESP32C3_PERIPH_DMA_CH1 45 +#define ESP32C3_PERIPH_DMA_CH2 46 #define ESP32C3_PERIPH_RSA 47 #define ESP32C3_PERIPH_AES 48 #define ESP32C3_PERIPH_SHA 49 @@ -130,6 +133,8 @@ /* Reserved CPU interrupt for specific drivers */ #define ESP32C3_CPUINT_WMAC 1 /* Wi-Fi MAC */ +#define ESP32C3_CPUINT_BT_BB 5 /* BT BB */ +#define ESP32C3_CPUINT_RWBLE 8 /* RW BLE */ /* IRQ numbers. */ @@ -186,8 +191,8 @@ #define ESP32C3_IRQ_ICACHE_SYNC0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_ICACHE_SYNC0) #define ESP32C3_IRQ_APB_ADC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_APB_ADC) #define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0) -#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0) -#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0) +#define ESP32C3_IRQ_DMA_CH1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH1) +#define ESP32C3_IRQ_DMA_CH2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH2) #define ESP32C3_IRQ_RSA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RSA) #define ESP32C3_IRQ_AES (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_AES) #define ESP32C3_IRQ_SHA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SHA) @@ -225,89 +230,4 @@ #define NR_IRQS (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH + ESP32C3_NIRQ_GPIO) -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Name: up_irq_restore - * - * Description: - * Restore the value of the mstatus register - * - ****************************************************************************/ - -static inline void up_irq_restore(irqstate_t flags) -{ - __asm__ __volatile__ - ( - "csrw mstatus, %0" : /* no output */ : "r" (flags) - ); -} - -/**************************************************************************** - * Name: up_irq_save - * - * Description: - * Disable interrupts and return the previous value of the mstatus register - * - ****************************************************************************/ - -static inline irqstate_t up_irq_save(void) -{ - irqstate_t flags; - - /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ - - __asm__ __volatile__ - ( - "csrrc %0, mstatus, %1" : "=r" (flags) : "r"(MSTATUS_MIE) - ); - - /* Return the previous mstatus value so that it can be restored with - * up_irq_restore(). - */ - - return flags; -} - -/**************************************************************************** - * Name: up_irq_enable - * - * Description: - * Return the current interrupt state and enable interrupts - * - ****************************************************************************/ - -static inline irqstate_t up_irq_enable(void) -{ - uint32_t flags; - - /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - - __asm__ __volatile__ - ( - "csrrs %0, mstatus, %1": "=r" (flags) : "r"(MSTATUS_MIE) - ); - - return flags; -} - -/**************************************************************************** - * Name: up_irq_disable - * - * Description: - * Disable interrupts - * - ****************************************************************************/ - -static inline void up_irq_disable(void) -{ - up_irq_save(); -} - -#endif /* __ASSEMBLY__ */ - #endif /* __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H */ diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h index 6622f2cfb16..00241adc838 100644 --- a/arch/risc-v/include/irq.h +++ b/arch/risc-v/include/irq.h @@ -33,6 +33,7 @@ #include #include +#include #include /* Include RISC-V architecture-specific IRQ definitions */ @@ -64,12 +65,70 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irq_save + * + * Description: + * Disable interrupts and return the previous value of the mstatus register + * + ****************************************************************************/ + +static inline irqstate_t up_irq_save(void) +{ + irqstate_t flags; + + /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ + + __asm__ __volatile__ + ( + "csrrc %0, mstatus, %1\n" + : "=r" (flags) + : "r"(MSTATUS_MIE) + : "memory" + ); + + /* Return the previous mstatus value so that it can be restored with + * up_irq_restore(). + */ + + return flags; +} + +/**************************************************************************** + * Name: up_irq_restore + * + * Description: + * Restore the value of the mstatus register + * + ****************************************************************************/ + +static inline void up_irq_restore(irqstate_t flags) +{ + __asm__ __volatile__ + ( + "csrw mstatus, %0\n" + : /* no output */ + : "r" (flags) + : "memory" + ); +} + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -EXTERN irqstate_t up_irq_save(void); -EXTERN void up_irq_restore(irqstate_t); +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Return the current interrupt state and enable interrupts + * + ****************************************************************************/ + EXTERN irqstate_t up_irq_enable(void); #undef EXTERN diff --git a/arch/risc-v/include/mpfs/chip.h b/arch/risc-v/include/mpfs/chip.h new file mode 100755 index 00000000000..0efd02220d0 --- /dev/null +++ b/arch/risc-v/include/mpfs/chip.h @@ -0,0 +1,34 @@ +/**************************************************************************** + * arch/risc-v/include/mpfs/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_MPFS_CHIP_H +#define __ARCH_RISCV_INCLUDE_MPFS_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include + +#endif /* __ARCH_RISCV_INCLUDE_MPFS_CHIP_H */ diff --git a/arch/risc-v/include/mpfs/irq.h b/arch/risc-v/include/mpfs/irq.h new file mode 100755 index 00000000000..4ee52acefc9 --- /dev/null +++ b/arch/risc-v/include/mpfs/irq.h @@ -0,0 +1,308 @@ +/**************************************************************************** + * arch/risc-v/include/mpfs/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_MPFS_IRQ_H +#define __ARCH_RISCV_INCLUDE_MPFS_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Map RISC-V exception code to NuttX IRQ */ + +/* IRQ 0-15 : (exception:interrupt=0) */ + +#define MPFS_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */ +#define MPFS_IRQ_IAFAULT (1) /* Instruction Address Fault */ +#define MPFS_IRQ_IINSTRUCTION (2) /* Illegal Instruction */ +#define MPFS_IRQ_BPOINT (3) /* Break Point */ +#define MPFS_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */ +#define MPFS_IRQ_LAFAULT (5) /* Load Access Fault */ +#define MPFS_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */ +#define MPFS_IRQ_SAFAULT (7) /* Store/AMO Access Fault */ +#define MPFS_IRQ_ECALLU (8) /* Environment Call from U-mode */ +#define MPFS_IRQ_ECALLS (9) /* Environment Call from S-mode */ +#define MPFS_IRQ_ECALLH (10) /* Environment Call from H-mode */ +#define MPFS_IRQ_ECALLM (11) /* Environment Call from M-mode */ +#define MPFS_IRQ_INSTRUCTIONPF (12) /* Instruction page fault */ +#define MPFS_IRQ_LOADPF (13) /* Load page fault */ +#define MPFS_IRQ_RESERVED (14) /* Reserved */ +#define MPFS_IRQ_SROREPF (15) /* Store/AMO page fault */ + +/* IRQ 16- : (async event:interrupt=1) */ + +#define MPFS_IRQ_ASYNC (16) +#define MPFS_IRQ_SSOFT (MPFS_IRQ_ASYNC + 1) /* Supervisor Software Int */ +#define MPFS_IRQ_MSOFT (MPFS_IRQ_ASYNC + 3) /* Machine Software Int */ +#define MPFS_IRQ_STIMER (MPFS_IRQ_ASYNC + 5) /* Supervisor Timer Int */ +#define MPFS_IRQ_MTIMER (MPFS_IRQ_ASYNC + 7) /* Machine Timer Int */ +#define MPFS_IRQ_SEXT (MPFS_IRQ_ASYNC + 9) /* Supervisor External Int */ +#define MPFS_IRQ_MEXT (MPFS_IRQ_ASYNC + 11) /* Machine External Int */ + +/* IRQ 32-79 : 47 Local interrupts. */ + +#define MPFS_IRQ_LOCAL_START (MPFS_IRQ_ASYNC + 16) +#define MPFS_IRQ_LOCAL_0 (MPFS_IRQ_LOCAL_START + 0) /* Local 0 spare */ +#define MPFS_IRQ_LOCAL_1 (MPFS_IRQ_LOCAL_START + 1) /* Local 1 spare */ +#define MPFS_IRQ_LOCAL_2 (MPFS_IRQ_LOCAL_START + 2) /* Local 2 spare */ +#define MPFS_IRQ_LOCAL_U54_MAC_MMSL (MPFS_IRQ_LOCAL_START + 3) /* check hartid for mac source */ +#define MPFS_IRQ_LOCAL_U54_MAC_EMAC (MPFS_IRQ_LOCAL_START + 4) +#define MPFS_IRQ_LOCAL_U54_MAC_QUE3 (MPFS_IRQ_LOCAL_START + 5) +#define MPFS_IRQ_LOCAL_U54_MAC_QUE2 (MPFS_IRQ_LOCAL_START + 6) +#define MPFS_IRQ_LOCAL_U54_MAC_QUE1 (MPFS_IRQ_LOCAL_START + 7) +#define MPFS_IRQ_LOCAL_U54_MAC_INT (MPFS_IRQ_LOCAL_START + 8) +#define MPFS_IRQ_LOCAL_U54_WDOG_TOUT (MPFS_IRQ_LOCAL_START + 9) /* check hartid for wdog source */ +#define MPFS_IRQ_LOCAL_U54_MVRP (MPFS_IRQ_LOCAL_START + 10) +#define MPFS_IRQ_LOCAL_E51_MMUART0 (MPFS_IRQ_LOCAL_START + 11) +#define MPFS_IRQ_LOCAL_U54_H1_MMUART1 (MPFS_IRQ_LOCAL_START + 11) +#define MPFS_IRQ_LOCAL_U54_H2_MMUART2 (MPFS_IRQ_LOCAL_START + 11) +#define MPFS_IRQ_LOCAL_U54_H3_MMUART3 (MPFS_IRQ_LOCAL_START + 11) +#define MPFS_IRQ_LOCAL_U54_H4_MMUART4 (MPFS_IRQ_LOCAL_START + 11) +#define MPFS_IRQ_LOCAL_12 (MPFS_IRQ_LOCAL_START + 12) /* Local 12 spare */ +#define MPFS_IRQ_LOCAL_13 (MPFS_IRQ_LOCAL_START + 13) /* Local 13 spare */ +#define MPFS_IRQ_LOCAL_14 (MPFS_IRQ_LOCAL_START + 14) /* Local 14 spare */ +#define MPFS_IRQ_LOCAL_15 (MPFS_IRQ_LOCAL_START + 15) /* Local 15 spare */ +#define MPFS_IRQ_LOCAL_U54_F2H_0 (MPFS_IRQ_LOCAL_START + 16) /* Fabric 0 */ +#define MPFS_IRQ_LOCAL_U54_F2H_1 (MPFS_IRQ_LOCAL_START + 17) /* Fabric 1 */ +#define MPFS_IRQ_LOCAL_U54_F2H_2 (MPFS_IRQ_LOCAL_START + 18) /* Fabric 2 */ +#define MPFS_IRQ_LOCAL_U54_F2H_3 (MPFS_IRQ_LOCAL_START + 19) /* Fabric 3 */ +#define MPFS_IRQ_LOCAL_U54_F2H_4 (MPFS_IRQ_LOCAL_START + 20) /* Fabric 4 */ +#define MPFS_IRQ_LOCAL_U54_F2H_5 (MPFS_IRQ_LOCAL_START + 21) /* Fabric 5 */ +#define MPFS_IRQ_LOCAL_U54_F2H_6 (MPFS_IRQ_LOCAL_START + 22) /* Fabric 6 */ +#define MPFS_IRQ_LOCAL_U54_F2H_7 (MPFS_IRQ_LOCAL_START + 23) /* Fabric 7 */ +#define MPFS_IRQ_LOCAL_U54_F2H_8 (MPFS_IRQ_LOCAL_START + 24) /* Fabric 8 */ +#define MPFS_IRQ_LOCAL_U54_F2H_9 (MPFS_IRQ_LOCAL_START + 25) /* Fabric 9 */ +#define MPFS_IRQ_LOCAL_U54_F2H_10 (MPFS_IRQ_LOCAL_START + 26) /* Fabric 10 */ +#define MPFS_IRQ_LOCAL_U54_F2H_11 (MPFS_IRQ_LOCAL_START + 27) /* Fabric 11 */ +#define MPFS_IRQ_LOCAL_U54_F2H_12 (MPFS_IRQ_LOCAL_START + 28) /* Fabric 12 */ +#define MPFS_IRQ_LOCAL_U54_F2H_13 (MPFS_IRQ_LOCAL_START + 29) /* Fabric 13 */ +#define MPFS_IRQ_LOCAL_U54_F2H_14 (MPFS_IRQ_LOCAL_START + 30) /* Fabric 14 */ +#define MPFS_IRQ_LOCAL_U54_F2H_15 (MPFS_IRQ_LOCAL_START + 31) /* Fabric 15 */ +#define MPFS_IRQ_LOCAL_U54_F2H_16 (MPFS_IRQ_LOCAL_START + 32) /* Fabric 16 */ +#define MPFS_IRQ_LOCAL_U54_F2H_17 (MPFS_IRQ_LOCAL_START + 33) /* Fabric 17 */ +#define MPFS_IRQ_LOCAL_U54_F2H_18 (MPFS_IRQ_LOCAL_START + 34) /* Fabric 18 */ +#define MPFS_IRQ_LOCAL_U54_F2H_19 (MPFS_IRQ_LOCAL_START + 35) /* Fabric 19 */ +#define MPFS_IRQ_LOCAL_U54_F2H_20 (MPFS_IRQ_LOCAL_START + 36) /* Fabric 20 */ +#define MPFS_IRQ_LOCAL_U54_F2H_21 (MPFS_IRQ_LOCAL_START + 37) /* Fabric 21 */ +#define MPFS_IRQ_LOCAL_U54_F2H_22 (MPFS_IRQ_LOCAL_START + 38) /* Fabric 22 */ +#define MPFS_IRQ_LOCAL_U54_F2H_23 (MPFS_IRQ_LOCAL_START + 39) /* Fabric 23 */ +#define MPFS_IRQ_LOCAL_U54_F2H_24 (MPFS_IRQ_LOCAL_START + 40) /* Fabric 24 */ +#define MPFS_IRQ_LOCAL_U54_F2H_25 (MPFS_IRQ_LOCAL_START + 41) /* Fabric 25 */ +#define MPFS_IRQ_LOCAL_U54_F2H_26 (MPFS_IRQ_LOCAL_START + 42) /* Fabric 26 */ +#define MPFS_IRQ_LOCAL_U54_F2H_27 (MPFS_IRQ_LOCAL_START + 43) /* Fabric 27 */ +#define MPFS_IRQ_LOCAL_U54_F2H_28 (MPFS_IRQ_LOCAL_START + 44) /* Fabric 28 */ +#define MPFS_IRQ_LOCAL_U54_F2H_29 (MPFS_IRQ_LOCAL_START + 45) /* Fabric 29 */ +#define MPFS_IRQ_LOCAL_U54_F2H_30 (MPFS_IRQ_LOCAL_START + 46) /* Fabric 30 */ +#define MPFS_IRQ_LOCAL_U54_F2H_31 (MPFS_IRQ_LOCAL_START + 47) /* Fabric 31 */ + +/* External Interrupts. if irq is MPFS_IRQ_MEXT or MPFS_IRQ_SEXT */ + +#define MPFS_IRQ_EXT_START (MPFS_IRQ_ASYNC + 80U) +#define MPFS_IRQ_INVALID (MPFS_IRQ_EXT_START + 0) +#define MPFS_IRQ_L2_METADATA_CORR (MPFS_IRQ_EXT_START + 1) +#define MPFS_IRQ_L2_METADATA_UNCORR (MPFS_IRQ_EXT_START + 2) +#define MPFS_IRQ_L2_DATA_CORR (MPFS_IRQ_EXT_START + 3) +#define MPFS_IRQ_L2_DATA_UNCORR (MPFS_IRQ_EXT_START + 4) +#define MPFS_IRQ_DMA_CH0_DONE (MPFS_IRQ_EXT_START + 5) +#define MPFS_IRQ_DMA_CH0_ERR (MPFS_IRQ_EXT_START + 6) +#define MPFS_IRQ_DMA_CH1_DONE (MPFS_IRQ_EXT_START + 7) +#define MPFS_IRQ_DMA_CH1_ERR (MPFS_IRQ_EXT_START + 8) +#define MPFS_IRQ_DMA_CH2_DONE (MPFS_IRQ_EXT_START + 9) +#define MPFS_IRQ_DMA_CH2_ERR (MPFS_IRQ_EXT_START + 10) +#define MPFS_IRQ_DMA_CH3_DONE (MPFS_IRQ_EXT_START + 11) +#define MPFS_IRQ_DMA_CH3_ERR (MPFS_IRQ_EXT_START + 12) + +/* Global Interrupts */ + +#define OFFSET_TO_MSS_GLOBAL_INTS (13U) +#define MPFS_IRQ_GLOBAL_START (MPFS_IRQ_EXT_START + OFFSET_TO_MSS_GLOBAL_INTS) +#define MPFS_IRQ_GPIO02_BIT0 (MPFS_IRQ_GLOBAL_START + 0) +#define MPFS_IRQ_GPIO02_BIT1 (MPFS_IRQ_GLOBAL_START + 1) +#define MPFS_IRQ_GPIO02_BIT2 (MPFS_IRQ_GLOBAL_START + 2) +#define MPFS_IRQ_GPIO02_BIT3 (MPFS_IRQ_GLOBAL_START + 3) +#define MPFS_IRQ_GPIO02_BIT4 (MPFS_IRQ_GLOBAL_START + 4) +#define MPFS_IRQ_GPIO02_BIT5 (MPFS_IRQ_GLOBAL_START + 5) +#define MPFS_IRQ_GPIO02_BIT6 (MPFS_IRQ_GLOBAL_START + 6) +#define MPFS_IRQ_GPIO02_BIT7 (MPFS_IRQ_GLOBAL_START + 7) +#define MPFS_IRQ_GPIO02_BIT8 (MPFS_IRQ_GLOBAL_START + 8) +#define MPFS_IRQ_GPIO02_BIT9 (MPFS_IRQ_GLOBAL_START + 9) +#define MPFS_IRQ_GPIO02_BIT10 (MPFS_IRQ_GLOBAL_START + 10) +#define MPFS_IRQ_GPIO02_BIT11 (MPFS_IRQ_GLOBAL_START + 11) +#define MPFS_IRQ_GPIO02_BIT12 (MPFS_IRQ_GLOBAL_START + 12) +#define MPFS_IRQ_GPIO02_BIT13 (MPFS_IRQ_GLOBAL_START + 13) +#define MPFS_IRQ_GPIO1_BIT0_OR_GPIO2_BIT14 (MPFS_IRQ_GLOBAL_START + 14) +#define MPFS_IRQ_GPIO1_BIT1_OR_GPIO2_BIT15 (MPFS_IRQ_GLOBAL_START + 15) +#define MPFS_IRQ_GPIO1_BIT2_OR_GPIO2_BIT16 (MPFS_IRQ_GLOBAL_START + 16) +#define MPFS_IRQ_GPIO1_BIT3_OR_GPIO2_BIT17 (MPFS_IRQ_GLOBAL_START + 17) +#define MPFS_IRQ_GPIO1_BIT4_OR_GPIO2_BIT18 (MPFS_IRQ_GLOBAL_START + 18) +#define MPFS_IRQ_GPIO1_BIT5_OR_GPIO2_BIT19 (MPFS_IRQ_GLOBAL_START + 19) +#define MPFS_IRQ_GPIO1_BIT6_OR_GPIO2_BIT20 (MPFS_IRQ_GLOBAL_START + 20) +#define MPFS_IRQ_GPIO1_BIT7_OR_GPIO2_BIT21 (MPFS_IRQ_GLOBAL_START + 21) +#define MPFS_IRQ_GPIO1_BIT8_OR_GPIO2_BIT22 (MPFS_IRQ_GLOBAL_START + 22) +#define MPFS_IRQ_GPIO1_BIT9_OR_GPIO2_BIT23 (MPFS_IRQ_GLOBAL_START + 23) +#define MPFS_IRQ_GPIO1_BIT10_OR_GPIO2_BIT24 (MPFS_IRQ_GLOBAL_START + 24) +#define MPFS_IRQ_GPIO1_BIT11_OR_GPIO2_BIT25 (MPFS_IRQ_GLOBAL_START + 25) +#define MPFS_IRQ_GPIO1_BIT12_OR_GPIO2_BIT26 (MPFS_IRQ_GLOBAL_START + 26) +#define MPFS_IRQ_GPIO1_BIT13_OR_GPIO2_BIT27 (MPFS_IRQ_GLOBAL_START + 27) +#define MPFS_IRQ_GPIO1_BIT14_OR_GPIO2_BIT28 (MPFS_IRQ_GLOBAL_START + 28) +#define MPFS_IRQ_GPIO1_BIT15_OR_GPIO2_BIT29 (MPFS_IRQ_GLOBAL_START + 29) +#define MPFS_IRQ_GPIO1_BIT16_OR_GPIO2_BIT30 (MPFS_IRQ_GLOBAL_START + 30) +#define MPFS_IRQ_GPIO1_BIT17_OR_GPIO2_BIT31 (MPFS_IRQ_GLOBAL_START + 31) +#define MPFS_IRQ_GPIO1_BIT18 (MPFS_IRQ_GLOBAL_START + 32) +#define MPFS_IRQ_GPIO1_BIT19 (MPFS_IRQ_GLOBAL_START + 33) +#define MPFS_IRQ_GPIO1_BIT20 (MPFS_IRQ_GLOBAL_START + 34) +#define MPFS_IRQ_GPIO1_BIT21 (MPFS_IRQ_GLOBAL_START + 35) +#define MPFS_IRQ_GPIO1_BIT22 (MPFS_IRQ_GLOBAL_START + 36) +#define MPFS_IRQ_GPIO1_BIT23 (MPFS_IRQ_GLOBAL_START + 37) +#define MPFS_IRQ_GPIO0_NON_DIRECT (MPFS_IRQ_GLOBAL_START + 38) +#define MPFS_IRQ_GPIO1_NON_DIRECT (MPFS_IRQ_GLOBAL_START + 39) +#define MPFS_IRQ_GPIO2_NON_DIRECT (MPFS_IRQ_GLOBAL_START + 40) +#define MPFS_IRQ_SPI0 (MPFS_IRQ_GLOBAL_START + 41) +#define MPFS_IRQ_SPI1 (MPFS_IRQ_GLOBAL_START + 42) +#define MPFS_IRQ_CAN0 (MPFS_IRQ_GLOBAL_START + 43) +#define MPFS_IRQ_CAN1 (MPFS_IRQ_GLOBAL_START + 44) +#define MPFS_IRQ_I2C0_MAIN (MPFS_IRQ_GLOBAL_START + 45) +#define MPFS_IRQ_I2C0_ALERT (MPFS_IRQ_GLOBAL_START + 46) +#define MPFS_IRQ_I2C0_SUS (MPFS_IRQ_GLOBAL_START + 47) +#define MPFS_IRQ_I2C1_MAIN (MPFS_IRQ_GLOBAL_START + 48) +#define MPFS_IRQ_I2C1_ALERT (MPFS_IRQ_GLOBAL_START + 49) +#define MPFS_IRQ_I2C1_SUS (MPFS_IRQ_GLOBAL_START + 50) +#define MPFS_IRQ_MAC0_INT (MPFS_IRQ_GLOBAL_START + 51) +#define MPFS_IRQ_MAC0_QUEUE1 (MPFS_IRQ_GLOBAL_START + 52) +#define MPFS_IRQ_MAC0_QUEUE2 (MPFS_IRQ_GLOBAL_START + 53) +#define MPFS_IRQ_MAC0_QUEUE3 (MPFS_IRQ_GLOBAL_START + 54) +#define MPFS_IRQ_MAC0_EMAC (MPFS_IRQ_GLOBAL_START + 55) +#define MPFS_IRQ_MAC0_MMSL (MPFS_IRQ_GLOBAL_START + 56) +#define MPFS_IRQ_MAC1_INT (MPFS_IRQ_GLOBAL_START + 57) +#define MPFS_IRQ_MAC1_QUEUE1 (MPFS_IRQ_GLOBAL_START + 58) +#define MPFS_IRQ_MAC1_QUEUE2 (MPFS_IRQ_GLOBAL_START + 59) +#define MPFS_IRQ_MAC1_QUEUE3 (MPFS_IRQ_GLOBAL_START + 60) +#define MPFS_IRQ_MAC1_EMAC (MPFS_IRQ_GLOBAL_START + 61) +#define MPFS_IRQ_MAC1_MMSL (MPFS_IRQ_GLOBAL_START + 62) +#define MPFS_IRQ_DDRC_TRAIN (MPFS_IRQ_GLOBAL_START + 63) +#define MPFS_IRQ_SCB_INTERRUPT (MPFS_IRQ_GLOBAL_START + 64) +#define MPFS_IRQ_ECC_ERROR (MPFS_IRQ_GLOBAL_START + 65) +#define MPFS_IRQ_ECC_CORRECT (MPFS_IRQ_GLOBAL_START + 66) +#define MPFS_IRQ_RTC_WAKEUP (MPFS_IRQ_GLOBAL_START + 67) +#define MPFS_IRQ_RTC_MATCH (MPFS_IRQ_GLOBAL_START + 68) +#define MPFS_IRQ_TIMER1 (MPFS_IRQ_GLOBAL_START + 69) +#define MPFS_IRQ_TIMER2 (MPFS_IRQ_GLOBAL_START + 70) +#define MPFS_IRQ_ENVM (MPFS_IRQ_GLOBAL_START + 71) +#define MPFS_IRQ_QSPI (MPFS_IRQ_GLOBAL_START + 72) +#define MPFS_IRQ_USB_DMA (MPFS_IRQ_GLOBAL_START + 73) +#define MPFS_IRQ_USB_MC (MPFS_IRQ_GLOBAL_START + 74) +#define MPFS_IRQ_MMC_MAIN (MPFS_IRQ_GLOBAL_START + 75) +#define MPFS_IRQ_MMC_WAKEUP (MPFS_IRQ_GLOBAL_START + 76) +#define MPFS_IRQ_MMUART0 (MPFS_IRQ_GLOBAL_START + 77) +#define MPFS_IRQ_MMUART1 (MPFS_IRQ_GLOBAL_START + 78) +#define MPFS_IRQ_MMUART2 (MPFS_IRQ_GLOBAL_START + 79) +#define MPFS_IRQ_MMUART3 (MPFS_IRQ_GLOBAL_START + 80) +#define MPFS_IRQ_MMUART4 (MPFS_IRQ_GLOBAL_START + 81) +#define MPFS_IRQ_WDOG0_MRVP (MPFS_IRQ_GLOBAL_START + 87) +#define MPFS_IRQ_WDOG1_MRVP (MPFS_IRQ_GLOBAL_START + 88) +#define MPFS_IRQ_WDOG2_MRVP (MPFS_IRQ_GLOBAL_START + 89) +#define MPFS_IRQ_WDOG3_MRVP (MPFS_IRQ_GLOBAL_START + 90) +#define MPFS_IRQ_WDOG4_MRVP (MPFS_IRQ_GLOBAL_START + 91) +#define MPFS_IRQ_WDOG0_TOUT (MPFS_IRQ_GLOBAL_START + 92) +#define MPFS_IRQ_WDOG1_TOUT (MPFS_IRQ_GLOBAL_START + 93) +#define MPFS_IRQ_WDOG2_TOUT (MPFS_IRQ_GLOBAL_START + 94) +#define MPFS_IRQ_WDOG3_TOUT (MPFS_IRQ_GLOBAL_START + 95) +#define MPFS_IRQ_WDOG4_TOUT (MPFS_IRQ_GLOBAL_START + 96) +#define MPFS_IRQ_FABRIC_F2H_0 (MPFS_IRQ_GLOBAL_START + 105) +#define MPFS_IRQ_FABRIC_F2H_1 (MPFS_IRQ_GLOBAL_START + 106) +#define MPFS_IRQ_FABRIC_F2H_2 (MPFS_IRQ_GLOBAL_START + 107) +#define MPFS_IRQ_FABRIC_F2H_3 (MPFS_IRQ_GLOBAL_START + 108) +#define MPFS_IRQ_FABRIC_F2H_4 (MPFS_IRQ_GLOBAL_START + 109) +#define MPFS_IRQ_FABRIC_F2H_5 (MPFS_IRQ_GLOBAL_START + 110) +#define MPFS_IRQ_FABRIC_F2H_6 (MPFS_IRQ_GLOBAL_START + 111) +#define MPFS_IRQ_FABRIC_F2H_7 (MPFS_IRQ_GLOBAL_START + 112) +#define MPFS_IRQ_FABRIC_F2H_8 (MPFS_IRQ_GLOBAL_START + 113) +#define MPFS_IRQ_FABRIC_F2H_9 (MPFS_IRQ_GLOBAL_START + 114) +#define MPFS_IRQ_FABRIC_F2H_10 (MPFS_IRQ_GLOBAL_START + 115) +#define MPFS_IRQ_FABRIC_F2H_11 (MPFS_IRQ_GLOBAL_START + 116) +#define MPFS_IRQ_FABRIC_F2H_12 (MPFS_IRQ_GLOBAL_START + 117) +#define MPFS_IRQ_FABRIC_F2H_13 (MPFS_IRQ_GLOBAL_START + 118) +#define MPFS_IRQ_FABRIC_F2H_14 (MPFS_IRQ_GLOBAL_START + 119) +#define MPFS_IRQ_FABRIC_F2H_15 (MPFS_IRQ_GLOBAL_START + 120) +#define MPFS_IRQ_FABRIC_F2H_16 (MPFS_IRQ_GLOBAL_START + 121) +#define MPFS_IRQ_FABRIC_F2H_17 (MPFS_IRQ_GLOBAL_START + 122) +#define MPFS_IRQ_FABRIC_F2H_18 (MPFS_IRQ_GLOBAL_START + 123) +#define MPFS_IRQ_FABRIC_F2H_19 (MPFS_IRQ_GLOBAL_START + 124) +#define MPFS_IRQ_FABRIC_F2H_20 (MPFS_IRQ_GLOBAL_START + 125) +#define MPFS_IRQ_FABRIC_F2H_21 (MPFS_IRQ_GLOBAL_START + 126) +#define MPFS_IRQ_FABRIC_F2H_22 (MPFS_IRQ_GLOBAL_START + 127) +#define MPFS_IRQ_FABRIC_F2H_23 (MPFS_IRQ_GLOBAL_START + 128) +#define MPFS_IRQ_FABRIC_F2H_24 (MPFS_IRQ_GLOBAL_START + 129) +#define MPFS_IRQ_FABRIC_F2H_25 (MPFS_IRQ_GLOBAL_START + 130) +#define MPFS_IRQ_FABRIC_F2H_26 (MPFS_IRQ_GLOBAL_START + 131) +#define MPFS_IRQ_FABRIC_F2H_27 (MPFS_IRQ_GLOBAL_START + 132) +#define MPFS_IRQ_FABRIC_F2H_28 (MPFS_IRQ_GLOBAL_START + 133) +#define MPFS_IRQ_FABRIC_F2H_29 (MPFS_IRQ_GLOBAL_START + 134) +#define MPFS_IRQ_FABRIC_F2H_30 (MPFS_IRQ_GLOBAL_START + 135) +#define MPFS_IRQ_FABRIC_F2H_31 (MPFS_IRQ_GLOBAL_START + 136) +#define MPFS_IRQ_FABRIC_F2H_32 (MPFS_IRQ_GLOBAL_START + 137) +#define MPFS_IRQ_FABRIC_F2H_33 (MPFS_IRQ_GLOBAL_START + 138) +#define MPFS_IRQ_FABRIC_F2H_34 (MPFS_IRQ_GLOBAL_START + 139) +#define MPFS_IRQ_FABRIC_F2H_35 (MPFS_IRQ_GLOBAL_START + 140) +#define MPFS_IRQ_FABRIC_F2H_36 (MPFS_IRQ_GLOBAL_START + 141) +#define MPFS_IRQ_FABRIC_F2H_37 (MPFS_IRQ_GLOBAL_START + 142) +#define MPFS_IRQ_FABRIC_F2H_38 (MPFS_IRQ_GLOBAL_START + 143) +#define MPFS_IRQ_FABRIC_F2H_39 (MPFS_IRQ_GLOBAL_START + 144) +#define MPFS_IRQ_FABRIC_F2H_40 (MPFS_IRQ_GLOBAL_START + 145) +#define MPFS_IRQ_FABRIC_F2H_41 (MPFS_IRQ_GLOBAL_START + 146) +#define MPFS_IRQ_FABRIC_F2H_42 (MPFS_IRQ_GLOBAL_START + 147) +#define MPFS_IRQ_FABRIC_F2H_43 (MPFS_IRQ_GLOBAL_START + 148) +#define MPFS_IRQ_FABRIC_F2H_44 (MPFS_IRQ_GLOBAL_START + 149) +#define MPFS_IRQ_FABRIC_F2H_45 (MPFS_IRQ_GLOBAL_START + 150) +#define MPFS_IRQ_FABRIC_F2H_46 (MPFS_IRQ_GLOBAL_START + 151) +#define MPFS_IRQ_FABRIC_F2H_47 (MPFS_IRQ_GLOBAL_START + 152) +#define MPFS_IRQ_FABRIC_F2H_48 (MPFS_IRQ_GLOBAL_START + 153) +#define MPFS_IRQ_FABRIC_F2H_49 (MPFS_IRQ_GLOBAL_START + 154) +#define MPFS_IRQ_FABRIC_F2H_50 (MPFS_IRQ_GLOBAL_START + 155) +#define MPFS_IRQ_FABRIC_F2H_51 (MPFS_IRQ_GLOBAL_START + 156) +#define MPFS_IRQ_FABRIC_F2H_52 (MPFS_IRQ_GLOBAL_START + 157) +#define MPFS_IRQ_FABRIC_F2H_53 (MPFS_IRQ_GLOBAL_START + 158) +#define MPFS_IRQ_FABRIC_F2H_54 (MPFS_IRQ_GLOBAL_START + 159) +#define MPFS_IRQ_FABRIC_F2H_55 (MPFS_IRQ_GLOBAL_START + 160) +#define MPFS_IRQ_FABRIC_F2H_56 (MPFS_IRQ_GLOBAL_START + 161) +#define MPFS_IRQ_FABRIC_F2H_57 (MPFS_IRQ_GLOBAL_START + 162) +#define MPFS_IRQ_FABRIC_F2H_58 (MPFS_IRQ_GLOBAL_START + 163) +#define MPFS_IRQ_FABRIC_F2H_59 (MPFS_IRQ_GLOBAL_START + 164) +#define MPFS_IRQ_FABRIC_F2H_60 (MPFS_IRQ_GLOBAL_START + 165) +#define MPFS_IRQ_FABRIC_F2H_61 (MPFS_IRQ_GLOBAL_START + 166) +#define MPFS_IRQ_FABRIC_F2H_62 (MPFS_IRQ_GLOBAL_START + 167) +#define MPFS_IRQ_FABRIC_F2H_63 (MPFS_IRQ_GLOBAL_START + 168) +#define MPFS_IRQ_BUS_ERROR_UNIT_HART_0 (MPFS_IRQ_GLOBAL_START + 169) +#define MPFS_IRQ_BUS_ERROR_UNIT_HART_1 (MPFS_IRQ_GLOBAL_START + 170) +#define MPFS_IRQ_BUS_ERROR_UNIT_HART_2 (MPFS_IRQ_GLOBAL_START + 171) +#define MPFS_IRQ_BUS_ERROR_UNIT_HART_3 (MPFS_IRQ_GLOBAL_START + 172) +#define MPFS_IRQ_BUS_ERROR_UNIT_HART_4 (MPFS_IRQ_GLOBAL_START + 173) + +/* Total number of IRQs */ + +#define NR_IRQS (MPFS_IRQ_BUS_ERROR_UNIT_HART_4 + 1) + +#endif /* __ARCH_RISCV_INCLUDE_MPFS_IRQ_H */ diff --git a/arch/risc-v/include/rv32im/irq.h b/arch/risc-v/include/rv32im/irq.h index b1ed3afdc0d..62b39566636 100644 --- a/arch/risc-v/include/rv32im/irq.h +++ b/arch/risc-v/include/rv32im/irq.h @@ -114,7 +114,12 @@ #define REG_INT_CTX_NDX 32 -#define INT_XCPT_REGS 33 +#ifdef CONFIG_ARCH_RISCV_INTXCPT_EXTREGS + #define INT_XCPT_REGS (33 + CONFIG_ARCH_RISCV_INTXCPT_EXTREGS) +#else + #define INT_XCPT_REGS 33 +#endif + #define INT_XCPT_SIZE (4 * INT_XCPT_REGS) #ifdef CONFIG_ARCH_FPU diff --git a/arch/risc-v/include/rv32m1/chip.h b/arch/risc-v/include/rv32m1/chip.h new file mode 100644 index 00000000000..3e9e6291c65 --- /dev/null +++ b/arch/risc-v/include/rv32m1/chip.h @@ -0,0 +1,24 @@ +/**************************************************************************** + * arch/risc-v/include/rv32m1/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_RV32M1_CHIP_H +#define __ARCH_RISCV_INCLUDE_RV32M1_CHIP_H + +#endif /* __ARCH_RISCV_INCLUDE_RV32M1_CHIP_H */ diff --git a/arch/risc-v/include/rv32m1/irq.h b/arch/risc-v/include/rv32m1/irq.h new file mode 100644 index 00000000000..6a1a9976e6d --- /dev/null +++ b/arch/risc-v/include/rv32m1/irq.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/risc-v/include/rv32m1/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_RV32M1_IRQ_H +#define __ARCH_RISCV_INCLUDE_RV32M1_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifdef CONFIG_ARCH_CHIP_RV32M1_RI5CY +# include "rv32m1ri5cy_irq.h" +#elif defined(CONFIG_ARCH_CHIP_RV32M1_ZERORISCY) +# error "RV32M1 zeroriscy is not supported yet" +#else +# error "Unsupported RV32M1 cortex-m cores" +#endif + +#endif /* __ARCH_RISCV_INCLUDE_RV32M1_IRQ_H */ diff --git a/arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h b/arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h new file mode 100644 index 00000000000..eb556857fe2 --- /dev/null +++ b/arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_RV32M1_RV32M1RI5CY_IRQ_H +#define __ARCH_RISCV_INCLUDE_RV32M1_RV32M1RI5CY_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RV32M1 RI5CY CPU throws four exceptions: + * -Reset, + * -Illegal Instruction, + * -ECALL Instruct Excecuted, + * -Load Store Unit Error. MCAUSE must be checked to + * figure out what kind of Error. + */ + +/* RISC-V standard exceptions alias with prefix RV32M1 **********************/ + +#define RV32M1_IRQ_ADDE_MISALIGNED MCAUSE_ADDE_MISALIGNED +#define RV32M1_IRQ_INST_ACCESS_FAULT MCAUSE_INST_ACCESS_FAULT +#define RV32M1_IRQ_ILLEGAL_INST MCAUSE_ILLEGAL_INST +#define RV32M1_IRQ_LOAD_MISALIGNED MCAUSE_LOAD_MISALIGNED +#define RV32M1_IRQ_LOAD_ACCESS_FAULT MCAUSE_LOAD_ACCESS_FAULT +#define RV32M1_IRQ_STORE_MISALIGNED MCAUSE_STORE_MISALIGNED +#define RV32M1_IRQ_STORE_ACCESS_FAULT MCAUSE_STORE_ACCESS_FAULT +#define RV32M1_IRQ_ECALL_U MCAUSE_ECALL_U +#define RV32M1_IRQ_ECALL_M MCAUSE_ECALL_M + +/* RV32M1 RI5CY Interrupts **************************************************/ + +/* IRQ 16- : (async event:interrupt=1) */ + +#define RV32M1_IRQ_ASYNC (16) +#define RV32M1_IRQ_MEXT (RV32M1_IRQ_ASYNC + 0) /* Machine External Int */ + +/* Machine Global External Interrupt */ + +#define RV32M1_IRQ_DMA0G0 (RV32M1_IRQ_MEXT + 0) /* DMA0 Group0, channel 0/4/8/12 */ +#define RV32M1_IRQ_DMA0G1 (RV32M1_IRQ_MEXT + 1) /* DMA0 Group1, channel 1/5/9/13 */ +#define RV32M1_IRQ_DMA0G2 (RV32M1_IRQ_MEXT + 2) /* DMA0 Group2, channel 2/6/10/14 */ +#define RV32M1_IRQ_DMA0G3 (RV32M1_IRQ_MEXT + 3) /* DMA0 Group3, channel 3/7/11/15 */ +#define RV32M1_IRQ_DMA0EER (RV32M1_IRQ_MEXT + 4) /* DAM0 Error */ +#define RV32M1_IRQ_CMC0 (RV32M1_IRQ_MEXT + 5) /* Core Mode Controller 0 */ +#define RV32M1_IRQ_MUA (RV32M1_IRQ_MEXT + 6) /* MU Side A */ +#define RV32M1_IRQ_USB0 (RV32M1_IRQ_MEXT + 7) /* USB0 */ +#define RV32M1_IRQ_USDHC0 (RV32M1_IRQ_MEXT + 8) /* SDHC0 */ +#define RV32M1_IRQ_I2S0 (RV32M1_IRQ_MEXT + 9) /* I2S0 */ +#define RV32M1_IRQ_FLEXIO0 (RV32M1_IRQ_MEXT + 10) /* FlexIO0 */ +#define RV32M1_IRQ_EMVSIM0 (RV32M1_IRQ_MEXT + 11) /* EMVSIM0 */ +#define RV32M1_IRQ_LPIT0 (RV32M1_IRQ_MEXT + 12) /* LPIT0 */ +#define RV32M1_IRQ_LPSPI0 (RV32M1_IRQ_MEXT + 13) /* LPSPI0 */ +#define RV32M1_IRQ_LPSPI1 (RV32M1_IRQ_MEXT + 14) /* LPSPI1 */ +#define RV32M1_IRQ_LPI2C0 (RV32M1_IRQ_MEXT + 15) /* LPI2C0 */ +#define RV32M1_IRQ_LPI2C1 (RV32M1_IRQ_MEXT + 16) /* LPI2C1 */ +#define RV32M1_IRQ_LPUART0 (RV32M1_IRQ_MEXT + 17) /* LPUART0 */ +#define RV32M1_IRQ_PORTA (RV32M1_IRQ_MEXT + 18) /* PORTA */ +#define RV32M1_IRQ_TPM0 (RV32M1_IRQ_MEXT + 19) /* TPM0 */ +#define RV32M1_IRQ_ADC0 (RV32M1_IRQ_MEXT + 20) /* ADC0 */ +#define RV32M1_IRQ_LPDAC0 (RV32M1_IRQ_MEXT + 21) /* LPDAC0 */ +#define RV32M1_IRQ_LPCMP0 (RV32M1_IRQ_MEXT + 22) /* LPCMP0 */ +#define RV32M1_IRQ_RTC (RV32M1_IRQ_MEXT + 23) /* RTC */ +#define RV32M1_IRQ_INTMUX0 (RV32M1_IRQ_MEXT + 24) /* INTMUX0 */ +#define RV32M1_IRQ_INTMUX1 (RV32M1_IRQ_MEXT + 25) /* INTMUX1 */ +#define RV32M1_IRQ_INTMUX2 (RV32M1_IRQ_MEXT + 26) /* INTMUX2 */ +#define RV32M1_IRQ_INTMUX3 (RV32M1_IRQ_MEXT + 27) /* INTMUX3 */ +#define RV32M1_IRQ_INTMUX4 (RV32M1_IRQ_MEXT + 28) /* INTMUX4 */ +#define RV32M1_IRQ_INTMUX5 (RV32M1_IRQ_MEXT + 29) /* INTMUX5 */ +#define RV32M1_IRQ_INTMUX6 (RV32M1_IRQ_MEXT + 30) /* INTMUX6 */ +#define RV32M1_IRQ_INTMUX7 (RV32M1_IRQ_MEXT + 31) /* INTMUX7 */ +#define RV32M1_IRQ_EWM (RV32M1_IRQ_MEXT + 32) /* EWM */ +# define RV32M1_IRQ_INTMUX RV32M1_IRQ_EWM +#define RV32M1_IRQ_FTFE_CC (RV32M1_IRQ_MEXT + 33) /* FTFE Command Complete */ +#define RV32M1_IRQ_FTFE_RC (RV32M1_IRQ_MEXT + 34) /* FTFE Read Collision */ +#define RV32M1_IRQ_LLWU0 (RV32M1_IRQ_MEXT + 35) /* Low leakage wake up 0 */ +#define RV32M1_IRQ_SPM (RV32M1_IRQ_MEXT + 36) /* SPM */ +#define RV32M1_IRQ_WDOG0 (RV32M1_IRQ_MEXT + 37) /* WDOG0 */ +#define RV32M1_IRQ_SCG (RV32M1_IRQ_MEXT + 38) /* SCG */ +#define RV32M1_IRQ_LPTMR0 (RV32M1_IRQ_MEXT + 39) /* LPTMR0 */ +#define RV32M1_IRQ_LPTMR1 (RV32M1_IRQ_MEXT + 40) /* LPTMR1 */ +#define RV32M1_IRQ_TPM1 (RV32M1_IRQ_MEXT + 41) /* TPM1 */ +#define RV32M1_IRQ_TMP2 (RV32M1_IRQ_MEXT + 42) /* TPM2 */ +#define RV32M1_IRQ_LPI2C2 (RV32M1_IRQ_MEXT + 43) /* LPI2C2 */ +#define RV32M1_IRQ_SPI2 (RV32M1_IRQ_MEXT + 44) /* SPI2 */ +#define RV32M1_IRQ_LPUART1 (RV32M1_IRQ_MEXT + 45) /* LPUART1 */ +#define RV32M1_IRQ_LPUART2 (RV32M1_IRQ_MEXT + 46) /* LPUART2 */ +#define RV32M1_IRQ_PORTB (RV32M1_IRQ_MEXT + 47) /* PORTB */ +#define RV32M1_IRQ_PORTC (RV32M1_IRQ_MEXT + 48) /* PORTC */ +#define RV32M1_IRQ_PORTD (RV32M1_IRQ_MEXT + 49) /* PORTD */ +#define RV32M1_IRQ_CAU3_TC (RV32M1_IRQ_MEXT + 50) /* CAU3 Task Complete */ +#define RV32M1_IRQ_CAU3_SV (RV32M1_IRQ_MEXT + 51) /* CAU3 Security Violation */ +#define RV32M1_IRQ_TRNG (RV32M1_IRQ_MEXT + 52) /* TRNG */ +#define RV32M1_IRQ_LPIT1 (RV32M1_IRQ_MEXT + 53) /* LPIT1 */ +#define RV32M1_IRQ_LPTMR2 (RV32M1_IRQ_MEXT + 54) /* LPTMR2 */ +#define RV32M1_IRQ_TPM3 (RV32M1_IRQ_MEXT + 55) /* TPM3 */ +#define RV32M1_IRQ_LPI2C3 (RV32M1_IRQ_MEXT + 56) /* LPI2C3 */ +#define RV32M1_IRQ_LPSPI3 (RV32M1_IRQ_MEXT + 57) /* LPSPI3 */ +#define RV32M1_IRQ_LPUART3 (RV32M1_IRQ_MEXT + 58) /* LPUART3 */ +#define RV32M1_IRQ_PORTE (RV32M1_IRQ_MEXT + 59) /* PORTE */ +#define RV32M1_IRQ_LPCMP1 (RV32M1_IRQ_MEXT + 60) /* LPCMP1 */ +#define RV32M1_IRQ_RF0_0 (RV32M1_IRQ_MEXT + 61) /* RF0 Interrupt 0 */ +#define RV32M1_IRQ_RF0_1 (RV32M1_IRQ_MEXT + 62) /* RF0 Interrupt 1 */ + +/* Total number of IRQs */ + +#define NR_IRQS (RV32M1_IRQ_RF0_1 + 1) + +#endif /* __ARCH_RISCV_INCLUDE_RV32M1_RV32M1RI5CY_IRQ_H */ diff --git a/arch/risc-v/include/rv64gc/irq.h b/arch/risc-v/include/rv64gc/irq.h index c9e51ed06ac..2852b0cdb51 100644 --- a/arch/risc-v/include/rv64gc/irq.h +++ b/arch/risc-v/include/rv64gc/irq.h @@ -115,7 +115,11 @@ #define REG_INT_CTX_NDX 32 -#define INT_XCPT_REGS 33 +#ifdef CONFIG_ARCH_RISCV_INTXCPT_EXTREGS + #define INT_XCPT_REGS (33 + CONFIG_ARCH_RISCV_INTXCPT_EXTREGS) +#else + #define INT_XCPT_REGS 33 +#endif #define INT_XCPT_SIZE (8 * INT_XCPT_REGS) diff --git a/arch/risc-v/src/bl602/Kconfig b/arch/risc-v/src/bl602/Kconfig index b68dab4070f..e813dbf55a6 100644 --- a/arch/risc-v/src/bl602/Kconfig +++ b/arch/risc-v/src/bl602/Kconfig @@ -45,6 +45,14 @@ config BL602_I2C0 config BL602_SPI0 bool "SPI0" +config BL602_RTC + bool "RTC" + +config BL602_RTC_USE_XTAL32K + bool "Select enable RTC XTAL32K clock source, otherwise use internal RC32K" + default n + depends on BL602_RTC + config BL602_SPIFLASH bool "SPI Flash" default n @@ -84,11 +92,14 @@ config BL602_WIRELESS_CONTRY_CODE depends on BL602_WIRELESS default "CN" +config BL602_NET_MULTI_INTERFACE + bool "STA and AP as independent interfaces" + depends on BL602_WIRELESS + default n + config BL602_BLE_CONTROLLER bool "ble controller support" default n - depends on PSEUDOTERM - depends on PSEUDOTERM_SUSV1 depends on !DISABLE_MQUEUE depends on SCHED_HPWORK depends on BL602_WIRELESS diff --git a/arch/risc-v/src/bl602/Make.defs b/arch/risc-v/src/bl602/Make.defs index cddc3a8c250..a34d1830ed7 100644 --- a/arch/risc-v/src/bl602/Make.defs +++ b/arch/risc-v/src/bl602/Make.defs @@ -50,13 +50,13 @@ endif CHIP_CSRCS = bl602_allocateheap.c CHIP_CSRCS += bl602_idle.c bl602_irq.c bl602_irq_dispatch.c CHIP_CSRCS += bl602_serial.c bl602_lowputc.c bl602_tim.c -CHIP_CSRCS += bl602_start.c bl602_timerisr.c +CHIP_CSRCS += bl602_start.c bl602_timerisr.c bl602_efuse.c -ifeq ($(CONFIG_I2C),y) +ifeq ($(CONFIG_I2C),y) CHIP_CSRCS += bl602_i2c.c endif -ifeq ($(CONFIG_SPI),y) +ifeq ($(CONFIG_SPI),y) CHIP_CSRCS += bl602_spi.c endif @@ -75,15 +75,17 @@ endif ifeq ($(CONFIG_BL602_SPIFLASH),y) CHIP_CSRCS += bl602_flash.c bl602_spiflash.c endif +ifeq ($(CONFIG_RTC_DRIVER),y) +CHIP_CSRCS += bl602_rtc.c bl602_rtc_lowerhalf.c +endif CHIP_CSRCS += bl602_glb.c bl602_gpio.c bl602_hbn.c bl602_systemreset.c ifeq ($(CONFIG_BL602_WIRELESS),y) WIRELESS_DRV_UNPACK = bl_blob -WIRELESS_DRV_VERSION = v1.6.19 -WIRELESS_DRV_ID = main -WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip -WIRELESS_DRV_URL = https://github.com/bouffalolab/bl_blob/archive +WIRELESS_DRV_VERSION = 1.7.0 +WIRELESS_DRV_ZIP = v$(WIRELESS_DRV_VERSION).zip +WIRELESS_DRV_URL = https://github.com/bouffalolab/bl_blob/archive/refs/heads $(WIRELESS_DRV_ZIP): $(Q) echo "Downloading: BL602 Wireless Drivers" @@ -93,7 +95,7 @@ chip/$(WIRELESS_DRV_UNPACK): $(WIRELESS_DRV_ZIP) $(Q) echo "Unpacking: BL602 Wireless Drivers" $(Q) mkdir -p chip/$(WIRELESS_DRV_UNPACK) $(Q) unzip -oqq chip/$(WIRELESS_DRV_ZIP) -d chip/ - $(Q) mv chip/$(WIRELESS_DRV_UNPACK)-$(WIRELESS_DRV_ID)/* chip/$(WIRELESS_DRV_UNPACK) + $(Q) mv chip/$(WIRELESS_DRV_UNPACK)-$(WIRELESS_DRV_VERSION)/* chip/$(WIRELESS_DRV_UNPACK) $(Q) touch chip/$(WIRELESS_DRV_UNPACK) context:: chip/$(WIRELESS_DRV_UNPACK) @@ -102,10 +104,10 @@ clean_context:: $(call DELFILE, chip/$(WIRELESS_DRV_ZIP)) $(call DELDIR, chip/$(WIRELESS_DRV_UNPACK)) -INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(WIRELESS_DRV_UNPACK)$(DELIM)includes$(DELIM)$(WIRELESS_DRV_VERSION)$(DELIM)BL602$(DELIM)nuttx) +INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(WIRELESS_DRV_UNPACK)$(DELIM)includes$(DELIM)BL602$(DELIM)nuttx) CHIP_CSRCS += bl602_netdev.c -EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(WIRELESS_DRV_UNPACK)$(DELIM)libs$(DELIM)$(WIRELESS_DRV_VERSION)$(DELIM)BL602$(DELIM)nuttx +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(WIRELESS_DRV_UNPACK)$(DELIM)libs$(DELIM)BL602$(DELIM)nuttx EXTRA_LIBS += -lbl602_wifi -lblecontroller # Due to some Wi-Fi related libraries, the option is need to avoid linking too much diff --git a/arch/risc-v/src/bl602/bl602_efuse.c b/arch/risc-v/src/bl602/bl602_efuse.c new file mode 100644 index 00000000000..2afcb96919e --- /dev/null +++ b/arch/risc-v/src/bl602/bl602_efuse.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/risc-v/src/bl602/bl602_efuse.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "riscv_arch.h" + +#include "hardware/bl602_ef.h" +#include "bl602_romapi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define bl602_romapi_efuse_ctrl_load_r0 \ + ((void (*)(void))BL602_ROMAPI_EFUSE_CTRL_LOAD_R0) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline uint32_t count_zero_bits_in_byte(uint8_t val) +{ + uint32_t cnt = 0; + uint32_t i = 0; + for (i = 0; i < 8; i++) + { + if ((val & (1 << i)) == 0) + { + cnt += 1; + } + } + + return cnt; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bl602_efuse_read_mac_address + * + * Description: + * Read MAC address from efuse. + * + * Input Parameters: + * mac: the buffer to hold mac address + * + * Returned Value: + * 0: OK + * ENODATA: Failed + * + ****************************************************************************/ + +int bl602_efuse_read_mac_address(uint8_t mac[6]) +{ + DEBUGASSERT(mac != NULL); + + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmp_val; + uint32_t i = 0; + uint32_t cnt = 0; + + /* Trigger read data from efuse */ + + bl602_romapi_efuse_ctrl_load_r0(); + + tmp_val = getreg32(BL602_EF_WIFI_MAC_LOW); + maclow[0] = tmp_val & 0xff; + maclow[1] = (tmp_val >> 8) & 0xff; + maclow[2] = (tmp_val >> 16) & 0xff; + maclow[3] = (tmp_val >> 24) & 0xff; + + tmp_val = getreg32(BL602_EF_WIFI_MAC_HIGH); + machigh[0] = tmp_val & 0xff; + machigh[1] = (tmp_val >> 8) & 0xff; + + /* Check parity */ + + for (i = 0; i < 6; i++) + { + cnt += count_zero_bits_in_byte(mac[i]); + } + + if ((cnt & 0x3f) == ((tmp_val >> 16) & 0x3f)) + { + /* Change to network order */ + + for (i = 0; i < 3; i++) + { + tmp_val = mac[i]; + mac[i] = mac[5 - i]; + mac[5 - i] = tmp_val; + } + + return 0; + } + else + { + return -ENODATA; + } +} + diff --git a/arch/risc-v/src/bl602/bl602_efuse.h b/arch/risc-v/src/bl602/bl602_efuse.h new file mode 100644 index 00000000000..fa1266c4afa --- /dev/null +++ b/arch/risc-v/src/bl602/bl602_efuse.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/risc-v/src/bl602/bl602_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_BL602_BL602_EFUSE_H +#define __ARCH_RISCV_SRC_BL602_BL602_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: bl602_efuse_read_mac_address + * + * Description: + * Read MAC address from efuse. + * + * Input Parameters: + * mac: the buffer to hold mac address + * + * Returned Value: + * 0: OK + * ENODATA: Failed + * + ****************************************************************************/ + +int bl602_efuse_read_mac_address(uint8_t mac[6]); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_BL602_BL602_EFUSE_H */ diff --git a/arch/risc-v/src/bl602/bl602_entry.S b/arch/risc-v/src/bl602/bl602_entry.S index a7e94cbfc4b..283103648b0 100644 --- a/arch/risc-v/src/bl602/bl602_entry.S +++ b/arch/risc-v/src/bl602/bl602_entry.S @@ -51,16 +51,6 @@ bl602_start: add sp, sp, t0 andi sp, sp, ~0xF - la t0, g_idle_stack - li t1, CONFIG_IDLETHREAD_STACKSIZE - li t2, 0xdeadbeef -color_idle_stack: - addi t1, t1, -4 - add t3, t1, t0 - sw t2, 0(t3) - bnez t1, color_idle_stack - - #ifndef RUN_IN_RAM /* Load boot2 partition address */ diff --git a/arch/risc-v/src/bl602/bl602_flash.c b/arch/risc-v/src/bl602/bl602_flash.c index 91a8c0e2547..9a124d1410f 100644 --- a/arch/risc-v/src/bl602/bl602_flash.c +++ b/arch/risc-v/src/bl602/bl602_flash.c @@ -29,37 +29,37 @@ #include #include +#include "bl602_romapi.h" #ifdef CONFIG_BL602_SPIFLASH +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define bl602_romapi_sflash_erase \ + ((void (*)(uint8_t *, uint32_t, int))BL602_ROMAPI_SFLASH_EREASE_NEEDLOCK) + +#define bl602_romapi_sflash_write \ + ((void (*)(uint8_t *, uint32_t, const uint8_t *, int)) \ + BL602_ROMAPI_SFLASH_WRITE_NEEDLOCK) + +#define bl602_romapi_sflash_read \ + ((void (*)( \ + uint8_t *, uint32_t, uint8_t *, int))BL602_ROMAPI_SFLASH_READ_NEEDLOCK) + /**************************************************************************** * Private Data ****************************************************************************/ +static struct bl602_romflash_cfg_desc g_bl602_romflash_cfg; + struct bl602_romflash_cfg_desc { uint32_t magic; uint8_t cfg[84]; }; -#define ROMAPI_BASE (0x21010800) -#define ROMAPI_SFLASH_EREASE_NEEDLOCK (ROMAPI_BASE + 163 * 4) -#define ROMAPI_SFLASH_WRITE_NEEDLOCK (ROMAPI_BASE + 164 * 4) -#define ROMAPI_SFLASH_READ_NEEDLOCK (ROMAPI_BASE + 165 * 4) -#define ROMAPI_SFLASH_GET_JEDECID_NOLOCK (ROMAPI_BASE + 166 * 4) -#define ROMAPI_SFLASH_READ_WITHLOCK (ROMAPI_BASE + 170 * 4) -#define ROMAPI_SFLASH_WRITE_WITHLOCK (ROMAPI_BASE + 171 * 4) -#define ROMAPI_SFLASH_EREASE_WITHLOCK (ROMAPI_BASE + 172 * 4) - -static struct bl602_romflash_cfg_desc g_bl602_romflash_cfg; - -typedef void (*bl602_romdrv_erase_fn) (uint8_t *cfg, - uint32_t addr, int len); -typedef void (*bl602_romdrv_write_fn) (uint8_t *cfg, - uint32_t addr, const uint8_t *dst, int len); -typedef void (*bl602_romdrv_read_fn) (uint8_t *cfg, - uint32_t addr, uint8_t *dst, int len); - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -71,8 +71,7 @@ int bl602_flash_erase(uint32_t addr, int len) finfo("addr = %08lx, len = %d\n", addr, len); flags = up_irq_save(); - ((bl602_romdrv_erase_fn)(*((uint32_t *)(ROMAPI_SFLASH_EREASE_NEEDLOCK)))) - (g_bl602_romflash_cfg.cfg, addr, addr + len - 1); + bl602_romapi_sflash_erase(g_bl602_romflash_cfg.cfg, addr, addr + len - 1); up_irq_restore(flags); return 0; @@ -85,8 +84,7 @@ int bl602_flash_write(uint32_t addr, const uint8_t *src, int len) finfo("addr = %08lx, len = %d\n", addr, len); flags = up_irq_save(); - ((bl602_romdrv_write_fn)(*((uint32_t *)(ROMAPI_SFLASH_WRITE_NEEDLOCK)))) - (g_bl602_romflash_cfg.cfg, addr, src, len); + bl602_romapi_sflash_write(g_bl602_romflash_cfg.cfg, addr, src, len); up_irq_restore(flags); return 0; @@ -99,8 +97,7 @@ int bl602_flash_read(uint32_t addr, uint8_t *dst, int len) finfo("addr = %08lx, len = %d\n", addr, len); flags = up_irq_save(); - ((bl602_romdrv_read_fn)(*((uint32_t *)(ROMAPI_SFLASH_READ_NEEDLOCK)))) - (g_bl602_romflash_cfg.cfg, addr, dst, len); + bl602_romapi_sflash_read(g_bl602_romflash_cfg.cfg, addr, dst, len); up_irq_restore(flags); return 0; diff --git a/arch/risc-v/src/bl602/bl602_hbn.c b/arch/risc-v/src/bl602/bl602_hbn.c index 10726adf78c..75738716909 100644 --- a/arch/risc-v/src/bl602/bl602_hbn.c +++ b/arch/risc-v/src/bl602/bl602_hbn.c @@ -22,9 +22,85 @@ * Included Files ****************************************************************************/ +#include "nuttx/arch.h" #include "hardware/bl602_hbn.h" +#include "bl602_hbn.h" +#include "bl602_rtc.h" #include "riscv_arch.h" +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct bl602_hbn_info_s +{ + bl602_hbn_cb_t out0_callback[3]; + void *out0_arg[3]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct bl602_hbn_info_s g_bl602_hbn_info; + +/**************************************************************************** + * Name: bl602_hbn_irq + ****************************************************************************/ + +static int bl602_hbn_irq(int irq, void *context, void *p_arg) +{ + bl602_hbn_cb_t isr_cb; + void *arg; + + /* GPIO7 GPIO8 and RTC */ + + if (bl602_hbn_get_int_state(BL602_HBN_INT_GPIO7)) + { + /* gpio7 sync/async mode */ + + bl602_hbn_clear_irq(BL602_HBN_INT_GPIO7); + + isr_cb = g_bl602_hbn_info.out0_callback[BL602_HBN_OUT0_INT_GPIO7]; + arg = g_bl602_hbn_info.out0_arg[BL602_HBN_OUT0_INT_GPIO7]; + + if (isr_cb) + { + isr_cb(arg); + } + } + + if (bl602_hbn_get_int_state(BL602_HBN_INT_GPIO8)) + { + /* gpio8 sync/async mode */ + + bl602_hbn_clear_irq(BL602_HBN_INT_GPIO8); + + isr_cb = g_bl602_hbn_info.out0_callback[BL602_HBN_OUT0_INT_GPIO8]; + arg = g_bl602_hbn_info.out0_arg[BL602_HBN_OUT0_INT_GPIO8]; + + if (isr_cb) + { + isr_cb(arg); + } + } + + if (bl602_hbn_get_int_state(BL602_HBN_INT_RTC)) + { + bl602_hbn_clear_irq(BL602_HBN_INT_RTC); + bl602_hbn_clear_rtc_int(); + + isr_cb = g_bl602_hbn_info.out0_callback[BL602_HBN_OUT0_INT_RTC]; + arg = g_bl602_hbn_info.out0_arg[BL602_HBN_OUT0_INT_RTC]; + + if (isr_cb) + { + isr_cb(arg); + } + } + return OK; +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -64,3 +140,160 @@ void bl602_aon_pad_iesmt_cfg(uint8_t pad_cfg) modifyreg32(BL602_HBN_IRQ_MODE, HBN_IRQ_MODE_REG_AON_PAD_IE_SMT, pad_cfg << 8); } + +/**************************************************************************** + * Name: bl602_hbn_get_int_state + * + * Description: + * HBN get interrupt status. + * + * Input Parameters: + * irq_type: HBN interrupt type + * + * Returned Value: + * true or false + * + ****************************************************************************/ + +bool bl602_hbn_get_int_state(uint8_t irq_type) +{ + uint32_t tmp_val; + + /* Check the parameters */ + + tmp_val = getreg32(BL602_HBN_IRQ_STAT); + + if (tmp_val & (1 << irq_type)) + { + return true; + } + + return false; +} + +/**************************************************************************** + * Name: bl602_hbn_clear_irq + * + * Description: + * HBN clear interrupt status. + * + * Input Parameters: + * hbn_int_type: HBN interrupt type + * + * Returned Value: + * None + * + ****************************************************************************/ + +void bl602_hbn_clear_irq(uint8_t hbn_int_type) +{ + modifyreg32(BL602_HBN_IRQ_CLR, 0, 1 << hbn_int_type); + modifyreg32(BL602_HBN_IRQ_CLR, 1 << hbn_int_type, 0); +} + +/**************************************************************************** + * Name: bl602_hbn_out0_int_register + * + * Description: + * HBN out0 interrupt cllback register. + * + * Input Parameters: + * irq_type: HBN interrupt type + * isr_cb: callback + * arg: callback arg + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +int bl602_hbn_out0_int_register(uint8_t irq_type, bl602_hbn_cb_t isr_cb, + void *arg) +{ + irqstate_t flags; + + if (irq_type > 2) + { + return -EINVAL; + } + + flags = enter_critical_section(); + g_bl602_hbn_info.out0_callback[irq_type] = isr_cb; + g_bl602_hbn_info.out0_arg[irq_type] = arg; + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: bl602_hbn_out0_int_unregister + * + * Description: + * HBN out0 interrupt cllback unregister. + * + * Input Parameters: + * irq_type: HBN interrupt type + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +int bl602_hbn_out0_int_unregister(uint8_t irq_type) +{ + irqstate_t flags; + + if (irq_type > 2) + { + return -EINVAL; + } + + flags = enter_critical_section(); + g_bl602_hbn_info.out0_callback[irq_type] = NULL; + g_bl602_hbn_info.out0_arg[irq_type] = NULL; + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: bl602_hbn_out0_int_enable + * + * Description: + * HBN out0 interrupt enable. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_out0_int_enable(void) +{ + irq_attach(BL602_IRQ_HBN_OUT0, bl602_hbn_irq, NULL); + up_enable_irq(BL602_IRQ_HBN_OUT0); +} + +/**************************************************************************** + * Name: bl602_hbn_out0_int_disable + * + * Description: + * HBN out0 interrupt disable. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_out0_int_disable(void) +{ + irq_detach(BL602_IRQ_HBN_OUT0); + up_disable_irq(BL602_IRQ_HBN_OUT0); +} diff --git a/arch/risc-v/src/bl602/bl602_hbn.h b/arch/risc-v/src/bl602/bl602_hbn.h index b6808e10109..d09248cb253 100644 --- a/arch/risc-v/src/bl602/bl602_hbn.h +++ b/arch/risc-v/src/bl602/bl602_hbn.h @@ -26,7 +26,11 @@ ****************************************************************************/ #include +#include +#include +#include +#include #include /**************************************************************************** @@ -44,6 +48,24 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BL602_HBN_OUT0_INT_GPIO7 (0) /* HBN out 0 interrupt type: GPIO7 */ +#define BL602_HBN_OUT0_INT_GPIO8 (1) /* HBN out 0 interrupt type: GPIO8 */ +#define BL602_HBN_OUT0_INT_RTC (2) /* HBN out 0 interrupt type: RTC */ + +#define BL602_HBN_INT_GPIO7 (0) /* HBN interrupt type: GPIO7 */ +#define BL602_HBN_INT_GPIO8 (1) /* HBN interrupt type: GPIO8 */ +#define BL602_HBN_INT_RTC (16) /* HBN interrupt type: RTC */ +#define BL602_HBN_INT_PIR (17) /* HBN interrupt type: PIR */ +#define BL602_HBN_INT_BOR (18) /* HBN interrupt type: BOR */ +#define BL602_HBN_INT_ACOMP0 (20) /* HBN interrupt type: ACOMP0 */ +#define BL602_HBN_INT_ACOMP1 (22) /* HBN interrupt type: ACOMP1 */ + +typedef CODE int (*bl602_hbn_cb_t)(FAR void *arg); + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -68,6 +90,107 @@ extern "C" void bl602_set_uart_clk_sel(int clk_sel); +/**************************************************************************** + * Name: bl602_hbn_get_int_state + * + * Description: + * HBN get interrupt status. + * + * Input Parameters: + * irq_type: HBN interrupt type + * + * Returned Value: + * true or false + * + ****************************************************************************/ + +bool bl602_hbn_get_int_state(uint8_t irq_type); + +/**************************************************************************** + * Name: bl602_hbn_clear_irq + * + * Description: + * HBN clear interrupt status. + * + * Input Parameters: + * hbn_int_type: HBN interrupt type + * + * Returned Value: + * None + * + ****************************************************************************/ + +void bl602_hbn_clear_irq(uint8_t hbn_int_type); + +/**************************************************************************** + * Name: bl602_hbn_out0_int_register + * + * Description: + * HBN out0 interrupt cllback register. + * + * Input Parameters: + * irq_type: HBN interrupt type + * isr_cb: callback + * arg: callback arg + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +int bl602_hbn_out0_int_register(uint8_t irq_type, bl602_hbn_cb_t isr_cb, + void *arg); + +/**************************************************************************** + * Name: bl602_hbn_out0_int_unregister + * + * Description: + * HBN out0 interrupt cllback unregister. + * + * Input Parameters: + * irq_type: HBN interrupt type + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +int bl602_hbn_out0_int_unregister(uint8_t irq_type); + +/**************************************************************************** + * Name: bl602_hbn_out0_int_enable + * + * Description: + * HBN out0 interrupt enable. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_out0_int_enable(void); + +/**************************************************************************** + * Name: bl602_hbn_out0_int_disable + * + * Description: + * HBN out0 interrupt disable. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_out0_int_disable(void); + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/risc-v/src/bl602/bl602_head.S b/arch/risc-v/src/bl602/bl602_head.S index a1e870e36ed..2439e13f3e8 100644 --- a/arch/risc-v/src/bl602/bl602_head.S +++ b/arch/risc-v/src/bl602/bl602_head.S @@ -85,7 +85,7 @@ exception_common: mv a1, sp /* context = sp */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 /* Switch to interrupt stack */ lui sp, %hi(g_intstacktop) diff --git a/arch/risc-v/src/bl602/bl602_i2c.c b/arch/risc-v/src/bl602/bl602_i2c.c index efc817e467a..e0ea59b338e 100644 --- a/arch/risc-v/src/bl602/bl602_i2c.c +++ b/arch/risc-v/src/bl602/bl602_i2c.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include #include diff --git a/arch/risc-v/src/bl602/bl602_i2c.h b/arch/risc-v/src/bl602/bl602_i2c.h index a2ba836bc8c..07a9297c4fa 100644 --- a/arch/risc-v/src/bl602/bl602_i2c.h +++ b/arch/risc-v/src/bl602/bl602_i2c.h @@ -89,4 +89,4 @@ int bl602_i2cbus_uninitialize(FAR struct i2c_master_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_BL602_BL602_HBN_H */ +#endif /* __ARCH_RISCV_SRC_BL602_BL602_I2C_H */ diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c index 4686bd828b3..f59391c3016 100644 --- a/arch/risc-v/src/bl602/bl602_irq.c +++ b/arch/risc-v/src/bl602/bl602_irq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -78,10 +79,10 @@ void up_irqinitialize(void) up_irq_save(); -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 /* Colorize the interrupt stack for debug purposes */ - size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); riscv_stack_color((FAR void *)&g_intstackalloc, intstack_size); #endif @@ -202,41 +203,6 @@ void riscv_ack_irq(int irq) { } -/**************************************************************************** - * Name: up_irq_save - * - * Description: - * Return the current interrupt state and disable interrupts - * - ****************************************************************************/ - -irqstate_t up_irq_save(void) -{ - uint32_t oldstat; - - /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ - - asm volatile("csrrc %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE)); - return oldstat; -} - -/**************************************************************************** - * Name: up_irq_restore - * - * Description: - * Restore previous IRQ mask state - * - ****************************************************************************/ - -void up_irq_restore(irqstate_t flags) -{ - /* Write flags to mstatus */ - - asm volatile("csrw mstatus, %0" - : /* no output */ - : "r"(flags)); -} - /**************************************************************************** * Name: up_irq_enable * diff --git a/arch/risc-v/src/bl602/bl602_netdev.c b/arch/risc-v/src/bl602/bl602_netdev.c index 67363132b21..9e1522bb094 100644 --- a/arch/risc-v/src/bl602/bl602_netdev.c +++ b/arch/risc-v/src/bl602/bl602_netdev.c @@ -62,6 +62,7 @@ #include "wifi_manager/include/wifi_mgmr_ext.h" #include "wifi_driver/os_hal.h" #include "bl602_netdev.h" +#include "bl602_efuse.h" #ifdef CONFIG_BL602_WIRELESS @@ -90,12 +91,14 @@ #define ETHWORK HPWORK -/* CONFIG_BL602_NET_NINTERFACES determines the number of physical interfaces +/* BL602_NET_NINTERFACES determines the number of physical interfaces * that will be supported. */ -#ifndef CONFIG_BL602_NET_NINTERFACES -#define CONFIG_BL602_NET_NINTERFACES 1 +#ifndef CONFIG_BL602_NET_MULTI_INTERFACE +#define BL602_NET_NINTERFACES 1 +#else +#define BL602_NET_NINTERFACES 2 #endif /* TX poll delay = 1 seconds. @@ -150,7 +153,6 @@ struct bl602_net_driver_s */ unsigned int current_mode : 2; /* current mode */ - unsigned int scan_result_len : 6; /* max 64 */ unsigned int push_cnt : 4; /* max 16 */ unsigned int prev_connectd : 1; /* mark of prev connection status */ @@ -189,6 +191,7 @@ typedef uint8_t (*tx_buff_t)[BL602_NET_TXBUFF_SIZE]; struct rx_pending_item_s { struct list_node node; + struct bl602_net_driver_s *priv; /* Which interface should to deliver */ uint8_t * data; int len; }; @@ -199,7 +202,7 @@ struct rx_pending_item_s /* Driver state structure */ -struct bl602_net_driver_s g_bl602_net[CONFIG_BL602_NET_NINTERFACES]; +struct bl602_net_driver_s g_bl602_net[BL602_NET_NINTERFACES]; static struct tx_buf_ind_s g_tx_buf_indicator = BITSET_T_INITIALIZER((1 << BL602_NET_TXBUFF_NUM) - 1); @@ -214,11 +217,22 @@ static sem_t g_wifi_connect_sem; static struct list_node g_rx_pending; +/* Firmware default config */ + static wifi_conf_t g_conf = { .country_code = CONFIG_BL602_WIRELESS_CONTRY_CODE, }; +/* Global state */ + +static struct +{ + uint32_t scan_result_status : 2; /* WiFi scan result status */ + uint32_t scan_result_len : 6; + uint32_t retry_cnt : 4; /* MAX 16 retries */ +} g_state; + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -645,7 +659,7 @@ static void bl602_net_receive(FAR struct bl602_net_driver_s *priv) } } -static int bl602_launch_pending_rx(FAR struct bl602_net_driver_s *priv) +static int bl602_launch_pending_rx(void) { struct rx_pending_item_s *item; irqstate_t irqstate; @@ -689,14 +703,15 @@ static int bl602_launch_pending_rx(FAR struct bl602_net_driver_s *priv) /* now we have avaliable tx buffer and pending rx data, launch it */ - DEBUGASSERT(priv->net_dev.d_buf == NULL); + DEBUGASSERT(item->priv != NULL); + DEBUGASSERT(item->priv->net_dev.d_buf == NULL); DEBUGASSERT(item->data != NULL && item->len > 0); - priv->net_dev.d_buf = item->data; - priv->net_dev.d_len = item->len; - bl602_net_receive(priv); + item->priv->net_dev.d_buf = item->data; + item->priv->net_dev.d_len = item->len; + bl602_net_receive(item->priv); - DEBUGASSERT(priv->net_dev.d_buf == NULL); + DEBUGASSERT(item->priv->net_dev.d_buf == NULL); net_unlock(); kmm_free(item); @@ -713,24 +728,29 @@ static int bl602_launch_pending_rx(FAR struct bl602_net_driver_s *priv) * event: notify type, tx done or received new data * data: The data of the event, may be NULL * len: data length + * opaque: customer data * * Returned Value: * OK on success; a negated errno on failure * ****************************************************************************/ -int bl602_net_notify(uint32_t event, uint8_t *data, int len) +int bl602_net_notify(uint32_t event, uint8_t *data, int len, void *opaque) { - /* TODO distinguish which driver */ + DEBUGASSERT(opaque != NULL); - FAR struct bl602_net_driver_s *priv = &g_bl602_net[0]; - int ret; + FAR struct bl602_net_driver_s *priv = + (FAR struct bl602_net_driver_s *)opaque; + + DEBUGASSERT(priv == &g_bl602_net[0] || priv == &g_bl602_net[1]); + + int ret; if (event & BL602_NET_EVT_TX_DONE) { /* if we have tx buffer, we put pending input packet first */ - ret = bl602_launch_pending_rx(priv); + ret = bl602_launch_pending_rx(); if (ret != OK) { /* There is no tx buffer, we needn't to poll.. */ @@ -782,6 +802,7 @@ int bl602_net_notify(uint32_t event, uint8_t *data, int len) item->data = data; item->len = len; + item->priv = priv; wlinfo("pending rx data :%p %d\n", item->data, item->len); @@ -959,6 +980,25 @@ static int bl602_net_ifup(FAR struct net_driver_s *dev) return OK; } +static int bl602_net_soft_reset(void) +{ + int idx; + + wifi_mgmr_sta_disconnect(); + nxsig_sleep(1); + wifi_mgmr_api_ap_stop(); + nxsig_sleep(1); + wifi_mgmr_api_idle(); + wifi_mgmr_reset(); + + for (idx = 0; idx < BL602_NET_NINTERFACES; idx++) + { + g_bl602_net[idx].current_mode = IW_MODE_AUTO; + } + + return 0; +} + /**************************************************************************** * Name: bl602_net_ifdown * @@ -993,6 +1033,12 @@ static int bl602_net_ifdown(FAR struct net_driver_s *dev) wd_cancel(&priv->txpoll); leave_critical_section(flags); + + if (priv == &g_bl602_net[0]) + { + bl602_net_soft_reset(); + } + net_unlock(); return OK; } @@ -1245,7 +1291,7 @@ static void scan_complete_indicate(void *data, void *param) para = (struct scan_parse_param_s *)data; DEBUGASSERT(para != NULL); DEBUGASSERT(para->priv != NULL); - para->priv->scan_result_len = 0; + g_state.scan_result_len = 0; for (i = 0; i < sizeof(WIFI_MGMR.scan_items) / sizeof(WIFI_MGMR.scan_items[0]); @@ -1260,14 +1306,19 @@ static void scan_complete_indicate(void *data, void *param) } else if (scan->is_used) { - if (para->flags & IW_SCAN_THIS_ESSID) + if (para->priv->channel != 0 && + scan->channel != para->priv->channel) + { + scan->is_used = 0; + } + else if (para->flags & IW_SCAN_THIS_ESSID) { if (strncmp(scan->ssid, (char *)para->scan_req.essid, sizeof(scan->ssid)) == 0) { scan->is_used = 1; - para->priv->scan_result_len++; + g_state.scan_result_len++; } else { @@ -1276,12 +1327,11 @@ static void scan_complete_indicate(void *data, void *param) } else { - para->priv->scan_result_len++; + g_state.scan_result_len++; } } } - sem_post(&g_wifi_scan_sem); kmm_free(data); return; } @@ -1446,14 +1496,14 @@ static int bl602_ioctl_wifi_start(FAR struct bl602_net_driver_s *priv, int state; wifi_mgmr_sta_autoconnect_enable(); - if (wifi_mgmr_api_connect(mgmr->wifi_mgmr_stat_info.ssid, - mgmr->wifi_mgmr_stat_info.psk, + if (wifi_mgmr_sta_connect(NULL, mgmr->wifi_mgmr_stat_info.ssid, + mgmr->wifi_mgmr_stat_info.passphr, NULL, (uint8_t *)priv->bssid, 0, priv->channel) == -1) { - return -ENOBUFS; + return -EPIPE; } sem_wait(&g_wifi_connect_sem); @@ -1463,17 +1513,21 @@ static int bl602_ioctl_wifi_start(FAR struct bl602_net_driver_s *priv, wifi_mgmr_state_get_internal(&state); if (state != WIFI_STATE_CONNECTED_IP_GOT) { - return -EINVAL; + return -EPIPE; } } else if (priv->current_mode == IW_MODE_MASTER) { + int channel; + wifi_mgmr_channel_get(&channel); + syslog(LOG_INFO, "current channel:%d\n", channel); + if (wifi_mgmr_api_ap_start(mgmr->wifi_mgmr_stat_info.ssid, - mgmr->wifi_mgmr_stat_info.psk, - 1, + mgmr->wifi_mgmr_stat_info.passphr, + channel ? channel : 1, 0) < 0) { - return -ENOBUFS; + return -EPIPE; } } else @@ -1568,7 +1622,16 @@ bl602_net_ioctl(FAR struct net_driver_s *dev, int cmd, unsigned long arg) if (sem_trywait(&g_wifi_scan_sem) == 0) { - wifi_mgmr_scan(para, scan_complete_indicate); + if (priv->channel != 0) + { + wifi_mgmr_scan_fixed_channels(para, scan_complete_indicate, + &priv->channel, 1); + } + else + { + wifi_mgmr_scan(para, scan_complete_indicate); + } + return OK; } else @@ -1587,14 +1650,21 @@ bl602_net_ioctl(FAR struct net_driver_s *dev, int cmd, unsigned long arg) sem_wait(&g_wifi_scan_sem); - if (priv->scan_result_len == 0) + if (g_state.scan_result_status != 0) + { + wlwarn("scan failed\n"); + sem_post(&g_wifi_scan_sem); + return -EIO; + } + + if (g_state.scan_result_len == 0) { req->u.data.length = 0; sem_post(&g_wifi_scan_sem); return OK; } - ret = format_scan_result_to_wapi(req, priv->scan_result_len); + ret = format_scan_result_to_wapi(req, g_state.scan_result_len); sem_post(&g_wifi_scan_sem); return ret; } @@ -1627,7 +1697,7 @@ bl602_net_ioctl(FAR struct net_driver_s *dev, int cmd, unsigned long arg) strncpy(passphrase, (char *)ext->key, ext->key_len); passphrase[ext->key_len] = 0; - wifi_mgmr_sta_psk_set(passphrase); + wifi_mgmr_sta_passphr_set(passphrase); kmm_free(passphrase); return OK; } @@ -1662,6 +1732,13 @@ bl602_net_ioctl(FAR struct net_driver_s *dev, int cmd, unsigned long arg) do { struct iwreq *req = (struct iwreq *)arg; +#ifdef CONFIG_BL602_NET_MULTI_INTERFACE + int interface_idx = priv - g_bl602_net; + + DEBUGASSERT(interface_idx >= 0 && + interface_idx < BL602_NET_NINTERFACES); +#endif + if (req->u.mode == priv->current_mode) { wlinfo("mode not change\n"); @@ -1672,7 +1749,15 @@ bl602_net_ioctl(FAR struct net_driver_s *dev, int cmd, unsigned long arg) { /* station */ - priv->wlan = wifi_mgmr_sta_enable(); +#ifdef CONFIG_BL602_NET_MULTI_INTERFACE + if (interface_idx != 0) + { + wlwarn("The interface does not support this mode.\n"); + return -ENOSYS; + } +#endif + + priv->wlan = wifi_mgmr_sta_enable((void *)priv); memcpy(priv->wlan->mac, priv->net_dev.d_mac.ether.ether_addr_octet, @@ -1685,7 +1770,15 @@ bl602_net_ioctl(FAR struct net_driver_s *dev, int cmd, unsigned long arg) { /* AP Mode */ - priv->wlan = wifi_mgmr_ap_enable(); +#ifdef CONFIG_BL602_NET_MULTI_INTERFACE + if (interface_idx != 1) + { + wlwarn("The interface does not support this mode.\n"); + return -ENOSYS; + } +#endif + + priv->wlan = wifi_mgmr_ap_enable((void *)priv); memcpy(priv->wlan->mac, priv->net_dev.d_mac.ether.ether_addr_octet, 6); @@ -1776,6 +1869,7 @@ bl602_net_ioctl(FAR struct net_driver_s *dev, int cmd, unsigned long arg) else if (req->u.essid.flags == 1) { priv->prev_connectd = 0; + g_state.retry_cnt = 0; return bl602_ioctl_wifi_start(priv, arg); } else @@ -1849,13 +1943,29 @@ bl602_net_ioctl(FAR struct net_driver_s *dev, int cmd, unsigned long arg) ext = (struct iw_encode_ext *)req->u.encoding.pointer; length = req->u.encoding.length - sizeof(struct iw_encode_ext); ext->alg = IW_ENCODE_ALG_NONE; - ext->key_len = strlen(mgmr->wifi_mgmr_stat_info.psk); + ext->key_len = strlen(mgmr->wifi_mgmr_stat_info.passphr); if (ext->key_len > length) { return -E2BIG; } - memcpy(ext->key, mgmr->wifi_mgmr_stat_info.psk, ext->key_len); + memcpy(ext->key, mgmr->wifi_mgmr_stat_info.passphr, ext->key_len); + + return OK; + } + while (0); + break; + + case SIOCSIWCOUNTRY: /* Set country code */ + do + { + struct iwreq *req = (struct iwreq *)arg; + + ret = wifi_mgmr_set_country_code(req->u.data.pointer); + if (ret != 0) + { + return -EINVAL; + } return OK; } @@ -1967,9 +2077,6 @@ void bl602_netdev_free_txbuf(uint8_t *buf) void bl602_net_event(int evt, int val) { - /* TODO distinguish which driver */ - - FAR struct bl602_net_driver_s *priv = &g_bl602_net[0]; net_lock(); switch (evt) @@ -1977,8 +2084,10 @@ void bl602_net_event(int evt, int val) case CODE_WIFI_ON_CONNECTED: do { + struct bl602_net_driver_s *priv = &g_bl602_net[0]; priv->prev_connectd = 1; + wifi_mgmr_sta_autoconnect_disable(); sem_post(&g_wifi_connect_sem); } while (0); @@ -1987,13 +2096,13 @@ void bl602_net_event(int evt, int val) case CODE_WIFI_CMD_RECONNECT: do { - static int retry_cnt = 0; - wlinfo("retry connect : %d\n", retry_cnt); + struct bl602_net_driver_s *priv = &g_bl602_net[0]; + + wlinfo("retry connect : %d\n", g_state.retry_cnt); if (!priv->prev_connectd) { - if (retry_cnt++ > 3) + if (g_state.retry_cnt++ > 1) { - retry_cnt = 0; wifi_mgmr_sta_autoconnect_disable(); wifi_mgmr_api_idle(); @@ -2004,6 +2113,14 @@ void bl602_net_event(int evt, int val) while (0); break; + case CODE_WIFI_ON_SCAN_DONE: + do + { + g_state.scan_result_status = val; + sem_post(&g_wifi_scan_sem); + } + while (0); + default: wlwarn("unhandled msg:%d\n", evt); break; @@ -2019,8 +2136,7 @@ void bl602_net_event(int evt, int val) * Initialize the Wireless controller and driver * * Input Parameters: - * intf - In the case where there are multiple EMACs, this value - * identifies which EMAC is to be initialized. + * None * * Returned Value: * OK on success; Negated errno on failure. @@ -2030,39 +2146,13 @@ void bl602_net_event(int evt, int val) * ****************************************************************************/ -int bl602_net_initialize(int intf) +int bl602_net_initialize(void) { FAR struct bl602_net_driver_s *priv; int tmp; + int idx; uint8_t mac[6]; - /* Get the interface structure associated with this interface number. */ - - DEBUGASSERT(intf < CONFIG_BL602_NET_NINTERFACES); - priv = &g_bl602_net[intf]; - - /* Initialize the driver structure */ - - memset(priv, 0, sizeof(struct bl602_net_driver_s)); - priv->net_dev.d_ifup = - bl602_net_ifup; /* I/F up (new IP address) callback */ - - priv->net_dev.d_ifdown = bl602_net_ifdown; /* I/F down callback */ - priv->net_dev.d_txavail = bl602_net_txavail; /* New TX data callback */ -#ifdef CONFIG_NET_MCASTGROUP - priv->net_dev.d_addmac = bl602_net_addmac; /* Add multicast MAC address */ - priv->net_dev.d_rmmac = bl602_net_rmmac; /* Remove multicast MAC address */ -#endif -#ifdef CONFIG_NETDEV_IOCTL - priv->net_dev.d_ioctl = bl602_net_ioctl; /* Handle network IOCTL commands */ -#endif - priv->net_dev.d_private = priv; /* Used to recover private state from dev */ - priv->net_dev.d_pktsize = - BL602_NET_TXBUFF_SIZE - PRESERVE_80211_HEADER_LEN; - - priv->current_mode = IW_MODE_AUTO; - priv->scan_result_len = 0; - /* Initialize scan semaphore */ tmp = sem_init(&g_wifi_scan_sem, 0, 1); @@ -2088,7 +2178,7 @@ int bl602_net_initialize(int intf) * Applies only if the Wireless MAC has its own internal address. */ - bl602_ef_ctrl_read_mac_address(mac); + bl602_efuse_read_mac_address(mac); wlinfo(":::MAC:%x %x %x %x %x %x\n", mac[0], mac[1], @@ -2097,17 +2187,66 @@ int bl602_net_initialize(int intf) mac[4], mac[5]); - memcpy(priv->net_dev.d_mac.ether.ether_addr_octet, mac, 6); - bl_wifi_ap_mac_addr_set(priv->net_dev.d_mac.ether.ether_addr_octet); - bl_wifi_sta_mac_addr_set(priv->net_dev.d_mac.ether.ether_addr_octet); - - /* Register the device with the OS so that socket IOCTLs can be performed */ - - tmp = netdev_register(&priv->net_dev, NET_LL_IEEE80211); - if (tmp < 0) + for (idx = 0; idx < BL602_NET_NINTERFACES; idx++) { - sem_destroy(&g_wifi_scan_sem); - return tmp; + /* Get the interface structure associated with this interface number. */ + + priv = &g_bl602_net[idx]; + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct bl602_net_driver_s)); + priv->net_dev.d_ifup = + bl602_net_ifup; /* I/F up (new IP address) callback */ + + priv->net_dev.d_ifdown = bl602_net_ifdown; /* I/F down callback */ + priv->net_dev.d_txavail = bl602_net_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_MCASTGROUP + priv->net_dev.d_addmac = bl602_net_addmac; /* Add multicast MAC address */ + priv->net_dev.d_rmmac = bl602_net_rmmac; /* Remove multicast MAC address */ +#endif +#ifdef CONFIG_NETDEV_IOCTL + priv->net_dev.d_ioctl = bl602_net_ioctl; /* Handle network IOCTL commands */ +#endif + priv->net_dev.d_private = priv; /* Used to recover private state from dev */ + priv->net_dev.d_pktsize = + BL602_NET_TXBUFF_SIZE - PRESERVE_80211_HEADER_LEN; + +#ifdef CONFIG_BL602_NET_MULTI_INTERFACE + /* Set AP's MAC address equals STA's MAC */ + + memcpy(priv->net_dev.d_mac.ether.ether_addr_octet, mac, 6); + + if (idx == 0) + { + bl_wifi_sta_mac_addr_set( + priv->net_dev.d_mac.ether.ether_addr_octet); + } + else + { + bl_wifi_ap_mac_addr_set( + priv->net_dev.d_mac.ether.ether_addr_octet); + } +#else + DEBUGASSERT(idx == 0); + + memcpy(priv->net_dev.d_mac.ether.ether_addr_octet, mac, 6); + bl_wifi_sta_mac_addr_set(priv->net_dev.d_mac.ether.ether_addr_octet); + bl_wifi_ap_mac_addr_set(priv->net_dev.d_mac.ether.ether_addr_octet); +#endif + + priv->current_mode = IW_MODE_AUTO; + + /* Register the device with the OS so that socket IOCTLs can be + * performed + */ + + tmp = netdev_register(&priv->net_dev, NET_LL_IEEE80211); + if (tmp < 0) + { + sem_destroy(&g_wifi_scan_sem); + return tmp; + } } return OK; diff --git a/arch/risc-v/src/bl602/bl602_netdev.h b/arch/risc-v/src/bl602/bl602_netdev.h index 548c3da1633..933c34e801c 100644 --- a/arch/risc-v/src/bl602/bl602_netdev.h +++ b/arch/risc-v/src/bl602/bl602_netdev.h @@ -100,13 +100,14 @@ void bl602_netdev_free_txbuf(uint8_t *buf); * event: notify type, tx done or received new data * data: The data of the event, may be NULL * len: data length + * opaque: customer data * * Returned Value: * OK on success; a negated errno on failure * ****************************************************************************/ -int bl602_net_notify(uint32_t event, uint8_t *data, int len); +int bl602_net_notify(uint32_t event, uint8_t *data, int len, void *opaque); /**************************************************************************** * Name: bl602_net_event diff --git a/arch/risc-v/src/bl602/bl602_romapi.h b/arch/risc-v/src/bl602/bl602_romapi.h new file mode 100644 index 00000000000..c2696e39775 --- /dev/null +++ b/arch/risc-v/src/bl602/bl602_romapi.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/risc-v/src/bl602/bl602_romapi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_BL602_BL602_ROMAPI_H +#define __ARCH_RISCV_SRC_BL602_BL602_ROMAPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#define BL602_ROMAPI_BASE (0x21010800) +#define BL602_ROMAPI_FUNC(idx) (*(uintptr_t *)(BL602_ROMAPI_BASE + (idx)*4)) + +#define BL602_ROMAPI_ASM_DELAY_US BL602_ROMAPI_FUNC(20) +#define BL602_ROMAPI_EFUSE_CTRL_LOAD_R0 BL602_ROMAPI_FUNC(31) +#define BL602_ROMAPI_RST_SYSTEM BL602_ROMAPI_FUNC(47) +#define BL602_ROMAPI_RST_CPU_SW BL602_ROMAPI_FUNC(48) +#define BL602_ROMAPI_RST_POR BL602_ROMAPI_FUNC(49) +#define BL602_ROMAPI_SFLASH_EREASE_NEEDLOCK BL602_ROMAPI_FUNC(163) +#define BL602_ROMAPI_SFLASH_WRITE_NEEDLOCK BL602_ROMAPI_FUNC(164) +#define BL602_ROMAPI_SFLASH_READ_NEEDLOCK BL602_ROMAPI_FUNC(165) +#define BL602_ROMAPI_SFLASH_GET_JEDECID_NOLOCK BL602_ROMAPI_FUNC(166) +#define BL602_ROMAPI_SFLASH_READ_WITHLOCK BL602_ROMAPI_FUNC(170) +#define BL602_ROMAPI_SFLASH_WRITE_WITHLOCK BL602_ROMAPI_FUNC(171) +#define BL602_ROMAPI_SFLASH_EREASE_WITHLOCK BL602_ROMAPI_FUNC(172) + +#endif diff --git a/arch/risc-v/src/bl602/bl602_rtc.c b/arch/risc-v/src/bl602/bl602_rtc.c new file mode 100644 index 00000000000..7392f1ebead --- /dev/null +++ b/arch/risc-v/src/bl602/bl602_rtc.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * arch/risc-v/src/bl602/bl602_rtc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "riscv_arch.h" + +#include "chip.h" +#include "hardware/bl602_hbn.h" +#include "bl602_rtc.h" + +#define ROM_APITABLE ((uint32_t *)0x21010800) +#define ROMAPI_HBN_32K_SEL (ROM_APITABLE + 66) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef void (*bl602_romapi_hbn_sel_t)(uint8_t clk_type); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bl602_hbn_sel + * + * Description: + * HBN select 32K + * + * Input Parameters: + * clk_type: HBN 32k clock type + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_sel(uint8_t clk_type) +{ + modifyreg32(BL602_HBN_GLB, + HBN_GLB_HBN_F32K_SEL_MASK, + clk_type << HBN_GLB_HBN_F32K_SEL_SHIFT); +} + +/**************************************************************************** + * Name: bl602_hbn_clear_rtc_int + * + * Description: + * HBN clear RTC timer interrupt,this function must be called to clear + * delayed rtc IRQ + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_clear_rtc_int(void) +{ + /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */ + + modifyreg32(BL602_HBN_CTL, 0x7 << 1, 0); +} + +/**************************************************************************** + * Name: bl602_hbn_set_rtc_timer + * + * Description: + * HBN set RTC timer configuration + * + * Input Parameters: + * delay: RTC interrupt delay 32 clocks + * compval_low: RTC interrupt commpare value low 32 bits + * compval_high: RTC interrupt commpare value high 32 bits + * comp_mode: RTC interrupt commpare + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_set_rtc_timer(uint8_t delay_type, uint32_t compval_low, + uint32_t compval_high, uint8_t comp_mode) +{ + putreg32(compval_low, BL602_HBN_TIME_L); + putreg32(compval_high & 0xff, BL602_HBN_TIME_H); + + modifyreg32(BL602_HBN_CTL, + HBN_CTL_RTC_DLY_OPTION | (0x7 << 1), + delay_type | (comp_mode << 1)); +} + +/**************************************************************************** + * Name: bl602_hbn_clear_rtc_counter + * + * Description: + * HBN set RTC timer configuration + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_clear_rtc_counter(void) +{ + modifyreg32(BL602_HBN_CTL, 1, 0); +} + +/**************************************************************************** + * Name: bl602_hbn_enable_rtc_counter + * + * Description: + * HBN clear RTC timer counter + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_enable_rtc_counter(void) +{ + modifyreg32(BL602_HBN_CTL, 0, 1); +} + +/**************************************************************************** + * Name: bl602_hbn_get_rtc_timer_val + * + * Description: + * HBN get RTC timer count value + * + * Input Parameters: + * val_low: RTC count value pointer for low 32 bits + * val_high: RTC count value pointer for high 8 bits + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void bl602_hbn_get_rtc_timer_val(uint32_t *val_low, uint32_t *val_high) +{ + modifyreg32(BL602_HBN_RTC_TIME_H, 0, HBN_RTC_TIME_H_RTC_TIME_LATCH); + + modifyreg32(BL602_HBN_RTC_TIME_H, HBN_RTC_TIME_H_RTC_TIME_LATCH, 0); + + *val_low = getreg32(BL602_HBN_RTC_TIME_L); + *val_high = getreg32(BL602_HBN_RTC_TIME_H) & 0xff; +} + diff --git a/arch/risc-v/src/bl602/bl602_rtc.h b/arch/risc-v/src/bl602/bl602_rtc.h new file mode 100644 index 00000000000..c6cfe500a85 --- /dev/null +++ b/arch/risc-v/src/bl602/bl602_rtc.h @@ -0,0 +1,170 @@ +/**************************************************************************** + * arch/risc-v/src/bl602/bl602_rtc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_BL602_RTC_LOWERHALF_H +#define __ARCH_RISCV_SRC_BL602_RTC_LOWERHALF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BL602_HBN_32K_RC 0 /* HBN use rc 32k */ +#define BL602_HBN_32K_XTAL 1 /* HBN use xtal 32k */ +#define BL602_HBN_32K_DIG 3 /* HBN use dig 32k */ + +#define BL602_HBN_RTC_INT_DELAY_32T 0 /* HBN RTC int delay 32T */ +#define BL602_HBN_RTC_INT_DELAY_0T 1 /* HBN RTC int delay 0T */ + +#define BL602_HBN_RTC_COMP_BIT0_39 0x01 /* RTC COMP mode bit0-39 */ +#define BL602_HBN_RTC_COMP_BIT0_23 0x02 /* RTC COMP mode bit0-23 */ +#define BL602_HBN_RTC_COMP_BIT13_39 0x04 /* RTC COMP mode bit13-39 */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: bl602_hbn_sel + * + * Description: + * HBN select 32K + * + * Input Parameters: + * clk_type: HBN 32k clock type + * + * Returned Value: + * None. + * + ****************************************************************************/ + +FAR void bl602_hbn_sel(uint8_t clk_type); + +/**************************************************************************** + * Name: bl602_hbn_clear_rtc_int + * + * Description: + * HBN clear RTC timer interrupt,this function must be called to clear + * delayed rtc IRQ + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +FAR void bl602_hbn_clear_rtc_int(void); + +/**************************************************************************** + * Name: bl602_hbn_set_rtc_timer + * + * Description: + * HBN set RTC timer configuration + * + * Input Parameters: + * delay: RTC interrupt delay 32 clocks + * compval_low: RTC interrupt commpare value low 32 bits + * compval_high: RTC interrupt commpare value high 32 bits + * comp_mode: RTC interrupt commpare + * + * Returned Value: + * None. + * + ****************************************************************************/ + +FAR void bl602_hbn_set_rtc_timer(uint8_t delay_type, uint32_t compval_low, + uint32_t compval_high, uint8_t comp_mode); + +/**************************************************************************** + * Name: bl602_hbn_clear_rtc_counter + * + * Description: + * HBN set RTC timer configuration + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +FAR void bl602_hbn_clear_rtc_counter(void); + +/**************************************************************************** + * Name: bl602_hbn_enable_rtc_counter + * + * Description: + * HBN clear RTC timer counter + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +FAR void bl602_hbn_enable_rtc_counter(void); + +/**************************************************************************** + * Name: bl602_hbn_get_rtc_timer_val + * + * Description: + * HBN get RTC timer count value + * + * Input Parameters: + * val_low: RTC count value pointer for low 32 bits + * val_high: RTC count value pointer for high 8 bits + * + * Returned Value: + * None. + * + ****************************************************************************/ + +FAR void bl602_hbn_get_rtc_timer_val(uint32_t *val_low, uint32_t *val_high); + +/**************************************************************************** + * Name: bl602_rtc_lowerhalf_initialize + * + * Description: + * None. + * + * Input Parameters: + * pwm - A number identifying the pwm instance. + * + * Returned Value: + * On success, a pointer to the BL602 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +FAR struct rtc_lowerhalf_s *bl602_rtc_lowerhalf_initialize(void); + +#endif /* __ARCH_RISCV_SRC_BL602_RTC_LOWERHALF_H */ diff --git a/arch/risc-v/src/bl602/bl602_rtc_lowerhalf.c b/arch/risc-v/src/bl602/bl602_rtc_lowerhalf.c new file mode 100644 index 00000000000..0032e557dc3 --- /dev/null +++ b/arch/risc-v/src/bl602/bl602_rtc_lowerhalf.c @@ -0,0 +1,690 @@ +/**************************************************************************** + * arch/risc-v/src/bl602/bl602_rtc_lowerhalf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "riscv_arch.h" + +#include "chip.h" +#include "hardware/bl602_hbn.h" +#include "bl602_hbn.h" +#include "bl602_rtc.h" +#include "time.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct bl602_cbinfo_s +{ + rtc_alarm_callback_t cb; /* Callback when the alarm expires */ + FAR void *priv; /* Private argument to accompany callback */ +}; +#endif + +/* This is the private type for the RTC state. It must be cast compatible + * with struct rtc_lowerhalf_s. + */ + +struct bl602_lowerhalf_s +{ + /* This is the contained reference to the read-only, lower-half + * operations vtable (which may lie in FLASH or ROM) + */ + + FAR const struct rtc_ops_s *ops; + + /* Data following is private to this driver and not visible outside of + * this file. + */ + + sem_t devsem; /* Threads can only exclusively access the RTC */ + + struct rtc_time rtc_base; + struct rtc_time rtc_alarm; + +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct bl602_cbinfo_s cbinfo; +#endif + +#ifdef CONFIG_RTC_PERIODIC + /* Periodic wakeup information */ + + uint8_t periodic_enable; + struct lower_setperiodic_s periodic; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Prototypes for static methods in struct rtc_ops_s */ + +static int bl602_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime); +static int bl602_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime); +static bool bl602_havesettime(FAR struct rtc_lowerhalf_s *lower); + +#ifdef CONFIG_RTC_ALARM +static int bl602_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo); +static int bl602_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo); +static int bl602_cancelalarm(FAR struct rtc_lowerhalf_s *lower, + int alarmid); +static int bl602_rdalarm(FAR struct rtc_lowerhalf_s *lower, + FAR struct lower_rdalarm_s *alarminfo); +#endif + +#ifdef CONFIG_RTC_PERIODIC +static int bl602_setperiodic(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setperiodic_s *alarminfo); +static int bl602_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* BL602 RTC driver operations */ + +static const struct rtc_ops_s g_rtc_ops = +{ + .rdtime = bl602_rdtime, + .settime = bl602_settime, + .havesettime = bl602_havesettime, +#ifdef CONFIG_RTC_ALARM + .setalarm = bl602_setalarm, + .setrelative = bl602_setrelative, + .cancelalarm = bl602_cancelalarm, + .rdalarm = bl602_rdalarm, +#endif +#ifdef CONFIG_RTC_PERIODIC + .setperiodic = bl602_setperiodic, + .cancelperiodic = bl602_cancelperiodic, +#endif +#ifdef CONFIG_RTC_IOCTL + .ioctl = NULL, +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + .destroy = NULL, +#endif +}; + +/* BL602 RTC device state */ + +static struct bl602_lowerhalf_s g_rtc_lowerhalf = +{ + .ops = &g_rtc_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static uint64_t bl602_rtc_get_timestamp_ms(void) +{ + uint64_t cnt; + uint32_t val_low; + uint32_t val_high; + + bl602_hbn_get_rtc_timer_val(&val_low, &val_high); + + cnt = (uint64_t)val_high << 32 | val_low; + + /* cnt * 1000 / 32768 */ + + return (cnt >> 5) - (cnt >> 11) - (cnt >> 12); +} + +#if defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_PERIODIC) +static void bl602_rtc_set_timestamp_ms(uint64_t ms) +{ + ms += bl602_rtc_get_timestamp_ms(); + ms = ms * 32768 / 1000; + + bl602_hbn_set_rtc_timer(BL602_HBN_RTC_INT_DELAY_0T, + (uint32_t)ms, + (uint32_t)(ms >> 32), + BL602_HBN_RTC_COMP_BIT0_39); +} +#endif + +/**************************************************************************** + * Name: bl602_alarm_callback + * + * Description: + * This is the function that is called from the RTC driver when the alarm + * goes off. It just invokes the upper half drivers callback. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_PERIODIC) +static int bl602_alarm_callback(void *arg) +{ + struct bl602_lowerhalf_s *priv = (struct bl602_lowerhalf_s *)arg; + struct bl602_cbinfo_s *cbinfo = &priv->cbinfo; + + rtc_alarm_callback_t cb = (rtc_alarm_callback_t)cbinfo->cb; + FAR void *p_arg = (FAR void *)cbinfo->priv; + +#ifdef CONFIG_RTC_PERIODIC + if (priv->periodic_enable) + { + uint64_t time_stamp_s; + struct timespec *tm_spec = &priv->periodic.period; + + time_stamp_s = tm_spec->tv_sec; + + if (time_stamp_s) + { + bl602_rtc_set_timestamp_ms(time_stamp_s * 1000); + bl602_hbn_out0_int_enable(); + } + + if (priv->periodic.cb) + { + priv->periodic.cb(priv->periodic.priv, priv->periodic.id); + } + } +#endif + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(p_arg, 0); + } + + return OK; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: bl602_rdtime + * + * Description: + * Implements the rdtime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The location in which to return the current RTC time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int bl602_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime) +{ + struct bl602_lowerhalf_s *priv; + uint64_t time_stamp_s; + struct rtc_time tim; + + priv = (FAR struct bl602_lowerhalf_s *)lower; + time_stamp_s = bl602_rtc_get_timestamp_ms() / 1000; + + tim = priv->rtc_base; + + if (tim.tm_year >= 1900) + { + tim.tm_year -= 1900; + } + + time_stamp_s += mktime((FAR struct tm *)&tim); + gmtime_r((const time_t *)&time_stamp_s, (FAR struct tm *)&rtctime); + + return OK; +} + +/**************************************************************************** + * Name: bl602_settime + * + * Description: + * Implements the settime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The new time to set + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int bl602_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime) +{ + struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower; + + if (rtctime->tm_year < 1900) + { + return -ETIME; + } + + priv->rtc_base = *rtctime; + + return OK; +} + +/**************************************************************************** + * Name: bl602_havesettime + * + * Description: + * Implements the havesettime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Returns true if RTC date-time have been previously set. + * + ****************************************************************************/ + +static bool bl602_havesettime(FAR struct rtc_lowerhalf_s *lower) +{ + struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower; + + return (priv->rtc_base.tm_year != 0); +} + +/**************************************************************************** + * Name: bl602_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int bl602_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo) +{ + FAR struct bl602_lowerhalf_s *priv; + FAR struct bl602_cbinfo_s *cbinfo; + int ret; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0); + priv = (FAR struct bl602_lowerhalf_s *)lower; + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + ret = -EINVAL; + if (alarminfo->id == 0) + { + uint64_t time_stamp_s; + + /* Convert the RTC time to a timespec */ + + time_stamp_s = mktime((FAR struct tm *)&alarminfo->time); + priv->rtc_alarm = alarminfo->time; + + /* Remember the callback information */ + + cbinfo = &priv->cbinfo; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + + /* And set the alarm */ + + bl602_rtc_set_timestamp_ms(time_stamp_s * 1000); + + bl602_hbn_out0_int_enable(); + + ret = OK; + } + + nxsem_post(&priv->devsem); + + return ret; +} +#endif + +/**************************************************************************** + * Name: bl602_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int bl602_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo) +{ + FAR struct bl602_lowerhalf_s *priv; + struct lower_setalarm_s setalarm; + struct rtc_time *time; + time_t seconds; + int ret = -EINVAL; + + priv = (FAR struct bl602_lowerhalf_s *)lower; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + + if (alarminfo->id == 0 && alarminfo->reltime > 0) + { + /* Get the current time in broken out format */ + + time = &priv->rtc_base; + + /* Convert to seconds since the epoch */ + + seconds = mktime((struct tm *)time); + + /* Add the seconds offset. Add one to the number of seconds + * because we are unsure of the phase of the timer. + */ + + seconds += (alarminfo->reltime + 1); + + /* And convert the time back to broken out format */ + + gmtime_r(&seconds, (FAR struct tm *)&setalarm.time); + + /* The set the alarm using this absolute time */ + + setalarm.id = alarminfo->id; + setalarm.cb = alarminfo->cb; + setalarm.priv = alarminfo->priv; + + ret = bl602_setalarm(lower, &setalarm); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: bl602_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int bl602_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid) +{ + FAR struct bl602_lowerhalf_s *priv; + FAR struct bl602_cbinfo_s *cbinfo; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT(alarmid == 0); + priv = (FAR struct bl602_lowerhalf_s *)lower; + + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + memset(&priv->rtc_alarm, 0, sizeof(priv->rtc_alarm)); + + /* Then cancel the alarm */ + + bl602_hbn_out0_int_unregister(BL602_HBN_OUT0_INT_RTC); + bl602_hbn_out0_int_disable(); + + return OK; +} +#endif + +/**************************************************************************** + * Name: bl602_rdalarm + * + * Description: + * Query the RTC alarm. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to query the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int bl602_rdalarm(FAR struct rtc_lowerhalf_s *lower, + FAR struct lower_rdalarm_s *alarminfo) +{ + FAR struct bl602_lowerhalf_s *priv; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); + priv = (FAR struct bl602_lowerhalf_s *)lower; + + if (alarminfo->id == 0) + { + *alarminfo->time = priv->rtc_alarm; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: bl602_setperiodic + * + * Description: + * Set a new periodic wakeup relative to the current time, with a given + * period. This function implements the setperiodic() method of the RTC + * driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the wakeup activity + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int bl602_setperiodic(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setperiodic_s *alarminfo) +{ + FAR struct bl602_lowerhalf_s *priv; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + priv = (FAR struct bl602_lowerhalf_s *)lower; + + flags = enter_critical_section(); + priv->periodic = *alarminfo; + priv->periodic_enable = 1; + memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); + leave_critical_section(flags); + + return OK; +} +#endif + +/**************************************************************************** + * Name: bl602_cancelperiodic + * + * Description: + * Cancel the current periodic wakeup activity. This function implements + * the cancelperiodic() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int bl602_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id) +{ + FAR struct bl602_lowerhalf_s *priv; + irqstate_t flags; + + DEBUGASSERT(lower != NULL); + priv = (FAR struct bl602_lowerhalf_s *)lower; + + DEBUGASSERT(id == 0); + + flags = enter_critical_section(); + priv->periodic_enable = 0; + leave_critical_section(flags); + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. This + * function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ +#ifdef CONFIG_BL602_RTC_USE_XTAL32K + bl602_hbn_sel(BL602_HBN_32K_XTAL); +#else + bl602_hbn_sel(BL602_HBN_32K_RC); +#endif + + bl602_hbn_clear_rtc_counter(); + bl602_hbn_enable_rtc_counter(); + + bl602_hbn_out0_int_register(BL602_HBN_OUT0_INT_RTC, + bl602_alarm_callback, + (void *)&g_rtc_lowerhalf); + return OK; +} + +/**************************************************************************** + * Name: bl602_rtc_lowerhalf_initialize + * + * Description: + * Instantiate the RTC lower half driver for the BL602. General usage: + * + * #include + * #include "bl602_rtc.h" + * + * struct rtc_lowerhalf_s *lower; + * lower = bl602_rtc_lowerhalf_initialize(); + * rtc_initialize(0, lower); + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +FAR struct rtc_lowerhalf_s *bl602_rtc_lowerhalf_initialize(void) +{ + nxsem_init(&g_rtc_lowerhalf.devsem, 0, 1); + +#ifdef CONFIG_RTC_PERIODIC + g_rtc_lowerhalf.periodic_enable = 0; +#endif + memset(&g_rtc_lowerhalf.rtc_base, 0, sizeof(g_rtc_lowerhalf.rtc_base)); + + return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; +} diff --git a/arch/risc-v/src/bl602/bl602_spi.c b/arch/risc-v/src/bl602/bl602_spi.c index e05c2945013..f304bb9d2b5 100644 --- a/arch/risc-v/src/bl602/bl602_spi.c +++ b/arch/risc-v/src/bl602/bl602_spi.c @@ -24,6 +24,8 @@ #include +#include +#include #include #include #include diff --git a/arch/risc-v/src/bl602/bl602_start.c b/arch/risc-v/src/bl602/bl602_start.c index deaea60e9b6..f037832c2e0 100644 --- a/arch/risc-v/src/bl602/bl602_start.c +++ b/arch/risc-v/src/bl602/bl602_start.c @@ -25,10 +25,12 @@ #include #include +#include #include #include #include +#include #ifdef CONFIG_STACK_OVERFLOW_CHECK # include "sched/sched.h" diff --git a/arch/risc-v/src/bl602/bl602_systemreset.c b/arch/risc-v/src/bl602/bl602_systemreset.c index 172ae632d9d..c639fc4a52a 100644 --- a/arch/risc-v/src/bl602/bl602_systemreset.c +++ b/arch/risc-v/src/bl602/bl602_systemreset.c @@ -29,6 +29,11 @@ #include "hardware/bl602_glb.h" #include "hardware/bl602_hbn.h" +#include "bl602_romapi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ /* We choose to use ROM driver here. * @@ -36,11 +41,9 @@ * reset, this part of the code cannot be placed on the XIP Flash. */ -typedef void (*bl602_romdrv_reset_system) (void); -typedef void (*bl602_romdrv_reset_sw_cpu) (void); -typedef void (*bl602_romdrv_reset_por) (void); - -#define ROM_APITABLE ((uint32_t *)0x21010800) +#define bl602_romapi_reset_system ((void (*)(void))BL602_ROMAPI_RST_SYSTEM) +#define bl602_romapi_reset_cpu_sw ((void (*)(void))BL602_ROMAPI_RST_CPU_SW) +#define bl602_romapi_reset_por ((void (*)(void))BL602_ROMAPI_RST_POR) /**************************************************************************** * Private Functions @@ -64,7 +67,7 @@ void up_systemreset(void) asm volatile("csrci mstatus, 8"); - ((bl602_romdrv_reset_system)(*(ROM_APITABLE + 47)))(); + bl602_romapi_reset_system(); } /**************************************************************************** @@ -81,7 +84,7 @@ void bl602_cpu_reset(void) asm volatile("csrci mstatus, 8"); - ((bl602_romdrv_reset_sw_cpu)(*(ROM_APITABLE + 48)))(); + bl602_romapi_reset_cpu_sw(); } /**************************************************************************** @@ -98,5 +101,5 @@ void bl602_por_reset(void) asm volatile("csrci mstatus, 8"); - ((bl602_romdrv_reset_por)(*(ROM_APITABLE + 49)))(); + bl602_romapi_reset_por(); } diff --git a/arch/risc-v/src/bl602/bl602_wdt_lowerhalf.c b/arch/risc-v/src/bl602/bl602_wdt_lowerhalf.c index c0ee29cf250..7a5f79e0547 100644 --- a/arch/risc-v/src/bl602/bl602_wdt_lowerhalf.c +++ b/arch/risc-v/src/bl602/bl602_wdt_lowerhalf.c @@ -27,6 +27,7 @@ #include #include +#include #include #include diff --git a/arch/risc-v/src/c906/Make.defs b/arch/risc-v/src/c906/Make.defs index a367c4d79a8..8088b461510 100644 --- a/arch/risc-v/src/c906/Make.defs +++ b/arch/risc-v/src/c906/Make.defs @@ -55,6 +55,7 @@ CHIP_CSRCS += c906_start.c c906_timerisr.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c +CMN_CSRCS += riscv_pthread_exit.c CMN_CSRCS += riscv_signal_dispatch.c riscv_pmp.c CMN_UASRCS += riscv_signal_handler.S diff --git a/arch/risc-v/src/c906/c906_head.S b/arch/risc-v/src/c906/c906_head.S index f183286b72e..f7a585365b7 100644 --- a/arch/risc-v/src/c906/c906_head.S +++ b/arch/risc-v/src/c906/c906_head.S @@ -93,33 +93,6 @@ __start: la t0, __trap_vec csrw mtvec, t0 -#ifdef CONFIG_STACK_COLORATION - - /* Write a known value to the IDLE thread stack to support stack - * monitoring logic - */ - - lui t0, %hi(C906_IDLESTACK_BASE) - addi t0, t0, %lo(C906_IDLESTACK_BASE) - - lui t1, %hi(C906_IDLESTACK_TOP) - addi t1, t1, %lo(C906_IDLESTACK_TOP) - - lui t2, %hi(STACK_COLOR) - addi t2, t2, %lo(STACK_COLOR) - - bgeu t0, t1, 2f - - /* t0 = start of IDLE stack; t1 = Size of tack; t2 = coloration */ - -1: - sw t2, 0(t0) - addi t0, t0, 4 - bne t0, t1, 1b -2: - -#endif - /* Jump to __c906_start with mhartid */ j __c906_start @@ -191,7 +164,7 @@ exception_common: mv a1, sp /* context = sp */ -#if CONFIG_ARCH_INTERRUPTSTACK > 7 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 /* Load mhartid (cpuid) */ csrr s0, mhartid @@ -203,7 +176,7 @@ exception_common: j 4f 3: la sp, g_intstacktop - addi sp, sp, -(CONFIG_ARCH_INTERRUPTSTACK & ~7) + addi sp, sp, -(CONFIG_ARCH_INTERRUPTSTACK & ~15) 4: #endif diff --git a/arch/risc-v/src/c906/c906_irq.c b/arch/risc-v/src/c906/c906_irq.c index eae7ca814ce..8db70604aeb 100644 --- a/arch/risc-v/src/c906/c906_irq.c +++ b/arch/risc-v/src/c906/c906_irq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -72,8 +73,8 @@ void up_irqinitialize(void) /* Colorize the interrupt stack for debug purposes */ -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 7 - size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~7); +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); riscv_stack_color((FAR void *)&g_intstackalloc, intstack_size); #endif @@ -233,39 +234,6 @@ void riscv_ack_irq(int irq) { } -/**************************************************************************** - * Name: up_irq_save - * - * Description: - * Return the current interrupt state and disable interrupts - * - ****************************************************************************/ - -irqstate_t up_irq_save(void) -{ - uint64_t oldstat; - - /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ - - asm volatile ("csrrc %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE)); - return oldstat; -} - -/**************************************************************************** - * Name: up_irq_restore - * - * Description: - * Restore previous IRQ mask state - * - ****************************************************************************/ - -void up_irq_restore(irqstate_t flags) -{ - /* Write flags to mstatus */ - - asm volatile("csrw mstatus, %0" : /* no output */ : "r" (flags)); -} - /**************************************************************************** * Name: up_irq_enable * diff --git a/arch/risc-v/src/c906/c906_serial.c b/arch/risc-v/src/c906/c906_serial.c index da70e92dbf3..4d5fafa0dba 100644 --- a/arch/risc-v/src/c906/c906_serial.c +++ b/arch/risc-v/src/c906/c906_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/common/riscv_checkstack.c b/arch/risc-v/src/common/riscv_checkstack.c index ca35375e3cf..5429696cc50 100644 --- a/arch/risc-v/src/common/riscv_checkstack.c +++ b/arch/risc-v/src/common/riscv_checkstack.c @@ -176,16 +176,16 @@ ssize_t up_check_stack_remain(void) return up_check_tcbstack_remain(this_task()); } -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 size_t up_check_intstack(void) { return do_stackcheck((uintptr_t)&g_intstackalloc, - (CONFIG_ARCH_INTERRUPTSTACK & ~3)); + (CONFIG_ARCH_INTERRUPTSTACK & ~15)); } size_t up_check_intstack_remain(void) { - return (CONFIG_ARCH_INTERRUPTSTACK & ~3) - up_check_intstack(); + return (CONFIG_ARCH_INTERRUPTSTACK & ~15) - up_check_intstack(); } #endif diff --git a/arch/risc-v/src/common/riscv_createstack.c b/arch/risc-v/src/common/riscv_createstack.c index 4e77a469f80..1616c99bbf5 100644 --- a/arch/risc-v/src/common/riscv_createstack.c +++ b/arch/risc-v/src/common/riscv_createstack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/common/riscv_initialize.c b/arch/risc-v/src/common/riscv_initialize.c index abbbe169901..bcf07ba26b3 100644 --- a/arch/risc-v/src/common/riscv_initialize.c +++ b/arch/risc-v/src/common/riscv_initialize.c @@ -53,13 +53,13 @@ * ****************************************************************************/ -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 static inline void up_color_intstack(void) { uint32_t *ptr = (uint32_t *)&g_intstackalloc; ssize_t size; - for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); size > 0; size -= sizeof(uint32_t)) { diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h index 6c1e4a033da..80d89d1678a 100644 --- a/arch/risc-v/src/common/riscv_internal.h +++ b/arch/risc-v/src/common/riscv_internal.h @@ -113,7 +113,7 @@ EXTERN uint32_t g_idle_topstack; /* Address of the saved user stack pointer */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 EXTERN uint32_t g_intstackalloc; /* Allocated stack base */ EXTERN uint32_t g_intstacktop; /* Initial top of interrupt stack */ #endif diff --git a/arch/risc-v/src/common/riscv_pthread_exit.c b/arch/risc-v/src/common/riscv_pthread_exit.c new file mode 100644 index 00000000000..39964ea1ff1 --- /dev/null +++ b/arch/risc-v/src/common/riscv_pthread_exit.c @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/risc-v/src/common/riscv_pthread_exit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "svcall.h" +#include "riscv_internal.h" + +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) && \ + !defined(CONFIG_DISABLE_PTHREAD) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_pthread_exit + * + * Description: + * In this kernel mode build, this function will be called to execute a + * pthread in user-space. This kernel-mode stub will then be called + * transfer control to the user-mode pthread_exit. + * + * Input Parameters: + * exit - The user-space pthread_exit function + * exit_value - The pointer of the pthread exit parameter + * + * Returned Value: + * None + ****************************************************************************/ + +void up_pthread_exit(pthread_exitroutine_t exit, FAR void *exit_value) +{ + sys_call2(SYS_pthread_exit, (uintptr_t)exit, (uintptr_t)exit_value); +} + +#endif /* !CONFIG_BUILD_FLAT && __KERNEL__ && !CONFIG_DISABLE_PTHREAD */ diff --git a/arch/risc-v/src/common/riscv_pthread_start.c b/arch/risc-v/src/common/riscv_pthread_start.c index f66b1740c64..a625385ec7f 100644 --- a/arch/risc-v/src/common/riscv_pthread_start.c +++ b/arch/risc-v/src/common/riscv_pthread_start.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "svcall.h" #include "riscv_internal.h" @@ -47,9 +48,10 @@ * pthread. * * Normally the a user-mode start-up stub will also execute before the - * pthread actually starts. See libc/pthread/pthread_startup.c + * pthread actually starts. See libc/pthread/pthread_create.c * * Input Parameters: + * startup - The user-space pthread startup function * entrypt - The user-space address of the pthread entry point * arg - Standard argument for the pthread entry point * @@ -60,11 +62,13 @@ * ****************************************************************************/ -void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) +void up_pthread_start(pthread_trampoline_t startup, + pthread_startroutine_t entrypt, pthread_addr_t arg) { - /* Let sys_call2() do all of the work */ + /* Let sys_call3() do all of the work */ - sys_call2(SYS_pthread_start, (uintptr_t)entrypt, (uintptr_t)arg); + sys_call3(SYS_pthread_start, (uintptr_t)startup, (uintptr_t)entrypt, + (uintptr_t)arg); PANIC(); } diff --git a/arch/risc-v/src/common/riscv_task_start.c b/arch/risc-v/src/common/riscv_task_start.c index f1783c18e27..dfc0b1b310a 100644 --- a/arch/risc-v/src/common/riscv_task_start.c +++ b/arch/risc-v/src/common/riscv_task_start.c @@ -24,6 +24,7 @@ #include #include +#include #include "svcall.h" #include "riscv_internal.h" diff --git a/arch/risc-v/src/common/riscv_usestack.c b/arch/risc-v/src/common/riscv_usestack.c index 68b2a89c998..a47b5082390 100644 --- a/arch/risc-v/src/common/riscv_usestack.c +++ b/arch/risc-v/src/common/riscv_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig index 8115c55fdcd..f5ba5130d4c 100644 --- a/arch/risc-v/src/esp32c3/Kconfig +++ b/arch/risc-v/src/esp32c3/Kconfig @@ -151,13 +151,31 @@ config ESP32C3_CPU_FREQ_MHZ config ESP32C3_RT_TIMER bool "Real-time Timer" default n + select ESP32C3_TIMER0 config ESP32C3_DISABLE_STDC_ATOMIC bool "Disable standard C atomic" default n +config ESP32C3_RTC_HEAP + bool "Use the RTC memory as a separate heap" + select ARCH_HAVE_EXTRA_HEAPS + default n + +config ESP32C3_WIRELESS + bool + default n + select ESP32C3_RT_TIMER + select ESP32C3_TIMER0 + menu "ESP32-C3 Peripheral Support" +config ESP32C3_ADC + bool + default n + select ANALOG + select ADC + config ESP32C3_UART bool default n @@ -174,10 +192,21 @@ config ESP32C3_WDT bool default n +config ESP32C3_EFUSE + bool "EFUSE support" + default n + ---help--- + Enable ESP32-C3 efuse support. + config ESP32C3_SPI bool default n +config ESP32C3_LEDC + bool "LEDC (PWM)" + default n + select PWM + config ESP32C3_GPIO_IRQ bool "GPIO pin interrupts" default n @@ -237,6 +266,11 @@ config ESP32C3_SPI2 select ESP32C3_SPI select SPI +config ESP32C3_DMA + bool "General DMA (GDMA)" + default n + select ARCH_DMA + config ESP32C3_MWDT0 bool "Main System Watchdog Timer (Group 0)" default n @@ -264,6 +298,11 @@ config ESP32C3_RWDT to have the RTC module reset, please, use the Timers' Module WDTs. They will only reset Main System. +config ESP32C3_ADC1 + bool "ADC1" + default n + select ESP32C3_ADC + config ESP32C3_WIRELESS bool "Wireless" default n @@ -274,8 +313,50 @@ config ESP32C3_WIRELESS ---help--- Enable Wireless support +config ESP32C3_AES_ACCELERATOR + bool "AES Accelerator" + default n +config ESP32C3_SHA_ACCELERATOR + bool "SHA Accelerator" + default n + ---help--- + Enable ESP32-C3 SHA accelerator support. + +config ESP32C3_BIGNUM_ACCELERATOR + bool "BIGNUM Accelerator" + default n + ---help--- + Enable ESP32-C3 BIGNUM accelerator support. + +config ESP32C3_RSA_ACCELERATOR + bool "RSA Accelerator" + default n + ---help--- + Enable ESP32-C3 RSA accelerator support. + +config ESP32C3_WIFI + bool "Wi-Fi" + default n + select NET + select ARCH_PHY_INTERRUPT + select ESP32C3_WIRELESS + ---help--- + Enable Wi-Fi support + +config ESP32C3_BLE + bool "BLE" + default n + select ESP32C3_WIRELESS + ---help--- + Enable BLE support + endmenu # ESP32-C3 Peripheral Support +menuconfig ESP32C3_WIFI_BT_COEXIST + bool "Wi-Fi and BT coexist" + default n + depends on ESP32C3_WIFI && ESP32C3_BLE + menu "I2C Configuration" depends on ESP32C3_I2C @@ -313,6 +394,44 @@ config ESP32C3_SPI_UDCS if ESP32C3_SPI2 +config ESP32C3_SPI2_SLAVE + bool "SPI2 Slave mode" + default n + depends on SPI_SLAVE + select ESP32C3_GPIO_IRQ + ---help--- + Configure SPI2 to operate in Slave mode. + +config ESP32C3_SPI2_DMA + bool "SPI2 use GDMA" + default n + depends on ESP32C3_DMA + ---help--- + Enable support for transfers using the GDMA engine. + +config ESP32C3_SPI2_DMADESC_NUM + int "SPI2 Master GDMA maximum number of descriptors" + default 2 + depends on ESP32C3_SPI2_DMA + ---help--- + Configure the maximum number of out-link/in-link descriptors to + be chained for a GDMA transfer. + +config ESP32C3_SPI2_DMATHRESHOLD + int "SPI2 Master GDMA threshold" + default 64 + depends on ESP32C3_SPI2_DMA + ---help--- + When SPI GDMA is enabled, GDMA transfers whose size are below the + defined threshold will be performed by polling logic. + +config ESP32C3_SPI2_SLAVE_BUFSIZE + int "SPI2 Slave buffer size" + default 2048 + depends on ESP32C3_SPI2_SLAVE + ---help--- + Configure the size of SPI2 Slave controller's internal buffers. + config ESP32C3_SPI2_CSPIN int "SPI2 CS Pin" default 10 @@ -350,17 +469,41 @@ config ESP32C3_UART0_RXPIN int "UART0 RX Pin" default 20 +config ESP32C3_UART0_RTSPIN + int "UART0 RTS Pin" + depends on SERIAL_IFLOWCONTROL + default 16 + range 0 21 + +config ESP32C3_UART0_CTSPIN + int "UART0 CTS Pin" + depends on SERIAL_OFLOWCONTROL + default 15 + range 0 21 + endif # ESP32C3_UART0 if ESP32C3_UART1 config ESP32C3_UART1_TXPIN int "UART1 TX Pin" - default 6 + default 8 config ESP32C3_UART1_RXPIN int "UART1 RX Pin" - default 7 + default 9 + +config ESP32C3_UART1_RTSPIN + int "UART1 RTS Pin" + depends on SERIAL_IFLOWCONTROL + default 1 + range 0 21 + +config ESP32C3_UART1_CTSPIN + int "UART1 CTS Pin" + depends on SERIAL_OFLOWCONTROL + default 2 + range 0 21 endif # ESP32C3_UART1 @@ -403,11 +546,129 @@ config ESP32C3_ONESHOT Enable a wrapper around the low level timer/counter functions to support one-shot timer. +config ESP32C3_FREERUN + bool "TIM free-running wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + endmenu # Timer/counter Configuration endif # ESP32C3_TIMER +menu "LEDC configuration" + depends on ESP32C3_LEDC + +menuconfig ESP32C3_LEDC_TIM0 + bool "Timer 0" + default n + +if ESP32C3_LEDC_TIM0 + +config ESP32C3_LEDC_TIM0_CHANNELS + int "Number of Timer 0 channels" + default 2 + +endif # ESP32C3_LEDC_TIM0 + +menuconfig ESP32C3_LEDC_TIM1 + bool "Timer 1" + default n + +if ESP32C3_LEDC_TIM1 + +config ESP32C3_LEDC_TIM1_CHANNELS + int "Number of Timer 1 channels" + default 2 + +endif # ESP32C3_LEDC_TIM1 + +menuconfig ESP32C3_LEDC_TIM2 + bool "Timer 2" + default n + +if ESP32C3_LEDC_TIM2 + +config ESP32C3_LEDC_TIM2_CHANNELS + int "Number of Timer 2 channels" + default 2 + +endif # ESP32C3_LEDC_TIM2 + +config ESP32C3_LEDC_CHANNEL0_PIN + int "Channel 0 pin" + default 2 + +config ESP32C3_LEDC_CHANNEL1_PIN + int "Channel 1 pin" + default 3 + +config ESP32C3_LEDC_CHANNEL2_PIN + int "Channel 2 pin" + default 4 + +config ESP32C3_LEDC_CHANNEL3_PIN + int "Channel 3 pin" + default 5 + +config ESP32C3_LEDC_CHANNEL4_PIN + int "Channel 4 pin" + default 6 + +config ESP32C3_LEDC_CHANNEL5_PIN + int "Channel 5 pin" + default 7 + +endmenu # LEDC configuration + +menu "ADC Configuration" + depends on ESP32C3_ADC + +if ESP32C3_ADC1 + +choice ESP32C3_ADC_VOL_RANGES + prompt "ADC1 voltage ranges" + default ESP32C3_ADC_VOL_750 + +config ESP32C3_ADC_VOL_750 + bool "0~750mV" + +config ESP32C3_ADC_VOL_1050 + bool "0~1050mV" + +config ESP32C3_ADC_VOL_1300 + bool "0~1300mV" + +config ESP32C3_ADC_VOL_2500 + bool "0~2500mV" + +endchoice + +config ESP32C3_ADC1_CHANNEL0 + bool "ADC1 channel 0" + default n + +config ESP32C3_ADC1_CHANNEL1 + bool "ADC1 channel 1" + default n + +config ESP32C3_ADC1_CHANNEL2 + bool "ADC1 channel 2" + default n + +config ESP32C3_ADC1_CHANNEL3 + bool "ADC1 channel 3" + default n + +config ESP32C3_ADC1_CHANNEL4 + bool "ADC1 channel 4" + default n + +endif # ESP32C3_ADC1 +endmenu # ADC Configuration + menu "Wi-Fi configuration" - depends on ESP32C3_WIRELESS + depends on ESP32C3_WIFI choice prompt "ESP32-C3 Wi-Fi mode" @@ -495,7 +756,63 @@ config ESP32C3_WIFI_STA_DISCONNECT_PM Select this option to enable power management for station when disconnected. Chip will do modem-sleep when RF module is not in use anymore. -endmenu # ESP32C3_WIRELESS +config EXAMPLE_WIFI_LISTEN_INTERVAL + int "Wi-Fi listen interval" + default 3 + ---help--- + Interval for station to listen to beacon from AP. The unit of listen interval is one beacon interval. + For example, if beacon interval is 100 ms and listen interval is 3, the interval for station to listen + to beacon is 300 ms. + +choice EXAMPLE_POWER_SAVE_MODE + prompt "Power save mode" + default EXAMPLE_POWER_SAVE_NONE + ---help--- + Power save mode for the ESP32-C3 to use. Modem sleep mode includes minimum and maximum power save modes. + In minimum power save mode, station wakes up every DTIM to receive beacon. Broadcast data will not be + lost because it is transmitted after DTIM. However, it can not save much more power if DTIM is short + for DTIM is determined by AP. + In maximum power save mode, station wakes up every listen interval to receive beacon. Broadcast data + may be lost because station may be in sleep state at DTIM time. If listen interval is longer, more power + is saved but broadcast data is more easy to lose. + + config EXAMPLE_POWER_SAVE_NONE + bool "none" + config EXAMPLE_POWER_SAVE_MIN_MODEM + bool "minimum modem" + config EXAMPLE_POWER_SAVE_MAX_MODEM + bool "maximum modem" +endchoice + +config ESP32C3_WIFI_RECONNECT + bool "Enable Wi-Fi to reconnect" + default n + ---help--- + Select this option to enable Wi-Fi to reconnect for station when disconnected. + +endmenu # Wi-Fi configuration + +menu "BLE Configuration" + depends on ESP32C3_BLE + +config ESP32C3_BLE_PKTBUF_NUM + int "BLE netcard packet buffer number per netcard" + default 16 + +config ESP32C3_BLE_TTY_NAME + string "BLE TTY device name" + default "/dev/ttyHCI0" + depends on UART_BTH4 + +config ESP32C3_BLE_TASK_STACK_SIZE + int "Controller task stack size" + default 4096 + +config ESP32C3_BLE_TASK_PRIORITY + int "Controller task priority" + default 110 + +endmenu # BLE Configuration menu "SPI Flash configuration" depends on ESP32C3_SPIFLASH @@ -535,4 +852,74 @@ config ESP32C3_PARTITION_MOUNT endmenu # ESP32C3_PARTITION +menu "GDMA Configuration" + depends on ESP32C3_DMA + +config ESP32C3_DMA_M2M_TEST + bool "Test GDMA M2M" + default n + +config ESP32C3_DMA_M2M_TEST_LOOPS + int "Test GDMA M2M loops" + default 256 + depends on ESP32C3_DMA_M2M_TEST + +config ESP32C3_DMA_M2M_TEST_BUFSIZE + int "Test GDMA M2M buffer size" + default 16000 + depends on ESP32C3_DMA_M2M_TEST + +endmenu # GDMA Configuration + +config ESP32C3_AUTO_SLEEP + bool "Auto-sleep" + default n + select PM + select ESP32C3_RT_TIMER + select ESP32C3_TIMER0 + select ESP32C3_TICKLESS + ---help--- + Enable ESP32-C3 Auto-sleep + +config ESP32C3_TICKLESS + bool "Enable ESP32-C3 tickless OS" + default n + select ARCH_HAVE_TICKLESS + select SCHED_TICKLESS + +menu "AES accelerator" + depends on ESP32C3_AES_ACCELERATOR + +config ESP32C3_AES_ACCELERATOR_TEST + bool "AES driver test" + default n + +endmenu # AES accelerator +menu "SHA accelerator" + depends on ESP32C3_SHA_ACCELERATOR + +config ESP32C3_SHA_ACCELERATOR_TEST + bool "SHA accelerator test" + default n + +endmenu # ESP32C3_SHA_ACCELERATOR + +menu "RSA Accelerate Configuration" + depends on ESP32C3_RSA_ACCELERATOR + +config ESP32C3_RSA_ACCELERATOR_TEST + bool "RSA driver test" + default n + +menu "BIGNUM" + depends on ESP32C3_BIGNUM_ACCELERATOR + +config ESP32C3_BIGNUM_ACCELERATOR_TEST + bool "BIGNUM driver test" + default n + +endmenu # ESP32C3_BIGNUM_ACCELERATOR + +endmenu # ESP32C3_RSA_ACCELERATOR + endif # ARCH_CHIP_ESP32C3 diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs index 30d217ff687..19a7621ae0d 100644 --- a/arch/risc-v/src/esp32c3/Make.defs +++ b/arch/risc-v/src/esp32c3/Make.defs @@ -46,10 +46,17 @@ endif # Specify our C code within this directory to be included CHIP_CSRCS = esp32c3_allocateheap.c esp32c3_start.c esp32c3_idle.c -CHIP_CSRCS += esp32c3_irq.c esp32c3_timerisr.c +CHIP_CSRCS += esp32c3_irq.c CHIP_CSRCS += esp32c3_clockconfig.c esp32c3_gpio.c CHIP_CSRCS += esp32c3_lowputc.c CHIP_CSRCS += esp32c3_systemreset.c esp32c3_resetcause.c +CHIP_CSRCS += esp32c3_uid.c + +ifeq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += esp32c3_tickless.c +else +CHIP_CSRCS += esp32c3_timerisr.c +endif ifeq ($(CONFIG_ESP32C3_UART),y) CHIP_CSRCS += esp32c3_serial.c @@ -65,6 +72,9 @@ endif ifeq ($(CONFIG_ESP32C3_SPI),y) CHIP_CSRCS += esp32c3_spi.c + ifeq ($(CONFIG_SPI_SLAVE),y) + CHIP_CSRCS += esp32c3_spi_slave.c + endif endif ifeq ($(CONFIG_ESP32C3_SPIFLASH),y) @@ -100,13 +110,76 @@ ifeq ($(CONFIG_ESP32C3_RT_TIMER),y) CHIP_CSRCS += esp32c3_rt_timer.c endif +ifeq ($(CONFIG_ESP32C3_BIGNUM_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_bignum.c +endif + +ifeq ($(CONFIG_ESP32C3_RSA_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_rsa.c +endif + +ifeq ($(CONFIG_ESP32C3_SHA_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_sha.c +endif + +ifeq ($(CONFIG_ESP32C3_FREERUN),y) +CHIP_CSRCS += esp32c3_freerun.c +endif + ifeq ($(CONFIG_ESP32C3_DISABLE_STDC_ATOMIC),) CHIP_CSRCS += esp32c3_std_atomic.c endif +ifeq ($(CONFIG_ESP32C3_DMA),y) +CHIP_CSRCS += esp32c3_dma.c +endif + +ifeq ($(CONFIG_PM),y) +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += esp32c3_pminitialize.c +endif +CHIP_CSRCS += esp32c3_pm.c +endif + +CHIP_CSRCS += esp32c3_rtc.c + +ifeq ($(CONFIG_ESP32C3_LEDC),y) +CHIP_CSRCS += esp32c3_ledc.c +endif + +ifeq ($(CONFIG_ESP32C3_ADC),y) +CHIP_CSRCS += esp32c3_adc.c +endif + +ifeq ($(CONFIG_ESP32C3_AES_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_aes.c +endif + +ifeq ($(CONFIG_ESP32C3_EFUSE),y) +CHIP_CSRCS += esp32c3_efuse.c +CHIP_CSRCS += esp32c3_efuse_table.c +CHIP_CSRCS += esp32c3_efuse_lowerhalf.c +endif + +ifeq ($(CONFIG_ARCH_HAVE_EXTRA_HEAPS),y) +CHIP_CSRCS += esp32c3_extraheaps.c +endif + +ifeq ($(CONFIG_ARCH_USE_TEXT_HEAP),y) +CHIP_CSRCS += esp32c3_textheap.c +endif + +ifeq ($(CONFIG_RTC_DRIVER),y) +CHIP_CSRCS += esp32c3_rtc_lowerhalf.c +endif + +ifeq ($(CONFIG_ESP32C3_RTC_HEAP),y) +CHIP_CSRCS += esp32c3_rtcheap.c +endif + ifeq ($(CONFIG_ESP32C3_WIRELESS),y) WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty -WIRELESS_DRV_ID = 2b53111 +WIRELESS_DRV_ID = df1f8c1 WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip WIRELESS_DRV_URL = https://github.com/espressif/esp-wireless-drivers-3rdparty/archive @@ -128,13 +201,22 @@ clean_context:: INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include) INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include$(DELIM)esp32c3) -CHIP_CSRCS += esp32c3_wlan.c esp32c3_wifi_utils.c esp32c3_wifi_adapter.c EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)libs$(DELIM)esp32c3 -EXTRA_LIBS += -lcore -lnet80211 -lpp -lsmartconfig -lcoexist -lespnow -lphy -lwpa_supplicant -lwapi +EXTRA_LIBS += -lphy # Due to some Wi-Fi related libraries, the option is need to avoid linking too much # unused functions. LDFLAGS += --gc-sections endif + +ifeq ($(CONFIG_ESP32C3_WIFI),y) +CHIP_CSRCS += esp32c3_wlan.c esp32c3_wifi_utils.c esp32c3_wifi_adapter.c +EXTRA_LIBS += -lcore -lnet80211 -lpp -lsmartconfig -lcoexist -lespnow -lwpa_supplicant -lwapi -lmesh +endif + +ifeq ($(CONFIG_ESP32C3_BLE),y) +CHIP_CSRCS += esp32c3_ble_adapter.c esp32c3_ble.c +EXTRA_LIBS += -lbtbb -lbtdm_app +endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_adc.c b/arch/risc-v/src/esp32c3/esp32c3_adc.c new file mode 100644 index 00000000000..bafda50d69c --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_adc.c @@ -0,0 +1,787 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_adc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "riscv_arch.h" + +#include "esp32c3.h" +#include "esp32c3_gpio.h" +#include "esp32c3_adc.h" + +#include "hardware/esp32c3_system.h" +#include "hardware/esp32c3_saradc.h" +#include "hardware/esp32c3_gpio_sigmap.h" +#include "hardware/regi2c_ctrl.h" +#include "hardware/regi2c_saradc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ADC calibration max count */ + +#define ADC_CAL_CNT_MAX (32) + +/* ADC calibration max value */ + +#define ADC_CAL_VAL_MAX (4096 - 1) + +/* ADC calibration sampling channel */ + +#define ADC_CAL_CHANNEL (0xf) + +/* ADC max value mask */ + +#define ADC_VAL_MASK (0xfff) + +/* ADC input voltage attenuation, this affects measuring range */ + +#define ADC_ATTEN_DB_0 (0) /* Vmax = 800 mV */ +#define ADC_ATTEN_DB_2_5 (1) /* Vmax = 1100 mV */ +#define ADC_ATTEN_DB_6 (2) /* Vmax = 1350 mV */ +#define ADC_ATTEN_DB_11 (3) /* Vmax = 2600 mV */ + +/* ADC attenuation */ + +#if defined(CONFIG_ESP32C3_ADC_VOL_750) +# define ADC_ATTEN_DEF ADC_ATTEN_DB_0 +# define ADC_VOL_VAL (750) +#elif defined(CONFIG_ESP32C3_ADC_VOL_1050) +# define ADC_ATTEN_DEF ADC_ATTEN_DB_2_5 +# define ADC_VOL_VAL (1050) +#elif defined(CONFIG_ESP32C3_ADC_VOL_1300) +# define ADC_ATTEN_DEF ADC_ATTEN_DB_6 +# define ADC_VOL_VAL (1300) +#elif defined(CONFIG_ESP32C3_ADC_VOL_2500) +# define ADC_ATTEN_DEF ADC_ATTEN_DB_11 +# define ADC_VOL_VAL (2500) +#endif + +#define ADC_WORK_DELAY (1) + +#ifndef MIN +# define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#ifndef MAX +# define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* ADC Private Data */ + +struct adc_chan_s +{ + uint32_t ref; /* Reference count */ + + const uint8_t channel; /* Channel number */ + const uint8_t pin; /* GPIO pin number */ + + const struct adc_callback_s *cb; /* Upper driver callback */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int adc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback); +static void adc_reset(struct adc_dev_s *dev); +static int adc_setup(struct adc_dev_s *dev); +static void adc_shutdown(struct adc_dev_s *dev); +static void adc_rxint(struct adc_dev_s *dev, bool enable); +static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC interface operations */ + +static const struct adc_ops_s g_adcops = +{ + .ao_bind = adc_bind, + .ao_reset = adc_reset, + .ao_setup = adc_setup, + .ao_shutdown = adc_shutdown, + .ao_rxint = adc_rxint, + .ao_ioctl = adc_ioctl, +}; + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL0 +static struct adc_chan_s g_adc1_chan0 = +{ + .channel = 0, + .pin = 0 +}; + +static struct adc_dev_s g_adc1_chan0_dev = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adc1_chan0 +}; +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL1 +static struct adc_chan_s g_adc1_chan1 = +{ + .channel = 1, + .pin = 1 +}; + +static struct adc_dev_s g_adc1_chan1_dev = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adc1_chan1, +}; +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL2 +static struct adc_chan_s g_adc1_chan2 = +{ + .channel = 2, + .pin = 2 +}; + +static struct adc_dev_s g_adc1_chan2_dev = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adc1_chan2, +}; +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL3 +static struct adc_chan_s g_adc1_chan3 = +{ + .channel = 3, + .pin = 3 +}; + +static struct adc_dev_s g_adc1_chan3_dev = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adc1_chan3, +}; +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL4 +static struct adc_chan_s g_adc1_chan4 = +{ + .channel = 4, + .pin = 4 +}; + +static struct adc_dev_s g_adc1_chan4_dev = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adc1_chan4, +}; +#endif + +/* ADC calibration mark */ + +static bool g_calibrated; + +/* ADC clock reference */ + +static uint32_t g_clk_ref; + +static sem_t g_sem_excl = SEM_INITIALIZER(1); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adc_enable_clk + * + * Description: + * Enable ADC clock. + * + * Input Parameters: + * NOne + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_enable_clk(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (!g_clk_ref) + { + setbits(SYSTEM_APB_SARADC_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG); + resetbits(SYSTEM_APB_SARADC_RST, SYSTEM_PERIP_RST_EN0_REG); + } + + g_clk_ref++; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: adc_disable_clk + * + * Description: + * Disable ADC clock. + * + * Input Parameters: + * NOne + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_disable_clk(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + g_clk_ref--; + + if (!g_clk_ref) + { + setbits(SYSTEM_APB_SARADC_RST, SYSTEM_PERIP_RST_EN0_REG); + resetbits(SYSTEM_APB_SARADC_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: adc_set_calibration + * + * Description: + * Set calibration parameter to ADC hardware. + * + * Input Parameters: + * data - Calibration parameter + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_set_calibration(uint16_t data) +{ + uint8_t h_data = data >> 8; + uint8_t l_data = data & 0xff; + + rom_i2c_writereg_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_INITVAL_H, + I2C_ADC1_INITVAL_H_MSB, + I2C_ADC1_INITVAL_H_LSB, h_data); + + rom_i2c_writereg_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_INITVAL_L, + I2C_ADC1_INITVAL_L_MSB, + I2C_ADC1_INITVAL_L_LSB, l_data); +} + +/**************************************************************************** + * Name: adc_samplecfg + * + * Description: + * Set ADC sampling with given channel. + * + * Input Parameters: + * channel - Sampling channel number + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void adc_samplecfg(int channel) +{ + uint32_t regval; + + /* Enable ADC1, its sampling channel and attenuation */ + + regval = getreg32(APB_SARADC_ONETIME_SAMPLE_REG); + regval &= ~(APB_SARADC1_ONETIME_SAMPLE | APB_SARADC2_ONETIME_SAMPLE | + APB_SARADC_ONETIME_CHANNEL_M | APB_SARADC_ONETIME_ATTEN_M); + regval |= (channel << APB_SARADC_ONETIME_CHANNEL_S) | + (ADC_ATTEN_DEF << APB_SARADC_ONETIME_ATTEN_S) | + APB_SARADC1_ONETIME_SAMPLE; + putreg32(regval, APB_SARADC_ONETIME_SAMPLE_REG); +} + +/**************************************************************************** + * Name: adc_read + * + * Description: + * Start ADC sampling and read ADC value. + * + * Input Parameters: + * None + * + * Returned Value: + * Read ADC value. + * + ****************************************************************************/ + +static uint16_t adc_read(void) +{ + uint16_t adc; + uint32_t regval; + + /* Trigger ADC sampling */ + + setbits(APB_SARADC_ONETIME_START, APB_SARADC_ONETIME_SAMPLE_REG); + + /* Wait until ADC1 sampling is done */ + + do + { + regval = getreg32(APB_SARADC_INT_ST_REG); + } + while (!(regval & APB_SARADC_ADC1_DONE_INT_ST)); + + adc = getreg32(APB_SARADC_1_DATA_STATUS_REG) & ADC_VAL_MASK; + + /* Disable ADC sampling */ + + resetbits(APB_SARADC_ONETIME_START, APB_SARADC_ONETIME_SAMPLE_REG); + + /* Clear ADC1 sampling done interrupt bit */ + + setbits(APB_SARADC_ADC1_DONE_INT_CLR, APB_SARADC_INT_CLR_REG); + + return adc; +} + +/**************************************************************************** + * Name: adc_calibrate + * + * Description: + * ADC calibration. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_calibrate(void) +{ + uint16_t cali_val; + uint16_t adc; + uint16_t adc_max = 0; + uint16_t adc_min = UINT16_MAX; + uint32_t adc_sum = 0; + + /* Enable Vdef */ + + rom_i2c_writereg_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_DEF, I2C_ADC1_DEF_MSB, + I2C_ADC1_DEF_LSB, 1); + + /* Start sampling */ + + adc_samplecfg(ADC_CAL_CHANNEL); + + /* Enable internal connect GND (for calibration). */ + + rom_i2c_writereg_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_ENCAL_GND, I2C_ADC1_ENCAL_GND_MSB, + I2C_ADC1_ENCAL_GND_LSB, 1); + + for (int i = 1; i < ADC_CAL_CNT_MAX ; i++) + { + adc_set_calibration(0); + adc = adc_read(); + + adc_sum += adc; + adc_max = MAX(adc, adc_max); + adc_min = MIN(adc, adc_min); + } + + cali_val = (adc_sum - adc_max - adc_min) / (ADC_CAL_CNT_MAX - 2); + + /* Disable internal connect GND (for calibration). */ + + rom_i2c_writereg_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_ENCAL_GND, + I2C_ADC1_ENCAL_GND_MSB, + I2C_ADC1_ENCAL_GND_LSB, 0); + + ainfo("calibration value: %" PRIu16 "\n", cali_val); + + /* Set final calibration parameters */ + + adc_set_calibration(cali_val); +} + +/**************************************************************************** + * Name: adc_read_work + * + * Description: + * Read ADC value and pass it to up. + * + * Input Parameters: + * dev - ADC device pointer + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_read_work(struct adc_dev_s *dev) +{ + int ret; + uint16_t adc; + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ret = sem_wait(&g_sem_excl); + if (ret < 0) + { + aerr("Failed to wait sem ret=%d\n", ret); + return ; + } + + adc_samplecfg(priv->channel); + adc = adc_read(); + + priv->cb->au_receive(dev, priv->channel, adc); + + ainfo("channel: %" PRIu8 ", voltage: %" PRIu32 " mV\n", priv->channel, + (uint32_t)adc * ADC_VOL_VAL / ADC_CAL_VAL_MAX); + + sem_post(&g_sem_excl); +} + +/**************************************************************************** + * Name: adc_bind + * + * Description: + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. + * + ****************************************************************************/ + +static int adc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback) +{ + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + DEBUGASSERT(priv != NULL); + + ainfo("channel: %" PRIu8 "\n", priv->channel); + + priv->cb = callback; + + return OK; +} + +/**************************************************************************** + * Name: adc_reset + * + * Description: + * Reset the ADC device. Called early to initialize the hardware. + * This is called, before adc_setup() and on error conditions. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_reset(struct adc_dev_s *dev) +{ + irqstate_t flags; + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ainfo("channel: %" PRIu8 "\n", priv->channel); + + flags = enter_critical_section(); + + /* Do nothing if ADC instance is currently in use */ + + if (priv->ref > 0) + { + goto out; + } + + /* Reset ADC hardware */ + + adc_enable_clk(); + + adc_disable_clk(); + +out: + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: adc_setup + * + * Description: + * Configure the ADC. This method is called the first time that the ADC + * device is opened. This will occur when the port is first opened. + * This setup includes configuring. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_setup(struct adc_dev_s *dev) +{ + int ret; + uint32_t regval; + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ainfo("channel: %" PRIu8 "\n", priv->channel); + + /* Do nothing when the ADC device is already set up */ + + if (priv->ref > 0) + { + return OK; + } + + /* Enable ADC clock */ + + adc_enable_clk(); + + /* Disable GPIO input and output */ + + ainfo("pin: %" PRIu8 "\n", priv->pin); + + esp32c3_configgpio(priv->pin, INPUT); + + /* Config ADC hardware */ + + regval = APB_SARADC_SAR_CLK_GATED_M | APB_SARADC_XPD_SAR_FORCE_M; + setbits(regval, APB_SARADC_CTRL_REG); + + regval = APB_SARADC_ADC1_DONE_INT_ENA; + setbits(regval, APB_SARADC_INT_ENA_REG); + + /* Start calibration only once */ + + ret = sem_wait(&g_sem_excl); + if (ret < 0) + { + adc_disable_clk(); + aerr("Failed to wait sem ret=%d\n", ret); + return ret; + } + + if (!g_calibrated) + { + adc_calibrate(); + g_calibrated = true; + } + + sem_post(&g_sem_excl); + + /* The ADC device is ready */ + + priv->ref++; + + return OK; +} + +/**************************************************************************** + * Name: adc_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_rxint(struct adc_dev_s *dev, bool enable) +{ +} + +/**************************************************************************** + * Name: adc_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) +{ + int ret; + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ainfo("channel: %" PRIu8 " cmd=%d\n", priv->channel, cmd); + + switch (cmd) + { + case ANIOC_TRIGGER: + + /* Start sampling and read ADC value here */ + + adc_read_work(dev); + ret = OK; + break; + + default: + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: adc_shutdown + * + * Description: + * Disable the ADC. This method is called when the ADC device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_shutdown(struct adc_dev_s *dev) +{ + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ainfo("channel: %" PRIu8 "\n", priv->channel); + + /* Decrement count only when ADC device is in use */ + + if (priv->ref > 0) + { + priv->ref--; + + /* Shutdown the ADC device only when not in use */ + + if (!priv->ref) + { + adc_rxint(dev, false); + + /* Disable ADC clock */ + + adc_disable_clk(); + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_adc_init + * + * Description: + * Initialize the ADC. + * + * Input Parameters: + * channel - ADC channel number + * + * Returned Value: + * ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s *esp32c3_adc_init(int channel) +{ + struct adc_dev_s *dev; + + ainfo("ADC channel: %" PRIu8 "\n", channel); + + switch (channel) + { +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL0 + case 0: + dev = &g_adc1_chan0_dev; + break; +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL1 + case 1: + dev = &g_adc1_chan1_dev; + break; +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL2 + case 2: + dev = &g_adc1_chan2_dev; + break; +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL3 + case 3: + dev = &g_adc1_chan3_dev; + break; +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL4 + case 4: + dev = &g_adc1_chan4_dev; + break; +#endif + + default: + { + aerr("ERROR: No ADC interface defined\n"); + return NULL; + } + } + + return dev; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_adc.h b/arch/risc-v/src/esp32c3/esp32c3_adc.h new file mode 100644 index 00000000000..f79bf3f025d --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_adc.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_adc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ADC_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: esp32c3_adc_init + * + * Description: + * Initialize the ADC. + * + * Input Parameters: + * channel - ADC channel number + * + * Returned Value: + * ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s *esp32c3_adc_init(int channel); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ADC_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_aes.c b/arch/risc-v/src/esp32c3/esp32c3_aes.c new file mode 100644 index 00000000000..8353df579e5 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_aes.c @@ -0,0 +1,1128 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_aes.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "riscv_arch.h" + +#include "esp32c3.h" +#include "esp32c3_aes.h" + +#include "hardware/esp32c3_aes.h" +#include "hardware/esp32c3_system.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AES_BLK_SIZE (16) + +#define AES_MODE_DECRYPT (BIT(2)) + +#define AES_IDLE_STATE (0) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_aes_inited; +static sem_t g_aes_sem = SEM_INITIALIZER(1); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: aes_hw_setkey + * + * Description: + * Set AES hardware key and encryption/decryption mode + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void aes_hw_setkey(struct esp32c3_aes_s *aes, bool encrypt) +{ + int i; + uint32_t cryptbits = encrypt ? 0 : AES_MODE_DECRYPT; + uint32_t keybits = (aes->keybits / 64) - 2; + uint32_t keywords = aes->keybits / 32; + + putreg32(cryptbits | keybits, AES_MODE_REG); + + for (i = 0; i < keywords; ++i) + { + putreg32(aes->key[i], AES_KEY_0_REG + i * 4); + } +} + +/**************************************************************************** + * Name: aes_hw_cypher + * + * Description: + * Process AES hardware encryption/decryption. + * + * Input Parameters: + * s - Input data pointer + * d - Output buffer pointer + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void aes_hw_cypher(const uint8_t *s, uint8_t *d) +{ + uint32_t buffer[AES_BLK_SIZE / 4]; + + memcpy(buffer, s, AES_BLK_SIZE); + + putreg32(buffer[0], AES_TEXT_IN_0_REG + 0); + putreg32(buffer[1], AES_TEXT_IN_0_REG + 4); + putreg32(buffer[2], AES_TEXT_IN_0_REG + 8); + putreg32(buffer[3], AES_TEXT_IN_0_REG + 12); + + putreg32(AES_TRIGGER_M, AES_TRIGGER_REG); + + while (getreg32(AES_STATE_REG) != AES_IDLE_STATE) + { + } + + buffer[0] = getreg32(AES_TEXT_OUT_0_REG + 0); + buffer[1] = getreg32(AES_TEXT_OUT_0_REG + 4); + buffer[2] = getreg32(AES_TEXT_OUT_0_REG + 8); + buffer[3] = getreg32(AES_TEXT_OUT_0_REG + 12); + + memcpy(d, buffer, AES_BLK_SIZE); +} + +/**************************************************************************** + * Name: gf128mul_x_ble + * + * Description: + * GF(2^128) multiplication function. + * + * Input Parameters: + * d - Result buffer + * s - Input data buffer + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void gf128mul_x_ble(uint8_t *d, const uint8_t *s) +{ + uint64_t a, b, ra, rb; + + memcpy(&a, s, 8); + memcpy(&b, s + 8, 8); + + ra = (a << 1) ^ (0x0087 >> (8 - ((b >> 63) << 3))); + rb = (a >> 63) | (b << 1); + + memcpy(d, &ra, 8); + memcpy(d + 8, &rb, 8); +} + +/**************************************************************************** + * Name: esp32c3_aes_ecb_cypher + * + * Description: + * Process AES ECB encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_ecb_cypher(struct esp32c3_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size) +{ + int ret; + uint32_t i; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && input && output); + DEBUGASSERT(size && ((size % AES_BLK_SIZE) == 0)); + + ret = nxsem_wait(&g_aes_sem); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, encrypt); + + for (i = 0; i < size; i += AES_BLK_SIZE) + { + aes_hw_cypher(s, d); + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + ret = nxsem_post(&g_aes_sem); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_aes_cbc_cypher + * + * Description: + * Process AES CBC encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * ivptr - Initialization vector pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_cbc_cypher(struct esp32c3_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + uint8_t *iv = (uint8_t *)ivptr; + + DEBUGASSERT(aes && input && output && ivptr); + DEBUGASSERT(size && ((size % AES_BLK_SIZE) == 0)); + + ret = nxsem_wait(&g_aes_sem); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, encrypt); + + for (i = 0; i < size; i += AES_BLK_SIZE) + { + if (encrypt) + { + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = s[j] ^ iv[j]; + } + + aes_hw_cypher(d, d); + + memcpy(iv, d, AES_BLK_SIZE); + } + else + { + aes_hw_cypher(s, d); + + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = d[j] ^ iv[j]; + } + + memcpy(iv, s, AES_BLK_SIZE); + } + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + ret = nxsem_post(&g_aes_sem); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_aes_ctr_cypher + * + * Description: + * Process AES CTR encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * offptr - Offset buffer pointer + * cntptr - Counter buffer pointer + * cacheptr - Counter calculation buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_ctr_cypher(struct esp32c3_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + uint32_t n; + uint8_t *cnt = (uint8_t *)cntptr; + uint8_t *cache = (uint8_t *)cacheptr; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && offptr && cntptr && cacheptr && input && output); + DEBUGASSERT(size); + + ret = nxsem_wait(&g_aes_sem); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, true); + + n = *offptr; + for (i = 0; i < size; i++) + { + if (n == 0) + { + aes_hw_cypher(cnt, cache); + for (j = AES_BLK_SIZE - 1; j > 0; j--) + { + cnt[j]++; + if (cnt[j] != 0) + { + break; + } + } + } + + d[i] = s[i] ^ cache[n]; + + n = (n + 1) & (AES_BLK_SIZE - 1); + } + + *offptr = n; + + ret = nxsem_post(&g_aes_sem); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_aes_xts_cypher + * + * Description: + * Process AES XTS encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * unitptr - Unit data buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_xts_cypher(struct esp32c3_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + uint32_t blks; + uint32_t rst; + uint8_t *t; + uint8_t *prev_output; + uint8_t tweak[AES_BLK_SIZE]; + uint8_t prev_tweak[AES_BLK_SIZE]; + uint8_t tmp[AES_BLK_SIZE]; + uint8_t *unit = (uint8_t *)unitptr; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && unitptr && input && output); + + /* NIST SP 80-38E disallows data units larger than 2**20 blocks. */ + + DEBUGASSERT((size >= AES_BLK_SIZE) && + (size <= ((1 << 20) * AES_BLK_SIZE))); + + ret = nxsem_wait(&g_aes_sem); + if (ret < 0) + { + return ret; + } + + blks = size / AES_BLK_SIZE; + rst = size % AES_BLK_SIZE; + + aes_hw_setkey(&aes->tweak, true); + aes_hw_cypher(unit, tweak); + + for (i = 0; i < blks; i++) + { + if (rst && (encrypt == false) && (blks == 1)) + { + memcpy(prev_tweak, tweak, AES_BLK_SIZE); + gf128mul_x_ble(tweak, tweak); + } + + for (j = 0; j < AES_BLK_SIZE; j++) + { + tmp[j] = s[j] ^ tweak[j]; + } + + aes_hw_setkey(&aes->crypt, encrypt); + aes_hw_cypher(tmp, tmp); + + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = tmp[j] ^ tweak[j]; + } + + gf128mul_x_ble(tweak, tweak); + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + if (rst) + { + t = encrypt ? tweak : prev_tweak; + prev_output = d - AES_BLK_SIZE; + + for (i = 0; i < rst; i++) + { + d[i] = prev_output[i]; + tmp[i] = s[i] ^ t[i]; + } + + for (; i < AES_BLK_SIZE; i++) + { + tmp[i] = prev_output[i] ^ t[i]; + } + + aes_hw_setkey(&aes->crypt, encrypt); + aes_hw_cypher(tmp, tmp); + + for (i = 0; i < AES_BLK_SIZE; i++) + { + prev_output[i] = tmp[i] ^ t[i]; + } + } + + ret = nxsem_post(&g_aes_sem); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_aes_setkey + * + * Description: + * Configurate AES key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_setkey(struct esp32c3_aes_s *aes, const void *keyptr, + uint16_t keybits) +{ + DEBUGASSERT(aes && keyptr); + + if ((keybits != 128) && (keybits != 256)) + { + return -EINVAL; + } + + aes->keybits = keybits; + memcpy(aes->key, keyptr, keybits / 8); + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_aes_xts_setkey + * + * Description: + * Configurate AES XTS key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_xts_setkey(struct esp32c3_aes_xts_s *aes, const void *keyptr, + uint16_t keybits) +{ + const uint8_t *key = (const uint8_t *)keyptr; + uint16_t half_keybits = keybits / 2; + + DEBUGASSERT(aes && keyptr); + + if ((keybits != 256) && (keybits != 512)) + { + return -EINVAL; + } + + aes->crypt.keybits = half_keybits; + memcpy(aes->crypt.key, key, half_keybits / 8); + + aes->tweak.keybits = half_keybits; + memcpy(aes->tweak.key, key + half_keybits / 8, half_keybits / 8); + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_aes_init + * + * Description: + * Initialize ESP32-C3 AES hardware. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_init(void) +{ + if (!g_aes_inited) + { + setbits(SYSTEM_CRYPTO_AES_CLK_EN, SYSTEM_PERIP_CLK_EN1_REG); + resetbits(SYSTEM_CRYPTO_AES_RST, SYSTEM_PERIP_RST_EN1_REG); + g_aes_inited = true; + } + + return OK; +} + +/**************************************************************************** + * Name: aes_cypher + ****************************************************************************/ + +#ifdef CONFIG_CRYPTO_AES + +int aes_cypher(FAR void *out, FAR const void *in, uint32_t size, + FAR const void *iv, FAR const void *key, uint32_t keysize, + int mode, int encrypt) +{ + int ret; + uint8_t iv_buf[AES_BLK_SIZE]; + uint8_t cache_buf[AES_BLK_SIZE]; + uint32_t nc_off; + struct esp32c3_aes_s aes; + + if ((size & (AES_BLK_SIZE - 1)) != 0) + { + return -EINVAL; + } + + if (keysize != 16) + { + return -EINVAL; + } + + if ((mode != AES_MODE_ECB) && + (mode != AES_MODE_CBC) && + (mode != AES_MODE_CTR)) + { + return -EINVAL; + } + + ret = esp32c3_aes_init(); + if (ret < 0) + { + return ret; + } + + ret = esp32c3_aes_setkey(&aes, key, keysize * 8); + if (ret < 0) + { + return ret; + } + + switch (mode) + { + case AES_MODE_ECB: + ret = esp32c3_aes_ecb_cypher(&aes, encrypt, in, out, size); + break; + case AES_MODE_CBC: + memcpy(iv_buf, iv, AES_BLK_SIZE); + ret = esp32c3_aes_cbc_cypher(&aes, encrypt, iv_buf, in, out, size); + break; + case AES_MODE_CTR: + nc_off = 0; + memcpy(iv_buf, iv, AES_BLK_SIZE); + ret = esp32c3_aes_ctr_cypher(&aes, &nc_off, iv_buf, cache_buf, + in, out, size); + default : + ret = -EINVAL; + break; + } + + return ret; +} + +#endif + +/**************************************************************************** + * Test Functions + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_AES_ACCELERATOR_TEST + +/**************************************************************************** + * Name: esp32c3_aes_ecb_test + ****************************************************************************/ + +static bool esp32c3_aes_ecb_test(void) +{ + int ret; + int i; + int keybits; + uint8_t encrypt_buf[16]; + uint8_t decrypt_buf[16]; + struct esp32c3_aes_s aes; + const int size = 16; + + const uint32_t input[8] = + { + 0x740fdb34, 0x002defca, 0xb042437b, 0xc2f42cf9, + 0xc64444be, 0x32365bc1, 0xb613cfa2, 0x15ce0d23 + }; + + const uint32_t key[16] = + { + 0x8ffdc2c5, 0x14d6c69d, 0x9cb7608f, 0x899b2472, + 0xbf9e4372, 0x855290d0, 0xc62753da, 0xdeedeab7 + }; + + const uint32_t result[3][4] = + { + /* keybits = 128 */ + + { + 0xc810df2a, 0x8ae67e6e, 0x50c5e32c, 0xd535f3e4 + }, + + /* keybits = 256 */ + + { + 0xa0714c2b, 0x356adb1f, 0xe905c243, 0x35195a7c + } + }; + + esp32c3_aes_init(); + + for (i = 0; i < 2; i++) + { + keybits = i * 128 + 128; + + ret = esp32c3_aes_setkey(&aes, key, keybits); + if (ret < 0) + { + return false; + } + + ret = esp32c3_aes_ecb_cypher(&aes, 1, input, encrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(encrypt_buf, result[i], size); + if (ret) + { + return false; + } + + ret = esp32c3_aes_ecb_cypher(&aes, 0, encrypt_buf, decrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; + } + + syslog(LOG_INFO, "ESP32-C3 AES ECB key=%d bits test: PASS\n", keybits); + } + + return true; +} + +/**************************************************************************** + * Name: esp32c3_aes_cbc_test + ****************************************************************************/ + +static bool esp32c3_aes_cbc_test(void) +{ + int ret; + int i; + int keybits; + uint8_t encrypt_buf[32]; + uint8_t decrypt_buf[32]; + uint8_t iv_buf[16]; + struct esp32c3_aes_s aes; + const int size = 32; + + const uint32_t input[8] = + { + 0x740fdb34, 0x002defca, 0xb042437b, 0xc2f42cf9, + 0xc64444be, 0x32365bc1, 0xb613cfa2, 0x15ce0d23 + }; + + const uint32_t key[16] = + { + 0x8ffdc2c5, 0x14d6c69d, 0x9cb7608f, 0x899b2472, + 0xbf9e4372, 0x855290d0, 0xc62753da, 0xdeedeab7 + }; + + const uint32_t iv[4] = + { + 0xf53a50f2, 0x8aaf711d, 0x953bbbfa, 0x228d53cb + }; + + const uint32_t result[3][8] = + { + /* keybits = 128 */ + + { + 0x04e27d12, 0x1a91e508, 0x01092431, 0x9d572184, + 0xa39979e1, 0x5543e1bc, 0x7173b71d, 0x4e3be064 + }, + + /* keybits = 256 */ + + { + 0x6f36b8fe, 0x33bc1f37, 0x24fe659c, 0x0370def0, + 0xb9a852f8, 0x64a79ae2, 0xd59f5045, 0x648a0f44 + } + }; + + for (i = 0; i < 2; i++) + { + keybits = i * 128 + 128; + + ret = esp32c3_aes_setkey(&aes, key, keybits); + if (ret < 0) + { + return false; + } + + memcpy(iv_buf, iv, 16); + ret = esp32c3_aes_cbc_cypher(&aes, 1, iv_buf, input, encrypt_buf, + size); + if (ret < 0) + { + return false; + } + + ret = memcmp(encrypt_buf, result[i], size); + if (ret) + { + return false; + } + + memcpy(iv_buf, iv, 16); + ret = esp32c3_aes_cbc_cypher(&aes, 0, iv_buf, encrypt_buf, + decrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; + } + + syslog(LOG_INFO, "ESP32-C3 AES CBC key=%d bits test: PASS\n", keybits); + } + + return true; +} + +/**************************************************************************** + * Name: esp32c3_aes_ctr_test + ****************************************************************************/ + +static bool esp32c3_aes_ctr_test(void) +{ + int ret; + int i; + int keybits; + uint8_t encrypt_buf[32]; + uint8_t decrypt_buf[32]; + uint8_t cnt_buf[16]; + uint8_t cache_buf[16]; + uint32_t nc_off; + struct esp32c3_aes_s aes; + const int size = 32; + + const uint32_t input[8] = + { + 0x740fdb34, 0x002defca, 0xb042437b, 0xc2f42cf9, + 0xc64444be, 0x32365bc1, 0xb613cfa2, 0x15ce0d23 + }; + + const uint32_t key[16] = + { + 0x8ffdc2c5, 0x14d6c69d, 0x9cb7608f, 0x899b2472, + 0xbf9e4372, 0x855290d0, 0xc62753da, 0xdeedeab7 + }; + + const uint32_t cnt[4] = + { + 0xf53a50f2, 0x8aaf711d, 0x953bbbfa, 0x228d53cb + }; + + const uint32_t result[3][8] = + { + /* keybits = 128 */ + + { + 0x5f922338, 0x5aff403d, 0x45fede3f, 0x616568c6, + 0x3cd0ffc7, 0xa26cb704, 0x0aaa8b6a, 0x1d0b5e1c + }, + + /* keybits = 256 */ + + { + 0x70af4473, 0x597d2126, 0xd598ed09, 0x3fea540c, + 0xfb5c743c, 0x0c1a39ca, 0xcbcf2d17, 0x341a7a0c + } + }; + + for (i = 0; i < 2; i++) + { + keybits = i * 128 + 128; + + ret = esp32c3_aes_setkey(&aes, key, keybits); + if (ret < 0) + { + return false; + } + + nc_off = 0; + memcpy(cnt_buf, cnt, 16); + ret = esp32c3_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, + input, encrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(encrypt_buf, result[i], size); + if (ret) + { + return false; + } + + nc_off = 0; + memcpy(cnt_buf, cnt, 16); + ret = esp32c3_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, + encrypt_buf, decrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; + } + + syslog(LOG_INFO, "ESP32-C3 AES CTR key=%d bits test: PASS\n", keybits); + } + + return true; +} + +/**************************************************************************** + * Name: esp32c3_aes_xts_test + ****************************************************************************/ + +static bool esp32c3_aes_xts_test(void) +{ + int ret; + int i; + int keybits; + uint8_t encrypt_buf[32]; + uint8_t decrypt_buf[32]; + uint8_t unit_buf[16]; + struct esp32c3_aes_xts_s aes; + int size; + + const uint32_t input[8] = + { + 0x740fdb34, 0x002defca, 0xb042437b, 0xc2f42cf9, + 0xc64444be, 0x32365bc1, 0xb613cfa2, 0x15ce0d23 + }; + + const uint32_t key[16] = + { + 0x8ffdc2c5, 0x14d6c69d, 0x9cb7608f, 0x899b2472, + 0xbf9e4372, 0x855290d0, 0xc62753da, 0xdeedeab7, + 0x7ac6c53b, 0xc94f0b81, 0xdd673fc9, 0x8c1b71a6, + 0x1f99b728, 0x5e7af2eb, 0xcc7274a3, 0xf0005b23 + }; + + const uint32_t unit[4] = + { + 0xf53a50f2, 0x8aaf711d, 0x953bbbfa, 0x228d53cb + }; + + const uint32_t result_in32[2][8] = + { + /* keybits = 256 */ + + { + 0xf70e05fd, 0x2791be41, 0x926ec006, 0xc76068f4, + 0x01fd0843, 0xdf5e576a, 0xa4b1833d, 0x90502608 + }, + + /* keybits = 512 */ + + { + 0x164b4185, 0x4cb1cce7, 0xf285e523, 0x06a5923a, + 0xae4fcb7b, 0x59ce9dc6, 0xed64546f, 0x5889cb17 + } + }; + + const uint32_t result_in30[2][8] = + { + /* keybits = 256 */ + + { + 0x26991fb6, 0x72e4a7bc, 0x97041d61, 0x9ec889af, + 0xf70e05fd, 0x2791be41, 0x926ec006, 0x000068f4 + }, + + /* keybits = 512 */ + + { + 0x4b42dd86, 0xeee792c0, 0x1516ff95, 0x1f5fd9e6, + 0x164b4185, 0x4cb1cce7, 0xf285e523, 0x0000923a + } + }; + + for (i = 0; i < 2; i++) + { + keybits = i * 256 + 256; + + ret = esp32c3_aes_xts_setkey(&aes, key, keybits); + if (ret < 0) + { + return false; + } + + /* Encrypt/Decrypt 32 bytes */ + + size = 32; + + memcpy(unit_buf, unit, 16); + ret = esp32c3_aes_xts_cypher(&aes, true, unit_buf, input, + encrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(encrypt_buf, result_in32[i], size); + if (ret) + { + return false; + } + + memcpy(unit_buf, unit, 16); + ret = esp32c3_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, + decrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; + } + + /* Encrypt/Decrypt 30 bytes */ + + size = 30; + + memcpy(unit_buf, unit, 16); + ret = esp32c3_aes_xts_cypher(&aes, true, unit_buf, input, + encrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(encrypt_buf, result_in30[i], size); + if (ret) + { + return false; + } + + memcpy(unit_buf, unit, 16); + ret = esp32c3_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, + decrypt_buf, size); + if (ret < 0) + { + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; + } + + syslog(LOG_INFO, "ESP32-C3 AES XTS key=%d bits test: PASS\n", keybits); + } + + return true; +} + +/**************************************************************************** + * Name: esp32c3_aes_main + ****************************************************************************/ + +int esp32c3_aes_main(int argc, char *argv[]) +{ + bool success; + + syslog(LOG_INFO, "----- BEGIN TEST -----\n"); + + esp32c3_aes_init(); + + success = esp32c3_aes_ecb_test(); + if (!success) + { + goto test_end; + } + + success = esp32c3_aes_cbc_test(); + if (!success) + { + goto test_end; + } + + success = esp32c3_aes_ctr_test(); + if (!success) + { + goto test_end; + } + + success = esp32c3_aes_xts_test(); + if (!success) + { + goto test_end; + } + +test_end: + syslog(LOG_INFO, "----- END TEST -----\n"); + + syslog(LOG_INFO, "\n"); + + syslog(LOG_INFO, "----- RESULT: %s -----\n", + success ? "SUCCESS" : "FAILED"); + + return 0; +} + +#endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_aes.h b/arch/risc-v/src/esp32c3/esp32c3_aes.h new file mode 100644 index 00000000000..6ed25f17c07 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_aes.h @@ -0,0 +1,217 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_AES_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_AES_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* AES private description */ + +struct esp32c3_aes_s +{ + uint32_t key[8]; /* Key data value */ + uint16_t keybits; /* Key data bits */ +}; + +/* AES XTS private description */ + +struct esp32c3_aes_xts_s +{ + struct esp32c3_aes_s crypt; /* AES block encryption/decryption */ + struct esp32c3_aes_s tweak; /* AES tweak encryption/decryption */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_aes_ecb_cypher + * + * Description: + * Process AES ECB encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_ecb_cypher(struct esp32c3_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size); + +/**************************************************************************** + * Name: esp32c3_aes_cbc_cypher + * + * Description: + * Process AES CBC encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * ivptr - Initialization vector pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_cbc_cypher(struct esp32c3_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size); + +/**************************************************************************** + * Name: esp32c3_aes_ctr_cypher + * + * Description: + * Process AES CTR encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * offptr - Offset buffer pointer + * cntptr - Counter buffer pointer + * cacheptr - Counter calculation buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_ctr_cypher(struct esp32c3_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size); + +/**************************************************************************** + * Name: esp32c3_aes_xts_cypher + * + * Description: + * Process AES XTS encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * unitptr - Unit data buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_xts_cypher(struct esp32c3_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size); + +/**************************************************************************** + * Name: esp32c3_aes_setkey + * + * Description: + * Configurate AES key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_setkey(struct esp32c3_aes_s *aes, const void *keyptr, + uint16_t keybits); + +/**************************************************************************** + * Name: esp32c3_aes_xts_setkey + * + * Description: + * Configurate AES XTS key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_xts_setkey(struct esp32c3_aes_xts_s *aes, const void *keyptr, + uint16_t keybits); + +/**************************************************************************** + * Name: esp32c3_aes_init + * + * Description: + * Initialize ESP32-C3 AES hardware driver. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_AES_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_bignum.c b/arch/risc-v/src/esp32c3/esp32c3_bignum.c new file mode 100644 index 00000000000..0e52e7e6009 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_bignum.c @@ -0,0 +1,4067 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_bignum.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32C3_BIGNUM_ACCELERATOR + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "hardware/esp32c3_rsa.h" +#include "hardware/esp32c3_system.h" + +#include "esp32c3_bignum.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +#undef MIN +#undef MAX +#define MIN(X,Y) ((X) < (Y) ? (X) : (Y)) +#define MAX(X,Y) ((X) > (Y) ? (X) : (Y)) +#define SOC_RSA_MAX_BIT_LEN (3072) + +#define CIL (sizeof(uint32_t)) /* chars in limb */ +#define BIL (CIL << 3) /* bits in limb */ +#define BIH (CIL << 2) /* half limb size */ + +#define MPI_SIZE_T_MAX ((size_t) -1) /* SIZE_T_MAX is not standard */ + +/* Convert between bits/chars and number of limbs + * Divide first in order to avoid potential overflows + */ + +#define BITS_TO_LIMBS(i) ((i) / BIL + ((i) % BIL != 0)) +#define CHARS_TO_LIMBS(i) ((i) / CIL + ((i) % CIL != 0)) + +/* Get a specific byte, without range checks. */ +#define BYTE_BITS (8) +#define BYTE_CHECKS (0xff) +#define GET_BYTE(X, i) (((X)->p[(i) / CIL] >> \ + (((i) % CIL) * BYTE_BITS)) & BYTE_CHECKS) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static sem_t g_rsa_sem = SEM_INITIALIZER(1); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_mpi_to_mem_block + * + * Description: + * Copy MPI bignum 'mpi' to hardware memory block. + * + * Input Parameters: + * mem_base - The hardware memory block + * mpi - The bignum 'mpi' from the previous calculation + * num_words - The number of words to be represented + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_to_mem_block(uint32_t mem_base, + const struct esp32c3_mpi_s *mpi, + size_t num_words) +{ + uint32_t *pbase = (uint32_t *)mem_base; + uint32_t copy_words = MIN(num_words, mpi->n); + int i; + + /* Copy MPI data to memory block registers */ + + memcpy(pbase, mpi->p, copy_words * sizeof(uint32_t)); + + /* Zero any remaining memory block data */ + + for (i = copy_words; i < num_words; i++) + { + pbase[i] = 0; + } +} + +/**************************************************************************** + * Name: esp32c3_mem_block_to_mpi + * + * Description: + * Read MPI bignum back from hardware memory block. + * + * Input Parameters: + * x - The result from the previous calculation + * mem_base - The hardware memory block + * num_words - The number of words to be represented + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mem_block_to_mpi(struct esp32c3_mpi_s *x, + uint32_t mem_base, int num_words) +{ + int i; + + /* Copy data from memory block registers */ + + const size_t REG_WIDTH = sizeof(uint32_t); + for (i = 0; i < num_words; i++) + { + x->p[i] = getreg32(mem_base + (i * REG_WIDTH)); + } + + /* Zero any remaining limbs in the bignum, + * if the buffer is bigger than num_words + */ + + for (i = num_words; i < x->n; i++) + { + x->p[i] = 0; + } +} + +/**************************************************************************** + * Name: esp32c3_mpi_start_op + * + * Description: + * Begin an RSA operation. + * + * Input Parameters: + * op_reg - Specifies which 'START' register to write to. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_start_op(uint32_t op_reg) +{ + /* Clear interrupt status */ + + putreg32(1, RSA_CLEAR_INTERRUPT_REG); + + /* Note: above putreg32 includes a memw, so we know any writes + * to the memory blocks are also complete. + */ + + putreg32(1, op_reg); +} + +/**************************************************************************** + * Name: esp32c3_mpi_wait_op_complete + * + * Description: + * Wait for an RSA operation to complete. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_wait_op_complete(void) +{ + while (getreg32(RSA_IDLE_REG) != 1) + { + } + + /* clear the interrupt */ + + putreg32(1, RSA_CLEAR_INTERRUPT_REG); +} + +/**************************************************************************** + * Name: esp32c3_mpi_enable_hardware_hw_op + * + * Description: + * Enable the MPI hardware and acquire the lock. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_enable_hardware_hw_op(void) +{ + nxsem_wait(&g_rsa_sem); + + /* Enable RSA hardware */ + + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, 0, SYSTEM_CRYPTO_RSA_CLK_EN); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, (SYSTEM_CRYPTO_RSA_RST | + SYSTEM_CRYPTO_DS_RST), 0); + + modifyreg32(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD, 0); + + while (getreg32(RSA_CLEAN_REG) != 1) + { + } +} + +/**************************************************************************** + * Name: esp32c3_mpi_disable_hardware_hw_op + * + * Description: + * Disable the MPI hardware and release the lock. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_disable_hardware_hw_op(void) +{ + modifyreg32(SYSTEM_RSA_PD_CTRL_REG, 0, SYSTEM_RSA_MEM_PD); + + /* Disable RSA hardware */ + + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_CRYPTO_RSA_CLK_EN, 0); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, 0, SYSTEM_CRYPTO_RSA_RST); + + nxsem_post(&g_rsa_sem); +} + +/**************************************************************************** + * Name: esp32c3_mpi_read_result_hw_op + * + * Description: + * Read out the result from the previous calculation. + * + * Input Parameters: + * Z - The result from the previous calculation + * z_words - The number of words to be represented + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_read_result_hw_op(struct esp32c3_mpi_s *Z, + size_t z_words) +{ + esp32c3_mpi_wait_op_complete(); + esp32c3_mem_block_to_mpi(Z, RSA_MEM_Z_BLOCK_REG, z_words); +} + +/**************************************************************************** + * Name: esp32c3_mpi_mul_mpi_hw_op + * + * Description: + * Starts a (X * Y) calculation in hardware. + * + * Input Parameters: + * X - First multiplication argument + * Y - Second multiplication argument + * n_words - The number of words to be represented + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_mul_mpi_hw_op(const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y, + size_t n_words) +{ + /* Copy X (right-extended) & Y (left-extended) to memory block */ + + esp32c3_mpi_to_mem_block(RSA_MEM_X_BLOCK_REG, X, n_words); + esp32c3_mpi_to_mem_block(RSA_MEM_Z_BLOCK_REG + n_words * 4, Y, n_words); + + putreg32(((n_words * 2) - 1), RSA_MODE_REG); + esp32c3_mpi_start_op(RSA_MULT_START_REG); +} + +/**************************************************************************** + * Name: esp32c3_mpi_mult_failover_mod_op + * + * Description: + * Special-case of (X * Y), where we use hardware montgomery mod + * multiplication to calculate result where either A or B are > 2048 bits + * so can't use the standard multiplication method. + * + * Input Parameters: + * X - First multiplication argument + * Y - Second multiplication argument + * num_words - The number of words to be represented + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_mult_failover_mod_op(const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y, + size_t num_words) +{ + int i; + + /* M = 2^num_words - 1, so block is entirely FF */ + + for (i = 0; i < num_words; i++) + { + putreg32(UINT32_MAX, RSA_MEM_M_BLOCK_REG + i * 4); + } + + /* mprime = 1 */ + + putreg32(1, RSA_M_PRIME_REG); + putreg32(num_words - 1, RSA_MODE_REG); + + /* Load X & Y */ + + esp32c3_mpi_to_mem_block(RSA_MEM_X_BLOCK_REG, X, num_words); + esp32c3_mpi_to_mem_block(RSA_MEM_Y_BLOCK_REG, Y, num_words); + + /* rinv = 1, write first word */ + + putreg32(1, RSA_MEM_RB_BLOCK_REG); + + /* Zero out rest of the rinv words */ + + for (i = 1; i < num_words; i++) + { + putreg32(0, RSA_MEM_RB_BLOCK_REG + i * 4); + } + + esp32c3_mpi_start_op(RSA_MODMULT_START_REG); +} + +/**************************************************************************** + * Name: esp32c3_mpi_zeroize + * + * Description: + * Zero any limbs data. + * + * Input Parameters: + * v - The pointer to limbs + * n - The total number of limbs + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_mpi_zeroize(uint32_t *v, size_t n) +{ + memset(v, 0, CIL * n); +} + +/**************************************************************************** + * Name: bits_to_words + * + * Description: + * Convert bit count to 32-bits word count. + * + * Input Parameters: + * bits - The number of bit count + * + * Returned Value: + * Number of words count. + * + ****************************************************************************/ + +static size_t bits_to_words(size_t bits) +{ + return (bits + 31) / 32; +} + +/**************************************************************************** + * Name: mpi_sub_hlp + * + * Description: + * Helper for esp32c3_mpi subtraction + * + * Input Parameters: + * n - Number of limbs of \p d and \p s + * d - On input, the left operand, On output, the result operand + * s - The right operand + * + * Returned Value: + * \c 1 if \p `d < \p s`. + * \c 0 if \p `d >= \p s`.. + * + ****************************************************************************/ + +static uint32_t mpi_sub_hlp(size_t n, + uint32_t *d, + const uint32_t *s) +{ + size_t i; + uint32_t c; + uint32_t z; + + for (i = c = 0; i < n; i++, s++, d++) + { + z = (*d < c); + *d -= c; + c = (*d < *s) + z; + *d -= *s; + } + + return c; +} + +/**************************************************************************** + * Name: mpi_mul_addc + * + * Description: + * Helper for esp32c3_mpi multiplication + * + * Input Parameters: + * count - The count of limbs + * c - The result number of limbs + * s - The target number of limbs + * d - The pointer to limbs + * b - The total number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static inline void mpi_mul_addc(uint32_t count, uint32_t *c, + uint32_t **s, uint32_t **d, uint32_t b) +{ + uint32_t s0; + uint32_t s1; + uint32_t b0; + uint32_t b1; + uint32_t r0; + uint32_t r1; + uint32_t rx; + uint32_t ry; + + b0 = (b << BIH) >> BIH; + b1 = (b >> BIH); + + for (int i = 0; i < count; ++i) + { + s0 = (**s << BIH) >> BIH; + s1 = (**s >> BIH); + (*s)++; + rx = s0 * b1; + r0 = s0 * b0; + ry = s1 * b0; + r1 = s1 * b1; + r1 += (rx >> BIH); + r1 += (ry >> BIH); + rx <<= BIH; + ry <<= BIH; + r0 += rx; + r1 += (r0 < rx); + r0 += ry; + r1 += (r0 < ry); + r0 += *c; + r1 += (r0 < *c); + r0 += **d; + r1 += (r0 < **d); + *c = r1; + *((*d)++) = r0; + } +} + +/**************************************************************************** + * Name: mpi_mul_hlp + * + * Description: + * Helper for esp32c3_mpi multiplication + * + * Input Parameters: + * i - The MPI context to grow + * s - The target number of limbs + * d - The pointer to limbs + * b - The total number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static void mpi_mul_hlp(size_t i, uint32_t *s, uint32_t *d, uint32_t b) +{ + uint32_t c = 0; + + for (; i >= 16; i -= 16) + { + mpi_mul_addc(16, &c, &s, &d, b); + } + + for (; i >= 8; i -= 8) + { + mpi_mul_addc(8, &c, &s, &d, b); + } + + for (; i > 0; i--) + { + mpi_mul_addc(1, &c, &s, &d, b); + } + + do + { + *d += c; + c = (*d < c); + d++; + } + while (c != 0); +} + +/**************************************************************************** + * Name: mpi_safe_cond_assign + * + * Description: + * Conditionally assign dest = src, without leaking information + * about whether the assignment was made or not. + * + * Input Parameters: + * n - The MPI context to grow + * dest - The MPI to conditionally assign to + * src - The MPI to conditionally assign from + * assign - The condition deciding whether perform the assignment or not + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void mpi_safe_cond_assign(size_t n, + uint32_t *dest, + const uint32_t *src, + unsigned char assign) +{ + size_t i; + for (i = 0; i < n; i++) + { + dest[i] = dest[i] * (1 - assign) + src[i] * assign; + } +} + +/**************************************************************************** + * Name: mpi_montg_init + * + * Description: + * Fast Montgomery initialization + * + * Input Parameters: + * X - The MPI context to grow + * nblimbs - The target number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static void mpi_montg_init(uint32_t *mm, const struct esp32c3_mpi_s *N) +{ + uint32_t x; + uint32_t m0 = N->p[0]; + unsigned int i; + + x = m0 + (((m0 + 2) & 4) << 1); + + for (i = BIL; i >= 8; i /= 2) + { + x *= (2 - (m0 * x)); + } + + *mm = ~x + 1; +} + +/**************************************************************************** + * Name: mpi_montmul + * + * Description: + * Montgomery multiplication: A = A * B * R^-1 mod N + * + * Input Parameters: + * A - One of the numbers to multiply, + * It must have at least as many limbs as N + * (A->n >= N->n), and any limbs beyond n are ignored. + * On successful completion, A contains the result of + * the multiplication A * B * R^-1 mod N where + * R = (2^CIL)^n. + * B - One of the numbers to multiply, It must be nonzero + * and must not have more limbs than N (B->n <= N->n) + * N - The modulo. N must be odd. + * mm - The value calculated by `mpi_montg_init(&mm, N)`. + * This is -N^-1 mod 2^CIL. + * T - A bignum for temporary storage. + * It must be at least twice the limb size of N plus 2 + * (T->n >= 2 * (N->n + 1)). + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void mpi_montmul(struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B, + const struct esp32c3_mpi_s *N, + uint32_t mm, + const struct esp32c3_mpi_s *T) +{ + size_t i; + size_t n; + size_t m; + uint32_t u0; + uint32_t u1; + uint32_t *d; + + memset(T->p, 0, T->n * CIL); + + d = T->p; + n = N->n; + m = (B->n < n) ? B->n : n; + + for (i = 0; i < n; i++) + { + /* T = (T + u0*B + u1*N) / 2^BIL */ + + u0 = A->p[i]; + u1 = (d[0] + u0 * B->p[0]) * mm; + + mpi_mul_hlp(m, B->p, d, u0); + mpi_mul_hlp(n, N->p, d, u1); + + *d++ = u0; + d[n + 1] = 0; + } + + /* At this point, d is either the desired result or the desired result + * plus N. We now potentially subtract N, avoiding leaking whether the + * subtraction is performed through side channels. + */ + + /* Copy the n least significant limbs of d to A, so that + * A = d if d < N (recall that N has n limbs). + */ + + memcpy(A->p, d, n * CIL); + + /* If d >= N then we want to set A to d - N. To prevent timing attacks, + * do the calculation without using conditional tests. + */ + + /* Set d to d0 + (2^BIL)^n - N where d0 is the current value of d. + */ + + d[n] += 1; + d[n] -= mpi_sub_hlp(n, d, N->p); + /* If d0 < N then d < (2^BIL)^n + * so d[n] == 0 and we want to keep A as it is. + * If d0 >= N then d >= (2^BIL)^n, and d <= (2^BIL)^n + N < 2 * (2^BIL)^n + * so d[n] == 1 and we want to set A to the result of the subtraction + * which is d - (2^BIL)^n, i.e. the n least significant limbs of d. + * This exactly corresponds to a conditional assignment. + */ + + mpi_safe_cond_assign(n, A->p, d, (unsigned char) d[n]); +} + +/**************************************************************************** + * Name: mpi_montred + * + * Description: + * Montgomery reduction: A = A * R^-1 mod N + * + * Input Parameters: + * A - One of the numbers to multiply, + * It must have at least as many limbs as N + * (A->n >= N->n), and any limbs beyond n are ignored. + * On successful completion, A contains the result of + * the multiplication A * B * R^-1 mod N where + * R = (2^CIL)^n. + * N - The modulo. N must be odd. + * mm - The value calculated by `mpi_montg_init(&mm, N)`. + * This is -N^-1 mod 2^CIL. + * T - A bignum for temporary storage. + * It must be at least twice the limb size of N plus 2 + * (T->n >= 2 * (N->n + 1)). + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static void mpi_montred(struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *N, + uint32_t mm, + const struct esp32c3_mpi_s *T) +{ + uint32_t z = 1; + struct esp32c3_mpi_s U; + + U.n = (int) z; + U.s = (int) z; + U.p = &z; + + mpi_montmul(A, &U, N, mm, T); +} + +/**************************************************************************** + * Name: mpi_mult_mpi_overlong + * + * Description: + * Deal with the case when X & Y are too long for the hardware unit, + * by splitting one operand into two halves. + * + * Input Parameters: + * Z - The destination MPI + * X - The first factor + * Y - The second factor + * y_words - The number of words to be process + * z_words - The number of words to be represented + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int mpi_mult_mpi_overlong(struct esp32c3_mpi_s *Z, + const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y, + size_t y_words, size_t z_words) +{ + int ret = 0; + struct esp32c3_mpi_s ztemp; + + /* Rather than slicing in two on bits we slice on limbs (32 bit words) */ + + const size_t words_slice = y_words / 2; + + /* yp holds lower bits of Y */ + + const struct esp32c3_mpi_s yp = { + .p = Y->p, + .n = words_slice, + .s = Y->s + }; + + /* ypp holds upper bits of Y, + * right shifted (also reuses Y's array contents) + */ + + const struct esp32c3_mpi_s ypp = { + .p = Y->p + words_slice, + .n = y_words - words_slice, + .s = Y->s + }; + + esp32c3_mpi_init(&ztemp); + + /* Get result ztemp = yp * X (need temporary variable ztemp) */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&ztemp, X, &yp), cleanup); + + /* Z = ypp * Y */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(Z, X, &ypp), cleanup); + + /* Z = Z << b */ + + ESP32C3_MPI_CHK(esp32c3_mpi_shift_l(Z, words_slice * 32), cleanup); + + /* Z += ztemp */ + + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(Z, Z, &ztemp), cleanup); + +cleanup: + esp32c3_mpi_free(&ztemp); + + return ret; +} + +/**************************************************************************** + * Name: mpi_mult_mpi_failover_mod_mult + * + * Description: + * Where we use hardware montgomery mod multiplication to calculate an + * esp32c3_mpi_mult_mpi result where either A or B are > 2048 bits + * so can't use the standard multiplication method. + * + * Input Parameters: + * Z - The destination MPI + * X - The first factor + * Y - The second factor + * z_words - The number of words to be represented + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int mpi_mult_mpi_failover_mod_mult(struct esp32c3_mpi_s *Z, + const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y, + size_t z_words) +{ + int ret; + + esp32c3_mpi_enable_hardware_hw_op(); + + esp32c3_mpi_mult_failover_mod_op(X, Y, z_words); + ESP32C3_MPI_CHK(esp32c3_mpi_grow(Z, z_words), cleanup); + esp32c3_mpi_read_result_hw_op(Z, z_words); + + Z->s = X->s * Y->s; +cleanup: + esp32c3_mpi_disable_hardware_hw_op(); + return ret; +} + +/**************************************************************************** + * Name: esp32c3_bignum_clz + * + * Description: + * Count leading zero bits in a given integer + * + * Input Parameters: + * x - The MPI context to query + * + * Returned Value: + * The count leading zero bits in a given integer. + * + ****************************************************************************/ + +static size_t esp32c3_bignum_clz(const uint32_t x) +{ + size_t j; + uint32_t mask = UINT32_C(1) << (BIL - 1); + + for (j = 0; j < BIL; j++) + { + if (x & mask) + { + break; + } + + mask >>= 1; + } + + return j; +} + +/**************************************************************************** + * Name: mpi_get_digit + * + * Description: + * Convert an ASCII character to digit value + * + * Input Parameters: + * d - The destination MPI + * radix - The numeric base of the input character + * c - An ASCII character + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int mpi_get_digit(uint32_t *d, int radix, char c) +{ + *d = 255; + + if (c >= 0x30 && c <= 0x39) + { + *d = c - 0x30; + } + + if (c >= 0x41 && c <= 0x46) + { + *d = c - 0x37; + } + + if (c >= 0x61 && c <= 0x66) + { + *d = c - 0x57; + } + + if (*d >= (uint32_t) radix) + { + return ESP32C3_ERR_MPI_INVALID_CHARACTER; + } + + return OK; +} + +/**************************************************************************** + * Name: mpi_write_hlp + * + * Description: + * Helper to write the digits high-order first + * + * Input Parameters: + * X - The source MPI + * radix - The numeric base of the output string + * p - The buffer to write the string to + * buflen - The available size in Bytes of p + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int mpi_write_hlp(struct esp32c3_mpi_s *X, int radix, + char **p, const size_t buflen) +{ + int ret; + uint32_t r; + size_t length = 0; + char *p_end = *p + buflen; + + do + { + if (length >= buflen) + { + return ESP32C3_ERR_MPI_BUFFER_TOO_SMALL; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_mod_int(&r, X, radix), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_div_int(X, NULL, X, radix), cleanup); + + /* Write the residue in the current position, as an ASCII character. + */ + + if (r < 0xa) + { + *(--p_end) = (char)('0' + r); + } + else + { + *(--p_end) = (char)('A' + (r - 0xa)); + } + + length++; + } + while (esp32c3_mpi_cmp_int(X, 0) != 0); + + memmove(*p, p_end, length); + *p += length; + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: mpi_uint_bigendian_to_host + * + * Description: + * Convert a big-endian byte array aligned to the size of uint32_t + * into the storage form used by esp32c3_mpi + * + * Input Parameters: + * X - The MPI context to convert + * + * Returned Value: + * The size of uint32_t into the storage form used by esp32c3_mpi. + * + ****************************************************************************/ + +static uint32_t mpi_uint_bigendian_to_host(uint32_t x) +{ + uint8_t i; + unsigned char *x_ptr; + uint32_t tmp = 0; + + for (i = 0, x_ptr = (unsigned char *) &x; i < CIL; i++, x_ptr++) + { + tmp <<= CHAR_BIT; + tmp |= (uint32_t) *x_ptr; + } + + return (tmp); +} + +/**************************************************************************** + * Name: mpi_bigendian_to_host + * + * Description: + * Enlarge an MPI to the specified number of limbs + * + * Input Parameters: + * p - The MPI context to grow + * limbs - The target number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static void mpi_bigendian_to_host(uint32_t * const p, size_t limbs) +{ + uint32_t *cur_limb_left; + uint32_t *cur_limb_right; + if (limbs == 0) + { + return ; + } + + /* Traverse limbs and + * - adapt byte-order in each limb + * - swap the limbs themselves. + * For that, simultaneously traverse the limbs from left to right + * and from right to left, as long as the left index is not bigger + * than the right index (it's not a problem if limbs is odd and the + * indices coincide in the last iteration). + */ + + for (cur_limb_left = p, cur_limb_right = p + (limbs - 1); + cur_limb_left <= cur_limb_right; + cur_limb_left++, cur_limb_right--) + { + uint32_t tmp; + + /* Note that if cur_limb_left == cur_limb_right, + * this code effectively swaps the bytes only once. + */ + + tmp = mpi_uint_bigendian_to_host(*cur_limb_left); + *cur_limb_left = mpi_uint_bigendian_to_host(*cur_limb_right); + *cur_limb_right = tmp; + } +} + +/**************************************************************************** + * Name: ct_lt_mpi_uint + * + * Description: + * Decide if an integer is less than the other, without branches. + * + * Input Parameters: + * X - First integer + * nblimbs - Second integer + * + * Returned Value: + * 1 if \p x is less than \p y, 0 otherwise. + * + ****************************************************************************/ + +static unsigned ct_lt_mpi_uint(const uint32_t x, + const uint32_t y) +{ + uint32_t ret; + uint32_t cond; + + /* Check if the most significant bits (MSB) of the operands are different. + */ + + cond = (x ^ y); + + /* If the MSB are the same then the difference x-y will be negative (and + * have its MSB set to 1 during conversion to unsigned) if and only if x> (BIL - 1); + + return (unsigned) ret; +} + +/**************************************************************************** + * Name: esp32c3_bignum_int_div_int + * + * Description: + * Unsigned integer divide - double uint32_t dividend, u1/u0, and + * uint32_t divisor, d + * + * Input Parameters: + * X - The MPI context to grow + * nblimbs - The target number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static uint32_t esp32c3_bignum_int_div_int(uint32_t u1, uint32_t u0, + uint32_t d, uint32_t *r) +{ + const uint32_t radix = (uint32_t) 1 << BIH; + const uint32_t uint_halfword_mask = ((uint32_t) 1 << BIH) - 1; + uint32_t d0; + uint32_t d1; + uint32_t q0; + uint32_t q1; + uint32_t rax; + uint32_t r0; + uint32_t quotient; + uint32_t u0_msw; + uint32_t u0_lsw; + size_t s; + + /* Check for overflow */ + + if (0 == d || u1 >= d) + { + if (r != NULL) + { + *r = ~0; + } + + return (~0); + } + + /* Algorithm D, Section 4.3.1 - The Art of Computer Programming + * Vol. 2 - Seminumerical Algorithms, Knuth + */ + + /* Normalize the divisor, d, and dividend, u0, u1 + */ + + s = esp32c3_bignum_clz(d); + d = d << s; + + u1 = u1 << s; + u1 |= (u0 >> (BIL - s)) & (-(int32_t)s >> (BIL - 1)); + u0 = u0 << s; + + d1 = d >> BIH; + d0 = d & uint_halfword_mask; + + u0_msw = u0 >> BIH; + u0_lsw = u0 & uint_halfword_mask; + + /* Find the first quotient and remainder + */ + + q1 = u1 / d1; + r0 = u1 - d1 * q1; + + while (q1 >= radix || (q1 * d0 > radix * r0 + u0_msw)) + { + q1 -= 1; + r0 += d1; + + if (r0 >= radix) + { + break; + } + } + + rax = (u1 * radix) + (u0_msw - q1 * d); + q0 = rax / d1; + r0 = rax - q0 * d1; + + while (q0 >= radix || (q0 * d0 > radix * r0 + u0_lsw)) + { + q0 -= 1; + r0 += d1; + + if (r0 >= radix) + { + break; + } + } + + if (r != NULL) + { + *r = (rax * radix + u0_lsw - q0 * d) >> s; + } + + quotient = q1 * radix + q0; + + return quotient; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_mpi_init + * + * Description: + * Initialize an MPI context + * + * Input Parameters: + * X - The MPI context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_mpi_init(struct esp32c3_mpi_s *X) +{ + DEBUGASSERT(X != NULL); + + X->s = 1; + X->n = 0; + X->p = NULL; +} + +/**************************************************************************** + * Name: esp32c3_mpi_free + * + * Description: + * Frees the components of an MPI context + * + * Input Parameters: + * X - The MPI context to be cleared + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_mpi_free(struct esp32c3_mpi_s *X) +{ + if (X == NULL) + { + return ; + } + + if (X->p != NULL) + { + esp32c3_mpi_zeroize(X->p, X->n); + free(X->p); + } + + X->s = 1; + X->n = 0; + X->p = NULL; +} + +/**************************************************************************** + * Name: esp32c3_mpi_grow + * + * Description: + * Enlarge an MPI to the specified number of limbs + * + * Input Parameters: + * X - The MPI context to grow + * nblimbs - The target number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_grow(struct esp32c3_mpi_s *X, size_t nblimbs) +{ + uint32_t *p; + DEBUGASSERT(X != NULL); + + if (nblimbs > ESP32C3_MPI_MAX_LIMBS) + { + return ESP32C3_ERR_MPI_ALLOC_FAILED; + } + + if (X->n < nblimbs) + { + if ((p = (uint32_t *)calloc(nblimbs, CIL)) == NULL) + { + return ESP32C3_ERR_MPI_ALLOC_FAILED; + } + + if (X->p != NULL) + { + memcpy(p, X->p, X->n * CIL); + esp32c3_mpi_zeroize(X->p, X->n); + free(X->p); + } + + X->n = nblimbs; + X->p = p; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_shrink + * + * Description: + * Resizes an MPI downwards, keeping at least the specified number of limbs + * + * Input Parameters: + * X - The MPI context to shrink + * nblimbs - The minimum number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_shrink(struct esp32c3_mpi_s *X, size_t nblimbs) +{ + uint32_t *p; + size_t i; + DEBUGASSERT(X != NULL); + + if (nblimbs > ESP32C3_MPI_MAX_LIMBS) + { + return ESP32C3_ERR_MPI_ALLOC_FAILED; + } + + /* Actually resize up if there are currently fewer than nblimbs limbs. */ + + if (X->n <= nblimbs) + { + return (esp32c3_mpi_grow(X, nblimbs)); + } + + /* After this point, then X->n > nblimbs and in particular X->n > 0. */ + + for (i = X->n - 1; i > 0; i--) + { + if (X->p[i] != 0) + { + break; + } + } + + i++; + + if (i < nblimbs) + { + i = nblimbs; + } + + if ((p = (uint32_t *)calloc(i, CIL)) == NULL) + { + return ESP32C3_ERR_MPI_ALLOC_FAILED; + } + + if (X->p != NULL) + { + memcpy(p, X->p, i * CIL); + esp32c3_mpi_zeroize(X->p, X->n); + free(X->p); + } + + X->n = i; + X->p = p; + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_copy + * + * Description: + * Copy the contents of Y into X + * + * Input Parameters: + * X - The destination MPI + * Y - The source MPI + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_copy(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y) +{ + int ret = 0; + size_t i; + DEBUGASSERT(X != NULL); + DEBUGASSERT(Y != NULL); + + if (X == Y) + { + return OK; + } + + if (Y->n == 0) + { + esp32c3_mpi_free(X); + return OK; + } + + for (i = Y->n - 1; i > 0; i--) + { + if (Y->p[i] != 0) + { + break; + } + } + + i ++; + + X->s = Y->s; + + if (X->n < i) + { + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, i), cleanup); + } + else + { + memset(X->p + i, 0, (X->n - i) * CIL); + } + + memcpy(X->p, Y->p, i * CIL); + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_swap + * + * Description: + * Swap the contents of X and Y + * + * Input Parameters: + * X - The first MPI + * nblimbs - The second MPI + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_mpi_swap(struct esp32c3_mpi_s *X, struct esp32c3_mpi_s *Y) +{ + struct esp32c3_mpi_s T; + DEBUGASSERT(X != NULL); + DEBUGASSERT(Y != NULL); + + memcpy(&T, X, sizeof(struct esp32c3_mpi_s)); + memcpy(X, Y, sizeof(struct esp32c3_mpi_s)); + memcpy(Y, &T, sizeof(struct esp32c3_mpi_s)); +} + +/**************************************************************************** + * Name: esp32c3_mpi_safe_cond_assign + * + * Description: + * Perform a safe conditional copy of MPI which doesn't + * reveal whether the condition was true or not. + * + * Input Parameters: + * X - The MPI to conditionally assign to + * Y - The MPI to be assigned from + * assign - The condition deciding whether perform the assignment or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_safe_cond_assign(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y, + unsigned char assign) +{ + int ret = 0; + size_t i; + DEBUGASSERT(X != NULL); + DEBUGASSERT(Y != NULL); + + /* make sure assign is 0 or 1 in a time-constant manner */ + + assign = (assign | (unsigned char)-assign) >> 7; + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, Y->n), cleanup); + + X->s = X->s * (1 - assign) + Y->s * assign; + + mpi_safe_cond_assign(Y->n, X->p, Y->p, assign); + + for (i = Y->n; i < X->n; i++) + { + X->p[i] *= (1 - assign); + } + +cleanup: + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_safe_cond_swap + * + * Description: + * Perform a safe conditional swap which doesn't + * reveal whether the condition was true or not. + * + * Input Parameters: + * X - The first MPI + * Y - The second MPI + * swap - The condition deciding whether to perform the swap or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_safe_cond_swap(struct esp32c3_mpi_s *X, + struct esp32c3_mpi_s *Y, + unsigned char swap) +{ + int ret; + int s; + size_t i; + uint32_t tmp; + DEBUGASSERT(X != NULL); + DEBUGASSERT(Y != NULL); + + if (X == Y) + { + return OK; + } + + /* make sure swap is 0 or 1 in a time-constant manner */ + + swap = (swap | (unsigned char)-swap) >> 7; + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, Y->n), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_grow(Y, X->n), cleanup); + + s = X->s; + X->s = X->s * (1 - swap) + Y->s * swap; + Y->s = Y->s * (1 - swap) + s * swap; + + for (i = 0; i < X->n; i++) + { + tmp = X->p[i]; + X->p[i] = X->p[i] * (1 - swap) + Y->p[i] * swap; + Y->p[i] = Y->p[i] * (1 - swap) + tmp * swap; + } + +cleanup: + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_lset + * + * Description: + * Set value from integer + * + * Input Parameters: + * X - The MPI to set + * z - The value to use + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_lset(struct esp32c3_mpi_s *X, int32_t z) +{ + int ret; + DEBUGASSERT(X != NULL); + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, 1), cleanup); + memset(X->p, 0, X->n * CIL); + + X->p[0] = (z < 0) ? -z : z; + X->s = (z < 0) ? -1 : 1; + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_get_bit + * + * Description: + * Get a specific bit from an MPI + * + * Input Parameters: + * X - The MPI context to query + * pos - Zero-based index of the bit to query + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_get_bit(const struct esp32c3_mpi_s *X, size_t pos) +{ + DEBUGASSERT(X != NULL); + + if (X->n * BIL <= pos) + { + return OK; + } + + return ((X->p[pos / BIL] >> (pos % BIL)) & 0x01); +} + +/**************************************************************************** + * Name: esp32c3_mpi_set_bit + * + * Description: + * Modify a specific bit in an MPI + * + * Input Parameters: + * X - The MPI context to modify + * pos - Zero-based index of the bit to modify + * val - The desired value of bit + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_set_bit(struct esp32c3_mpi_s *X, + size_t pos, unsigned char val) +{ + int ret = 0; + size_t off = pos / BIL; + size_t idx = pos % BIL; + DEBUGASSERT(X != NULL); + + if (val != 0 && val != 1) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + if (X->n * BIL <= pos) + { + if (val == 0) + { + return OK; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, off + 1), cleanup); + } + + X->p[off] &= ~((uint32_t) 0x01 << idx); + X->p[off] |= (uint32_t) val << idx; + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_lsb + * + * Description: + * Return the number of bits of value + * + * Input Parameters: + * X - The MPI context to query + * + * Returned Value: + * The number of bits of value. + * + ****************************************************************************/ + +size_t esp32c3_mpi_lsb(const struct esp32c3_mpi_s *X) +{ + size_t i; + size_t j; + size_t count = 0; + DEBUGASSERT(X != NULL); + + for (i = 0; i < X->n; i++) + { + for (j = 0; j < BIL; j++, count++) + { + if (((X->p[i] >> j) & 1) != 0) + { + return (count); + } + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_bitlen + * + * Description: + * Return the number of bits up to and including the most + * significant bit of value + * + * Input Parameters: + * X - The MPI context to query + * + * Returned Value: + * The number of bits up and including the most significant bit of value. + * + ****************************************************************************/ + +size_t esp32c3_mpi_bitlen(const struct esp32c3_mpi_s *X) +{ + size_t i; + size_t j; + + if (X->n == 0) + { + return OK; + } + + for (i = X->n - 1; i > 0; i--) + { + if (X->p[i] != 0) + { + break; + } + } + + j = BIL - esp32c3_bignum_clz(X->p[i]); + + return ((i * BIL) + j); +} + +/**************************************************************************** + * Name: esp32c3_mpi_size + * + * Description: + * Return the total size of an MPI value in bytes + * + * Input Parameters: + * X - The MPI context to query + * + * Returned Value: + * The least number of bytes capable of storing the absolute value. + * + ****************************************************************************/ + +size_t esp32c3_mpi_size(const struct esp32c3_mpi_s *X) +{ + return ((esp32c3_mpi_bitlen(X) + 7) >> 3); +} + +/**************************************************************************** + * Name: esp32c3_mpi_read_string + * + * Description: + * Import from an ASCII string + * + * Input Parameters: + * X - The destination MPI + * radix - The numeric base of the input string + * s - Null-terminated string buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_read_string(struct esp32c3_mpi_s *X, + int radix, const char *s) +{ + int ret; + size_t i; + size_t j; + size_t slen; + size_t n; + uint32_t d; + struct esp32c3_mpi_s T; + DEBUGASSERT(X != NULL); + DEBUGASSERT(s != NULL); + + if (radix < 2 || radix > 16) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + esp32c3_mpi_init(&T); + + slen = strlen(s); + + if (radix == 16) + { + if (slen > MPI_SIZE_T_MAX >> 2) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + n = BITS_TO_LIMBS(slen << 2); + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, n), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_lset(X, 0), cleanup); + + for (i = slen, j = 0; i > 0; i--, j++) + { + if (i == 1 && s[i - 1] == '-') + { + X->s = -1; + break; + } + + ESP32C3_MPI_CHK(mpi_get_digit(&d, radix, s[i - 1]), cleanup); + X->p[j / (2 * CIL)] |= d << ((j % (2 * CIL)) << 2); + } + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_lset(X, 0), cleanup); + + for (i = 0; i < slen; i++) + { + if (i == 0 && s[i] == '-') + { + X->s = -1; + continue; + } + + ESP32C3_MPI_CHK(mpi_get_digit(&d, radix, s[i]), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_int(&T, X, radix), cleanup); + + if (X->s == 1) + { + ESP32C3_MPI_CHK(esp32c3_mpi_add_int(X, &T, d), cleanup); + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(X, &T, d), cleanup); + } + } + } + +cleanup: + + esp32c3_mpi_free(&T); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_write_string + * + * Description: + * Export an MPI to an ASCII string + * + * Input Parameters: + * X - The source MPI + * radix - The numeric base of the output string + * buf - The buffer to write the string to + * buflen - The available size in Bytes of buf + * olen - The address at which to store the length of the string written + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_write_string(const struct esp32c3_mpi_s *X, int radix, + char *buf, size_t buflen, size_t *olen) +{ + int ret = 0; + size_t n; + char *p; + struct esp32c3_mpi_s T; + DEBUGASSERT(X != NULL); + DEBUGASSERT(olen != NULL); + DEBUGASSERT(buflen == 0 || buf != NULL); + + if (radix < 2 || radix > 16) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + /* Number of bits necessary to present `n`. */ + + n = esp32c3_mpi_bitlen(X); + if (radix >= 4) + { + /* Number of 4-adic digits necessary to present + * `n`. If radix > 4, this might be a strict + * overapproximation of the number of + * radix-adic digits needed to present `n`. + */ + + n >>= 1; + } + + if (radix >= 16) + { + /* Number of hexadecimal digits necessary to + * present `n`. + */ + + n >>= 1; + } + + /* Terminating null byte */ + + n += 1; + + /* Compensate for the divisions above, which round down `n` + * in case it's not even. + */ + + n += 1; + + /* Potential '-'-sign. */ + + n += 1; + + /* Make n even to have enough space for hexadecimal writing, + * which always uses an even number of hex-digits. + */ + + n += (n & 1); + + if (buflen < n) + { + *olen = n; + return ESP32C3_ERR_MPI_BUFFER_TOO_SMALL; + } + + p = buf; + esp32c3_mpi_init(&T); + + if (X->s == -1) + { + *p++ = '-'; + buflen--; + } + + if (radix == 16) + { + int c; + size_t i, j, k; + + for (i = X->n, k = 0; i > 0; i--) + { + for (j = CIL; j > 0; j--) + { + c = (X->p[i - 1] >> ((j - 1) << 3)) & 0xff; + + if (c == 0 && k == 0 && (i + j) != 2) + { + continue; + } + + *(p++) = "0123456789ABCDEF" [c / 16]; + *(p++) = "0123456789ABCDEF" [c % 16]; + k = 1; + } + } + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&T, X), cleanup); + + if (T.s == -1) + { + T.s = 1; + } + + ESP32C3_MPI_CHK(mpi_write_hlp(&T, radix, &p, buflen), cleanup); + } + + *p++ = '\0'; + *olen = p - buf; + +cleanup: + + esp32c3_mpi_free(&T); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_read_binary + * + * Description: + * Import an MPI from unsigned big endian binary data + * + * Input Parameters: + * X - The destination MPI + * buf - The input buffer + * buflen - The length of the input buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_read_binary(struct esp32c3_mpi_s *X, + const unsigned char *buf, + size_t buflen) +{ + int ret; + size_t const limbs = CHARS_TO_LIMBS(buflen); + size_t const overhead = (limbs * CIL) - buflen; + unsigned char *XP; + + DEBUGASSERT(X != NULL); + DEBUGASSERT(buflen == 0 || buf != NULL); + + /* Ensure that target MPI has exactly the necessary number of limbs */ + + if (X->n != limbs) + { + esp32c3_mpi_free(X); + esp32c3_mpi_init(X); + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, limbs), cleanup); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_lset(X, 0), cleanup); + + /* Avoid calling `memcpy` with NULL source argument, + * even if buflen is 0. + */ + + if (buf != NULL) + { + XP = (unsigned char *) X->p; + memcpy(XP + overhead, buf, buflen); + + mpi_bigendian_to_host(X->p, limbs); + } + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_write_binary + * + * Description: + * Export X into unsigned binary data, big endian + * + * Input Parameters: + * X - The source MPI + * buf - The output buffer + * buflen - The length of the output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_write_binary(const struct esp32c3_mpi_s *X, + unsigned char *buf, size_t buflen) +{ + size_t stored_bytes; + size_t bytes_to_copy; + unsigned char *p; + size_t i; + + DEBUGASSERT(X != NULL); + DEBUGASSERT(buflen == 0 || buf != NULL); + + stored_bytes = X->n * CIL; + + if (stored_bytes < buflen) + { + /* There is enough space in the output buffer. Write initial + * null bytes and record the position at which to start + * writing the significant bytes. In this case, the execution + * trace of this function does not depend on the value of the + * number. + */ + + bytes_to_copy = stored_bytes; + p = buf + buflen - stored_bytes; + memset(buf, 0, buflen - stored_bytes); + } + else + { + /* The output buffer is smaller than the allocated size of X. + * However X may fit if its leading bytes are zero. + */ + + bytes_to_copy = buflen; + p = buf; + for (i = bytes_to_copy; i < stored_bytes; i++) + { + if (GET_BYTE(X, i) != 0) + { + return ESP32C3_ERR_MPI_BUFFER_TOO_SMALL; + } + } + } + + for (i = 0; i < bytes_to_copy; i++) + { + p[bytes_to_copy - i - 1] = GET_BYTE(X, i); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_shift_l + * + * Description: + * Perform a left-shift on an MPI: X <<= count + * + * Input Parameters: + * X - The MPI to shift + * count - The number of bits to shift by + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_shift_l(struct esp32c3_mpi_s *X, size_t count) +{ + int ret; + size_t i, v0, t1; + uint32_t r0 = 0, r1; + DEBUGASSERT(X != NULL); + + v0 = count / (BIL); + t1 = count & (BIL - 1); + + i = esp32c3_mpi_bitlen(X) + count; + + if (X->n * BIL < i) + { + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, BITS_TO_LIMBS(i)), cleanup); + } + + ret = 0; + + /* shift by count / limb_size */ + + if (v0 > 0) + { + for (i = X->n; i > v0; i--) + X->p[i - 1] = X->p[i - v0 - 1]; + + for (; i > 0; i--) + X->p[i - 1] = 0; + } + + /* shift by count % limb_size + */ + + if (t1 > 0) + { + for (i = v0; i < X->n; i++) + { + r1 = X->p[i] >> (BIL - t1); + X->p[i] <<= t1; + X->p[i] |= r0; + r0 = r1; + } + } + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_shift_r + * + * Description: + * Perform a right-shift on an MPI: X >>= count + * + * Input Parameters: + * X - The MPI to shift + * count - The number of bits to shift by + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_shift_r(struct esp32c3_mpi_s *X, size_t count) +{ + size_t i, v0, v1; + uint32_t r0 = 0, r1; + DEBUGASSERT(X != NULL); + + v0 = count / BIL; + v1 = count & (BIL - 1); + + if (v0 > X->n || (v0 == X->n && v1 > 0)) + { + return esp32c3_mpi_lset(X, 0); + } + + /* shift by count / limb_size + */ + + if (v0 > 0) + { + for (i = 0; i < X->n - v0; i++) + { + X->p[i] = X->p[i + v0]; + } + + for (; i < X->n; i++) + { + X->p[i] = 0; + } + } + + /* shift by count % limb_size + */ + + if (v1 > 0) + { + for (i = X->n; i > 0; i--) + { + r1 = X->p[i - 1] << (BIL - v1); + X->p[i - 1] >>= v1; + X->p[i - 1] |= r0; + r0 = r1; + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_cmp_abs + * + * Description: + * Compare the absolute values of two MPIs + * + * Input Parameters: + * X - The left-hand MPI + * Y - The right-hand MPI + * + * Returned Value: + * 1 if \p `|X|` is greater than \p `|Y|`. + * -1 if \p `|X|` is lesser than \p `|Y|`. + * 0 if \p `|X|` is equal to \p `|Y|`. + * + ****************************************************************************/ + +int esp32c3_mpi_cmp_abs(const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y) +{ + size_t i, j; + DEBUGASSERT(X != NULL); + DEBUGASSERT(Y != NULL); + + for (i = X->n; i > 0; i--) + { + if (X->p[i - 1] != 0) + { + break; + } + } + + for (j = Y->n; j > 0; j--) + { + if (Y->p[j - 1] != 0) + { + break; + } + } + + if (i == 0 && j == 0) + { + return OK; + } + + if (i > j) + { + return (1); + } + + if (j > i) + { + return (-1); + } + + for (; i > 0; i--) + { + if (X->p[i - 1] > Y->p[i - 1]) + { + return (1); + } + + if (X->p[i - 1] < Y->p[i - 1]) + { + return (-1); + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_cmp_mpi + * + * Description: + * Compare two MPIs. + * + * Input Parameters: + * X - The left-hand MPI + * Y - The right-hand MPI + * + * Returned Value: + * 1 if \p `X` is greater than \p `Y`. + * -1 if \p `X` is lesser than \p `Y`. + * 0 if \p `X` is equal to \p `Y`. + * + ****************************************************************************/ + +int esp32c3_mpi_cmp_mpi(const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y) +{ + size_t i, j; + DEBUGASSERT(X != NULL); + DEBUGASSERT(Y != NULL); + + for (i = X->n; i > 0; i--) + { + if (X->p[i - 1] != 0) + { + break; + } + } + + for (j = Y->n; j > 0; j--) + { + if (Y->p[j - 1] != 0) + { + break; + } + } + + if (i == 0 && j == 0) + { + return OK; + } + + if (i > j) + { + return (X->s); + } + + if (j > i) + { + return (-Y->s); + } + + if (X->s > 0 && Y->s < 0) + { + return (1); + } + + if (Y->s > 0 && X->s < 0) + { + return (-1); + } + + for (; i > 0; i--) + { + if (X->p[i - 1] > Y->p[i - 1]) + { + return (X->s); + } + + if (X->p[i - 1] < Y->p[i - 1]) + { + return (-X->s); + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_lt_mpi_ct + * + * Description: + * Check if an MPI is less than the other in constant time + * + * Input Parameters: + * X - The left-hand MPI + * Y - The right-hand MPI + * ret - The result of the comparison: + * 1 if \p X is less than \p Y. + * 0 if \p X is greater than or equal to \p Y. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_lt_mpi_ct(const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y, + unsigned *ret) +{ + size_t i; + + /* The value of any of these variables is either 0 or 1 at all times. */ + + unsigned cond, done, x_is_negative, y_is_negative; + + DEBUGASSERT(X != NULL); + DEBUGASSERT(Y != NULL); + DEBUGASSERT(ret != NULL); + + if (X->n != Y->n) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + /* Set sign_N to 1 if N >= 0, 0 if N < 0. + * We know that N->s == 1 if N >= 0 and N->s == -1 if N < 0. + */ + + x_is_negative = (X->s & 2) >> 1; + y_is_negative = (Y->s & 2) >> 1; + + /* If the signs are different, then the positive operand is the bigger. + * That is if X is negative (x_is_negative == 1), then X < Y is true and it + * is false if X is positive (x_is_negative == 0). + */ + + cond = (x_is_negative ^ y_is_negative); + *ret = cond & x_is_negative; + + /* This is a constant-time function. We might have the result, but we still + * need to go through the loop. Record if we have the result already. + */ + + done = cond; + + for (i = X->n; i > 0; i--) + { + /* If Y->p[i - 1] < X->p[i - 1] then X < Y is true if and only if both + * X and Y are negative. + * + * Again even if we can make a decision, we just mark the result and + * the fact that we are done and continue looping. + */ + + cond = ct_lt_mpi_uint(Y->p[i - 1], X->p[i - 1]); + *ret |= cond & (1 - done) & x_is_negative; + done |= cond; + + /* If X->p[i - 1] < Y->p[i - 1] then X < Y is true if and only if both + * X and Y are positive. + * + * Again even if we can make a decision, we just mark the result and + * the fact that we are done and continue looping. + */ + + cond = ct_lt_mpi_uint(X->p[i - 1], Y->p[i - 1]); + *ret |= cond & (1 - done) & (1 - x_is_negative); + done |= cond; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_cmp_int + * + * Description: + * Compare an MPI with an integer + * + * Input Parameters: + * X - The left-hand MPI + * z - The integer value to compare \p X to + * + * Returned Value: + * \c 1 if \p X is greater than \p z. + * \c -1 if \p X is lesser than \p z. + * \c 0 if \p X is equal to \p z. + * + ****************************************************************************/ + +int esp32c3_mpi_cmp_int(const struct esp32c3_mpi_s *X, int32_t z) +{ + struct esp32c3_mpi_s Y; + uint32_t p[1]; + DEBUGASSERT(X != NULL); + + *p = (z < 0) ? -z : z; + Y.s = (z < 0) ? -1 : 1; + Y.n = 1; + Y.p = p; + + return (esp32c3_mpi_cmp_mpi(X, &Y)); +} + +/**************************************************************************** + * Name: esp32c3_mpi_add_abs + * + * Description: + * Perform an unsigned addition of MPIs: X = |A| + |B| + * + * Input Parameters: + * X - The left-hand MPI + * z - The integer value to compare \p X to. + * + * Returned Value: + * \c 1 if \p X is greater than \p z. + * \c -1 if \p X is lesser than \p z. + * \c 0 if \p X is equal to \p z. + * + ****************************************************************************/ + +int esp32c3_mpi_add_abs(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B) +{ + int ret; + size_t i, j; + uint32_t *o, *p, c, tmp; + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + DEBUGASSERT(B != NULL); + + if (X == B) + { + const struct esp32c3_mpi_s *T = A; A = X; B = T; + } + + if (X != A) + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(X, A), cleanup); + } + + /* X should always be positive as a result of unsigned additions. + */ + + X->s = 1; + + for (j = B->n; j > 0; j--) + { + if (B->p[j - 1] != 0) + { + break; + } + } + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, j), cleanup); + + o = B->p; p = X->p; c = 0; + + /* tmp is used because it might happen that p == o + */ + + for (i = 0; i < j; i++, o++, p++) + { + tmp = *o; + *p += c; c = (*p < c); + *p += tmp; c += (*p < tmp); + } + + while (c != 0) + { + if (i >= X->n) + { + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, i + 1), cleanup); + p = X->p + i; + } + + *p += c; c = (*p < c); i++; p++; + } + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_sub_abs + * + * Description: + * Perform an unsigned subtraction of MPIs: X = |A| - |B| + * + * Input Parameters: + * X - The destination MPI + * A - The minuend + * B - The subtrahend + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_sub_abs(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B) +{ + struct esp32c3_mpi_s TB; + int ret; + size_t n; + uint32_t carry; + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + DEBUGASSERT(B != NULL); + + esp32c3_mpi_init(&TB); + + if (X == B) + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&TB, B), cleanup); + B = &TB; + } + + if (X != A) + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(X, A), cleanup); + } + + /* X should always be positive as a result of unsigned subtractions. */ + + X->s = 1; + + ret = 0; + + for (n = B->n; n > 0; n--) + { + if (B->p[n - 1] != 0) + { + break; + } + } + + carry = mpi_sub_hlp(n, X->p, B->p); + if (carry != 0) + { + /* Propagate the carry to the first nonzero limb of X. */ + + for (; n < X->n && X->p[n] == 0; n++) + { + --X->p[n]; + } + + /* If we ran out of space for the carry, it means that the result + * is negative. + */ + + if (n == X->n) + { + ret = ESP32C3_ERR_MPI_NEGATIVE_VALUE; + goto cleanup; + } + + --X->p[n]; + } + +cleanup: + + esp32c3_mpi_free(&TB); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_add_mpi + * + * Description: + * Perform a signed addition of MPIs: X = A + B + * + * Input Parameters: + * X - The destination MPI + * A - The first summand + * B - The second summand + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_add_mpi(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B) +{ + int ret, s; + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + DEBUGASSERT(B != NULL); + + s = A->s; + if (A->s * B->s < 0) + { + if (esp32c3_mpi_cmp_abs(A, B) >= 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_abs(X, A, B), cleanup); + X->s = s; + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_abs(X, B, A), cleanup); + X->s = -s; + } + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_add_abs(X, A, B), cleanup); + X->s = s; + } + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_sub_mpi + * + * Description: + * Perform a signed subtraction of MPIs: X = A - B + * + * Input Parameters: + * X - The destination MPI + * A - The minuend + * B - The subtrahend + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_sub_mpi(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B) +{ + int ret, s; + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + DEBUGASSERT(B != NULL); + + s = A->s; + if (A->s * B->s > 0) + { + if (esp32c3_mpi_cmp_abs(A, B) >= 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_abs(X, A, B), cleanup); + X->s = s; + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_abs(X, B, A), cleanup); + X->s = -s; + } + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_add_abs(X, A, B), cleanup); + X->s = s; + } + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_add_int + * + * Description: + * Perform a signed addition of an MPI and an integer: X = A + b + * + * Input Parameters: + * X - The destination MPI + * A - The first summand + * b - The second summand + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_add_int(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + int32_t b) +{ + struct esp32c3_mpi_s _B; + uint32_t p[1]; + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + + p[0] = (b < 0) ? -b : b; + _B.s = (b < 0) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return (esp32c3_mpi_add_mpi(X, A, &_B)); +} + +/**************************************************************************** + * Name: esp32c3_mpi_sub_int + * + * Description: + * Perform a signed subtraction of an MPI and an integer: X = A - b + * + * Input Parameters: + * X - The destination MPI + * A - The minuend + * b - The subtrahend + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_sub_int(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + int32_t b) +{ + struct esp32c3_mpi_s _B; + uint32_t p[1]; + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + + p[0] = (b < 0) ? -b : b; + _B.s = (b < 0) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return (esp32c3_mpi_sub_mpi(X, A, &_B)); +} + +/**************************************************************************** + * Name: esp32c3_mpi_mul_mpi + * + * Description: + * Perform a multiplication of two MPIs: Z = X * Y + * + * Input Parameters: + * Z - The destination MPI + * X - The first factor + * Y - The second factor + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_mul_mpi(struct esp32c3_mpi_s *Z, + const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y) +{ + int ret = 0; + size_t x_bits = esp32c3_mpi_bitlen(X); + size_t y_bits = esp32c3_mpi_bitlen(Y); + size_t x_words = bits_to_words(x_bits); + size_t y_words = bits_to_words(y_bits); + size_t z_words = bits_to_words(x_bits + y_bits); + size_t hw_words = MAX(x_words, y_words); + + /* Short-circuit eval if either argument is 0 or 1. + + * This is needed as the mpi modular division + * argument will sometimes call in here when one + * argument is too large for the hardware unit, but the other + * argument is zero or one. + */ + + if (x_bits == 0 || y_bits == 0) + { + esp32c3_mpi_lset(Z, 0); + return 0; + } + + if (x_bits == 1) + { + ret = esp32c3_mpi_copy(Z, Y); + Z->s *= X->s; + return ret; + } + + if (y_bits == 1) + { + ret = esp32c3_mpi_copy(Z, X); + Z->s *= Y->s; + return ret; + } + + /* Grow Z to result size early, avoid interim allocations */ + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(Z, z_words), cleanup); + + /* If factor is over 2048 bits, we can't use the standard + * hardware multiplier + */ + + if (hw_words * 32 > SOC_RSA_MAX_BIT_LEN / 2) + { + if (z_words * 32 <= SOC_RSA_MAX_BIT_LEN) + { + return mpi_mult_mpi_failover_mod_mult(Z, X, Y, z_words); + } + else + { + /* Still too long for the hardware unit... */ + + if (y_words > x_words) + { + return mpi_mult_mpi_overlong(Z, X, Y, y_words, z_words); + } + else + { + return mpi_mult_mpi_overlong(Z, Y, X, x_words, z_words); + } + } + } + + /* Otherwise, we can use the (faster) multiply hardware unit */ + + esp32c3_mpi_enable_hardware_hw_op(); + + esp32c3_mpi_mul_mpi_hw_op(X, Y, hw_words); + esp32c3_mpi_read_result_hw_op(Z, z_words); + + esp32c3_mpi_disable_hardware_hw_op(); + + Z->s = X->s * Y->s; + +cleanup: + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_mul_int + * + * Description: + * Perform a multiplication of an MPI with an unsigned integer: X = A * b + * + * Input Parameters: + * X - The destination MPI + * A - The first factor + * b - The second factor. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_mul_int(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + uint32_t b) +{ + struct esp32c3_mpi_s _B; + uint32_t p[1]; + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + + _B.s = 1; + _B.n = 1; + _B.p = p; + p[0] = b; + + return (esp32c3_mpi_mul_mpi(X, A, &_B)); +} + +/**************************************************************************** + * Name: esp32c3_mpi_div_mpi + * + * Description: + * Perform a division with remainder of two MPIs: A = Q * B + R + * + * Input Parameters: + * Q - The destination MPI for the quotient + * R - The destination MPI for the remainder value + * A - The dividend + * B - The divisor + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_div_mpi(struct esp32c3_mpi_s *Q, + struct esp32c3_mpi_s *R, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B) +{ + int ret; + size_t i, n, t, k; + struct esp32c3_mpi_s X, Y, Z, T1, T2; + DEBUGASSERT(A != NULL); + DEBUGASSERT(B != NULL); + + if (esp32c3_mpi_cmp_int(B, 0) == 0) + { + return ESP32C3_ERR_MPI_DIVISION_BY_ZERO; + } + + esp32c3_mpi_init(&X); + esp32c3_mpi_init(&Y); + esp32c3_mpi_init(&Z); + esp32c3_mpi_init(&T1); + esp32c3_mpi_init(&T2); + + if (esp32c3_mpi_cmp_abs(A, B) < 0) + { + if (Q != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_lset(Q, 0), cleanup); + } + + if (R != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(R, A), cleanup); + } + + return OK; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&X, A), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&Y, B), cleanup); + X.s = Y.s = 1; + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(&Z, A->n + 2), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&Z, 0), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_grow(&T1, 2), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_grow(&T2, 3), cleanup); + + k = esp32c3_mpi_bitlen(&Y) % BIL; + if (k < BIL - 1) + { + k = BIL - 1 - k; + ESP32C3_MPI_CHK(esp32c3_mpi_shift_l(&X, k), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_l(&Y, k), cleanup); + } + else + { + k = 0; + } + + n = X.n - 1; + t = Y.n - 1; + ESP32C3_MPI_CHK(esp32c3_mpi_shift_l(&Y, BIL * (n - t)), cleanup); + + while (esp32c3_mpi_cmp_mpi(&X, &Y) >= 0) + { + Z.p[n - t]++; + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&X, &X, &Y), cleanup); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&Y, BIL * (n - t)), cleanup); + + for (i = n; i > t ; i--) + { + if (X.p[i] >= Y.p[t]) + { + Z.p[i - t - 1] = ~0; + } + else + { + Z.p[i - t - 1] = esp32c3_bignum_int_div_int(X.p[i], X.p[i - 1], + Y.p[t], NULL); + } + + Z.p[i - t - 1]++; + do + { + Z.p[i - t - 1]--; + + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&T1, 0), cleanup); + T1.p[0] = (t < 1) ? 0 : Y.p[t - 1]; + T1.p[1] = Y.p[t]; + ESP32C3_MPI_CHK(esp32c3_mpi_mul_int(&T1, &T1, Z.p[i - t - 1]), + cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&T2, 0), cleanup); + T2.p[0] = (i < 2) ? 0 : X.p[i - 2]; + T2.p[1] = (i < 1) ? 0 : X.p[i - 1]; + T2.p[2] = X.p[i]; + } + while (esp32c3_mpi_cmp_mpi(&T1, &T2) > 0); + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_int(&T1, &Y, Z.p[i - t - 1]), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_l(&T1, BIL * (i - t - 1)), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&X, &X, &T1), cleanup); + + if (esp32c3_mpi_cmp_int(&X, 0) < 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&T1, &Y), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_l(&T1, BIL * (i - t - 1)), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(&X, &X, &T1), cleanup); + Z.p[i - t - 1]--; + } + } + + if (Q != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(Q, &Z), cleanup); + Q->s = A->s * B->s; + } + + if (R != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&X, k), cleanup); + X.s = A->s; + ESP32C3_MPI_CHK(esp32c3_mpi_copy(R, &X), cleanup); + + if (esp32c3_mpi_cmp_int(R, 0) == 0) + { + R->s = 1; + } + } + +cleanup: + + esp32c3_mpi_free(&X); esp32c3_mpi_free(&Y); esp32c3_mpi_free(&Z); + esp32c3_mpi_free(&T1); esp32c3_mpi_free(&T2); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_div_int + * + * Description: + * Perform a division with remainder of an MPI by an integer: A = Q * b + R + * + * Input Parameters: + * Q - The destination MPI for the quotient + * R - The destination MPI for the remainder value + * A - The dividend + * B - The divisor + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_div_int(struct esp32c3_mpi_s *Q, + struct esp32c3_mpi_s *R, + const struct esp32c3_mpi_s *A, + int32_t b) +{ + struct esp32c3_mpi_s _B; + uint32_t p[1]; + DEBUGASSERT(A != NULL); + + p[0] = (b < 0) ? -b : b; + _B.s = (b < 0) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return (esp32c3_mpi_div_mpi(Q, R, A, &_B)); +} + +/**************************************************************************** + * Name: esp32c3_mpi_mod_mpi + * + * Description: + * erform a modular reduction. R = A mod B + * + * Input Parameters: + * R - The destination MPI for the residue value + * A - The MPI to compute the residue of + * B - The base of the modular reduction + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_mod_mpi(struct esp32c3_mpi_s *R, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B) +{ + int ret; + DEBUGASSERT(R != NULL); + DEBUGASSERT(A != NULL); + DEBUGASSERT(B != NULL); + + if (esp32c3_mpi_cmp_int(B, 0) < 0) + { + return ESP32C3_ERR_MPI_NEGATIVE_VALUE; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_div_mpi(NULL, R, A, B), cleanup); + + while (esp32c3_mpi_cmp_int(R, 0) < 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(R, R, B), cleanup); + } + + while (esp32c3_mpi_cmp_mpi(R, B) >= 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(R, R, B), cleanup); + } + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_mod_int + * + * Description: + * Perform a modular reduction with respect to an integer: r = A mod b + * + * Input Parameters: + * r - The address at which to store the residue + * A - The MPI to compute the residue of + * b - The integer base of the modular reduction + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_mod_int(uint32_t *r, + const struct esp32c3_mpi_s *A, int32_t b) +{ + size_t i; + uint32_t x, y, z; + DEBUGASSERT(r != NULL); + DEBUGASSERT(A != NULL); + + if (b == 0) + { + return ESP32C3_ERR_MPI_DIVISION_BY_ZERO; + } + + if (b < 0) + { + return ESP32C3_ERR_MPI_NEGATIVE_VALUE; + } + + /* handle trivial cases */ + + if (b == 1) + { + *r = 0; + return OK; + } + + if (b == 2) + { + *r = A->p[0] & 1; + return OK; + } + + /* general case */ + + for (i = A->n, y = 0; i > 0; i--) + { + x = A->p[i - 1]; + y = (y << BIH) | (x >> BIH); + z = y / b; + y -= z * b; + + x <<= BIH; + y = (y << BIH) | (x >> BIH); + z = y / b; + y -= z * b; + } + + /* If A is negative, then the current y represents a negative value. + * Flipping it to the positive side. + */ + + if (A->s < 0 && y != 0) + { + y = b - y; + } + + *r = y; + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_mpi_exp_mod + * + * Description: + * Perform a sliding-window exponentiation: X = A^E mod N + * + * Input Parameters: + * X - The destination MPI + * A - The base of the exponentiation + * E - The exponent MPI + * N - The base for the modular reduction + * _RR - A helper MPI depending solely on \p N which can be used to + * speed-up multiple modular exponentiations for the same value + * of \p N. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_exp_mod(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *E, + const struct esp32c3_mpi_s *N, + struct esp32c3_mpi_s *_RR) +{ + int ret; + size_t wbits, wsize, one = 1; + size_t i, j, nblimbs; + size_t bufsize, nbits; + uint32_t ei, mm, state; + struct esp32c3_mpi_s RR, T, W[1 << ESP32C3_MPI_WINDOW_SIZE], apos; + int neg; + + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + DEBUGASSERT(E != NULL); + DEBUGASSERT(N != NULL); + + if (esp32c3_mpi_cmp_int(N, 0) <= 0 || (N->p[0] & 1) == 0) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + if (esp32c3_mpi_cmp_int(E, 0) < 0) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + if (esp32c3_mpi_bitlen(E) > ESP32C3_MPI_MAX_BITS || + esp32c3_mpi_bitlen(N) > ESP32C3_MPI_MAX_BITS) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + /* Init temps and window size + */ + + mpi_montg_init(&mm, N); + esp32c3_mpi_init(&RR); esp32c3_mpi_init(&T); + esp32c3_mpi_init(&apos); + memset(W, 0, sizeof(W)); + + i = esp32c3_mpi_bitlen(E); + + wsize = (i > 671) ? 6 : (i > 239) ? 5 : + (i > 79) ? 4 : (i > 23) ? 3 : 1; + +#if (ESP32C3_MPI_WINDOW_SIZE < 6) + if (wsize > ESP32C3_MPI_WINDOW_SIZE) + { + wsize = ESP32C3_MPI_WINDOW_SIZE; + } +#endif + + j = N->n + 1; + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, j), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_grow(&W[1], j), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_grow(&T, j * 2), cleanup); + + /* Compensate for negative A (and correct at the end) */ + + neg = (A->s == -1); + if (neg) + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&apos, A), cleanup); + apos.s = 1; + A = ' + } + + /* If 1st call, pre-compute R^2 mod N */ + + if (_RR == NULL || _RR->p == NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&RR, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_l(&RR, N->n * 2 * BIL), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&RR, &RR, N), cleanup); + + if (_RR != NULL) + { + memcpy(_RR, &RR, sizeof(struct esp32c3_mpi_s)); + } + } + else + { + memcpy(&RR, _RR, sizeof(struct esp32c3_mpi_s)); + } + + /* W[1] = A * R^2 * R^-1 mod N = A * R mod N */ + + if (esp32c3_mpi_cmp_mpi(A, N) >= 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&W[1], A, N), cleanup); + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&W[1], A), cleanup); + } + + mpi_montmul(&W[1], &RR, N, mm, &T); + + /* X = R^2 * R^-1 mod N = R mod N */ + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(X, &RR), cleanup); + mpi_montred(X, N, mm, &T); + + if (wsize > 1) + { + /* W[1 << (wsize - 1)] = W[1] ^ (wsize - 1) */ + + j = one << (wsize - 1); + + ESP32C3_MPI_CHK(esp32c3_mpi_grow(&W[j], N->n + 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&W[j], &W[1]), cleanup); + + for (i = 0; i < wsize - 1; i++) + { + mpi_montmul(&W[j], &W[j], N, mm, &T); + } + + /* W[i] = W[i - 1] * W[1] */ + + for (i = j + 1; i < (one << wsize); i++) + { + ESP32C3_MPI_CHK(esp32c3_mpi_grow(&W[i], N->n + 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&W[i], &W[i - 1]), cleanup); + + mpi_montmul(&W[i], &W[1], N, mm, &T); + } + } + + nblimbs = E->n; + bufsize = 0; + nbits = 0; + wbits = 0; + state = 0; + + while (1) + { + if (bufsize == 0) + { + if (nblimbs == 0) + { + break; + } + + nblimbs--; + + bufsize = sizeof(uint32_t) << 3; + } + + bufsize--; + + ei = (E->p[nblimbs] >> bufsize) & 1; + + /* skip leading 0s */ + + if (ei == 0 && state == 0) + { + continue; + } + + if (ei == 0 && state == 1) + { + /* out of window, square X */ + + mpi_montmul(X, X, N, mm, &T); + continue; + } + + /* add ei to current window */ + + state = 2; + + nbits++; + wbits |= (ei << (wsize - nbits)); + + if (nbits == wsize) + { + /* X = X^wsize R^-1 mod N */ + + for (i = 0; i < wsize; i++) + { + mpi_montmul(X, X, N, mm, &T); + } + + /* X = X * W[wbits] R^-1 mod N */ + + mpi_montmul(X, &W[wbits], N, mm, &T); + + state--; + nbits = 0; + wbits = 0; + } + } + + /* process the remaining bits */ + + for (i = 0; i < nbits; i++) + { + mpi_montmul(X, X, N, mm, &T); + + wbits <<= 1; + + if ((wbits & (one << wsize)) != 0) + mpi_montmul(X, &W[1], N, mm, &T); + } + + /* X = A^E * R * R^-1 mod N = A^E mod N */ + + mpi_montred(X, N, mm, &T); + + if (neg && E->n != 0 && (E->p[0] & 1) != 0) + { + X->s = -1; + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(X, N, X), cleanup); + } + +cleanup: + + for (i = (one << (wsize - 1)); i < (one << wsize); i++) + { + esp32c3_mpi_free(&W[i]); + } + + esp32c3_mpi_free(&W[1]); + esp32c3_mpi_free(&T); + esp32c3_mpi_free(&apos); + + if (_RR == NULL || _RR->p == NULL) + { + esp32c3_mpi_free(&RR); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_gcd + * + * Description: + * Compute the greatest common divisor: G = gcd(A, B) + * + * Input Parameters: + * G - The destination MPI + * A - The first operand + * B - The second operand + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_gcd(struct esp32c3_mpi_s *G, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B) +{ + int ret; + size_t lz, lzt; + struct esp32c3_mpi_s TG, TA, TB; + + DEBUGASSERT(G != NULL); + DEBUGASSERT(A != NULL); + DEBUGASSERT(B != NULL); + + esp32c3_mpi_init(&TG); esp32c3_mpi_init(&TA); esp32c3_mpi_init(&TB); + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&TA, A), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&TB, B), cleanup); + + lz = esp32c3_mpi_lsb(&TA); + lzt = esp32c3_mpi_lsb(&TB); + + if (lzt < lz) + { + lz = lzt; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&TA, lz), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&TB, lz), cleanup); + + TA.s = TB.s = 1; + + while (esp32c3_mpi_cmp_int(&TA, 0) != 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&TA, esp32c3_mpi_lsb(&TA)), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&TB, esp32c3_mpi_lsb(&TB)), + cleanup); + + if (esp32c3_mpi_cmp_mpi(&TA, &TB) >= 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_abs(&TA, &TA, &TB), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&TA, 1), cleanup); + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_abs(&TB, &TB, &TA), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&TB, 1), cleanup); + } + } + + ESP32C3_MPI_CHK(esp32c3_mpi_shift_l(&TB, lz), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(G, &TB), cleanup); + +cleanup: + + esp32c3_mpi_free(&TG); esp32c3_mpi_free(&TA); esp32c3_mpi_free(&TB); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_fill_random + * + * Description: + * Fill an MPI with a number of random bytes + * + * Input Parameters: + * X - The destination MPI + * size - The number of random bytes to generate + * f_rng - The RNG function to use. This must not be \c NULL + * p_rng - The RNG parameter to be passed to \p f_rng + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_fill_random(struct esp32c3_mpi_s *X, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + int ret; + size_t const limbs = CHARS_TO_LIMBS(size); + size_t const overhead = (limbs * CIL) - size; + unsigned char *XP; + + DEBUGASSERT(X != NULL); + DEBUGASSERT(f_rng != NULL); + + /* Ensure that target MPI has exactly the necessary number of limbs */ + + if (X->n != limbs) + { + esp32c3_mpi_free(X); + esp32c3_mpi_init(X); + ESP32C3_MPI_CHK(esp32c3_mpi_grow(X, limbs), cleanup); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_lset(X, 0), cleanup); + + XP = (unsigned char *) X->p; + ESP32C3_MPI_CHK(f_rng(p_rng, XP + overhead, size), cleanup); + + mpi_bigendian_to_host(X->p, limbs); + +cleanup: + return ret; +} + +/**************************************************************************** + * Name: esp32c3_mpi_inv_mod + * + * Description: + * Compute the modular inverse: X = A^-1 mod N + * + * Input Parameters: + * X - The destination MPI + * A - The MPI to calculate the modular inverse of + * N - The base of the modular inversion + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_inv_mod(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *N) +{ + int ret; + struct esp32c3_mpi_s G, TA, TU, U1, U2, TB, TV, V1, V2; + DEBUGASSERT(X != NULL); + DEBUGASSERT(A != NULL); + DEBUGASSERT(N != NULL); + + if (esp32c3_mpi_cmp_int(N, 1) <= 0) + { + return ESP32C3_ERR_MPI_BAD_INPUT_DATA; + } + + esp32c3_mpi_init(&TA); + esp32c3_mpi_init(&TU); + esp32c3_mpi_init(&U1); + esp32c3_mpi_init(&U2); + esp32c3_mpi_init(&G); + esp32c3_mpi_init(&TB); + esp32c3_mpi_init(&TV); + esp32c3_mpi_init(&V1); + esp32c3_mpi_init(&V2); + + ESP32C3_MPI_CHK(esp32c3_mpi_gcd(&G, A, N), cleanup); + + if (esp32c3_mpi_cmp_int(&G, 1) != 0) + { + ret = ESP32C3_ERR_MPI_NOT_ACCEPTABLE; + goto cleanup; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&TA, A, N), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&TU, &TA), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&TB, N), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&TV, N), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&U1, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&U2, 0), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&V1, 0), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&V2, 1), cleanup); + + do + { + while ((TU.p[0] & 1) == 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&TU, 1), cleanup); + + if ((U1.p[0] & 1) != 0 || (U2.p[0] & 1) != 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(&U1, &U1, &TB), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&U2, &U2, &TA), cleanup); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&U1, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&U2, 1), cleanup); + } + + while ((TV.p[0] & 1) == 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&TV, 1), cleanup); + + if ((V1.p[0] & 1) != 0 || (V2.p[0] & 1) != 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(&V1, &V1, &TB), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&V2, &V2, &TA), cleanup); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&V1, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&V2, 1), cleanup); + } + + if (esp32c3_mpi_cmp_mpi(&TU, &TV) >= 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&TU, &TU, &TV), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&U1, &U1, &V1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&U2, &U2, &V2), cleanup); + } + else + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&TV, &TV, &TU), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&V1, &V1, &U1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&V2, &V2, &U2), cleanup); + } + } + while (esp32c3_mpi_cmp_int(&TU, 0) != 0); + + while (esp32c3_mpi_cmp_int(&V1, 0) < 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(&V1, &V1, N), cleanup); + } + + while (esp32c3_mpi_cmp_mpi(&V1, N) >= 0) + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&V1, &V1, N), cleanup); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(X, &V1), cleanup); + +cleanup: + + esp32c3_mpi_free(&TA); + esp32c3_mpi_free(&TU); + esp32c3_mpi_free(&U1); + esp32c3_mpi_free(&U2); + esp32c3_mpi_free(&G); + esp32c3_mpi_free(&TB); + esp32c3_mpi_free(&TV); + esp32c3_mpi_free(&V1); + esp32c3_mpi_free(&V2); + + return ret; +} + +/**************************************************************************** + * Test Functions + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_BIGNUM_ACCELERATOR_TEST + +#define GCD_PAIR_COUNT 3 + +/**************************************************************************** + * Name: esp32c3_mpi_self_test + * + * Description: + * Checkup routine + * + * Input Parameters: + * verbose - The result output or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_self_test(int verbose) +{ + int ret; + int i; + struct esp32c3_mpi_s A; + struct esp32c3_mpi_s E; + struct esp32c3_mpi_s N; + struct esp32c3_mpi_s X; + struct esp32c3_mpi_s Y; + struct esp32c3_mpi_s U; + struct esp32c3_mpi_s V; + + const int gcd_pairs[GCD_PAIR_COUNT][3] = + { + { + 693, 609, 21 + }, + + { + 1764, 868, 28 + }, + + { + 768454923, 542167814, 1 + } + }; + + esp32c3_mpi_init(&A); + esp32c3_mpi_init(&E); + esp32c3_mpi_init(&N); + esp32c3_mpi_init(&X); + esp32c3_mpi_init(&Y); + esp32c3_mpi_init(&U); + esp32c3_mpi_init(&V); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&A, 16, + "EFE021C2645FD1DC586E69184AF4A31E" \ + "D5F53E93B5F123FA41680867BA110131" \ + "944FE7952E2517337780CB0DB80E61AA" \ + "E7C8DDC6C5C6AADEB34EB38A2F40D5E6"), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&E, 16, + "B2E7EFD37075B9F03FF989C7C5051C20" \ + "34D2A323810251127E7BF8625A4F49A5" \ + "F3E27F4DA8BD59C47D6DAABA4C8127BD" \ + "5B5C25763222FEFCCFC38B832366C29E"), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&N, 16, + "0066A198186C18C10B2F5ED9B522752A" \ + "9830B69916E535C8F047518A889A43A5" \ + "94B6BED27A168D31D4A52F88925AA8F5"), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&X, &A, &N), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&U, 16, + "602AB7ECA597A3D6B56FF9829A5E8B85" \ + "9E857EA95A03512E2BAE7391688D264A" \ + "A5663B0341DB9CCFD2C4C5F421FEC814" \ + "8001B72E848A38CAE1C65F78E56ABDEF" \ + "E12D3C039B8A02D6BE593F0BBBDA56F1" \ + "ECF677152EF804370C1A305CAF3B5BF1" \ + "30879B56C61DE584A0F53A2447A51E"), cleanup); + + if (verbose != 0) + { + syslog(LOG_INFO, " MPI test #1 (mul_mpi): "); + } + + if (esp32c3_mpi_cmp_mpi(&X, &U) != 0) + { + if (verbose != 0) + { + syslog(LOG_INFO, "failed\n"); + } + + ret = 1; + goto cleanup; + } + + if (verbose != 0) + { + syslog(LOG_INFO, "passed\n"); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_div_mpi(&X, &Y, &A, &N), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&U, 16, + "256567336059E52CAE22925474705F39A94"), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&V, 16, + "6613F26162223DF488E9CD48CC132C7A" \ + "0AC93C701B001B092E4E5B9F73BCD27B" \ + "9EE50D0657C77F374E903CDFA4C642"), cleanup); + + if (verbose != 0) + { + syslog(LOG_INFO, " MPI test #2 (div_mpi): "); + } + + if (esp32c3_mpi_cmp_mpi(&X, &U) != 0 || + esp32c3_mpi_cmp_mpi(&Y, &V) != 0) + { + if (verbose != 0) + { + syslog(LOG_INFO, "failed\n"); + } + + ret = 1; + goto cleanup; + } + + if (verbose != 0) + { + syslog(LOG_INFO, "passed\n"); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_exp_mod(&X, &A, &E, &N, NULL), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&U, 16, + "36E139AEA55215609D2816998ED020BB" \ + "BD96C37890F65171D948E9BC7CBAA4D9" \ + "325D24D6A3C12710F10A09FA08AB87"), cleanup); + + if (verbose != 0) + { + syslog(LOG_INFO, " MPI test #3 (exp_mod): "); + } + + if (esp32c3_mpi_cmp_mpi(&X, &U) != 0) + { + if (verbose != 0) + { + syslog(LOG_INFO, "failed\n"); + } + + ret = 1; + goto cleanup; + } + + if (verbose != 0) + { + syslog(LOG_INFO, "passed\n"); + } + + ESP32C3_MPI_CHK(esp32c3_mpi_inv_mod(&X, &A, &N), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&U, 16, + "003A0AAEDD7E784FC07D8F9EC6E3BFD5" \ + "C3DBA76456363A10869622EAC2DD84EC" \ + "C5B8A74DAC4D09E03B5E0BE779F2DF61"), cleanup); + + if (verbose != 0) + { + syslog(LOG_INFO, " MPI test #4 (inv_mod): "); + } + + if (esp32c3_mpi_cmp_mpi(&X, &U) != 0) + { + if (verbose != 0) + { + syslog(LOG_INFO, "failed\n"); + } + + ret = 1; + goto cleanup; + } + + if (verbose != 0) + { + syslog(LOG_INFO, "passed\n"); + } + + if (verbose != 0) + { + syslog(LOG_INFO, " MPI test #5 (simple gcd): "); + } + + for (i = 0; i < GCD_PAIR_COUNT; i++) + { + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&X, gcd_pairs[i][0]), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_lset(&Y, gcd_pairs[i][1]), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_gcd(&A, &X, &Y), cleanup); + + if (esp32c3_mpi_cmp_int(&A, gcd_pairs[i][2]) != 0) + { + if (verbose != 0) + { + syslog(LOG_INFO, "failed at %d\n", i); + } + + ret = 1; + goto cleanup; + } + } + + if (verbose != 0) + { + syslog(LOG_INFO, "passed\n"); + } + +cleanup: + + if (ret != 0 && verbose != 0) + { + syslog(LOG_INFO, "Unexpected error, return code = %08X\n", ret); + } + + esp32c3_mpi_free(&A); + esp32c3_mpi_free(&E); + esp32c3_mpi_free(&N); + esp32c3_mpi_free(&X); + esp32c3_mpi_free(&Y); + esp32c3_mpi_free(&U); + esp32c3_mpi_free(&V); + + if (verbose != 0) + { + syslog(LOG_INFO, "\n"); + } + + return ret; +} + +#endif /* CONFIG_ESP32C3_BIGNUM_ACCELERATOR_TEST */ + +#endif /* CONFIG_ESP32C3_BIGNUM_ACCELERATOR */ + diff --git a/arch/risc-v/src/esp32c3/esp32c3_bignum.h b/arch/risc-v/src/esp32c3/esp32c3_bignum.h new file mode 100644 index 00000000000..3ee4a58713e --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_bignum.h @@ -0,0 +1,892 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_bignum.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BIGNUM_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BIGNUM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +#define ESP32C3_ERR_MPI_FILE_IO_ERROR -0x0002 /**< An error occurred while reading from or writing to a file. */ +#define ESP32C3_ERR_MPI_BAD_INPUT_DATA -0x0004 /**< Bad input parameters to function. */ +#define ESP32C3_ERR_MPI_INVALID_CHARACTER -0x0006 /**< There is an invalid character in the digit string. */ +#define ESP32C3_ERR_MPI_BUFFER_TOO_SMALL -0x0008 /**< The buffer is too small to write to. */ +#define ESP32C3_ERR_MPI_NEGATIVE_VALUE -0x000A /**< The input arguments are negative or result in illegal output. */ +#define ESP32C3_ERR_MPI_DIVISION_BY_ZERO -0x000C /**< The input argument for division is zero, which is not allowed. */ +#define ESP32C3_ERR_MPI_NOT_ACCEPTABLE -0x000E /**< The input arguments are not acceptable. */ +#define ESP32C3_ERR_MPI_ALLOC_FAILED -0x0010 /**< Memory allocation failed. */ + +#define ESP32C3_MPI_CHK(f, a) \ + do \ + { \ + ret = (f); \ + if (ret != 0) \ + { \ + goto a; \ + } \ + } \ + while(0) + +/* Maximum size MPIs are allowed to grow to in number of limbs. */ +#define ESP32C3_MPI_MAX_LIMBS 10000 + +/* Maximum window size used for modular exponentiation */ +#define ESP32C3_MPI_WINDOW_SIZE 6 + +/* Maximum size of MPIs allowed in bits and bytes for user-MPIs. */ +#define ESP32C3_MPI_MAX_SIZE 1024 + +/**< Maximum number of bits for usable MPIs. */ +#define ESP32C3_MPI_MAX_BITS (8 * ESP32C3_MPI_MAX_SIZE) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* MPI structure */ + +struct esp32c3_mpi_s +{ + int s; /* Sign: -1 if the mpi is negative, 1 otherwise */ + size_t n; /* total number of limbs */ + uint32_t *p; /* pointer to limbs */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_mpi_init + * + * Description: + * Initialize an MPI context + * + * Input Parameters: + * X - The MPI context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_mpi_init(struct esp32c3_mpi_s *X); + +/**************************************************************************** + * Name: esp32c3_mpi_free + * + * Description: + * Frees the components of an MPI context + * + * Input Parameters: + * X - The MPI context to be cleared + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_mpi_free(struct esp32c3_mpi_s *X); + +/**************************************************************************** + * Name: esp32c3_mpi_grow + * + * Description: + * Enlarge an MPI to the specified number of limbs + * + * Input Parameters: + * X - The MPI context to grow + * nblimbs - The target number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_grow(struct esp32c3_mpi_s *X, size_t nblimbs); + +/**************************************************************************** + * Name: esp32c3_mpi_shrink + * + * Description: + * Resizes an MPI downwards, keeping at least the specified number of limbs + * + * Input Parameters: + * X - The MPI context to shrink + * nblimbs - The minimum number of limbs + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_shrink(struct esp32c3_mpi_s *X, size_t nblimbs); + +/**************************************************************************** + * Name: esp32c3_mpi_copy + * + * Description: + * Copy the contents of Y into X + * + * Input Parameters: + * X - The destination MPI + * Y - The source MPI + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_copy(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y); + +/**************************************************************************** + * Name: esp32c3_mpi_swap + * + * Description: + * Swap the contents of X and Y + * + * Input Parameters: + * X - The first MPI + * nblimbs - The second MPI + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_mpi_swap(struct esp32c3_mpi_s *X, + struct esp32c3_mpi_s *Y); + +/**************************************************************************** + * Name: esp32c3_mpi_safe_cond_assign + * + * Description: + * Perform a safe conditional copy of MPI which doesn't + * reveal whether the condition was true or not. + * + * Input Parameters: + * X - The MPI to conditionally assign to + * Y - The MPI to be assigned from + * assign - The condition deciding whether perform the assignment or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_safe_cond_assign(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y, + unsigned char assign); + +/**************************************************************************** + * Name: esp32c3_mpi_safe_cond_swap + * + * Description: + * Perform a safe conditional swap which doesn't + * reveal whether the condition was true or not. + * + * Input Parameters: + * X - The first MPI + * Y - The second MPI + * swap - The condition deciding whether to perform the swap or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_safe_cond_swap(struct esp32c3_mpi_s *X, + struct esp32c3_mpi_s *Y, + unsigned char assign); + +/**************************************************************************** + * Name: esp32c3_mpi_lset + * + * Description: + * Set value from integer + * + * Input Parameters: + * X - The MPI to set + * z - The value to use + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_lset(struct esp32c3_mpi_s *X, int32_t z); + +/**************************************************************************** + * Name: esp32c3_mpi_get_bit + * + * Description: + * Get a specific bit from an MPI + * + * Input Parameters: + * X - The MPI context to query + * pos - Zero-based index of the bit to query + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_get_bit(const struct esp32c3_mpi_s *X, size_t pos); + +/**************************************************************************** + * Name: esp32c3_mpi_set_bit + * + * Description: + * Modify a specific bit in an MPI + * + * Input Parameters: + * X - The MPI context to modify + * pos - Zero-based index of the bit to modify + * val - The desired value of bit + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_set_bit(struct esp32c3_mpi_s *X, + size_t pos, unsigned char val); + +/**************************************************************************** + * Name: esp32c3_mpi_lsb + * + * Description: + * Return the number of bits of value + * + * Input Parameters: + * X - The MPI context to query + * + * Returned Value: + * The number of bits of value. + * + ****************************************************************************/ + +size_t esp32c3_mpi_lsb(const struct esp32c3_mpi_s *X); + +/**************************************************************************** + * Name: esp32c3_mpi_bitlen + * + * Description: + * Return the number of bits up to and including the most + * significant bit of value + * + * Input Parameters: + * X - The MPI context to query + * + * Returned Value: + * The number of bits up and including the most significant bit of value. + * + ****************************************************************************/ + +size_t esp32c3_mpi_bitlen(const struct esp32c3_mpi_s *X); + +/**************************************************************************** + * Name: esp32c3_mpi_size + * + * Description: + * Return the total size of an MPI value in bytes + * + * Input Parameters: + * X - The MPI context to query + * + * Returned Value: + * The least number of bytes capable of storing the absolute value. + * + ****************************************************************************/ + +size_t esp32c3_mpi_size(const struct esp32c3_mpi_s *X); + +/**************************************************************************** + * Name: esp32c3_mpi_read_string + * + * Description: + * Import from an ASCII string + * + * Input Parameters: + * X - The destination MPI + * radix - The numeric base of the input string + * s - Null-terminated string buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_read_string(struct esp32c3_mpi_s *X, + int radix, const char *s); + +/**************************************************************************** + * Name: esp32c3_mpi_write_string + * + * Description: + * Export an MPI to an ASCII string + * + * Input Parameters: + * X - The source MPI + * radix - The numeric base of the output string + * buf - The buffer to write the string to + * buflen - The available size in Bytes of buf + * olen - The address at which to store the length of the string written + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_write_string(const struct esp32c3_mpi_s *X, int radix, + char *buf, size_t buflen, size_t *olen); + +/**************************************************************************** + * Name: esp32c3_mpi_read_binary + * + * Description: + * Import an MPI from unsigned big endian binary data + * + * Input Parameters: + * X - The destination MPI + * buf - The input buffer + * buflen - The length of the input buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_read_binary(struct esp32c3_mpi_s *X, + const unsigned char *buf, size_t buflen); + +/**************************************************************************** + * Name: esp32c3_mpi_write_binary + * + * Description: + * Export X into unsigned binary data, big endian + * + * Input Parameters: + * X - The source MPI + * buf - The output buffer + * buflen - The length of the output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_write_binary(const struct esp32c3_mpi_s *X, + unsigned char *buf, size_t buflen); + +/**************************************************************************** + * Name: esp32c3_mpi_shift_l + * + * Description: + * Perform a left-shift on an MPI: X <<= count + * + * Input Parameters: + * X - The MPI to shift + * count - The number of bits to shift by + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_shift_l(struct esp32c3_mpi_s *X, size_t count); + +/**************************************************************************** + * Name: esp32c3_mpi_shift_r + * + * Description: + * Perform a right-shift on an MPI: X >>= count + * + * Input Parameters: + * X - The MPI to shift + * count - The number of bits to shift by + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_shift_r(struct esp32c3_mpi_s *X, size_t count); + +/**************************************************************************** + * Name: esp32c3_mpi_cmp_abs + * + * Description: + * Compare the absolute values of two MPIs + * + * Input Parameters: + * X - The left-hand MPI + * Y - The right-hand MPI + * + * Returned Value: + * 1 if \p `|X|` is greater than \p `|Y|`. + * -1 if \p `|X|` is lesser than \p `|Y|`. + * 0 if \p `|X|` is equal to \p `|Y|`. + * + ****************************************************************************/ + +int esp32c3_mpi_cmp_abs(const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y); + +/**************************************************************************** + * Name: esp32c3_mpi_cmp_mpi + * + * Description: + * Compare two MPIs. + * + * Input Parameters: + * X - The left-hand MPI + * Y - The right-hand MPI + * + * Returned Value: + * 1 if \p `X` is greater than \p `Y`. + * -1 if \p `X` is lesser than \p `Y`. + * 0 if \p `X` is equal to \p `Y`. + * + ****************************************************************************/ + +int esp32c3_mpi_cmp_mpi(const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y); + +/**************************************************************************** + * Name: esp32c3_mpi_lt_mpi_ct + * + * Description: + * Check if an MPI is less than the other in constant time + * + * Input Parameters: + * X - The left-hand MPI + * Y - The right-hand MPI + * ret - The result of the comparison: + * 1 if \p X is less than \p Y. + * 0 if \p X is greater than or equal to \p Y. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_lt_mpi_ct(const struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *Y, + unsigned *ret); + +/**************************************************************************** + * Name: esp32c3_mpi_cmp_int + * + * Description: + * Compare an MPI with an integer + * + * Input Parameters: + * X - The left-hand MPI + * z - The integer value to compare \p X to + * + * Returned Value: + * \c 1 if \p X is greater than \p z. + * \c -1 if \p X is lesser than \p z. + * \c 0 if \p X is equal to \p z. + * + ****************************************************************************/ + +int esp32c3_mpi_cmp_int(const struct esp32c3_mpi_s *X, int32_t z); + +/**************************************************************************** + * Name: esp32c3_mpi_add_abs + * + * Description: + * Perform an unsigned addition of MPIs: X = |A| + |B| + * + * Input Parameters: + * X - The left-hand MPI + * z - The integer value to compare \p X to. + * + * Returned Value: + * \c 1 if \p X is greater than \p z. + * \c -1 if \p X is lesser than \p z. + * \c 0 if \p X is equal to \p z. + * + ****************************************************************************/ + +int esp32c3_mpi_add_abs(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B); + +/**************************************************************************** + * Name: esp32c3_mpi_sub_abs + * + * Description: + * Perform an unsigned subtraction of MPIs: X = |A| - |B| + * + * Input Parameters: + * X - The destination MPI + * A - The minuend + * B - The subtrahend + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_sub_abs(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B); + +/**************************************************************************** + * Name: esp32c3_mpi_add_mpi + * + * Description: + * Perform a signed addition of MPIs: X = A + B + * + * Input Parameters: + * X - The destination MPI + * A - The first summand + * B - The second summand + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_add_mpi(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B); + +/**************************************************************************** + * Name: esp32c3_mpi_sub_mpi + * + * Description: + * Perform a signed subtraction of MPIs: X = A - B + * + * Input Parameters: + * X - The destination MPI + * A - The minuend + * B - The subtrahend + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_sub_mpi(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B); + +/**************************************************************************** + * Name: esp32c3_mpi_add_int + * + * Description: + * Perform a signed addition of an MPI and an integer: X = A + b + * + * Input Parameters: + * X - The destination MPI + * A - The first summand + * b - The second summand + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_add_int(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + int32_t b); + +/**************************************************************************** + * Name: esp32c3_mpi_sub_int + * + * Description: + * Perform a signed subtraction of an MPI and an integer: X = A - b + * + * Input Parameters: + * X - The destination MPI + * A - The minuend + * b - The subtrahend + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_sub_int(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + int32_t b); + +/**************************************************************************** + * Name: esp32c3_mpi_mul_mpi + * + * Description: + * Perform a multiplication of two MPIs: Z = X * Y + * + * Input Parameters: + * Z - The destination MPI + * X - The first factor + * Y - The second factor + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_mul_mpi(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B); + +/**************************************************************************** + * Name: esp32c3_mpi_mul_int + * + * Description: + * Perform a multiplication of an MPI with an unsigned integer: X = A * b + * + * Input Parameters: + * X - The destination MPI + * A - The first factor + * b - The second factor. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_mul_int(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + uint32_t b); + +/**************************************************************************** + * Name: esp32c3_mpi_div_mpi + * + * Description: + * Perform a division with remainder of two MPIs: A = Q * B + R + * + * Input Parameters: + * Q - The destination MPI for the quotient + * R - The destination MPI for the remainder value + * A - The dividend + * B - The divisor + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_div_mpi(struct esp32c3_mpi_s *Q, + struct esp32c3_mpi_s *R, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B); + +/**************************************************************************** + * Name: esp32c3_mpi_div_int + * + * Description: + * Perform a division with remainder of an MPI by an integer: A = Q * b + R + * + * Input Parameters: + * Q - The destination MPI for the quotient + * R - The destination MPI for the remainder value + * A - The dividend + * B - The divisor + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_div_int(struct esp32c3_mpi_s *Q, + struct esp32c3_mpi_s *R, + const struct esp32c3_mpi_s *A, + int32_t b); + +/**************************************************************************** + * Name: esp32c3_mpi_mod_mpi + * + * Description: + * erform a modular reduction. R = A mod B + * + * Input Parameters: + * R - The destination MPI for the residue value + * A - The MPI to compute the residue of + * B - The base of the modular reduction + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_mod_mpi(struct esp32c3_mpi_s *R, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B); + +/**************************************************************************** + * Name: esp32c3_mpi_mod_int + * + * Description: + * Perform a modular reduction with respect to an integer: r = A mod b + * + * Input Parameters: + * r - The address at which to store the residue + * A - The MPI to compute the residue of + * b - The integer base of the modular reduction + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_mod_int(uint32_t *r, + const struct esp32c3_mpi_s *A, + int32_t b); + +/**************************************************************************** + * Name: esp32c3_mpi_exp_mod + * + * Description: + * Perform a sliding-window exponentiation: X = A^E mod N + * + * Input Parameters: + * X - The destination MPI + * A - The base of the exponentiation + * E - The exponent MPI + * N - The base for the modular reduction + * _RR - A helper MPI depending solely on \p N which can be used to + * speed-up multiple modular exponentiations for the same value + * of \p N. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_exp_mod(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *E, + const struct esp32c3_mpi_s *N, + struct esp32c3_mpi_s *_RR); + +/**************************************************************************** + * Name: esp32c3_mpi_gcd + * + * Description: + * Compute the greatest common divisor: G = gcd(A, B) + * + * Input Parameters: + * G - The destination MPI + * A - The first operand + * B - The second operand + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_gcd(struct esp32c3_mpi_s *G, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *B); + +/**************************************************************************** + * Name: esp32c3_mpi_fill_random + * + * Description: + * Fill an MPI with a number of random bytes + * + * Input Parameters: + * X - The destination MPI + * size - The number of random bytes to generate + * f_rng - The RNG function to use. This must not be \c NULL + * p_rng - The RNG parameter to be passed to \p f_rng + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_fill_random(struct esp32c3_mpi_s *X, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/**************************************************************************** + * Name: esp32c3_mpi_inv_mod + * + * Description: + * Compute the modular inverse: X = A^-1 mod N + * + * Input Parameters: + * X - The destination MPI + * A - The MPI to calculate the modular inverse of + * N - The base of the modular inversion + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_inv_mod(struct esp32c3_mpi_s *X, + const struct esp32c3_mpi_s *A, + const struct esp32c3_mpi_s *N); + +#ifdef CONFIG_ESP32C3_BIGNUM_ACCELERATOR_TEST + +/**************************************************************************** + * Name: esp32c3_mpi_self_test + * + * Description: + * Checkup routine + * + * Input Parameters: + * verbose - The result output or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_mpi_self_test(int verbose); + +#endif + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BIGNUM_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble.c b/arch/risc-v/src/esp32c3/esp32c3_ble.c new file mode 100644 index 00000000000..47bab8b21f2 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_ble.c @@ -0,0 +1,337 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_ble.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_UART_BTH4) + #include +#endif + +#include "esp32c3_ble_adapter.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* BLE packet buffer max number */ + +#define BLE_BUF_NUM CONFIG_ESP32C3_BLE_PKTBUF_NUM + +/* BLE packet buffer max size */ + +#define BLE_BUF_SIZE 1024 + +/* Low-priority work queue process RX/TX */ + +#define BLE_WORK LPWORK + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct esp32c3_ble_priv_s +{ + struct bt_driver_s drv; /* NuttX BT/BLE driver data */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int esp32c3_ble_open(struct bt_driver_s *drv); +static int esp32c3_ble_send(struct bt_driver_s *drv, + enum bt_buf_type_e type, + void *data, size_t len); +static void esp32c3_ble_close(struct bt_driver_s *drv); + +static void esp32c3_ble_send_ready(void); +static int esp32c3_ble_recv_cb(uint8_t *data, uint16_t len); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct esp32c3_ble_priv_s g_ble_priv = +{ + .drv = + { + .head_reserve = H4_HEADER_SIZE, + .open = esp32c3_ble_open, + .send = esp32c3_ble_send, + .close = esp32c3_ble_close + } +}; + +static esp_vhci_host_callback_t vhci_host_cb = +{ + .notify_host_send_available = esp32c3_ble_send_ready, + .notify_host_recv = esp32c3_ble_recv_cb +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ble_send_ready + * + * Description: + * If the controller could send HCI comand will callback this function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32c3_ble_send_ready(void) +{ +} + +/**************************************************************************** + * Name: esp32c3_ble_recv_cb + * + * Description: + * BLE receive callback function when BLE hardware receive packet + * + * Input Parameters: + * data - BLE packet data pointer + * len - BLE packet length + * + * Returned Value: + * 0 on success or a negated value on failure. + * + ****************************************************************************/ + +static int esp32c3_ble_recv_cb(uint8_t *data, uint16_t len) +{ + int ret; + bool valid; + enum bt_buf_type_e type; + struct esp32c3_ble_priv_s *priv = &g_ble_priv; + + switch (data[0]) + { + case H4_EVT: + type = BT_EVT; + valid = true; + break; + case H4_ACL: + type = BT_ACL_IN; + valid = true; + break; + case H4_ISO: + type = BT_ISO_IN; + valid = true; + break; + default: + valid = false; + break; + } + + if (!valid) + { + ret = ERROR; + } + else + { + /* send packet to host */ + + ret = bt_netdev_receive(&priv->drv, type, + &data[H4_HEADER_SIZE], + len - H4_HEADER_SIZE); + if (ret < 0) + { + wlerr("Failed to receive ret=%d\n", ret); + } + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_ble_send + * + * Description: + * ESP32-C3 BLE send callback function for BT driver. + * + * Input Parameters: + * drv - BT driver pointer + * type - BT packet type + * data - BT packte data buffer pointer + * len - BT packte length + * + * Returned Value: + * Sent bytes on success or a negated value on failure. + * + ****************************************************************************/ + +static int esp32c3_ble_send(struct bt_driver_s *drv, + enum bt_buf_type_e type, + void *data, size_t len) +{ + uint8_t *hdr = (uint8_t *)data - drv->head_reserve; + + if ((len + H4_HEADER_SIZE) > BLE_BUF_SIZE) + { + return -EINVAL; + } + + if (type == BT_CMD) + { + *hdr = H4_CMD; + } + else if (type == BT_ACL_OUT) + { + *hdr = H4_ACL; + } + else if (type == BT_ISO_OUT) + { + *hdr = H4_ISO; + } + else + { + return -EINVAL; + } + + if (esp32c3_vhci_host_check_send_available()) + { + esp32c3_vhci_host_send_packet(hdr, len + drv->head_reserve); + } + + return len; +} + +/**************************************************************************** + * Name: esp32c3_ble_close + * + * Description: + * ESP32-C3 BLE close callback function for BT driver. + * + * Input Parameters: + * drv - BT driver pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32c3_ble_close(struct bt_driver_s *drv) +{ +} + +/**************************************************************************** + * Name: esp32c3_ble_open + * + * Description: + * ESP32-C3 BLE open callback function for BT driver. + * + * Input Parameters: + * drv - BT driver pointer + * + * Returned Value: + * OK on success or a negated value on failure. + * + ****************************************************************************/ + +static int esp32c3_ble_open(struct bt_driver_s *drv) +{ + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ble_initialize + * + * Description: + * Init BT controller + * + * Input Parameters: + * None + * + * Returned Value: + * success or fail + * + ****************************************************************************/ + +int esp32c3_ble_initialize(void) +{ + int ret; + + ret = esp32c3_bt_controller_init(); + if (ret) + { + wlerr("Failed to initialize BLE ret=%d\n", ret); + return ERROR; + } + + ret = esp32c3_bt_controller_enable(ESP_BT_MODE_BLE); + if (ret) + { + wlerr("Failed to Enable BLE ret=%d\n", ret); + return ERROR; + } + + ret = esp32c3_vhci_register_callback(&vhci_host_cb); + if (ret) + { + wlerr("Failed to register BLE callback ret=%d\n", ret); + return ERROR; + } + +#if defined(CONFIG_UART_BTH4) + ret = uart_bth4_register(CONFIG_ESP32C3_BLE_TTY_NAME, &g_ble_priv.drv); +#else + ret = bt_netdev_register(&g_ble_priv.drv); +#endif + if (ret < 0) + { + wlerr("bt_netdev_register error: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble.h b/arch/risc-v/src/esp32c3/esp32c3_ble.h new file mode 100644 index 00000000000..d1cd2c9bd1e --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_ble.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_ble.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ble_initialize + * + * Description: + * Init BT controller + * + * Input Parameters: + * None + * + * Returned Value: + * success or fail + * + ****************************************************************************/ + +int esp32c3_ble_initialize(void); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c b/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c new file mode 100644 index 00000000000..21926fb2f96 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c @@ -0,0 +1,2458 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hardware/esp32c3_syscon.h" +#include "espidf_wifi.h" +#include "esp32c3.h" +#include "esp32c3_attr.h" +#include "esp32c3_irq.h" +#include "esp32c3_rt_timer.h" +#include "esp32c3_ble_adapter.h" + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST +# include "esp_coexist_internal.h" +# include "esp_coexist_adapter.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OSI_FUNCS_TIME_BLOCKING 0xffffffff +#define OSI_VERSION 0x00010006 +#define OSI_MAGIC_VALUE 0xfadebead + +#ifdef CONFIG_PM +#define BTDM_MIN_TIMER_UNCERTAINTY_US (1800) + +/* Sleep and wakeup interval control */ + +#define BTDM_MIN_SLEEP_DURATION (24) /* threshold of interval in half slots to allow to fall into modem sleep */ +#define BTDM_MODEM_WAKE_UP_DELAY (8) /* delay in half slots of modem wake up procedure, including re-enable PHY/RF */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* BLE message queue private data */ + +struct mq_adpt_s +{ + struct file mq; /* Message queue handle */ + uint32_t msgsize; /* Message size */ + char name[16]; /* Message queue name */ +}; + +/* BLE interrupt adapter private data */ + +struct irq_adpt_s +{ + void (*func)(void *arg); /* Interrupt callback function */ + void *arg; /* Interrupt private data */ +}; + +/* BLE low power control struct */ + +typedef enum btdm_lpclk_sel_e +{ + BTDM_LPCLK_SEL_XTAL = 0, + BTDM_LPCLK_SEL_XTAL32K = 1, + BTDM_LPCLK_SEL_RTC_SLOW = 2, + BTDM_LPCLK_SEL_8M = 3, +} btdm_lpclk_sel_t; + +typedef enum btdm_vnd_ol_sig_e +{ + BTDM_VND_OL_SIG_WAKEUP_TMR, + BTDM_VND_OL_SIG_NUM, +} btdm_vnd_ol_sig_t; + +typedef struct btdm_lpcntl_s +{ + bool enable; /* whether low power mode is required */ + bool wakeup_timer_required; /* whether system timer is needed */ + btdm_lpclk_sel_t lpclk_sel; /* low power clock source */ +} btdm_lpcntl_t; + +/* low power control status */ + +typedef struct btdm_lpstat_s +{ + bool pm_lock_released; /* whether power management lock is released */ + bool phy_enabled; /* whether phy is switched on */ + bool wakeup_timer_started; /* whether wakeup timer is started */ +} btdm_lpstat_t; + +#ifdef CONFIG_PM +/* wakeup request sources */ + +enum btdm_wakeup_src_e +{ + BTDM_ASYNC_WAKEUP_SRC_VHCI, + BTDM_ASYNC_WAKEUP_SRC_DISA, + BTDM_ASYNC_WAKEUP_SRC_TMR, + BTDM_ASYNC_WAKEUP_SRC_MAX, +}; +#endif + +/* prototype of function to handle vendor dependent signals */ + +typedef void (* btdm_vnd_ol_task_func_t)(void *param); + +/* VHCI function interface */ + +typedef struct vhci_host_callback_s +{ + void (*notify_host_send_available)(void); /* callback used to notify that the host can send packet to controller */ + int (*notify_host_recv)(uint8_t *data, uint16_t len); /* callback used to notify that the controller has a packet to send to the host */ +} vhci_host_callback_t; + +/* DRAM region */ + +typedef struct btdm_dram_available_region_s +{ + esp_bt_mode_t mode; + intptr_t start; + intptr_t end; +} btdm_dram_available_region_t; + +typedef void (* osi_intr_handler)(void); + +/* BLE OS function */ + +struct osi_funcs_s +{ + uint32_t _magic; + uint32_t _version; + void (*_interrupt_set)(int cpu_no, int intr_source, + int interrupt_no, int interrpt_prio); + void (*_interrupt_clear)(int interrupt_source, int interrupt_no); + void (*_interrupt_handler_set)(int interrupt_no, void * fn, void *arg); + void (*_interrupt_disable)(void); + void (*_interrupt_restore)(void); + void (*_task_yield)(void); + void (*_task_yield_from_isr)(void); + void *(*_semphr_create)(uint32_t max, uint32_t init); + void (*_semphr_delete)(void *semphr); + int (*_semphr_take_from_isr)(void *semphr, void *hptw); + int (*_semphr_give_from_isr)(void *semphr, void *hptw); + int (*_semphr_take)(void *semphr, uint32_t block_time_ms); + int (*_semphr_give)(void *semphr); + void *(*_mutex_create)(void); + void (*_mutex_delete)(void *mutex); + int (*_mutex_lock)(void *mutex); + int (*_mutex_unlock)(void *mutex); + void *(* _queue_create)(uint32_t queue_len, uint32_t item_size); + void (* _queue_delete)(void *queue); + int (* _queue_send)(void *queue, void *item, uint32_t block_time_ms); + int (* _queue_send_from_isr)(void *queue, void *item, void *hptw); + int (* _queue_recv)(void *queue, void *item, uint32_t block_time_ms); + int (* _queue_recv_from_isr)(void *queue, void *item, void *hptw); + int (* _task_create)(void *task_func, const char *name, + uint32_t stack_depth, void *param, uint32_t prio, + void *task_handle, uint32_t core_id); + void (* _task_delete)(void *task_handle); + bool (* _is_in_isr)(void); + int (* _cause_sw_intr_to_core)(int core_id, int intr_no); + void *(* _malloc)(size_t size); + void *(* _malloc_internal)(size_t size); + void (* _free)(void *p); + int (* _read_efuse_mac)(uint8_t mac[6]); + void (* _srand)(unsigned int seed); + int (* _rand)(void); + uint32_t (* _btdm_lpcycles_2_hus)(uint32_t cycles, uint32_t *error_corr); + uint32_t (* _btdm_hus_2_lpcycles)(uint32_t us); + bool (* _btdm_sleep_check_duration)(int32_t *slot_cnt); + void (* _btdm_sleep_enter_phase1)(uint32_t lpcycles); /* called when interrupt is disabled */ + void (* _btdm_sleep_enter_phase2)(void); + void (* _btdm_sleep_exit_phase1)(void); /* called from ISR */ + void (* _btdm_sleep_exit_phase2)(void); /* called from ISR */ + void (* _btdm_sleep_exit_phase3)(void); /* called from task */ + void (* _coex_wifi_sleep_set)(bool sleep); + int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high); + void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status); + void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status); + void (* _interrupt_on)(int intr_num); + void (* _interrupt_off)(int intr_num); + void (* _esp_hw_power_down)(void); + void (* _esp_hw_power_up)(void); + void (* _ets_backup_dma_copy)(uint32_t reg, + uint32_t mem_addr, uint32_t num, + bool to_rem); +}; + +/**************************************************************************** + * Private Function + ****************************************************************************/ + +static void interrupt_set_wrapper(int cpu_no, int intr_source, + int intr_num, int intr_prio); +static void interrupt_clear_wrapper(int intr_source, int intr_num); +static void interrupt_handler_set_wrapper(int n, void *fn, void *arg); +static void IRAM_ATTR interrupt_disable(void); +static void IRAM_ATTR interrupt_restore(void); +static void IRAM_ATTR task_yield_from_isr(void); +static void *semphr_create_wrapper(uint32_t max, uint32_t init); +static void semphr_delete_wrapper(void *semphr); +static int IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw); +static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw); +static int semphr_take_wrapper(void *semphr, uint32_t block_time_ms); +static int semphr_give_wrapper(void *semphr); +static void *mutex_create_wrapper(void); +static void mutex_delete_wrapper(void *mutex); +static int mutex_lock_wrapper(void *mutex); +static int mutex_unlock_wrapper(void *mutex); +static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue, void *item, + void *hptw); +static int IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, void *item, + void *hptw); +static int task_create_wrapper(void *task_func, const char *name, + uint32_t stack_depth, void *param, + uint32_t prio, void *task_handle, + uint32_t core_id); +static void task_delete_wrapper(void *task_handle); +static bool IRAM_ATTR is_in_isr_wrapper(void); +static void *malloc_wrapper(size_t size); +static void *malloc_internal_wrapper(size_t size); +static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6]); +static void IRAM_ATTR srand_wrapper(unsigned int seed); +static int IRAM_ATTR rand_wrapper(void); +static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, + uint32_t *error_corr); +static uint32_t IRAM_ATTR btdm_hus_2_lpcycles(uint32_t us); +static void coex_wifi_sleep_set_hook(bool sleep); +static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status); +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status); +static void interrupt_on_wrapper(int intr_num); +static void interrupt_off_wrapper(int intr_num); +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size); +static int queue_send_wrapper(void *queue, void *item, + uint32_t block_time_ms); +static int queue_recv_wrapper(void *queue, void *item, + uint32_t block_time_ms); +static void queue_delete_wrapper(void *queue); + +#ifdef CONFIG_PM +static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt); +static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles); +static void btdm_sleep_enter_phase2_wrapper(void); +static void btdm_sleep_exit_phase3_wrapper(void); +#endif + +/**************************************************************************** + * Extern Functions declaration and value + ****************************************************************************/ + +extern int btdm_osi_funcs_register(void *osi_funcs); +extern void btdm_controller_rom_data_init(void); + +/* Initialise and De-initialise */ + +extern int btdm_controller_init(esp_bt_controller_config_t *config_opts); +extern void btdm_controller_deinit(void); +extern int btdm_controller_enable(esp_bt_mode_t mode); +extern void btdm_controller_disable(void); +extern uint8_t btdm_controller_get_mode(void); +extern const char *btdm_controller_get_compile_version(void); +extern void btdm_rf_bb_init_phase2(void); /* shall be called after PHY/RF is enabled */ + +/* Sleep */ + +extern void btdm_controller_enable_sleep(bool enable); +extern uint8_t btdm_controller_get_sleep_mode(void); +extern bool btdm_power_state_active(void); +extern void btdm_wakeup_request(void); +extern void btdm_in_wakeup_requesting_set(bool in_wakeup_requesting); + +/* vendor dependent tasks to be posted and handled by controller task */ + +extern int btdm_vnd_offload_task_register(btdm_vnd_ol_sig_t sig, + btdm_vnd_ol_task_func_t func); +extern int btdm_vnd_offload_task_deregister(btdm_vnd_ol_sig_t sig); +extern int btdm_vnd_offload_post_from_isr(btdm_vnd_ol_sig_t sig, + void *param, bool need_yield); +extern int btdm_vnd_offload_post(btdm_vnd_ol_sig_t sig, void *param); + +/* Low Power Clock */ + +extern bool btdm_lpclk_select_src(uint32_t sel); +extern bool btdm_lpclk_set_div(uint32_t div); +extern int btdm_hci_tl_io_event_post(int event); + +/* VHCI */ + +extern bool API_vhci_host_check_send_available(void); /* Functions in bt lib */ +extern void API_vhci_host_send_packet(uint8_t * data, uint16_t len); +extern int API_vhci_host_register_callback(const vhci_host_callback_t + *callback); + +/* TX power */ + +extern int ble_txpwr_set(int power_type, int power_level); +extern int ble_txpwr_get(int power_type); + +extern uint16_t l2c_ble_link_get_tx_buf_num(void); +extern int coex_core_ble_conn_dyn_prio_get(bool *low, bool *high); + +extern bool btdm_deep_sleep_mem_init(void); +extern void btdm_deep_sleep_mem_deinit(void); +extern void btdm_ble_power_down_dma_copy(bool copy); +extern uint8_t btdm_sleep_clock_sync(void); + +extern char _bss_start_btdm; +extern char _bss_end_btdm; +extern char _data_start_btdm; +extern char _data_end_btdm; +extern uint32_t _data_start_btdm_rom; +extern uint32_t _data_end_btdm_rom; + +extern uint32_t _bt_bss_start; +extern uint32_t _bt_bss_end; +extern uint32_t _btdm_bss_start; +extern uint32_t _btdm_bss_end; +extern uint32_t _bt_data_start; +extern uint32_t _bt_data_end; +extern uint32_t _btdm_data_start; +extern uint32_t _btdm_data_end; + +extern char _bt_tmp_bss_start; +extern char _bt_tmp_bss_end; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Controller status */ + +static DRAM_ATTR esp_bt_controller_status_t btdm_controller_status = + ESP_BT_CONTROLLER_STATUS_IDLE; + +/* low power control struct */ + +static DRAM_ATTR btdm_lpcntl_t g_lp_cntl; + +/* low power status struct */ + +static DRAM_ATTR btdm_lpstat_t g_lp_stat; + +/* measured average low power clock period in micro seconds */ + +static DRAM_ATTR uint32_t g_btdm_lpcycle_us = 0; + +/* number of fractional bit for g_btdm_lpcycle_us */ + +static DRAM_ATTR uint8_t g_btdm_lpcycle_us_frac = 0; + +#ifdef CONFIG_PM +/* semaphore used for blocking VHCI API to wait for controller to wake up */ + +static DRAM_ATTR void * g_wakeup_req_sem = NULL; + +/* wakeup timer */ + +static DRAM_ATTR esp_timer_handle_t g_btdm_slp_tmr; +#endif + +/* BT interrupt private data */ + +static bool g_ble_irq_bind; +static irqstate_t g_inter_flags; +static uint32_t g_phy_clk_en_cnt; +static int64_t g_phy_rf_en_ts; +static uint8_t g_phy_access_ref; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* BLE OS adapter data */ + +static struct osi_funcs_s g_osi_funcs = +{ + ._magic = OSI_MAGIC_VALUE, + ._version = OSI_VERSION, + ._interrupt_set = interrupt_set_wrapper, + ._interrupt_clear = interrupt_clear_wrapper, + ._interrupt_handler_set = interrupt_handler_set_wrapper, + ._interrupt_disable = interrupt_disable, + ._interrupt_restore = interrupt_restore, + ._task_yield = task_yield_from_isr, + ._task_yield_from_isr = task_yield_from_isr, + ._semphr_create = semphr_create_wrapper, + ._semphr_delete = semphr_delete_wrapper, + ._semphr_take_from_isr = semphr_take_from_isr_wrapper, + ._semphr_give_from_isr = semphr_give_from_isr_wrapper, + ._semphr_take = semphr_take_wrapper, + ._semphr_give = semphr_give_wrapper, + ._mutex_create = mutex_create_wrapper, + ._mutex_delete = mutex_delete_wrapper, + ._mutex_lock = mutex_lock_wrapper, + ._mutex_unlock = mutex_unlock_wrapper, + ._queue_create = queue_create_wrapper, + ._queue_delete = queue_delete_wrapper, + ._queue_send = queue_send_wrapper, + ._queue_send_from_isr = queue_send_from_isr_wrapper, + ._queue_recv = queue_recv_wrapper, + ._queue_recv_from_isr = queue_recv_from_isr_wrapper, + ._task_create = task_create_wrapper, + ._task_delete = task_delete_wrapper, + ._is_in_isr = is_in_isr_wrapper, + ._malloc = malloc_wrapper, + ._malloc_internal = malloc_internal_wrapper, + ._free = free, + ._read_efuse_mac = read_mac_wrapper, + ._srand = srand_wrapper, + ._rand = rand_wrapper, + ._btdm_lpcycles_2_hus = btdm_lpcycles_2_hus, + ._btdm_hus_2_lpcycles = btdm_hus_2_lpcycles, +#ifdef CONFIG_PM + ._btdm_sleep_check_duration = btdm_sleep_check_duration, + ._btdm_sleep_enter_phase1 = btdm_sleep_enter_phase1_wrapper, + ._btdm_sleep_enter_phase2 = btdm_sleep_enter_phase2_wrapper, + ._btdm_sleep_exit_phase3 = btdm_sleep_exit_phase3_wrapper, +#endif + ._coex_wifi_sleep_set = coex_wifi_sleep_set_hook, + ._coex_core_ble_conn_dyn_prio_get = coex_core_ble_conn_dyn_prio_get, + ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper, + ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper, + ._interrupt_on = interrupt_on_wrapper, + ._interrupt_off = interrupt_off_wrapper, +}; + +/**************************************************************************** + * Private Functions and Public Functions only used by libraries + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_errno_trans + * + * Description: + * Transform from nuttx error code to Wi-Fi adapter error code + * + * Input Parameters: + * ret - NuttX error code + * + * Returned Value: + * Wi-Fi adapter error code + * + ****************************************************************************/ + +static inline int32_t esp_errno_trans(int ret) +{ + if (!ret) + { + return true; + } + else + { + return false; + } +} + +/**************************************************************************** + * Name: esp_task_create_pinned_to_core + * + * Description: + * Create task and bind it to target CPU, the task will run when it + * is created + * + * Input Parameters: + * entry - Task entry + * name - Task name + * stack_depth - Task stack size + * param - Task private data + * prio - Task priority + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * core_id - CPU which the task runs in + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t esp_task_create_pinned_to_core(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id) +{ + int pid; + + pid = kthread_create(name, prio, stack_depth, entry, + (char * const *)param); + if (pid > 0) + { + if (task_handle) + { + *((int *)task_handle) = pid; + } + } + else + { + wlerr("Failed to create task\n"); + } + + return pid > 0 ? true : false; +} + +/**************************************************************************** + * Name: interrupt_set_wrapper + * + * Description: + * Bind IRQ and resource with given parameters. + * + * Input Parameters: + * cpu_no - The CPU which the interrupt number belongs. + * intr_source - The interrupt hardware source number. + * intr_num - The interrupt number CPU. + * intr_prio - The interrupt priority. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void interrupt_set_wrapper(int cpu_no, + int intr_source, + int intr_num, + int intr_prio) +{ + wlinfo("cpu_no=%d , intr_source=%d , intr_num=%d, intr_prio=%d\n", + cpu_no, intr_source, intr_num, intr_prio); + esp32c3_bind_irq(intr_num, intr_source, intr_prio, ESP32C3_INT_LEVEL); +} + +/**************************************************************************** + * Name: interrupt_clear_wrapper + * + * Description: + * Not supported + * + ****************************************************************************/ + +static void interrupt_clear_wrapper(int intr_source, int intr_num) +{ +} + +/**************************************************************************** + * Name: esp_int_adpt_cb + * + * Description: + * BT interrupt adapter callback function + * + * Input Parameters: + * arg - interrupt adapter private data + * + * Returned Value: + * NuttX error code + * + ****************************************************************************/ + +static int esp_int_adpt_cb(int irq, void *context, FAR void *arg) +{ + struct irq_adpt_s *adapter = (struct irq_adpt_s *)arg; + + adapter->func(adapter->arg); + + return OK; +} + +/**************************************************************************** + * Name: interrupt_handler_set_wrapper + * + * Description: + * Register interrupt function + * + * Input Parameters: + * n - Interrupt ID + * f - Interrupt function + * arg - Function private data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void interrupt_handler_set_wrapper(int n, void *fn, void *arg) +{ + int ret; + struct irq_adpt_s *adapter; + + if (g_ble_irq_bind) + { + return; + } + + adapter = kmm_malloc(sizeof(struct irq_adpt_s)); + DEBUGASSERT(adapter); + + adapter->func = fn; + adapter->arg = arg; + + ret = irq_attach(n + ESP32C3_IRQ_FIRSTPERIPH, esp_int_adpt_cb, adapter); + DEBUGASSERT(ret == OK); + + g_ble_irq_bind = true; +} + +/**************************************************************************** + * Name: esp32c3_ints_on + * + * Description: + * Enable Wi-Fi interrupt + * + * Input Parameters: + * intr_num - No mean + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void interrupt_on_wrapper(int intr_num) +{ + up_enable_irq(intr_num); +} + +/**************************************************************************** + * Name: esp32c3_ints_off + * + * Description: + * Disable Wi-Fi interrupt + * + * Input Parameters: + * intr_num - No mean + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void interrupt_off_wrapper(int intr_num) +{ + up_disable_irq(intr_num); +} + +/**************************************************************************** + * Name: interrupt_disable + * + * Description: + * Enter critical section by disabling interrupts and taking the spin lock + * if in SMP mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void IRAM_ATTR interrupt_disable(void) +{ + enter_critical_section(); +} + +/**************************************************************************** + * Name: interrupt_restore + * + * Description: + * Exit from critical section by enabling interrupts and releasing the spin + * lock if in SMP mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR interrupt_restore(void) +{ + leave_critical_section(g_inter_flags); +} + +/**************************************************************************** + * Name: task_yield_from_isr + * + * Description: + * Do nothing in NuttX + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR task_yield_from_isr(void) +{ +} + +/**************************************************************************** + * Name: semphr_create_wrapper + * + * Description: + * Create and initialize semaphore + * + * Input Parameters: + * max - Unused + * init - semaphore initialization value + * + * Returned Value: + * Semaphore data pointer + * + ****************************************************************************/ + +static void *semphr_create_wrapper(uint32_t max, uint32_t init) +{ + int ret; + sem_t *sem; + int tmp; + + tmp = sizeof(sem_t); + sem = kmm_malloc(tmp); + DEBUGASSERT(sem); + + ret = sem_init(sem, 0, init); + DEBUGASSERT(ret == OK); + + return sem; +} + +/**************************************************************************** + * Name: semphr_delete_wrapper + * + * Description: + * Delete semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void semphr_delete_wrapper(void *semphr) +{ + sem_t *sem = (sem_t *)semphr; + sem_destroy(sem); + kmm_free(sem); +} + +/**************************************************************************** + * Name: semphr_take_from_isr_wrapper + * + * Description: + * take a semaphore from an ISR + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw) +{ + return semphr_take_wrapper(semphr, 0); +} + +/**************************************************************************** + * Name: semphr_give_from_isr_wrapper + * + * Description: + * Post semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw) +{ + return semphr_give_wrapper(semphr); +} + +/**************************************************************************** + * Name: esp_update_time + * + * Description: + * Transform ticks to time and add this time to timespec value + * + * Input Parameters: + * timespec - Input timespec data pointer + * ticks - System ticks + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_update_time(struct timespec *timespec, uint32_t ticks) +{ + uint32_t tmp; + + tmp = TICK2SEC(ticks); + timespec->tv_sec += tmp; + + ticks -= SEC2TICK(tmp); + tmp = TICK2NSEC(ticks); + + timespec->tv_nsec += tmp; +} + +/**************************************************************************** + * Name: semphr_take_wrapper + * + * Description: + * Wait semaphore within a certain period of time + * + * Input Parameters: + * semphr - Semaphore data pointer + * block_time_ms - Wait time + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int semphr_take_wrapper(void *semphr, uint32_t block_time_ms) +{ + int ret; + struct timespec timeout; + sem_t *sem = (sem_t *)semphr; + + if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) + { + ret = sem_wait(sem); + if (ret) + { + wlerr("Failed to wait sem\n"); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + wlerr("Failed to get time\n"); + return false; + } + + if (block_time_ms) + { + esp_update_time(&timeout, MSEC2TICK(block_time_ms)); + } + + ret = sem_timedwait(sem, &timeout); + } + + return esp_errno_trans(ret); +} + +/**************************************************************************** + * Name: semphr_give_wrapper + * + * Description: + * Post semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int semphr_give_wrapper(void *semphr) +{ + int ret; + sem_t *sem = (sem_t *)semphr; + + ret = sem_post(sem); + if (ret) + { + wlerr("Failed to post sem error=%d\n", ret); + } + + return esp_errno_trans(ret); +} + +/**************************************************************************** + * Name: mutex_create_wrapper + * + * Description: + * Create mutex + * + * Input Parameters: + * None + * + * Returned Value: + * Mutex data pointer + * + ****************************************************************************/ + +static void *mutex_create_wrapper(void) +{ + int ret; + pthread_mutex_t *mutex; + int tmp; + + tmp = sizeof(pthread_mutex_t); + mutex = kmm_malloc(tmp); + DEBUGASSERT(mutex); + + ret = pthread_mutex_init(mutex, NULL); + if (ret) + { + wlerr("Failed to initialize mutex error=%d\n", ret); + kmm_free(mutex); + return NULL; + } + + return mutex; +} + +/**************************************************************************** + * Name: mutex_delete_wrapper + * + * Description: + * Delete mutex + * + * Input Parameters: + * None + * + * Returned Value: + * Mutex data pointer + * + ****************************************************************************/ + +static void mutex_delete_wrapper(void *mutex) +{ + pthread_mutex_destroy(mutex); + kmm_free(mutex); +} + +/**************************************************************************** + * Name: mutex_lock_wrapper + * + * Description: + * Lock mutex + * + * Input Parameters: + * mutex_data - mutex data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int mutex_lock_wrapper(void *mutex) +{ + int ret; + + ret = pthread_mutex_lock(mutex); + if (ret) + { + wlerr("Failed to lock mutex error=%d\n", ret); + } + + return esp_errno_trans(ret); +} + +/**************************************************************************** + * Name: mutex_unlock_wrapper + * + * Description: + * Unlock mutex + * + * Input Parameters: + * mutex_data - mutex data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int mutex_unlock_wrapper(void *mutex) +{ + int ret; + + ret = pthread_mutex_unlock(mutex); + if (ret) + { + wlerr("Failed to unlock mutex error=%d\n", ret); + } + + return esp_errno_trans(ret); +} + +/**************************************************************************** + * Name: esp_queue_send_generic + * + * Description: + * Generic send message to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * prio - Message priority + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t esp_queue_send_generic(void *queue, void *item, + uint32_t ticks, int prio) +{ + int ret; + struct timespec timeout; + struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; + + if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) + { + /** + * BLE interrupt function will call this adapter function to send + * message to message queue, so here we should call kernel API + * instead of application API + */ + + ret = file_mq_send(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio); + if (ret < 0) + { + wlerr("Failed to send message to mqueue error=%d\n", ret); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + wlerr("Failed to get time\n"); + return false; + } + + if (ticks) + { + esp_update_time(&timeout, ticks); + } + + ret = file_mq_timedsend(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio, &timeout); + if (ret < 0) + { + wlerr("Failed to timedsend message to mqueue error=%d\n", ret); + } + } + + return esp_errno_trans(ret); +} + +/**************************************************************************** + * Name: queue_send_from_isr_wrapper + * + * Description: + * Send message of low priority to queue in ISR within + * a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * hptw - Unused + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue, + void *item, + void *hptw) +{ + return esp_queue_send_generic(queue, item, 0, 0); +} + +/**************************************************************************** + * Name: queue_recv_from_isr_wrapper + * + * Description: + * Receive message from queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * hptw - Unused + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, + void *item, + void *hptw) +{ + return 0; +} + +/**************************************************************************** + * Name: task_create_wrapper + * + * Description: + * Create task and the task will run when it is created + * + * Input Parameters: + * entry - Task entry + * name - Task name + * stack_depth - Task stack size + * param - Task private data + * prio - Task priority + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int task_create_wrapper(void *task_func, const char *name, + uint32_t stack_depth, void *param, + uint32_t prio, void *task_handle, + uint32_t core_id) +{ + return esp_task_create_pinned_to_core(task_func, name, + stack_depth, param, + prio, task_handle, UINT32_MAX); +} + +/**************************************************************************** + * Name: task_delete_wrapper + * + * Description: + * Delete the target task + * + * Input Parameters: + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void task_delete_wrapper(void *task_handle) +{ + pid_t pid = (pid_t)((uintptr_t)task_handle); + kthread_delete(pid); +} + +/**************************************************************************** + * Name: is_in_isr_wrapper + * + * Description: + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static bool IRAM_ATTR is_in_isr_wrapper(void) +{ + return false; +} + +/**************************************************************************** + * Name: malloc_wrapper + * + * Description: + * Malloc buffer + * + * Input Parameters: + * szie - buffer size + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void *malloc_wrapper(size_t size) +{ + void * p = NULL; + + p = kmm_malloc(size); + DEBUGASSERT(p); + + return p; +} + +/**************************************************************************** + * Name: malloc_internal_wrapper + * + * Description: + * Malloc buffer in DRAM + * + * Input Parameters: + * szie - buffer size + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void *malloc_internal_wrapper(size_t size) +{ + void * p = NULL; + + p = kmm_malloc(size); + DEBUGASSERT(p); + + return p; +} + +/**************************************************************************** + * Name: read_mac_wrapper + * + * Description: + * Get Mac Address + * + * Input Parameters: + * mac - mac address + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6]) +{ + return 0; +} + +/**************************************************************************** + * Name: srand_wrapper + * + * Description: + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR srand_wrapper(unsigned int seed) +{ + /* empty function */ +} + +/**************************************************************************** + * Name: rand_wrapper + * + * Description: + * Get random value + * Input Parameters: + * None + * + * Returned Value: + * Random value + * + ****************************************************************************/ + +static int IRAM_ATTR rand_wrapper(void) +{ + return random(); +} + +/**************************************************************************** + * Name: btdm_lpcycles_2_hus + * + * Description: + * Converts a number of low power clock cycles into a duration in half us. + * + * Input Parameters: + * cycles + * error_corr + * + * Returned Value: + * us + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, + uint32_t *error_corr) +{ + uint64_t us = (uint64_t)g_btdm_lpcycle_us * cycles; + us = (us + (1 << (g_btdm_lpcycle_us_frac - 1))) >> g_btdm_lpcycle_us_frac; + return (uint32_t)us; +} + +/**************************************************************************** + * Name: btdm_hus_2_lpcycles + * + * Description: + * Converts a duration in half us into a number of low power clock cycles. + * + * Input Parameters: + * us + * + * Returned Value: + * cycles + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR btdm_hus_2_lpcycles(uint32_t us) +{ + uint64_t cycles; + cycles = ((uint64_t)(us) << g_btdm_lpcycle_us_frac) / g_btdm_lpcycle_us; + return (uint32_t)cycles; +} + +#ifdef CONFIG_PM +/**************************************************************************** + * Name: btdm_sleep_exit_phase0 + * + * Description: + * acquire PM lock and stop esp timer. + * + * Input Parameters: + * param - wakeup event + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR btdm_sleep_exit_phase0(void *param) +{ + DEBUGASSERT(g_lp_cntl.enable == true); + + if (g_lp_stat.pm_lock_released) + { + esp32c3_pm_lockacquire(); + g_lp_stat.pm_lock_released = false; + } + + int event = (int) param; + + if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI || + event == BTDM_ASYNC_WAKEUP_SRC_DISA) + { + btdm_wakeup_request(); + } + + if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started) + { + esp_timer_stop(g_btdm_slp_tmr); + g_lp_stat.wakeup_timer_started = false; + } + + if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI || + event == BTDM_ASYNC_WAKEUP_SRC_DISA) + { + semphr_give_wrapper(g_wakeup_req_sem); + } +} + +/**************************************************************************** + * Name: btdm_slp_tmr_callback + * + * Description: + * Esp ble sleep callback function. + * + * Input Parameters: + * arg - Unused + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) +{ + btdm_vnd_offload_post(BTDM_VND_OL_SIG_WAKEUP_TMR, + (void *)BTDM_ASYNC_WAKEUP_SRC_TMR); +} + +/**************************************************************************** + * Name: btdm_sleep_check_duration + * + * Description: + * Wake up in advance considering the delay in enabling PHY/RF. + * + * Input Parameters: + * half_slot_cnt - half slots to allow to fall into modem sleep + * + * Returned Value: + * None + * + ****************************************************************************/ + +static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt) +{ + if (*half_slot_cnt < BTDM_MIN_SLEEP_DURATION) + { + return false; + } + + *half_slot_cnt -= BTDM_MODEM_WAKE_UP_DELAY; + return true; +} + +/**************************************************************************** + * Name: btdm_sleep_enter_phase1_wrapper + * + * Description: + * ESP32C3 BLE lightsleep callback function. + * + * Input Parameters: + * lpcycles - light sleep cycles + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles) +{ + if (g_lp_cntl.wakeup_timer_required == false) + { + return; + } + + /* start a timer to wake up and acquire the pm_lock before sleep awakes */ + + uint32_t us_to_sleep = btdm_lpcycles_2_hus(lpcycles, NULL) >> 1; + + DEBUGASSERT(us_to_sleep > BTDM_MIN_TIMER_UNCERTAINTY_US); + uint32_t uncertainty = (us_to_sleep >> 11); + + if (uncertainty < BTDM_MIN_TIMER_UNCERTAINTY_US) + { + uncertainty = BTDM_MIN_TIMER_UNCERTAINTY_US; + } + + DEBUGASSERT(g_lp_stat.wakeup_timer_started == false); + + if (esp_timer_start_once(g_btdm_slp_tmr, + us_to_sleep - uncertainty) == ESP_OK) + { + g_lp_stat.wakeup_timer_started = true; + } + else + { + wlerr("timer start failed"); + DEBUGASSERT(0); + } +} + +/**************************************************************************** + * Name: btdm_sleep_enter_phase2_wrapper + * + * Description: + * ESP32C3 BLE lightsleep callback function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void btdm_sleep_enter_phase2_wrapper(void) +{ + if (btdm_controller_get_sleep_mode() == ESP_BT_SLEEP_MODE_1) + { + if (g_lp_stat.phy_enabled) + { + bt_phy_disable(); + g_lp_stat.phy_enabled = false; + } + else + { + DEBUGASSERT(0); + } + + if (g_lp_stat.pm_lock_released == false) + { + esp32c3_pm_lockrelease(); + g_lp_stat.pm_lock_released = true; + } + } +} + +/**************************************************************************** + * Name: btdm_sleep_exit_phase3_wrapper + * + * Description: + * ESP32C3 BLE lightsleep callback function.. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void btdm_sleep_exit_phase3_wrapper(void) +{ + if (g_lp_stat.pm_lock_released) + { + esp32c3_pm_lockacquire(); + g_lp_stat.pm_lock_released = false; + } + + if (btdm_sleep_clock_sync()) + { + wlerr("sleep eco state err\n"); + DEBUGASSERT(0); + } + + if (btdm_controller_get_sleep_mode() == ESP_BT_SLEEP_MODE_1) + { + if (g_lp_stat.phy_enabled == false) + { + bt_phy_enable(); + g_lp_stat.phy_enabled = true; + } + } + + if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started) + { + esp_timer_stop(g_btdm_slp_tmr); + g_lp_stat.wakeup_timer_started = false; + } +} +#endif + +/**************************************************************************** + * Name: coex_schm_status_bit_set_wrapper + * + * Description: + * + * Input Parameters: + * type + * status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status) +{ +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_schm_status_bit_set(type, status); +#endif +} + +/**************************************************************************** + * Name: coex_schm_status_bit_clear_wrapper + * + * Description: + * + * Input Parameters: + * szie + * status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status) +{ +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_schm_status_bit_clear(type, status); +#endif +} + +/**************************************************************************** + * Name: btdm_controller_mem_init + * + * Description: + * Initialize BT controller to allocate task and other resource. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void btdm_controller_mem_init(void) +{ + btdm_controller_rom_data_init(); +} + +/**************************************************************************** + * Name: phy_printf + * + * Description: + * Output format string and its arguments + * + * Input Parameters: + * format - format string + * + * Returned Value: + * 0 + * + ****************************************************************************/ + +#ifndef CONFIG_ESP32C3_WIFI +int phy_printf(const char *format, ...) +{ +#ifdef CONFIG_DEBUG_WIRELESS_INFO + va_list arg; + + va_start(arg, format); + vsyslog(LOG_INFO, format, arg); + va_end(arg); +#endif + + return 0; +} +#endif + +/**************************************************************************** + * Name: bt_phy_enable_clock + * + * Description: + * Enable BT clock. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void bt_phy_enable_clock(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (g_phy_clk_en_cnt == 0) + { + modifyreg32(SYSTEM_WIFI_CLK_EN_REG, 0, + SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); + } + + g_phy_clk_en_cnt++; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: bt_phy_disable_clock + * + * Description: + * Disable BT clock. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void bt_phy_disable_clock(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (g_phy_clk_en_cnt) + { + g_phy_clk_en_cnt--; + if (!g_phy_clk_en_cnt) + { + modifyreg32(SYSTEM_WIFI_CLK_EN_REG, + SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M, + 0); + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: bt_phy_disable + * + * Description: + * Disable BT phy. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void bt_phy_disable(void) +{ + irqstate_t flags; + flags = enter_critical_section(); + + g_phy_access_ref--; + + if (g_phy_access_ref == 0) + { + /* Disable PHY and RF. */ + + phy_close_rf(); + + /* Disable Wi-Fi/BT common peripheral clock. + * Do not disable clock for hardware RNG. + */ + + bt_phy_disable_clock(); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: bt_phy_enable + * + * Description: + * Enable BT phy. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void bt_phy_enable(void) +{ + irqstate_t flags; + esp_phy_calibration_data_t *cal_data; + + cal_data = kmm_zalloc(sizeof(esp_phy_calibration_data_t)); + if (!cal_data) + { + wlerr("Failed to kmm_zalloc"); + DEBUGASSERT(0); + } + + flags = enter_critical_section(); + + if (g_phy_access_ref == 0) + { + /* Update time stamp */ + + g_phy_rf_en_ts = (int64_t)rt_timer_time_us(); + + bt_phy_enable_clock(); + phy_set_wifi_mode_only(0); + register_chipv7_phy(&phy_init_data, cal_data, PHY_RF_CAL_NONE); + extern void coex_pti_v2(void); + coex_pti_v2(); + } + + g_phy_access_ref++; + leave_critical_section(flags); + kmm_free(cal_data); +} + +static void coex_wifi_sleep_set_hook(bool sleep) +{ +} + +/**************************************************************************** + * Name: queue_create_wrapper + * + * Description: + * Create message queue + * + * Input Parameters: + * queue_len - queue message number + * item_size - message size + * + * Returned Value: + * Message queue data pointer + * + ****************************************************************************/ + +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) +{ + struct mq_attr attr; + struct mq_adpt_s *mq_adpt; + int ret; + + mq_adpt = kmm_malloc(sizeof(struct mq_adpt_s)); + DEBUGASSERT(mq_adpt); + + snprintf(mq_adpt->name, sizeof(mq_adpt->name), "/tmp/%p", mq_adpt); + + attr.mq_maxmsg = queue_len; + attr.mq_msgsize = item_size; + attr.mq_curmsgs = 0; + attr.mq_flags = 0; + + ret = file_mq_open(&mq_adpt->mq, mq_adpt->name, + O_RDWR | O_CREAT, 0644, &attr); + + if (ret < 0) + { + wlerr("Failed to create mqueue\n"); + kmm_free(mq_adpt); + return NULL; + } + + mq_adpt->msgsize = item_size; + return (void *)mq_adpt; +} + +/**************************************************************************** + * Name: queue_send_wrapper + * + * Description: + * Generic send message to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointerint + * block_time_ms - Wait time + * + * Returned Value:uint32_t + * True if success or false if fail + * + ****************************************************************************/ + +static int queue_send_wrapper(void *queue, void *item, + uint32_t block_time_ms) +{ + return esp_queue_send_generic(queue, item, block_time_ms, 0); +} + +/**************************************************************************** + * Name: queue_recv_wrapper + * + * Description: + * Receive message from queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * block_time_ms - Wait time + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int queue_recv_wrapper(void *queue, void *item, + uint32_t block_time_ms) +{ + ssize_t ret; + struct timespec timeout; + unsigned int prio; + struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; + + if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) + { + ret = file_mq_receive(&mq_adpt->mq, (char *)item, + mq_adpt->msgsize, &prio); + + if (ret < 0) + { + wlerr("Failed to receive from mqueue error=%d\n", ret); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + + if (ret < 0) + { + wlerr("Failed to get time\n"); + return false; + } + + if (block_time_ms) + { + esp_update_time(&timeout, MSEC2TICK(block_time_ms)); + } + + ret = file_mq_timedreceive(&mq_adpt->mq, (char *)item, + mq_adpt->msgsize, &prio, &timeout); + + if (ret < 0) + { + wlerr("Failed to timedreceive from mqueue error=%d\n", ret); + } + } + + return ret > 0 ? true : false; +} + +/**************************************************************************** + * Name: queue_delete_wrapper + * + * Description: + * Delete message queue + * + * Input Parameters: + * queue - Message queue data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void queue_delete_wrapper(void *queue) +{ + struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; + + file_mq_close(&mq_adpt->mq); + file_mq_unlink(mq_adpt->name); + kmm_free(mq_adpt); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_bt_controller_init + * + * Description: + * Init BT controller. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_bt_controller_init(void) +{ + esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); + esp_bt_controller_config_t *cfg = &bt_cfg; +#ifdef CONFIG_PM + bool select_src_ret; + bool set_div_ret; +#endif + + if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) + { + wlerr("Invalid controller status"); + return -1; + } + + cfg->controller_task_stack_size = CONFIG_ESP32C3_BLE_TASK_STACK_SIZE; + cfg->controller_task_prio = CONFIG_ESP32C3_BLE_TASK_PRIORITY; + + cfg->controller_task_run_cpu = 0; + cfg->ble_max_act = 10; + cfg->sleep_mode = 0; + cfg->coex_phy_coded_tx_rx_time_limit = 0; + cfg->bluetooth_mode = 1; + cfg->sleep_clock = 0; + cfg->ble_st_acl_tx_buf_nb = 0; + cfg->ble_hw_cca_check = 0; + cfg->ble_adv_dup_filt_max = 30; + cfg->ce_len_type = 0; + cfg->hci_tl_type = 1; + cfg->hci_tl_funcs = NULL; + cfg->txant_dft = 0; + cfg->rxant_dft = 0; + cfg->txpwr_dft = 7; + cfg->cfg_mask = 1; + cfg->scan_duplicate_mode = 0; + cfg->scan_duplicate_type = 0; + cfg->normal_adv_size = 20; + cfg->mesh_adv_size = 0; + + btdm_controller_mem_init(); + + if (btdm_osi_funcs_register(&g_osi_funcs) != 0) + { + return -EINVAL; + } + + wlinfo("BT controller compile version [%s]\n", + btdm_controller_get_compile_version()); + +#ifdef CONFIG_PM + /* init low-power control resources */ + + memset(&g_lp_cntl, 0x0, sizeof(btdm_lpcntl_t)); + memset(&g_lp_stat, 0x0, sizeof(btdm_lpstat_t)); + g_wakeup_req_sem = NULL; + g_btdm_slp_tmr = NULL; + + /* configure and initialize resources */ + + g_lp_cntl.enable = (cfg->sleep_mode == ESP_BT_SLEEP_MODE_1) ? true : false; + + if (g_lp_cntl.enable) + { + g_lp_cntl.wakeup_timer_required = true; + g_wakeup_req_sem = semphr_create_wrapper(1, 0); + + if (g_wakeup_req_sem == NULL) + { + goto error; + } + + btdm_vnd_offload_task_register(BTDM_VND_OL_SIG_WAKEUP_TMR, + btdm_sleep_exit_phase0); + } + + if (g_lp_cntl.wakeup_timer_required) + { + esp_timer_create_args_t create_args = + { + .callback = btdm_slp_tmr_callback, + .arg = NULL, + .name = "btSlp", + }; + + if ((err = esp_timer_create(&create_args, &g_btdm_slp_tmr)) != ESP_OK) + { + goto error; + } + } + + g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT; + g_btdm_lpcycle_us = 2 << (g_btdm_lpcycle_us_frac); + + if (esp32c3_rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_32K_XTAL) + { + g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL32K; + } + else + { + wlwarn("32.768kHz XTAL not detected"); + g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL; + } + + if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_XTAL) + { + select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL); + set_div_ret = btdm_lpclk_set_div(esp32c3_rtc_clk_xtal_freq_get() * 2); + DEBUGASSERT(select_src_ret && set_div_ret); + g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT; + g_btdm_lpcycle_us = 2 << (g_btdm_lpcycle_us_frac); + } + else if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_XTAL32K) + { + select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL32K); + set_div_ret = btdm_lpclk_set_div(0); + DEBUGASSERT(select_src_ret && set_div_ret); + g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT; + g_btdm_lpcycle_us = (RTC_CLK_CAL_FRACT > 15) ? + (1000000 << (RTC_CLK_CAL_FRACT - 15)) : + (1000000 >> (15 - RTC_CLK_CAL_FRACT)); + DEBUGASSERT(g_btdm_lpcycle_us != 0); + } + else if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_RTC_SLOW) + { + select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_RTC_SLOW); + set_div_ret = btdm_lpclk_set_div(0); + DEBUGASSERT(select_src_ret && set_div_ret); + g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT; + g_btdm_lpcycle_us = esp_clk_slowclk_cal_get_wrapper(); + } + else + { + goto error; + } + + g_lp_stat.pm_lock_released = true; +#endif + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_init(); +#endif + + modifyreg32(SYSTEM_WIFI_CLK_EN_REG, 0, UINT32_MAX); + + bt_phy_enable(); + g_lp_stat.phy_enabled = true; + + if (btdm_controller_init(cfg) != 0) + { + bt_phy_disable(); + g_lp_stat.phy_enabled = false; + return -EIO; + } + + btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; + + return 0; + +#ifdef CONFIG_PM +error: + if (g_lp_stat.phy_enabled) + { + bt_phy_disable(); + g_lp_stat.phy_enabled = false; + } + + g_lp_stat.pm_lock_released = false; + + if (g_lp_cntl.wakeup_timer_required && g_btdm_slp_tmr != NULL) + { + esp_timer_delete(g_btdm_slp_tmr); + g_btdm_slp_tmr = NULL; + } + + if (g_lp_cntl.enable) + { + btdm_vnd_offload_task_deregister(BTDM_VND_OL_SIG_WAKEUP_TMR); + + if (g_wakeup_req_sem != NULL) + { + semphr_delete_wrapper(g_wakeup_req_sem); + g_wakeup_req_sem = NULL; + } + } + + return ENOMEM; +#endif +} + +/**************************************************************************** + * Name: esp32c3_bt_controller_deinit + * + * Description: + * Deinit BT controller. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_bt_controller_deinit(void) +{ + if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) + { + return -1; + } + + btdm_controller_deinit(); + + if (g_lp_stat.phy_enabled) + { + bt_phy_disable(); + g_lp_stat.phy_enabled = false; + } + else + { + DEBUGASSERT(0); + } + +#ifdef CONFIG_PM + /* deinit low power control resources */ + + g_lp_stat.pm_lock_released = false; + + if (g_lp_cntl.wakeup_timer_required) + { + if (g_lp_stat.wakeup_timer_started) + { + esp_timer_stop(g_btdm_slp_tmr); + } + + g_lp_stat.wakeup_timer_started = false; + esp_timer_delete(g_btdm_slp_tmr); + g_btdm_slp_tmr = NULL; + } + + if (g_lp_cntl.enable) + { + btdm_vnd_offload_task_deregister(BTDM_VND_OL_SIG_WAKEUP_TMR); + semphr_delete_wrapper(g_wakeup_req_sem); + g_wakeup_req_sem = NULL; + } +#endif + + btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; + g_btdm_lpcycle_us = 0; + return 0; +} + +/**************************************************************************** + * Name: esp32c3_bt_controller_disable + * + * Description: + * disable BT controller. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_bt_controller_disable(void) +{ + if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) + { + return -1; + } + + while (!btdm_power_state_active()) + { + usleep(1000); /* wait */ + } + + btdm_controller_disable(); + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_disable(); +#endif + + btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; + +#ifdef CONFIG_PM + /* disable low power mode */ + + if (g_lp_stat.pm_lock_released == false) + { + esp32c3_pm_lockrelease(); + g_lp_stat.pm_lock_released = true; + } + else + { + DEBUGASSERT(0); + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: esp32c3_bt_controller_enable + * + * Description: + * Enable BT controller. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_bt_controller_enable(esp_bt_mode_t mode) +{ + int ret = 0; + + if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) + { + return -1; + } + + if (mode != btdm_controller_get_mode()) + { + wlerr("invalid mode %d, controller support mode is %d", + mode, btdm_controller_get_mode()); + return -1; + } + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_enable(); +#endif + +#ifdef CONFIG_PM + /* enable low power mode */ + + esp32c3_pm_lockacquire(); + g_lp_stat.pm_lock_released = false; + + if (g_lp_cntl.enable) + { + btdm_controller_enable_sleep(true); + } +#endif + + if (g_lp_cntl.enable) + { + btdm_controller_enable_sleep(true); + } + + if (btdm_controller_enable(mode) != 0) + { + ret = -1; + goto error; + } + + btdm_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED; + + return ret; + +error: + + /* disable low power mode */ + + btdm_controller_enable_sleep(false); + +#ifdef CONFIG_PM + if (g_lp_stat.pm_lock_released == false) + { + esp32c3_pm_lockrelease(); + g_lp_stat.pm_lock_released = true; + } +#endif + + return ret; +} + +esp_bt_controller_status_t esp32c3_bt_controller_get_status(void) +{ + return btdm_controller_status; +} + +/**************************************************************************** + * Name: esp32c3_vhci_host_check_send_available + * + * Description: + * Check if the host can send packet to controller or not. + * + * Input Parameters: + * None + * + * Returned Value: + * bool - true or false + * + ****************************************************************************/ + +bool esp32c3_vhci_host_check_send_available(void) +{ + if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) + { + return false; + } + + return API_vhci_host_check_send_available(); +} + +/**************************************************************************** + * Name: esp32c3_vhci_host_send_packet + * + * Description: + * host send packet to controller. + * Input Parameters: + * data - the packet point + * len - the packet length + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_vhci_host_send_packet(uint8_t *data, uint16_t len) +{ + if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) + { + return; + } + + API_vhci_host_send_packet(data, len); +} + +/**************************************************************************** + * Name: esp32c3_vhci_register_callback + * + * Description: + * register the vhci reference callback. + * Input Parameters: + * callback - struct defined by vhci_host_callback structure. + * + * Returned Value: + * status - success or fail + * + ****************************************************************************/ + +int esp32c3_vhci_register_callback(const esp_vhci_host_callback_t *callback) +{ + int ret = -1; + if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) + { + return ret; + } + + ret = API_vhci_host_register_callback( + (const vhci_host_callback_t *)callback) == 0 ? 0 : -1; + return ret; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.h b/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.h new file mode 100644 index 00000000000..70260356e95 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.h @@ -0,0 +1,161 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_ble_adapter.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_ADAPTER_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_ADAPTER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "esp_bt.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_bt_controller_init + * + * Description: + * Init BT controller. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_bt_controller_init(void); + +/**************************************************************************** + * Name: esp32c3_bt_controller_deinit + * + * Description: + * Deinit BT controller. + * Input Parameters: + * cfg - Initial configuration of BT controller. + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_bt_controller_deinit(void); + +/**************************************************************************** + * Name: esp32c3_bt_controller_enable + * + * Description: + * disable BT controller. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_bt_controller_enable(esp_bt_mode_t mode); + +/**************************************************************************** + * Name: esp32c3_bt_controller_disable + * + * Description: + * disable BT controller. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_bt_controller_disable(void); + +/**************************************************************************** + * Name: esp32c3_bt_controller_enable + * + * Description: + * Enable BT controller. + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +esp_bt_controller_status_t esp32c3_bt_controller_get_status(void); + +/**************************************************************************** + * Name: esp32c3_vhci_host_check_send_available + * + * Description: + * used for check actively if the host can send packet to controller or not. + * Input Parameters: + * None + * + * Returned Value: + * bool - true or false + * + ****************************************************************************/ + +bool esp32c3_vhci_host_check_send_available(void); + +/**************************************************************************** + * Name: esp32c3_vhci_host_send_packet + * + * Description: + * host send packet to controller. + * Input Parameters: + * data - the packet point + * len - the packet length + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_vhci_host_send_packet(uint8_t *data, uint16_t len); + +/**************************************************************************** + * Name: esp32c3_vhci_register_callback + * + * Description: + * register the vhci reference callback. + * Input Parameters: + * callback - struct defined by vhci_host_callback structure. + * + * Returned Value: + * status - success or fail + * + ****************************************************************************/ + +int esp32c3_vhci_register_callback( + const esp_vhci_host_callback_t *callback); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_ADAPTER_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_dma.c b/arch/risc-v/src/esp32c3/esp32c3_dma.c new file mode 100644 index 00000000000..36dad7da167 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_dma.c @@ -0,0 +1,533 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_dma.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "riscv_arch.h" + +#include "esp32c3_dma.h" + +#include "hardware/esp32c3_dma.h" +#include "hardware/esp32c3_soc.h" +#include "hardware/esp32c3_system.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +#define REG_OFF (DMA_OUT_CONF0_CH1_REG - DMA_OUT_CONF0_CH0_REG) + +#define SET_REG(_r, _ch, _v) putreg32((_v), (_r) + (_ch) * REG_OFF) +#define GET_REG(_r, _ch) getreg32((_r) + (_ch) * REG_OFF) + +#define SET_BITS(_r, _ch, _b) modifyreg32((_r) + (_ch) * REG_OFF, 0, (_b)) +#define CLR_BITS(_r, _ch, _b) modifyreg32((_r) + (_ch) * REG_OFF, (_b), 0) + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef ALIGN_UP +# define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_dma_chan_used[ESP32C3_DMA_CHAN_MAX]; +static sem_t g_dma_exc_sem = SEM_INITIALIZER(1); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_dma_request + * + * Description: + * Request DMA channel and config it with given parameters. + * + * Input Parameters: + * periph - Peripheral for which the DMA channel request was made + * tx_prio - Interrupt priority + * rx_prio - Interrupt flags + * burst_en - Enable burst transmission + * + * Returned Value: + * DMA channel number (>=0) if success or -1 if fail. + * + ****************************************************************************/ + +int32_t esp32c3_dma_request(enum esp32c3_dma_periph_e periph, + uint32_t tx_prio, + uint32_t rx_prio, + bool burst_en) +{ + int chan; + + DEBUGASSERT((periph < ESP32C3_DMA_PERIPH_NUM) && + (periph != ESP32C3_DMA_PERIPH_RD0) && + (periph != ESP32C3_DMA_PERIPH_RD1)); + + DEBUGASSERT(tx_prio <= ESP32C3_DMA_TX_PRIO_MAX); + DEBUGASSERT(rx_prio <= ESP32C3_DMA_RX_PRIO_MAX); + + dmainfo("periph=%" PRIu32 " tx_prio=%" PRIu32 " rx_prio=%" PRIu32 "\n", + (uint32_t)periph, tx_prio, rx_prio); + + nxsem_wait_uninterruptible(&g_dma_exc_sem); + + for (chan = 0; chan < ESP32C3_DMA_CHAN_MAX; chan++) + { + if (!g_dma_chan_used[chan]) + { + g_dma_chan_used[chan] = true; + break; + } + } + + if (chan == ESP32C3_DMA_CHAN_MAX) + { + dmaerr("No available GDMA channel for allocation\n"); + + nxsem_post(&g_dma_exc_sem); + + return ERROR; + } + + dmainfo("Allocated channel=%d\n", chan); + + if (periph == ESP32C3_DMA_PERIPH_MEM) + { + /* Enable DMA channel M2M mode */ + + SET_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_MEM_TRANS_EN_CH0_M); + + /* Just setting a valid value to the register */ + + SET_REG(DMA_OUT_PERI_SEL_CH0_REG, chan, 0); + SET_REG(DMA_IN_PERI_SEL_CH0_REG, chan, 0); + } + else + { + /* Disable DMA channel M2M mode */ + + CLR_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_MEM_TRANS_EN_CH0_M); + + /* Connect DMA TX/RX channels to a given peripheral */ + + SET_REG(DMA_OUT_PERI_SEL_CH0_REG, chan, periph); + SET_REG(DMA_IN_PERI_SEL_CH0_REG, chan, periph); + } + + if (burst_en) + { + /* Enable DMA TX/RX channels burst sending data */ + + SET_BITS(DMA_OUT_CONF0_CH0_REG, chan, DMA_OUT_DATA_BURST_EN_CH0_M); + SET_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_IN_DATA_BURST_EN_CH0_M); + + /* Enable DMA TX/RX channels burst reading descriptor link */ + + SET_BITS(DMA_OUT_CONF0_CH0_REG, chan, DMA_OUTDSCR_BURST_EN_CH0_M); + SET_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_INDSCR_BURST_EN_CH0_M); + } + + /* Set priority for DMA TX/RX channels */ + + SET_REG(DMA_OUT_PRI_CH0_REG, chan, tx_prio); + SET_REG(DMA_IN_PRI_CH0_REG, chan, rx_prio); + + nxsem_post(&g_dma_exc_sem); + + return chan; +} + +/**************************************************************************** + * Name: esp32c3_dma_setup + * + * Description: + * Set up DMA descriptor with given parameters. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * dmadesc - DMA descriptor pointer + * num - DMA descriptor number + * pbuf - Buffer pointer + * len - Buffer length by byte + * + * Returned Value: + * Bind pbuf data bytes. + * + ****************************************************************************/ + +uint32_t esp32c3_dma_setup(int chan, bool tx, + struct esp32c3_dmadesc_s *dmadesc, uint32_t num, + uint8_t *pbuf, uint32_t len) +{ + int i; + uint32_t regval; + uint32_t bytes = len; + uint8_t *pdata = pbuf; + uint32_t data_len; + uint32_t buf_len; + + DEBUGASSERT(chan >= 0); + DEBUGASSERT(dmadesc != NULL); + DEBUGASSERT(num > 0); + DEBUGASSERT(pbuf != NULL); + DEBUGASSERT(len > 0); + + for (i = 0; i < num; i++) + { + data_len = MIN(bytes, ESP32C3_DMA_BUFLEN_MAX); + + /* Buffer length must be rounded to next 32-bit boundary. */ + + buf_len = ALIGN_UP(data_len, sizeof(uintptr_t)); + + dmadesc[i].ctrl = (data_len << ESP32C3_DMA_CTRL_DATALEN_S) | + (buf_len << ESP32C3_DMA_CTRL_BUFLEN_S) | + ESP32C3_DMA_CTRL_OWN; + dmadesc[i].pbuf = pdata; + dmadesc[i].next = &dmadesc[i + 1]; + + bytes -= data_len; + if (bytes == 0) + { + break; + } + + pdata += data_len; + } + + dmadesc[i].ctrl |= ESP32C3_DMA_CTRL_EOF; + dmadesc[i].next = NULL; + + if (tx) + { + /* Reset DMA TX channel FSM and FIFO pointer */ + + SET_BITS(DMA_OUT_CONF0_CH0_REG, chan, DMA_OUT_RST_CH0_M); + CLR_BITS(DMA_OUT_CONF0_CH0_REG, chan, DMA_OUT_RST_CH0_M); + + /* Set the descriptor link base address for TX channel */ + + regval = (uint32_t)dmadesc & DMA_OUTLINK_ADDR_CH0; + SET_BITS(DMA_OUT_LINK_CH0_REG, chan, regval); + } + else + { + /* Reset DMA RX channel FSM and FIFO pointer */ + + SET_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_IN_RST_CH0_M); + CLR_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_IN_RST_CH0_M); + + /* Set the descriptor link base address for RX channel */ + + regval = (uint32_t)dmadesc & DMA_INLINK_ADDR_CH0; + SET_BITS(DMA_IN_LINK_CH0_REG, chan, regval); + } + + return len - bytes; +} + +/**************************************************************************** + * Name: esp32c3_dma_enable + * + * Description: + * Enable DMA channel transmission. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_enable(int chan, bool tx) +{ + if (tx) + { + SET_BITS(DMA_OUT_LINK_CH0_REG, chan, DMA_OUTLINK_START_CH0_M); + } + else + { + SET_BITS(DMA_IN_LINK_CH0_REG, chan, DMA_INLINK_START_CH0_M); + } +} + +/**************************************************************************** + * Name: esp32c3_dma_disable + * + * Description: + * Disable DMA channel transmission. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_disable(int chan, bool tx) +{ + if (tx) + { + SET_BITS(DMA_OUT_LINK_CH0_REG, chan, DMA_OUTLINK_STOP_CH0_M); + } + else + { + SET_BITS(DMA_IN_LINK_CH0_REG, chan, DMA_INLINK_STOP_CH0_M); + } +} + +/**************************************************************************** + * Name: esp32c3_dma_wait_idle + * + * Description: + * Wait until transmission ends. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_wait_idle(int chan, bool tx) +{ + uint32_t regval; + uint32_t regaddr; + uint32_t waitbits; + + if (tx) + { + regaddr = DMA_OUT_LINK_CH0_REG + chan * REG_OFF; + waitbits = DMA_OUTLINK_PARK_CH0; + } + else + { + regaddr = DMA_IN_LINK_CH0_REG + chan * REG_OFF; + waitbits = DMA_INLINK_PARK_CH0; + } + + do + { + regval = getreg32(regaddr); + } + while ((waitbits & regval) == 0); +} + +/**************************************************************************** + * Name: esp32c3_dma_init + * + * Description: + * Initialize DMA driver. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_init(void) +{ + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, 0, SYSTEM_DMA_CLK_EN_M); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST_M, 0); + + modifyreg32(DMA_MISC_CONF_REG, 0, DMA_CLK_EN_M); +} + +/**************************************************************************** + * Name: esp32c3_dma_main + * + * Description: + * ESP32-C3 DMA testing example. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_DMA_M2M_TEST +void esp32c3_dma_main(int argc, char *argv[]) +{ + int chan; + struct esp32c3_dmadesc_s *rx_dmadesc; + struct esp32c3_dmadesc_s *tx_dmadesc; + uint8_t *rxbuf; + uint8_t *txbuf; + bool success = true; + + const size_t bufsize = CONFIG_ESP32C3_DMA_M2M_TEST_BUFSIZE; +#if (CONFIG_ESP32C3_DMA_M2M_TEST_BUFSIZE % ESP32C3_DMA_BUFLEN_MAX) > 0 + const size_t dmadesc_num = bufsize / ESP32C3_DMA_BUFLEN_MAX + 1; +#else + const size_t dmadesc_num = bufsize / ESP32C3_DMA_BUFLEN_MAX; +#endif + + syslog(LOG_INFO, "----- BEGIN TEST -----\n"); + + rxbuf = kmm_malloc(bufsize); + if (rxbuf == NULL) + { + syslog(LOG_ERR, "Failed to malloc RX buffer\n"); + + success = false; + goto test_end; + } + + txbuf = kmm_malloc(bufsize); + if (txbuf == NULL) + { + syslog(LOG_ERR, "Failed to malloc TX buffer\n"); + kmm_free(rxbuf); + + success = false; + goto test_end; + } + + rx_dmadesc = kmm_malloc(sizeof(struct esp32c3_dmadesc_s) * dmadesc_num); + if (rx_dmadesc == NULL) + { + syslog(LOG_ERR, "Failed to malloc RX DMA descriptor\n"); + kmm_free(txbuf); + kmm_free(rxbuf); + + success = false; + goto test_end; + } + + tx_dmadesc = kmm_malloc(sizeof(struct esp32c3_dmadesc_s) * dmadesc_num); + if (txbuf == NULL) + { + syslog(LOG_ERR, "Failed to malloc TX DMA descriptor\n"); + kmm_free(rx_dmadesc); + kmm_free(txbuf); + kmm_free(rxbuf); + + success = false; + goto test_end; + } + + esp32c3_dma_init(); + + chan = esp32c3_dma_request(ESP32C3_DMA_PERIPH_MEM, 1, 1, false); + if (chan < 0) + { + syslog(LOG_ERR, "Request DMA channel error\n"); + + success = false; + goto test_end_cleanup; + } + + for (int i = 1; i <= CONFIG_ESP32C3_DMA_M2M_TEST_LOOPS; ++i) + { + const uint8_t watermark = i & UINT8_MAX; + size_t j = 0; + + /* Prepare buffers for DMA transfer */ + + memset(rxbuf, 0, bufsize); + memset(txbuf, watermark, bufsize); + + /* Setup DMA descriptors. + * Intentionally ignore the last byte for TX. + */ + + esp32c3_dma_setup(chan, false, rx_dmadesc, dmadesc_num, + rxbuf, bufsize); + esp32c3_dma_setup(chan, true, tx_dmadesc, dmadesc_num, + txbuf, bufsize - 1); + + /* Start DMA transfer */ + + esp32c3_dma_enable(chan, false); + esp32c3_dma_enable(chan, true); + + /* Wait for DMA transfer to complete */ + + esp32c3_dma_wait_idle(chan, true); + esp32c3_dma_wait_idle(chan, false); + + /* Verify if last byte on RX buffer is unchanged */ + + if (rxbuf[bufsize - 1] != 0) + { + success = false; + goto test_end_cleanup; + } + + /* Verify if RX buffer contains expected values */ + + for (j = 0; j < bufsize - 1; ++j) + { + if (rxbuf[j] != watermark) + { + syslog(LOG_ERR, + "DMA-M2M-TEST loop %d fail buf[%zu]=%" PRIu8 "\n", + i, j, rxbuf[j]); + + success = false; + goto test_end_cleanup; + } + } + + syslog(LOG_INFO, "DMA-M2M-TEST loop %d OK\n", i); + } + +test_end_cleanup: + kmm_free(tx_dmadesc); + kmm_free(rx_dmadesc); + kmm_free(txbuf); + kmm_free(rxbuf); + +test_end: + syslog(LOG_INFO, "----- END TEST -----\n"); + + syslog(LOG_INFO, "\n"); + + syslog(LOG_INFO, "----- RESULT: %s -----\n", + success ? "SUCCESS" : "FAILED"); +} +#endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_dma.h b/arch/risc-v/src/esp32c3/esp32c3_dma.h new file mode 100644 index 00000000000..17272a9b379 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_dma.h @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_dma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H + +#include +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* DMA max data length */ + +#define ESP32C3_DMA_DATALEN_MAX (0x1000 - 4) + +/* DMA max buffer length */ + +#define ESP32C3_DMA_BUFLEN_MAX ESP32C3_DMA_DATALEN_MAX + +/* DMA channel number */ + +#define ESP32C3_DMA_CHAN_MAX (3) + +/* DMA RX MAX priority */ + +#define ESP32C3_DMA_RX_PRIO_MAX (15) + +/* DMA TX MAX priority */ + +#define ESP32C3_DMA_TX_PRIO_MAX (15) + +/* DMA descriptor */ + +#define ESP32C3_DMA_CTRL_OWN (1 << 31) /* Owned by DMA */ +#define ESP32C3_DMA_CTRL_EOF (1 << 30) /* End of frame */ +#define ESP32C3_DMA_CTRL_ERREOF (1 << 28) /* Received data error */ +#define ESP32C3_DMA_CTRL_DATALEN_S (12) /* Data length shift */ +#define ESP32C3_DMA_CTRL_DATALEN_V (0xfff) /* Data length value */ +#define ESP32C3_DMA_CTRL_BUFLEN_S (0) /* Buffer length shift */ +#define ESP32C3_DMA_CTRL_BUFLEN_V (0xfff) /* Buffer length value */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum esp32c3_dma_periph_e +{ + ESP32C3_DMA_PERIPH_MEM = -1, + ESP32C3_DMA_PERIPH_SPI = 0, + ESP32C3_DMA_PERIPH_UCHI0 = 2, + ESP32C3_DMA_PERIPH_I2S = 3, + ESP32C3_DMA_PERIPH_RD0 = 4, + ESP32C3_DMA_PERIPH_RD1 = 5, + ESP32C3_DMA_PERIPH_AES = 6, + ESP32C3_DMA_PERIPH_SHA = 7, + ESP32C3_DMA_PERIPH_ADC = 8, + ESP32C3_DMA_PERIPH_NUM, +}; + +/* DMA descriptor type */ + +struct esp32c3_dmadesc_s +{ + uint32_t ctrl; /* DMA control block */ + const uint8_t *pbuf; /* DMA TX/RX buffer address */ + struct esp32c3_dmadesc_s *next; /* Next DMA descriptor address */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_dma_request + * + * Description: + * Request DMA channel and config it with given parameters. + * + * Input Parameters: + * periph - Peripheral for which the DMA channel request was made + * tx_prio - Interrupt priority + * rx_prio - Interrupt flags + * + * Returned Value: + * DMA channel number (>=0) if success or -1 if fail. + * + ****************************************************************************/ + +int32_t esp32c3_dma_request(enum esp32c3_dma_periph_e periph, + uint32_t tx_prio, + uint32_t rx_prio, + bool burst_en); + +/**************************************************************************** + * Name: esp32c3_dma_setup + * + * Description: + * Set up DMA descriptor with given parameters. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * dmadesc - DMA descriptor pointer + * num - DMA descriptor number + * pbuf - Buffer pointer + * len - Buffer length by byte + * + * Returned Value: + * Bind pbuf data bytes. + * + ****************************************************************************/ + +uint32_t esp32c3_dma_setup(int chan, bool tx, + struct esp32c3_dmadesc_s *dmadesc, uint32_t num, + uint8_t *pbuf, uint32_t len); + +/**************************************************************************** + * Name: esp32c3_dma_enable + * + * Description: + * Enable DMA channel transmission. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_enable(int chan, bool tx); + +/**************************************************************************** + * Name: esp32c3_dma_disable + * + * Description: + * Disable DMA channel transmission. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_disable(int chan, bool tx); + +/**************************************************************************** + * Name: esp32c3_dma_wait_idle + * + * Description: + * Wait until transmission ends. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_wait_idle(int chan, bool tx); + +/**************************************************************************** + * Name: esp32c3_dma_init + * + * Description: + * Initialize DMA driver. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse.c b/arch/risc-v/src/esp32c3/esp32c3_efuse.c new file mode 100644 index 00000000000..c44b0ed7d8c --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_efuse.c @@ -0,0 +1,712 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_efuse.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "hardware/esp32c3_soc.h" +#include "hardware/esp32c3_efuse.h" + +#include "esp32c3_clockconfig.h" +#include "esp32c3_efuse.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EFUSE_CONF_WRITE 0x5a5a /* eFuse_pgm_op_ena, force no rd/wr dis. */ +#define EFUSE_CONF_READ 0x5aa5 /* eFuse_read_op_ena, release force. */ +#define EFUSE_CMD_PGM 0x02 /* Command to program. */ +#define EFUSE_CMD_READ 0x01 /* Command to read. */ +#define EFUSE_MAX_BLK_LEN 256 /* Max length of efuse block. */ + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_start_efuse_rdreg[11] = +{ + EFUSE_RD_WR_DIS_REG, + EFUSE_RD_MAC_SPI_SYS_0_REG, + EFUSE_RD_SYS_DATA_PART1_0_REG, + EFUSE_RD_USR_DATA0_REG, + EFUSE_RD_KEY0_DATA0_REG, + EFUSE_RD_KEY1_DATA0_REG, + EFUSE_RD_KEY2_DATA0_REG, + EFUSE_RD_KEY3_DATA0_REG, + EFUSE_RD_KEY4_DATA0_REG, + EFUSE_RD_KEY5_DATA0_REG, + EFUSE_RD_SYS_DATA_PART2_0_REG +}; + +static uint32_t g_start_efuse_wrreg[2] = +{ + EFUSE_PGM_DATA0_REG, + EFUSE_PGM_CHECK_VALUE0_REG +}; + +/**************************************************************************** + * Private Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_efuse_set_timing + * + * Description: + * Modify both EFUSE_CLK_REG and EFUSE_DAC_CONF_REG + * for match ABP frequency in Hertz. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32c3_efuse_set_timing(void) +{ + uint32_t apb_freq_mhz = esp32c3_clk_apb_freq() / 1000000; + uint32_t clk_sel0; + uint32_t clk_sel1; + uint32_t dac_clk_div; + + if (apb_freq_mhz <= 26) + { + clk_sel0 = 250; + clk_sel1 = 255; + dac_clk_div = 52; + } + else + { + if (apb_freq_mhz <= 40) + { + clk_sel0 = 160; + clk_sel1 = 255; + dac_clk_div = 80; + } + else + { + clk_sel0 = 80; + clk_sel1 = 128; + dac_clk_div = 100; + } + } + + modifyreg32(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div); + modifyreg32(EFUSE_CLK_REG, EFUSE_DAC_CLK_DIV, clk_sel0); + modifyreg32(EFUSE_CLK_REG, EFUSE_DAC_CLK_DIV, clk_sel1); + return OK; +} + +/**************************************************************************** + * Name: esp32c3_efuse_get_mask + * + * Description: + * Return mask with required the number of ones with shift. + * + * Input Parameters: + * bit_count - The number of bits required + * shift - The shift of programmed as, '1' or '0' + * + * Returned Value: + * The mask with required the number of ones with shift. + * + ****************************************************************************/ + +static uint32_t esp32c3_efuse_get_mask(uint32_t bit_count, uint32_t shift) +{ + uint32_t mask; + + if (bit_count != 32) + { + mask = (1 << bit_count) - 1; + } + else + { + mask = 0xffffffff; + } + + return mask << shift; +} + +/**************************************************************************** + * Name: esp32c3_efuse_get_reg_num + * + * Description: + * Returns the number of bits in the register. + * + * Input Parameters: + * bit_offset - Start bit in block + * bit_count - The number of bits required + * i_reg - The register number in the block + * + * Returned Value: + * The register number in the array. + * + ****************************************************************************/ + +static int esp32c3_efuse_get_reg_num(int bit_offset, + int bit_count, int i_reg) +{ + uint32_t bit_start = (bit_offset % EFUSE_MAX_BLK_LEN); + int num_reg = i_reg + bit_start / 32; + + if (num_reg > (bit_start + bit_count - 1) / 32) + { + return -1; + } + + return num_reg; +} + +/**************************************************************************** + * Name: esp32c3_efuse_get_count_bits_in_reg + * + * Description: + * Returns the number of bits in the register. + * + * Input Parameters: + * bit_offset - Start bit in block + * bit_count - The number of bits required + * i_reg - The register number in the block + * + * Returned Value: + * The number of bits in the register. + * + ****************************************************************************/ + +static int esp32c3_efuse_get_count_bits_in_reg(int bit_offset, + int bit_count, int i_reg) +{ + int ret_count = 0; + int num_reg = 0; + int bit_start = (bit_offset % EFUSE_MAX_BLK_LEN); + int last_used_bit = (bit_start + bit_count - 1); + + for (int num_bit = bit_start; num_bit <= last_used_bit; ++num_bit) + { + ++ret_count; + if ((((num_bit + 1) % 32) == 0) || (num_bit == last_used_bit)) + { + if (i_reg == num_reg) + { + return ret_count; + } + + ++num_reg; + ret_count = 0; + } + } + + return 0; +} + +/**************************************************************************** + * Name: esp32c3_efuse_get_field_size + * + * Description: + * Get the length of the field in bits. + * + * Input Parameters: + * field - Pointer to the structure describing the efuse field + * + * Returned Value: + * The length of the field in bits. + * + ****************************************************************************/ + +static int esp32c3_efuse_get_field_size(const efuse_desc_t *field[]) +{ + int bits_counter = 0; + + if (field != NULL) + { + int i = 0; + + while (field[i] != NULL) + { + bits_counter += field[i]->bit_count; + ++i; + } + } + + return bits_counter; +} + +/**************************************************************************** + * Name: esp32c3_efuse_check_range_of_bits + * + * Description: + * Check range of bits for any coding scheme. + * + * Input Parameters: + * offset_in_bits - The bit offset related to beginning of efuse + * size_bits - The length of bit field + * + * Returned Value: + * True is returned if the bits offset matched. Otherwise false. + * + ****************************************************************************/ + +static bool esp32c3_efuse_check_range_of_bits(int offset_in_bits, + int size_bits) +{ + int blk_offset = offset_in_bits % EFUSE_MAX_BLK_LEN; + int max_num_bit = blk_offset + size_bits; + + if (max_num_bit > EFUSE_MAX_BLK_LEN) + { + return false; + } + + return true; +} + +/**************************************************************************** + * Name: esp32c3_efuse_get_number_of_items + * + * Description: + * Returns the number of array elements for placing these bits in an array + * with the length of each element equal to size_of_base. + * + * Input Parameters: + * bits - The number of bits required + * size_of_base - The base of bits required + * + * Returned Value: + * The number of array elements. + * + ****************************************************************************/ + +static int esp32c3_efuse_get_number_of_items(int bits, int size_of_base) +{ + return bits / size_of_base + (bits % size_of_base > 0 ? 1 : 0); +} + +/**************************************************************************** + * Name: esp32c3_efuse_fill_reg + * + * Description: + * Fill efuse register from array. + * + * Input Parameters: + * bit_start_in_reg - Start bit in block + * bit_count_in_reg - The number of bits required to write + * blob - A pointer that will contain the value + * filled_bits_blob - A pointer that will contain the bits counter + * + * Returned Value: + * The value to write efuse register. + * + ****************************************************************************/ + +static uint32_t esp32c3_efuse_fill_reg(int bit_start_in_reg, + int bit_count_in_reg, + uint8_t *blob, int *filled_bits_blob) +{ + uint32_t reg_to_write = 0; + uint32_t temp_blob_32; + int shift_reg; + int shift_bit = (*filled_bits_blob) % 8; + + if (shift_bit != 0) + { + temp_blob_32 = blob[(*filled_bits_blob) / 8] >> shift_bit; + shift_bit = MIN((8 - shift_bit), bit_count_in_reg); + + reg_to_write = temp_blob_32 & esp32c3_efuse_get_mask(shift_bit, 0); + (*filled_bits_blob) += shift_bit; + bit_count_in_reg -= shift_bit; + } + + shift_reg = shift_bit; + + while (bit_count_in_reg > 0) + { + temp_blob_32 = blob[(*filled_bits_blob) / 8]; + shift_bit = MIN(bit_count_in_reg, 8); + reg_to_write |= (temp_blob_32 & \ + esp32c3_efuse_get_mask(shift_bit, 0)) << shift_reg; + (*filled_bits_blob) += shift_bit; + bit_count_in_reg -= shift_bit; + shift_reg += 8; + }; + + return reg_to_write << bit_start_in_reg; +} + +/**************************************************************************** + * Name: esp32c3_efuse_process + * + * Description: + * Processes the field by calling the passed function. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * ptr - A pointer to array that will contain the result + * ptr_size_bits - The number of bits required to read + * func_proc - A callback for handle the efuse field register + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32c3_efuse_process(const efuse_desc_t *field[], void *ptr, + size_t ptr_size_bits, + efuse_func_proc_t func_proc) +{ + int err = OK; + int bits_counter = 0; + int field_len; + int req_size; + int i = 0; + + /* get and check size */ + + field_len = esp32c3_efuse_get_field_size(field); + req_size = (ptr_size_bits == 0) ? field_len : \ + MIN(ptr_size_bits, field_len); + + while (err == OK && req_size > bits_counter && field[i] != NULL) + { + int i_reg = 0; + int num_reg; + + if (esp32c3_efuse_check_range_of_bits(field[i]->bit_offset, + field[i]->bit_count) == false) + { + minfo("Range of data does not match the coding scheme"); + err = -EINVAL; + } + + while (err == OK && req_size > bits_counter && + (num_reg = esp32c3_efuse_get_reg_num(field[i]->bit_offset, + field[i]->bit_count, i_reg)) != -1) + { + int num_bits = esp32c3_efuse_get_count_bits_in_reg( + field[i]->bit_offset, + field[i]->bit_count, + i_reg); + int bit_offset = field[i]->bit_offset; + + if ((bits_counter + num_bits) > req_size) + { + /* Limits the length of the field */ + + num_bits = req_size - bits_counter; + } + + err = func_proc(num_reg, bit_offset, num_bits, ptr, &bits_counter); + ++i_reg; + } + + i++; + } + + DEBUGASSERT(bits_counter <= req_size); + return err; +} + +/**************************************************************************** + * Name: esp32c3_efuse_write_reg + * + * Description: + * Write value to efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * value - Value to write + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32c3_efuse_write_reg(uint32_t blk, uint32_t num_reg, + uint32_t value) +{ + uint32_t addr_wr_reg; + uint32_t reg_to_write; + uint32_t blk_start = g_start_efuse_wrreg[blk]; + + DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); + + DEBUGASSERT(num_reg <= 7); + + /* The block 0 and register 7 doesn't exist */ + + if (blk == 0 && num_reg == 7) + { + merr("Block 0 Register 7 doesn't exist!\n"); + return; + } + + addr_wr_reg = blk_start + num_reg * 4; + reg_to_write = getreg32(addr_wr_reg) | value; + + /* The register can be written in parts so we combine the new value + * with the one already available. + */ + + putreg32(reg_to_write, addr_wr_reg); +} + +/**************************************************************************** + * Name: esp32c3_efuse_write_blob + * + * Description: + * Fill registers from array for writing. + * + * Input Parameters: + * num_reg - The register number in the block + * bit_offset - Start bit in block + * bit_count - The number of bits required to read + * arr_in - A pointer to array that will contain the value of writing + * bits_counter - A pointer that will contain the bits counter of writing + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32c3_efuse_write_blob(uint32_t num_reg, int bit_offset, + int bit_count, void *arr_in, + int *bits_counter) +{ + uint32_t block = (bit_offset / EFUSE_MAX_BLK_LEN); + uint32_t bit_start = (bit_offset % EFUSE_MAX_BLK_LEN); + uint32_t reg_to_write = esp32c3_efuse_fill_reg(bit_start, bit_count, + (uint8_t *) arr_in, + bits_counter); + + esp32c3_efuse_write_reg(block, num_reg, reg_to_write); + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_efuse_read_reg + * + * Description: + * Read efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * + * Returned Value: + * Return the value in the efuse register. + * + ****************************************************************************/ + +static uint32_t esp32c3_efuse_read_reg(uint32_t blk, uint32_t num_reg) +{ + DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); + uint32_t value; + uint32_t blk_start = g_start_efuse_rdreg[blk]; + + DEBUGASSERT(num_reg <= 7); + + value = getreg32(blk_start + num_reg * 4); + return value; +} + +/**************************************************************************** + * Name: esp32c3_efuse_fill_buff + * + * Description: + * Read efuse register and write this value to array. + * + * Input Parameters: + * num_reg - The register number in the block + * bit_offset - Start bit in block + * bit_count - The number of bits required to read + * arr_out - A pointer to array that will contain the result + * bits_counter - A pointer that will contain the bits counter of reading + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32c3_efuse_fill_buff(uint32_t num_reg, int bit_offset, + int bit_count, void *arr_out, + int *bits_counter) +{ + uint8_t *blob = (uint8_t *) arr_out; + uint32_t efuse_block = (bit_offset / EFUSE_MAX_BLK_LEN); + uint32_t bit_start = (bit_offset % EFUSE_MAX_BLK_LEN); + uint32_t reg = esp32c3_efuse_read_reg(efuse_block, num_reg); + uint64_t reg_of_aligned_bits = (reg >> bit_start) & \ + esp32c3_efuse_get_mask(bit_count, 0); + int sum_shift = 0; + int shift_bit = (*bits_counter) % 8; + + if (shift_bit != 0) + { + blob[(*bits_counter) / 8] |= (uint8_t)(reg_of_aligned_bits << \ + shift_bit); + shift_bit = ((8 - shift_bit) < bit_count) ? (8 - shift_bit) : \ + bit_count; + (*bits_counter) += shift_bit; + bit_count -= shift_bit; + } + + while (bit_count > 0) + { + sum_shift += shift_bit; + blob[(*bits_counter) / 8] |= (uint8_t)(reg_of_aligned_bits >> \ + sum_shift); + shift_bit = (bit_count > 8) ? 8 : bit_count; + (*bits_counter) += shift_bit; + bit_count -= shift_bit; + }; + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_efuse_read_field + * + * Description: + * Read value from EFUSE, writing it into an array. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * dst - A pointer to array that contains the data for reading + * dst_size_bits - The number of bits required to read + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_read_field(const efuse_desc_t *field[], void *dst, + size_t dst_size_bits) +{ + int err = OK; + + if (field == NULL || dst == NULL || dst_size_bits == 0) + { + err = -EINVAL; + } + else + { + memset((uint8_t *)dst, 0, + esp32c3_efuse_get_number_of_items(dst_size_bits, 8)); + + err = esp32c3_efuse_process(field, dst, dst_size_bits, + esp32c3_efuse_fill_buff); + } + + return err; +} + +/**************************************************************************** + * Name: esp32c3_efuse_write_field + * + * Description: + * Write array to EFUSE. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * src - A pointer to array that contains the data for writing + * src_size_bits - The number of bits required to write + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_write_field(const efuse_desc_t *field[], + const void *src, size_t src_size_bits) +{ + int err = OK; + + if (field == NULL || src == NULL || src_size_bits == 0) + { + err = -EINVAL; + } + else + { + err = esp32c3_efuse_process(field, (void *)src, src_size_bits, + esp32c3_efuse_write_blob); + } + + return err; +} + +/**************************************************************************** + * Name: esp32c3_efuse_burn_efuses + * + * Description: + * Burn values written to the efuse write registers. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_efuse_burn_efuses(void) +{ + esp32c3_efuse_set_timing(); + + /* Permanently update values written to the efuse write registers */ + + putreg32(EFUSE_CONF_WRITE, EFUSE_CONF_REG); + putreg32(EFUSE_CMD_PGM, EFUSE_CMD_REG); + + while (getreg32(EFUSE_CMD_REG) != 0) + { + }; + + putreg32(EFUSE_CONF_READ, EFUSE_CONF_REG); + putreg32(EFUSE_CMD_READ, EFUSE_CMD_REG); + + while (getreg32(EFUSE_CMD_REG) != 0) + { + }; +} + diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse.h b/arch/risc-v/src/esp32c3/esp32c3_efuse.h new file mode 100644 index 00000000000..eaf95c4518f --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_efuse.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_EFUSE_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Type of eFuse blocks for ESP32C3 */ + +typedef enum +{ + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA */ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA */ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY_MAX = 10, + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/**************************************************************************** + * Name: efuse_func_proc_t + * + * Description: + * This is type of function that will handle the efuse field register. + * + * Input Parameters: + * num_reg - The register number in the block. + * bit_start - Start bit in the register. + * bit_count - The number of bits used in the register. + * arr - A pointer to an array or variable. + * bits_counter - Counter bits. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +typedef int (*efuse_func_proc_t) (uint32_t num_reg, + int bit_start, + int bit_count, + void *arr, int *bits_counter); + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_efuse_read_field + * + * Description: + * Read value from EFUSE, writing it into an array. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * dst - A pointer to array that contains the data for reading + * dst_size_bits - The number of bits required to read + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_read_field(const efuse_desc_t *field[], void *dst, + size_t dst_size_bits); + +/**************************************************************************** + * Name: esp32c3_efuse_write_field + * + * Description: + * Write array to EFUSE. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * src - A pointer to array that contains the data for writing + * src_size_bits - The number of bits required to write + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_write_field(const efuse_desc_t *field[], + const void *src, size_t src_size_bits); + +/**************************************************************************** + * Name: esp32c3_efuse_burn_efuses + * + * Description: + * Burn values written to the efuse write registers. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_efuse_burn_efuses(void); + +/**************************************************************************** + * Name: esp32c3_efuse_initialize + * + * Description: + * Initialize the efuse driver. The efuse is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the efuse device. + * This should be of the form /dev/efuse + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_initialize(FAR const char *devpath); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_EFUSE_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse_lowerhalf.c b/arch/risc-v/src/esp32c3/esp32c3_efuse_lowerhalf.c new file mode 100644 index 00000000000..f347b385207 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_efuse_lowerhalf.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_efuse_lowerhalf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "hardware/esp32c3_soc.h" +#include "esp32c3_efuse.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +struct esp32c3_efuse_lowerhalf_s +{ + FAR const struct efuse_ops_s *ops; /* Lower half operations */ + void *upper; /* Pointer to efuse_upperhalf_s */ +}; + +/**************************************************************************** + * Private Functions Prototypes + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static int esp32c3_efuse_lowerhalf_read(FAR struct efuse_lowerhalf_s *lower, + const efuse_desc_t *field[], + uint8_t *data, size_t bits_len); +static int esp32c3_efuse_lowerhalf_write(FAR struct efuse_lowerhalf_s *lower, + const efuse_desc_t *field[], + const uint8_t *data, + size_t bits_len); +static int esp32c3_efuse_lowerhalf_ioctl(FAR struct efuse_lowerhalf_s *lower, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct efuse_ops_s g_esp32c3_efuse_ops = +{ + .read_field = esp32c3_efuse_lowerhalf_read, + .write_field = esp32c3_efuse_lowerhalf_write, + .ioctl = esp32c3_efuse_lowerhalf_ioctl, +}; + +/* EFUSE lower-half */ + +static struct esp32c3_efuse_lowerhalf_s g_esp32c3_efuse_lowerhalf = +{ + .ops = &g_esp32c3_efuse_ops, + .upper = NULL, +}; + +/**************************************************************************** + * Private functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_efuse_lowerhalf_read + * + * Description: + * Read value from EFUSE, writing it into an array. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure + * field - A pointer to describing the fields of efuse + * dst - A pointer to array that contains the data for reading + * bits_len - The number of bits required to read + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32c3_efuse_lowerhalf_read(FAR struct efuse_lowerhalf_s *lower, + const efuse_desc_t *field[], + uint8_t *data, size_t bits_len) +{ + int ret = OK; + + /* Read the requested field */ + + ret = esp32c3_efuse_read_field(field, data, bits_len); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_efuse_lowerhalf_write + * + * Description: + * Write array to EFUSE. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure + * field - A pointer to describing the fields of efuse + * data - A pointer to array that contains the data for writing + * bits_len - The number of bits required to write + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32c3_efuse_lowerhalf_write(FAR struct efuse_lowerhalf_s *lower, + const efuse_desc_t *field[], + const uint8_t *data, + size_t bits_len) +{ + irqstate_t flags; + int ret = OK; + + flags = enter_critical_section(); + + /* Write the blob data to the field */ + + ret = esp32c3_efuse_write_field(field, data, bits_len); + + /* Burn the EFUSEs */ + + esp32c3_efuse_burn_efuses(); + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_efuse_lowerhalf_ioctl + * + * Description: + * Initialize the efuse driver. The efuse is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure + * cmd - The ioctl command value + * arg - The optional argument that accompanies the 'cmd' + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32c3_efuse_lowerhalf_ioctl(FAR struct efuse_lowerhalf_s *lower, + int cmd, unsigned long arg) +{ + int ret = OK; + + switch (cmd) + { + /* We don't have proprietary EFUSE ioctls */ + + default: + { + minfo("Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + } + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_efuse_initialize + * + * Description: + * Initialize the efuse driver. The efuse is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the efuse device. + * This should be of the form /dev/efuse + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_initialize(FAR const char *devpath) +{ + struct esp32c3_efuse_lowerhalf_s *lower = NULL; + int ret = OK; + + DEBUGASSERT(devpath != NULL); + + lower = &g_esp32c3_efuse_lowerhalf; + + /* Register the efuse upper driver */ + + lower->upper = efuse_register(devpath, + (FAR struct efuse_lowerhalf_s *)lower); + + if (lower->upper == NULL) + { + /* The actual cause of the failure may have been a failure to allocate + * perhaps a failure to register the efuser driver (such as if the + * 'devpath' were not unique). We know here but we return EEXIST to + * indicate the failure (implying the non-unique devpath). + */ + + ret = -EEXIST; + } + + return ret; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse_table.c b/arch/risc-v/src/esp32c3/esp32c3_efuse_table.c new file mode 100644 index 00000000000..9eaeef685c1 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_efuse_table.c @@ -0,0 +1,1360 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_efuse_table.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include "esp32c3_efuse.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +static const efuse_desc_t WR_DIS_RD_DIS[] = +{ + { + 0, 1 /* Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, */ + }, +}; + +static const efuse_desc_t WR_DIS_GROUP_1[] = +{ + { + 2, 1 /* Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, */ + }, +}; + +static const efuse_desc_t WR_DIS_GROUP_2[] = +{ + { + 3, 1 /* Write protection for WDT_DELAY_SEL, */ + }, +}; + +static const efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = +{ + { + 4, 1 /* Write protection for SPI_BOOT_CRYPT_CNT, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = +{ + { + 5, 1 /* Write protection for SECURE_BOOT_KEY_REVOKE0, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = +{ + { + 6, 1 /* Write protection for SECURE_BOOT_KEY_REVOKE1, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = +{ + { + 7, 1 /* Write protection for SECURE_BOOT_KEY_REVOKE2, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY0_PURPOSE[] = +{ + { + 8, 1 /* Write protection for key_purpose. KEY0, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY1_PURPOSE[] = +{ + { + 9, 1 /* Write protection for key_purpose. KEY1, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY2_PURPOSE[] = +{ + { + 10, 1 /* Write protection for key_purpose. KEY2, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY3_PURPOSE[] = +{ + { + 11, 1 /* Write protection for key_purpose. KEY3, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY4_PURPOSE[] = +{ + { + 12, 1 /* Write protection for key_purpose. KEY4, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY5_PURPOSE[] = +{ + { + 13, 1 /* Write protection for key_purpose. KEY5, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = +{ + { + 15, 1 /* Write protection for SECURE_BOOT_EN, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = +{ + { + 16, 1 /* Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, */ + }, +}; + +static const efuse_desc_t WR_DIS_GROUP_3[] = +{ + { + 18, 1 /* Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, */ + }, +}; + +static const efuse_desc_t WR_DIS_BLK1[] = +{ + { + 20, 1 /* Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, */ + }, +}; + +static const efuse_desc_t WR_DIS_SYS_DATA_PART1[] = +{ + { + 21, 1 /* Write protection for EFUSE_BLK2. SYS_DATA_PART1, */ + }, +}; + +static const efuse_desc_t WR_DIS_USER_DATA[] = +{ + { + 22, 1 /* Write protection for EFUSE_BLK3. USER_DATA, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY0[] = +{ + { + 23, 1 /* Write protection for EFUSE_BLK4. KEY0, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY1[] = +{ + { + 24, 1 /* Write protection for EFUSE_BLK5. KEY1, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY2[] = +{ + { + 25, 1 /* Write protection for EFUSE_BLK6. KEY2, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY3[] = +{ + { + 26, 1 /* Write protection for EFUSE_BLK7. KEY3, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY4[] = +{ + { + 27, 1 /* Write protection for EFUSE_BLK8. KEY4, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY5[] = +{ + { + 28, 1 /* Write protection for EFUSE_BLK9. KEY5, */ + }, +}; + +static const efuse_desc_t WR_DIS_SYS_DATA_PART2[] = +{ + { + 29, 1 /* Write protection for EFUSE_BLK10. SYS_DATA_PART2, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY0[] = +{ + { + 32, 1 /* Read protection for EFUSE_BLK4. KEY0, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY1[] = +{ + { + 33, 1 /* Read protection for EFUSE_BLK5. KEY1, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY2[] = +{ + { + 34, 1 /* Read protection for EFUSE_BLK6. KEY2, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY3[] = +{ + { + 35, 1 /* Read protection for EFUSE_BLK7. KEY3, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY4[] = +{ + { + 36, 1 /* Read protection for EFUSE_BLK8. KEY4, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY5[] = +{ + { + 37, 1 /* Read protection for EFUSE_BLK9. KEY5, */ + }, +}; + +static const efuse_desc_t RD_DIS_SYS_DATA_PART2[] = +{ + { + 38, 1 /* Read protection for EFUSE_BLK10. SYS_DATA_PART2, */ + }, +}; + +static const efuse_desc_t DIS_RTC_RAM_BOOT[] = +{ + { + 39, 1 /* Disable boot from RTC RAM, */ + }, +}; + +static const efuse_desc_t DIS_ICACHE[] = +{ + { + 40, 1 /* Disable Icache, */ + }, +}; + +static const efuse_desc_t DIS_USB_JTAG[] = +{ + { + 41, 1 /* Disable USB JTAG, */ + }, +}; + +static const efuse_desc_t DIS_DOWNLOAD_ICACHE[] = +{ + { + 42, 1 /* Disable Icache in download mode, */ + }, +}; + +static const efuse_desc_t DIS_USB_DEVICE[] = +{ + { + 43, 1 /* Disable USB_DEVICE, */ + }, +}; + +static const efuse_desc_t DIS_FORCE_DOWNLOAD[] = +{ + { + 44, 1 /* Disable force chip go to download mode function, */ + }, +}; + +static const efuse_desc_t DIS_USB[] = +{ + { + 45, 1 /* Disable USB function, */ + }, +}; + +static const efuse_desc_t DIS_CAN[] = +{ + { + 46, 1 /* Disable CAN function, */ + }, +}; + +static const efuse_desc_t JTAG_SEL_ENABLE[] = +{ + { + 47, 1 /* Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0., */ + }, +}; + +static const efuse_desc_t SOFT_DIS_JTAG[] = +{ + { + 48, 2 /* Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module., */ + }, +}; + +static const efuse_desc_t DIS_PAD_JTAG[] = +{ + { + 51, 1 /* Disable JTAG in the hard way. JTAG is disabled permanently., */ + }, +}; + +static const efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = +{ + { + 52, 1 /* Disable flash encryption when in download boot modes., */ + }, +}; + +static const efuse_desc_t USB_DREFH[] = +{ + { + 53, 2 /* Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse., */ + }, +}; + +static const efuse_desc_t USB_DREFL[] = +{ + { + 55, 2 /* Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse., */ + }, +}; + +static const efuse_desc_t USB_EXCHG_PINS[] = +{ + { + 57, 1 /* Exchange D+ D- pins, */ + }, +}; + +static const efuse_desc_t VDD_SPI_AS_GPIO[] = +{ + { + 58, 1 /* Set this bit to vdd spi pin function as gpio, */ + }, +}; + +static const efuse_desc_t BTLC_GPIO_ENABLE[] = +{ + { + 59, 2 /* Enable btlc gpio, */ + }, +}; + +static const efuse_desc_t POWERGLITCH_EN[] = +{ + { + 61, 1 /* Set this bit to enable power glitch function, */ + }, +}; + +static const efuse_desc_t POWER_GLITCH_DSENSE[] = +{ + { + 62, 2 /* Sample delay configuration of power glitch, */ + }, +}; + +static const efuse_desc_t WDT_DELAY_SEL[] = +{ + { + 80, 2 /* Select RTC WDT time out threshold, */ + }, +}; + +static const efuse_desc_t SPI_BOOT_CRYPT_CNT[] = +{ + { + 82, 3 /* SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = +{ + { + 85, 1 /* Enable revoke first secure boot key, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = +{ + { + 86, 1 /* Enable revoke second secure boot key, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = +{ + { + 87, 1 /* Enable revoke third secure boot key, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_0[] = +{ + { + 88, 4 /* Key0 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_1[] = +{ + { + 92, 4 /* Key1 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_2[] = +{ + { + 96, 4 /* Key2 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_3[] = +{ + { + 100, 4 /* Key3 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_4[] = +{ + { + 104, 4 /* Key4 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_5[] = +{ + { + 108, 4 /* Key5 purpose, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_EN[] = +{ + { + 116, 1 /* Secure boot enable, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = +{ + { + 117, 1 /* Enable aggressive secure boot revoke, */ + }, +}; + +static const efuse_desc_t FLASH_TPUW[] = +{ + { + 124, 4 /* Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, */ + }, +}; + +static const efuse_desc_t DIS_DOWNLOAD_MODE[] = +{ + { + 128, 1 /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, */ + }, +}; + +static const efuse_desc_t DIS_LEGACY_SPI_BOOT[] = +{ + { + 129, 1 /* Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4, */ + }, +}; + +static const efuse_desc_t UART_PRINT_CHANNEL[] = +{ + { + 130, 1 /* 0: UART0. 1: UART1, */ + }, +}; + +static const efuse_desc_t FLASH_ECC_MODE[] = +{ + { + 131, 1 /* Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode, */ + }, +}; + +static const efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = +{ + { + 132, 1 /* Disable download through USB, */ + }, +}; + +static const efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = +{ + { + 133, 1 /* Enable security download mode, */ + }, +}; + +static const efuse_desc_t UART_PRINT_CONTROL[] = +{ + { + 134, 2 /* b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print., */ + }, +}; + +static const efuse_desc_t PIN_POWER_SELECTION[] = +{ + { + 136, 1 /* GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI., */ + }, +}; + +static const efuse_desc_t FLASH_TYPE[] = +{ + { + 137, 1 /* Connected Flash interface type. 0: 4 data line. 1: 8 data line, */ + }, +}; + +static const efuse_desc_t FLASH_PAGE_SIZE[] = +{ + { + 138, 2 /* Flash page size, */ + }, +}; + +static const efuse_desc_t FLASH_ECC_EN[] = +{ + { + 140, 1 /* Enable ECC for flash boot, */ + }, +}; + +static const efuse_desc_t FORCE_SEND_RESUME[] = +{ + { + 141, 1 /* Force ROM code to send a resume command during SPI boot, */ + }, +}; + +static const efuse_desc_t SECURE_VERSION[] = +{ + { + 142, 16 /* Secure version for anti-rollback, */ + }, +}; + +static const efuse_desc_t MAC_FACTORY[] = +{ + { + 296, 8 /* Factory MAC addr [0], */ + }, + { + 288, 8 /* Factory MAC addr [1], */ + }, + { + 280, 8 /* Factory MAC addr [2], */ + }, + { + 272, 8 /* Factory MAC addr [3], */ + }, + { + 264, 8 /* Factory MAC addr [4], */ + }, + { + 256, 8 /* Factory MAC addr [5], */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_CLK[] = +{ + { + 304, 6 /* SPI_PAD_configure CLK, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = +{ + { + 310, 6 /* SPI_PAD_configure Q(D1), */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D_D0[] = +{ + { + 316, 6 /* SPI_PAD_configure D(D0), */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_CS[] = +{ + { + 322, 6 /* SPI_PAD_configure CS, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = +{ + { + 328, 6 /* SPI_PAD_configure HD(D3), */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = +{ + { + 334, 6 /* SPI_PAD_configure WP(D2), */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_DQS[] = +{ + { + 340, 6 /* SPI_PAD_configure DQS, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D4[] = +{ + { + 346, 6 /* SPI_PAD_configure D4, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D5[] = +{ + { + 352, 6 /* SPI_PAD_configure D5, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D6[] = +{ + { + 358, 6 /* SPI_PAD_configure D6, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D7[] = +{ + { + 364, 6 /* SPI_PAD_configure D7, */ + }, +}; + +static const efuse_desc_t SYS_DATA_PART1[] = +{ + { + 512, 256 /* System configuration, */ + }, +}; + +static const efuse_desc_t USER_DATA[] = +{ + { + 768, 256 /* User data, */ + }, +}; + +static const efuse_desc_t KEY0[] = +{ + { + 1024, 256 /* Key0 or user data, */ + }, +}; + +static const efuse_desc_t KEY1[] = +{ + { + 1280, 256 /* Key1 or user data, */ + }, +}; + +static const efuse_desc_t KEY2[] = +{ + { + 1536, 256 /* Key2 or user data, */ + }, +}; + +static const efuse_desc_t KEY3[] = +{ + { + 1792, 256 /* Key3 or user data, */ + }, +}; + +static const efuse_desc_t KEY4[] = +{ + { + 2048, 256 /* Key4 or user data, */ + }, +}; + +static const efuse_desc_t KEY5[] = +{ + { + 2304, 256 /* Key5 or user data, */ + }, +}; + +static const efuse_desc_t SYS_DATA_PART2[] = +{ + { + 2560, 256 /* System configuration, */ + }, +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_RD_DIS[] = +{ + &WR_DIS_RD_DIS[0], /* Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_1[] = +{ + &WR_DIS_GROUP_1[0], /* Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_2[] = +{ + &WR_DIS_GROUP_2[0], /* Write protection for WDT_DELAY_SEL */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = +{ + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], /* Write protection for SPI_BOOT_CRYPT_CNT */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = +{ + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], /* Write protection for SECURE_BOOT_KEY_REVOKE0 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = +{ + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], /* Write protection for SECURE_BOOT_KEY_REVOKE1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = +{ + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], /* Write protection for SECURE_BOOT_KEY_REVOKE2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = +{ + &WR_DIS_KEY0_PURPOSE[0], /* Write protection for key_purpose. KEY0 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = +{ + &WR_DIS_KEY1_PURPOSE[0], /* Write protection for key_purpose. KEY1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = +{ + &WR_DIS_KEY2_PURPOSE[0], /* Write protection for key_purpose. KEY2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = +{ + &WR_DIS_KEY3_PURPOSE[0], /* Write protection for key_purpose. KEY3 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = +{ + &WR_DIS_KEY4_PURPOSE[0], /* Write protection for key_purpose. KEY4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = +{ + &WR_DIS_KEY5_PURPOSE[0], /* Write protection for key_purpose. KEY5 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = +{ + &WR_DIS_SECURE_BOOT_EN[0], /* Write protection for SECURE_BOOT_EN */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = +{ + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], /* Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_3[] = +{ + &WR_DIS_GROUP_3[0], /* Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK1[] = +{ + &WR_DIS_BLK1[0], /* Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = +{ + &WR_DIS_SYS_DATA_PART1[0], /* Write protection for EFUSE_BLK2. SYS_DATA_PART1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_USER_DATA[] = +{ + &WR_DIS_USER_DATA[0], /* Write protection for EFUSE_BLK3. USER_DATA */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY0[] = +{ + &WR_DIS_KEY0[0], /* Write protection for EFUSE_BLK4. KEY0 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY1[] = +{ + &WR_DIS_KEY1[0], /* Write protection for EFUSE_BLK5. KEY1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY2[] = +{ + &WR_DIS_KEY2[0], /* Write protection for EFUSE_BLK6. KEY2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY3[] = +{ + &WR_DIS_KEY3[0], /* Write protection for EFUSE_BLK7. KEY3 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY4[] = +{ + &WR_DIS_KEY4[0], /* Write protection for EFUSE_BLK8. KEY4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY5[] = +{ + &WR_DIS_KEY5[0], /* Write protection for EFUSE_BLK9. KEY5 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = +{ + &WR_DIS_SYS_DATA_PART2[0], /* Write protection for EFUSE_BLK10. SYS_DATA_PART2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY0[] = +{ + &RD_DIS_KEY0[0], /* Read protection for EFUSE_BLK4. KEY0 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY1[] = +{ + &RD_DIS_KEY1[0], /* Read protection for EFUSE_BLK5. KEY1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY2[] = +{ + &RD_DIS_KEY2[0], /* Read protection for EFUSE_BLK6. KEY2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY3[] = +{ + &RD_DIS_KEY3[0], /* Read protection for EFUSE_BLK7. KEY3 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY4[] = +{ + &RD_DIS_KEY4[0], /* Read protection for EFUSE_BLK8. KEY4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY5[] = +{ + &RD_DIS_KEY5[0], /* Read protection for EFUSE_BLK9. KEY5 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = +{ + &RD_DIS_SYS_DATA_PART2[0], /* Read protection for EFUSE_BLK10. SYS_DATA_PART2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_RTC_RAM_BOOT[] = +{ + &DIS_RTC_RAM_BOOT[0], /* Disable boot from RTC RAM */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_ICACHE[] = +{ + &DIS_ICACHE[0], /* Disable Icache */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_USB_JTAG[] = +{ + &DIS_USB_JTAG[0], /* Disable USB JTAG */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = +{ + &DIS_DOWNLOAD_ICACHE[0], /* Disable Icache in download mode */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_USB_DEVICE[] = +{ + &DIS_USB_DEVICE[0], /* Disable USB_DEVICE */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = +{ + &DIS_FORCE_DOWNLOAD[0], /* Disable force chip go to download mode function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_USB[] = +{ + &DIS_USB[0], /* Disable USB function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_CAN[] = +{ + &DIS_CAN[0], /* Disable CAN function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_JTAG_SEL_ENABLE[] = +{ + &JTAG_SEL_ENABLE[0], /* Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SOFT_DIS_JTAG[] = +{ + &SOFT_DIS_JTAG[0], /* Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_PAD_JTAG[] = +{ + &DIS_PAD_JTAG[0], /* Disable JTAG in the hard way. JTAG is disabled permanently. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = +{ + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], /* Disable flash encryption when in download boot modes. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_USB_DREFH[] = +{ + &USB_DREFH[0], /* Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_USB_DREFL[] = +{ + &USB_DREFL[0], /* Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_USB_EXCHG_PINS[] = +{ + &USB_EXCHG_PINS[0], /* Exchange D+ D- pins */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_VDD_SPI_AS_GPIO[] = +{ + &VDD_SPI_AS_GPIO[0], /* Set this bit to vdd spi pin function as gpio */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_BTLC_GPIO_ENABLE[] = +{ + &BTLC_GPIO_ENABLE[0], /* Enable btlc gpio */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_POWERGLITCH_EN[] = +{ + &POWERGLITCH_EN[0], /* Set this bit to enable power glitch function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_POWER_GLITCH_DSENSE[] = +{ + &POWER_GLITCH_DSENSE[0], /* Sample delay configuration of power glitch */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WDT_DELAY_SEL[] = +{ + &WDT_DELAY_SEL[0], /* Select RTC WDT time out threshold */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = +{ + &SPI_BOOT_CRYPT_CNT[0], /* SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = +{ + &SECURE_BOOT_KEY_REVOKE0[0], /* Enable revoke first secure boot key */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = +{ + &SECURE_BOOT_KEY_REVOKE1[0], /* Enable revoke second secure boot key */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = +{ + &SECURE_BOOT_KEY_REVOKE2[0], /* Enable revoke third secure boot key */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_0[] = +{ + &KEY_PURPOSE_0[0], /* Key0 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_1[] = +{ + &KEY_PURPOSE_1[0], /* Key1 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_2[] = +{ + &KEY_PURPOSE_2[0], /* Key2 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_3[] = +{ + &KEY_PURPOSE_3[0], /* Key3 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_4[] = +{ + &KEY_PURPOSE_4[0], /* Key4 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_5[] = +{ + &KEY_PURPOSE_5[0], /* Key5 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_EN[] = +{ + &SECURE_BOOT_EN[0], /* Secure boot enable */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = +{ + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], /* Enable aggressive secure boot revoke */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FLASH_TPUW[] = +{ + &FLASH_TPUW[0], /* Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MODE[] = +{ + &DIS_DOWNLOAD_MODE[0], /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = +{ + &DIS_LEGACY_SPI_BOOT[0], /* Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_UART_PRINT_CHANNEL[] = +{ + &UART_PRINT_CHANNEL[0], /* 0: UART0. 1: UART1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FLASH_ECC_MODE[] = +{ + &FLASH_ECC_MODE[0], /* Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = +{ + &DIS_USB_DOWNLOAD_MODE[0], /* Disable download through USB */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = +{ + &ENABLE_SECURITY_DOWNLOAD[0], /* Enable security download mode */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_UART_PRINT_CONTROL[] = +{ + &UART_PRINT_CONTROL[0], /* b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_PIN_POWER_SELECTION[] = +{ + &PIN_POWER_SELECTION[0], /* GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FLASH_TYPE[] = +{ + &FLASH_TYPE[0], /* Connected Flash interface type. 0: 4 data line. 1: 8 data line */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FLASH_PAGE_SIZE[] = +{ + &FLASH_PAGE_SIZE[0], /* Flash page size */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FLASH_ECC_EN[] = +{ + &FLASH_ECC_EN[0], /* Enable ECC for flash boot */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FORCE_SEND_RESUME[] = +{ + &FORCE_SEND_RESUME[0], /* Force ROM code to send a resume command during SPI boot */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_VERSION[] = +{ + &SECURE_VERSION[0], /* Secure version for anti-rollback */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_MAC_FACTORY[] = +{ + &MAC_FACTORY[0], /* Factory MAC addr [0] */ + &MAC_FACTORY[1], /* Factory MAC addr [1] */ + &MAC_FACTORY[2], /* Factory MAC addr [2] */ + &MAC_FACTORY[3], /* Factory MAC addr [3] */ + &MAC_FACTORY[4], /* Factory MAC addr [4] */ + &MAC_FACTORY[5], /* Factory MAC addr [5] */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = +{ + &SPI_PAD_CONFIG_CLK[0], /* SPI_PAD_configure CLK */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = +{ + &SPI_PAD_CONFIG_Q_D1[0], /* SPI_PAD_configure Q(D1) */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = +{ + &SPI_PAD_CONFIG_D_D0[0], /* SPI_PAD_configure D(D0) */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_CS[] = +{ + &SPI_PAD_CONFIG_CS[0], /* SPI_PAD_configure CS */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = +{ + &SPI_PAD_CONFIG_HD_D3[0], /* SPI_PAD_configure HD(D3) */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = +{ + &SPI_PAD_CONFIG_WP_D2[0], /* SPI_PAD_configure WP(D2) */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = +{ + &SPI_PAD_CONFIG_DQS[0], /* SPI_PAD_configure DQS */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D4[] = +{ + &SPI_PAD_CONFIG_D4[0], /* SPI_PAD_configure D4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D5[] = +{ + &SPI_PAD_CONFIG_D5[0], /* SPI_PAD_configure D5 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D6[] = +{ + &SPI_PAD_CONFIG_D6[0], /* SPI_PAD_configure D6 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D7[] = +{ + &SPI_PAD_CONFIG_D7[0], /* SPI_PAD_configure D7 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SYS_DATA_PART1[] = +{ + &SYS_DATA_PART1[0], /* System configuration */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_USER_DATA[] = +{ + &USER_DATA[0], /* User data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY0[] = +{ + &KEY0[0], /* Key0 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY1[] = +{ + &KEY1[0], /* Key1 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY2[] = +{ + &KEY2[0], /* Key2 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY3[] = +{ + &KEY3[0], /* Key3 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY4[] = +{ + &KEY4[0], /* Key4 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY5[] = +{ + &KEY5[0], /* Key5 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SYS_DATA_PART2[] = +{ + &SYS_DATA_PART2[0], /* System configuration */ + NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ diff --git a/arch/risc-v/src/esp32c3/esp32c3_extraheaps.c b/arch/risc-v/src/esp32c3/esp32c3_extraheaps.c new file mode 100644 index 00000000000..beb6b96fa6a --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_extraheaps.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_extraheaps.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "hardware/esp32c3_soc.h" + +#ifdef CONFIG_ESP32C3_RTC_HEAP +#include "esp32c3_rtcheap.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_extraheaps_init + * + * Description: + * Initialize any extra heap. + * + ****************************************************************************/ + +void up_extraheaps_init() +{ +#ifdef CONFIG_ESP32C3_RTC_HEAP + /* Initialize the RTC heap */ + + esp32c3_rtcheap_initialize(); +#endif +} + diff --git a/arch/risc-v/src/esp32c3/esp32c3_freerun.c b/arch/risc-v/src/esp32c3/esp32c3_freerun.c new file mode 100644 index 00000000000..635a2497f7b --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_freerun.c @@ -0,0 +1,354 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_freerun.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "esp32c3_freerun.h" +#include "esp32c3_clockconfig.h" +#include "esp32c3_gpio.h" + +#ifdef CONFIG_ESP32C3_FREERUN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MAX_TIMERS 2 +#define MAX_US_RESOLUTION 819 +#define TIMER_WIDTH 54 + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_freerun_handler + * + * Description: + * Timer interrupt callback. When the freerun timer counter overflows, + * this interrupt will occur. We will just increment an overflow counter. + * + * Input Parameters: + * irq - IRQ associated to that interrupt. + * arg - An opaque argument provided when the interrupt + * was registered. + * + * Returned Value: + * OK + * + ****************************************************************************/ + +#ifndef CONFIG_CLOCK_TIMEKEEPING +static int esp32c3_freerun_handler(int irq, void *context, void *arg) +{ + struct esp32c3_freerun_s *freerun = (struct esp32c3_freerun_s *) arg; + + DEBUGASSERT(freerun != NULL); + + freerun->overflow++; + ESP32C3_TIM_SETALRM(freerun->tch, true); /* Re-enables the alarm */ + ESP32C3_TIM_ACKINT(freerun->tch); /* Clear the Interrupt */ + return OK; +} +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_freerun_initialize + * + * Description: + * Initialize the freerun timer wrapper. + * + * Input Parameters: + * freerun - Caller allocated instance of the freerun + * state structure + * chan - Timer counter channel to be used. + * resolution - The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to + * the range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int esp32c3_freerun_initialize(struct esp32c3_freerun_s *freerun, int chan, + uint16_t resolution) +{ + uint16_t pre; + int ret = OK; + + tmrinfo("chan=%d resolution=%d usecs\n", chan, resolution); + + DEBUGASSERT(freerun != NULL); + DEBUGASSERT(chan >= 0); + DEBUGASSERT(chan < MAX_TIMERS); + DEBUGASSERT(resolution > 0); + + /* We can't have a resolution bigger than this. + * The ESP32-C3 prescaler doesn't support. + * max resolution = (max prescaler * USEC_PER_SEC) / esp32c3_clk_apb_freq() + */ + + DEBUGASSERT(resolution <= MAX_US_RESOLUTION); + + freerun->tch = esp32c3_tim_init(chan); + if (freerun->tch == NULL) + { + tmrerr("ERROR: Failed to allocate TIM %d\n", chan); + ret = -EBUSY; + } + else + { + /* Initialize the remaining fields in the state structure. */ + + freerun->chan = chan; + freerun->resolution = resolution; + freerun->max_timeout = (UINT64_C(1) << (TIMER_WIDTH - 1)); + + /* Ensure timer is disabled. + * Change the prescaler divider with the timer enabled can lead to + * unpredictable results. + */ + + ESP32C3_TIM_STOP(freerun->tch); + + /* Configure clock source */ + + ESP32C3_TIM_CLK_SRC(freerun->tch, ESP32C3_TIM_APB_CLK); + + /* Calculate the suitable prescaler for a period + * for the requested resolution. + */ + + pre = esp32c3_clk_apb_freq() * resolution / USEC_PER_SEC; + + tmrinfo("pre=% "PRIu16 " clk=%d \n", pre, esp32c3_clk_apb_freq()); + + /* Configure TIMER prescaler */ + + ESP32C3_TIM_SETPRE(freerun->tch, pre); + + /* Configure TIMER mode */ + + ESP32C3_TIM_SETMODE(freerun->tch, ESP32C3_TIM_MODE_UP); + + /* Clear TIMER counter value */ + + ESP32C3_TIM_CLEAR(freerun->tch); + + /* Set the maximum timeout */ + + ESP32C3_TIM_SETALRVL(freerun->tch, freerun->max_timeout); + +#ifndef CONFIG_CLOCK_TIMEKEEPING + + /* Set the interrupt */ + + freerun->overflow = 0; + + /* Enable autoreload */ + + ESP32C3_TIM_SETARLD(freerun->tch, true); + + /* Enable TIMER alarm */ + + ESP32C3_TIM_SETALRM(freerun->tch, true); + + /* Clear Interrupt Bits Status */ + + ESP32C3_TIM_ACKINT(freerun->tch); + + /* Register the handler */ + + { + irqstate_t flags = enter_critical_section(); + ret = ESP32C3_TIM_SETISR(freerun->tch, esp32c3_freerun_handler, + freerun); + leave_critical_section(flags); + } + + if (ret == OK) + { + ESP32C3_TIM_ENABLEINT(freerun->tch); + } + +#endif + /* Finally, start the TIMER */ + + ESP32C3_TIM_START(freerun->tch); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_freerun_counter + * + * Description: + * Read the counter register of the free-running timer. + * + * Input Parameters: + * freerun - Caller allocated instance of the freerun state + * structure. This structure must have been previously + * initialized via a call to + * esp32c3_freerun_initialize(); + * ts - The location in which to return the time from the + * free-running timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_CLOCK_TIMEKEEPING + +int esp32c3_freerun_counter(struct esp32c3_freerun_s *freerun, + struct timespec *ts) +{ + uint64_t usec; + uint64_t counter; + uint64_t verify; + uint32_t overflow; + uint32_t sec; + int pending; + irqstate_t flags; + + DEBUGASSERT(freerun != NULL); + DEBUGASSERT(ts != NULL); + DEBUGASSERT(freerun->tch != NULL); + + /* Temporarily disable the overflow counter. */ + + flags = enter_critical_section(); + + overflow = freerun->overflow; + ESP32C3_TIM_GETCTR(freerun->tch, &counter); + pending = ESP32C3_TIM_CHECKINT(freerun->tch); + ESP32C3_TIM_GETCTR(freerun->tch, &verify); + + /* If an interrupt was pending before we re-enabled interrupts, + * then the overflow needs to be incremented. + */ + + if (pending) + { + ESP32C3_TIM_ACKINT(freerun->tch); + + /* Increment the overflow count and use the value of the + * guaranteed to be AFTER the overflow occurred. + */ + + overflow++; + counter = verify; + + /* Update freerun overflow counter. */ + + freerun->overflow = overflow; + } + + leave_critical_section(flags); + + tmrinfo("counter=%" PRIu64 " (%" PRIu64 ") overflow=%" PRIu32 + ", pending=%i\n", + counter, verify, overflow, pending); + + usec = (uint64_t)(((overflow * freerun->max_timeout) + counter) + * freerun->resolution); + + /* And return the value of the timer */ + + sec = (uint32_t)(usec / USEC_PER_SEC); + ts->tv_sec = sec; + ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + tmrinfo(" usec=%" PRIu64 " ts=(%lu, %lu)\n", + usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + + return OK; +} + +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Name: esp32c3_freerun_uninitialize + * + * Description: + * Stop the free-running timer and release all resources that it uses. + * + * Input Parameters: + * freerun - Caller allocated instance of the freerun state + * structure. This structure must have been previously + * initialized via a call to + * esp32c3_freerun_initialize(); + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int esp32c3_freerun_uninitialize(struct esp32c3_freerun_s *freerun) +{ + int ret; + DEBUGASSERT(freerun != NULL); + DEBUGASSERT(freerun->tch != NULL); + + /* Stop timer */ + + ESP32C3_TIM_STOP(freerun->tch); + + /* Disable timer interrupt */ + + ESP32C3_TIM_DISABLEINT(freerun->tch); + + /* Detach handler */ + + ret = ESP32C3_TIM_SETISR(freerun->tch, NULL, NULL); + + /* Free the timer */ + + esp32c3_tim_deinit(freerun->tch); + freerun->tch = NULL; + + return ret; +} + +#endif /* CONFIG_ESP32C3_FREERUN */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_freerun.h b/arch/risc-v/src/esp32c3/esp32c3_freerun.h new file mode 100644 index 00000000000..d80da590489 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_freerun.h @@ -0,0 +1,145 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_freerun.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_FREERUN_H +#define __ARCH_RISCV_SRC_ESP32C3_FREERUN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp32c3_tim.h" + +#ifdef CONFIG_ESP32C3_FREERUN + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The freerun client must allocate an instance of this structure and called + * esp32c3_freerun_initialize() before using the freerun facilities. The + * client should not access the contents of this structure directly since + * the contents are subject to change. + */ + +struct esp32c3_freerun_s +{ + uint8_t chan; /* The timer/counter in use */ + uint32_t overflow; /* Timer counter overflow */ + uint16_t resolution; /* Timer resolution */ + uint64_t max_timeout; /* Maximum timeout to overflow */ + FAR struct esp32c3_tim_dev_s *tch; /* Handle returned by esp32c3_tim_init() */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_freerun_initialize + * + * Description: + * Initialize the freerun timer wrapper. + * + * Input Parameters: + * freerun - Caller allocated instance of the freerun + * state structure + * chan - Timer counter channel to be used. + * resolution - The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to + * the range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int esp32c3_freerun_initialize(struct esp32c3_freerun_s *freerun, int chan, + uint16_t resolution); + +/**************************************************************************** + * Name: esp32c3_freerun_counter + * + * Description: + * Read the counter register of the free-running timer. + * + * Input Parameters: + * freerun - Caller allocated instance of the freerun state + * structure. This structure must have been previously + * initialized via a call to + * esp32c3_freerun_initialize(); + * ts - The location in which to return the time from the + * free-running timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int esp32c3_freerun_counter(struct esp32c3_freerun_s *freerun, + struct timespec *ts); + +/**************************************************************************** + * Name: esp32c3_freerun_uninitialize + * + * Description: + * Stop the free-running timer and release all resources that it uses. + * + * Input Parameters: + * freerun - Caller allocated instance of the freerun state + * structure. This structure must have been previously + * initialized via a call to + * esp32c3_freerun_initialize(); + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int esp32c3_freerun_uninitialize(struct esp32c3_freerun_s *freerun); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_ESP32C3_FREERUN */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_FREERUN_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_i2c.c b/arch/risc-v/src/esp32c3/esp32c3_i2c.c index 639e58e9f98..8807703315c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_i2c.c +++ b/arch/risc-v/src/esp32c3/esp32c3_i2c.c @@ -31,9 +31,11 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -77,6 +79,12 @@ ((_ack_val) << 10) + \ (_bytes)) +/* Helper */ + +#ifdef CONFIG_I2C_POLLED +#define TIMESPEC_TO_US(sec, nano) ((sec * USEC_PER_SEC) + (nano / NSEC_PER_USEC)) +#endif + /* I2C hardware FIFO depth */ #define I2C_FIFO_SIZE (32) @@ -128,7 +136,9 @@ enum esp32c3_i2cstate_e I2CSTATE_IDLE = 0, I2CSTATE_PROC, I2CSTATE_STOP, +#ifndef CONFIG_I2C_POLLED I2CSTATE_FINISH, +#endif I2CSTATE_ERROR }; @@ -180,8 +190,10 @@ struct esp32c3_i2c_config_s uint8_t scl_pin; /* GPIO configuration for SCL as SCL */ uint8_t sda_pin; /* GPIO configuration for SDA as SDA */ +#ifndef CONFIG_I2C_POLLED uint8_t periph; /* Peripheral ID */ uint8_t irq; /* Interrupt ID */ +#endif uint32_t clk_bit; /* Clock enable bit */ uint32_t rst_bit; /* I2C reset bit */ @@ -206,7 +218,10 @@ struct esp32c3_i2c_priv_s const struct esp32c3_i2c_config_s *config; int refs; /* Reference count */ sem_t sem_excl; /* Mutual exclusion semaphore */ + +#ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ +#endif /* I2C work state (see enum esp32c3_i2cstate_e) */ @@ -217,7 +232,9 @@ struct esp32c3_i2c_priv_s uint8_t msgid; /* Current message ID */ ssize_t bytes; /* Processed data bytes */ +#ifndef CONFIG_I2C_POLLED int cpuint; /* CPU interrupt assigned to this I2C */ +#endif uint32_t error; /* I2C transform error */ @@ -248,6 +265,12 @@ static void esp32c3_i2c_deinit(struct esp32c3_i2c_priv_s *priv); static int esp32c3_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); +static inline void esp32c3_i2c_process(struct esp32c3_i2c_priv_s *priv, + uint32_t status); +#ifdef CONFIG_I2C_POLLED +static int esp32c3_i2c_polling_waitdone(FAR struct esp32c3_i2c_priv_s *priv); +#endif + #ifdef CONFIG_I2C_RESET static int esp32c3_i2c_reset(struct i2c_master_s *dev); #endif /* CONFIG_I2C_RESET */ @@ -286,8 +309,10 @@ static const struct esp32c3_i2c_config_s esp32c3_i2c0_config = .clk_freq = I2C_CLK_FREQ_DEF, .scl_pin = CONFIG_ESP32C3_I2C0_SCLPIN, .sda_pin = CONFIG_ESP32C3_I2C0_SDAPIN, +#ifndef CONFIG_I2C_POLLED .periph = ESP32C3_PERIPH_I2C_EXT0, .irq = ESP32C3_IRQ_I2C_EXT0, +#endif .clk_bit = SYSTEM_I2C_EXT0_CLK_EN, .rst_bit = SYSTEM_I2C_EXT0_RST, .scl_insig = I2CEXT0_SCL_IN_IDX, @@ -306,7 +331,9 @@ static struct esp32c3_i2c_priv_s esp32c3_i2c0_priv = .msgv = NULL, .msgid = 0, .bytes = 0, +#ifndef CONFIG_I2C_POLLED .cpuint = -ENOMEM, +#endif .error = 0, .ready_read = false, .clk_freq = 0 @@ -473,7 +500,7 @@ static void esp32c3_i2c_senddata(struct esp32c3_i2c_priv_s *priv) * Name: esp32c3_i2c_recvdata * * Description: - * Receive I2C data. + * Transfer data from the FIFO to the driver buffer. * * Parameters: * priv - Pointer to the internal driver state structure. @@ -745,9 +772,9 @@ static void esp32c3_i2c_deinit(struct esp32c3_i2c_priv_s *priv) static void esp32c3_i2c_reset_fsmc(struct esp32c3_i2c_priv_s *priv) { - esp32c3_i2c_deinit(priv); + /* Reset FSM machine */ - esp32c3_i2c_init(priv); + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_FSM_RST_M); } /**************************************************************************** @@ -764,7 +791,7 @@ static void esp32c3_i2c_reset_fsmc(struct esp32c3_i2c_priv_s *priv) * failure. * ****************************************************************************/ - +#ifndef CONFIG_I2C_POLLED static int esp32c3_i2c_sem_waitdone(struct esp32c3_i2c_priv_s *priv) { int ret; @@ -779,6 +806,120 @@ static int esp32c3_i2c_sem_waitdone(struct esp32c3_i2c_priv_s *priv) return ret; } +#endif + +/**************************************************************************** + * Name: esp32c3_i2c_polling_waitdone + * + * Description: + * Wait for a transfer to complete by polling status interrupt registers, + * which indicates the status of the I2C operations. This function is only + * used in polling driven mode. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + * Returned Values: + * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * in case a transfer didn't finish within the timeout interval. And ERROR + * is returned in case of any I2C error during the transfer has happened. + * + ****************************************************************************/ +#ifdef CONFIG_I2C_POLLED +static int esp32c3_i2c_polling_waitdone(FAR struct esp32c3_i2c_priv_s *priv) +{ + int ret; + struct timespec current_time; + struct timespec timeout; + uint64_t current_us; + uint64_t timeout_us; + uint32_t status = 0; + + /* Get the current absolute time and add an offset as timeout. + * Preferable to use monotonic, so in case the time changes, + * the time reference is kept, i.e., current time can't jump + * forward and backwards. + */ + + #ifdef CONFIG_CLOCK_MONOTONIC + clock_gettime(CLOCK_MONOTONIC, ¤t_time); + #else + clock_gettime(CLOCK_REALTIME, ¤t_time); + #endif + + timeout.tv_sec = current_time.tv_sec + 10; + timeout.tv_nsec = current_time.tv_nsec + 0; + + current_us = TIMESPEC_TO_US(current_time.tv_sec, current_time.tv_nsec); + timeout_us = TIMESPEC_TO_US(timeout.tv_sec, timeout.tv_nsec); + + /* Loop while a transfer is in progress + * and an error didn't occur within the timeout + */ + + while ((current_us < timeout_us) && (priv->error == 0)) + { + /* Check if any interrupt triggered, clear them + * process the operation. + */ + + status = getreg32(I2C_INT_STATUS_REG(priv->id)); + if (status != 0) + { + /* Check if the stop operation ended. Don't use + * I2CSTATE_FINISH, because it is set before the stop + * signal really ends. This works for interrupts because + * the i2c_state is checked in the next interrupt when + * stop signal has concluded. This is not the case of + * polling. + */ + + if (status & I2C_TRANS_COMPLETE_INT_ST_M) + { + putreg32(status, I2C_INT_CLR_REG(priv->id)); + break; + } + + putreg32(status, I2C_INT_CLR_REG(priv->id)); + esp32c3_i2c_process(priv, status); + } + + /* Update current time */ + + #ifdef CONFIG_CLOCK_MONOTONIC + clock_gettime(CLOCK_MONOTONIC, ¤t_time); + #else + clock_gettime(CLOCK_REALTIME, ¤t_time); + #endif + current_us = TIMESPEC_TO_US(current_time.tv_sec, current_time.tv_nsec); + } + + /* Return a negated value in case of timeout, and in the other scenarios + * return a positive value. + * The transfer function will check the status of priv to check the other + * scenarios. + */ + + if (current_us >= timeout_us) + { + ret = -ETIMEDOUT; + } + else if (priv->error) + { + ret = ERROR; + } + else + { + ret = OK; + } + + /* Disable all interrupts */ + + esp32c3_i2c_intr_disable(priv); + + return ret; +} +#endif /**************************************************************************** * Name: esp32c3_i2c_sem_wait @@ -830,7 +971,9 @@ static void esp32c3_i2c_sem_post(struct esp32c3_i2c_priv_s *priv) static void esp32c3_i2c_sem_destroy(struct esp32c3_i2c_priv_s *priv) { nxsem_destroy(&priv->sem_excl); +#ifndef CONFIG_I2C_POLLED nxsem_destroy(&priv->sem_isr); +#endif } /**************************************************************************** @@ -851,9 +994,10 @@ static inline void esp32c3_i2c_sem_init(struct esp32c3_i2c_priv_s *priv) /* This semaphore is used for signaling and, hence, should not have * priority inheritance enabled. */ - +#ifndef CONFIG_I2C_POLLED nxsem_init(&priv->sem_isr, 0, 0); nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE); +#endif } /**************************************************************************** @@ -925,9 +1069,10 @@ static int esp32c3_i2c_transfer(struct i2c_master_s *dev, esp32c3_i2c_sendstart(priv); +#ifndef CONFIG_I2C_POLLED if (esp32c3_i2c_sem_waitdone(priv) < 0) { - i2cinfo("Message %" PRIu8 " timed out.\n", priv->msgid); + i2cerr("Message %" PRIu8 " timed out.\n", priv->msgid); ret = -ETIMEDOUT; break; } @@ -935,7 +1080,7 @@ static int esp32c3_i2c_transfer(struct i2c_master_s *dev, { if (priv->error != 0) { - i2cinfo("Transfer error %" PRIu32 "\n", priv->error); + i2cerr("Transfer error %" PRIu32 "\n", priv->error); ret = -EIO; break; } @@ -945,6 +1090,28 @@ static int esp32c3_i2c_transfer(struct i2c_master_s *dev, ret = OK; } } +#else + ret = esp32c3_i2c_polling_waitdone(priv); + if (ret < 0) + { + if (ret == -ETIMEDOUT) + { + break; + } + else + { + ret = -EIO; + break; + } + } + else + { + /* Successful transfer, update the I2C state to idle */ + + priv->i2cstate = I2CSTATE_IDLE; + ret = OK; + } +#endif i2cinfo("Message %" PRIu8 " transfer complete.\n", priv->msgid); } @@ -973,83 +1140,12 @@ static int esp32c3_i2c_transfer(struct i2c_master_s *dev, #ifdef CONFIG_I2C_RESET static void esp32c3_i2c_clear_bus(struct esp32c3_i2c_priv_s *priv) { - uint32_t clock_count; - uint32_t stretch_count; - int ret; + uint32_t value = VALUE_TO_FIELD(I2C_SCL_CYC_NUM_DEF, I2C_SCL_RST_SLV_NUM); + modifyreg32(I2C_SCL_SP_CONF_REG(priv->id), I2C_SCL_RST_SLV_NUM_M, value); - const struct esp32c3_i2c_config_s *config = priv->config; + modifyreg32(I2C_SCL_SP_CONF_REG(priv->id), 0, I2C_SCL_RST_SLV_EN_M); - /* Use GPIO configuration to un-wedge the bus */ - - esp32c3_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); - esp32c3_gpio_matrix_out(config->scl_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32c3_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); - esp32c3_gpio_matrix_out(config->sda_pin, SIG_GPIO_OUT_IDX, 0, 0); - - /* Let SDA go high */ - - esp32c3_gpiowrite(config->sda_pin, 1); - - /* Clock the bus until any slaves currently driving it let it go. */ - - clock_count = 0; - while (!esp32c3_gpioread(config->sda_pin)) - { - /* Give up if we have tried too hard */ - - if (clock_count++ >= I2C_SCL_CYC_NUM_DEF) - { - ret = -EIO; - goto out; - } - - /* Sniff to make sure that clock stretching has finished. - * - * If the bus never relaxes, the reset has failed. - */ - - stretch_count = 0; - while (!esp32c3_gpioread(config->scl_pin)) - { - /* Give up if we have tried too hard */ - - if (stretch_count++ > 10) - { - ret = -EIO; - goto out; - } - - up_udelay(10); - } - - /* Drive SCL low */ - - esp32c3_gpiowrite(config->scl_pin, 0); - up_udelay(10); - - /* Drive SCL high again */ - - esp32c3_gpiowrite(config->scl_pin, 1); - up_udelay(10); - } - - /* Generate a start followed by a stop to reset slave - * state machines. - */ - - esp32c3_gpiowrite(config->sda_pin, 0); - up_udelay(10); - esp32c3_gpiowrite(config->scl_pin, 0); - up_udelay(10); - esp32c3_gpiowrite(config->scl_pin, 1); - up_udelay(10); - esp32c3_gpiowrite(config->sda_pin, 1); - up_udelay(10); - - ret = OK; - -out: - return ret; + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_CONF_UPGATE_M); } #endif @@ -1080,12 +1176,12 @@ static int esp32c3_i2c_reset(struct i2c_master_s *dev) flags = enter_critical_section(); - esp32c3_i2c_deinit(priv); + esp32c3_i2c_reset_fsmc(priv); + + /* Clear bus */ esp32c3_i2c_clear_bus(priv); - esp32c3_i2c_init(priv); - priv->i2cstate = I2CSTATE_IDLE; priv->msgid = 0; priv->bytes = 0; @@ -1293,14 +1389,40 @@ static void esp32c3_i2c_tracedump(struct esp32c3_i2c_priv_s *priv) * failure. * ****************************************************************************/ - +#ifndef CONFIG_I2C_POLLED static int esp32c3_i2c_irq(int cpuint, void *context, void *arg) { struct esp32c3_i2c_priv_s *priv = (struct esp32c3_i2c_priv_s *)arg; + uint32_t irq_status = getreg32(I2C_INT_STATUS_REG(priv->id)); + + putreg32(irq_status, I2C_INT_CLR_REG(priv->id)); + esp32c3_i2c_process(priv , irq_status); + return OK; +} +#endif + +/**************************************************************************** + * Name: esp32c3_i2c_process + * + * Description: + * This routine manages the transfer. It's called after some specific + * commands from the I2C controller are executed or in case of errors. + * It's responsible for writing/reading operations and transferring data + * from/to FIFO. + * It's called in the interrupt and polled driven mode. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * status - The current interrupt status register. + * + ****************************************************************************/ + +static inline void esp32c3_i2c_process(struct esp32c3_i2c_priv_s *priv, + uint32_t irq_status) +{ struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; - uint32_t irq_status = getreg32(I2C_INT_STATUS_REG(priv->id)); - putreg32(irq_status, I2C_INT_CLR_REG(priv->id)); + /* Check for any errors */ if (I2C_INT_ERR_MASK & irq_status) { @@ -1309,7 +1431,9 @@ static int esp32c3_i2c_irq(int cpuint, void *context, void *arg) esp32c3_i2c_traceevent(priv, I2CEVENT_ERROR, priv->error, getreg32(I2C_SR_REG(priv->id))); esp32c3_i2c_intr_disable(priv); +#ifndef CONFIG_I2C_POLLED nxsem_post(&priv->sem_isr); +#endif } else { @@ -1331,8 +1455,9 @@ static int esp32c3_i2c_irq(int cpuint, void *context, void *arg) esp32c3_i2c_traceevent(priv, I2CEVENT_STOP, msg->length, getreg32(I2C_SR_REG(priv->id))); esp32c3_i2c_sendstop(priv); - +#ifndef CONFIG_I2C_POLLED priv->i2cstate = I2CSTATE_FINISH; +#endif } else { @@ -1361,15 +1486,18 @@ static int esp32c3_i2c_irq(int cpuint, void *context, void *arg) getreg32(I2C_SR_REG(priv->id))); esp32c3_i2c_sendstop(priv); +#ifndef CONFIG_I2C_POLLED priv->i2cstate = I2CSTATE_FINISH; +#endif } +#ifndef CONFIG_I2C_POLLED else if (priv->i2cstate == I2CSTATE_FINISH) { + esp32c3_i2c_intr_disable(priv); nxsem_post(&priv->sem_isr); } +#endif } - - return 0; } /**************************************************************************** @@ -1396,10 +1524,12 @@ static int esp32c3_i2c_irq(int cpuint, void *context, void *arg) struct i2c_master_s *esp32c3_i2cbus_initialize(int port) { - int ret; irqstate_t flags; struct esp32c3_i2c_priv_s *priv; +#ifndef CONFIG_I2C_POLLED const struct esp32c3_i2c_config_s *config; + int ret; +#endif switch (port) { @@ -1412,8 +1542,6 @@ struct i2c_master_s *esp32c3_i2cbus_initialize(int port) return NULL; } - config = priv->config; - flags = enter_critical_section(); if ((volatile int)priv->refs++ != 0) @@ -1426,6 +1554,8 @@ struct i2c_master_s *esp32c3_i2cbus_initialize(int port) return (struct i2c_master_s *)priv; } +#ifndef CONFIG_I2C_POLLED + config = priv->config; if (priv->cpuint != -ENOMEM) { /* Disable the provided CPU Interrupt to configure it. */ @@ -1460,6 +1590,7 @@ struct i2c_master_s *esp32c3_i2cbus_initialize(int port) /* Enable the CPU interrupt that is linked to the I2C device. */ up_enable_irq(priv->cpuint); +#endif esp32c3_i2c_sem_init(priv); @@ -1510,9 +1641,11 @@ int esp32c3_i2cbus_uninitialize(struct i2c_master_s *dev) leave_critical_section(flags); +#ifndef CONFIG_I2C_POLLED up_disable_irq(priv->cpuint); esp32c3_free_cpuint(priv->config->periph); priv->cpuint = -ENOMEM; +#endif esp32c3_i2c_deinit(priv); diff --git a/arch/risc-v/src/esp32c3/esp32c3_idle.c b/arch/risc-v/src/esp32c3/esp32c3_idle.c index fb894e7c569..ea7923e5a7b 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_idle.c +++ b/arch/risc-v/src/esp32c3/esp32c3_idle.c @@ -22,25 +22,216 @@ * Included Files ****************************************************************************/ +#include +#include +#include #include #include #include #include #include "esp32c3.h" +#include "esp32c3_pm.h" + +#ifdef CONFIG_ESP32C3_RT_TIMER +#include "esp32c3_rt_timer.h" +#endif + +#ifdef CONFIG_SCHED_TICKLESS +#include "esp32c3_tickless.h" +#endif /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode + * (which corresponds to ESP32-C3 stop mode). If this alarm expires, + * the logic in this file will wakeup from PM_STANDBY mode and + * transition to PM_SLEEP mode (ESP32-C3 standby mode). + */ + +#ifdef CONFIG_PM +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 15 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +#ifndef CONFIG_PM_SLEEP_WAKEUP_SEC +# define CONFIG_PM_SLEEP_WAKEUP_SEC 20 +#endif + +#ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC +# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0 +#endif + +#define PM_IDLE_DOMAIN 0 /* Revisit */ + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#define EXPECTED_IDLE_TIME_US (800) +#define EARLY_WAKEUP_US (200) + +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Public Functions + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * ****************************************************************************/ +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + irqstate_t flags; + +#ifdef CONFIG_ESP32C3_AUTO_SLEEP + flags = spin_lock_irqsave(NULL); + if (esp32c3_pm_lockstatus() == 0 && + (esp32c3_should_skip_light_sleep() == false)) + { + uint64_t os_start_us; + uint64_t os_end_us; + uint64_t os_step_us; + uint64_t hw_start_us; + uint64_t hw_end_us; + uint64_t hw_step_us; + uint64_t rtc_diff_us; + struct timespec ts; + uint64_t os_idle_us = up_get_idletime(); + uint64_t hw_idle_us = rt_timer_get_alarm(); + uint64_t sleep_us = MIN(os_idle_us, hw_idle_us); + if (sleep_us > EXPECTED_IDLE_TIME_US) + { + esp32c3_sleep_enable_rtc_timer_wakeup(sleep_us - EARLY_WAKEUP_US); + up_timer_gettime(&ts); + os_start_us = (ts.tv_sec * USEC_PER_SEC + + ts.tv_nsec / NSEC_PER_USEC); + hw_start_us = rt_timer_time_us(); + + esp32c3_light_sleep_start(&rtc_diff_us); + + hw_end_us = rt_timer_time_us(); + up_timer_gettime(&ts); + os_end_us = (ts.tv_sec * USEC_PER_SEC + + ts.tv_nsec / NSEC_PER_USEC); + hw_step_us = rtc_diff_us - (hw_end_us - hw_start_us); + os_step_us = rtc_diff_us - (os_end_us - os_start_us); + DEBUGASSERT(hw_step_us > 0); + DEBUGASSERT(os_step_us > 0); + + /* Adjust current RT timer by a certain value. */ + + rt_timer_calibration(hw_step_us); + + /* Adjust system time by a certain value. */ + + up_step_idletime((uint32_t)os_step_us); + } + } + + spin_unlock_irqrestore(NULL, flags); +#else /* CONFIG_ESP32C3_AUTO_SLEEP */ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = spin_lock_irqsave(NULL); + + /* Perform board-specific, state-dependent logic here */ + + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + spin_unlock_irqrestore(NULL, flags); + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + { + /* Enter Force-sleep mode */ + + esp32c3_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 + + CONFIG_PM_ALARM_NSEC / 1000); + } + break; + + case PM_SLEEP: + { + /* Enter Deep-sleep mode */ + + esp32c3_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 + + CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000); + } + break; + + default: + break; + } + } + else + { + if (oldstate == PM_NORMAL) + { + /* Relax normal operation */ + + pm_relax(PM_IDLE_DOMAIN, PM_NORMAL); + } + +#ifdef CONFIG_WATCHDOG + /* Announce the power management state change to feed watchdog */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); +#endif + } +#endif +} +#else +# define up_idlepm() +#endif + /**************************************************************************** * Name: up_idle * @@ -69,5 +260,9 @@ void up_idle(void) asm("WFI"); + /* Perform IDLE mode power management */ + + up_idlepm(); + #endif } diff --git a/arch/risc-v/src/esp32c3/esp32c3_interrupt.S b/arch/risc-v/src/esp32c3/esp32c3_interrupt.S index 3b73c2c1a28..d0cf1ba2bec 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_interrupt.S +++ b/arch/risc-v/src/esp32c3/esp32c3_interrupt.S @@ -115,7 +115,7 @@ _interrupt_handler: csrr a0, mcause /* Handler arg0: Exception cause */ mv a1, sp /* Handler arg1: Context (saved registers on stack) */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 lui sp, %hi(g_intstacktop) addi sp, sp, %lo(g_intstacktop) #endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c index 42522995221..23e57c7062c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_irq.c +++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c @@ -24,6 +24,7 @@ #include +#include #include #include @@ -54,18 +55,6 @@ #define CPUINT_UNASSIGNED 0xff -/* Wi-Fi reserved CPU interrupt bit */ - -#ifdef CONFIG_ESP32C3_WIRELESS -# define CPUINT_WMAC_MAP (1 << ESP32C3_CPUINT_WMAC) -#else -# define CPUINT_WMAC_MAP 0 -#endif - -/* Reserved CPU interrupt bits */ - -#define CPUINT_RESERVED_MAPS (CPUINT_WMAC_MAP) - /**************************************************************************** * Public Data ****************************************************************************/ @@ -76,7 +65,7 @@ volatile uint32_t *g_current_regs; * Private Data ****************************************************************************/ -uint8_t g_cpuint_map[ESP32C3_CPUINT_MAX]; +static uint8_t g_cpuint_map[ESP32C3_CPUINT_MAX]; /**************************************************************************** * Public Functions @@ -96,13 +85,22 @@ void up_irqinitialize(void) /** * Initialize specific driver's CPU interrupt ID: - * Object | CPU INT | Pheripheral + * Object | CPU INT | Peripheral * | | * Wi-Fi | 1 | 1 + * BT BB | 5 | 5 + * RW BLE | 8 | 8 */ #ifdef CONFIG_ESP32C3_WIRELESS +# ifdef CONFIG_ESP32C3_WIFI g_cpuint_map[ESP32C3_CPUINT_WMAC] = ESP32C3_PERIPH_WIFI_MAC_NMI; +# endif + +# ifdef CONFIG_ESP32C3_BLE + g_cpuint_map[ESP32C3_CPUINT_BT_BB] = ESP32C3_PERIPH_BT_BB; + g_cpuint_map[ESP32C3_CPUINT_RWBLE] = ESP32C3_PERIPH_RWBLE_IRQ; +# endif #endif /* Clear all peripheral interrupts from "bootloader" */ @@ -163,6 +161,8 @@ void up_enable_irq(int cpuint) { irqstate_t irqstate; + irqinfo("cpuint=%d\n", cpuint); + DEBUGASSERT(cpuint >= ESP32C3_CPUINT_MIN && cpuint <= ESP32C3_CPUINT_MAX); irqstate = enter_critical_section(); @@ -182,6 +182,8 @@ void up_disable_irq(int cpuint) { irqstate_t irqstate; + irqinfo("cpuint=%d\n", cpuint); + DEBUGASSERT(cpuint >= ESP32C3_CPUINT_MIN && cpuint <= ESP32C3_CPUINT_MAX); irqstate = enter_critical_section(); @@ -252,8 +254,7 @@ void esp32c3_bind_irq(uint8_t cpuint, uint8_t periphid, uint8_t prio, int esp32c3_request_irq(uint8_t periphid, uint8_t prio, uint32_t flags) { int ret; - uint32_t regval; - int cpuint; + uint8_t cpuint; irqstate_t irqstate; DEBUGASSERT(periphid < ESP32C3_NPERIPHERALS); @@ -262,33 +263,27 @@ int esp32c3_request_irq(uint8_t periphid, uint8_t prio, uint32_t flags) irqstate = enter_critical_section(); - /* Skip over enabled interrupts. NOTE: bit 0 is reserved. */ - - regval = getreg32(INTERRUPT_CPU_INT_ENABLE_REG); - - /* Skip over reserved CPU interrupts */ - - regval |= CPUINT_RESERVED_MAPS; + /* Skip over already registered interrupts. + * NOTE: bit 0 is reserved for exceptions. + */ for (cpuint = 1; cpuint <= ESP32C3_CPUINT_MAX; cpuint++) { - if (!(regval & (1 << cpuint))) + if (g_cpuint_map[cpuint] == CPUINT_UNASSIGNED) { break; } } - irqinfo("INFO: cpuint=%d\n", cpuint); + irqinfo("periphid:%" PRIu8 " cpuint=%" PRIu8 "\n", periphid, cpuint); if (cpuint <= ESP32C3_CPUINT_MAX) { - DEBUGASSERT(g_cpuint_map[cpuint] == CPUINT_UNASSIGNED); - - /* We have a free CPU interrupt. We can continue with mapping the + /* We have a free CPU interrupt. We can continue with mapping the * peripheral. */ - /* Save the CPU interrupt ID. We will return this value. */ + /* Save the CPU interrupt ID. We will return this value. */ ret = cpuint; @@ -329,7 +324,7 @@ int esp32c3_request_irq(uint8_t periphid, uint8_t prio, uint32_t flags) void esp32c3_free_cpuint(uint8_t periphid) { irqstate_t irqstate; - uint32_t cpuint; + uint8_t cpuint; DEBUGASSERT(periphid < ESP32C3_NPERIPHERALS); @@ -338,9 +333,10 @@ void esp32c3_free_cpuint(uint8_t periphid) /* Get the CPU interrupt ID mapped to this peripheral. */ cpuint = getreg32(DR_REG_INTERRUPT_BASE + periphid * 4) & 0x1f; - irqinfo("INFO: irq[%d]=%08lx\n", periphid, cpuint); - if (cpuint) + irqinfo("INFO: irq[%" PRIu8 "]=%" PRIu8 "\n", periphid, cpuint); + + if (cpuint != 0) { /* Undo the allocation process: * 1. Unmap the peripheral from the CPU interrupt ID. @@ -378,13 +374,12 @@ void esp32c3_free_cpuint(uint8_t periphid) IRAM_ATTR uint32_t *esp32c3_dispatch_irq(uint32_t mcause, uint32_t *regs) { - int cpuint; int irq; DEBUGASSERT(g_current_regs == NULL); g_current_regs = regs; - irqinfo("INFO: mcause=%08lx\n", mcause); + irqinfo("INFO: mcause=%08" PRIX32 "\n", mcause); /* If the board supports LEDs, turn on an LED now to indicate that we are * processing an interrupt. @@ -392,13 +387,13 @@ IRAM_ATTR uint32_t *esp32c3_dispatch_irq(uint32_t mcause, uint32_t *regs) board_autoled_on(LED_INIRQ); - if (MCAUSE_INTERRUPT & mcause) + if ((MCAUSE_INTERRUPT & mcause) != 0) { - cpuint = mcause & MCAUSE_INTERRUPT_MASK; + uint8_t cpuint = mcause & MCAUSE_INTERRUPT_MASK; DEBUGASSERT(cpuint <= ESP32C3_CPUINT_MAX); - irqinfo("INFO: cpuint=%d\n", cpuint); + irqinfo("INFO: cpuint=%" PRIu8 "\n", cpuint); /* Clear edge interrupts. */ @@ -430,3 +425,28 @@ IRAM_ATTR uint32_t *esp32c3_dispatch_irq(uint32_t mcause, uint32_t *regs) return regs; } + +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Return the current interrupt state and enable interrupts + * + ****************************************************************************/ + +irqstate_t up_irq_enable(void) +{ + uint32_t flags; + + /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ + + __asm__ __volatile__ + ( + "csrrs %0, mstatus, %1\n" + : "=r" (flags) + : "r"(MSTATUS_MIE) + : "memory" + ); + + return flags; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_ledc.c b/arch/risc-v/src/esp32c3/esp32c3_ledc.c new file mode 100644 index 00000000000..c769d26a163 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_ledc.c @@ -0,0 +1,776 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_ledc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include "esp32c3.h" +#include "esp32c3_clockconfig.h" +#include "esp32c3_gpio.h" +#include "esp32c3_ledc.h" + +#include "riscv_arch.h" +#include "hardware/esp32c3_ledc.h" +#include "hardware/esp32c3_system.h" +#include "hardware/esp32c3_gpio_sigmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDC total timers */ + +#define LEDC_TIMERS (3) + +/* LEDC total channels */ + +#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1 +# define LEDC_CHANNELS (6) +#else +# define LEDC_CHANNELS (3) +#endif + +/* LEDC timer0 channels and offset */ + +#ifdef CONFIG_ESP32C3_LEDC_TIM0 +# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1 +# define LEDC_TIM0_CHANS CONFIG_ESP32C3_LEDC_TIM0_CHANNELS +# else +# define LEDC_TIM0_CHANS (1) +# endif +# define LEDC_TIM0_CHANS_OFF (0) +#endif + +/* LEDC timer1 channels and offset */ + +#ifdef CONFIG_ESP32C3_LEDC_TIM1 +# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1 +# define LEDC_TIM1_CHANS CONFIG_ESP32C3_LEDC_TIM1_CHANNELS +# else +# define LEDC_TIM1_CHANS (1) +# endif +# define LEDC_TIM1_CHANS_OFF (LEDC_TIM0_CHANS_OFF + LEDC_TIM0_CHANS) +#endif + +/* LEDC timer2 channels and offset */ + +#ifdef CONFIG_ESP32C3_LEDC_TIM2 +# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1 +# define LEDC_TIM2_CHANS CONFIG_ESP32C3_LEDC_TIM2_CHANNELS +# else +# define LEDC_TIM2_CHANS (1) +# endif + +# define LEDC_TIM2_CHANS_OFF (LEDC_TIM1_CHANS_OFF + LEDC_TIM1_CHANS) +#endif + +/* LEDC clock resource */ + +#define LEDC_CLK_RES (1) /* APB clock */ + +/* LEDC timer max reload */ + +#define LEDC_RELOAD_MAX (16384) /* 2^14 */ + +/* LEDC timer max clock divider parameter */ + +#define LEDC_CLKDIV_MAX (1024) /* 2^10 */ + +/* LEDC timer registers mapping */ + +#define LEDC_TIMER_REG(r, n) ((r) + (n) * (LEDC_TIMER1_CONF_REG - \ + LEDC_TIMER2_CONF_REG)) + +/* LEDC timer channel registers mapping */ + +#define LEDC_CHAN_REG(r, n) ((r) + (n) * (LEDC_CH0_CONF0_REG - \ + LEDC_CH1_CONF0_REG)) + +#define SET_TIMER_BITS(t, r, b) setbits(b, LEDC_TIMER_REG(r, (t)->num)); +#define SET_TIMER_REG(t, r, v) putreg32(v, LEDC_TIMER_REG(r, (t)->num)); + +#define SET_CHAN_BITS(c, r, b) setbits(b, LEDC_CHAN_REG(r, (c)->num)); +#define SET_CHAN_REG(c, r, v) putreg32(v, LEDC_CHAN_REG(r, (c)->num)); + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* LEDC timer channel configuration */ + +struct esp32c3_ledc_chan_s +{ + const uint8_t num; /* Timer channel ID */ + const uint8_t pin; /* Timer channel GPIO pin number */ + + uint16_t duty; /* Timer channel current duty */ +}; + +/* This structure represents the state of one LEDC timer */ + +struct esp32c3_ledc_s +{ + const struct pwm_ops_s *ops; /* PWM operations */ + + const uint8_t num; /* Timer ID */ + + const uint8_t channels; /* Timer channels number */ + struct esp32c3_ledc_chan_s *chans; /* Timer channels pointer */ + + uint32_t frequency; /* Timer current frequency */ + uint32_t reload; /* Timer current reload */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int pwm_setup(struct pwm_lowerhalf_s *dev); +static int pwm_shutdown(struct pwm_lowerhalf_s *dev); +static int pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info); +static int pwm_stop(struct pwm_lowerhalf_s *dev); +static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LEDC PWM operations */ + +static const struct pwm_ops_s g_pwmops = +{ + .setup = pwm_setup, + .shutdown = pwm_shutdown, + .start = pwm_start, + .stop = pwm_stop, + .ioctl = pwm_ioctl +}; + +/* LEDC channels table */ + +static struct esp32c3_ledc_chan_s g_ledc_chans[LEDC_CHANNELS] = +{ + { + .num = 0, + .pin = CONFIG_ESP32C3_LEDC_CHANNEL0_PIN + }, + + { + .num = 1, + .pin = CONFIG_ESP32C3_LEDC_CHANNEL1_PIN + }, + + { + .num = 2, + .pin = CONFIG_ESP32C3_LEDC_CHANNEL2_PIN + }, + +#if LEDC_CHANNELS > 3 + { + .num = 3, + .pin = CONFIG_ESP32C3_LEDC_CHANNEL3_PIN + }, + + { + .num = 4, + .pin = CONFIG_ESP32C3_LEDC_CHANNEL4_PIN + }, + + { + .num = 5, + .pin = CONFIG_ESP32C3_LEDC_CHANNEL5_PIN + } +#endif +}; + +/* LEDC timer0 private data */ + +#ifdef CONFIG_ESP32C3_LEDC_TIM0 +static struct esp32c3_ledc_s g_pwm0dev = +{ + .ops = &g_pwmops, + .num = 0, + .channels = LEDC_TIM0_CHANS, + .chans = &g_ledc_chans[LEDC_TIM0_CHANS_OFF] +}; +#endif /* CONFIG_ESP32C3_LEDC_TIM0 */ + +/* LEDC timer1 private data */ + +#ifdef CONFIG_ESP32C3_LEDC_TIM1 +static struct esp32c3_ledc_s g_pwm1dev = +{ + .ops = &g_pwmops, + .num = 1, + .channels = LEDC_TIM1_CHANS, + .chans = &g_ledc_chans[LEDC_TIM1_CHANS_OFF] +}; +#endif /* CONFIG_ESP32C3_LEDC_TIM1 */ + +/* LEDC timer2 private data */ + +#ifdef CONFIG_ESP32C3_LEDC_TIM2 +static struct esp32c3_ledc_s g_pwm2dev = +{ + .ops = &g_pwmops, + .num = 2, + .channels = LEDC_TIM2_CHANS, + .chans = &g_ledc_chans[LEDC_TIM2_CHANS_OFF] +}; +#endif /* CONFIG_ESP32C3_LEDC_TIM2 */ + +/* Clock reference count */ + +static uint32_t g_clk_ref; + +/**************************************************************************** + * Private functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ledc_enable_clk + * + * Description: + * Enable LEDC clock. + * + * Input Parameters: + * NOne + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void ledc_enable_clk(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (!g_clk_ref) + { + setbits(SYSTEM_LEDC_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG); + resetbits(SYSTEM_LEDC_RST, SYSTEM_PERIP_RST_EN0_REG); + + putreg32(LEDC_CLK_RES, LEDC_CONF_REG); + + pwminfo("Enable ledc clock\n"); + } + + g_clk_ref++; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: ledc_disable_clk + * + * Description: + * Disable LEDC clock. + * + * Input Parameters: + * NOne + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void ledc_disable_clk(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + g_clk_ref--; + + if (!g_clk_ref) + { + pwminfo("Disable ledc clock\n"); + + setbits(SYSTEM_LEDC_RST, SYSTEM_PERIP_RST_EN0_REG); + resetbits(SYSTEM_LEDC_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: setup_timer + * + * Description: + * Setup LEDC timer frequency and reload. + * + * Input Parameters: + * priv - A reference to the LEDC timer state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void setup_timer(struct esp32c3_ledc_s *priv) +{ + irqstate_t flags; + uint32_t regval; + uint32_t reload; + uint32_t prescaler; + uint32_t shift = 1; + uint64_t pwmclk = esp32c3_clk_apb_freq(); + + /* Reset timer */ + + SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_RST); + + /* Calculate optimal values for the timer prescaler and for the timer + * modulo register. If' frequency' is the desired frequency, then + * + * tpmclk = pwmclk / presc + * frequency = tpmclk / reload + * + * ==> + * + * reload = pwmclk / presc / frequency + * + * In ESP32-C3, there are 4 clock resources for PWM: + * + * 1. APB clock (80 MHz) + * 2. RTC clock (8 MHz) + * 3. XTAL clock (depends on hardware, generally is 40 MHz) + * 4. REF clock (this is APB clock divided, generally is 1 MHz) + * + * We mostly use APB clock generally. + * + * There are many solutions to this, but the best solution will be the one + * that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 2 <= presc <= 2^14(16,384) + * 1 <= clkdiv <= 2^10 + * + * clkdiv has 8-bit decimal precision, so + * clkdiv = pwmclk * 256 / 16384 / frequency would be optimal. + * + * Example: + * + * pwmclk = 80 MHz + * frequency = 100 Hz + * + * presc = 80,000,000 * 256 / 16,384 / 100 + * = 12,500 + * timclk = 80,000,000 / (12,500 / 256) + * = 1,638,400 + * counter = 1,638,400 / 100 + * = 16,384 + * = 2^14 + * shift = 14 + */ + + reload = (pwmclk * 256 / priv->frequency + LEDC_CLKDIV_MAX) / + LEDC_CLKDIV_MAX; + if (reload == 0) + { + reload = 1; + } + else if (reload > LEDC_RELOAD_MAX) + { + reload = LEDC_RELOAD_MAX; + } + + for (int c = 2; c <= LEDC_RELOAD_MAX; c *= 2) + { + if (c * 2 > reload) + { + reload = c; + break; + } + + shift++; + } + + prescaler = pwmclk * 256 / reload / priv->frequency; + + pwminfo("PWM timer%" PRIu8 " frequency=%0.4f reload=%" PRIu32 " shift=%" \ + PRIu32 " prescaler=%0.4f\n", + priv->num, (float)pwmclk / reload / ((float)prescaler / 256), + reload, shift, (float)prescaler / 256); + + /* Store reload for channel duty */ + + priv->reload = reload; + + flags = enter_critical_section(); + + /* Set timer clock divide and reload */ + + regval = (shift << LEDC_TIMER0_DUTY_RES_S) | + (prescaler << LEDC_CLK_DIV_TIMER0_S); + SET_TIMER_REG(priv, LEDC_TIMER0_CONF_REG, regval); + + /* Update clock divide and reload to hardware */ + + SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_PARA_UP); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: setup_channel + * + * Description: + * Setup LEDC timer channel duty. + * + * Input Parameters: + * priv - A reference to the LEDC timer state structure + * cn - Timer channel number + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void setup_channel(struct esp32c3_ledc_s *priv, int cn) +{ + irqstate_t flags; + uint32_t regval; + struct esp32c3_ledc_chan_s *chan = &priv->chans[cn]; + + /* Duty cycle: + * + * duty cycle = duty / 65536 * reload (fractional value) + */ + + regval = b16toi(chan->duty * priv->reload + b16HALF); + + pwminfo("channel=%" PRIu8 " duty=%" PRIu16 "(%0.4f) regval=%" PRIu32 \ + " reload=%" PRIu32 "\n", + chan->num, chan->duty, (float)chan->duty / UINT16_MAX, + regval, priv->reload); + + flags = enter_critical_section(); + + /* Reset config 0 & 1 registers */ + + SET_CHAN_REG(chan, LEDC_CH0_CONF0_REG, 0); + SET_CHAN_REG(chan, LEDC_CH0_CONF1_REG, 0); + + /* Set pulse phase 0 */ + + SET_CHAN_REG(chan, LEDC_CH0_HPOINT_REG, 0); + + /* Duty register uses bits [18:4] */ + + SET_CHAN_REG(chan, LEDC_CH0_DUTY_REG, regval << 4); + + /* Start GPIO output */ + + SET_CHAN_BITS(chan, LEDC_CH0_CONF0_REG, LEDC_SIG_OUT_EN_CH0); + + /* Start Duty counter */ + + SET_CHAN_BITS(chan, LEDC_CH0_CONF1_REG, LEDC_DUTY_START_CH0); + + /* Update duty and phase to hardware */ + + SET_CHAN_BITS(chan, LEDC_CH0_CONF0_REG, LEDC_PARA_UP_CH0); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: pwm_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_setup(struct pwm_lowerhalf_s *dev) +{ + struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev; + + pwminfo("PWM timer%d\n", priv->num); + + ledc_enable_clk(); + + /* Setup channel GPIO pins */ + + for (int i = 0; i < priv->channels; i++) + { + pwminfo("channel%d --> pin%d\n", priv->chans[i].num, + priv->chans[i].pin); + + esp32c3_configgpio(priv->chans[i].pin, OUTPUT | PULLUP); + esp32c3_gpio_matrix_out(priv->chans[i].pin, + LEDC_LS_SIG_OUT0_IDX + priv->chans[i].num, + 0, 0); + } + + return 0; +} + +/**************************************************************************** + * Name: pwm_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_shutdown(struct pwm_lowerhalf_s *dev) +{ + struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev; +#ifdef CONFIG_PWM_NCHANNELS + int channels = MIN(priv->channels, CONFIG_PWM_NCHANNELS); +#else + int channels = 1; +#endif + + /* Stop timer */ + + pwm_stop(dev); + + /* Clear timer and channel configuration */ + + priv->frequency = 0; + priv->reload = 0; + for (int i = 0; i < channels; i++) + { + priv->chans[i].duty = 0; + } + + ledc_disable_clk(); + + return 0; +} + +/**************************************************************************** + * Name: pwm_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info) +{ + struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev; +#ifdef CONFIG_PWM_NCHANNELS + int channels = MIN(priv->channels, CONFIG_PWM_NCHANNELS); +#else + int channels = 1; +#endif + + pwminfo("PWM timer%d\n", priv->num); + + /* Update timer with given PWM timer frequency */ + + if (priv->frequency != info->frequency) + { + priv->frequency = info->frequency; + setup_timer(priv); + } + + /* Update timer with given PWM channel duty */ + + for (int i = 0; i < channels; i++) + { + if (priv->chans[i].duty != info[i].duty) + { + priv->chans[i].duty = info[i].duty; + setup_channel(priv, i); + } + } + + return 0; +} + +/**************************************************************************** + * Name: pwm_stop + * + * Description: + * Stop the pulsed output and reset the timer resources. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_stop(struct pwm_lowerhalf_s *dev) +{ + irqstate_t flags; + struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev; + + pwminfo("PWM timer%d\n", priv->num); + + flags = enter_critical_section(); + + /* Stop timer */ + + SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_PAUSE); + + /* Reset timer */ + + SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_RST); + + leave_critical_section(flags); + return 0; +} + +/**************************************************************************** + * Name: pwm_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ +#ifdef CONFIG_DEBUG_PWM_INFO + struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev; + + pwminfo("PWM timer%d\n", priv->num); +#endif + + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ledc_init + * + * Description: + * Initialize one LEDC timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. + * + * Returned Value: + * On success, a pointer to the ESP32-C3 LEDC lower half PWM driver is + * returned. NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *esp32c3_ledc_init(int timer) +{ + struct esp32c3_ledc_s *lower = NULL; + + pwminfo("TIM%u\n", timer); + + switch (timer) + { +#ifdef CONFIG_ESP32C3_LEDC_TIM0 + case 0: + { + lower = &g_pwm0dev; + break; + } +#endif + +#ifdef CONFIG_ESP32C3_LEDC_TIM1 + case 1: + { + lower = &g_pwm1dev; + break; + } +#endif + +#ifdef CONFIG_ESP32C3_LEDC_TIM2 + case 2: + { + lower = &g_pwm2dev; + break; + } +#endif + +#ifdef CONFIG_ESP32C3_LEDC_TIM3 + case 3: + { + lower = &g_pwm3dev; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such timer configured %d\n", timer); + lower = NULL; + break; + } + } + + return (struct pwm_lowerhalf_s *)lower; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_ledc.h b/arch/risc-v/src/esp32c3/esp32c3_ledc.h new file mode 100644 index 00000000000..73ece77f671 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_ledc.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_ledc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ledc_init + * + * Description: + * Initialize one LEDC timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. + * + * Returned Value: + * On success, a pointer to the ESP32-C3 LEDC lower half PWM driver is + * returned. NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *esp32c3_ledc_init(int timer); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_lowputc.c b/arch/risc-v/src/esp32c3/esp32c3_lowputc.c index 1aa4fdd02d4..952350699a3 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_lowputc.c +++ b/arch/risc-v/src/esp32c3/esp32c3_lowputc.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -74,6 +75,24 @@ struct esp32c3_uart_s g_uart0_config = .txsig = U0TXD_OUT_IDX, .rxpin = CONFIG_ESP32C3_UART0_RXPIN, .rxsig = U0RXD_IN_IDX, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rtspin = CONFIG_ESP32C3_UART0_RTSPIN, + .rtssig = U0RTS_OUT_IDX, +#ifdef CONFIG_UART0_IFLOWCONTROL + .iflow = true, /* input flow control (RTS) enabled */ +#else + .iflow = false, /* input flow control (RTS) disabled */ +#endif +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .ctspin = CONFIG_ESP32C3_UART0_CTSPIN, + .ctssig = U0CTS_IN_IDX, +#ifdef CONFIG_UART0_OFLOWCONTROL + .oflow = true, /* output flow control (CTS) enabled */ +#else + .oflow = false, /* output flow control (CTS) disabled */ +#endif +#endif }; #endif /* CONFIG_ESP32C3_UART0 */ @@ -95,6 +114,24 @@ struct esp32c3_uart_s g_uart1_config = .txsig = U1TXD_OUT_IDX, .rxpin = CONFIG_ESP32C3_UART1_RXPIN, .rxsig = U1RXD_IN_IDX, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rtspin = CONFIG_ESP32C3_UART1_RTSPIN, + .rtssig = U1RTS_OUT_IDX, +#ifdef CONFIG_UART1_IFLOWCONTROL + .iflow = true, /* input flow control (RTS) enabled */ +#else + .iflow = false, /* input flow control (RTS) disabled */ +#endif +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .ctspin = CONFIG_ESP32C3_UART1_CTSPIN, + .ctssig = U1CTS_IN_IDX, +#ifdef CONFIG_UART1_OFLOWCONTROL + .oflow = true, /* output flow control (CTS) enabled */ +#else + .oflow = false, /* output flow control (CTS) disabled */ +#endif +#endif }; #endif /* CONFIG_ESP32C3_UART1 */ @@ -104,6 +141,72 @@ struct esp32c3_uart_s g_uart1_config = * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp32c3_lowputc_set_iflow + * + * Description: + * Configure the input hardware flow control. + * + * Parameters: + * priv - Pointer to the private driver struct. + * threshold - RX FIFO value from which RST will automatically be + * asserted. + * enable - true = enable, false = disable + * + ****************************************************************************/ + +void esp32c3_lowputc_set_iflow(const struct esp32c3_uart_s *priv, + uint8_t threshold, bool enable) +{ + uint32_t mask; + if (enable) + { + /* Enable RX flow control */ + + modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN); + + /* Configure the threshold */ + + mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD); + modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask); + } + else + { + /* Disable RX flow control */ + + modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0); + } +} + +/**************************************************************************** + * Name: esp32c3_lowputc_set_oflow + * + * Description: + * Configure the output hardware flow control. + * + * Parameters: + * priv - Pointer to the private driver struct. + * enable - true = enable, false = disable + * + ****************************************************************************/ + +void esp32c3_lowputc_set_oflow(const struct esp32c3_uart_s *priv, + bool enable) +{ + if (enable) + { + /* Enable TX flow control */ + + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN); + } + else + { + /* Disable TX flow control */ + + modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0); + } +} + /**************************************************************************** * Name: esp32c3_lowputc_reset_core * @@ -642,6 +745,23 @@ void esp32c3_lowputc_config_pins(const struct esp32c3_uart_s *priv) esp32c3_configgpio(priv->rxpin, INPUT_FUNCTION_1); esp32c3_gpio_matrix_in(priv->rxpin, priv->rxsig, 0); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + esp32c3_configgpio(priv->rtspin, OUTPUT_FUNCTION_1); + esp32c3_gpio_matrix_out(priv->rtspin, priv->rtssig, + 0, 0); + } + +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->oflow) + { + esp32c3_configgpio(priv->ctspin, INPUT_FUNCTION_1); + esp32c3_gpio_matrix_in(priv->ctspin, priv->ctssig, 0); + } +#endif } /**************************************************************************** diff --git a/arch/risc-v/src/esp32c3/esp32c3_lowputc.h b/arch/risc-v/src/esp32c3/esp32c3_lowputc.h index d4295719062..e8455ca5727 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_lowputc.h +++ b/arch/risc-v/src/esp32c3/esp32c3_lowputc.h @@ -105,6 +105,16 @@ struct esp32c3_uart_s uint8_t txsig; /* TX signal */ uint8_t rxpin; /* RX pin */ uint8_t rxsig; /* RX signal */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + uint8_t rtspin; /* RTS pin number */ + uint8_t rtssig; /* RTS signal */ + bool iflow; /* Input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + uint8_t ctspin; /* CTS pin number */ + uint8_t ctssig; /* CTS signal */ + bool oflow; /* Output flow control (CTS) enabled */ +#endif }; extern struct esp32c3_uart_s g_uart0_config; @@ -114,6 +124,38 @@ extern struct esp32c3_uart_s g_uart1_config; * Public Function Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: esp32c3_lowputc_set_iflow + * + * Description: + * Configure the input hardware flow control. + * + * Parameters: + * priv - Pointer to the private driver struct. + * threshold - RX FIFO value from which RST will automatically be + * asserted. + * enable - true = enable, false = disable + * + ****************************************************************************/ + +void esp32c3_lowputc_set_iflow(const struct esp32c3_uart_s *priv, + uint8_t threshold, bool enable); + +/**************************************************************************** + * Name: esp32c3_lowputc_set_oflow + * + * Description: + * Configure the output hardware flow control. + * + * Parameters: + * priv - Pointer to the private driver struct. + * enable - true = enable, false = disable + * + ****************************************************************************/ + +void esp32c3_lowputc_set_oflow(const struct esp32c3_uart_s *priv, + bool enable); + /**************************************************************************** * Name: esp32c3_lowputc_reset_core * diff --git a/arch/risc-v/src/esp32c3/esp32c3_oneshot.c b/arch/risc-v/src/esp32c3/esp32c3_oneshot.c index adcf7956a89..c3235552ece 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_oneshot.c +++ b/arch/risc-v/src/esp32c3/esp32c3_oneshot.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/esp32c3/esp32c3_oneshot_lowerhalf.c b/arch/risc-v/src/esp32c3/esp32c3_oneshot_lowerhalf.c index fa8e3e5d0c0..496038e7d3d 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_oneshot_lowerhalf.c +++ b/arch/risc-v/src/esp32c3/esp32c3_oneshot_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/risc-v/src/esp32c3/esp32c3_pm.c b/arch/risc-v/src/esp32c3/esp32c3_pm.c new file mode 100644 index 00000000000..ebea7dc2490 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_pm.c @@ -0,0 +1,1712 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_pm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#ifdef CONFIG_PM + +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "riscv_arch.h" + +#include "hardware/esp32c3_rtccntl.h" +#include "hardware/esp32c3_system.h" +#include "hardware/esp32c3_syscon.h" +#include "hardware/esp32c3_soc.h" +#include "hardware/esp32c3_uart.h" +#include "hardware/esp32c3_gpio.h" +#include "hardware/apb_ctrl_reg.h" + +#include "esp32c3_attr.h" +#include "esp32c3_rtc.h" +#include "esp32c3_clockconfig.h" +#include "esp32c3_pm.h" + +#ifdef CONFIG_ESP32C3_RT_TIMER +#include "esp32c3_rt_timer.h" +#endif + +#ifdef CONFIG_SCHED_TICKLESS +#include "esp32c3_tickless.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If light sleep time is less than that, don't power down flash */ + +#define FLASH_PD_MIN_SLEEP_TIME_US 2000 + +/* Minimal amount of time we can sleep for. */ + +#define LIGHT_SLEEP_MIN_TIME_US 200 + +#define RTC_MODULE_SLEEP_PREPARE_CYCLES (6) + +#ifndef MAX +#define MAX(a,b) a > b ? a : b +#endif + +/* Time from VDD_SDIO power up to first flash read in ROM code */ + +#define VDD_SDIO_POWERUP_TO_FLASH_READ_US (700) + +/* Extra time it takes to enter and exit light sleep and deep sleep */ + +#define LIGHT_SLEEP_TIME_OVERHEAD_US (37) + +#ifdef CONFIG_ESP32C3_CPU_FREQ_MHZ +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32C3_CPU_FREQ_MHZ +#else +#define DEFAULT_CPU_FREQ_MHZ (160) +#endif + +#define DEFAULT_SLEEP_OUT_OVERHEAD_US (105) +#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ) + +#define DEEP_SLEEP_WAKEUP_DELAY 0 + +#define RTC_VDDSDIO_TIEH_1_8V 0 /* TIEH field value for 1.8V VDDSDIO */ +#define RTC_VDDSDIO_TIEH_3_3V 1 /* TIEH field value for 3.3V VDDSDIO */ + +#define RTC_GPIO_TRIG_EN BIT(2) /* GPIO wakeup */ +#define RTC_TIMER_TRIG_EN BIT(3) /* Timer wakeup */ +#define RTC_WIFI_TRIG_EN BIT(5) /* Wi-Fi wakeup (light sleep only) */ +#define RTC_UART0_TRIG_EN BIT(6) /* UART0 wakeup (light sleep only) */ +#define RTC_UART1_TRIG_EN BIT(7) /* UART1 wakeup (light sleep only) */ +#define RTC_BT_TRIG_EN BIT(10) /* BT wakeup (light sleep only) */ +#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) +#define RTC_USB_TRIG_EN BIT(14) +#define RTC_BROWNOUT_DET_TRIG_EN BIT(16) + +#define PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO (1) +#define PERIPH_SKIP_SLEEP_NO (1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Power down options */ + +enum esp32c3_sleep_pd_option_e +{ + /* Power down the power domain in sleep mode */ + + ESP_PD_OPTION_OFF, + + /* Keep power domain enabled during sleep mode */ + + ESP_PD_OPTION_ON, + + /* Keep power domain enabled in sleep mode if it is needed + * by one of the wakeup options, otherwise power it down. + */ + + ESP_PD_OPTION_AUTO +}; + +/* Power domains which can be powered down in sleep mode. */ + +enum esp32c3_sleep_pd_domain_e +{ + ESP_PD_DOMAIN_RTC_PERIPH = 0, /* RTC IO, sensors */ + ESP_PD_DOMAIN_RTC_SLOW_MEM, /* RTC slow memory */ + ESP_PD_DOMAIN_RTC_FAST_MEM, /* RTC fast memory */ + ESP_PD_DOMAIN_XTAL, /* XTAL oscillator */ + ESP_PD_DOMAIN_CPU, /* CPU core */ + ESP_PD_DOMAIN_MAX /* Number of domains */ +}; + +enum esp32c3_periph_module_e +{ + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_SPI_MODULE, + PERIPH_SPI2_MODULE, + PERIPH_TWAI_MODULE, + PERIPH_RNG_MODULE, + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_WIFI_BT_COMMON_MODULE, + PERIPH_BT_BASEBAND_MODULE, + PERIPH_BT_LC_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_MODULE_MAX +}; + +/* Internal structure which holds all requested deep sleep parameters. */ + +struct esp32c3_sleep_config_s +{ + enum esp32c3_sleep_pd_option_e pd_options[ESP_PD_DOMAIN_MAX]; + uint64_t sleep_duration; + uint32_t wakeup_triggers : 15; + uint32_t ext1_trigger_mode : 1; + uint32_t ext1_rtc_gpio_mask : 18; + uint32_t ext0_trigger_level : 1; + uint32_t ext0_rtc_gpio_num : 5; + uint32_t gpio_wakeup_mask : 6; + uint32_t gpio_trigger_mode : 6; + uint32_t sleep_time_adjustment; + uint32_t ccount_ticks_record; + uint32_t sleep_time_overhead_out; + uint32_t rtc_clk_cal_period; + uint64_t rtc_ticks_at_sleep_start; + void *cpu_pd_mem; +}; + +/* Structure describing vddsdio configuration. */ + +struct esp32c3_rtc_vddsdio_config_s +{ + uint32_t force : 1; /* If 1, use configuration from RTC registers; + * if 0, use EFUSE/bootstrapping pins. + */ + uint32_t enable : 1; /* Enable VDDSDIO regulator */ + uint32_t tieh : 1; /* Select VDDSDIO voltage. One of + * RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V + */ + uint32_t drefh : 2; /* Tuning parameter for VDDSDIO regulator */ + uint32_t drefm : 2; /* Tuning parameter for VDDSDIO regulator */ + uint32_t drefl : 2; /* Tuning parameter for VDDSDIO regulator */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t IRAM_ATTR esp32c3_periph_ll_get_rst_en_mask + (enum esp32c3_periph_module_e periph, bool enable); +static uint32_t IRAM_ATTR esp32c3_periph_ll_get_rst_en_reg( + enum esp32c3_periph_module_e periph); +static uint32_t IRAM_ATTR esp32c3_periph_ll_get_clk_en_reg( + enum esp32c3_periph_module_e periph); +static inline uint32_t IRAM_ATTR esp32c3_periph_ll_get_clk_en_mask( + enum esp32c3_periph_module_e periph); +static inline bool IRAM_ATTR esp32c3_periph_ll_periph_enabled( + enum esp32c3_periph_module_e periph); +static inline void IRAM_ATTR esp32c3_uart_tx_wait_idle(uint8_t uart_no); +static void IRAM_ATTR esp32c3_flush_uarts(void); +static void IRAM_ATTR esp32c3_suspend_uarts(void); +static void IRAM_ATTR esp32c3_resume_uarts(void); +static void IRAM_ATTR esp32c3_timer_wakeup_prepare(void); +static uint32_t IRAM_ATTR esp32c3_get_power_down_flags(void); +static void IRAM_ATTR esp32c3_set_vddsdio_config( + struct esp32c3_rtc_vddsdio_config_s config); +static int IRAM_ATTR esp32c3_get_vddsdio_config( + struct esp32c3_rtc_vddsdio_config_s *config); +static int IRAM_ATTR esp32c3_light_sleep_inner(uint32_t pd_flags, + uint32_t time_us, struct esp32c3_rtc_vddsdio_config_s config); +static void esp32c3_periph_module_enable( + enum esp32c3_periph_module_e periph); +static void IRAM_ATTR esp32c3_perip_clk_init(void); +static int IRAM_ATTR esp32c3_sleep_start(uint32_t pd_flags); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct esp32c3_sleep_config_s s_config = +{ + .pd_options = + { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, + ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, + ESP_PD_OPTION_AUTO + }, + .ccount_ticks_record = 0, + .sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US, + .wakeup_triggers = 0 +}; + +static _Atomic uint32_t pm_wakelock = 0; + +/* Inform peripherals of light sleep wakeup overhead time */ + +inform_out_sleep_overhead_cb_t + g_periph_inform_out_sleep_overhead_cb[PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO]; + +/* Indicates if light sleep shoule be skipped by peripherals. */ + +skip_light_sleep_cb_t g_periph_skip_sleep_cb[PERIPH_SKIP_SLEEP_NO]; + +static uint8_t ref_counts[PERIPH_MODULE_MAX] = +{ + 0 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Set the real CPU ticks per us to the ets, + * so that ets_delay_us will be accurate. + */ + +extern void ets_update_cpu_frequency(uint32_t ticks_per_us); + +/* Pauses execution for us microseconds. */ + +extern void esp_rom_delay_us(uint32_t us); + +/**************************************************************************** + * Name: esp32c3_periph_ll_get_rst_en_mask + * + * Description: + * Get system reset bit through periph module + * + * Input Parameters: + * periph - Periph module (one of enum esp32c3_periph_module_e values) + * enable - Whether hardware acceleration is enabled + * + * Returned Value: + * System reset bit + * + ****************************************************************************/ + +static inline uint32_t IRAM_ATTR esp32c3_periph_ll_get_rst_en_mask + (enum esp32c3_periph_module_e periph, bool enable) +{ + switch (periph) + { + case PERIPH_SARADC_MODULE: + return SYSTEM_APB_SARADC_RST; + + case PERIPH_RMT_MODULE: + return SYSTEM_RMT_RST; + + case PERIPH_LEDC_MODULE: + return SYSTEM_LEDC_RST; + + case PERIPH_UART0_MODULE: + return SYSTEM_UART_RST; + + case PERIPH_UART1_MODULE: + return SYSTEM_UART1_RST; + + case PERIPH_I2C0_MODULE: + return SYSTEM_I2C_EXT0_RST; + + case PERIPH_I2S1_MODULE: + return SYSTEM_I2S1_RST; + + case PERIPH_TIMG0_MODULE: + return SYSTEM_TIMERGROUP_RST; + + case PERIPH_TIMG1_MODULE: + return SYSTEM_TIMERGROUP1_RST; + + case PERIPH_UHCI0_MODULE: + return SYSTEM_UHCI0_RST; + + case PERIPH_SYSTIMER_MODULE: + return SYSTEM_SYSTIMER_RST; + + case PERIPH_GDMA_MODULE: + return SYSTEM_DMA_RST; + + case PERIPH_SPI_MODULE: + return SYSTEM_SPI01_RST; + + case PERIPH_SPI2_MODULE: + return SYSTEM_SPI2_RST; + + case PERIPH_TWAI_MODULE: + return SYSTEM_TWAI_RST; + + case PERIPH_HMAC_MODULE: + return SYSTEM_CRYPTO_HMAC_RST; + + case PERIPH_AES_MODULE: + if (enable == true) + { + /* Clear reset on digital signature, + * otherwise AES unit is held in reset also. + */ + + return (SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST); + } + + /* Don't return other units to reset, + * as this pulls reset on RSA & SHA units, respectively. + */ + + return SYSTEM_CRYPTO_AES_RST; + + case PERIPH_SHA_MODULE: + if (enable == true) + { + /* Clear reset on digital signature and HMAC, + * otherwise SHA is held in reset + */ + + return (SYSTEM_CRYPTO_SHA_RST | + SYSTEM_CRYPTO_DS_RST | SYSTEM_CRYPTO_HMAC_RST); + } + + /* Don't assert reset on secure boot, + * otherwise AES is held in reset + */ + + return SYSTEM_CRYPTO_SHA_RST; + + case PERIPH_RSA_MODULE: + if (enable == true) + { + /* also clear reset on digital signature, + * otherwise RSA is held in reset + */ + + return (SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_DS_RST); + } + + /* don't reset digital signature unit, + * as this resets AES also. + */ + + return SYSTEM_CRYPTO_RSA_RST; + + case PERIPH_DS_MODULE: + return SYSTEM_CRYPTO_DS_RST; + + default: + return 0; + } +} + +/**************************************************************************** + * Name: esp32c3_periph_ll_get_rst_en_reg + * + * Description: + * Get system reset register through periph module + * + * Input Parameters: + * periph - Periph module (one of enum esp32c3_periph_module_e values) + * + * Returned Value: + * System reset register + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32c3_periph_ll_get_rst_en_reg( + enum esp32c3_periph_module_e periph) +{ + switch (periph) + { + case PERIPH_RNG_MODULE: + case PERIPH_WIFI_MODULE: + case PERIPH_BT_MODULE: + case PERIPH_WIFI_BT_COMMON_MODULE: + case PERIPH_BT_BASEBAND_MODULE: + case PERIPH_BT_LC_MODULE: + return SYSTEM_WIFI_RST_EN_REG; + + case PERIPH_HMAC_MODULE: + case PERIPH_DS_MODULE: + case PERIPH_AES_MODULE: + case PERIPH_RSA_MODULE: + case PERIPH_SHA_MODULE: + case PERIPH_GDMA_MODULE: + return SYSTEM_PERIP_RST_EN1_REG; + + default: + return SYSTEM_PERIP_RST_EN0_REG; + } +} + +/**************************************************************************** + * Name: esp32c3_periph_ll_get_clk_en_reg + * + * Description: + * Get module clock register through periph module + * + * Input Parameters: + * periph - Periph module (one of enum esp32c3_periph_module_e values) + * + * Returned Value: + * Module clock register + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32c3_periph_ll_get_clk_en_reg( + enum esp32c3_periph_module_e periph) +{ + switch (periph) + { + case PERIPH_RNG_MODULE: + case PERIPH_WIFI_MODULE: + case PERIPH_BT_MODULE: + case PERIPH_WIFI_BT_COMMON_MODULE: + case PERIPH_BT_BASEBAND_MODULE: + case PERIPH_BT_LC_MODULE: + return SYSTEM_WIFI_CLK_EN_REG; + + case PERIPH_HMAC_MODULE: + case PERIPH_DS_MODULE: + case PERIPH_AES_MODULE: + case PERIPH_RSA_MODULE: + case PERIPH_SHA_MODULE: + case PERIPH_GDMA_MODULE: + return SYSTEM_PERIP_CLK_EN1_REG; + + default: + return SYSTEM_PERIP_CLK_EN0_REG; + } +} + +/**************************************************************************** + * Name: esp32c3_periph_ll_get_clk_en_mask + * + * Description: + * Get module clock bit through periph module + * + * Input Parameters: + * periph - Periph module (one of enum esp32c3_periph_module_e values) + * + * Returned Value: + * Module clock bit + * + ****************************************************************************/ + +static inline uint32_t IRAM_ATTR esp32c3_periph_ll_get_clk_en_mask( + enum esp32c3_periph_module_e periph) +{ + switch (periph) + { + case PERIPH_SARADC_MODULE: + return SYSTEM_APB_SARADC_CLK_EN; + + case PERIPH_RMT_MODULE: + return SYSTEM_RMT_CLK_EN; + + case PERIPH_LEDC_MODULE: + return SYSTEM_LEDC_CLK_EN; + + case PERIPH_UART0_MODULE: + return SYSTEM_UART_CLK_EN; + + case PERIPH_UART1_MODULE: + return SYSTEM_UART1_CLK_EN; + + case PERIPH_I2C0_MODULE: + return SYSTEM_I2C_EXT0_CLK_EN; + + case PERIPH_I2S1_MODULE: + return SYSTEM_I2S1_CLK_EN; + + case PERIPH_TIMG0_MODULE: + return SYSTEM_TIMERGROUP_CLK_EN; + + case PERIPH_TIMG1_MODULE: + return SYSTEM_TIMERGROUP1_CLK_EN; + + case PERIPH_UHCI0_MODULE: + return SYSTEM_UHCI0_CLK_EN; + + case PERIPH_SYSTIMER_MODULE: + return SYSTEM_SYSTIMER_CLK_EN; + + case PERIPH_SPI_MODULE: + return SYSTEM_SPI01_CLK_EN; + + case PERIPH_SPI2_MODULE: + return SYSTEM_SPI2_CLK_EN; + + case PERIPH_TWAI_MODULE: + return SYSTEM_TWAI_CLK_EN; + + case PERIPH_GDMA_MODULE: + return SYSTEM_DMA_CLK_EN; + + case PERIPH_AES_MODULE: + return SYSTEM_CRYPTO_AES_CLK_EN; + + case PERIPH_SHA_MODULE: + return SYSTEM_CRYPTO_SHA_CLK_EN; + + case PERIPH_RSA_MODULE: + return SYSTEM_CRYPTO_RSA_CLK_EN; + + case PERIPH_HMAC_MODULE: + return SYSTEM_CRYPTO_HMAC_CLK_EN; + + case PERIPH_DS_MODULE: + return SYSTEM_CRYPTO_DS_CLK_EN; + + case PERIPH_RNG_MODULE: + return SYSTEM_WIFI_CLK_RNG_EN; + + case PERIPH_WIFI_MODULE: + return SYSTEM_WIFI_CLK_WIFI_EN_M; + + case PERIPH_BT_MODULE: + return SYSTEM_WIFI_CLK_BT_EN_M; + + case PERIPH_WIFI_BT_COMMON_MODULE: + return SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M; + + case PERIPH_BT_BASEBAND_MODULE: + return SYSTEM_BT_BASEBAND_EN; + + case PERIPH_BT_LC_MODULE: + return SYSTEM_BT_LC_EN; + + default: + return 0; + } +} + +/**************************************************************************** + * Name: esp32c3_periph_ll_periph_enabled + * + * Description: + * Whether the current Periph module is enabled + * + * Input Parameters: + * periph - Periph module (one of enum esp32c3_periph_module_e values) + * + * Returned Value: + * Periph module is enabled or not + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32c3_periph_ll_periph_enabled( + enum esp32c3_periph_module_e periph) +{ + return ((getreg32(esp32c3_periph_ll_get_rst_en_reg(periph)) & + esp32c3_periph_ll_get_rst_en_mask(periph, false)) == 0) && + ((getreg32(esp32c3_periph_ll_get_clk_en_reg(periph)) & + esp32c3_periph_ll_get_clk_en_mask(periph)) != 0); +} + +/**************************************************************************** + * Name: esp32c3_uart_tx_wait_idle + * + * Description: + * Wait until uart tx full empty and the last char send ok. + * + * Input Parameters: + * uart_no - 0 for UART0, 1 for UART1, 2 for UART2 + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void IRAM_ATTR esp32c3_uart_tx_wait_idle(uint8_t uart_no) +{ + uint32_t status; + do + { + status = getreg32(UART_STATUS_REG(uart_no)); + } + while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0); +} + +/**************************************************************************** + * Name: esp32c3_flush_uarts + * + * Description: + * Wait until UART0/UART1 tx full empty and the last char send ok + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_flush_uarts(void) +{ + int i; + + for (i = 0; i < ESP32C3_NUARTS; ++i) + { + if (esp32c3_periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) + { + esp32c3_uart_tx_wait_idle(i); + } + } +} + +/**************************************************************************** + * Name: esp32c3_suspend_uarts + * + * Description: + * Suspend UART0/UART1 output + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_suspend_uarts(void) +{ + int i; + uint32_t uart_fsm = 0; + + for (i = 0; i < ESP32C3_NUARTS; ++i) + { + if (!esp32c3_periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) + { + continue; + } + + modifyreg32(UART_FLOW_CONF_REG(i), 0, UART_FORCE_XOFF); + do + { + uart_fsm = REG_GET_FIELD(UART_STATUS_REG(i), UART_ST_UTX_OUT); + } + while (!(uart_fsm == UART_FSM_IDLE || + uart_fsm == UART_FSM_TX_WAIT_SEND)); + } +} + +/**************************************************************************** + * Name: esp32c3_resume_uarts + * + * Description: + * Re-enable UART0/UART1/UART2 output + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_resume_uarts(void) +{ + int i; + + for (i = 0; i < ESP32C3_NUARTS; ++i) + { + if (!esp32c3_periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) + { + continue; + } + + REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF); + REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); + REG_CLR_BIT(UART_FLOW_CONF_REG(i), + UART_SW_FLOW_CON_EN | UART_FORCE_XON); + REG_SET_BIT(UART_ID_REG(i), UART_UPDATE); + } +} + +/**************************************************************************** + * Name: esp32c3_get_power_down_flags + * + * Description: + * Get power domains that can be powered down + * + * Input Parameters: + * None + * + * Returned Value: + * Power domains + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32c3_get_power_down_flags(void) +{ + uint32_t pd_flags = 0; + + s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON; + + if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) + { + if (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN) + { + s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = + ESP_PD_OPTION_ON; + } + else + { + s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = + ESP_PD_OPTION_OFF; + } + } + + if (s_config.cpu_pd_mem == NULL) + { + s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON; + } + + if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) + { + s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF; + } + + /* Prepare flags based on the selected options */ + + if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM; + } + + if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_RTC_PERIPH; + } + + if (s_config.pd_options[ESP_PD_DOMAIN_CPU] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_CPU; + } + + return pd_flags; +} + +/**************************************************************************** + * Name: esp32c3_timer_wakeup_prepare + * + * Description: + * Configure timer to wake-up + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_timer_wakeup_prepare(void) +{ + int64_t ticks; + int64_t sleep_duration = (int64_t)s_config.sleep_duration - + (int64_t) s_config.sleep_time_adjustment; + if (sleep_duration < 0) + { + sleep_duration = 0; + } + + ticks = esp32c3_rtc_time_us_to_slowclk(sleep_duration, + s_config.rtc_clk_cal_period); + esp32c3_rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start + + ticks); +} + +/**************************************************************************** + * Name: esp32c3_set_vddsdio_config + * + * Description: + * Set new VDDSDIO configuration using RTC registers. + * + * Input Parameters: + * New VDDSDIO configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_set_vddsdio_config( + struct esp32c3_rtc_vddsdio_config_s config) +{ + uint32_t val = 0; + val |= (config.force << RTC_CNTL_SDIO_FORCE_S); + val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S); + val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S); + val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S); + val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S); + val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S); + val |= RTC_CNTL_SDIO_PD_EN; + putreg32((uint32_t)val, RTC_CNTL_SDIO_CONF_REG); +} + +/**************************************************************************** + * Name: esp32c3_get_vddsdio_config + * + * Description: + * Get current VDDSDIO configuration. + * + * Input Parameters: + * Incoming parameter address of VDDSDIO configuration to be saved + * + * Returned Value: + * Zero (OK) is returned on success. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32c3_get_vddsdio_config( + struct esp32c3_rtc_vddsdio_config_s *config) +{ + struct esp32c3_rtc_vddsdio_config_s *result = config; + uint32_t strap_reg; + uint32_t sdio_conf_reg = getreg32(RTC_CNTL_SDIO_CONF_REG); + + result->drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) + >> RTC_CNTL_DREFH_SDIO_S; + result->drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) + >> RTC_CNTL_DREFM_SDIO_S; + result->drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) + >> RTC_CNTL_DREFL_SDIO_S; + + if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) + { + /* Get configuration from RTC */ + + result->force = 1; + result->enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) + >> RTC_CNTL_XPD_SDIO_REG_S; + result->tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) + >> RTC_CNTL_SDIO_TIEH_S; + + return OK; + } + + /* Otherwise, VDD_SDIO is controlled by bootstrapping pin */ + + strap_reg = getreg32(GPIO_STRAP_REG); + result->force = 0; + result->tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V + : RTC_VDDSDIO_TIEH_3_3V; + result->enable = 1; + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sleep_start + * + * Description: + * Enter low power mode. + * + * Input Parameters: + * Power domains + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +static int IRAM_ATTR esp32c3_sleep_start(uint32_t pd_flags) +{ + int result; + struct esp32c3_cpu_freq_config_s cpu_freq_config; + bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG; + + /* Stop UART output so that output is not lost due to APB frequency change. + * For light sleep, suspend UART output — it will resume after wakeup. + * For deep sleep, wait for the contents of UART FIFO to be sent. + */ + + if (deep_sleep) + { + esp32c3_flush_uarts(); + } + else + { + esp32c3_suspend_uarts(); + } + + /* Save current frequency and switch to XTAL */ + + esp32c3_rtc_clk_cpu_freq_get_config(&cpu_freq_config); + esp32c3_rtc_cpu_freq_set_xtal(); + + /* Enter sleep */ + + esp32c3_rtc_sleep_init(pd_flags); + + esp32c3_rtc_sleep_low_init(s_config.rtc_clk_cal_period); + + /* Set state machine time for light sleep */ + + if (deep_sleep == false) + { + esp32c3_rtc_sleep_low_init(s_config.rtc_clk_cal_period); + } + + /* Configure timer wakeup */ + + if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) + && s_config.sleep_duration > 0) + { + esp32c3_timer_wakeup_prepare(); + } + + if (deep_sleep) + { + /* Otherwise, need to call the dedicated soc function for this */ + + result = esp32c3_rtc_deep_sleep_start(s_config.wakeup_triggers, 0); + } + else + { + result = esp32c3_rtc_sleep_start(s_config.wakeup_triggers, 0, 1); + } + + /* Restore CPU frequency */ + + esp32c3_rtc_clk_cpu_freq_set_config(&cpu_freq_config); + + if (!deep_sleep) + { + s_config.ccount_ticks_record = esp32c3_cpu_cycle_count(); + } + + REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); + + /* Re-enable UART output */ + + esp32c3_resume_uarts(); + + return result; +} + +/**************************************************************************** + * Name: esp32c3_light_sleep_inner + * + * Description: + * Enter low power mode, then wait for flash to be ready on wakeup + * + * Input Parameters: + * pd_flags - Power domains + * time_us - Time to wait for spi_flash become ready + * config - VDDSDIO configuration + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +static int IRAM_ATTR esp32c3_light_sleep_inner(uint32_t pd_flags, + uint32_t time_us, struct esp32c3_rtc_vddsdio_config_s config) +{ + /* Enter sleep */ + + int err = esp32c3_sleep_start(pd_flags); + + /* If VDDSDIO regulator was controlled by RTC registers before sleep. + * restore the configuration. + */ + + if (config.force) + { + esp32c3_set_vddsdio_config(config); + } + + /* If SPI flash was powered down, wait for it to become ready. */ + + if (pd_flags & RTC_SLEEP_PD_VDDSDIO) + { + /* Wait for the flash chip to start up. */ + + esp_rom_delay_us(time_us); + } + + return err; +} + +/**************************************************************************** + * Name: esp32c3_periph_module_enable + * + * Description: + * Enable peripheral module + * + * Input Parameters: + * periph - Periph module (one of enum esp32c3_periph_module_e values) + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32c3_periph_module_enable(enum esp32c3_periph_module_e periph) +{ + irqstate_t flags = enter_critical_section(); + + assert(periph < PERIPH_MODULE_MAX); + if (ref_counts[periph] == 0) + { + modifyreg32(esp32c3_periph_ll_get_clk_en_reg(periph), 0, + esp32c3_periph_ll_get_clk_en_mask(periph)); + modifyreg32(esp32c3_periph_ll_get_rst_en_reg(periph), + esp32c3_periph_ll_get_rst_en_mask(periph, true), 0); + } + + ref_counts[periph]++; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32c3_perip_clk_init + * + * Description: + * This function disables clock of useless peripherals when cpu starts. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_perip_clk_init(void) +{ + uint32_t common_perip_clk1 = 0; + + /* Reset the communication peripherals like I2C, SPI, + * UART, I2S and bring them to known state. + */ + + uint32_t common_perip_clk = SYSTEM_WDG_CLK_EN | + SYSTEM_I2S0_CLK_EN | + SYSTEM_UART1_CLK_EN | + SYSTEM_UART2_CLK_EN | + SYSTEM_SPI2_CLK_EN | + SYSTEM_I2C_EXT0_CLK_EN | + SYSTEM_UHCI0_CLK_EN | + SYSTEM_RMT_CLK_EN | + SYSTEM_LEDC_CLK_EN | + SYSTEM_UHCI1_CLK_EN | + SYSTEM_TIMERGROUP1_CLK_EN | + SYSTEM_SPI3_CLK_EN | + SYSTEM_SPI4_CLK_EN | + SYSTEM_I2C_EXT1_CLK_EN | + SYSTEM_TWAI_CLK_EN | + SYSTEM_I2S1_CLK_EN | + SYSTEM_SPI2_DMA_CLK_EN | + SYSTEM_SPI3_DMA_CLK_EN; + + uint32_t hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | + SYSTEM_CRYPTO_SHA_CLK_EN | + SYSTEM_CRYPTO_RSA_CLK_EN; + uint32_t wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | + SYSTEM_WIFI_CLK_BT_EN_M | + SYSTEM_WIFI_CLK_UNUSED_BIT5 | + SYSTEM_WIFI_CLK_UNUSED_BIT12; + + /* Disable some peripheral clocks. */ + + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk, 0); + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, common_perip_clk); + + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1, 0); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, 0, common_perip_clk1); + + /* Disable hardware crypto clocks. */ + + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk, 0); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, 0, hwcrypto_perip_clk); + + /* Disable WiFi/BT/SDIO clocks. */ + + modifyreg32(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk, 0); + modifyreg32(SYSTEM_WIFI_CLK_EN_REG, 0, SYSTEM_WIFI_CLK_EN); + + /* Set WiFi light sleep clock source to RTC slow clock */ + + REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); + modifyreg32(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M, + SYSTEM_LPCLK_SEL_RTC_SLOW); + + /* Enable RNG clock. */ + + esp32c3_periph_module_enable(PERIPH_RNG_MODULE); +} + +/**************************************************************************** + * Name: esp32c3_periph_should_skip_sleep + * + * Description: + * Indicates if light sleep shoule be skipped by peripherals + * + * Input Parameters: + * None + * + * Returned Value: + * True is returned on success. Otherwise false. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32c3_periph_should_skip_sleep(void) +{ + for (int i = 0; i < PERIPH_SKIP_SLEEP_NO; i++) + { + if (g_periph_skip_sleep_cb[i]) + { + if (g_periph_skip_sleep_cb[i]() == true) + { + return true; + } + } + } + + return false; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_pm_register_skip_sleep_callback + * + * Description: + * Unregister callback function of skipping light sleep. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_pm_register_skip_sleep_callback(skip_light_sleep_cb_t cb) +{ + for (int i = 0; i < PERIPH_SKIP_SLEEP_NO; i++) + { + if (g_periph_skip_sleep_cb[i] == cb) + { + return OK; + } + else if (g_periph_skip_sleep_cb[i] == NULL) + { + g_periph_skip_sleep_cb[i] = cb; + return OK; + } + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp32c3_pm_unregister_skip_sleep_callback + * + * Description: + * Register callback function of skipping light sleep. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb) +{ + for (int i = 0; i < PERIPH_SKIP_SLEEP_NO; i++) + { + if (g_periph_skip_sleep_cb[i] == cb) + { + g_periph_skip_sleep_cb[i] = NULL; + return OK; + } + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp32c3_should_skip_light_sleep + * + * Description: + * Indicates if light sleep shoule be skipped. + * + * Input Parameters: + * None + * + * Returned Value: + * True is returned on success. Otherwise false. + * + ****************************************************************************/ + +bool IRAM_ATTR esp32c3_should_skip_light_sleep(void) +{ + if (esp32c3_periph_should_skip_sleep() == true) + { + return true; + } + + return false; +} + +/**************************************************************************** + * Name: esp32c3_pm_register_inform_out_sleep_overhead_callback + * + * Description: + * Register informing peripherals of light sleep wakeup overhead time + * callback function. + * + * Input Parameters: + * cb - callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_pm_register_inform_out_sleep_overhead_callback( + inform_out_sleep_overhead_cb_t cb) +{ + for (int i = 0; i < PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO; i++) + { + if (g_periph_inform_out_sleep_overhead_cb[i] == cb) + { + return ERROR; + } + else if (g_periph_inform_out_sleep_overhead_cb[i] == NULL) + { + g_periph_inform_out_sleep_overhead_cb[i] = cb; + return OK; + } + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp32c3_pm_unregister_inform_out_sleep_overhead_callback + * + * Description: + * Unregister informing peripherals of light sleep wakeup overhead time + * callback function. + * + * Input Parameters: + * cb - callback function + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_pm_unregister_inform_out_sleep_overhead_callback( + inform_out_sleep_overhead_cb_t cb) +{ + for (int i = 0; i < PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO; i++) + { + if (g_periph_inform_out_sleep_overhead_cb[i] == cb) + { + g_periph_inform_out_sleep_overhead_cb[i] = NULL; + return OK; + } + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp32c3_periph_inform_out_sleep_overhead + * + * Description: + * Inform peripherals of light sleep wakeup overhead time + * + * Input Parameters: + * us - light sleep wakeup overhead time + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_periph_inform_out_sleep_overhead(uint32_t us) +{ + for (int i = 0; i < PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO; i++) + { + if (g_periph_inform_out_sleep_overhead_cb[i]) + { + g_periph_inform_out_sleep_overhead_cb[i](us); + } + } +} + +/**************************************************************************** + * Name: esp32c3_sleep_enable_rtc_timer_wakeup + * + * Description: + * Configure RTC TIMER wake-up interval + * + * Input Parameters: + * time_in_us - Configure wake-up time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_sleep_enable_rtc_timer_wakeup(uint64_t time_in_us) +{ + s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN; + s_config.sleep_duration = time_in_us; +} + +/**************************************************************************** + * Name: esp32c3_sleep_enable_wifi_wakeup + * + * Description: + * Configure Wi-Fi wake-up source + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_sleep_enable_wifi_wakeup(void) +{ + s_config.wakeup_triggers |= RTC_WIFI_TRIG_EN; +} + +/**************************************************************************** + * Name: esp32c3_light_sleep_start + * + * Description: + * Enter light sleep mode + * + * Input Parameters: + * sleep_time - Actual sleep time + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +int IRAM_ATTR esp32c3_light_sleep_start(uint64_t *sleep_time) +{ + int ret = OK; + irqstate_t flags; + uint32_t pd_flags; + uint32_t flash_enable_time_us; + uint32_t vddsdio_pd_sleep_duration; + struct esp32c3_rtc_vddsdio_config_s vddsdio_config; + uint32_t rtc_cntl_xtl_buf_wait_cycles; + uint32_t sleep_time_overhead_in; + uint32_t ccount_at_sleep_start; + + flags = enter_critical_section(); + + s_config.ccount_ticks_record = esp32c3_cpu_cycle_count(); + s_config.rtc_ticks_at_sleep_start = esp32c3_rtc_time_get(); + ccount_at_sleep_start = esp32c3_cpu_cycle_count(); + sleep_time_overhead_in = (ccount_at_sleep_start - + s_config.ccount_ticks_record) / (esp32c3_clk_cpu_freq() / 1000000ULL); + + /* Decide which power domains can be powered down */ + + pd_flags = esp32c3_get_power_down_flags(); + + s_config.rtc_clk_cal_period = + esp32c3_rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); + + /* Adjustment time consists of parts below: + * 1. Hardware time waiting for internal 8M oscilate clock and XTAL; + * 2. Hardware state swithing time of the rtc main state machine; + * 3. Code execution time when clock is not stable; + * 4. Code execution time which can be measured; + */ + + rtc_cntl_xtl_buf_wait_cycles = esp32c3_rtc_time_us_to_slowclk( + RTC_CNTL_XTL_BUF_WAIT_SLP_US, s_config.rtc_clk_cal_period); + + s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + + sleep_time_overhead_in + s_config.sleep_time_overhead_out + + esp32c3_rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_cycles + + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, + s_config.rtc_clk_cal_period); + + /* Decide if VDD_SDIO needs to be powered down; + * If it needs to be powered down, adjust sleep time. + */ + + flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US + + DEEP_SLEEP_WAKEUP_DELAY; + + /* When SPIRAM is disabled in menuconfig, the minimum sleep time of the + * system needs to meet the sum below: + * 1. Wait time for the flash power-on after waking up; + * 2. The execution time of codes between RTC Timer get start time + * with hardware starts to switch state to sleep; + * 3. The hardware state switching time of the rtc state machine during + * sleep and wake-up. This process requires 6 cycles to complete. + * The specific hardware state switching process and the cycles + * consumed are rtc_cpu_run_stall(1), cut_pll_rtl(2), cut_8m(1), + * min_protect(2); + * 4. All the adjustment time which is + * s_config.sleep_time_adjustment below. + */ + + vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US, + flash_enable_time_us + LIGHT_SLEEP_MIN_TIME_US + + s_config.sleep_time_adjustment + esp32c3_rtc_time_slowclk_to_us( + RTC_MODULE_SLEEP_PREPARE_CYCLES, s_config.rtc_clk_cal_period)); + + if (s_config.sleep_duration > vddsdio_pd_sleep_duration) + { + pd_flags |= RTC_SLEEP_PD_VDDSDIO; + if (s_config.sleep_time_overhead_out < flash_enable_time_us) + { + s_config.sleep_time_adjustment += flash_enable_time_us; + } + } + else + { + if (s_config.sleep_time_overhead_out > flash_enable_time_us) + { + s_config.sleep_time_adjustment -= flash_enable_time_us; + } + } + + esp32c3_periph_inform_out_sleep_overhead( + s_config.sleep_time_adjustment - sleep_time_overhead_in); + + esp32c3_get_vddsdio_config(&vddsdio_config); + + /* Enter sleep, then wait for flash to be ready on wakeup */ + + ret = esp32c3_light_sleep_inner(pd_flags, flash_enable_time_us, + vddsdio_config); + + if (sleep_time != NULL) + { + *sleep_time = esp32c3_rtc_time_slowclk_to_us(esp32c3_rtc_time_get() - + s_config.rtc_ticks_at_sleep_start, s_config.rtc_clk_cal_period); + } + + s_config.sleep_time_overhead_out = (esp32c3_cpu_cycle_count() - + s_config.ccount_ticks_record) / (esp32c3_clk_cpu_freq() / 1000000ULL); + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_pminit + * + * Description: + * Initialize force sleep parameters. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_pminit(void) +{ + /* Initialize RTC parameters */ + + esp32c3_rtc_init(); + esp32c3_rtc_clk_set(); + esp32c3_perip_clk_init(); +} + +/**************************************************************************** + * Name: esp32c3_pmstandby + * + * Description: + * Enter force sleep. + * + * Input Parameters: + * time_in_us - force sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_pmstandby(uint64_t time_in_us) +{ + uint64_t rtc_diff_us; +#ifdef CONFIG_ESP32C3_RT_TIMER + uint64_t hw_start_us; + uint64_t hw_end_us; + uint64_t hw_diff_us; +#endif + + /* don't power down XTAL — powering it up takes different time on. */ + + fflush(stdout); + esp32c3_sleep_enable_rtc_timer_wakeup(time_in_us); +#ifdef CONFIG_ESP32C3_RT_TIMER + /* Get rt-timer timestamp before entering sleep */ + + hw_start_us = rt_timer_time_us(); +#endif + + esp32c3_light_sleep_start(&rtc_diff_us); + +#ifdef CONFIG_ESP32C3_RT_TIMER + /* Get rt-timer timestamp after waking up from sleep */ + + hw_end_us = rt_timer_time_us(); + hw_diff_us = hw_end_us - hw_start_us; + DEBUGASSERT(rtc_diff_us > hw_diff_us); + + rt_timer_calibration(rtc_diff_us - hw_diff_us); +#endif + +#ifdef CONFIG_SCHED_TICKLESS + up_step_idletime((uint32_t)time_in_us); +#endif + + pwrinfo("Returned from auto-sleep, slept for %" PRIu32 " ms\n", + (uint32_t)(rtc_diff_us) / 1000); +} + +/**************************************************************************** + * Name: esp32c3_deep_sleep_start + * + * Description: + * Enter deep sleep mode + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_deep_sleep_start(void) +{ + uint32_t pd_flags; + + /* record current RTC time */ + + s_config.rtc_ticks_at_sleep_start = esp32c3_rtc_time_get(); + + /* Decide which power domains can be powered down */ + + pd_flags = esp32c3_get_power_down_flags(); + s_config.rtc_clk_cal_period = getreg32(RTC_SLOW_CLK_CAL_REG); + + /* Correct the sleep time */ + + s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US; + + /* Enter deep sleep */ + + esp32c3_sleep_start(RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | pd_flags); + + /* Because RTC is in a slower clock domain than the CPU, it + * can take several CPU cycles for the sleep mode to start. + */ + + while (1); +} + +/**************************************************************************** + * Name: esp32c3_pmsleep + * + * Description: + * Enter deep sleep. + * + * Input Parameters: + * time_in_us - deep sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_pmsleep(uint64_t time_in_us) +{ + fflush(stdout); + esp32c3_sleep_enable_rtc_timer_wakeup(time_in_us); + esp32c3_deep_sleep_start(); +} + +/**************************************************************************** + * Name: esp32c3_pm_lockacquire + * + * Description: + * Take a power management lock + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_pm_lockacquire(void) +{ + ++pm_wakelock; +} + +/**************************************************************************** + * Name: esp32c3_pm_lockrelease + * + * Description: + * Release the lock taken using esp32c3_pm_lockacquire. + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_pm_lockrelease(void) +{ + --pm_wakelock; +} + +/**************************************************************************** + * Name: esp32c3_pm_lockstatus + * + * Description: + * Return power management lock status. + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32c3_pm_lockstatus(void) +{ + return pm_wakelock; +} + +#endif /* CONFIG_PM */ \ No newline at end of file diff --git a/arch/risc-v/src/esp32c3/esp32c3_pm.h b/arch/risc-v/src/esp32c3/esp32c3_pm.h new file mode 100644 index 00000000000..6644a7f42f1 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_pm.h @@ -0,0 +1,300 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_pm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Callback function type for peripherals to + * know light sleep wakeup overhead. + */ + +typedef void (*inform_out_sleep_overhead_cb_t)(uint32_t); + +/* Callback function type for peripherals to skip light sleep. */ + +typedef bool (*skip_light_sleep_cb_t)(void); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_sleep_enable_rtc_timer_wakeup + * + * Description: + * Configure wake-up interval + * + * Input Parameters: + * time_in_us - Configure wake-up time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_sleep_enable_rtc_timer_wakeup(uint64_t time_in_us); + +/**************************************************************************** + * Name: esp32c3_light_sleep_start + * + * Description: + * Enter light sleep mode + * + * Input Parameters: + * sleep_time - Actual sleep time + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +int esp32c3_light_sleep_start(uint64_t *sleep_time); + +/**************************************************************************** + * Name: esp32c3_pminit + * + * Description: + * Initialize force sleep parameters. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_pminit(void); + +/**************************************************************************** + * Name: esp32c3_pmstandby + * + * Description: + * Enter force sleep time interval. + * + * Input Parameters: + * time_in_us - force sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_pmstandby(uint64_t time_in_us); + +/**************************************************************************** + * Name: esp32c3_deep_sleep_start + * + * Description: + * Enter deep sleep mode + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_deep_sleep_start(void); + +/**************************************************************************** + * Name: esp32c3_pmsleep + * + * Description: + * Enter deep sleep. + * + * Input Parameters: + * time_in_us - deep sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_pmsleep(uint64_t time_in_us); + +/**************************************************************************** + * Name: esp32c3_pm_lockacquire + * + * Description: + * Take a power management lock + * + ****************************************************************************/ + +void esp32c3_pm_lockacquire(void); + +/**************************************************************************** + * Name: esp32c3_pm_lockrelease + * + * Description: + * Release the lock taken using esp32c3_pm_lockacquire. + * + ****************************************************************************/ + +void esp32c3_pm_lockrelease(void); + +/**************************************************************************** + * Name: esp32c3_pm_lockstatus + * + * Description: + * Return power management lock status. + * + ****************************************************************************/ + +uint32_t esp32c3_pm_lockstatus(void); + +/**************************************************************************** + * Name: esp32c3_sleep_enable_wifi_wakeup + * + * Description: + * Configure Wi-Fi wake-up source + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_sleep_enable_wifi_wakeup(void); + +/**************************************************************************** + * Name: esp32c3_should_skip_light_sleep + * + * Description: + * Indicates if light sleep shoule be skipped. + * + * Input Parameters: + * None + * + * Returned Value: + * True is returned on success. Otherwise false. + * + ****************************************************************************/ + +bool esp32c3_should_skip_light_sleep(void); + +/**************************************************************************** + * Name: esp32c3_pm_register_inform_out_sleep_overhead_callback + * + * Description: + * Register informing peripherals of light sleep wakeup overhead time + * callback function. + * + * Input Parameters: + * cb - callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_pm_register_inform_out_sleep_overhead_callback( + inform_out_sleep_overhead_cb_t cb); + +/**************************************************************************** + * Name: esp32c3_pm_unregister_inform_out_sleep_overhead_callback + * + * Description: + * Unregister informing peripherals of light sleep wakeup overhead time + * callback function. + * + * Input Parameters: + * cb - callback function + * + * Returned Value: + * None + * + ****************************************************************************/ + +int esp32c3_pm_unregister_inform_out_sleep_overhead_callback( + inform_out_sleep_overhead_cb_t cb); + +/**************************************************************************** + * Name: esp32c3_pm_register_skip_sleep_callback + * + * Description: + * Unregister callback function of skipping light sleep. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_pm_register_skip_sleep_callback(skip_light_sleep_cb_t cb); + +/**************************************************************************** + * Name: esp32c3_pm_unregister_skip_sleep_callback + * + * Description: + * Register callback function of skipping light sleep. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb); + +#endif /* CONFIG_PM */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_pminitialize.c b/arch/risc-v/src/esp32c3/esp32c3_pminitialize.c new file mode 100644 index 00000000000..ad1e87a02ce --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_pminitialize.c @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_pminitialize.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "esp32c3_pm.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_pminitialize + * + * Description: + * Initialize the power management subsystem. + * + ****************************************************************************/ + +void riscv_pminitialize(void) +{ + /* Initialize RTC parameters */ + + esp32c3_pminit(); + + /* Then initialize the NuttX power management subsystem proper */ + + pm_initialize(); +} + +#endif /* CONFIG_PM */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rsa.c b/arch/risc-v/src/esp32c3/esp32c3_rsa.c new file mode 100644 index 00000000000..fd4d21f9c20 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rsa.c @@ -0,0 +1,2375 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rsa.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32C3_RSA_ACCELERATOR + +#include +#include +#include +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "esp32c3_rsa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_PKCS1_V15 +#define RSA_EXPONENT_BLINDING 28 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rsa_check_context + * + * Description: + * Checks whether the context fields are set in such a way + * that the RSA primitives will be able to execute without error. + * + * Input Parameters: + * ctx - The initialized RSA context to store the parameters in + * N - The RSA modulus + * NL - The Byte length of \p N + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int rsa_check_context(struct esp32c3_rsa_context_s const *ctx, + int is_priv, int blinding_needed) +{ +#if !defined(ESP32C3_RSA_NO_CRT) + ((void) blinding_needed); +#endif + + if (ctx->len != esp32c3_mpi_size(&ctx->N) || + ctx->len > ESP32C3_MPI_MAX_SIZE) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + /* 1. Modular exponentiation needs positive, odd moduli */ + + if (esp32c3_mpi_cmp_int(&ctx->N, 0) <= 0 || + esp32c3_mpi_get_bit(&ctx->N, 0) == 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + +#if !defined(ESP32C3_RSA_NO_CRT) + if (is_priv && + (esp32c3_mpi_cmp_int(&ctx->P, 0) <= 0 || + esp32c3_mpi_get_bit(&ctx->P, 0) == 0 || + esp32c3_mpi_cmp_int(&ctx->Q, 0) <= 0 || + esp32c3_mpi_get_bit(&ctx->Q, 0) == 0)) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } +#endif /* !ESP32C3_RSA_NO_CRT */ + + /* 2. Exponents must be positive */ + + /* Always need E for public key operations */ + + if (esp32c3_mpi_cmp_int(&ctx->E, 0) <= 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + +#if defined(ESP32C3_RSA_NO_CRT) + /* For private key operations, use D or DP & DQ as exponents */ + + if (is_priv && esp32c3_mpi_cmp_int(&ctx->D, 0) <= 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } +#else + if (is_priv && + (esp32c3_mpi_cmp_int(&ctx->DP, 0) <= 0 || + esp32c3_mpi_cmp_int(&ctx->DQ, 0) <= 0)) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } +#endif /* ESP32C3_RSA_NO_CRT */ + +#if defined(ESP32C3_RSA_NO_CRT) + if (is_priv && blinding_needed && + (esp32c3_mpi_cmp_int(&ctx->P, 0) <= 0 || + esp32c3_mpi_cmp_int(&ctx->Q, 0) <= 0)) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } +#endif + +#if !defined(ESP32C3_RSA_NO_CRT) + if (is_priv && esp32c3_mpi_cmp_int(&ctx->QP, 0) <= 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: rsa_prepare_blinding + * + * Description: + * Generate or update blinding values. + * + * Input Parameters: + * ctx - The initialized RSA context to store the parameters in. + * f_rng - The RNG function + * p_rng - The RNG context to pass to \p f_rng + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int rsa_prepare_blinding(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) +{ + int ret; + int count = 0; + struct esp32c3_mpi_s R; + + esp32c3_mpi_init(&R); + + if (ctx->VF.p != NULL) + { + /* We already have blinding values, just update them by squaring */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&ctx->VI, &ctx->VI, &ctx->VI), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&ctx->VI, &ctx->VI, &ctx->N), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&ctx->VF, &ctx->VF, &ctx->VF), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&ctx->VF, &ctx->VF, &ctx->N), + cleanup); + + goto cleanup; + } + + /* Unblinding value: VF = random number, invertible mod N */ + + do + { + if (count++ > 10) + { + ret = ESP32C3_ERR_RSA_RNG_FAILED; + goto cleanup; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_fill_random(&ctx->VF, ctx->len - 1, + f_rng, p_rng), cleanup); + + /* Compute VF^-1 as R * (R VF)^-1 to avoid leaks from inv_mod. */ + + ESP32C3_MPI_CHK(esp32c3_mpi_fill_random(&R, ctx->len - 1, + f_rng, p_rng), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&ctx->VI, &ctx->VF, &R), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&ctx->VI, &ctx->VI, &ctx->N), + cleanup); + + ret = esp32c3_mpi_inv_mod(&ctx->VI, &ctx->VI, &ctx->N); + if (ret != 0 && ret != ESP32C3_ERR_MPI_NOT_ACCEPTABLE) + { + goto cleanup; + } + } + while (ret == ESP32C3_ERR_MPI_NOT_ACCEPTABLE); + + /* Finish the computation of VF^-1 = R * (R VF)^-1 */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&ctx->VI, &ctx->VI, &R), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&ctx->VI, &ctx->VI, &ctx->N), + cleanup); + + /* Blinding value: VI = VF^(-e) mod N */ + + ESP32C3_MPI_CHK(esp32c3_mpi_exp_mod(&ctx->VI, &ctx->VI, + &ctx->E, &ctx->N, &ctx->RN), + cleanup); + +cleanup: + esp32c3_mpi_free(&R); + + return ret; +} + +#if defined(ESP32C3_PKCS1_V15) +/* Implementation of the PKCS1-V1_5-ENCRYPT function */ + +static int esp32c3_rsa_pkcs1_v15_encrypt(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output) +{ + size_t nb_pad; + size_t olen; + int ret; + unsigned char *p = output; + + DEBUGASSERT(ctx != NULL); + DEBUGASSERT(mode == ESP32C3_RSA_PRIVATE || + mode == ESP32C3_RSA_PUBLIC); + DEBUGASSERT(output != NULL); + DEBUGASSERT(input != NULL); + + if (mode == ESP32C3_RSA_PRIVATE && ctx->padding != ESP32C3_RSA_PKCS_V15) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + olen = ctx->len; + + /* first comparison checks for overflow */ + + if (ilen + 11 < ilen || olen < ilen + 11) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + nb_pad = olen - 3 - ilen; + + *p++ = 0; + if (mode == ESP32C3_RSA_PUBLIC) + { + if (f_rng == NULL) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + *p++ = ESP32C3_RSA_CRYPT; + + while (nb_pad-- > 0) + { + int rng_dl = 100; + + do + { + ret = f_rng(p_rng, p, 1); + } + while (*p == 0 && --rng_dl && ret == 0); + + /* Check if RNG failed to generate data */ + + if (rng_dl == 0 || ret != 0) + { + return (ESP32C3_ERR_RSA_RNG_FAILED + ret); + } + + p++; + } + } + else + { + *p++ = ESP32C3_RSA_SIGN; + + while (nb_pad-- > 0) + { + *p++ = 0xff; + } + } + + *p++ = 0; + memcpy(p, input, ilen); + + return ((mode == ESP32C3_RSA_PUBLIC) + ? esp32c3_rsa_public(ctx, output, output) + : esp32c3_rsa_private(ctx, f_rng, p_rng, output, output)); +} +#endif /* ESP32C3_PKCS1_V15 */ + +#if defined(ESP32C3_PKCS1_V15) + +/**************************************************************************** + * Name: all_or_nothing_int + * + * Description: + * Turn zero-or-nonzero into zero-or-all-bits-one, without branches. + * + * Input Parameters: + * value - The value to analyze. + * + * Returned Value: + * Zero if \p value is zero, otherwise all-bits-one. + * + ****************************************************************************/ + +static unsigned all_or_nothing_int(unsigned value) +{ + return (- ((value | - value) >> (sizeof(value) * 8 - 1))); +} + +/**************************************************************************** + * Name: size_greater_than + * + * Description: + * Check whether a size is out of bounds, without branches. + * + * Input Parameters: + * size - Size to check. + * max - Maximum desired value for \p size. + * + * Returned Value: + * \c 0 if `size <= max`, \c 1 if `size > max`. + * + ****************************************************************************/ + +static unsigned size_greater_than(size_t size, size_t max) +{ + /* Return the sign bit (1 for negative) of (max - size). */ + + return ((max - size) >> (sizeof(size_t) * 8 - 1)); +} + +/**************************************************************************** + * Name: if_int + * + * Description: + * Choose between two integer values, without branches. + * + * Input Parameters: + * cond - Condition to test. + * if1 - Value to use if \p cond is nonzero. + * if0 - Value to use if \p cond is zero. + * + * Returned Value: + * \c if1 if \p cond is nonzero, otherwise \c if0. + * + ****************************************************************************/ + +static unsigned if_int(unsigned cond, unsigned if1, unsigned if0) +{ + unsigned mask = all_or_nothing_int(cond); + return ((mask & if1) | (~mask & if0)); +} + +/**************************************************************************** + * Name: mem_move_to_left + * + * Description: + * Shift some data towards the left inside a buffer without leaking + * the length of the data through side channels. + * + * Input Parameters: + * start - Pointer to the start of the buffer. + * total - Total size of the buffer. + * offset - Offset from which to copy bytes. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void mem_move_to_left(void *start, + size_t total, + size_t offset) +{ + volatile unsigned char *buf = start; + size_t i; + size_t n; + if (total == 0) + { + return; + } + + for (i = 0; i < total; i++) + { + unsigned no_op = size_greater_than(total - offset, i); + for (n = 0; n < total - 1; n++) + { + unsigned char current = buf[n]; + unsigned char next = buf[n + 1]; + buf[n] = if_int(no_op, current, next); + } + + buf[total - 1] = if_int(no_op, buf[total - 1], 0); + } +} + +/* Implementation of the PKCS#1 v2.1 RSAES-PKCS1-V1_5-DECRYPT function */ + +static int esp32c3_rsa_pkcs1_v15_decrypt(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len) +{ + int ret; + size_t ilen; + size_t i; + size_t plaintext_max_size; + unsigned char buf[ESP32C3_MPI_MAX_SIZE]; + size_t pad_count = 0; + unsigned bad = 0; + unsigned char pad_done = 0; + size_t plaintext_size = 0; + unsigned output_too_large; + + DEBUGASSERT(ctx != NULL); + DEBUGASSERT(mode == ESP32C3_RSA_PRIVATE || + mode == ESP32C3_RSA_PUBLIC); + DEBUGASSERT(output_max_len == 0 || output != NULL); + DEBUGASSERT(input != NULL); + DEBUGASSERT(olen != NULL); + + ilen = ctx->len; + plaintext_max_size = (output_max_len > ilen - 11 ? + ilen - 11 : + output_max_len); + + if (mode == ESP32C3_RSA_PRIVATE && ctx->padding != ESP32C3_RSA_PKCS_V15) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + if (ilen < 16 || ilen > sizeof(buf)) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + ret = (mode == ESP32C3_RSA_PUBLIC) + ? esp32c3_rsa_public(ctx, input, buf) + : esp32c3_rsa_private(ctx, f_rng, p_rng, input, buf); + + if (ret != 0) + { + goto cleanup; + } + + /* Check and get padding length in constant time */ + + bad |= buf[0]; + + if (mode == ESP32C3_RSA_PRIVATE) + { + /* Decode EME-PKCS1-v1_5 padding */ + + bad |= buf[1] ^ ESP32C3_RSA_CRYPT; + + /* Read the whole buffer */ + + for (i = 2; i < ilen; i++) + { + pad_done |= ((buf[i] | (unsigned char)-buf[i]) >> 7) ^ 1; + pad_count += ((pad_done | (unsigned char)-pad_done) >> 7) ^ 1; + } + } + else + { + /* Decode EMSA-PKCS1-v1_5 padding */ + + bad |= buf[1] ^ ESP32C3_RSA_SIGN; + + /* Read the whole buffer */ + + for (i = 2; i < ilen; i++) + { + pad_done |= if_int(buf[i], 0, 1); + pad_count += if_int(pad_done, 0, 1); + bad |= if_int(pad_done, 0, buf[i] ^ 0xff); + } + } + + /* If pad_done is still zero, there's no data, only unfinished padding. */ + + bad |= if_int(pad_done, 0, 1); + + /* There must be at least 8 bytes of padding. */ + + bad |= size_greater_than(8, pad_count); + plaintext_size = if_int(bad, + (unsigned) plaintext_max_size, + (unsigned) (ilen - pad_count - 3)); + output_too_large = size_greater_than(plaintext_size, + plaintext_max_size); + + /* Set ret without branches to avoid timing attacks */ + + ret = - (int) if_int(bad, - ESP32C3_ERR_RSA_INVALID_PADDING, + if_int(output_too_large, - ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE, + 0)); + + /* If the padding is bad or the plaintext is too large, zero the data */ + + bad = all_or_nothing_int(bad | output_too_large); + for (i = 11; i < ilen; i++) + buf[i] &= ~bad; + + /* If the plaintext is too large, truncate it to the buffer size. */ + + plaintext_size = if_int(output_too_large, + (unsigned) plaintext_max_size, + (unsigned) plaintext_size); + + /* Move the plaintext to the leftmost position */ + + mem_move_to_left(buf + ilen - plaintext_max_size, + plaintext_max_size, + plaintext_max_size - plaintext_size); + + /* Copy the decrypted plaintext into the output buffer */ + + memcpy(output, buf + ilen - plaintext_max_size, plaintext_max_size); + + /* Report the amount of data we copied to the output buffer */ + + *olen = plaintext_size; + +cleanup: + memset(buf, 0, sizeof(buf)); + + return ret; +} +#endif /* ESP32C3_PKCS1_V15 */ + +/**************************************************************************** + * Name: esp32c3_rsa_deduce_primes + * + * Description: + * Compute RSA prime moduli P, Q from public modulus N=PQ + * and a pair of private and public key. + * + * Input Parameters: + * N - RSA modulus N = PQ, with P, Q to be found + * E - RSA public exponent + * D - RSA private exponent + * P - Pointer to MPI holding first prime factor of N on success + * Q - Pointer to MPI holding second prime factor of N on success + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_rsa_deduce_primes(struct esp32c3_mpi_s const *N, + struct esp32c3_mpi_s const *E, struct esp32c3_mpi_s const *D, + struct esp32c3_mpi_s *P, struct esp32c3_mpi_s *Q) +{ + int ret = 0; + + uint16_t attempt; /* Number of current attempt */ + uint16_t iter; /* Number of squares computed in the current attempt */ + + uint16_t order; /* Order of 2 in DE - 1 */ + + struct esp32c3_mpi_s T; /* Holds largest odd divisor of DE - 1 */ + struct esp32c3_mpi_s K; /* Temporary holding the current candidate */ + + const unsigned char primes[] = + { + 2, 3, 5, 7, 11, 13, 17, 19, 23, + 29, 31, 37, 41, 43, 47, 53, 59, + 61, 67, 71, 73, 79, 83, 89, 97, + 101, 103, 107, 109, 113, 127, 131, 137, + 139, 149, 151, 157, 163, 167, 173, 179, + 181, 191, 193, 197, 199, 211, 223, 227, + 229, 233, 239, 241, 251 + }; + + const size_t num_primes = sizeof(primes) / sizeof(*primes); + + if (P == NULL || Q == NULL || P->p != NULL || Q->p != NULL) + { + return (ESP32C3_ERR_MPI_BAD_INPUT_DATA); + } + + if (esp32c3_mpi_cmp_int(N, 0) <= 0 || + esp32c3_mpi_cmp_int(D, 1) <= 0 || + esp32c3_mpi_cmp_mpi(D, N) >= 0 || + esp32c3_mpi_cmp_int(E, 1) <= 0 || + esp32c3_mpi_cmp_mpi(E, N) >= 0) + { + return (ESP32C3_ERR_MPI_BAD_INPUT_DATA); + } + + /* Initializations and temporary changes */ + + esp32c3_mpi_init(&K); + esp32c3_mpi_init(&T); + + /* T := DE - 1 */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&T, D, E), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&T, &T, 1), cleanup); + + if ((order = (uint16_t) esp32c3_mpi_lsb(&T)) == 0) + { + ret = ESP32C3_ERR_MPI_BAD_INPUT_DATA; + goto cleanup; + } + + /* After this operation, T holds the largest odd divisor of DE - 1. */ + + ESP32C3_MPI_CHK(esp32c3_mpi_shift_r(&T, order), cleanup); + + /* Skip trying 2 if N == 1 mod 8 */ + + attempt = 0; + if (N->p[0] % 8 == 1) + { + attempt = 1; + } + + for (; attempt < num_primes; ++attempt) + { + esp32c3_mpi_lset(&K, primes[attempt]); + + /* Check if gcd(K,N) = 1 */ + + ESP32C3_MPI_CHK(esp32c3_mpi_gcd(P, &K, N), cleanup); + if (esp32c3_mpi_cmp_int(P, 1) != 0) + { + continue; + } + + /* Go through K^T + 1, K^(2T) + 1, K^(4T) + 1, ... */ + + ESP32C3_MPI_CHK(esp32c3_mpi_exp_mod(&K, &K, &T, N, Q), cleanup); + + for (iter = 1; iter <= order; ++iter) + { + /* Continuing to square K */ + + if (esp32c3_mpi_cmp_int(&K, 1) == 0) + { + break; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_add_int(&K, &K, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_gcd(P, &K, N), cleanup); + + if (esp32c3_mpi_cmp_int(P, 1) == 1 && + esp32c3_mpi_cmp_mpi(P, N) == -1) + { + /* Q := N / P */ + + ESP32C3_MPI_CHK(esp32c3_mpi_div_mpi(Q, NULL, N, P), cleanup); + goto cleanup; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, &K, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&K, &K, &K), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&K, &K, N), cleanup); + } + + if (esp32c3_mpi_cmp_int(&K, 1) != 0) + { + break; + } + } + + ret = ESP32C3_ERR_MPI_BAD_INPUT_DATA; + +cleanup: + + esp32c3_mpi_free(&K); + esp32c3_mpi_free(&T); + return ret; +} + +/**************************************************************************** + * Name: esp32c3_rsa_deduce_private_exponent + * + * Description: + * Compute RSA private exponent from prime moduli and public key. + * + * Input Parameters: + * P First prime factor of RSA modulus + * Q Second prime factor of RSA modulus + * E RSA public exponent + * D Pointer to MPI holding the private exponent on success. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_rsa_deduce_private_exponent(struct esp32c3_mpi_s const *P, + struct esp32c3_mpi_s const *Q, + struct esp32c3_mpi_s const *E, + struct esp32c3_mpi_s *D) +{ + int ret = 0; + struct esp32c3_mpi_s K; + struct esp32c3_mpi_s L; + + if (D == NULL || esp32c3_mpi_cmp_int(D, 0) != 0) + { + return (ESP32C3_ERR_MPI_BAD_INPUT_DATA); + } + + if (esp32c3_mpi_cmp_int(P, 1) <= 0 || + esp32c3_mpi_cmp_int(Q, 1) <= 0 || + esp32c3_mpi_cmp_int(E, 0) == 0) + { + return (ESP32C3_ERR_MPI_BAD_INPUT_DATA); + } + + esp32c3_mpi_init(&K); + esp32c3_mpi_init(&L); + + /* Temporarily put K := P-1 and L := Q-1 */ + + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, P, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&L, Q, 1), cleanup); + + /* Temporarily put D := gcd(P-1, Q-1) */ + + ESP32C3_MPI_CHK(esp32c3_mpi_gcd(D, &K, &L), cleanup); + + /* K := LCM(P-1, Q-1) */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&K, &K, &L), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_div_mpi(&K, NULL, &K, D), cleanup); + + /* Compute modular inverse of E in LCM(P-1, Q-1) */ + + ESP32C3_MPI_CHK(esp32c3_mpi_inv_mod(D, E, &K), cleanup); + +cleanup: + + esp32c3_mpi_free(&K); + esp32c3_mpi_free(&L); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_rsa_validate_crt + * + * Description: + * Check validity of core RSA parameters + * + * Input Parameters: + * P - First prime factor of RSA modulus + * Q - Second prime factor of RSA modulus + * D - RSA private exponent + * DP - MPI to check for D modulo P-1 + * DQ - MPI to check for D modulo P-1 + * QP - MPI to check for the modular inverse of Q modulo P. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_rsa_validate_crt( + const struct esp32c3_mpi_s *P, + const struct esp32c3_mpi_s *Q, + const struct esp32c3_mpi_s *D, + const struct esp32c3_mpi_s *DP, + const struct esp32c3_mpi_s *DQ, + const struct esp32c3_mpi_s *QP) +{ + int ret = 0; + + struct esp32c3_mpi_s K; + struct esp32c3_mpi_s L; + + esp32c3_mpi_init(&K); + esp32c3_mpi_init(&L); + + /* Check that DP - D == 0 mod P - 1 */ + + if (DP != NULL) + { + if (P == NULL) + { + ret = ESP32C3_ERR_RSA_BAD_INPUT_DATA; + goto cleanup; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, P, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&L, DP, D), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&L, &L, &K), cleanup); + + if (esp32c3_mpi_cmp_int(&L, 0) != 0) + { + ret = ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + goto cleanup; + } + } + + /* Check that DQ - D == 0 mod Q - 1 */ + + if (DQ != NULL) + { + if (Q == NULL) + { + ret = ESP32C3_ERR_RSA_BAD_INPUT_DATA; + goto cleanup; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, Q, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&L, DQ, D), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&L, &L, &K), cleanup); + + if (esp32c3_mpi_cmp_int(&L, 0) != 0) + { + ret = ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + goto cleanup; + } + } + + /* Check that QP * Q - 1 == 0 mod P */ + + if (QP != NULL) + { + if (P == NULL || Q == NULL) + { + ret = ESP32C3_ERR_RSA_BAD_INPUT_DATA; + goto cleanup; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&K, QP, Q), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, &K, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&K, &K, P), cleanup); + if (esp32c3_mpi_cmp_int(&K, 0) != 0) + { + ret = ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + goto cleanup; + } + } + +cleanup: + + /* Wrap MPI error codes by RSA check failure error code */ + + if (ret != 0 && + ret != ESP32C3_ERR_RSA_KEY_CHECK_FAILED && + ret != ESP32C3_ERR_RSA_BAD_INPUT_DATA) + { + ret += ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + } + + esp32c3_mpi_free(&K); + esp32c3_mpi_free(&L); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_rsa_validate_params + * + * Description: + * Check validity of core RSA parameters + * + * Input Parameters: + * N - RSA modulus N = PQ + * P - First prime factor of N + * Q - Second prime factor of N + * D - RSA private exponent + * E - RSA public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_rsa_validate_params(const struct esp32c3_mpi_s *N, + const struct esp32c3_mpi_s *P, + const struct esp32c3_mpi_s *Q, + const struct esp32c3_mpi_s *D, + const struct esp32c3_mpi_s *E, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + int ret = 0; + struct esp32c3_mpi_s K; + struct esp32c3_mpi_s L; + + esp32c3_mpi_init(&K); + esp32c3_mpi_init(&L); + + /* Step 1: Check that 1 < N = P * Q */ + + if (P != NULL && Q != NULL && N != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&K, P, Q), cleanup); + if (esp32c3_mpi_cmp_int(N, 1) <= 0 || + esp32c3_mpi_cmp_mpi(&K, N) != 0) + { + ret = ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + goto cleanup; + } + } + + /* Step 2: Check and 1 < D, E < N if present */ + + if (N != NULL && D != NULL && E != NULL) + { + if (esp32c3_mpi_cmp_int(D, 1) <= 0 || + esp32c3_mpi_cmp_int(E, 1) <= 0 || + esp32c3_mpi_cmp_mpi(D, N) >= 0 || + esp32c3_mpi_cmp_mpi(E, N) >= 0) + { + ret = ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + goto cleanup; + } + } + + /* Step 3: Check that D, E are inverse modulo P-1 and Q-1 */ + + if (P != NULL && Q != NULL && D != NULL && E != NULL) + { + if (esp32c3_mpi_cmp_int(P, 1) <= 0 || + esp32c3_mpi_cmp_int(Q, 1) <= 0) + { + ret = ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + goto cleanup; + } + + /* Compute DE-1 mod P-1 */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&K, D, E), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, &K, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&L, P, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&K, &K, &L), cleanup); + if (esp32c3_mpi_cmp_int(&K, 0) != 0) + { + ret = ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + goto cleanup; + } + + /* Compute DE-1 mod Q-1 */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&K, D, E), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, &K, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&L, Q, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&K, &K, &L), cleanup); + if (esp32c3_mpi_cmp_int(&K, 0) != 0) + { + ret = ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + goto cleanup; + } + } + +cleanup: + + esp32c3_mpi_free(&K); + esp32c3_mpi_free(&L); + + /* Wrap MPI error codes by RSA check failure error code */ + + if (ret != 0 && ret != ESP32C3_ERR_RSA_KEY_CHECK_FAILED) + { + ret += ESP32C3_ERR_RSA_KEY_CHECK_FAILED; + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_rsa_deduce_crt + * + * Description: + * Generate RSA-CRT parameters + * + * Input Parameters: + * P - First prime factor of N + * Q - Second prime factor of N + * D - RSA private exponent + * DP - Output variable for D modulo P-1 + * DQ - Output variable for D modulo Q-1 + * QP - Output variable for the modular inverse of Q modulo P + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_rsa_deduce_crt(const struct esp32c3_mpi_s *P, + const struct esp32c3_mpi_s *Q, + const struct esp32c3_mpi_s *D, + struct esp32c3_mpi_s *DP, + struct esp32c3_mpi_s *DQ, + struct esp32c3_mpi_s *QP) +{ + int ret = 0; + struct esp32c3_mpi_s K; + esp32c3_mpi_init(&K); + + /* DP = D mod P-1 */ + + if (DP != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, P, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(DP, D, &K), cleanup); + } + + /* DQ = D mod Q-1 */ + + if (DQ != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&K, Q, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(DQ, D, &K), cleanup); + } + + /* QP = Q^{-1} mod P */ + + if (QP != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_inv_mod(QP, Q, P), cleanup); + } + +cleanup: + esp32c3_mpi_free(&K); + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_rsa_import + * + * Description: + * Imports a set of core parameters into an RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to store the parameters in + * N - The RSA modulus + * P - The first prime factor of \p N + * Q - The second prime factor of \p N + * D - The private exponent + * E - The public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_import(struct esp32c3_rsa_context_s *ctx, + const struct esp32c3_mpi_s *N, + const struct esp32c3_mpi_s *P, const struct esp32c3_mpi_s *Q, + const struct esp32c3_mpi_s *D, const struct esp32c3_mpi_s *E) +{ + int ret; + DEBUGASSERT(ctx != NULL); + + if ((N != NULL && (ret = esp32c3_mpi_copy(&ctx->N, N)) != 0) || + (P != NULL && (ret = esp32c3_mpi_copy(&ctx->P, P)) != 0) || + (Q != NULL && (ret = esp32c3_mpi_copy(&ctx->Q, Q)) != 0) || + (D != NULL && (ret = esp32c3_mpi_copy(&ctx->D, D)) != 0) || + (E != NULL && (ret = esp32c3_mpi_copy(&ctx->E, E)) != 0)) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA + ret); + } + + if (N != NULL) + { + ctx->len = esp32c3_mpi_size(&ctx->N); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_import_raw + * + * Description: + * Imports core RSA parameters into an RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to store the parameters in + * N - The RSA modulus + * NL - The Byte length of \p N + * P - The first prime factor of \p N + * PL - The Byte length of \p P + * Q - The second prime factor of \p N + * QL - The Byte length of \p Q + * D - The private exponent + * DL - The Byte length of \p D + * E - The public exponent + * EL - The Byte length of \p E + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_import_raw(struct esp32c3_rsa_context_s *ctx, + unsigned char const *N, size_t NL, + unsigned char const *P, size_t PL, + unsigned char const *Q, size_t QL, + unsigned char const *D, size_t DL, + unsigned char const *E, size_t EL) +{ + int ret = 0; + DEBUGASSERT(ctx != NULL); + + if (N != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_read_binary(&ctx->N, N, NL), cleanup); + ctx->len = esp32c3_mpi_size(&ctx->N); + } + + if (P != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_read_binary(&ctx->P, P, PL), cleanup); + } + + if (Q != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_read_binary(&ctx->Q, Q, QL), cleanup); + } + + if (D != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_read_binary(&ctx->D, D, DL), cleanup); + } + + if (E != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_read_binary(&ctx->E, E, EL), cleanup); + } + +cleanup: + + if (ret != 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA + ret); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_complete + * + * Description: + * Completes an RSA context from a set of imported core parameters. + * + * Input Parameters: + * ctx - The initialized RSA context holding imported parameters + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_complete(struct esp32c3_rsa_context_s *ctx) +{ + int ret = 0; + int have_n; + int have_p; + int have_q; + int have_d; + int have_e; +#if !defined(ESP32C3_RSA_NO_CRT) + int have_dp; + int have_dq; + int have_qp; +#endif + int n_missing; + int pq_missing; + int d_missing; + int is_pub; + int is_priv; + + DEBUGASSERT(ctx != NULL); + + have_n = (esp32c3_mpi_cmp_int(&ctx->N, 0) != 0); + have_p = (esp32c3_mpi_cmp_int(&ctx->P, 0) != 0); + have_q = (esp32c3_mpi_cmp_int(&ctx->Q, 0) != 0); + have_d = (esp32c3_mpi_cmp_int(&ctx->D, 0) != 0); + have_e = (esp32c3_mpi_cmp_int(&ctx->E, 0) != 0); + +#if !defined(ESP32C3_RSA_NO_CRT) + have_dp = (esp32c3_mpi_cmp_int(&ctx->DP, 0) != 0); + have_dq = (esp32c3_mpi_cmp_int(&ctx->DQ, 0) != 0); + have_qp = (esp32c3_mpi_cmp_int(&ctx->QP, 0) != 0); +#endif + + /* Check whether provided parameters are enough */ + + n_missing = have_p && have_q && have_d && have_e; + pq_missing = have_n && !have_p && !have_q && have_d && have_e; + d_missing = have_p && have_q && !have_d && have_e; + is_pub = have_n && !have_p && !have_q && !have_d && have_e; + + /* These three alternatives are mutually exclusive */ + + is_priv = n_missing || pq_missing || d_missing; + + if (!is_priv && !is_pub) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + /* Step 1: Deduce N if P, Q are provided */ + + if (!have_n && have_p && have_q) + { + if ((ret = esp32c3_mpi_mul_mpi(&ctx->N, &ctx->P, + &ctx->Q)) != 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA + ret); + } + + ctx->len = esp32c3_mpi_size(&ctx->N); + } + + /* Step 2: Deduce and verify all remaining core parameters */ + + if (pq_missing) + { + ret = esp32c3_rsa_deduce_primes(&ctx->N, &ctx->E, &ctx->D, + &ctx->P, &ctx->Q); + if (ret != 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA + ret); + } + } + else if (d_missing) + { + if ((ret = esp32c3_rsa_deduce_private_exponent(&ctx->P, &ctx->Q, + &ctx->E, &ctx->D)) != 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA + ret); + } + } + + /* Step 3: Deduce all additional parameters to RSA implementation */ + +#if !defined(ESP32C3_RSA_NO_CRT) + if (is_priv && ! (have_dp && have_dq && have_qp)) + { + ret = esp32c3_rsa_deduce_crt(&ctx->P, &ctx->Q, &ctx->D, + &ctx->DP, &ctx->DQ, &ctx->QP); + if (ret != 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA + ret); + } + } +#endif /* ESP32C3_RSA_NO_CRT */ + + /* Step 3: Basic sanity checks */ + + return (rsa_check_context(ctx, is_priv, 1)); +} + +/**************************************************************************** + * Name: esp32c3_rsa_export_raw + * + * Description: + * Eexports core parameters of an RSA key in raw big-endian binary format. + * + * Input Parameters: + * ctx - The initialized RSA context + * N - The Byte array to store the RSA modulus + * NL - The size of the buffer for the modulus + * P - The Byte array to hold the first prime factor of \p N + * PL - The size of the buffer for the first prime factor + * Q - The Byte array to hold the second prime factor of \p N + * QL - The size of the buffer for the second prime factor + * D - The Byte array to hold the private exponent + * DL - The size of the buffer for the private exponent + * E - The Byte array to hold the public exponent + * EL - The size of the buffer for the public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export_raw(const struct esp32c3_rsa_context_s *ctx, + unsigned char *N, size_t NL, + unsigned char *P, size_t PL, + unsigned char *Q, size_t QL, + unsigned char *D, size_t DL, + unsigned char *E, size_t EL) +{ + int ret = 0; + int is_priv; + DEBUGASSERT(ctx != NULL); + + /* Check if key is private or public */ + + is_priv = esp32c3_mpi_cmp_int(&ctx->N, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->P, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->Q, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->D, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->E, 0) != 0; + + if (!is_priv) + { + /* It can't try to export private parameters for a public key */ + + if (P != NULL || Q != NULL || D != NULL) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + } + + if (N != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_write_binary(&ctx->N, N, NL), cleanup); + } + + if (P != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_write_binary(&ctx->P, P, PL), cleanup); + } + + if (Q != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_write_binary(&ctx->Q, Q, QL), cleanup); + } + + if (D != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_write_binary(&ctx->D, D, DL), cleanup); + } + + if (E != NULL) + { + ESP32C3_MPI_CHK(esp32c3_mpi_write_binary(&ctx->E, E, EL), cleanup); + } + +cleanup: + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_rsa_export + * + * Description: + * Exports the core parameters of an RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * N - The MPI to hold the RSA modulus + * P - The MPI to hold the first prime factor of \p N + * Q - The MPI to hold the second prime factor of \p N + * D - The MPI to hold the private exponent + * E - The MPI to hold the public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export(const struct esp32c3_rsa_context_s *ctx, + struct esp32c3_mpi_s *N, + struct esp32c3_mpi_s *P, + struct esp32c3_mpi_s *Q, + struct esp32c3_mpi_s *D, + struct esp32c3_mpi_s *E) +{ + int ret; + int is_priv; + DEBUGASSERT(ctx != NULL); + + /* Check if key is private or public */ + + is_priv = + esp32c3_mpi_cmp_int(&ctx->N, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->P, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->Q, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->D, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->E, 0) != 0; + + if (!is_priv) + { + /* It can't try to export private parameters for a public key */ + + if (P != NULL || Q != NULL || D != NULL) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + } + + /* Export all requested core parameters. */ + + if ((N != NULL && (ret = esp32c3_mpi_copy(N, &ctx->N)) != 0) || + (P != NULL && (ret = esp32c3_mpi_copy(P, &ctx->P)) != 0) || + (Q != NULL && (ret = esp32c3_mpi_copy(Q, &ctx->Q)) != 0) || + (D != NULL && (ret = esp32c3_mpi_copy(D, &ctx->D)) != 0) || + (E != NULL && (ret = esp32c3_mpi_copy(E, &ctx->E)) != 0)) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_export_crt + * + * Description: + * Exports CRT parameters of a private RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * DP - The MPI to hold \c D modulo `P-1` + * DQ - The MPI to hold \c D modulo `Q-1` + * QP - The MPI to hold modular inverse of \c Q modulo \c P + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export_crt(const struct esp32c3_rsa_context_s *ctx, + struct esp32c3_mpi_s *DP, + struct esp32c3_mpi_s *DQ, + struct esp32c3_mpi_s *QP) +{ + int ret; + int is_priv; + DEBUGASSERT(ctx != NULL); + + /* Check if key is private or public */ + + is_priv = esp32c3_mpi_cmp_int(&ctx->N, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->P, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->Q, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->D, 0) != 0 && + esp32c3_mpi_cmp_int(&ctx->E, 0) != 0; + + if (!is_priv) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + +#if !defined(ESP32C3_RSA_NO_CRT) + /* Export all requested blinding parameters. */ + + if ((DP != NULL && (ret = esp32c3_mpi_copy(DP, &ctx->DP)) != 0) || + (DQ != NULL && (ret = esp32c3_mpi_copy(DQ, &ctx->DQ)) != 0) || + (QP != NULL && (ret = esp32c3_mpi_copy(QP, &ctx->QP)) != 0)) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA + ret); + } +#else + if ((ret = esp32c3_rsa_deduce_crt(&ctx->P, &ctx->Q, &ctx->D, + DP, DQ, QP)) != 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA + ret); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_init + * + * Description: + * Initializes an RSA context + * + * Input Parameters: + * ctx - The RSA context to initialize + * padding - The padding mode to use + * hash_id - The hash identifier of + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_init(struct esp32c3_rsa_context_s *ctx, + int padding, + int hash_id) +{ + DEBUGASSERT(ctx != NULL); + DEBUGASSERT(padding == ESP32C3_RSA_PKCS_V15 || + padding == ESP32C3_RSA_PKCS_V21); + + memset(ctx, 0, sizeof(struct esp32c3_rsa_context_s)); + + esp32c3_rsa_set_padding(ctx, padding, hash_id); +} + +/**************************************************************************** + * Name: esp32c3_rsa_set_padding + * + * Description: + * Sets padding for an already initialized RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to be configured + * padding - The padding mode to use + * hash_id - The hash identifier + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_set_padding(struct esp32c3_rsa_context_s *ctx, + int padding, int hash_id) +{ + DEBUGASSERT(ctx != NULL); + DEBUGASSERT(padding == ESP32C3_RSA_PKCS_V15 || + padding == ESP32C3_RSA_PKCS_V21); + + ctx->padding = padding; + ctx->hash_id = hash_id; +} + +/**************************************************************************** + * Name: esp32c3_rsa_get_len + * + * Description: + * Exports CRT parameters of a private RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * + * Returned Value: + * length of the RSA modulus in Bytes. + * + ****************************************************************************/ + +size_t esp32c3_rsa_get_len(const struct esp32c3_rsa_context_s *ctx) +{ + return (ctx->len); +} + +/**************************************************************************** + * Name: esp32c3_rsa_check_pubkey + * + * Description: + * checks if a context contains at least an RSA public key.. + * + * Input Parameters: + * ctx - The initialized RSA context to check + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_pubkey(const struct esp32c3_rsa_context_s *ctx) +{ + DEBUGASSERT(ctx != NULL); + + if (rsa_check_context(ctx, 0 /* public */, 0 /* no blinding */) != 0) + { + return (ESP32C3_ERR_RSA_KEY_CHECK_FAILED); + } + + if (esp32c3_mpi_bitlen(&ctx->N) < 128) + { + return (ESP32C3_ERR_RSA_KEY_CHECK_FAILED); + } + + if (esp32c3_mpi_get_bit(&ctx->E, 0) == 0 || + esp32c3_mpi_bitlen(&ctx->E) < 2 || + esp32c3_mpi_cmp_mpi(&ctx->E, &ctx->N) >= 0) + { + return (ESP32C3_ERR_RSA_KEY_CHECK_FAILED); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_check_privkey + * + * Description: + * Checks if a context contains at least an RSA private key + * and perform basic consistency checks. + * + * Input Parameters: + * ctx - The initialized RSA context to check + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_privkey(const struct esp32c3_rsa_context_s *ctx) +{ + DEBUGASSERT(ctx != NULL); + + if (esp32c3_rsa_check_pubkey(ctx) != 0 || + rsa_check_context(ctx, 1 /* private */, 1 /* blinding */) != 0) + { + return (ESP32C3_ERR_RSA_KEY_CHECK_FAILED); + } + + if (esp32c3_rsa_validate_params(&ctx->N, &ctx->P, &ctx->Q, + &ctx->D, &ctx->E, NULL, NULL) != 0) + { + return (ESP32C3_ERR_RSA_KEY_CHECK_FAILED); + } + +#if !defined(ESP32C3_RSA_NO_CRT) + else if (esp32c3_rsa_validate_crt(&ctx->P, &ctx->Q, &ctx->D, + &ctx->DP, &ctx->DQ, &ctx->QP) != 0) + { + return (ESP32C3_ERR_RSA_KEY_CHECK_FAILED); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_check_pub_priv + * + * Description: + * Checks a public-private RSA key pair. It checks each of the contexts, + * and makes sure they match. + * + * Input Parameters: + * pub - The initialized RSA context holding the public key + * prv - The initialized RSA context holding the private key + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_pub_priv(const struct esp32c3_rsa_context_s *pub, + const struct esp32c3_rsa_context_s *prv) +{ + DEBUGASSERT(pub != NULL); + DEBUGASSERT(prv != NULL); + + if (esp32c3_rsa_check_pubkey(pub) != 0 || + esp32c3_rsa_check_privkey(prv) != 0) + { + return (ESP32C3_ERR_RSA_KEY_CHECK_FAILED); + } + + if (esp32c3_mpi_cmp_mpi(&pub->N, &prv->N) != 0 || + esp32c3_mpi_cmp_mpi(&pub->E, &prv->E) != 0) + { + return (ESP32C3_ERR_RSA_KEY_CHECK_FAILED); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_public + * + * Description: + * Performs an RSA public key operation. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * input - The input buffer + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_public(struct esp32c3_rsa_context_s *ctx, + const unsigned char *input, + unsigned char *output) +{ + int ret; + size_t olen; + struct esp32c3_mpi_s T; + DEBUGASSERT(ctx != NULL); + DEBUGASSERT(input != NULL); + DEBUGASSERT(output != NULL); + + if (rsa_check_context(ctx, 0 /* public */, 0 /* no blinding */)) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + esp32c3_mpi_init(&T); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_binary(&T, input, ctx->len), cleanup); + + if (esp32c3_mpi_cmp_mpi(&T, &ctx->N) >= 0) + { + ret = ESP32C3_ERR_MPI_BAD_INPUT_DATA; + goto cleanup; + } + + olen = ctx->len; + ESP32C3_MPI_CHK(esp32c3_mpi_exp_mod(&T, &T, &ctx->E, &ctx->N, &ctx->RN), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_write_binary(&T, output, olen), cleanup); + +cleanup: + esp32c3_mpi_free(&T); + + if (ret != 0) + { + return (ESP32C3_ERR_RSA_PUBLIC_FAILED + ret); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_private + * + * Description: + * Performs an RSA private key operation. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG function + * p_rng - The RNG context to pass to \p f_rng + * input - The input buffer + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_private(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *input, + unsigned char *output) +{ + int ret; + size_t olen; + + /* Temporary holding the result */ + + struct esp32c3_mpi_s T; + + /* Temporaries holding P-1, Q-1 and the exponent blinding factor */ + + struct esp32c3_mpi_s P1, Q1, R; + +#if !defined(ESP32C3_RSA_NO_CRT) + /* Temporaries holding the results mod p resp. mod q. */ + + struct esp32c3_mpi_s TP, TQ; + + /* Temporaries holding the blinded exponents */ + + struct esp32c3_mpi_s dp_blind, dq_blind; + + /* Pointers to actual exponents to be used */ + + struct esp32c3_mpi_s *DP = &ctx->DP; + struct esp32c3_mpi_s *DQ = &ctx->DQ; +#else + /* Temporary holding the blinded exponent */ + + struct esp32c3_mpi_s d_blind; + + /* Pointer to actual exponent to be used */ + + struct esp32c3_mpi_s *D = &ctx->D; +#endif /* ESP32C3_RSA_NO_CRT */ + + /* Temporaries holding the initial input */ + + struct esp32c3_mpi_s I, C; + + DEBUGASSERT(ctx != NULL); + DEBUGASSERT(input != NULL); + DEBUGASSERT(output != NULL); + + if (rsa_check_context(ctx, 1, f_rng != NULL) != 0) + { + return (ESP32C3_ERR_RSA_BAD_INPUT_DATA); + } + + /* MPI Initialization */ + + esp32c3_mpi_init(&T); + + esp32c3_mpi_init(&P1); + esp32c3_mpi_init(&Q1); + esp32c3_mpi_init(&R); + + if (f_rng != NULL) + { +#if defined(ESP32C3_RSA_NO_CRT) + esp32c3_mpi_init(&d_blind); +#else + esp32c3_mpi_init(&dp_blind); + esp32c3_mpi_init(&dq_blind); +#endif + } + +#if !defined(ESP32C3_RSA_NO_CRT) + esp32c3_mpi_init(&TP); esp32c3_mpi_init(&TQ); +#endif + + esp32c3_mpi_init(&I); + esp32c3_mpi_init(&C); + + /* End of MPI initialization */ + + ESP32C3_MPI_CHK(esp32c3_mpi_read_binary(&T, input, ctx->len), cleanup); + if (esp32c3_mpi_cmp_mpi(&T, &ctx->N) >= 0) + { + ret = ESP32C3_ERR_MPI_BAD_INPUT_DATA; + goto cleanup; + } + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&I, &T), cleanup); + + if (f_rng != NULL) + { + /* Blinding T = T * VI mod N */ + + ESP32C3_MPI_CHK(rsa_prepare_blinding(ctx, f_rng, p_rng), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&T, &T, &ctx->VI), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&T, &T, &ctx->N), cleanup); + + /* Exponent blinding */ + + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&P1, &ctx->P, 1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_sub_int(&Q1, &ctx->Q, 1), cleanup); + +#if defined(ESP32C3_RSA_NO_CRT) + /* d_blind = (P - 1) * (Q - 1) * R + D */ + + ESP32C3_MPI_CHK(esp32c3_mpi_fill_random(&R, RSA_EXPONENT_BLINDING, + f_rng, p_rng), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&d_blind, &P1, &Q1), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&d_blind, &d_blind, &R), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(&d_blind, &d_blind, &ctx->D), + cleanup); + + D = &d_blind; +#else + /* dp_blind = (P - 1) * R + DP */ + + ESP32C3_MPI_CHK(esp32c3_mpi_fill_random(&R, RSA_EXPONENT_BLINDING, + f_rng, p_rng), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&dp_blind, &P1, &R), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(&dp_blind, &dp_blind, + &ctx->DP), cleanup); + + DP = &dp_blind; + + /* dq_blind = (Q - 1) * R + DQ */ + + ESP32C3_MPI_CHK(esp32c3_mpi_fill_random(&R, RSA_EXPONENT_BLINDING, + f_rng, p_rng), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&dq_blind, &Q1, &R), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(&dq_blind, &dq_blind, + &ctx->DQ), cleanup); + + DQ = &dq_blind; +#endif /* ESP32C3_RSA_NO_CRT */ + } + +#if defined(ESP32C3_RSA_NO_CRT) + ESP32C3_MPI_CHK(esp32c3_mpi_exp_mod(&T, &T, D, &ctx->N, &ctx->RN), + cleanup); +#else + /* TP = input ^ dP mod P and TQ = input ^ dQ mod Q */ + + ESP32C3_MPI_CHK(esp32c3_mpi_exp_mod(&TP, &T, DP, &ctx->P, &ctx->RP), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_exp_mod(&TQ, &T, DQ, &ctx->Q, &ctx->RQ), + cleanup); + + /* T = (TP - TQ) * (Q^-1 mod P) mod P */ + + ESP32C3_MPI_CHK(esp32c3_mpi_sub_mpi(&T, &TP, &TQ), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&TP, &T, &ctx->QP), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&T, &TP, &ctx->P), cleanup); + + /* T = TQ + T * Q */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&TP, &T, &ctx->Q), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_add_mpi(&T, &TQ, &TP), cleanup); +#endif /* ESP32C3_RSA_NO_CRT */ + + if (f_rng != NULL) + { + /* Unblind T = T * VF mod N */ + + ESP32C3_MPI_CHK(esp32c3_mpi_mul_mpi(&T, &T, &ctx->VF), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_mod_mpi(&T, &T, &ctx->N), cleanup); + } + + /* Verify the result to prevent glitching attacks. */ + + ESP32C3_MPI_CHK(esp32c3_mpi_exp_mod(&C, &T, &ctx->E, + &ctx->N, &ctx->RN), cleanup); + if (esp32c3_mpi_cmp_mpi(&C, &I) != 0) + { + ret = ESP32C3_ERR_RSA_VERIFY_FAILED; + goto cleanup; + } + + olen = ctx->len; + ESP32C3_MPI_CHK(esp32c3_mpi_write_binary(&T, output, olen), cleanup); + +cleanup: + esp32c3_mpi_free(&P1); + esp32c3_mpi_free(&Q1); + esp32c3_mpi_free(&R); + + if (f_rng != NULL) + { +#if defined(ESP32C3_RSA_NO_CRT) + esp32c3_mpi_free(&d_blind); +#else + esp32c3_mpi_free(&dp_blind); + esp32c3_mpi_free(&dq_blind); +#endif + } + + esp32c3_mpi_free(&T); + +#if !defined(ESP32C3_RSA_NO_CRT) + esp32c3_mpi_free(&TP); esp32c3_mpi_free(&TQ); +#endif + + esp32c3_mpi_free(&C); + esp32c3_mpi_free(&I); + + if (ret != 0) + { + return (ESP32C3_ERR_RSA_PRIVATE_FAILED + ret); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_rsa_encrypt + * + * Description: + * Adds the message padding, then performs an RSA operation. It is the + * generic wrapper for performing a PKCS#1 encryption operation using the + * \p mode from the context. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG to use + * p_rng - The RNG context to be passed to \p f_rng + * mode - The mode of operation + * ilen - The length of the plaintext in Bytes + * input - The input data to encrypt + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_encrypt(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output) +{ + DEBUGASSERT(ctx != NULL); + DEBUGASSERT(mode == ESP32C3_RSA_PRIVATE || + mode == ESP32C3_RSA_PUBLIC); + DEBUGASSERT(output != NULL); + DEBUGASSERT(input != NULL); + + switch (ctx->padding) + { +#if defined(ESP32C3_PKCS1_V15) + case ESP32C3_RSA_PKCS_V15: + return esp32c3_rsa_pkcs1_v15_encrypt(ctx, f_rng, p_rng, mode, ilen, + input, output); +#endif + default: + return (ESP32C3_ERR_RSA_INVALID_PADDING); + } +} + +/**************************************************************************** + * Name: esp32c3_rsa_decrypt + * + * Description: + * Performs an RSA operation, then removes the message padding. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG function + * p_rng - The RNG context to be passed to \p f_rng + * mode - The mode of operation + * olen - The point which to store the length of the plaintext + * input - The ciphertext buffer + * output - The buffer used to hold the plaintext + * output_max_len - The length in Bytes of the output buffer \p output + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_decrypt(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len) +{ + DEBUGASSERT(ctx != NULL); + DEBUGASSERT(mode == ESP32C3_RSA_PRIVATE || + mode == ESP32C3_RSA_PUBLIC); + DEBUGASSERT(output_max_len == 0 || output != NULL); + DEBUGASSERT(input != NULL); + DEBUGASSERT(olen != NULL); + + switch (ctx->padding) + { +#if defined(ESP32C3_PKCS1_V15) + case ESP32C3_RSA_PKCS_V15: + return esp32c3_rsa_pkcs1_v15_decrypt(ctx, f_rng, p_rng, mode, olen, + input, output, output_max_len); +#endif + default: + return (ESP32C3_ERR_RSA_INVALID_PADDING); + } +} + +/**************************************************************************** + * Name: esp32c3_rsa_copy + * + * Description: + * Copies the components of an RSA context. + * + * Input Parameters: + * dst - The destination context + * src - The source context + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_copy(struct esp32c3_rsa_context_s *dst, + const struct esp32c3_rsa_context_s *src) +{ + int ret; + DEBUGASSERT(dst != NULL); + DEBUGASSERT(src != NULL); + + dst->ver = src->ver; + dst->len = src->len; + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->N, &src->N), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->E, &src->E), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->D, &src->D), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->P, &src->P), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->Q, &src->Q), cleanup); + +#if !defined(ESP32C3_RSA_NO_CRT) + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->DP, &src->DP), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->DQ, &src->DQ), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->QP, &src->QP), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->RP, &src->RP), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->RQ, &src->RQ), cleanup); +#endif + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->RN, &src->RN), cleanup); + + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->VI, &src->VI), cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_copy(&dst->VF, &src->VF), cleanup); + + dst->padding = src->padding; + dst->hash_id = src->hash_id; + +cleanup: + if (ret != 0) + { + esp32c3_rsa_free(dst); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_rsa_free + * + * Description: + * Frees the components of an RSA key. + * + * Input Parameters: + * ctx - The RSA context to free + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_free(struct esp32c3_rsa_context_s *ctx) +{ + if (ctx == NULL) + { + return; + } + + esp32c3_mpi_free(&ctx->VI); + esp32c3_mpi_free(&ctx->VF); + esp32c3_mpi_free(&ctx->RN); + esp32c3_mpi_free(&ctx->D); + esp32c3_mpi_free(&ctx->Q); + esp32c3_mpi_free(&ctx->P); + esp32c3_mpi_free(&ctx->E); + esp32c3_mpi_free(&ctx->N); + +#if !defined(ESP32C3_RSA_NO_CRT) + esp32c3_mpi_free(&ctx->RQ); + esp32c3_mpi_free(&ctx->RP); + esp32c3_mpi_free(&ctx->QP); + esp32c3_mpi_free(&ctx->DQ); + esp32c3_mpi_free(&ctx->DP); +#endif /* ESP32C3_RSA_NO_CRT */ +} + +#endif + +/**************************************************************************** + * Test Functions + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_RSA_ACCELERATOR_TEST + +/* Example RSA-1024 keypair, for test purposes */ + +#define KEY_LEN 128 + +#define RSA_N "9292758453063D803DD603D5E777D788" \ + "8ED1D5BF35786190FA2F23EBC0848AEA" \ + "DDA92CA6C3D80B32C4D109BE0F36D6AE" \ + "7130B9CED7ACDF54CFC7555AC14EEBAB" \ + "93A89813FBF3C4F8066D2D800F7C38A8" \ + "1AE31942917403FF4946B0A83D3D3E05" \ + "EE57C6F5F5606FB5D4BC6CD34EE0801A" \ + "5E94BB77B07507233A0BC7BAC8F90F79" + +#define RSA_E "10001" + +#define RSA_D "24BF6185468786FDD303083D25E64EFC" \ + "66CA472BC44D253102F8B4A9D3BFA750" \ + "91386C0077937FE33FA3252D28855837" \ + "AE1B484A8A9A45F7EE8C0C634F99E8CD" \ + "DF79C5CE07EE72C7F123142198164234" \ + "CABB724CF78B8173B9F880FC86322407" \ + "AF1FEDFDDE2BEB674CA15F3E81A1521E" \ + "071513A1E85B5DFA031F21ECAE91A34D" + +#define RSA_P "C36D0EB7FCD285223CFB5AABA5BDA3D8" \ + "2C01CAD19EA484A87EA4377637E75500" \ + "FCB2005C5C7DD6EC4AC023CDA285D796" \ + "C3D9E75E1EFC42488BB4F1D13AC30A57" + +#define RSA_Q "C000DF51A7C77AE8D7C7370C1FF55B69" \ + "E211C2B9E5DB1ED0BF61D0D9899620F4" \ + "910E4168387E3C30AA1E00C339A79508" \ + "8452DD96A9A5EA5D9DCA68DA636032AF" + +#define PT_LEN 24 +#define RSA_PT "\xAA\xBB\xCC\x03\x02\x01\x00\xFF\xFF\xFF\xFF\xFF" \ + "\x11\x22\x33\x0A\x0B\x0C\xCC\xDD\xDD\xDD\xDD\xDD" + +#if defined(ESP32C3_PKCS1_V15) +static int myrand(void *rng_state, unsigned char *output, size_t len) +{ +#if !defined(__OpenBSD__) && !defined(__NetBSD__) + size_t i; + + if (rng_state != NULL) + rng_state = NULL; + + for (i = 0; i < len; ++i) + output[i] = rand(); +#else + if (rng_state != NULL) + rng_state = NULL; + + arc4random_buf(output, len); +#endif /* !OpenBSD && !NetBSD */ + + return OK; +} +#endif /* ESP32C3_PKCS1_V15 */ + +/* Checkup routine */ + +int esp32c3_rsa_self_test(int verbose) +{ + int ret = 0; +#if defined(ESP32C3_PKCS1_V15) + size_t len; + struct esp32c3_rsa_context_s rsa; + unsigned char rsa_plaintext[PT_LEN]; + unsigned char rsa_decrypted[PT_LEN]; + unsigned char rsa_ciphertext[KEY_LEN]; + + struct esp32c3_mpi_s K; + + esp32c3_mpi_init(&K); + esp32c3_rsa_init(&rsa, ESP32C3_RSA_PKCS_V15, 0); + + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&K, 16, RSA_N), cleanup); + ESP32C3_MPI_CHK(esp32c3_rsa_import(&rsa, &K, NULL, NULL, NULL, NULL), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&K, 16, RSA_P), cleanup); + ESP32C3_MPI_CHK(esp32c3_rsa_import(&rsa, NULL, &K, NULL, NULL, NULL), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&K, 16, RSA_Q), cleanup); + ESP32C3_MPI_CHK(esp32c3_rsa_import(&rsa, NULL, NULL, &K, NULL, NULL), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&K, 16, RSA_D), cleanup); + ESP32C3_MPI_CHK(esp32c3_rsa_import(&rsa, NULL, NULL, NULL, &K, NULL), + cleanup); + ESP32C3_MPI_CHK(esp32c3_mpi_read_string(&K, 16, RSA_E), cleanup); + ESP32C3_MPI_CHK(esp32c3_rsa_import(&rsa, NULL, NULL, NULL, NULL, &K), + cleanup); + + ESP32C3_MPI_CHK(esp32c3_rsa_complete(&rsa), cleanup); + + if (verbose != 0) + syslog(LOG_INFO, " RSA key validation: "); + + if (esp32c3_rsa_check_pubkey(&rsa) != 0 || + esp32c3_rsa_check_privkey(&rsa) != 0) + { + if (verbose != 0) + syslog(LOG_INFO, "failed\n"); + + ret = 1; + goto cleanup; + } + + if (verbose != 0) + syslog(LOG_INFO, "passed\n PKCS#1 encryption : "); + + memcpy(rsa_plaintext, RSA_PT, PT_LEN); + + if (esp32c3_rsa_encrypt(&rsa, myrand, NULL, ESP32C3_RSA_PUBLIC, + PT_LEN, rsa_plaintext, + rsa_ciphertext) != 0) + { + if (verbose != 0) + syslog(LOG_INFO, "failed\n"); + + ret = 1; + goto cleanup; + } + + if (verbose != 0) + syslog(LOG_INFO, "passed\n PKCS#1 decryption : "); + + if (esp32c3_rsa_decrypt(&rsa, myrand, NULL, ESP32C3_RSA_PRIVATE, + &len, rsa_ciphertext, rsa_decrypted, + sizeof(rsa_decrypted)) != 0) + { + if (verbose != 0) + syslog(LOG_INFO, "failed\n"); + + ret = 1; + goto cleanup; + } + + if (memcmp(rsa_decrypted, rsa_plaintext, len) != 0) + { + if (verbose != 0) + syslog(LOG_INFO, "failed\n"); + + ret = 1; + goto cleanup; + } + + if (verbose != 0) + syslog(LOG_INFO, "passed\n"); + +cleanup: + esp32c3_mpi_free(&K); + esp32c3_rsa_free(&rsa); +#else /* ESP32C3_PKCS1_V15 */ + ((void) verbose); +#endif /* ESP32C3_PKCS1_V15 */ + return ret; +} + +/**************************************************************************** + * Name: esp32c3_rsa_main + ****************************************************************************/ + +int esp32c3_rsa_main(int argc, char *argv[]) +{ + int ret = 0; + + syslog(LOG_INFO, "----- BEGIN TEST -----\n"); + + ret = esp32c3_mpi_self_test(true); + if (ret) + { + goto test_end; + } + + ret = esp32c3_rsa_self_test(true); + if (ret) + { + goto test_end; + } + +test_end: + syslog(LOG_INFO, "----- END TEST -----\n"); + + syslog(LOG_INFO, "\n"); + + syslog(LOG_INFO, "----- RESULT: %s -----\n", + !ret ? "SUCCESS" : "FAILED"); + + return 0; +} + +#endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_rsa.h b/arch/risc-v/src/esp32c3/esp32c3_rsa.h new file mode 100644 index 00000000000..cba4d767a35 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rsa.h @@ -0,0 +1,513 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rsa.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RSA_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RSA_H + +#include +#include +#include "esp32c3_bignum.h" + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* RSA Error codes */ + +#define ESP32C3_ERR_RSA_BAD_INPUT_DATA -0x4080 /**< Bad input parameters to function. */ +#define ESP32C3_ERR_RSA_INVALID_PADDING -0x4100 /**< Input data contains invalid padding and is rejected. */ +#define ESP32C3_ERR_RSA_KEY_GEN_FAILED -0x4180 /**< Something failed during generation of a key. */ +#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED -0x4200 /**< Key failed to pass the validity check of the library. */ +#define ESP32C3_ERR_RSA_PUBLIC_FAILED -0x4280 /**< The public key operation failed. */ +#define ESP32C3_ERR_RSA_PRIVATE_FAILED -0x4300 /**< The private key operation failed. */ +#define ESP32C3_ERR_RSA_VERIFY_FAILED -0x4380 /**< The PKCS#1 verification failed. */ +#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 /**< The output buffer for decryption is not large enough. */ +#define ESP32C3_ERR_RSA_RNG_FAILED -0x4480 /**< The random generator failed to generate non-zeros. */ + +/* RSA constants */ + +#define ESP32C3_RSA_PUBLIC 0 /**< Request private key operation. */ +#define ESP32C3_RSA_PRIVATE 1 /**< Request public key operation. */ + +#define ESP32C3_RSA_PKCS_V15 0 /**< Use PKCS#1 v1.5 encoding. */ +#define ESP32C3_RSA_PKCS_V21 1 /**< Use PKCS#1 v2.1 encoding. */ + +#define ESP32C3_RSA_SIGN 1 /**< Identifier for RSA signature operations. */ +#define ESP32C3_RSA_CRYPT 2 /**< Identifier for RSA encryption and decryption operations. */ + +#define ESP32C3_RSA_SALT_LEN_ANY -1 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/** + * \brief - The RSA context structure. + */ + +struct esp32c3_rsa_context_s +{ + int ver; /* Always 0 */ + size_t len; /* The size of \p N in Bytes */ + + struct esp32c3_mpi_s N; /* The public modulus */ + struct esp32c3_mpi_s E; /* The public exponent */ + + struct esp32c3_mpi_s D; /* The private exponent */ + struct esp32c3_mpi_s P; /* The first prime factor */ + struct esp32c3_mpi_s Q; /* The second prime factor */ + + struct esp32c3_mpi_s DP; /* D % (P - 1) */ + struct esp32c3_mpi_s DQ; /* D % (Q - 1) */ + struct esp32c3_mpi_s QP; /* 1 / (Q % P) */ + + struct esp32c3_mpi_s RN; /* cached R^2 mod N */ + + struct esp32c3_mpi_s RP; /* cached R^2 mod P */ + struct esp32c3_mpi_s RQ; /* cached R^2 mod Q */ + + struct esp32c3_mpi_s VI; /* The cached blinding value */ + struct esp32c3_mpi_s VF; /* The cached un-blinding value */ + + int padding; /* Selects padding mode */ + int hash_id; /* Hash identifier */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_rsa_init + * + * Description: + * Initializes an RSA context + * + * Input Parameters: + * ctx - The RSA context to initialize + * padding - The padding mode to use + * hash_id - The hash identifier of + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_init(struct esp32c3_rsa_context_s *ctx, + int padding, + int hash_id); + +/**************************************************************************** + * Name: esp32c3_rsa_import + * + * Description: + * Imports a set of core parameters into an RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to store the parameters in + * N - The RSA modulus + * P - The first prime factor of \p N + * Q - The second prime factor of \p N + * D - The private exponent + * E - The public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_import(struct esp32c3_rsa_context_s *ctx, + const struct esp32c3_mpi_s *N, + const struct esp32c3_mpi_s *P, + const struct esp32c3_mpi_s *Q, + const struct esp32c3_mpi_s *D, + const struct esp32c3_mpi_s *E); + +/**************************************************************************** + * Name: esp32c3_rsa_import_raw + * + * Description: + * Imports core RSA parameters into an RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to store the parameters in + * N - The RSA modulus + * NL - The Byte length of \p N + * P - The first prime factor of \p N + * PL - The Byte length of \p P + * Q - The second prime factor of \p N + * QL - The Byte length of \p Q + * D - The private exponent + * DL - The Byte length of \p D + * E - The public exponent + * EL - The Byte length of \p E + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_import_raw(struct esp32c3_rsa_context_s *ctx, + unsigned char const *N, size_t NL, + unsigned char const *P, size_t PL, + unsigned char const *Q, size_t QL, + unsigned char const *D, size_t DL, + unsigned char const *E, size_t EL); + +/**************************************************************************** + * Name: esp32c3_rsa_complete + * + * Description: + * Completes an RSA context from a set of imported core parameters. + * + * Input Parameters: + * ctx - The initialized RSA context holding imported parameters + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_complete(struct esp32c3_rsa_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_rsa_export + * + * Description: + * Exports the core parameters of an RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * N - The MPI to hold the RSA modulus + * P - The MPI to hold the first prime factor of \p N + * Q - The MPI to hold the second prime factor of \p N + * D - The MPI to hold the private exponent + * E - The MPI to hold the public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export(const struct esp32c3_rsa_context_s *ctx, + struct esp32c3_mpi_s *N, + struct esp32c3_mpi_s *P, + struct esp32c3_mpi_s *Q, + struct esp32c3_mpi_s *D, + struct esp32c3_mpi_s *E); + +/**************************************************************************** + * Name: esp32c3_rsa_export_raw + * + * Description: + * Eexports core parameters of an RSA key in raw big-endian binary format. + * + * Input Parameters: + * ctx - The initialized RSA context + * N - The Byte array to store the RSA modulus + * NL - The size of the buffer for the modulus + * P - The Byte array to hold the first prime factor of \p N + * PL - The size of the buffer for the first prime factor + * Q - The Byte array to hold the second prime factor of \p N + * QL - The size of the buffer for the second prime factor + * D - The Byte array to hold the private exponent + * DL - The size of the buffer for the private exponent + * E - The Byte array to hold the public exponent + * EL - The size of the buffer for the public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export_raw(const struct esp32c3_rsa_context_s *ctx, + unsigned char *N, size_t NL, + unsigned char *P, size_t PL, + unsigned char *Q, size_t QL, + unsigned char *D, size_t DL, + unsigned char *E, size_t EL); + +/**************************************************************************** + * Name: esp32c3_rsa_export_crt + * + * Description: + * Exports CRT parameters of a private RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * DP - The MPI to hold \c D modulo `P-1` + * DQ - The MPI to hold \c D modulo `Q-1` + * QP - The MPI to hold modular inverse of \c Q modulo \c P + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export_crt(const struct esp32c3_rsa_context_s *ctx, + struct esp32c3_mpi_s *DP, + struct esp32c3_mpi_s *DQ, + struct esp32c3_mpi_s *QP); + +/**************************************************************************** + * Name: esp32c3_rsa_set_padding + * + * Description: + * Sets padding for an already initialized RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to be configured + * padding - The padding mode to use + * hash_id - The hash identifier + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_set_padding(struct esp32c3_rsa_context_s *ctx, + int padding, int hash_id); + +/**************************************************************************** + * Name: esp32c3_rsa_get_len + * + * Description: + * Exports CRT parameters of a private RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * + * Returned Value: + * length of the RSA modulus in Bytes. + * + ****************************************************************************/ + +size_t esp32c3_rsa_get_len(const struct esp32c3_rsa_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_rsa_check_pubkey + * + * Description: + * checks if a context contains at least an RSA public key.. + * + * Input Parameters: + * ctx - The initialized RSA context to check + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_pubkey(const struct esp32c3_rsa_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_rsa_check_privkey + * + * Description: + * Checks if a context contains at least an RSA private key + * and perform basic consistency checks. + * + * Input Parameters: + * ctx - The initialized RSA context to check + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_privkey(const struct esp32c3_rsa_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_rsa_check_pub_priv + * + * Description: + * Checks a public-private RSA key pair. It checks each of the contexts, + * and makes sure they match. + * + * Input Parameters: + * pub - The initialized RSA context holding the public key + * prv - The initialized RSA context holding the private key + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_pub_priv(const struct esp32c3_rsa_context_s *pub, + const struct esp32c3_rsa_context_s *prv); + +/**************************************************************************** + * Name: esp32c3_rsa_public + * + * Description: + * Performs an RSA public key operation. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * input - The input buffer + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_public(struct esp32c3_rsa_context_s *ctx, + const unsigned char *input, + unsigned char *output); + +/**************************************************************************** + * Name: esp32c3_rsa_private + * + * Description: + * Performs an RSA private key operation. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG function + * p_rng - The RNG context to pass to \p f_rng + * input - The input buffer + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_private(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *input, + unsigned char *output); + +/**************************************************************************** + * Name: esp32c3_rsa_encrypt + * + * Description: + * Adds the message padding, then performs an RSA operation. It is the + * generic wrapper for performing a PKCS#1 encryption operation using the + * \p mode from the context. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG to use + * p_rng - The RNG context to be passed to \p f_rng + * mode - The mode of operation + * ilen - The length of the plaintext in Bytes + * input - The input data to encrypt + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_encrypt(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output); + +/**************************************************************************** + * Name: esp32c3_rsa_decrypt + * + * Description: + * Performs an RSA operation, then removes the message padding. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG function + * p_rng - The RNG context to be passed to \p f_rng + * mode - The mode of operation + * olen - The point which to store the length of the plaintext + * input - The ciphertext buffer + * output - The buffer used to hold the plaintext + * output_max_len - The length in Bytes of the output buffer \p output + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_decrypt(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len); + +/**************************************************************************** + * Name: esp32c3_rsa_copy + * + * Description: + * Copies the components of an RSA context. + * + * Input Parameters: + * dst - The destination context + * src - The source context + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_copy(struct esp32c3_rsa_context_s *dst, + const struct esp32c3_rsa_context_s *src); + +/**************************************************************************** + * Name: esp32c3_rsa_free + * + * Description: + * Frees the components of an RSA key. + * + * Input Parameters: + * ctx - The RSA context to free + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_free(struct esp32c3_rsa_context_s *ctx); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RSA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c index 4320d731854..47173539935 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c +++ b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c @@ -41,6 +41,7 @@ #include "hardware/esp32c3_soc.h" #include "esp32c3_tim.h" #include "esp32c3_rt_timer.h" +#include "esp32c3_attr.h" /**************************************************************************** * Pre-processor Definitions @@ -80,13 +81,13 @@ static struct esp32c3_tim_dev_s *s_esp32c3_tim_dev; * Name: start_rt_timer * * Description: - * Start timer by inserting it into running list and reset hardware timer - * alarm value if this timer in head of list. + * Start the timer by inserting it into the running list and reset the + * hardware timer alarm value if this timer is at the head of the list. * * Input Parameters: * timer - RT timer pointer * timeout - Timeout value - * repeat - If the timer run repeat + * repeat - repeat mode (true: enabled, false: disabled) * * Returned Value: * None. @@ -124,8 +125,8 @@ static void start_rt_timer(FAR struct rt_timer_s *timer, timer->flags &= ~RT_TIMER_REPEAT; } - /** Scan timer list and insert the new timer into previous - * node of timer whose alarm value is larger than new one + /* Scan the timer list and insert the new timer into previous + * node of timer whose alarm value is larger than new one */ list_for_every_entry(&s_runlist, p, struct rt_timer_s, list) @@ -138,7 +139,9 @@ static void start_rt_timer(FAR struct rt_timer_s *timer, } } - /* If not find a larger one, insert new timer into tail of list */ + /* If we didn't find a larger one, insert the new timer at the tail + * of the list. + */ if (!inserted) { @@ -147,11 +150,11 @@ static void start_rt_timer(FAR struct rt_timer_s *timer, timer->state = RT_TIMER_READY; - /* If this timer is in head of list */ + /* If this timer is at the head of the list */ if (timer == container_of(s_runlist.next, struct rt_timer_s, list)) { - /* Reset hardware timer alarm */ + /* Reset the hardware timer alarm */ ESP32C3_TIM_SETALRVL(tim, timer->alarm); ESP32C3_TIM_SETALRM(tim, true); @@ -165,8 +168,8 @@ static void start_rt_timer(FAR struct rt_timer_s *timer, * Name: stop_rt_timer * * Description: - * Stop timer by removing it from running list and reset hardware timer - * alarm value if this timer is in head of list. + * Stop the timer by removing it from the running list and reset the + * hardware timer alarm value if this timer is at the head of list. * * Input Parameters: * timer - RT timer pointer @@ -186,18 +189,17 @@ static void stop_rt_timer(FAR struct rt_timer_s *timer) flags = enter_critical_section(); - /** - * Function "start" can set timer to be repeat, and function "stop" - * should remove this feature although it is not in ready state. + /* "start" function can set the timer's repeat flag, and "stop" function + * should remove this flag. */ timer->flags &= ~RT_TIMER_REPEAT; - /* Only ready timer can be stopped */ + /* Only timers in "ready" state can be stopped */ if (timer->state == RT_TIMER_READY) { - /* Check if timer is in head of list */ + /* Check if the timer is at the head of the list */ if (timer == container_of(s_runlist.next, struct rt_timer_s, list)) { @@ -211,15 +213,15 @@ static void stop_rt_timer(FAR struct rt_timer_s *timer) list_delete(&timer->list); timer->state = RT_TIMER_IDLE; - /* If timer is in in head of list */ + /* If the timer is at the head of the list */ if (ishead) { - /* If list is not empty */ - if (!list_is_empty(&s_runlist)) { - /* Reset hardware timer alarm value to be next timer's */ + /* Set the value from the next timer as the new hardware timer + * alarm value. + */ next_timer = container_of(s_runlist.next, struct rt_timer_s, @@ -239,9 +241,9 @@ static void stop_rt_timer(FAR struct rt_timer_s *timer) * Name: delete_rt_timer * * Description: - * Delete timer by removing it from list, then set the timer's state - * to be "RT_TIMER_DELETE", inserting into work list to let rt-timer - * thread to delete it and free resource. + * Delete the timer by removing it from the list, then set the timer's + * state to "RT_TIMER_DELETE" and finally insert it into the work list + * to let the rt-timer's thread to delete it and free the resources. * * Input Parameters: * timer - RT timer pointer @@ -253,6 +255,7 @@ static void stop_rt_timer(FAR struct rt_timer_s *timer) static void delete_rt_timer(FAR struct rt_timer_s *timer) { + int ret; irqstate_t flags; flags = enter_critical_section(); @@ -273,6 +276,14 @@ static void delete_rt_timer(FAR struct rt_timer_s *timer) list_add_after(&s_toutlist, &timer->list); timer->state = RT_TIMER_DELETE; + /* Wake up the thread to process deleted timers */ + + ret = nxsem_post(&s_toutsem); + if (ret < 0) + { + tmrerr("ERROR: Failed to post sem ret=%d\n", ret); + } + exit: leave_critical_section(flags); } @@ -281,8 +292,8 @@ exit: * Name: rt_timer_thread * * Description: - * RT timer working thread, it wait for a timeout semaphore, scan - * the timeout list and process all timers in this list. + * RT timer working thread: Waits for a timeout semaphore, scans + * the timeout list and processes all the timers in the list. * * Input Parameters: * argc - Not used @@ -302,7 +313,7 @@ static int rt_timer_thread(int argc, FAR char *argv[]) while (1) { - /* Waiting for timers timeout */ + /* Waiting for all timers to time out */ ret = nxsem_wait(&s_toutsem); if (ret) @@ -311,15 +322,13 @@ static int rt_timer_thread(int argc, FAR char *argv[]) assert(0); } - /* Enter critical to check global timer timeout list */ - flags = enter_critical_section(); - /* Process all timers in list */ + /* Process all the timers in list */ while (!list_is_empty(&s_toutlist)) { - /* Get first timer in list */ + /* Get the first timer in the list */ timer = container_of(s_toutlist.next, struct rt_timer_s, list); @@ -327,16 +336,14 @@ static int rt_timer_thread(int argc, FAR char *argv[]) raw_state = timer->state; - /* Delete timer from list */ + /* Delete the timer from the list */ list_delete(&timer->list); - /* Set timer's state to be let it to able to restart by user */ + /* Set timer's state to idle so it can be restarted by the user. */ timer->state = RT_TIMER_IDLE; - /* Leave from critical to start to call "callback" function */ - leave_critical_section(flags); if (raw_state == RT_TIMER_TIMEOUT) @@ -348,13 +355,13 @@ static int rt_timer_thread(int argc, FAR char *argv[]) kmm_free(timer); } - /* Enter critical for next scanning list */ + /* Enter critical section for next scanning list */ flags = enter_critical_section(); if (raw_state == RT_TIMER_TIMEOUT) { - /* Check if timer is repeat */ + /* Check if the timer is in "repeat" mode */ if (timer->flags & RT_TIMER_REPEAT) { @@ -373,7 +380,7 @@ static int rt_timer_thread(int argc, FAR char *argv[]) * Name: rt_timer_isr * * Description: - * Hardware timer interrupt service function. + * Hardware timer interrupt service routine. * * Input Parameters: * irq - Not used @@ -387,23 +394,21 @@ static int rt_timer_thread(int argc, FAR char *argv[]) static int rt_timer_isr(int irq, void *context, void *arg) { + int ret; irqstate_t flags; struct rt_timer_s *timer; uint64_t alarm; uint64_t counter; + bool wake = false; struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev; /* Clear interrupt register status */ ESP32C3_TIM_ACKINT(tim); - /* Wake up thread to process timeout timers */ - - nxsem_post(&s_toutsem); - flags = enter_critical_section(); - /* Check if there is timer running */ + /* Check if there is a timer running */ if (!list_is_empty(&s_runlist)) { @@ -417,19 +422,19 @@ static int rt_timer_isr(int irq, void *context, void *arg) ESP32C3_TIM_GETCTR(tim, &counter); if (timer->alarm <= counter) { - /** - * Remove first timer in running list and add it into - * timeout list. + /* Remove the first timer from the running list and add it to + * the timeout list. * * Set the timer's state to be RT_TIMER_TIMEOUT to avoid - * other operation. + * other operations. */ list_delete(&timer->list); timer->state = RT_TIMER_TIMEOUT; list_add_after(&s_toutlist, &timer->list); + wake = true; - /* Check if thers is timer running */ + /* Check if there is a timer running */ if (!list_is_empty(&s_runlist)) { @@ -439,9 +444,23 @@ static int rt_timer_isr(int irq, void *context, void *arg) alarm = timer->alarm; ESP32C3_TIM_SETALRVL(tim, alarm); - ESP32C3_TIM_SETALRM(tim, true); } } + + /* If there is a timer in the list, the alarm should be enabled */ + + ESP32C3_TIM_SETALRM(tim, true); + } + + if (wake) + { + /* Wake up the thread to process timed-out timers */ + + ret = nxsem_post(&s_toutsem); + if (ret < 0) + { + tmrerr("ERROR: Failed to post sem ret=%d\n", ret); + } } leave_critical_section(flags); @@ -457,7 +476,7 @@ static int rt_timer_isr(int irq, void *context, void *arg) * Name: rt_timer_create * * Description: - * Create RT timer by into timer creation arguments + * Create a RT timer from the provided arguments. * * Input Parameters: * args - Input RT timer creation arguments @@ -495,12 +514,12 @@ int rt_timer_create(FAR const struct rt_timer_args_s *args, * Name: rt_timer_start * * Description: - * Start RT timer. + * Start the RT timer. * * Input Parameters: * timer - RT timer pointer * timeout - Timeout value - * repeat - If the timer run repeat + * repeat - repeat mode (true: enabled, false: disabled) * * Returned Value: * None @@ -520,7 +539,7 @@ void rt_timer_start(FAR struct rt_timer_s *timer, * Name: rt_timer_stop * * Description: - * Stop RT timer. + * Stop the RT timer. * * Input Parameters: * timer - RT timer pointer @@ -539,7 +558,7 @@ void rt_timer_stop(FAR struct rt_timer_s *timer) * Name: rt_timer_delete * * Description: - * Stop and delete RT timer. + * Stop and delete the RT timer. * * Input Parameters: * timer - RT timer pointer @@ -558,17 +577,17 @@ void rt_timer_delete(FAR struct rt_timer_s *timer) * Name: rt_timer_time_us * * Description: - * Get time of RT timer by microsecond. + * Get time of the RT timer in microseconds. * * Input Parameters: * None * * Returned Value: - * Time of RT timer by microsecond. + * Time of the RT timer in microseconds. * ****************************************************************************/ -uint64_t rt_timer_time_us(void) +uint64_t IRAM_ATTR rt_timer_time_us(void) { uint64_t counter; struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev; @@ -578,6 +597,74 @@ uint64_t rt_timer_time_us(void) return counter; } +/**************************************************************************** + * Name: rt_timer_get_alarm + * + * Description: + * Get the timestamp when the next timeout is expected to occur. + * + * Input Parameters: + * None + * + * Returned Value: + * Timestamp of the nearest timer event in microseconds. + * + ****************************************************************************/ + +uint64_t IRAM_ATTR rt_timer_get_alarm(void) +{ + irqstate_t flags; + uint64_t counter; + struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev; + uint64_t alarm_value = 0; + + flags = enter_critical_section(); + + ESP32C3_TIM_GETCTR(tim, &counter); + ESP32C3_TIM_GETALRVL(tim, &alarm_value); + + if (alarm_value <= counter) + { + alarm_value = 0; + } + else + { + alarm_value -= counter; + } + + leave_critical_section(flags); + + return alarm_value; +} + +/**************************************************************************** + * Name: rt_timer_calibration + * + * Description: + * Adjust current RT timer by a certain value. + * + * Input Parameters: + * time_us - adjustment to apply to the RT timer in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void IRAM_ATTR rt_timer_calibration(uint64_t time_us) +{ + uint64_t counter; + struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev; + irqstate_t flags; + + flags = enter_critical_section(); + ESP32C3_TIM_GETCTR(tim, &counter); + counter += time_us; + ESP32C3_TIM_SETCTR(tim, counter); + ESP32C3_TIM_RLD_NOW(tim); + leave_critical_section(flags); +} + /**************************************************************************** * Name: esp32c3_rt_timer_init * @@ -627,8 +714,7 @@ int esp32c3_rt_timer_init(void) flags = enter_critical_section(); - /** - * ESP32-C3 hardware timer configuration: + /* ESP32-C3 hardware timer configuration: * - 1 counter = 1us * - Counter increase mode * - Non-reload mode diff --git a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h index 3957483b9de..ff3b1591d4d 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h +++ b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h @@ -31,8 +31,16 @@ #include #include -#define RT_TIMER_NOFLAGS (0) /* Timer support no feature */ -#define RT_TIMER_REPEAT (1 << 0) /* Timer is repeat */ +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RT_TIMER_NOFLAGS (0) /* Timer supports no feature */ +#define RT_TIMER_REPEAT (1 << 0) /* Timer supports repeat mode */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ /** * RT timer state @@ -42,7 +50,7 @@ enum rt_timer_state_e { RT_TIMER_IDLE, /* Timer is not counting */ RT_TIMER_READY, /* Timer is counting */ - RT_TIMER_TIMEOUT, /* Timer is timeout */ + RT_TIMER_TIMEOUT, /* Timer timed out */ RT_TIMER_DELETE /* Timer is to be delete */ }; @@ -56,8 +64,8 @@ struct rt_timer_s uint64_t alarm; /* Timeout period */ void (*callback)(void *arg); /* Callback function */ void *arg; /* Private data */ - uint16_t flags; /* Support feature */ - enum rt_timer_state_e state; /* Mark if timer is started */ + uint16_t flags; /* Supported features */ + enum rt_timer_state_e state; /* Timer state */ struct list_node list; /* Working list */ }; @@ -80,11 +88,15 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + /**************************************************************************** * Name: rt_timer_create * * Description: - * Create RT timer by into timer creation arguments + * Create a RT timer from the provided arguments. * * Input Parameters: * args - Input RT timer creation arguments @@ -102,12 +114,12 @@ int rt_timer_create(const struct rt_timer_args_s *args, * Name: rt_timer_start * * Description: - * Start RT timer. + * Start the RT timer. * * Input Parameters: * timer - RT timer pointer * timeout - Timeout value - * repeat - If the timer run repeat + * repeat - repeat mode (true: enabled, false: disabled) * * Returned Value: * None @@ -122,7 +134,7 @@ void rt_timer_start(struct rt_timer_s *timer, * Name: rt_timer_stop * * Description: - * Stop RT timer. + * Stop the RT timer. * * Input Parameters: * timer - RT timer pointer @@ -138,7 +150,7 @@ void rt_timer_stop(struct rt_timer_s *timer); * Name: rt_timer_delete * * Description: - * Stop and delete RT timer. + * Stop and delete the RT timer. * * Input Parameters: * timer - RT timer pointer @@ -154,18 +166,50 @@ void rt_timer_delete(struct rt_timer_s *timer); * Name: rt_timer_time_us * * Description: - * Get time of RT timer by microsecond. + * Get time of the RT timer in microseconds. * * Input Parameters: * None * * Returned Value: - * Time of RT timer by microsecond. + * Time of the RT timer in microseconds. * ****************************************************************************/ uint64_t rt_timer_time_us(void); +/**************************************************************************** + * Name: rt_timer_get_alarm + * + * Description: + * Get the timestamp when the next timeout is expected to occur. + * + * Input Parameters: + * None + * + * Returned Value: + * Timestamp of the nearest timer event in microseconds. + * + ****************************************************************************/ + +uint64_t rt_timer_get_alarm(void); + +/**************************************************************************** + * Name: rt_timer_calibration + * + * Description: + * Adjust current RT timer by a certain value. + * + * Input Parameters: + * time_us - adjustment to apply to the RT timer in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void rt_timer_calibration(uint64_t time_us); + /**************************************************************************** * Name: esp32c3_rt_timer_init * diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc.c b/arch/risc-v/src/esp32c3/esp32c3_rtc.c new file mode 100644 index 00000000000..9f975f42853 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rtc.c @@ -0,0 +1,2680 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rtc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "riscv_arch.h" + +#include "hardware/esp32c3_rtccntl.h" +#include "hardware/esp32c3_soc.h" +#include "hardware/esp32c3_system.h" +#include "hardware/esp32c3_syscon.h" +#include "hardware/esp32c3_tim.h" +#include "hardware/apb_ctrl_reg.h" +#include "hardware/bb_reg.h" +#include "hardware/nrx_reg.h" +#include "hardware/fe_reg.h" +#include "hardware/regi2c_lp_bias.h" +#include "hardware/regi2c_dig_reg.h" +#include "hardware/regi2c_bbpll.h" +#include "hardware/regi2c_ctrl.h" +#include "hardware/extmem_reg.h" +#include "hardware/spi_mem_reg.h" + +#include "esp32c3_rtc.h" +#include "esp32c3_clockconfig.h" +#include "esp32c3_attr.h" +#include "esp32c3_rt_timer.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +#define STR2(X) #X +#define STR(X) STR2(X) + +#define MHZ (1000000) + +/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. + * The ideal value (assuming 32768 Hz frequency) + * is 1000000/32768*(2**19) = 16*10^6. + */ + +#define MIN_32K_XTAL_CAL_VAL 15000000L +#define DELAY_FAST_CLK_SWITCH 3 +#define DELAY_SLOW_CLK_SWITCH 300 +#define DELAY_8M_ENABLE 50 + +/* Indicates that this 32k oscillator gets input from external oscillator, + * rather than a crystal. + */ + +#define EXT_OSC_FLAG BIT(3) + +/* Number of cycles to wait from the 32k XTAL oscillator to + * consider it running. Larger values increase startup delay. + * Smaller values may cause false positive detection + * (i.e. oscillator runs for a few cycles and then stops). + */ + +#define SLOW_CLK_CAL_CYCLES 1024 + +#define RTC_FAST_CLK_FREQ_8M 8500000 + +/* With the default value of CK8M_DFREQ, + * 8M clock frequency is 8.5 MHz +/- 7%. + */ + +#define RTC_FAST_CLK_FREQ_APPROX 8500000 + +#define RTC_PLL_FREQ_320M 320 +#define RTC_PLL_FREQ_480M 480 + +#define RTC_SLOW_CLK_FREQ_90K 90000 +#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) +#define RTC_SLOW_CLK_FREQ_32K 32768 + +#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) + +/* Number of fractional bits in values returned by rtc_clk_cal */ + +#define RTC_CLK_CAL_FRACT 19 + +/* set sleep_init default param. */ + +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, + * RTC_CNTL_DBIAS_SLP, RTC_CNTL_DIG_DBIAS_WAK, + * RTC_CNTL_DIG_DBIAS_SLP values. Valid if RTC_CNTL_DBG_ATTEN is 0. + */ + +#define RTC_CNTL_DBIAS_SLP 0 +#define RTC_CNTL_DBIAS_0V90 13 +#define RTC_CNTL_DBIAS_0V95 16 +#define RTC_CNTL_DBIAS_1V00 18 +#define RTC_CNTL_DBIAS_1V05 20 +#define RTC_CNTL_DBIAS_1V10 23 +#define RTC_CNTL_DBIAS_1V15 25 +#define RTC_CNTL_DBIAS_1V20 28 +#define RTC_CNTL_DBIAS_1V25 30 +#define RTC_CNTL_DBIAS_1V30 31 + +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 + +/* Default initializer for esp32c3_rtc_sleep_config_s + * This initializer sets all fields to "reasonable" values + * (e.g. suggested for production use) based on a combination + * of RTC_SLEEP_PD_x flags. + */ + +#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ + .lslp_mem_inf_fpu = 0, \ + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ + .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ + .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ + .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ + .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ + .wdt_flashboot_mod_en = 0, \ + .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DBIAS_SLP, \ + .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_SLP, \ + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ + .deep_slp_reject = 1, \ + .light_slp_reject = 1 \ +}; + +#define X32K_CONFIG_DEFAULT() { \ + .dac = 3, \ + .dres = 3, \ + .dgm = 3, \ + .dbuf = 1, \ +} + +/* Initializer for struct esp32c3_rtc_sleep_pu_config_s + * which sets all flags to the same value + */ + +#define RTC_SLEEP_PU_CONFIG_ALL(val) {\ + .dig_fpu = (val), \ + .rtc_fpu = (val), \ + .cpu_fpu = (val), \ + .i2s_fpu = (val), \ + .bb_fpu = (val), \ + .nrx_fpu = (val), \ + .fe_fpu = (val), \ + .sram_fpu = (val), \ + .rom_ram_fpu = (val), \ +} + +#define RTC_INIT_CONFIG_DEFAULT() { \ + .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ + .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .bt_wait_cycles = OTHER_BLOCKS_WAIT, \ + .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \ +} + +/* Default initializer of struct esp32c3_rtc_config_s. + * This initializer sets all fields to "reasonable" values + * (e.g. suggested for production use). + */ + +#define RTC_CONFIG_DEFAULT() {\ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1, \ + .xtal_fpu = 0, \ + .bbpll_fpu = 0, \ + .cpu_waiti_clk_gate = 1, \ + .cali_ocode = 0\ +} + +#ifdef CONFIG_RTC_DRIVER +/* The magic data for the struct esp32c3_rtc_backup_s that is in RTC slow + * memory. + */ + +# define MAGIC_RTC_SAVE (UINT64_C(0x11223344556677)) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This is almost the same as esp32c3_rtc_slow_freq_e, except that we define + * an extra enum member for the external 32k oscillator. For convenience, + * lower 2 bits should correspond to esp32c3_rtc_slow_freq_e values. + */ + +enum esp32c3_slow_clk_sel_e +{ + /* Internal 90 kHz RC oscillator */ + + SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, + + /* External 32 kHz XTAL */ + + SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, + + /* Internal 8 MHz RC oscillator, divided by 256 */ + + SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, + + /* External 32k oscillator connected to 32K_XP pin */ + + SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG +}; + +/* RTC FAST_CLK frequency values */ + +enum esp32c3_rtc_fast_freq_e +{ + RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */ + RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */ +}; + +struct esp32c3_x32k_config_s +{ + uint32_t dac : 6; + uint32_t dres : 3; + uint32_t dgm : 3; + uint32_t dbuf: 1; +}; + +/* Power down flags for rtc_sleep_pd function */ + +struct esp32c3_rtc_sleep_pu_config_s +{ + uint32_t dig_fpu : 1; /* Set to 1 to power UP digital part in sleep */ + uint32_t rtc_fpu : 1; /* Set to 1 to power UP RTC memories in sleep */ + uint32_t cpu_fpu : 1; /* Set to 1 to power UP digital memories and + * CPU in sleep + */ + uint32_t i2s_fpu : 1; /* Set to 1 to power UP I2S in sleep */ + uint32_t bb_fpu : 1; /* Set to 1 to power UP WiFi in sleep */ + uint32_t nrx_fpu : 1; /* Set to 1 to power UP WiFi in sleep */ + uint32_t fe_fpu : 1; /* Set to 1 to power UP WiFi in sleep */ + uint32_t sram_fpu : 1; /* Set to 1 to power UP SRAM in sleep */ + uint32_t rom_ram_fpu : 1; /* Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep */ +}; + +struct esp32c3_rtc_init_config_s +{ + uint16_t wifi_powerup_cycles : 7; + uint16_t wifi_wait_cycles : 9; + uint16_t bt_powerup_cycles : 7; + uint16_t bt_wait_cycles : 9; + uint16_t cpu_top_powerup_cycles : 7; + uint16_t cpu_top_wait_cycles : 9; + uint16_t dg_wrap_powerup_cycles : 7; + uint16_t dg_wrap_wait_cycles : 9; + uint16_t dg_peri_powerup_cycles : 7; + uint16_t dg_peri_wait_cycles : 9; +}; + +/* RTC power and clock control initialization settings */ + +struct esp32c3_rtc_priv_s +{ + uint32_t ck8m_wait : 8; /* Number of rtc_fast_clk cycles to + * wait for 8M clock to be ready + */ + uint32_t xtal_wait : 8; /* Number of rtc_fast_clk cycles to + * wait for XTAL clock to be ready + */ + uint32_t pll_wait : 8; /* Number of rtc_fast_clk cycles to + * wait for PLL to be ready + */ + uint32_t clkctl_init : 1; /* Perform clock control related initialization */ + uint32_t pwrctl_init : 1; /* Perform power control related initialization */ + uint32_t rtc_dboost_fpd : 1; /* Force power down RTC_DBOOST */ + uint32_t xtal_fpu : 1; + uint32_t bbpll_fpu : 1; + uint32_t cpu_waiti_clk_gate : 1; + uint32_t cali_ocode : 1; /* Calibrate Ocode to make bangap voltage more precise. */ +}; + +/* sleep configuration for rtc_sleep_init function */ + +struct esp32c3_rtc_sleep_config_s +{ + uint32_t lslp_mem_inf_fpu : 1; /* force normal voltage in sleep mode */ + uint32_t rtc_mem_inf_follow_cpu : 1; /* keep low voltage in sleep mode */ + uint32_t rtc_fastmem_pd_en : 1; /* power down RTC fast memory */ + uint32_t rtc_slowmem_pd_en : 1; /* power down RTC slow memory */ + uint32_t rtc_peri_pd_en : 1; /* power down RTC peripherals */ + uint32_t wifi_pd_en : 1; /* power down WiFi */ + uint32_t bt_pd_en : 1; /* power down BT */ + uint32_t cpu_pd_en : 1; /* power down CPU, but not + * restart when lightsleep. + */ + uint32_t dig_peri_pd_en : 1; /* power down digital peripherals */ + uint32_t deep_slp : 1; /* power down digital domain */ + uint32_t wdt_flashboot_mod_en : 1; /* enable WDT flashboot mode */ + uint32_t dig_dbias_wak : 5; /* set bias for digital domain, + * in active mode + */ + uint32_t dig_dbias_slp : 5; /* set bias for digital domain, + * in sleep mode + */ + uint32_t rtc_dbias_wak : 5; /* set bias for RTC domain, in active mode */ + uint32_t rtc_dbias_slp : 5; /* set bias for RTC domain, in sleep mode */ + uint32_t vddsdio_pd_en : 1; /* power down VDDSDIO regulator */ + uint32_t deep_slp_reject : 1; + uint32_t light_slp_reject : 1; +}; + +#ifdef CONFIG_RTC_DRIVER + +#ifdef CONFIG_RTC_ALARM +struct alm_cbinfo_s +{ + struct rt_timer_s *alarm_hdl; /* Timer id point to here */ + volatile alm_callback_t ac_cb; /* Client callback function */ + volatile FAR void *ac_arg; /* Argument to pass with the callback function */ + uint64_t deadline_us; + uint8_t index; +}; +#endif + +struct esp32c3_rtc_backup_s +{ + uint64_t magic; + int64_t offset; /* Offset time from RTC HW value */ + int64_t reserved0; +}; + +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER + +/* Callback to use when the alarm expires */ + +#ifdef CONFIG_RTC_ALARM +static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; +#endif + +static RTC_DATA_ATTR struct esp32c3_rtc_backup_s rtc_saved_data; + +/* Saved data for persistent RTC time */ + +static struct esp32c3_rtc_backup_s *g_rtc_save; +static bool g_rt_timer_enabled = false; + +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_sleep_pu( + struct esp32c3_rtc_sleep_pu_config_s cfg); +static inline bool esp32c3_clk_val_is_valid(uint32_t val); +static uint32_t IRAM_ATTR esp32c3_rtc_clk_cal_internal( + enum esp32c3_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles); +static void IRAM_ATTR esp32c3_rtc_clk_32k_enable(bool enable); +static void IRAM_ATTR esp32c3_rtc_clk_8m_enable( + bool clk_8m_en, bool d256_en); +static uint32_t IRAM_ATTR esp32c3_rtc_clk_slow_freq_get_hz(void); +static void IRAM_ATTR esp32c3_select_rtc_slow_clk( + enum esp32c3_slow_clk_sel_e slow_clk); +static void IRAM_ATTR esp32c3_rtc_clk_fast_freq_set( + enum esp32c3_rtc_fast_freq_e fast_freq); +static uint32_t IRAM_ATTR esp32c3_rtc_sleep_finish(uint32_t + lslp_mem_inf_fpu); +static void IRAM_ATTR esp32c3_rtc_clk_apb_freq_update(uint32_t apb_freq); +static void IRAM_ATTR esp32c3_wait_dig_dbias_valid(uint64_t rtc_cycles); +static void IRAM_ATTR esp32c3_rtc_update_to_xtal(int freq, int div); +static void IRAM_ATTR esp32c3_rtc_clk_bbpll_disable(void); +static void IRAM_ATTR esp32c3_rtc_clk_set_xtal_wait(void); +static void IRAM_ATTR esp32c3_rtc_bbpll_configure( + enum esp32c3_rtc_xtal_freq_e xtal_freq, int pll_freq); +static void IRAM_ATTR esp32c3_rtc_clk_cpu_freq_to_8m(void); +static void IRAM_ATTR esp32c3_rtc_clk_cpu_freq_to_pll_mhz( + int cpu_freq_mhz); + +#ifdef CONFIG_RTC_DRIVER +static void IRAM_ATTR esp32c3_rt_cb_handler(FAR void *arg); +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +volatile bool g_rtc_enabled = false; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pauses execution for us microseconds */ + +extern void esp_rom_delay_us(uint32_t us); + +/* Set the real CPU ticks per us to the ets, so that ets_delay_us + * will be accurate. Call this function when CPU frequency is changed. + */ + +extern void ets_update_cpu_frequency(uint32_t ticks_per_us); + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_pu + * + * Description: + * Configure whether certain peripherals are powered down in deep sleep. + * + * Input Parameters: + * cfg - power down flags as esp32c3_rtc_sleep_pu_config_s structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_sleep_pu( + struct esp32c3_rtc_sleep_pu_config_s cfg) +{ + REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, + RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); + REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); + REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, + APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, + APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, + APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); + REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); + if (cfg.sram_fpu) + { + REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, + APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP); + } + else + { + REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, + APB_CTRL_SRAM_POWER_UP, 0); + } + + if (cfg.rom_ram_fpu) + { + REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, + APB_CTRL_ROM_POWER_UP, APB_CTRL_ROM_POWER_UP); + } + else + { + REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, + APB_CTRL_ROM_POWER_UP, 0); + } +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_fast_freq_set + * + * Description: + * Select source for RTC_FAST_CLK. + * + * Input Parameters: + * fast_freq - Clock source (one of enum esp32c3_rtc_fast_freq_e values) + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_clk_fast_freq_set( + enum esp32c3_rtc_fast_freq_e fast_freq) +{ + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, + RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); + esp_rom_delay_us(DELAY_FAST_CLK_SWITCH); +} + +/**************************************************************************** + * Name: esp32c3_clk_val_is_valid + * + * Description: + * Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are + * stored as two copies in lower and upper 16-bit halves. + * These are the routines to work with such a representation. + * + * Input Parameters: + * val - register value + * + * Returned Value: + * true: Valid register value. + * false: Invalid register value. + * + ****************************************************************************/ + +static inline bool esp32c3_clk_val_is_valid(uint32_t val) +{ + return (val & 0xffff) == ((val >> 16) & 0xffff) + && val != 0 && val != UINT32_MAX; +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cal_internal + * + * Description: + * Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio + * + * Input Parameters: + * cal_clk - which clock to calibrate + * slowclk_cycles - number of slow clock cycles to count. + * + * Returned Value: + * Number of XTAL clock cycles within the given number of slow clock cycles + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32c3_rtc_clk_cal_internal( + enum esp32c3_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles) +{ + uint32_t cal_val; + uint32_t expected_freq; + uint32_t us_time_estimate; + int dig_32k_xtal_state; + enum esp32c3_rtc_slow_freq_e slow_freq; + if (cal_clk == RTC_CAL_RTC_MUX) + { + slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, + RTC_CNTL_ANA_CLK_RTC_SEL); + if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) + { + cal_clk = RTC_CAL_32K_XTAL; + } + else if (slow_freq == RTC_SLOW_FREQ_8MD256) + { + cal_clk = RTC_CAL_8MD256; + } + } + + /* Enable requested clock (150k clock is always on) */ + + dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, + RTC_CNTL_DIG_XTAL32K_EN); + + if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) + { + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); + } + + if (cal_clk == RTC_CAL_8MD256) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_DIG_CLK8M_D256_EN); + } + + /* Prepare calibration */ + + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); + + /* There may be another calibration process already running during we + * call this function, so we should wait the last process is done. + */ + + if ((getreg32(TIMG_RTCCALICFG2_REG(0)) & TIMG_RTC_CALI_TIMEOUT) == 0) + { + if (getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_START_CYCLING) + { + while ((getreg32(TIMG_RTCCALICFG_REG(0)) & + TIMG_RTC_CALI_RDY) == 0); + } + } + + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING, 0); + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); + + /* Set timeout reg and expect time delay */ + + if (cal_clk == RTC_CAL_32K_XTAL) + { + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, + RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_32K; + } + else if (cal_clk == RTC_CAL_8MD256) + { + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, + RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_8MD256; + } + else + { + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, + RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_90K; + } + + us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * + MHZ / expected_freq); + + /* Start calibration */ + + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START, 0); + modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); + + /* Wait for calibration to finish up to another us_time_estimate */ + + esp_rom_delay_us(us_time_estimate); + while (1) + { + if (getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY) + { + cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), + TIMG_RTC_CALI_VALUE); + break; + } + + if (getreg32(TIMG_RTCCALICFG2_REG(0)) & TIMG_RTC_CALI_TIMEOUT) + { + cal_val = 0; + break; + } + } + + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START, 0); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, + RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state); + if (cal_clk == RTC_CAL_8MD256) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN, 0); + } + + return cal_val; +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_32k_enable + * + * Description: + * Enable or disable 32 kHz XTAL oscillator + * + * Input Parameters: + * enable - true to enable, false to disable + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_clk_32k_enable(bool enable) +{ + struct esp32c3_x32k_config_s cfg = X32K_CONFIG_DEFAULT(); + if (enable) + { + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, + RTC_CNTL_DAC_XTAL_32K, cfg.dac); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, + RTC_CNTL_DRES_XTAL_32K, cfg.dres); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, + RTC_CNTL_DGM_XTAL_32K, cfg.dgm); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, + RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf); + modifyreg32(RTC_CNTL_EXT_XTL_CONF_REG, 0, + RTC_CNTL_XPD_XTAL_32K); + } + else + { + modifyreg32(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K, + RTC_CNTL_XTAL32K_XPD_FORCE); + } +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_8m_enable + * + * Description: + * Enable or disable 8 MHz internal oscillator + * + * Input Parameters: + * clk_8m_en - true to enable 8MHz generator, false to disable + * d256_en - true to enable /256 divider, false to disable + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) +{ + if (clk_8m_en) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M, 0); + + /* no need to wait once enabled by software */ + + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, + RTC_CK8M_ENABLE_WAIT_DEFAULT); + esp_rom_delay_us(DELAY_8M_ENABLE); + } + else + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, + RTC_CNTL_CK8M_WAIT_DEFAULT); + } + + /* d256 should be independent configured with 8M + * Maybe we can split this function into 8m and dmd256 + */ + + if (d256_en) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV, 0); + } + else + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M_DIV); + } +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_slow_freq_get_hz + * + * Description: + * Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * Input Parameters: + * None + * + * Returned Value: + * slow_clk_freq - RTC_SLOW_CLK frequency, in Hz + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32c3_rtc_clk_slow_freq_get_hz(void) +{ + enum esp32c3_rtc_slow_freq_e slow_clk_freq = + esp32c3_rtc_clk_slow_freq_get(); + switch (slow_clk_freq) + { + case RTC_SLOW_FREQ_RTC: + return RTC_SLOW_CLK_FREQ_90K; + + case RTC_SLOW_FREQ_32K_XTAL: + return RTC_SLOW_CLK_FREQ_32K; + + case RTC_SLOW_FREQ_8MD256: + return RTC_SLOW_CLK_FREQ_8MD256; + } + + return 0; +} + +/**************************************************************************** + * Name: esp32c3_select_rtc_slow_clk + * + * Description: + * Selects an clock source for RTC. + * + * Input Parameters: + * slow_clk - RTC SLOW_CLK frequency values + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_select_rtc_slow_clk( + enum esp32c3_slow_clk_sel_e slow_clk) +{ + uint32_t cal_val = 0; + int retry_32k_xtal = 3; + uint64_t cal_dividend; + enum esp32c3_rtc_slow_freq_e rtc_slow_freq = slow_clk & + RTC_CNTL_ANA_CLK_RTC_SEL_V; + do + { + if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) + { + /* 32k XTAL oscillator needs to be enabled and running before + * it can be used. Hardware doesn't have a direct way of checking + * if the oscillator is running. Here we use rtc_clk_cal function + * to count the number of main XTAL cycles in the given number of + * 32k XTAL oscillator cycles. If the 32k XTAL has not started up, + * calibration will time out, returning 0. + */ + + if (slow_clk == SLOW_CLK_32K_XTAL || + slow_clk == SLOW_CLK_32K_EXT_OSC) + { + esp32c3_rtc_clk_32k_enable(true); + } + + if (SLOW_CLK_CAL_CYCLES > 0) + { + cal_val = esp32c3_rtc_clk_cal(RTC_CAL_32K_XTAL, + SLOW_CLK_CAL_CYCLES); + if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) + { + if (retry_32k_xtal-- > 0) + { + continue; + } + + rtc_slow_freq = RTC_SLOW_FREQ_RTC; + } + } + } + else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) + { + esp32c3_rtc_clk_8m_enable(true, true); + } + + esp32c3_rtc_clk_slow_freq_set(rtc_slow_freq); + if (SLOW_CLK_CAL_CYCLES > 0) + { + /* 32k XTAL oscillator has some frequency drift at startup. Improve + * calibration routine to wait until the frequency is stable. + */ + + cal_val = esp32c3_rtc_clk_cal(RTC_CAL_RTC_MUX, + SLOW_CLK_CAL_CYCLES); + } + else + { + cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; + cal_val = (uint32_t) (cal_dividend / + esp32c3_rtc_clk_slow_freq_get_hz()); + } + } + while (cal_val == 0); + + putreg32((uint32_t)cal_val, RTC_SLOW_CLK_CAL_REG); +} + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_finish + * + * Description: + * Wake up from sleep. + * + * Input Parameters: + * lslp_mem_inf_fpu - If non-zero then the low power config + * is restored immediately on wake + * + * Returned Value: + * non-zero if sleep was rejected by hardware + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32c3_rtc_sleep_finish(uint32_t lslp_mem_inf_fpu) +{ + uint32_t reject; + struct esp32c3_rtc_sleep_pu_config_s pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1); + + /* In deep sleep mode, we never get here */ + + reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW); + modifyreg32(RTC_CNTL_INT_CLR_REG, 0, + RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); + + /* restore config if it is a light sleep */ + + if (lslp_mem_inf_fpu) + { + esp32c3_rtc_sleep_pu(pu_cfg); + } + + return reject; +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_apb_freq_update + * + * Description: + * Store new APB frequency value into RTC_APB_FREQ_REG + * + * Input Parameters: + * apb_freq - New APB frequency, in Hz + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_clk_apb_freq_update(uint32_t apb_freq) +{ + uint32_t val = ((apb_freq >> 12) & UINT16_MAX) | + (((apb_freq >> 12) & UINT16_MAX) << 16); + putreg32(val, RTC_APB_FREQ_REG); +} + +/**************************************************************************** + * Name: esp32c3_wait_dig_dbias_valid + * + * Description: + * Wait digtial dbias valid + * + * Input Parameters: + * rtc_cycles - RTC count + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_wait_dig_dbias_valid(uint64_t rtc_cycles) +{ + enum esp32c3_rtc_slow_freq_e slow_clk_freq = + esp32c3_rtc_clk_slow_freq_get(); + enum esp32c3_rtc_cal_sel_e cal_clk = RTC_CAL_RTC_MUX; + if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) + { + cal_clk = RTC_CAL_32K_XTAL; + } + else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) + { + cal_clk = RTC_CAL_8MD256; + } + + esp32c3_rtc_clk_cal(cal_clk, rtc_cycles); +} + +/**************************************************************************** + * Name: esp32c3_rtc_update_to_xtal + * + * Description: + * Switch to XTAL frequency, does not disable the PLL + * + * Input Parameters: + * freq - XTAL frequency + * div - REF_TICK divider + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_update_to_xtal(int freq, int div) +{ + int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_PRE_DIV_CNT); + ets_update_cpu_frequency(freq); + + /* lower the voltage */ + + if (freq <= 2) + { + REGI2C_WRITE_MASK(I2C_DIG_REG, + I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_2M); + } + else + { + REGI2C_WRITE_MASK(I2C_DIG_REG, + I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL); + } + + if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) + && (origin_div_cnt > 0)) + { + esp32c3_wait_dig_dbias_valid(2); + } + + /* Set divider from XTAL to APB clock. + * Need to set divider to 1 (reg. value 0) first. + */ + + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1); + + /* No need to adjust the REF_TICK. + * Switch clock source. + */ + + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL); + esp32c3_rtc_clk_apb_freq_update(freq * MHZ); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_bbpll_disable + * + * Description: + * disable BBPLL. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_clk_bbpll_disable(void) +{ + modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_set_xtal_wait + * + * Description: + * Set XTAL wait cycles by RTC slow clock's period + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_clk_set_xtal_wait(void) +{ + uint32_t slow_clk_period; + + /* the `xtal_wait` time need 1ms, so we need calibrate slow clk period, + * and `RTC_CNTL_XTL_BUF_WAIT` depend on it. + */ + + uint32_t xtal_wait_1ms = 100; + enum esp32c3_rtc_slow_freq_e slow_clk_freq = + esp32c3_rtc_clk_slow_freq_get(); + enum esp32c3_rtc_cal_sel_e cal_clk = RTC_CAL_RTC_MUX; + if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) + { + cal_clk = RTC_CAL_32K_XTAL; + } + else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) + { + cal_clk = RTC_CAL_8MD256; + } + + slow_clk_period = esp32c3_rtc_clk_cal(cal_clk, 2000); + if (slow_clk_period) + { + xtal_wait_1ms = (1000 << RTC_CLK_CAL_FRACT) / slow_clk_period; + } + + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, xtal_wait_1ms); +} + +/**************************************************************************** + * Name: esp32c3_rtc_bbpll_configure + * + * Description: + * Configure main XTAL frequency values according to pll_freq. + * + * Input Parameters: + * xtal_freq - XTAL frequency values + * pll_freq - PLL frequency values + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_bbpll_configure( + enum esp32c3_rtc_xtal_freq_e xtal_freq, int pll_freq) +{ + uint8_t div_ref; + uint8_t div7_0; + uint8_t dr1; + uint8_t dr3; + uint8_t dchgp; + uint8_t dcur; + uint8_t dbias; + uint8_t i2c_bbpll_lref; + uint8_t i2c_bbpll_div_7_0; + uint8_t i2c_bbpll_dcur; + + modifyreg32(I2C_MST_ANA_CONF0_REG, + I2C_MST_BBPLL_STOP_FORCE_HIGH, 0); + modifyreg32(I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW); + if (pll_freq == RTC_PLL_FREQ_480M) + { + /* Set this register to let the digital part know 480M PLL is used */ + + modifyreg32(SYSTEM_CPU_PER_CONF_REG, 0, SYSTEM_PLL_FREQ_SEL); + + /* Configure 480M PLL */ + + switch (xtal_freq) + { + case RTC_XTAL_FREQ_40M: + { + div_ref = 0; + div7_0 = 8; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 3; + dbias = 2; + } + break; + + case RTC_XTAL_FREQ_32M: + { + div_ref = 1; + div7_0 = 26; + dr1 = 1; + dr3 = 1; + dchgp = 4; + dcur = 0; + dbias = 2; + } + break; + + default: + { + div_ref = 0; + div7_0 = 8; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 3; + dbias = 2; + } + break; + } + + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b); + } + else + { + /* Clear this register to let the digital part know 320M PLL is used */ + + modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL, 0); + + /* Configure 320M PLL */ + + switch (xtal_freq) + { + case RTC_XTAL_FREQ_40M: + { + div_ref = 0; + div7_0 = 4; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 3; + dbias = 2; + } + break; + + case RTC_XTAL_FREQ_32M: + { + div_ref = 1; + div7_0 = 6; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 3; + dbias = 2; + } + break; + + default: + { + div_ref = 0; + div7_0 = 4; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 3; + dbias = 2; + } + break; + } + + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69); + } + + i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref); + i2c_bbpll_div_7_0 = div7_0; + i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) + | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cpu_freq_to_8m + * + * Description: + * Switch CPU frequency to 8 Mhz. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_clk_cpu_freq_to_8m(void) +{ + int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_PRE_DIV_CNT); + ets_update_cpu_frequency(8); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, + DIG_DBIAS_XTAL); + if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) + && (origin_div_cnt > 4)) + { + esp32c3_wait_dig_dbias_valid(2); + } + + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, + DPORT_SOC_CLK_SEL_8M); + esp32c3_rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cpu_freq_to_pll_mhz + * + * Description: + * Switch to one of PLL-based frequencies. + * + * Input Parameters: + * cpu_freq_mhz - CPU frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rtc_clk_cpu_freq_to_pll_mhz( + int cpu_freq_mhz) +{ + int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + int origin_cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_CPUPERIOD_SEL); + int dbias = DIG_DBIAS_80M; + int per_conf = DPORT_CPUPERIOD_SEL_80; + if (cpu_freq_mhz == 160) + { + dbias = DIG_DBIAS_160M; + per_conf = DPORT_CPUPERIOD_SEL_160; + } + else + { + ASSERT(cpu_freq_mhz != 80); + } + + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias); + if ((origin_soc_clk == DPORT_SOC_CLK_SEL_XTAL) + || (origin_soc_clk == DPORT_SOC_CLK_SEL_8M) + || (((origin_soc_clk == DPORT_SOC_CLK_SEL_PLL) + && (0 == origin_cpuperiod_sel)))) + { + esp32c3_wait_dig_dbias_valid(2); + } + + REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf); + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, + DPORT_SOC_CLK_SEL_PLL); + esp32c3_rtc_clk_apb_freq_update(80 * MHZ); + ets_update_cpu_frequency(cpu_freq_mhz); +} + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Name: esp32c3_rt_cb_handler + * + * Description: + * RT-Timer service routine + * + * Input Parameters: + * arg - Information about the RT-Timer configuration. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_rt_cb_handler(FAR void *arg) +{ + FAR struct alm_cbinfo_s *cbinfo = (struct alm_cbinfo_s *)arg; + alm_callback_t cb; + FAR void *cb_arg; + int alminfo_id; + + DEBUGASSERT(cbinfo != NULL); + alminfo_id = cbinfo->index; + DEBUGASSERT((RTC_ALARM0 <= alminfo_id) && + (alminfo_id < RTC_ALARM_LAST)); + + if (cbinfo->ac_cb != NULL) + { + /* Alarm callback */ + + cb = cbinfo->ac_cb; + cb_arg = (FAR void *)cbinfo->ac_arg; + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + cbinfo->deadline_us = 0; + cb(cb_arg, alminfo_id); + } +} + +#endif /* CONFIG_RTC_DRIVER */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_rtc_clk_xtal_freq_get + * + * Description: + * Get main XTAL frequency + * + * Input Parameters: + * None + * + * Returned Value: + * XTAL frequency (one of enum esp32c3_rtc_xtal_freq_e values) + * + ****************************************************************************/ + +enum esp32c3_rtc_xtal_freq_e IRAM_ATTR + esp32c3_rtc_clk_xtal_freq_get(void) +{ + /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ + + uint32_t xtal_freq_reg = getreg32(RTC_XTAL_FREQ_REG); + if (!esp32c3_clk_val_is_valid(xtal_freq_reg)) + { + return RTC_XTAL_FREQ_40M; + } + + return (xtal_freq_reg & UINT16_MAX); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_slow_freq_set + * + * Description: + * Select source for RTC_SLOW_CLK + * + * Input Parameters: + * slow_freq - clock source (one of esp32c3_rtc_slow_freq_e values) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_clk_slow_freq_set( + enum esp32c3_rtc_slow_freq_e slow_freq) +{ + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); + + /* Why we need to connect this clock to digital? Or maybe this clock + * should be connected to digital when xtal 32k clock is enabled instead? + */ + + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, + (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); + + /* The clk_8m_d256 will be closed when rtc_state in SLEEP, + * so if the slow_clk is 8md256, clk_8m must be force power on + */ + + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, + (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0); + esp32c3_rtc_clk_set_xtal_wait(); + esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_slow_freq_get + * + * Description: + * Get the RTC_SLOW_CLK source + * + * Input Parameters: + * None + * + * Returned Value: + * Currently selected clock source + * (one of enum esp32c3_rtc_slow_freq_e values) + * + ****************************************************************************/ + +enum esp32c3_rtc_slow_freq_e IRAM_ATTR esp32c3_rtc_clk_slow_freq_get(void) +{ + return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cal + * + * Description: + * Measure RTC slow clock's period, based on main XTAL frequency + * + * Input Parameters: + * cal_clk - clock to be measured + * slowclk_cycles - number of slow clock cycles to average + * + * Returned Value: + * Average slow clock period in microseconds, Q13.19 fixed point format + * or 0 if calibration has timed out + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32c3_rtc_clk_cal(enum esp32c3_rtc_cal_sel_e cal_clk, + uint32_t slowclk_cycles) +{ + enum esp32c3_rtc_xtal_freq_e xtal_freq; + uint64_t xtal_cycles; + uint64_t divider; + uint64_t period_64; + uint32_t period; + + xtal_freq = esp32c3_rtc_clk_xtal_freq_get(); + xtal_cycles = esp32c3_rtc_clk_cal_internal(cal_clk, slowclk_cycles); + divider = ((uint64_t)xtal_freq) * slowclk_cycles; + period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) + / divider; + period = (uint32_t)(period_64 & UINT32_MAX); + + return period; +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_set + * + * Description: + * Set RTC CLK frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_clk_set(void) +{ + esp32c3_rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + esp32c3_select_rtc_slow_clk(RTC_SLOW_FREQ_RTC); +} + +/**************************************************************************** + * Name: esp32c3_rtc_init + * + * Description: + * Initialize RTC clock and power control related functions. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_init(void) +{ + struct esp32c3_rtc_priv_s cfg = RTC_CONFIG_DEFAULT(); + struct esp32c3_rtc_init_config_s rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT(); + + /* If this pd_cfg is set to 1, all memory won't + * enter low power mode during light sleep. + * If this pd_cfg is set to 0, all memory will + * enter low power mode during light sleep + */ + + struct esp32c3_rtc_sleep_pu_config_s pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); + modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU, 0); + esp32c3_rtc_clk_set_xtal_wait(); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); + REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, + RTC_CNTL_MIN_SLP_VAL_MIN); + + /* set default powerup & wait time */ + + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, + rtc_init_cfg.wifi_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, + rtc_init_cfg.wifi_wait_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, + rtc_init_cfg.bt_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, + rtc_init_cfg.bt_wait_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, + rtc_init_cfg.cpu_top_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, + rtc_init_cfg.cpu_top_wait_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, + rtc_init_cfg.dg_wrap_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, + rtc_init_cfg.dg_wrap_wait_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, + rtc_init_cfg.dg_peri_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, + rtc_init_cfg.dg_peri_wait_cycles); + + /* Reset RTC bias to default value (needed if waking up from deep sleep) */ + + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, + RTC_CNTL_DBIAS_1V10); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, + RTC_CNTL_DBIAS_1V10); + if (cfg.clkctl_init) + { + /* clear CMMU clock force on */ + + modifyreg32(EXTMEM_CACHE_MMU_POWER_CTRL_REG, + EXTMEM_CACHE_MMU_MEM_FORCE_ON, 0); + + /* clear tag clock force on */ + + modifyreg32(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, + EXTMEM_ICACHE_TAG_MEM_FORCE_ON, 0); + + /* clear register clock force on */ + + modifyreg32(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN, 0); + modifyreg32(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN, 0); + } + + if (cfg.pwrctl_init) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); + + /* cancel xtal force pu if no need to force power up + * cannot cancel xtal force pu if pll is force power on + */ + + if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, 0); + } + else + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_XTL_FORCE_PU); + } + + /* force pd APLL */ + + modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, 0); + modifyreg32(RTC_CNTL_ANA_CONF_REG, 0, RTC_CNTL_PLLA_FORCE_PD); + + /* open sar_i2c protect function to avoid sar_i2c + * reset when rtc_ldo is low. + */ + + modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD, 0); + + /* cancel bbpll force pu if setting no force power up */ + + if (!cfg.bbpll_fpu) + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU | + RTC_CNTL_BBPLL_I2C_FORCE_PU | RTC_CNTL_BB_I2C_FORCE_PU, 0); + } + else + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BBPLL_FORCE_PU | + RTC_CNTL_BBPLL_I2C_FORCE_PU | RTC_CNTL_BB_I2C_FORCE_PU); + } + + modifyreg32(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU | + RTC_CNTL_DBOOST_FORCE_PU, 0); + if (cfg.rtc_dboost_fpd) + { + modifyreg32(RTC_CNTL_REG, 0, RTC_CNTL_DBOOST_FORCE_PD); + } + else + { + modifyreg32(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD, 0); + } + + /* If this mask is enabled, all soc memories + * cannot enter power down mode. + * We should control soc memory power down mode from RTC, + * so we will not touch this register any more. + */ + + modifyreg32(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK, 0); + esp32c3_rtc_sleep_pu(pu_cfg); + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU | + RTC_CNTL_WIFI_FORCE_PU | RTC_CNTL_BT_FORCE_PU | + RTC_CNTL_CPU_TOP_FORCE_PU | RTC_CNTL_DG_PERI_FORCE_PU , 0); + + modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | + RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_BT_FORCE_NOISO | + RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_NOISO , 0); + + /* cancel digital PADS force no iso */ + + if (cfg.cpu_waiti_clk_gate) + { + modifyreg32(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_CPU_WAIT_MODE_FORCE_ON, 0); + } + else + { + modifyreg32(SYSTEM_CPU_PER_CONF_REG, 0, + SYSTEM_CPU_WAIT_MODE_FORCE_ON); + } + + /* if SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0 , + * the cpu clk will be closed when cpu enter WAITI mode. + */ + + modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD | + RTC_CNTL_DG_PAD_FORCE_NOISO, 0); + } +} + +/**************************************************************************** + * Name: esp32c3_rtc_get_time_us + * + * Description: + * Get current value of RTC counter in microseconds + * + * Input Parameters: + * None + * + * Returned Value: + * Current value of RTC counter in microseconds + * + ****************************************************************************/ + +uint64_t esp32c3_rtc_get_time_us(void) +{ + const uint32_t cal = getreg32(RTC_SLOW_CLK_CAL_REG); + const uint64_t rtc_this_ticks = esp32c3_rtc_time_get(); + + /* RTC counter result is up to 2^48, calibration factor is up to 2^24, + * for a 32kHz clock. We need to calculate (assuming no overflow): + * (ticks * cal) >> RTC_CLK_CAL_FRACT. An overflow in the (ticks * cal) + * multiplication would cause time to wrap around after approximately + * 13 days, which is probably not enough for some applications. + * Therefore multiplication is split into two terms, for the lower 32-bit + * and the upper 16-bit parts of "ticks", i.e.: + * ((ticks_low + 2^32 * ticks_high) * cal) >> RTC_CLK_CAL_FRACT + */ + + const uint64_t ticks_low = rtc_this_ticks & UINT32_MAX; + const uint64_t ticks_high = rtc_this_ticks >> 32; + const uint64_t delta_time_us = ((ticks_low * cal) >> RTC_CLK_CAL_FRACT) + + ((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT)); + + return delta_time_us; +} + +/**************************************************************************** + * Name: esp32c3_rtc_time_get + * + * Description: + * Get current value of RTC counter. + * + * Input Parameters: + * None + * + * Returned Value: + * current value of RTC counter + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32c3_rtc_time_get(void) +{ + uint64_t rtc_time; + + modifyreg32(RTC_CNTL_TIME_UPDATE_REG, 0, RTC_CNTL_TIME_UPDATE); + rtc_time = getreg32(RTC_CNTL_TIME0_REG); + rtc_time |= ((uint64_t) getreg32(RTC_CNTL_TIME1_REG)) << 32; + + return rtc_time; +} + +/**************************************************************************** + * Name: esp32c3_rtc_time_us_to_slowclk + * + * Description: + * Convert time interval from microseconds to RTC_SLOW_CLK cycles. + * + * Input Parameters: + * time_in_us - Time interval in microseconds + * slow_clk_period - Period of slow clock in microseconds + * + * Returned Value: + * number of slow clock cycles + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32c3_rtc_time_us_to_slowclk(uint64_t time_in_us, + uint32_t period) +{ + /* Overflow will happen in this function if time_in_us >= 2^45, + * which is about 400 days. TODO: fix overflow. + */ + + return (time_in_us << RTC_CLK_CAL_FRACT) / period; +} + +/**************************************************************************** + * Name: esp32c3_rtc_time_slowclk_to_us + * + * Description: + * Convert time interval from RTC_SLOW_CLK to microseconds + * + * Input Parameters: + * rtc_cycles - Time interval in RTC_SLOW_CLK cycles + * period - Period of slow clock in microseconds + * + * Returned Value: + * time interval in microseconds + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32c3_rtc_time_slowclk_to_us(uint64_t rtc_cycles, + uint32_t period) +{ + return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; +} + +/**************************************************************************** + * Name: esp32c3_rtc_cpu_freq_set_xtal + * + * Description: + * Switch CPU clock source to XTAL + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_cpu_freq_set_xtal(void) +{ + int freq_mhz = (int) esp32c3_rtc_clk_xtal_freq_get(); + esp32c3_rtc_update_to_xtal(freq_mhz, 1); + esp32c3_rtc_clk_bbpll_disable(); +} + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_init + * + * Description: + * Prepare the chip to enter sleep mode + * + * Input Parameters: + * flags - sleep mode configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_sleep_init(uint32_t flags) +{ + struct esp32c3_rtc_sleep_config_s cfg = RTC_SLEEP_CONFIG_DEFAULT(flags); + struct esp32c3_rtc_sleep_pu_config_s pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1); + if (cfg.lslp_mem_inf_fpu) + { + esp32c3_rtc_sleep_pu(pu_cfg); + } + + if (cfg.wifi_pd_en) + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_PD_EN); + } + else + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN, 0); + } + + if (cfg.bt_pd_en) + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_BT_PD_EN); + } + else + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN, 0); + } + + if (cfg.cpu_pd_en) + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_CPU_TOP_PD_EN); + } + else + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN, 0); + } + + if (cfg.dig_peri_pd_en) + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_DG_PERI_PD_EN); + } + else + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN, 0); + } + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, + RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, + RTC_CNTL_BIASSLP_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, + RTC_CNTL_BIASSLP_SLEEP_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, + RTC_CNTL_PD_CUR_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, + RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + if (cfg.deep_slp) + { + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); + modifyreg32(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0); + + /* It's only a temporary configuration to set dbg 0 to make + * deepsleep run successfully when in high temperature. + * We will restore it to RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT + * when ECO chip come back. TODO ESP32-C3 IDF-2568 + */ + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, 0); + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_DG_WRAP_PD_EN); + modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | + RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU, 0); + } + else + { + modifyreg32(RTC_CNTL_BIAS_CONF_REG, 0, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, + RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); + modifyreg32(RTC_CNTL_REG, 0, RTC_CNTL_REGULATOR_FORCE_PU); + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN, 0); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, + RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); + } + + /* enable VDDSDIO control by state machine */ + + REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); + REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, + cfg.vddsdio_pd_en); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, + cfg.rtc_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, + cfg.rtc_dbias_wak); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, + cfg.dig_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, + cfg.dig_dbias_wak); + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, + cfg.deep_slp_reject); + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, + cfg.light_slp_reject); + + /* gating XTAL clock */ + + REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING); +} + +/**************************************************************************** + * Name: esp32c3_rtc_deep_sleep_start + * + * Description: + * Enter deep sleep mode. + * + * Input Parameters: + * wakeup_opt - bit mask wake up reasons to enable + * reject_opt - bit mask of sleep reject reasons. + * + * Returned Value: + * non-zero if sleep was rejected by hardware + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32c3_rtc_deep_sleep_start(uint32_t wakeup_opt, + uint32_t reject_opt) +{ + /* Values used to set the SYSTEM_RTC_FASTMEM_CONFIG_REG value */ + + const unsigned CRC_START_ADDR = 0; + const unsigned CRC_LEN = 0x7ff; + + REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt); + putreg32(reject_opt, RTC_CNTL_SLP_REJECT_CONF_REG); + + /* Calculate RTC Fast Memory CRC (for wake stub) & go to deep sleep + * Because we may be running from RTC memory as stack, we can't easily + * call any functions to do this (as registers will spill to stack, + * corrupting the CRC). Instead, load all the values we need into registers + * then use register ops only to calculate the CRC value, write it to the + * RTC CRC value register, and immediately go into deep sleep. + */ + + asm volatile( + + /* Start CRC calculation */ + + "sw %1, 0(%0)\n" + "or t0, %1, %2\n" + "sw t0, 0(%0)\n" + + /* Wait for the CRC calculation to finish */ + + ".Lwaitcrc:\n" + "fence\n" + "lw t0, 0(%0)\n" + "li t1, "STR(SYSTEM_RTC_MEM_CRC_FINISH)"\n" + "and t0, t0, t1\n" + "beqz t0, .Lwaitcrc\n" + "not %2, %2\n" + "and t0, t0, %2\n" + "sw t0, 0(%0)\n" + "fence\n" + "not %2, %2\n" + + /* Store the calculated value in RTC_MEM_CRC_REG */ + + "lw t0, 0(%3)\n" + "sw t0, 0(%4)\n" + "fence\n" + + /* Set register bit to go into deep sleep */ + + "lw t0, 0(%5)\n" + "or t0, t0, %6\n" + "sw t0, 0(%5)\n" + "fence\n" + + /* Wait for sleep reject interrupt (never finishes if successful) */ + + ".Lwaitsleep:" + "fence\n" + "lw t0, 0(%7)\n" + "and t0, t0, %8\n" + "beqz t0, .Lwaitsleep\n" + + : + : + "r" (SYSTEM_RTC_FASTMEM_CONFIG_REG), + "r" ((CRC_START_ADDR << SYSTEM_RTC_MEM_CRC_START_S) + | (CRC_LEN << SYSTEM_RTC_MEM_CRC_LEN_S)), + "r" (SYSTEM_RTC_MEM_CRC_START), + "r" (SYSTEM_RTC_FASTMEM_CRC_REG), + "r" (RTC_MEMORY_CRC_REG), + "r" (RTC_CNTL_STATE0_REG), + "r" (RTC_CNTL_SLEEP_EN), + "r" (RTC_CNTL_INT_RAW_REG), + "r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) + : "t0", "t1" + ); + + return esp32c3_rtc_sleep_finish(0); +} + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_start + * + * Description: + * Enter force sleep mode. + * + * Input Parameters: + * wakeup_opt - bit mask wake up reasons to enable + * reject_opt - bit mask of sleep reject reasons. + * + * Returned Value: + * non-zero if sleep was rejected by hardware + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32c3_rtc_sleep_start(uint32_t wakeup_opt, + uint32_t reject_opt, uint32_t lslp_mem_inf_fpu) +{ + REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt); + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, + RTC_CNTL_SLEEP_REJECT_ENA, reject_opt); + + /* Start entry into sleep mode */ + + modifyreg32(RTC_CNTL_STATE0_REG, 0, RTC_CNTL_SLEEP_EN); + + while ((getreg32(RTC_CNTL_INT_RAW_REG) & + (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW)) == 0); + + return esp32c3_rtc_sleep_finish(lslp_mem_inf_fpu); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cpu_freq_set_config + * + * Description: + * Set CPU frequency configuration. + * + * Input Parameters: + * config - CPU frequency configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_clk_cpu_freq_set_config( + const struct esp32c3_cpu_freq_config_s *config) +{ + uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + if (config->source == RTC_CPU_FREQ_SRC_XTAL) + { + esp32c3_rtc_update_to_xtal(config->freq_mhz, config->div); + if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) + { + esp32c3_rtc_clk_bbpll_disable(); + } + } + else if (config->source == RTC_CPU_FREQ_SRC_PLL) + { + if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, 0); + esp32c3_rtc_bbpll_configure(esp32c3_rtc_clk_xtal_freq_get(), + config->source_freq_mhz); + } + + esp32c3_rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); + } + else if (config->source == RTC_CPU_FREQ_SRC_8M) + { + esp32c3_rtc_clk_cpu_freq_to_8m(); + if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) + { + esp32c3_rtc_clk_bbpll_disable(); + } + } +} + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_low_init + * + * Description: + * Low level initialize for rtc state machine waiting + * cycles after waking up. + * + * Input Parameters: + * slowclk_period - Re-calibrated slow clock period + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_sleep_low_init(uint32_t slowclk_period) +{ + /* Set 5 PWC state machine times to fit in main state machine time */ + + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, + RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, + esp32c3_rtc_time_us_to_slowclk( + RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, + RTC_CNTL_CK8M_WAIT_SLP_CYCLES); +} + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cpu_freq_get_config + * + * Description: + * Get the currently used CPU frequency configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * CPU clock configuration structure + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_clk_cpu_freq_get_config( + struct esp32c3_cpu_freq_config_s *out_config) +{ + uint32_t div = 3; + uint32_t freq_mhz = 160; + uint32_t source_freq_mhz = RTC_PLL_FREQ_480M; + enum esp32c3_rtc_cpu_freq_src_e source = RTC_CPU_FREQ_SRC_PLL; + uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + switch (soc_clk_sel) + { + case DPORT_SOC_CLK_SEL_XTAL: + { + source = RTC_CPU_FREQ_SRC_XTAL; + div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_PRE_DIV_CNT) + 1; + source_freq_mhz = (uint32_t) esp32c3_rtc_clk_xtal_freq_get(); + freq_mhz = source_freq_mhz / div; + } + break; + + case DPORT_SOC_CLK_SEL_PLL: + { + uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_CPUPERIOD_SEL); + uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_PLL_FREQ_SEL); + source = RTC_CPU_FREQ_SRC_PLL; + source_freq_mhz = (pllfreq_sel) ? + RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M; + if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) + { + div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4; + freq_mhz = 80; + } + else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) + { + div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 3 : 2; + div = 3; + freq_mhz = 160; + } + else + { + ASSERT(0); + } + } + break; + + case DPORT_SOC_CLK_SEL_8M: + { + source = RTC_CPU_FREQ_SRC_8M; + source_freq_mhz = 8; + div = 1; + freq_mhz = source_freq_mhz; + } + break; + + default: + ASSERT(0); + } + + *out_config = (struct esp32c3_cpu_freq_config_s) + { + .source = source, + .source_freq_mhz = source_freq_mhz, + .div = div, + .freq_mhz = freq_mhz + }; +} + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_set_wakeup_time + * + * Description: + * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. + * + * Input Parameters: + * t - value of RTC counter at which wakeup from sleep will happen. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_sleep_set_wakeup_time(uint64_t t) +{ + putreg32(t & UINT32_MAX, RTC_CNTL_SLP_TIMER0_REG); + putreg32((uint32_t)(t >> 32), RTC_CNTL_SLP_TIMER1_REG); + modifyreg32(RTC_CNTL_INT_CLR_REG, 0, RTC_CNTL_MAIN_TIMER_INT_CLR_M); + modifyreg32(RTC_CNTL_SLP_TIMER1_REG, 0, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); +} + +/**************************************************************************** + * Name: esp32c3_rtc_set_boot_time + * + * Description: + * Set time to RTC register to replace the original boot time. + * + * Input Parameters: + * time_us - set time in microseconds. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32c3_rtc_set_boot_time(uint64_t time_us) +{ + putreg32((uint32_t)(time_us & UINT32_MAX), RTC_BOOT_TIME_LOW_REG); + putreg32((uint32_t)(time_us >> 32), RTC_BOOT_TIME_HIGH_REG); +} + +/**************************************************************************** + * Name: esp32c3_rtc_get_boot_time + * + * Description: + * Get time of RTC register to indicate the original boot time. + * + * Input Parameters: + * None + * + * Returned Value: + * time_us - get time in microseconds. + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32c3_rtc_get_boot_time(void) +{ + return ((uint64_t)getreg32(RTC_BOOT_TIME_LOW_REG)) + + (((uint64_t)getreg32(RTC_BOOT_TIME_HIGH_REG)) << 32); +} + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation is selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but CONFIG_RTC_HIRES is not set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +#ifndef CONFIG_RTC_HIRES +time_t up_rtc_time(void) +{ + uint64_t time_us; + irqstate_t flags; + + flags = spin_lock_irqsave(NULL); + + /* NOTE: RT-Timer starts to work after the board is initialized, and the + * RTC controller starts works after up_rtc_initialize is initialized. + * Since the system clock starts to work before the board is initialized, + * if CONFIG_RTC is enabled, the system time must be matched by the time + * of the RTC controller (up_rtc_initialize has already been initialized, + * and RT-Timer cannot work). + */ + + /* Determine if RT-Timer is started */ + + if (g_rt_timer_enabled == true) + { + /* Get the time from RT-Timer, the time interval between RTC + * controller and RT-Timer is stored in g_rtc_save->offset. + */ + + time_us = rt_timer_time_us() + g_rtc_save->offset + + esp32c3_rtc_get_boot_time(); + } + else + { + /* Get the time from RTC controller. */ + + time_us = esp32c3_rtc_get_time_us() + + esp32c3_rtc_get_boot_time(); + } + + spin_unlock_irqrestore(NULL, flags); + + return (time_t)(time_us / USEC_PER_SEC); +} +#endif /* !CONFIG_RTC_HIRES */ + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. + * + * Input Parameters: + * ts - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(FAR const struct timespec *ts) +{ + irqstate_t flags; + uint64_t now_us; + uint64_t rtc_offset_us; + + DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC); + flags = spin_lock_irqsave(NULL); + + now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC + + ts->tv_nsec / NSEC_PER_USEC; + if (g_rt_timer_enabled == true) + { + /* Set based on RT-Timer offset value. */ + + rtc_offset_us = now_us - rt_timer_time_us(); + } + else + { + /* Set based on the offset value of the RT controller. */ + + rtc_offset_us = now_us - esp32c3_rtc_get_time_us(); + } + + g_rtc_save->offset = 0; + esp32c3_rtc_set_boot_time(rtc_offset_us); + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ +#ifndef CONFIG_PM + /* Initialize RTC controller parameters */ + + esp32c3_rtc_init(); + esp32c3_rtc_clk_set(); +#endif + + g_rtc_save = &rtc_saved_data; + + /* If saved data is invalid, clear offset information */ + + if (g_rtc_save->magic != MAGIC_RTC_SAVE) + { + g_rtc_save->magic = MAGIC_RTC_SAVE; + g_rtc_save->offset = 0; + esp32c3_rtc_set_boot_time(0); + } + +#ifdef CONFIG_RTC_HIRES + /* Synchronize the base time to the RTC time */ + + up_rtc_gettime(&g_basetime); +#endif + + g_rtc_enabled = true; + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC time or RT-Timer. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the RTC time or RT-Timer value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(FAR struct timespec *tp) +{ + irqstate_t flags; + uint64_t time_us; + + flags = spin_lock_irqsave(NULL); + + if (g_rt_timer_enabled == true) + { + time_us = rt_timer_time_us() + g_rtc_save->offset + + esp32c3_rtc_get_boot_time(); + } + else + { + time_us = = esp32c3_rtc_get_time_us() + + esp32c3_rtc_get_boot_time(); + } + + tp->tv_sec = time_us / USEC_PER_SEC; + tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} +#endif /* CONFIG_RTC_HIRES */ + +#ifdef CONFIG_RTC_ALARM + +/**************************************************************************** + * Name: up_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_setalarm(FAR struct alm_setalarm_s *alminfo) +{ + struct rt_timer_args_s rt_timer_args; + FAR struct alm_cbinfo_s *cbinfo; + irqstate_t flags; + int ret = -EBUSY; + int id; + + DEBUGASSERT(alminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alminfo->as_id) && + (alminfo->as_id < RTC_ALARM_LAST)); + + /* Set the alarm in RT-Timer */ + + id = alminfo->as_id; + cbinfo = &g_alarmcb[id]; + + if (cbinfo->ac_cb == NULL) + { + /* Create the RT-Timer alarm */ + + flags = spin_lock_irqsave(NULL); + + if (cbinfo->alarm_hdl == NULL) + { + cbinfo->index = id; + rt_timer_args.arg = cbinfo; + rt_timer_args.callback = esp32c3_rt_cb_handler; + ret = rt_timer_create(&rt_timer_args, &cbinfo->alarm_hdl); + if (ret < 0) + { + rtcerr("ERROR: Failed to create rt_timer error=%d\n", ret); + spin_unlock_irqrestore(NULL, flags); + return ret; + } + } + + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + cbinfo->deadline_us = alminfo->as_time.tv_sec * USEC_PER_SEC + + alminfo->as_time.tv_nsec / NSEC_PER_USEC; + + if (cbinfo->alarm_hdl == NULL) + { + rtcerr("ERROR: failed to create alarm timer\n"); + } + else + { + rtcinfo("Start RTC alarm.\n"); + rt_timer_start(cbinfo->alarm_hdl, cbinfo->deadline_us, false); + ret = OK; + } + + spin_unlock_irqrestore(NULL, flags); + } + + return ret; +} + +/**************************************************************************** + * Name: up_rtc_cancelalarm + * + * Description: + * Cancel an alarm. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_cancelalarm(enum alm_id_e alarmid) +{ + FAR struct alm_cbinfo_s *cbinfo; + irqstate_t flags; + int ret = -ENODATA; + + DEBUGASSERT((RTC_ALARM0 <= alarmid) && + (alarmid < RTC_ALARM_LAST)); + + /* Set the alarm in hardware and enable interrupts */ + + cbinfo = &g_alarmcb[alarmid]; + + if (cbinfo->ac_cb != NULL) + { + flags = spin_lock_irqsave(NULL); + + /* Stop and delete the alarm */ + + rtcinfo("Cancel RTC alarm.\n"); + rt_timer_stop(cbinfo->alarm_hdl); + rt_timer_delete(cbinfo->alarm_hdl); + cbinfo->ac_cb = NULL; + cbinfo->deadline_us = 0; + cbinfo->alarm_hdl = NULL; + + spin_unlock_irqrestore(NULL, flags); + + ret = OK; + } + + return ret; +} + +/**************************************************************************** + * Name: up_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * tp - Location to return the timer match register. + * alarmid - Identifies the alarm to get. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_rdalarm(FAR struct timespec *tp, uint32_t alarmid) +{ + irqstate_t flags; + FAR struct alm_cbinfo_s *cbinfo; + DEBUGASSERT(tp != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarmid) && + (alarmid < RTC_ALARM_LAST)); + + flags = spin_lock_irqsave(NULL); + + /* Get the alarm according to the alarmid */ + + cbinfo = &g_alarmcb[alarmid]; + + tp->tv_sec = (rt_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us) / USEC_PER_SEC; + tp->tv_nsec = ((rt_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: up_rtc_timer_init + * + * Description: + * Init RTC timer. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_timer_init(void) +{ + /* RT-Timer enabled */ + + g_rt_timer_enabled = true; + + /* Get the time difference between rt_timer and RTC timer */ + + g_rtc_save->offset = esp32c3_rtc_get_time_us() - rt_timer_time_us(); + + return OK; +} + +#endif /* CONFIG_RTC_DRIVER */ + diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc.h b/arch/risc-v/src/esp32c3/esp32c3_rtc.h new file mode 100644 index 00000000000..95a8feb62e5 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rtc.h @@ -0,0 +1,662 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rtc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include "hardware/esp32c3_soc.h" + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Cycles for RTC Timer clock source (internal oscillator) calibrate */ + +#define RTC_CLK_SRC_CAL_CYCLES (10) + +/* Various delays to be programmed into power control state machines */ + +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) + +#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG +#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG +#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG +#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG + +#define RTC_SLEEP_PD_DIG BIT(0) /* Deep sleep */ +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */ +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */ +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */ + +/* RTC FAST and SLOW memories are automatically + * powered up and down along with the CPU + */ + +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) +#define RTC_SLEEP_PD_VDDSDIO BIT(5) /* Power down VDDSDIO regulator */ +#define RTC_SLEEP_PD_WIFI BIT(6) /* Power down Wi-Fi */ +#define RTC_SLEEP_PD_BT BIT(7) /* Power down BT */ +#define RTC_SLEEP_PD_CPU BIT(8) /* Power down CPU when in light-sleep */ +#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) /* Power down DIG peripherals */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Clock source to be calibrated using rtc_clk_cal function */ + +enum esp32c3_rtc_cal_sel_e +{ + RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */ + RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */ + RTC_CAL_32K_XTAL = 2 /* External 32 kHz XTAL */ +}; + +/* CPU clock source */ + +enum esp32c3_rtc_cpu_freq_src_e +{ + RTC_CPU_FREQ_SRC_XTAL, /* XTAL */ + RTC_CPU_FREQ_SRC_PLL, /* PLL (480M or 320M) */ + RTC_CPU_FREQ_SRC_8M, /* Internal 8M RTC oscillator */ + RTC_CPU_FREQ_SRC_APLL /* APLL */ +}; + +/* Possible main XTAL frequency values. + * Enum values should be equal to frequency in MHz. + */ + +enum esp32c3_rtc_xtal_freq_e +{ + RTC_XTAL_FREQ_32M = 32, + RTC_XTAL_FREQ_40M = 40, +}; + +/* RTC SLOW_CLK frequency values */ + +enum esp32c3_rtc_slow_freq_e +{ + RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */ + RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */ + RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */ +}; + +/* CPU clock configuration structure */ + +struct esp32c3_cpu_freq_config_s +{ + /* The clock from which CPU clock is derived */ + + enum esp32c3_rtc_cpu_freq_src_e source; + uint32_t source_freq_mhz; /* Source clock frequency */ + uint32_t div; /* Divider, freq_mhz = source_freq_mhz / div */ + uint32_t freq_mhz; /* CPU clock frequency */ +}; + +#ifdef CONFIG_RTC_ALARM + +/* The form of an alarm callback */ + +typedef CODE void (*alm_callback_t)(FAR void *arg, unsigned int alarmid); + +enum alm_id_e +{ + RTC_ALARM0 = 0, /* RTC ALARM 0 */ + RTC_ALARM1 = 1, /* RTC ALARM 1 */ + RTC_ALARM_LAST, +}; + +/* Structure used to pass parameters to set an alarm */ + +struct alm_setalarm_s +{ + int as_id; /* enum alm_id_e */ + struct timespec as_time; /* Alarm expiration time */ + alm_callback_t as_cb; /* Callback (if non-NULL) */ + FAR void *as_arg; /* Argument for callback */ +}; + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_rtc_clk_xtal_freq_get + * + * Description: + * Get main XTAL frequency + * + * Input Parameters: + * None + * + * Returned Value: + * XTAL frequency (one of enum esp32c3_rtc_xtal_freq_e values) + * + ****************************************************************************/ + +enum esp32c3_rtc_xtal_freq_e esp32c3_rtc_clk_xtal_freq_get(void); + +/**************************************************************************** + * Name: esp32c3_rtc_clk_slow_freq_get + * + * Description: + * Get the RTC_SLOW_CLK source + * + * Input Parameters: + * None + * + * Returned Value: + * Currently selected clock source + * (one of enum esp32c3_rtc_slow_freq_e values) + * + ****************************************************************************/ + +enum esp32c3_rtc_slow_freq_e esp32c3_rtc_clk_slow_freq_get(void); + +/**************************************************************************** + * Name: esp32c3_rtc_clk_slow_freq_set + * + * Description: + * Select source for RTC_SLOW_CLK + * + * Input Parameters: + * slow_freq - clock source (one of esp32c3_rtc_slow_freq_e values) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_clk_slow_freq_set(enum esp32c3_rtc_slow_freq_e slow_freq); + +/**************************************************************************** + * Name: esp32c3_rtc_clk_set + * + * Description: + * Set RTC CLK frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_clk_set(void); + +/**************************************************************************** + * Name: esp32c3_rtc_init + * + * Description: + * Initialize RTC clock and power control related functions. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_init(void); + +/**************************************************************************** + * Name: esp32c3_rtc_time_get + * + * Description: + * Get current value of RTC counter. + * + * Input Parameters: + * None + * + * Returned Value: + * current value of RTC counter + * + ****************************************************************************/ + +uint64_t esp32c3_rtc_time_get(void); + +/**************************************************************************** + * Name: esp32c3_rtc_time_us_to_slowclk + * + * Description: + * Convert time interval from microseconds to RTC_SLOW_CLK cycles. + * + * Input Parameters: + * time_in_us - Time interval in microseconds + * slow_clk_period - Period of slow clock in microseconds + * + * Returned Value: + * number of slow clock cycles + * + ****************************************************************************/ + +uint64_t esp32c3_rtc_time_us_to_slowclk(uint64_t time_in_us, + uint32_t period); + +/**************************************************************************** + * Name: esp32c3_rtc_cpu_freq_set_xtal + * + * Description: + * Switch CPU clock source to XTAL + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_cpu_freq_set_xtal(void); + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_init + * + * Description: + * Prepare the chip to enter sleep mode + * + * Input Parameters: + * flags - sleep mode configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_sleep_init(uint32_t flags); + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_start + * + * Description: + * Enter force sleep mode. + * + * Input Parameters: + * wakeup_opt - bit mask wake up reasons to enable + * reject_opt - bit mask of sleep reject reasons. + * + * Returned Value: + * non-zero if sleep was rejected by hardware + * + ****************************************************************************/ + +uint32_t esp32c3_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, + uint32_t lslp_mem_inf_fpu); + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cal + * + * Description: + * Measure RTC slow clock's period, based on main XTAL frequency + * + * Input Parameters: + * cal_clk - clock to be measured + * slowclk_cycles - number of slow clock cycles to average + * + * Returned Value: + * Average slow clock period in microseconds, Q13.19 fixed point format + * or 0 if calibration has timed out + * + ****************************************************************************/ + +uint32_t esp32c3_rtc_clk_cal(enum esp32c3_rtc_cal_sel_e cal_clk, + uint32_t slowclk_cycles); + +/**************************************************************************** + * Name: esp32c3_rtc_time_slowclk_to_us + * + * Description: + * Convert time interval from RTC_SLOW_CLK to microseconds + * + * Input Parameters: + * rtc_cycles - Time interval in RTC_SLOW_CLK cycles + * period - Period of slow clock in microseconds + * + * Returned Value: + * time interval in microseconds + * + ****************************************************************************/ + +uint64_t esp32c3_rtc_time_slowclk_to_us(uint64_t rtc_cycles, + uint32_t period); + +/**************************************************************************** + * Name: esp32c3_rtc_deep_sleep_start + * + * Description: + * Enter deep sleep mode. + * + * Input Parameters: + * wakeup_opt - bit mask wake up reasons to enable + * reject_opt - bit mask of sleep reject reasons. + * + * Returned Value: + * non-zero if sleep was rejected by hardware + * + ****************************************************************************/ + +uint32_t esp32c3_rtc_deep_sleep_start(uint32_t wakeup_opt, + uint32_t reject_opt); + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cpu_freq_set_config + * + * Description: + * Set CPU frequency configuration. + * + * Input Parameters: + * config - CPU frequency configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_clk_cpu_freq_set_config( + const struct esp32c3_cpu_freq_config_s *config); + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_low_init + * + * Description: + * Low level initialize for rtc state machine waiting + * cycles after waking up. + * + * Input Parameters: + * slowclk_period - Re-calibrated slow clock period + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_sleep_low_init(uint32_t slowclk_period); + +/**************************************************************************** + * Name: esp32c3_rtc_clk_cpu_freq_get_config + * + * Description: + * Get the currently used CPU frequency configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * CPU clock configuration structure + * + ****************************************************************************/ + +void esp32c3_rtc_clk_cpu_freq_get_config( + struct esp32c3_cpu_freq_config_s *out_config); + +/**************************************************************************** + * Name: esp32c3_rtc_sleep_set_wakeup_time + * + * Description: + * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. + * + * Input Parameters: + * t - value of RTC counter at which wakeup from sleep will happen. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_sleep_set_wakeup_time(uint64_t t); + +/**************************************************************************** + * Name: esp32c3_rtc_get_time_us + * + * Description: + * Get current value of RTC counter in microseconds + * + * Input Parameters: + * None + * + * Returned Value: + * Current value of RTC counter in microseconds + * + ****************************************************************************/ + +uint64_t esp32c3_rtc_get_time_us(void); + +/**************************************************************************** + * Name: esp32c3_rtc_set_boot_time + * + * Description: + * Set time to RTC register to replace the original boot time. + * + * Input Parameters: + * time_us - set time in microseconds. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32c3_rtc_set_boot_time(uint64_t time_us); + +/**************************************************************************** + * Name: esp32c3_rtc_get_boot_time + * + * Description: + * Get time of RTC register to indicate the original boot time. + * + * Input Parameters: + * None + * + * Returned Value: + * time_us - get time in microseconds. + * + ****************************************************************************/ + +uint64_t esp32c3_rtc_get_boot_time(void); + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +#ifndef CONFIG_RTC_HIRES +time_t up_rtc_time(void); +#endif + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(FAR const struct timespec *ts); + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void); + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC clock/counter. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(FAR struct timespec *tp); +#endif + +#ifdef CONFIG_RTC_ALARM + +/**************************************************************************** + * Name: up_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_setalarm(FAR struct alm_setalarm_s *alminfo); + +/**************************************************************************** + * Name: up_rtc_cancelalarm + * + * Description: + * Cancel an alaram. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_cancelalarm(enum alm_id_e alarmid); + +/**************************************************************************** + * Name: up_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * tp - Location to return the timer match register. + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_rdalarm(FAR struct timespec *tp, uint32_t alarmid); + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: up_rtc_timer_init + * + * Description: + * Init RTC timer. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_timer_init(void); + +#endif /* CONFIG_RTC_DRIVER */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.c b/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.c new file mode 100644 index 00000000000..0ba283d6623 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.c @@ -0,0 +1,565 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "esp32c3_rtc.h" +#include "hardware/esp32c3_tim.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct esp32c3_cbinfo_s +{ + volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ + volatile FAR void *priv; /* Private argurment to accompany callback */ +}; +#endif + +/* This is the private type for the RTC state. It must be cast compatible + * with struct rtc_lowerhalf_s. + */ + +struct esp32c3_lowerhalf_s +{ + /* This is the contained reference to the read-only, lower-half + * operations vtable (which may lie in FLASH or ROM) + */ + + FAR const struct rtc_ops_s *ops; +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct esp32c3_cbinfo_s cbinfo[RTC_ALARM_LAST]; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Prototypes for static methods in struct rtc_ops_s */ + +static int rtc_lh_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime); +static int rtc_lh_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime); +static bool rtc_lh_havesettime(FAR struct rtc_lowerhalf_s *lower); + +#ifdef CONFIG_RTC_ALARM +static void rtc_lh_alarm_callback(FAR void *arg, unsigned int alarmid); +static int rtc_lh_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo); +static int rtc_lh_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo); +static int rtc_lh_cancelalarm(FAR struct rtc_lowerhalf_s *lower, + int alarmid); +static int rtc_lh_rdalarm(FAR struct rtc_lowerhalf_s *lower, + FAR struct lower_rdalarm_s *alarminfo); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ESP32-C3 RTC driver operations */ + +static const struct rtc_ops_s g_rtc_ops = +{ + .rdtime = rtc_lh_rdtime, + .settime = rtc_lh_settime, + .havesettime = rtc_lh_havesettime, +#ifdef CONFIG_RTC_ALARM + .setalarm = rtc_lh_setalarm, + .setrelative = rtc_lh_setrelative, + .cancelalarm = rtc_lh_cancelalarm, + .rdalarm = rtc_lh_rdalarm, +#endif +#ifdef CONFIG_RTC_PERIODIC + .setperiodic = NULL, + .cancelperiodic = NULL, +#endif +#ifdef CONFIG_RTC_IOCTL + .ioctl = NULL, +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + .destroy = NULL, +#endif +}; + +/* ESP32-C3 RTC device state */ + +static struct esp32c3_lowerhalf_s g_rtc_lowerhalf = +{ + .ops = &g_rtc_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_lh_alarm_callback + * + * Description: + * This is the function that is called from the RTC driver when the alarm + * goes off. It just invokes the upper half drivers callback. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static void rtc_lh_alarm_callback(FAR void *arg, unsigned int alarmid) +{ + FAR struct esp32c3_lowerhalf_s *lower; + FAR struct esp32c3_cbinfo_s *cbinfo; + rtc_alarm_callback_t cb; + FAR void *priv; + + DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); + + lower = (struct esp32c3_lowerhalf_s *)arg; + cbinfo = &lower->cbinfo[alarmid]; + + /* Sample and clear the callback information to minimize the window in + * time in which race conditions can occur. + */ + + cb = (rtc_alarm_callback_t)cbinfo->cb; + priv = (FAR void *)cbinfo->priv; + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(priv, alarmid); + } +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_rdtime + * + * Description: + * Returns the current RTC time. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The location in which to return the current RTC time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int rtc_lh_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime) +{ +#if defined(CONFIG_RTC_HIRES) + FAR struct timespec ts; + int ret; + + /* Get the higher resolution time */ + + ret = up_rtc_gettime(&ts); + if (ret < 0) + { + goto errout; + } + + /* Convert the one second epoch time to a struct tm. This operation + * depends on the fact that struct rtc_time and struct tm are cast + * compatible. + */ + + if (!gmtime_r(&ts.tv_sec, (FAR struct tm *)rtctime)) + { + ret = -get_errno(); + goto errout; + } + + return OK; + +errout: + rtcerr("ERROR: failed to get RTC time: %d\n", ret); + return ret; + +#else + time_t timer; + + /* The resolution of time is only 1 second */ + + timer = up_rtc_time(); + + /* Convert the one second epoch time to a struct tm */ + + if (gmtime_r(&timer, (FAR struct tm *)rtctime) == 0) + { + int errcode = get_errno(); + DEBUGASSERT(errcode > 0); + + rtcerr("ERROR: gmtime_r failed: %d\n", errcode); + return -errcode; + } + + return OK; +#endif +} + +/**************************************************************************** + * Name: rtc_lh_settime + * + * Description: + * Implements the settime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The new time to set + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int rtc_lh_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime) +{ + struct timespec ts; + + /* Convert the struct rtc_time to a time_t. Here we assume that struct + * rtc_time is cast compatible with struct tm. + */ + + ts.tv_sec = mktime((FAR struct tm *)rtctime); + ts.tv_nsec = 0; + + /* Now set the time (with a accuracy of seconds) */ + + return up_rtc_settime(&ts); +} + +/**************************************************************************** + * Name: rtc_lh_havesettime + * + * Description: + * Implements the havesettime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Returns true if RTC date-time have been previously set. + * + ****************************************************************************/ + +static bool rtc_lh_havesettime(FAR struct rtc_lowerhalf_s *lower) +{ + if (esp32c3_rtc_get_boot_time() == 0) + { + return false; + } + + return true; +} + +/**************************************************************************** + * Name: rtc_lh_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo) +{ + FAR struct esp32c3_lowerhalf_s *priv; + FAR struct esp32c3_cbinfo_s *cbinfo; + struct alm_setalarm_s lowerinfo; + int ret; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + priv = (FAR struct esp32c3_lowerhalf_s *)lower; + + /* Remember the callback information */ + + cbinfo = &priv->cbinfo[alarminfo->id]; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + + /* Set the alarm */ + + lowerinfo.as_id = alarminfo->id; + lowerinfo.as_cb = rtc_lh_alarm_callback; + lowerinfo.as_arg = priv; + + /* Convert the RTC time to a timespec (1 second accuracy) */ + + lowerinfo.as_time.tv_sec = mktime((FAR struct tm *)&alarminfo->time); + lowerinfo.as_time.tv_nsec = 0; + + /* And set the alarm */ + + ret = up_rtc_setalarm(&lowerinfo); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo) +{ + struct lower_setalarm_s setalarm; + time_t seconds; + int ret = -EINVAL; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + if (alarminfo->reltime > 0) + { + flags = spin_lock_irqsave(NULL); + + seconds = alarminfo->reltime; + gmtime_r(&seconds, (FAR struct tm *)&setalarm.time); + + /* The set the alarm using this absolute time */ + + setalarm.id = alarminfo->id; + setalarm.cb = alarminfo->cb; + setalarm.priv = alarminfo->priv; + ret = rtc_lh_setalarm(lower, &setalarm); + + spin_unlock_irqrestore(NULL, flags); + } + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarmid - the alarm id + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid) +{ + FAR struct esp32c3_lowerhalf_s *priv; + FAR struct esp32c3_cbinfo_s *cbinfo; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); + + priv = (FAR struct esp32c3_lowerhalf_s *)lower; + + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo[alarmid]; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Then cancel the alarm */ + + return up_rtc_cancelalarm((enum alm_id_e)alarmid); +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_rdalarm + * + * Description: + * Query the RTC alarm. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to query the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_rdalarm(FAR struct rtc_lowerhalf_s *lower, + FAR struct lower_rdalarm_s *alarminfo) +{ + struct timespec ts; + int ret; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + flags = spin_lock_irqsave(NULL); + + ret = up_rtc_rdalarm(&ts, alarminfo->id); + localtime_r((FAR const time_t *)&ts.tv_sec, + (FAR struct tm *)alarminfo->time); + + spin_unlock_irqrestore(NULL, flags); + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the ESP32-C3. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +FAR struct rtc_lowerhalf_s *esp32c3_rtc_lowerhalf(void) +{ + return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; +} + +/**************************************************************************** + * Name: esp32c3_rtc_driverinit + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32c3_rtc_driverinit(void) +{ + int ret; + FAR struct rtc_lowerhalf_s *lower; + + /* Instantiate the ESP32-C3 lower-half RTC driver */ + + lower = esp32c3_rtc_lowerhalf(); + if (lower == NULL) + { + return ret; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + } + + /* Init RTC timer */ + + up_rtc_timer_init(); + + return ret; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.h b/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.h new file mode 100644 index 00000000000..452570d0e54 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_LOWERHALF_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_LOWERHALF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_rtc_driverinit + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32c3_rtc_driverinit(void); + +#endif /* CONFIG_RTC_DRIVER */ + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_LOWERHALF_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtcheap.c b/arch/risc-v/src/esp32c3/esp32c3_rtcheap.c new file mode 100644 index 00000000000..c067578dc22 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rtcheap.c @@ -0,0 +1,183 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rtcheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "esp32c3_rtcheap.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static FAR struct mm_heap_s *g_rtcheap; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_rtcheap_initialize + * + * Description: + * Initialize the RTC heap. + * + ****************************************************************************/ + +void esp32c3_rtcheap_initialize(void) +{ + void *start; + size_t size; + + /* These values come from the linker scripts (esp32c3.ld and + * esp32c3.template.ld.) Check boards/risc-v/esp32c3. + */ + + extern uint8_t *_srtcheap; + extern uint8_t *_ertcheap; + + start = (FAR void *)&_srtcheap; + size = (size_t)((uintptr_t)&_ertcheap - (uintptr_t)&_srtcheap); + g_rtcheap = mm_initialize("rtcheap", start, size); +} + +/**************************************************************************** + * Name: esp32c3_rtcheap_malloc + * + * Description: + * Allocate memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_malloc(size_t size) +{ + return mm_malloc(g_rtcheap, size); +} + +/**************************************************************************** + * Name: esp32c3_rtcheap_calloc + * + * Description: + * Calculates the size of the allocation and allocate memory from + * the RTC heap. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_calloc(size_t n, size_t elem_size) +{ + return mm_calloc(g_rtcheap, n, elem_size); +} + +/**************************************************************************** + * Name: esp32c3_rtcheap_realloc + * + * Description: + * Reallocate memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_realloc(void *ptr, size_t size) +{ + return mm_realloc(g_rtcheap, ptr, size); +} + +/**************************************************************************** + * Name: esp32c3_rtcheap_zalloc + * + * Description: + * Allocate and zero memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_zalloc(size_t size) +{ + return mm_zalloc(g_rtcheap, size); +} + +/**************************************************************************** + * Name: esp32c3_rtcheap_free + * + * Description: + * Free memory from the RTC heap. + * + ****************************************************************************/ + +void esp32c3_rtcheap_free(FAR void *mem) +{ + mm_free(g_rtcheap, mem); +} + +/**************************************************************************** + * Name: esp32c3_rtcheap_memalign + * + * Description: + * memalign requests more than enough space from malloc, finds a region + * within that chunk that meets the alignment request and then frees any + * leading or trailing space. + * + * The alignment argument must be a power of two (not checked). 8-byte + * alignment is guaranteed by normal malloc calls. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_memalign(size_t alignment, size_t size) +{ + return mm_memalign(g_rtcheap, alignment, size); +} + +/**************************************************************************** + * Name: esp32c3_rtcheap_heapmember + * + * Description: + * Check if an address lies in the RTC heap. + * + * Parameters: + * mem - The address to check + * + * Return Value: + * true if the address is a member of the RTC heap. false if not + * + ****************************************************************************/ + +bool esp32c3_rtcheap_heapmember(FAR void *mem) +{ + return mm_heapmember(g_rtcheap, mem); +} + +/**************************************************************************** + * Name: esp32c3_rtcheap_mallinfo + * + * Description: + * mallinfo returns a copy of updated current heap information for the + * user heap. + * + ****************************************************************************/ + +int esp32c3_rtcheap_mallinfo(FAR struct mallinfo *info) +{ + return mm_mallinfo(g_rtcheap, info); +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtcheap.h b/arch/risc-v/src/esp32c3/esp32c3_rtcheap.h new file mode 100644 index 00000000000..b0d4b34f5bf --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_rtcheap.h @@ -0,0 +1,146 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_rtcheap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTCHEAP_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTCHEAP_H + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +struct mallinfo; /* Forward reference, see malloc.h */ + +/**************************************************************************** + * Name: esp32c3_rtcheap_initialize + * + * Description: + * Initialize the RTC heap. + * + ****************************************************************************/ + +void esp32c3_rtcheap_initialize(void); + +/**************************************************************************** + * Name: esp32c3_rtcheap_malloc + * + * Description: + * Allocate memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_malloc(size_t size); + +/**************************************************************************** + * Name: esp32c3_rtcheap_calloc + * + * Description: + * Calculates the size of the allocation and allocate memory from + * the RTC heap. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_calloc(size_t n, size_t elem_size); + +/**************************************************************************** + * Name: esp32c3_rtcheap_realloc + * + * Description: + * Reallocate memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_realloc(void *ptr, size_t size); + +/**************************************************************************** + * Name: esp32c3_rtcheap_zalloc + * + * Description: + * Allocate and zero memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_zalloc(size_t size); + +/**************************************************************************** + * Name: esp32c3_rtcheap_free + * + * Description: + * Free memory from the RTC heap. + * + ****************************************************************************/ + +void esp32c3_rtcheap_free(FAR void *mem); + +/**************************************************************************** + * Name: esp32c3_rtcheap_memalign + * + * Description: + * memalign requests more than enough space from malloc, finds a region + * within that chunk that meets the alignment request and then frees any + * leading or trailing space. + * + * The alignment argument must be a power of two (not checked). 8-byte + * alignment is guaranteed by normal malloc calls. + * + ****************************************************************************/ + +void *esp32c3_rtcheap_memalign(size_t alignment, size_t size); + +/**************************************************************************** + * Name: esp32c3_rtcheap_heapmember + * + * Description: + * Check if an address lies in the RTC heap. + * + * Parameters: + * mem - The address to check + * + * Return Value: + * true if the address is a member of the RTC heap. false if not + * + ****************************************************************************/ + +bool esp32c3_rtcheap_heapmember(FAR void *mem); + +/**************************************************************************** + * Name: esp32c3_rtcheap_mallinfo + * + * Description: + * mallinfo returns a copy of updated current heap information for the + * user heap. + * + ****************************************************************************/ + +int esp32c3_rtcheap_mallinfo(FAR struct mallinfo *info); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTCHEAP_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_serial.c b/arch/risc-v/src/esp32c3/esp32c3_serial.c index 196a8b0ff88..08f3d68a0fe 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_serial.c +++ b/arch/risc-v/src/esp32c3/esp32c3_serial.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -122,6 +123,10 @@ static bool esp32c3_txempty(struct uart_dev_s *dev); static void esp32c3_send(struct uart_dev_s *dev, int ch); static int esp32c3_receive(struct uart_dev_s *dev, unsigned int *status); static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg); +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool esp32c3_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif /**************************************************************************** * Private Data @@ -144,7 +149,7 @@ static struct uart_ops_s g_uart_ops = .receive = esp32c3_receive, .ioctl = esp32c3_ioctl, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, + .rxflowcontrol = esp32c3_rxflowcontrol, #endif }; @@ -244,16 +249,16 @@ static int uart_handler(int irq, FAR void *context, FAR void *arg) if (int_status & tx_mask) { - uart_xmitchars(dev); - modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask); + uart_xmitchars(dev); + modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask); } /* Rx fifo timeout interrupt or rx fifo full interrupt */ if (int_status & rx_mask) { - uart_recvchars(dev); - modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask); + uart_recvchars(dev); + modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask); } return OK; @@ -332,6 +337,44 @@ static int esp32c3_setup(struct uart_dev_s *dev) esp32c3_lowputc_stop_length(priv); +#ifdef CONFIG_SERIAL_IFLOWCONTROL + /* Configure the input flow control */ + + if (priv->iflow) + { + /* Enable input flow control and set the RX FIFO threshold + * to assert the RTS line to half the RX FIFO buffer. + * It will then save some space on the hardware fifo to + * remaining bytes that may arrive after RTS be asserted + * and before the transmitter stops sending data. + */ + + esp32c3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2), + true); + } + else + { + /* Just disable input flow control, threshold parameter + * will be discarded. + */ + + esp32c3_lowputc_set_iflow(priv, 0 , false); + } + +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + /* Configure the ouput flow control */ + + if (priv->oflow) + { + esp32c3_lowputc_set_oflow(priv, true); + } + else + { + esp32c3_lowputc_set_oflow(priv, false); + } +#endif + /* No Tx idle interval */ esp32c3_lowputc_set_tx_idle_time(priv, 0); @@ -725,6 +768,13 @@ static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg) termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= (priv->oflow) ? CCTS_OFLOW : 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= (priv->iflow) ? CRTS_IFLOW : 0; +#endif + /* Set the baud rate in ther termiosp using the * cfsetispeed interface. */ @@ -764,6 +814,12 @@ static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg) uint8_t parity; uint8_t bits; uint8_t stop2; +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; +#endif if (!termiosp) { @@ -815,6 +871,13 @@ static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg) stop2 = (termiosp->c_cflag & CSTOPB) ? 1 : 0; +#ifdef CONFIG_SERIAL_IFLOWCONTROL + iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif + /* Verify that all settings are valid before * performing the changes. */ @@ -827,6 +890,12 @@ static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg) priv->parity = parity; priv->bits = bits; priv->stop_b2 = stop2; +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = iflow; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = oflow; +#endif /* Effect the changes immediately - note that we do not * implement TCSADRAIN or TCSAFLUSH, only TCSANOW option. @@ -852,6 +921,78 @@ static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg) return ret; } +/**************************************************************************** + * Name: esp32c3_rxflowcontrol + * + * Description: + * Called when upper half RX buffer is full (or exceeds configured + * watermark levels if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if UART activated RX flow control to block more incoming + * data. + * NOTE: ESP32-C3 has a hardware RX FIFO threshold mechanism to control + * RTS line and to stop receiving data. This is very similar to the concept + * behind upper watermark level. The hardware threshold is used here + * to control the RTS line. When setting the threshold to zero, RTS will + * immediately be asserted. If nbuffered = 0 or the lower watermark is + * crossed and the serial driver decides to disable RX flow control, the + * threshold will be changed to UART_RX_FLOW_THRHD_VALUE, which is almost + * half the HW RX FIFO capacity. It keeps some space to keep the data + * received between the RTS assertion and the stop by the sender. + * + * Input Parameters: + * dev - UART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool esp32c3_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + bool ret = false; + struct esp32c3_uart_s *priv = dev->priv; + if (priv->iflow) + { + if (nbuffered == 0 || upper == false) + { + /* Empty buffer, RTS should be de-asserted and logic in above + * layers should re-enable RX interrupt. + */ + + esp32c3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2), + true); + esp32c3_rxint(dev, true); + ret = false; + } + else + { + /* If the RX buffer is not zero and watermarks are not enabled, + * then this function is called to announce RX buffer is full. + * The first thing it should do is to immediately assert RTS. + * Software RX FIFO is full, so besides asserting RTS, it's + * necessary to disable RX interrupts to prevent remaining bytes + * (that arrive after asserting RTS) to be pushed to the + * SW RX FIFO. + */ + + esp32c3_lowputc_set_iflow(priv, 0 , true); + esp32c3_rxint(dev, false); + ret = true; + } + } + + return ret; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/esp32c3/esp32c3_sha.c b/arch/risc-v/src/esp32c3/esp32c3_sha.c new file mode 100644 index 00000000000..773ad237ec4 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_sha.c @@ -0,0 +1,1715 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_sha.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR + +#include +#include +#include +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "hardware/esp32c3_sha.h" +#include "hardware/esp32c3_system.h" + +#include "esp32c3_sha.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PUT_UINT32_BE(n,b,i) \ +{ \ + (b)[(i)] = (unsigned char) ((n) >> 24); \ + (b)[(i) + 1] = (unsigned char) ((n) >> 16); \ + (b)[(i) + 2] = (unsigned char) ((n) >> 8); \ + (b)[(i) + 3] = (unsigned char) ((n)); \ +} + +#define GET_UINT64_BE(n,b,i) \ +{ \ + (n) = ((uint64_t) (b)[(i)] << 56) \ + | ((uint64_t) (b)[(i) + 1] << 48) \ + | ((uint64_t) (b)[(i) + 2] << 40) \ + | ((uint64_t) (b)[(i) + 3] << 32) \ + | ((uint64_t) (b)[(i) + 4] << 24) \ + | ((uint64_t) (b)[(i) + 5] << 16) \ + | ((uint64_t) (b)[(i) + 6] << 8) \ + | ((uint64_t) (b)[(i) + 7]); \ +} + +#define PUT_UINT64_BE(n,b,i) \ +{ \ + (b)[(i)] = (uint8_t) ((n) >> 56); \ + (b)[(i) + 1] = (uint8_t) ((n) >> 48); \ + (b)[(i) + 2] = (uint8_t) ((n) >> 40); \ + (b)[(i) + 3] = (uint8_t) ((n) >> 32); \ + (b)[(i) + 4] = (uint8_t) ((n) >> 24); \ + (b)[(i) + 5] = (uint8_t) ((n) >> 16); \ + (b)[(i) + 6] = (uint8_t) ((n) >> 8); \ + (b)[(i) + 7] = (uint8_t) ((n)); \ +} + +#define SHR(x,n) ((x) >> (n)) +#define ROTR(x,n) (SHR((x),(n)) | ((x) << (64 - (n)))) + +#define S0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x, 7)) +#define S1(x) (ROTR(x,19) ^ ROTR(x,61) ^ SHR(x, 6)) + +#define S2(x) (ROTR(x,28) ^ ROTR(x,34) ^ ROTR(x,39)) +#define S3(x) (ROTR(x,14) ^ ROTR(x,18) ^ ROTR(x,41)) + +#define F0(x,y,z) (((x) & (y)) | ((z) & ((x) | (y)))) +#define F1(x,y,z) ((z) ^ ((x) & ((y) ^ (z)))) + +#define P(a,b,c,d,e,f,g,h,x,K) \ + do \ + { \ + temp1 = (h) + S3(e) + F1((e),(f),(g)) + (K) + (x); \ + temp2 = S2(a) + F0((a),(b),(c)); \ + (d) += temp1; \ + (h) = temp1 + temp2; \ + } while(0) + +#define SHA1_BLK_SIZE (20) +#define SHA2_BLK_SIZE (32) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_sha_inited; +static sem_t g_sha_sem = SEM_INITIALIZER(1); +static const unsigned char esp32c3_sha_padding[64] = +{ + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static const uint64_t K[80] = +{ + UINT64_C(0x428a2f98d728ae22), UINT64_C(0x7137449123ef65cd), + UINT64_C(0xb5c0fbcfec4d3b2f), UINT64_C(0xe9b5dba58189dbbc), + UINT64_C(0x3956c25bf348b538), UINT64_C(0x59f111f1b605d019), + UINT64_C(0x923f82a4af194f9b), UINT64_C(0xab1c5ed5da6d8118), + UINT64_C(0xd807aa98a3030242), UINT64_C(0x12835b0145706fbe), + UINT64_C(0x243185be4ee4b28c), UINT64_C(0x550c7dc3d5ffb4e2), + UINT64_C(0x72be5d74f27b896f), UINT64_C(0x80deb1fe3b1696b1), + UINT64_C(0x9bdc06a725c71235), UINT64_C(0xc19bf174cf692694), + UINT64_C(0xe49b69c19ef14ad2), UINT64_C(0xefbe4786384f25e3), + UINT64_C(0x0fc19dc68b8cd5b5), UINT64_C(0x240ca1cc77ac9c65), + UINT64_C(0x2de92c6f592b0275), UINT64_C(0x4a7484aa6ea6e483), + UINT64_C(0x5cb0a9dcbd41fbd4), UINT64_C(0x76f988da831153b5), + UINT64_C(0x983e5152ee66dfab), UINT64_C(0xa831c66d2db43210), + UINT64_C(0xb00327c898fb213f), UINT64_C(0xbf597fc7beef0ee4), + UINT64_C(0xc6e00bf33da88fc2), UINT64_C(0xd5a79147930aa725), + UINT64_C(0x06ca6351e003826f), UINT64_C(0x142929670a0e6e70), + UINT64_C(0x27b70a8546d22ffc), UINT64_C(0x2e1b21385c26c926), + UINT64_C(0x4d2c6dfc5ac42aed), UINT64_C(0x53380d139d95b3df), + UINT64_C(0x650a73548baf63de), UINT64_C(0x766a0abb3c77b2a8), + UINT64_C(0x81c2c92e47edaee6), UINT64_C(0x92722c851482353b), + UINT64_C(0xa2bfe8a14cf10364), UINT64_C(0xa81a664bbc423001), + UINT64_C(0xc24b8b70d0f89791), UINT64_C(0xc76c51a30654be30), + UINT64_C(0xd192e819d6ef5218), UINT64_C(0xd69906245565a910), + UINT64_C(0xf40e35855771202a), UINT64_C(0x106aa07032bbd1b8), + UINT64_C(0x19a4c116b8d2d0c8), UINT64_C(0x1e376c085141ab53), + UINT64_C(0x2748774cdf8eeb99), UINT64_C(0x34b0bcb5e19b48a8), + UINT64_C(0x391c0cb3c5c95a63), UINT64_C(0x4ed8aa4ae3418acb), + UINT64_C(0x5b9cca4f7763e373), UINT64_C(0x682e6ff3d6b2b8a3), + UINT64_C(0x748f82ee5defb2fc), UINT64_C(0x78a5636f43172f60), + UINT64_C(0x84c87814a1f0ab72), UINT64_C(0x8cc702081a6439ec), + UINT64_C(0x90befffa23631e28), UINT64_C(0xa4506cebde82bde9), + UINT64_C(0xbef9a3f7b2c67915), UINT64_C(0xc67178f2e372532b), + UINT64_C(0xca273eceea26619c), UINT64_C(0xd186b8c721c0c207), + UINT64_C(0xeada7dd6cde0eb1e), UINT64_C(0xf57d4f7fee6ed178), + UINT64_C(0x06f067aa72176fba), UINT64_C(0x0a637dc5a2c898a6), + UINT64_C(0x113f9804bef90dae), UINT64_C(0x1b710b35131c471b), + UINT64_C(0x28db77f523047d84), UINT64_C(0x32caab7b40c72493), + UINT64_C(0x3c9ebe0a15c9bebc), UINT64_C(0x431d67c49c100d4c), + UINT64_C(0x4cc5d4becb3e42b6), UINT64_C(0x597f299cfc657e2a), + UINT64_C(0x5fcb6fab3ad6faec), UINT64_C(0x6c44198c4a475817) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_sha1_block + * + * Description: + * Performs SHA1 on multiple blocks at a time. + * + * Input Parameters: + * ctx - The SHA1 context + * data - Input message to be hashed on single block + * len - Length of the input message on single block + * buf - Input message to be hashed on multiple blocks + * buf_len - Length of the input message on multiple blocks + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +static int esp32c3_sha1_block(struct esp32c3_sha1_context_s *ctx, + const uint8_t *data, size_t len, + uint8_t *buf, size_t buf_len) +{ + uint32_t *data_words = NULL; + size_t blk_len = 0; + size_t blk_word_len = 0; + int num_block = 0; + int i; + int j; + + blk_len = 64; + blk_word_len = blk_len / 4; + num_block = len / blk_len; + + putreg32(ctx->mode, SHA_MODE_REG); + + if (buf_len != 0) + { + data_words = (uint32_t *)buf; + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < blk_word_len; i++) + { + putreg32(data_words[i], SHA_M_0_REG + i * 4); + } + + if (ctx->first_block) + { + putreg32(1, SHA_START_REG); + } + else + { + putreg32(1, SHA_CONTINUE_REG); + } + + ctx->first_block = false; + } + + for (j = 0; j < num_block; j++) + { + data_words = (uint32_t *)(data + blk_len * j); + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < blk_word_len; i++) + { + putreg32(data_words[i], SHA_M_0_REG + i * 4); + } + + if (ctx->first_block) + { + putreg32(1, SHA_START_REG); + } + else + { + putreg32(1, SHA_CONTINUE_REG); + } + + ctx->first_block = false; + } + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < 5; i ++) + { + ctx->state[i] = getreg32(SHA_H_0_REG + i * 4); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha256_block + * + * Description: + * Performs SHA256 on multiple blocks at a time. + * + * Input Parameters: + * ctx - The SHA256 context + * data - Input message to be hashed on single block + * len - Length of the input message on single block + * buf - Input message to be hashed on multiple blocks + * buf_len - Length of the input message on multiple blocks + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +static int esp32c3_sha256_block(struct esp32c3_sha256_context_s *ctx, + const uint8_t *data, size_t len, + uint8_t *buf, size_t buf_len) +{ + uint32_t *data_words = NULL; + size_t blk_len = 0; + size_t blk_word_len = 0; + int num_block = 0; + int i; + int j; + + blk_len = 64; + blk_word_len = blk_len / 4; + num_block = len / blk_len; + + putreg32(ctx->mode, SHA_MODE_REG); + + if (buf_len != 0) + { + data_words = (uint32_t *)buf; + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < blk_word_len; i++) + { + putreg32(data_words[i], SHA_M_0_REG + i * 4); + } + + if (ctx->first_block) + { + putreg32(1, SHA_START_REG); + } + else + { + putreg32(1, SHA_CONTINUE_REG); + } + + ctx->first_block = false; + } + + for (j = 0; j < num_block; j++) + { + data_words = (uint32_t *)(data + blk_len * j); + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < blk_word_len; i++) + { + putreg32(data_words[i], SHA_M_0_REG + i * 4); + } + + if (ctx->first_block) + { + putreg32(1, SHA_START_REG); + } + else + { + putreg32(1, SHA_CONTINUE_REG); + } + + ctx->first_block = false; + } + + while (getreg32(SHA_BUSY_REG)) + { + } + + if (ctx->mode == ESP32C3_SHA2_256) + { + num_block = 8; + } + else + { + num_block = 7; + } + + for (i = 0; i < num_block; i ++) + { + ctx->state[i] = getreg32(SHA_H_0_REG + i * 4); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha512_block + * + * Description: + * Performs SHA512 on multiple blocks at a time. + * + * Input Parameters: + * ctx - The SHA512 context + * data - Input message to be hashed + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +static int esp32c3_sha512_block(struct esp32c3_sha512_context_s *ctx, + const uint8_t *data) +{ + int i; + int j; + uint64_t temp1, temp2, W[80]; + uint64_t A, B, C, D, E, F, G, H; + + for (i = 0; i < 16; i++) + { + GET_UINT64_BE(W[i], data, i << 3); + } + + for (; i < 80; i++) + { + W[i] = S1(W[i - 2]) + W[i - 7] + S0(W[i - 15]) + W[i - 16]; + } + + A = ctx->state[0]; + B = ctx->state[1]; + C = ctx->state[2]; + D = ctx->state[3]; + E = ctx->state[4]; + F = ctx->state[5]; + G = ctx->state[6]; + H = ctx->state[7]; + i = 0; + j = 0; + + do + { + P(A, B, C, D, E, F, G, H, W[i++], K[j++]); + P(H, A, B, C, D, E, F, G, W[i++], K[j++]); + P(G, H, A, B, C, D, E, F, W[i++], K[j++]); + P(F, G, H, A, B, C, D, E, W[i++], K[j++]); + P(E, F, G, H, A, B, C, D, W[i++], K[j++]); + P(D, E, F, G, H, A, B, C, W[i++], K[j++]); + P(C, D, E, F, G, H, A, B, W[i++], K[j++]); + P(B, C, D, E, F, G, H, A, W[i++], K[j++]); + } + while (i < 80); + + ctx->state[0] += A; + ctx->state[1] += B; + ctx->state[2] += C; + ctx->state[3] += D; + ctx->state[4] += E; + ctx->state[5] += F; + ctx->state[6] += G; + ctx->state[7] += H; + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_sha1_init + * + * Description: + * Initializes a SHA-1 context. + * + * Input Parameters: + * ctx - The SHA-1 context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha1_init(struct esp32c3_sha1_context_s *ctx) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha1_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha1_starts + * + * Description: + * Starts a SHA-1 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-1 context to initialize + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha1_starts(struct esp32c3_sha1_context_s *ctx) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha1_context_s)); + ctx->mode = ESP32C3_SHA1_1; + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha1_update + * + * Description: + * Feeds an input buffer into an ongoing SHA-1 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-1 context to use + * input - The buffer holding the input data + * ilen - The length of the input data in Bytes + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha1_update(struct esp32c3_sha1_context_s *ctx, + const unsigned char *input, + size_t ilen) +{ + int ret; + size_t fill; + uint32_t left; + uint32_t len; + uint32_t local_len = 0; + int i; + + if (!ilen || (input == NULL)) + { + return OK; + } + + left = ctx->total[0] & 0x3f; + fill = 64 - left; + + ctx->total[0] += ilen; + ctx->total[0] &= UINT32_MAX; + + if (ctx->total[0] < ilen) + { + ctx->total[1]++; + } + + if (left && ilen >= fill) + { + memcpy((void *) (ctx->buffer + left), input, fill); + + input += fill; + ilen -= fill; + left = 0; + local_len = 64; + } + + len = (ilen / 64) * 64; + if (len || local_len) + { + ret = nxsem_wait(&g_sha_sem); + if (ret < 0) + { + return ret; + } + + if (ctx->sha_state == ESP32C3_SHA_STATE_INIT) + { + ctx->first_block = true; + + ctx->sha_state = ESP32C3_SHA_STATE_IN_PROCESS; + } + else if (ctx->sha_state == ESP32C3_SHA_STATE_IN_PROCESS) + { + ctx->first_block = false; + for (i = 0; i < 5; i++) + { + putreg32(ctx->state[i], SHA_H_0_REG + i * 4); + } + } + + ret = esp32c3_sha1_block(ctx, input, len, ctx->buffer, local_len); + ret |= nxsem_post(&g_sha_sem); + + if (ret != 0) + { + return ret; + } + } + + if (ilen > 0) + { + memcpy((void *) (ctx->buffer + left), input + len, ilen - len); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha1_finish + * + * Description: + * Finishes the SHA-1 operation, + * and writes the result to the output buffer. + * + * Input Parameters: + * ctx - The SHA-1 context to use + * output - The SHA-1 checksum result + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha1_finish(struct esp32c3_sha1_context_s *ctx, + unsigned char output[20]) +{ + int ret; + uint32_t last; + uint32_t padn; + uint32_t high; + uint32_t low; + unsigned char msglen[8]; + + high = (ctx->total[0] >> 29) | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); + + PUT_UINT32_BE(high, msglen, 0); + PUT_UINT32_BE(low, msglen, 4); + + last = ctx->total[0] & 0x3f; + padn = (last < 56) ? (56 - last) : (120 - last); + + ret = esp32c3_sha1_update(ctx, esp32c3_sha_padding, padn); + if (ret != 0) + { + return ret; + } + + ret = esp32c3_sha1_update(ctx, msglen, 8); + if (ret != 0) + { + return ret; + } + + memcpy(output, ctx->state, SHA1_BLK_SIZE); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_sha1_free + * + * Description: + * Clears a SHA-1 context. + * + * Input Parameters: + * ctx - The SHA-1 context to clear + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha1_free(struct esp32c3_sha1_context_s *ctx) +{ + if (ctx == NULL) + { + return; + } + + memset(ctx, 0, sizeof(struct esp32c3_sha1_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha256_init + * + * Description: + * Initializes a SHA-256 context. + * + * Input Parameters: + * ctx - The SHA-256 context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha256_init(struct esp32c3_sha256_context_s *ctx) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha256_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha256_starts + * + * Description: + * Starts a SHA-224 or SHA-256 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-256 context to initialize + * is224 - Determines which function to use + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha256_starts(struct esp32c3_sha256_context_s *ctx, bool is224) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha256_context_s)); + + if (is224) + { + ctx->mode = ESP32C3_SHA2_224; + } + else + { + ctx->mode = ESP32C3_SHA2_256; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha256_update + * + * Description: + * Feeds an input buffer into an ongoing SHA-224 or SHA-256 + * checksum calculation. + * + * Input Parameters: + * ctx - The SHA-256 context to use + * input - The buffer holding the input data + * ilen - The length of the input data in Bytes + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha256_update(struct esp32c3_sha256_context_s *ctx, + const unsigned char *input, + size_t ilen) +{ + int ret = 0; + size_t fill; + uint32_t left; + uint32_t len; + uint32_t local_len = 0; + int i; + + if (ilen == 0) + { + return OK; + } + + left = ctx->total[0] & 0x3f; + fill = 64 - left; + + ctx->total[0] += ilen; + ctx->total[0] &= UINT32_MAX; + + if (ctx->total[0] < ilen) + { + ctx->total[1]++; + } + + /* Check if any data pending from previous call to this API */ + + if (left && ilen >= fill) + { + memcpy((void *) (ctx->buffer + left), input, fill); + + input += fill; + ilen -= fill; + left = 0; + local_len = 64; + } + + len = (ilen / 64) * 64; + + if (len || local_len) + { + ret = nxsem_wait(&g_sha_sem); + if (ret < 0) + { + return ret; + } + + if (ctx->sha_state == ESP32C3_SHA_STATE_INIT) + { + ctx->first_block = true; + ctx->sha_state = ESP32C3_SHA_STATE_IN_PROCESS; + } + else if (ctx->sha_state == ESP32C3_SHA_STATE_IN_PROCESS) + { + ctx->first_block = false; + int block_num = (ctx->mode == ESP32C3_SHA2_224) ? 7 : 8; + for (i = 0; i < block_num; i++) + { + putreg32(ctx->state[i], SHA_H_0_REG + i * 4); + } + } + + ret = esp32c3_sha256_block(ctx, input, len, ctx->buffer, local_len); + ret |= nxsem_post(&g_sha_sem); + + if (ret != 0) + { + return ret; + } + } + + if (ilen > 0) + { + memcpy((void *) (ctx->buffer + left), input + len, ilen - len); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha256_finish + * + * Description: + * Finishes the SHA-224 or SHA-256 operation, and writes the result to + * the output buffer. + * + * Input Parameters: + * ctx - The SHA-256 context to use + * output - The SHA-256 checksum result + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha256_finish(struct esp32c3_sha256_context_s *ctx, + unsigned char output[32]) +{ + int ret; + uint32_t last; + uint32_t padn; + uint32_t high; + uint64_t low; + unsigned char msglen[8]; + + high = (ctx->total[0] >> 29) | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); + + PUT_UINT32_BE(high, msglen, 0); + PUT_UINT32_BE(low, msglen, 4); + + last = ctx->total[0] & 0x3f; + padn = (last < 56) ? (56 - last) : (120 - last); + + ret = esp32c3_sha256_update(ctx, esp32c3_sha_padding, padn); + if (ret != 0) + { + return ret; + } + + ret = esp32c3_sha256_update(ctx, msglen, 8); + if (ret != 0) + { + return ret; + } + + memcpy(output, ctx->state, SHA2_BLK_SIZE); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_sha256_free + * + * Description: + * Clears a SHA-256 context. + * + * Input Parameters: + * ctx - The SHA-256 context to clear + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha256_free(struct esp32c3_sha256_context_s *ctx) +{ + if (ctx == NULL) + { + return; + } + + memset(ctx, 0, sizeof(struct esp32c3_sha256_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha512_init + * + * Description: + * Initializes a SHA-512 context. + * + * Input Parameters: + * ctx - The SHA-512 context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha512_init(struct esp32c3_sha512_context_s *ctx) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha512_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha512_starts + * + * Description: + * Starts a SHA-384 or SHA-512 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-512 context to initialize + * is384 - Determines which function to use + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha512_starts(struct esp32c3_sha512_context_s *ctx, bool is384) +{ + int ret = 0; + + if (is384) + { + ctx->mode = ESP32C3_SHA3_384; + + ctx->total[0] = 0; + ctx->total[1] = 0; + + ctx->state[0] = UINT64_C(0xcbbb9d5dc1059ed8); + ctx->state[1] = UINT64_C(0x629a292a367cd507); + ctx->state[2] = UINT64_C(0x9159015a3070dd17); + ctx->state[3] = UINT64_C(0x152fecd8f70e5939); + ctx->state[4] = UINT64_C(0x67332667ffc00b31); + ctx->state[5] = UINT64_C(0x8eb44a8768581511); + ctx->state[6] = UINT64_C(0xdb0c2e0d64f98fa7); + ctx->state[7] = UINT64_C(0x47b5481dbefa4fa4); + } + else + { + ctx->mode = ESP32C3_SHA3_512; + + ctx->total[0] = 0; + ctx->total[1] = 0; + + ctx->state[0] = UINT64_C(0x6a09e667f3bcc908); + ctx->state[1] = UINT64_C(0xbb67ae8584caa73b); + ctx->state[2] = UINT64_C(0x3c6ef372fe94f82b); + ctx->state[3] = UINT64_C(0xa54ff53a5f1d36f1); + ctx->state[4] = UINT64_C(0x510e527fade682d1); + ctx->state[5] = UINT64_C(0x9b05688c2b3e6c1f); + ctx->state[6] = UINT64_C(0x1f83d9abfb41bd6b); + ctx->state[7] = UINT64_C(0x5be0cd19137e2179); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_sha512_update + * + * Description: + * Feeds an input buffer into an ongoing SHA-384 or SHA-512 + * checksum calculation. + * + * Input Parameters: + * ctx - The SHA-512 context to use + * input - The buffer holding the input data + * ilen - The length of the input data in Bytes + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha512_update(struct esp32c3_sha512_context_s *ctx, + const unsigned char *input, + size_t ilen) +{ + size_t fill; + uint32_t left; + const uint8_t *input_buffer = (const uint8_t *)input; + + left = (uint32_t) (ctx->total[0] & 0x7f); + fill = 128 - left; + + ctx->total[0] += (uint64_t)ilen; + + if (ctx->total[0] < (uint64_t)ilen) + { + ctx->total[1]++; + } + + if (left && ilen >= fill) + { + memcpy(ctx->buffer + left, input_buffer, fill); + + esp32c3_sha512_block(ctx, ctx->buffer); + + input_buffer += fill; + ilen -= fill; + left = 0; + } + + while (ilen >= 128) + { + esp32c3_sha512_block(ctx, input_buffer); + + input_buffer += 128; + ilen -= 128; + } + + if (ilen > 0) + { + memcpy((void *) (ctx->buffer + left), input_buffer, ilen); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha512_finish + * + * Description: + * Finishes the SHA-384 or SHA-512 operation, and writes the result to + * the output buffer. + * + * Input Parameters: + * ctx - The SHA-512 context to use + * output - The SHA-512 checksum result + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha512_finish(struct esp32c3_sha512_context_s *ctx, + unsigned char output[64]) +{ + uint8_t used; + uint64_t high; + uint64_t low; + uint8_t *output_buffer = (uint8_t *)output; + + used = ctx->total[0] & 0x7f; + ctx->buffer[used++] = 0x80; + + if (used <= 112) + { + memset(ctx->buffer + used, 0, 112 - used); + } + else + { + memset(ctx->buffer + used, 0, 128 - used); + esp32c3_sha512_block(ctx, ctx->buffer); + memset(ctx->buffer, 0, 112); + } + + high = (ctx->total[0] >> 61) | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); + + PUT_UINT64_BE(high, ctx->buffer, 112); + PUT_UINT64_BE(low, ctx->buffer, 120); + + esp32c3_sha512_block(ctx, ctx->buffer); + + PUT_UINT64_BE(ctx->state[0], output_buffer, 0); + PUT_UINT64_BE(ctx->state[1], output_buffer, 8); + PUT_UINT64_BE(ctx->state[2], output_buffer, 16); + PUT_UINT64_BE(ctx->state[3], output_buffer, 24); + PUT_UINT64_BE(ctx->state[4], output_buffer, 32); + PUT_UINT64_BE(ctx->state[5], output_buffer, 40); + + if (ctx->mode == ESP32C3_SHA3_512) + { + PUT_UINT64_BE(ctx->state[6], output_buffer, 48); + PUT_UINT64_BE(ctx->state[7], output_buffer, 56); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha512_free + * + * Description: + * Clears a SHA-512 context. + * + * Input Parameters: + * ctx - The SHA-512 context to clear + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha512_free(struct esp32c3_sha512_context_s *ctx) +{ + if (ctx == NULL) + { + return; + } + + memset(ctx, 0, sizeof(struct esp32c3_sha1_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha_init + * + * Description: + * Initialize ESP32-C3 SHA hardware. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha_init(void) +{ + if (!g_sha_inited) + { + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, 0, SYSTEM_CRYPTO_SHA_CLK_EN); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_CRYPTO_SHA_RST, 0); + g_sha_inited = true; + } + else + { + return -EBUSY; + } + + return OK; +} + +#endif + +/**************************************************************************** + * Test Functions + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR_TEST + +/**************************************************************************** + * Name: esp32c3_sha1_self_test + * + * Description: + * Checkup routine + * + * Input Parameters: + * verbose - The result output or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_sha1_self_test(bool verbose) +{ + int i; + int j; + int buflen; + int ret = 0; + unsigned char buf[1024]; + unsigned char sha1sum[20]; + struct esp32c3_sha1_context_s ctx; + + /* FIPS-180-1 test vectors */ + + const unsigned char sha1_test_buf[3][57] = + { + { + "abc" + }, + + { + "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" + }, + + { + "" + } + }; + + const size_t sha1_test_buflen[3] = + { + 3, 56, 1000 + }; + + const unsigned char sha1_test_sum[3][20] = + { + { + 0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a, 0xba, 0x3e, + 0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c, 0x9c, 0xd0, 0xd8, 0x9d + }, + + { + 0x84, 0x98, 0x3e, 0x44, 0x1c, 0x3b, 0xd2, 0x6e, 0xba, 0xae, + 0x4a, 0xa1, 0xf9, 0x51, 0x29, 0xe5, 0xe5, 0x46, 0x70, 0xf1 + }, + + { + 0x34, 0xaa, 0x97, 0x3c, 0xd4, 0xc4, 0xda, 0xa4, 0xf6, 0x1e, + 0xeb, 0x2b, 0xdb, 0xad, 0x27, 0x31, 0x65, 0x34, 0x01, 0x6f + } + }; + + esp32c3_sha1_init(&ctx); + + for (i = 0; i < 3; i++) + { + if (verbose) + { + syslog(LOG_INFO, " SHA-1 test #%d: ", i + 1); + } + + ret = esp32c3_sha1_starts(&ctx); + if (ret != 0) + { + goto fail; + } + + if (i == 2) + { + memset(buf, 'a', buflen = 1000); + + for (j = 0; j < 1000; j++) + { + ret = esp32c3_sha1_update(&ctx, buf, buflen); + if (ret != 0) + { + goto fail; + } + } + } + else + { + ret = esp32c3_sha1_update(&ctx, + sha1_test_buf[i], + sha1_test_buflen[i]); + if (ret != 0) + { + goto fail; + } + } + + ret = esp32c3_sha1_finish(&ctx, sha1sum); + if (ret != 0) + { + goto fail; + } + + if (memcmp(sha1sum, sha1_test_sum[i], 20) != 0) + { + ret = 1; + goto fail; + } + + if (verbose) + { + syslog(LOG_INFO, "passed\n"); + } + } + + if (verbose) + { + syslog(LOG_INFO, "\n"); + } + + goto exit; + +fail: + if (verbose) + { + syslog(LOG_INFO, "failed\n"); + } + +exit: + esp32c3_sha1_free(&ctx); + + return (ret); +} + +/**************************************************************************** + * Name: esp32c3_sha256_self_test + * + * Description: + * Checkup routine + * + * Input Parameters: + * verbose - The result output or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_sha256_self_test(bool verbose) +{ + int i; + int j; + int k; + int buflen; + int ret = 0; + unsigned char *buf; + unsigned char sha256sum[32]; + struct esp32c3_sha256_context_s ctx; + + /* FIPS-180-2 test vectors */ + + const unsigned char sha256_test_buf[3][57] = + { + { + "abc" + }, + + { + "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" + }, + + { + "" + } + }; + + const size_t sha256_test_buflen[3] = + { + 3, 56, 1000 + }; + + const unsigned char sha256_test_sum[6][32] = + { + /* SHA-224 test vectors */ + + { + 0x23, 0x09, 0x7d, 0x22, 0x34, 0x05, 0xd8, 0x22, + 0x86, 0x42, 0xa4, 0x77, 0xbd, 0xa2, 0x55, 0xb3, + 0x2a, 0xad, 0xbc, 0xe4, 0xbd, 0xa0, 0xb3, 0xf7, + 0xe3, 0x6c, 0x9d, 0xa7 + }, + + { + 0x75, 0x38, 0x8b, 0x16, 0x51, 0x27, 0x76, 0xcc, + 0x5d, 0xba, 0x5d, 0xa1, 0xfd, 0x89, 0x01, 0x50, + 0xb0, 0xc6, 0x45, 0x5c, 0xb4, 0xf5, 0x8b, 0x19, + 0x52, 0x52, 0x25, 0x25 + }, + + { + 0x20, 0x79, 0x46, 0x55, 0x98, 0x0c, 0x91, 0xd8, + 0xbb, 0xb4, 0xc1, 0xea, 0x97, 0x61, 0x8a, 0x4b, + 0xf0, 0x3f, 0x42, 0x58, 0x19, 0x48, 0xb2, 0xee, + 0x4e, 0xe7, 0xad, 0x67 + }, + + /* SHA-256 test vectors */ + + { + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, + 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, + 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad + }, + + { + 0x24, 0x8d, 0x6a, 0x61, 0xd2, 0x06, 0x38, 0xb8, + 0xe5, 0xc0, 0x26, 0x93, 0x0c, 0x3e, 0x60, 0x39, + 0xa3, 0x3c, 0xe4, 0x59, 0x64, 0xff, 0x21, 0x67, + 0xf6, 0xec, 0xed, 0xd4, 0x19, 0xdb, 0x06, 0xc1 + }, + + { + 0xcd, 0xc7, 0x6e, 0x5c, 0x99, 0x14, 0xfb, 0x92, + 0x81, 0xa1, 0xc7, 0xe2, 0x84, 0xd7, 0x3e, 0x67, + 0xf1, 0x80, 0x9a, 0x48, 0xa4, 0x97, 0x20, 0x0e, + 0x04, 0x6d, 0x39, 0xcc, 0xc7, 0x11, 0x2c, 0xd0 + } + }; + + buf = calloc(1024, sizeof(unsigned char)); + if (NULL == buf) + { + if (verbose) + { + syslog(LOG_INFO, "Buffer allocation failed\n"); + } + + return (1); + } + + esp32c3_sha256_init(&ctx); + + for (i = 0; i < 6; i++) + { + j = i % 3; + k = i < 3; + + if (verbose) + { + syslog(LOG_INFO, " SHA-%d test #%d: ", 256 - k * 32, j + 1); + } + + ret = esp32c3_sha256_starts(&ctx, k); + if (ret != 0) + { + goto fail; + } + + if (j == 2) + { + memset(buf, 'a', buflen = 1000); + + for (j = 0; j < 1000; j++) + { + ret = esp32c3_sha256_update(&ctx, buf, buflen); + if (ret != 0) + { + goto fail; + } + } + } + else + { + ret = esp32c3_sha256_update(&ctx, + sha256_test_buf[j], + sha256_test_buflen[j]); + if (ret != 0) + { + goto fail; + } + } + + ret = esp32c3_sha256_finish(&ctx, sha256sum); + if (ret != 0) + { + goto fail; + } + + if (memcmp(sha256sum, sha256_test_sum[i], 32 - k * 4) != 0) + { + ret = 1; + goto fail; + } + + if (verbose) + { + syslog(LOG_INFO, "passed\n"); + } + } + + if (verbose) + { + syslog(LOG_INFO, "\n"); + } + + goto exit; + +fail: + if (verbose) + { + syslog(LOG_INFO, "failed\n"); + } + +exit: + esp32c3_sha256_free(&ctx); + free(buf); + + return (ret); +} + +/**************************************************************************** + * Name: esp32c3_sha512_self_test + * + * Description: + * Checkup routine + * + * Input Parameters: + * verbose - The result output or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_sha512_self_test(bool verbose) +{ + int i; + int j; + int k; + int buflen; + int ret = 0; + unsigned char *buf; + unsigned char sha512sum[64]; + struct esp32c3_sha512_context_s ctx; + + /* FIPS-180-2 test vectors */ + + const unsigned char sha512_test_buf[3][113] = + { + { + "abc" + }, + + { + "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn" + "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" + }, + + { + "" + } + }; + + const size_t sha512_test_buflen[3] = + { + 3, 112, 1000 + }; + + const unsigned char sha512_test_sum[6][64] = + { + /* SHA-384 test vectors */ + + { + 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, + 0xb5, 0xa0, 0x3d, 0x69, 0x9a, 0xc6, 0x50, 0x07, + 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, + 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, + 0x80, 0x86, 0x07, 0x2b, 0xa1, 0xe7, 0xcc, 0x23, + 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7 + }, + + { + 0x09, 0x33, 0x0c, 0x33, 0xf7, 0x11, 0x47, 0xe8, + 0x3d, 0x19, 0x2f, 0xc7, 0x82, 0xcd, 0x1b, 0x47, + 0x53, 0x11, 0x1b, 0x17, 0x3b, 0x3b, 0x05, 0xd2, + 0x2f, 0xa0, 0x80, 0x86, 0xe3, 0xb0, 0xf7, 0x12, + 0xfc, 0xc7, 0xc7, 0x1a, 0x55, 0x7e, 0x2d, 0xb9, + 0x66, 0xc3, 0xe9, 0xfa, 0x91, 0x74, 0x60, 0x39 + }, + + { + 0x9d, 0x0e, 0x18, 0x09, 0x71, 0x64, 0x74, 0xcb, + 0x08, 0x6e, 0x83, 0x4e, 0x31, 0x0a, 0x4a, 0x1c, + 0xed, 0x14, 0x9e, 0x9c, 0x00, 0xf2, 0x48, 0x52, + 0x79, 0x72, 0xce, 0xc5, 0x70, 0x4c, 0x2a, 0x5b, + 0x07, 0xb8, 0xb3, 0xdc, 0x38, 0xec, 0xc4, 0xeb, + 0xae, 0x97, 0xdd, 0xd8, 0x7f, 0x3d, 0x89, 0x85 + }, + + /* SHA-512 test vectors */ + + { + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, + 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31, + 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, + 0x21, 0x92, 0x99, 0x2a, 0x27, 0x4f, 0xc1, 0xa8, + 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, + 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f + }, + + { + 0x8e, 0x95, 0x9b, 0x75, 0xda, 0xe3, 0x13, 0xda, + 0x8c, 0xf4, 0xf7, 0x28, 0x14, 0xfc, 0x14, 0x3f, + 0x8f, 0x77, 0x79, 0xc6, 0xeb, 0x9f, 0x7f, 0xa1, + 0x72, 0x99, 0xae, 0xad, 0xb6, 0x88, 0x90, 0x18, + 0x50, 0x1d, 0x28, 0x9e, 0x49, 0x00, 0xf7, 0xe4, + 0x33, 0x1b, 0x99, 0xde, 0xc4, 0xb5, 0x43, 0x3a, + 0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54, + 0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 + }, + + { + 0xe7, 0x18, 0x48, 0x3d, 0x0c, 0xe7, 0x69, 0x64, + 0x4e, 0x2e, 0x42, 0xc7, 0xbc, 0x15, 0xb4, 0x63, + 0x8e, 0x1f, 0x98, 0xb1, 0x3b, 0x20, 0x44, 0x28, + 0x56, 0x32, 0xa8, 0x03, 0xaf, 0xa9, 0x73, 0xeb, + 0xde, 0x0f, 0xf2, 0x44, 0x87, 0x7e, 0xa6, 0x0a, + 0x4c, 0xb0, 0x43, 0x2c, 0xe5, 0x77, 0xc3, 0x1b, + 0xeb, 0x00, 0x9c, 0x5c, 0x2c, 0x49, 0xaa, 0x2e, + 0x4e, 0xad, 0xb2, 0x17, 0xad, 0x8c, 0xc0, 0x9b + } + }; + + buf = calloc(1024, sizeof(unsigned char)); + if (NULL == buf) + { + if (verbose) + { + syslog(LOG_INFO, "Buffer allocation failed\n"); + } + + return (1); + } + + esp32c3_sha512_init(&ctx); + + for (i = 0; i < 6; i++) + { + j = i % 3; + k = i < 3; + + if (verbose) + { + syslog(LOG_INFO, " SHA-%d test #%d: ", 512 - k * 128, j + 1); + } + + ret = esp32c3_sha512_starts(&ctx, k); + if (ret != 0) + { + goto fail; + } + + if (j == 2) + { + memset(buf, 'a', buflen = 1000); + + for (j = 0; j < 1000; j++) + { + ret = esp32c3_sha512_update(&ctx, buf, buflen); + if (ret != 0) + { + goto fail; + } + } + } + else + { + ret = esp32c3_sha512_update(&ctx, + sha512_test_buf[j], + sha512_test_buflen[j]); + if (ret != 0) + { + goto fail; + } + } + + ret = esp32c3_sha512_finish(&ctx, sha512sum); + if (ret != 0) + { + goto fail; + } + + if (memcmp(sha512sum, sha512_test_sum[i], 64 - k * 16) != 0) + { + ret = 1; + goto fail; + } + + if (verbose) + { + syslog(LOG_INFO, "passed\n"); + } + } + + if (verbose) + { + syslog(LOG_INFO, "\n"); + } + + goto exit; + +fail: + if (verbose) + { + syslog(LOG_INFO, "failed\n"); + } + +exit: + esp32c3_sha512_free(&ctx); + free(buf); + + return (ret); +} + +/**************************************************************************** + * Name: esp32c3_sha_main + ****************************************************************************/ + +int esp32c3_sha_main(int argc, char *argv[]) +{ + int ret = 0; + + syslog(LOG_INFO, "----- BEGIN TEST -----\n"); + + esp32c3_sha_init(); + + ret = esp32c3_sha1_self_test(true); + if (ret) + { + goto test_end; + } + + ret = esp32c3_sha256_self_test(true); + if (ret) + { + goto test_end; + } + + ret = esp32c3_sha512_self_test(true); + if (ret) + { + goto test_end; + } + +test_end: + syslog(LOG_INFO, "----- END TEST -----\n"); + + syslog(LOG_INFO, "\n"); + + syslog(LOG_INFO, "----- RESULT: %s -----\n", + !ret ? "SUCCESS" : "FAILED"); + + return OK; +} + +#endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_sha.h b/arch/risc-v/src/esp32c3/esp32c3_sha.h new file mode 100644 index 00000000000..962204c30ae --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_sha.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_sha.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum esp32c3_sha_type_e +{ + ESP32C3_SHA1_1 = 0, + ESP32C3_SHA2_224, + ESP32C3_SHA2_256, + ESP32C3_SHA3_384, + ESP32C3_SHA3_512, + ESP32C3_SHA_TYPE_MAX +}; + +enum esp32c3_sha_state_e +{ + ESP32C3_SHA_STATE_INIT, + ESP32C3_SHA_STATE_IN_PROCESS +}; + +/* SHA-1 context structure */ + +struct esp32c3_sha1_context_s +{ + uint32_t total[2]; /* number of bytes processed */ + uint32_t state[5]; /* intermediate digest state */ + unsigned char buffer[64]; /* data block being processed */ + bool first_block; /* if first then true else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/* SHA-256 context structure */ + +struct esp32c3_sha256_context_s +{ + uint32_t total[2]; /* number of bytes processed */ + uint32_t state[8]; /* intermediate digest state */ + unsigned char buffer[64]; /* data block being processed */ + bool first_block; /* if first then true, else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/* SHA-512 context structure */ + +struct esp32c3_sha512_context_s +{ + uint64_t total[2]; /* number of bytes processed */ + uint64_t state[8]; /* intermediate digest state */ + uint8_t buffer[128]; /* data block being processed */ + + bool first_block; /* if first then true, else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/**************************************************************************** + * Name: esp32c3_sha_init + * + * Description: + * Initialize ESP32-C3 SHA hardware. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_spi.c b/arch/risc-v/src/esp32c3/esp32c3_spi.c index d65055b1a57..ab5f54cc69b 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_spi.c +++ b/arch/risc-v/src/esp32c3/esp32c3_spi.c @@ -27,22 +27,30 @@ #ifdef CONFIG_ESP32C3_SPI #include +#include #include #include #include #include #include +#include #include #include +#include #include #include #include #include "esp32c3_spi.h" +#include "esp32c3_irq.h" #include "esp32c3_gpio.h" +#ifdef CONFIG_ESP32C3_SPI2_DMA +#include "esp32c3_dma.h" +#endif + #include "riscv_arch.h" #include "hardware/esp32c3_gpio_sigmap.h" #include "hardware/esp32c3_pinmap.h" @@ -62,6 +70,18 @@ # define SPI_HAVE_SWCS FALSE #endif +#ifdef CONFIG_ESP32C3_SPI2_DMA + +/* SPI DMA RX/TX number of descriptors */ + +#define SPI_DMA_DESC_NUM (CONFIG_ESP32C3_SPI2_DMADESC_NUM) + +/* SPI DMA reset before exchange */ + +#define SPI_DMA_RESET_MASK (SPI_DMA_AFIFO_RST_M | SPI_RX_AFIFO_RST_M) + +#endif + /* Verify whether SPI has been assigned IOMUX pins. * Otherwise, SPI signals will be routed via GPIO Matrix. */ @@ -119,8 +139,16 @@ struct esp32c3_spi_config_s uint8_t mosi_pin; /* GPIO configuration for MOSI */ uint8_t miso_pin; /* GPIO configuration for MISO */ uint8_t clk_pin; /* GPIO configuration for CLK */ +#ifdef CONFIG_ESP32C3_SPI2_DMA + uint8_t periph; /* Peripheral ID */ + uint8_t irq; /* Interrupt ID */ +#endif uint32_t clk_bit; /* Clock enable bit */ uint32_t rst_bit; /* SPI reset bit */ +#ifdef CONFIG_ESP32C3_SPI2_DMA + uint32_t dma_clk_bit; /* DMA clock enable bit */ + uint32_t dma_rst_bit; /* DMA reset bit */ +#endif uint32_t cs_insig; /* SPI CS input signal index */ uint32_t cs_outsig; /* SPI CS output signal index */ uint32_t mosi_insig; /* SPI MOSI input signal index */ @@ -142,6 +170,11 @@ struct esp32c3_spi_priv_s const struct esp32c3_spi_config_s *config; int refs; /* Reference count */ sem_t exclsem; /* Held while chip is selected for mutual exclusion */ +#ifdef CONFIG_ESP32C3_SPI2_DMA + sem_t sem_isr; /* Interrupt wait semaphore */ + int cpuint; /* SPI interrupt ID */ + int32_t dma_channel; /* Channel assigned by the GDMA driver */ +#endif uint32_t frequency; /* Requested clock frequency */ uint32_t actual; /* Actual clock frequency */ enum spi_mode_e mode; /* Actual SPI hardware mode */ @@ -170,6 +203,19 @@ static uint32_t esp32c3_spi_send(FAR struct spi_dev_s *dev, uint32_t wd); static void esp32c3_spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords); +#ifdef CONFIG_ESP32C3_SPI2_DMA +static int esp32c3_spi_interrupt(int irq, void *context, FAR void *arg); +static int esp32c3_spi_sem_waitdone(FAR struct esp32c3_spi_priv_s *priv); +static void esp32c3_spi_dma_exchange(FAR struct esp32c3_spi_priv_s *priv, + FAR const void *txbuffer, + FAR void *rxbuffer, + uint32_t nwords); +#else +static void esp32c3_spi_poll_exchange(FAR struct esp32c3_spi_priv_s *priv, + FAR const void *txbuffer, + FAR void *rxbuffer, + size_t nwords); +#endif #ifndef CONFIG_SPI_EXCHANGE static void esp32c3_spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, @@ -181,6 +227,9 @@ static void esp32c3_spi_recvblock(FAR struct spi_dev_s *dev, #ifdef CONFIG_SPI_TRIGGER static int esp32c3_spi_trigger(FAR struct spi_dev_s *dev); #endif +#ifdef CONFIG_ESP32C3_SPI2_DMA +static void esp32c3_spi_dma_init(FAR struct spi_dev_s *dev); +#endif static void esp32c3_spi_init(FAR struct spi_dev_s *dev); static void esp32c3_spi_deinit(FAR struct spi_dev_s *dev); @@ -198,8 +247,16 @@ static const struct esp32c3_spi_config_s esp32c3_spi2_config = .mosi_pin = CONFIG_ESP32C3_SPI2_MOSIPIN, .miso_pin = CONFIG_ESP32C3_SPI2_MISOPIN, .clk_pin = CONFIG_ESP32C3_SPI2_CLKPIN, +#ifdef CONFIG_ESP32C3_SPI2_DMA + .periph = ESP32C3_PERIPH_SPI2, + .irq = ESP32C3_IRQ_SPI2, +#endif .clk_bit = SYSTEM_SPI2_CLK_EN, .rst_bit = SYSTEM_SPI2_RST, +#ifdef CONFIG_ESP32C3_SPI2_DMA + .dma_clk_bit = SYSTEM_SPI2_DMA_CLK_EN, + .dma_rst_bit = SYSTEM_SPI2_DMA_RST, +#endif .cs_insig = FSPICS0_IN_IDX, .cs_outsig = FSPICS0_OUT_IDX, .mosi_insig = FSPID_IN_IDX, @@ -243,20 +300,34 @@ static const struct spi_ops_s esp32c3_spi2_ops = static struct esp32c3_spi_priv_s esp32c3_spi2_priv = { - .spi_dev = - { - .ops = &esp32c3_spi2_ops - }, - .config = &esp32c3_spi2_config, - .refs = 0, - .exclsem = SEM_INITIALIZER(0), - .frequency = 0, - .actual = 0, - .mode = 0, - .nbits = 0 + .spi_dev = + { + .ops = &esp32c3_spi2_ops + }, + .config = &esp32c3_spi2_config, + .refs = 0, + .exclsem = SEM_INITIALIZER(0), +#ifdef CONFIG_ESP32C3_SPI2_DMA + .sem_isr = SEM_INITIALIZER(0), + .cpuint = -ENOMEM, + .dma_channel = -1, +#endif + .frequency = 0, + .actual = 0, + .mode = 0, + .nbits = 0 }; #endif /* CONFIG_ESP32C3_SPI2 */ +#ifdef CONFIG_ESP32C3_SPI2_DMA + +/* SPI DMA RX/TX description */ + +static struct esp32c3_dmadesc_s dma_rxdesc[SPI_DMA_DESC_NUM]; +static struct esp32c3_dmadesc_s dma_txdesc[SPI_DMA_DESC_NUM]; + +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -272,7 +343,7 @@ static struct esp32c3_spi_priv_s esp32c3_spi2_priv = * bits - Bits to be set * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -294,7 +365,7 @@ static inline void esp32c3_spi_set_regbits(uint32_t addr, uint32_t bits) * bits - Bits to be cleared * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -313,10 +384,10 @@ static inline void esp32c3_spi_clr_regbits(uint32_t addr, uint32_t bits) * * Input Parameters: * dev - Device-specific state data - * lock - true: Lock spi bus, false: unlock SPI bus + * lock - true: Lock SPI bus, false: unlock SPI bus * * Returned Value: - * The result of lock or unlock the SPI device + * The result of lock or unlock the SPI device. * ****************************************************************************/ @@ -337,6 +408,37 @@ static int esp32c3_spi_lock(FAR struct spi_dev_s *dev, bool lock) return ret; } +/**************************************************************************** + * Name: esp32c3_spi_sem_waitdone + * + * Description: + * Wait for a transfer to complete. + * + * Input Parameters: + * priv - SPI private state data + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +static int esp32c3_spi_sem_waitdone(FAR struct esp32c3_spi_priv_s *priv) +{ + int ret; + struct timespec abstime; + + clock_gettime(CLOCK_REALTIME, &abstime); + + abstime.tv_sec += 10; + abstime.tv_nsec += 0; + + ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime); + + return ret; +} +#endif + /**************************************************************************** * Name: esp32c3_spi_select * @@ -356,7 +458,7 @@ static int esp32c3_spi_lock(FAR struct spi_dev_s *dev, bool lock) * selected - true: slave selected, false: slave de-selected * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -509,7 +611,7 @@ static uint32_t esp32c3_spi_setfrequency(FAR struct spi_dev_s *dev, * mode - The requested SPI mode * * Returned Value: - * none + * None. * ****************************************************************************/ @@ -578,7 +680,7 @@ static void esp32c3_spi_setmode(FAR struct spi_dev_s *dev, * nbits - The number of bits in an SPI word. * * Returned Value: - * none + * None. * ****************************************************************************/ @@ -617,6 +719,115 @@ static int esp32c3_spi_hwfeatures(FAR struct spi_dev_s *dev, } #endif +/**************************************************************************** + * Name: esp32c3_spi_dma_exchange + * + * Description: + * Exchange a block of data from SPI by DMA. + * + * Input Parameters: + * priv - SPI private state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +static void esp32c3_spi_dma_exchange(FAR struct esp32c3_spi_priv_s *priv, + FAR const void *txbuffer, + FAR void *rxbuffer, + uint32_t nwords) +{ + const uint32_t total = nwords * (priv->nbits / 8); + const int32_t channel = priv->dma_channel; + uint32_t bytes = total; + uint32_t n; + uint8_t *tp; + uint8_t *rp; + + DEBUGASSERT((txbuffer != NULL) || (rxbuffer != NULL)); + + spiinfo("nwords=%" PRIu32 "\n", nwords); + + tp = (uint8_t *)txbuffer; + rp = (uint8_t *)rxbuffer; + + if (tp == NULL) + { + tp = rp; + } + + esp32c3_spi_clr_regbits(SPI_DMA_INT_RAW_REG, SPI_TRANS_DONE_INT_RAW_M); + + esp32c3_spi_set_regbits(SPI_DMA_INT_ENA_REG, SPI_TRANS_DONE_INT_ENA_M); + + while (bytes != 0) + { + /* Reset SPI DMA TX FIFO */ + + esp32c3_spi_set_regbits(SPI_DMA_CONF_REG, SPI_DMA_RESET_MASK); + esp32c3_spi_clr_regbits(SPI_DMA_CONF_REG, SPI_DMA_RESET_MASK); + + /* Enable SPI DMA TX */ + + esp32c3_spi_set_regbits(SPI_DMA_CONF_REG, SPI_DMA_TX_ENA_M); + + n = esp32c3_dma_setup(channel, true, dma_txdesc, SPI_DMA_DESC_NUM, + tp, bytes); + esp32c3_dma_enable(channel, true); + + putreg32((n * 8 - 1), SPI_MS_DLEN_REG); + esp32c3_spi_set_regbits(SPI_USER_REG, SPI_USR_MOSI_M); + + tp += n; + + if (rp != NULL) + { + /* Enable SPI DMA RX */ + + esp32c3_spi_set_regbits(SPI_DMA_CONF_REG, SPI_DMA_RX_ENA_M); + + esp32c3_dma_setup(channel, false, dma_rxdesc, SPI_DMA_DESC_NUM, + rp, bytes); + esp32c3_dma_enable(channel, false); + + esp32c3_spi_set_regbits(SPI_USER_REG, SPI_USR_MISO_M); + + rp += n; + } + else + { + esp32c3_spi_clr_regbits(SPI_USER_REG, SPI_USR_MISO_M); + } + + /* Trigger start of user-defined transaction for master. */ + + esp32c3_spi_set_regbits(SPI_CMD_REG, SPI_UPDATE_M); + + while ((getreg32(SPI_CMD_REG) & SPI_UPDATE_M) != 0) + { + ; + } + + esp32c3_spi_set_regbits(SPI_CMD_REG, SPI_USR_M); + + esp32c3_spi_sem_waitdone(priv); + + bytes -= n; + } + + esp32c3_spi_clr_regbits(SPI_DMA_INT_ENA_REG, SPI_TRANS_DONE_INT_ENA_M); +} +#endif + /**************************************************************************** * Name: esp32c3_spi_poll_send * @@ -629,7 +840,7 @@ static int esp32c3_spi_hwfeatures(FAR struct spi_dev_s *dev, * number of bits selected for the SPI interface. * * Returned Value: - * Received value + * Received value. * ****************************************************************************/ @@ -679,7 +890,7 @@ static uint32_t esp32c3_spi_poll_send(FAR struct esp32c3_spi_priv_s *priv, * number of bits selected for the SPI interface. * * Returned Value: - * Received value + * Received value. * ****************************************************************************/ @@ -707,7 +918,7 @@ static uint32_t esp32c3_spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * uint16_t's * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -836,7 +1047,7 @@ static void esp32c3_spi_poll_exchange(FAR struct esp32c3_spi_priv_s *priv, * uint16_t's * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -847,7 +1058,18 @@ static void esp32c3_spi_exchange(FAR struct spi_dev_s *dev, { FAR struct esp32c3_spi_priv_s *priv = (FAR struct esp32c3_spi_priv_s *)dev; - esp32c3_spi_poll_exchange(priv, txbuffer, rxbuffer, nwords); +#ifdef CONFIG_ESP32C3_SPI2_DMA + size_t thld = CONFIG_ESP32C3_SPI2_DMATHRESHOLD; + + if (nwords > thld) + { + esp32c3_spi_dma_exchange(priv, txbuffer, rxbuffer, nwords); + } + else +#endif + { + esp32c3_spi_poll_exchange(priv, txbuffer, rxbuffer, nwords); + } } #ifndef CONFIG_SPI_EXCHANGE @@ -868,7 +1090,7 @@ static void esp32c3_spi_exchange(FAR struct spi_dev_s *dev, * packed into uint16_t's * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -897,7 +1119,7 @@ static void esp32c3_spi_sndblock(FAR struct spi_dev_s *dev, * packed into uint16_t's * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -934,6 +1156,55 @@ static int esp32c3_spi_trigger(FAR struct spi_dev_s *dev) } #endif +/**************************************************************************** + * Name: esp32c3_spi_dma_init + * + * Description: + * Initialize ESP32-C3 SPI connection to GDMA engine. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +void esp32c3_spi_dma_init(FAR struct spi_dev_s *dev) +{ + FAR struct esp32c3_spi_priv_s *priv = (FAR struct esp32c3_spi_priv_s *)dev; + + /* Enable GDMA clock for the SPI peripheral */ + + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, priv->config->dma_clk_bit); + + /* Reset GDMA for the SPI peripheral */ + + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, priv->config->dma_rst_bit, 0); + + /* Initialize GDMA controller */ + + esp32c3_dma_init(); + + /* Request a GDMA channel for SPI peripheral */ + + priv->dma_channel = esp32c3_dma_request(ESP32C3_DMA_PERIPH_SPI, 1, 1, + true); + if (priv->dma_channel < 0) + { + spierr("Failed to allocate GDMA channel\n"); + + DEBUGASSERT(false); + } + + /* Disable segment transaction mode for SPI Master */ + + putreg32((SPI_SLV_RX_SEG_TRANS_CLR_EN_M | SPI_SLV_TX_SEG_TRANS_CLR_EN_M), + SPI_DMA_CONF_REG); +} +#endif + /**************************************************************************** * Name: esp32c3_spi_init * @@ -944,7 +1215,7 @@ static int esp32c3_spi_trigger(FAR struct spi_dev_s *dev) * dev - Device-specific state data * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -1015,6 +1286,13 @@ static void esp32c3_spi_init(FAR struct spi_dev_s *dev) putreg32(0, SPI_CTRL_REG); putreg32(VALUE_MASK(0, SPI_CS_HOLD_TIME), SPI_USER1_REG); +#ifdef CONFIG_ESP32C3_SPI2_DMA + nxsem_init(&priv->sem_isr, 0, 0); + nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE); + + esp32c3_spi_dma_init(dev); +#endif + esp32c3_spi_setfrequency(dev, config->clk_freq); esp32c3_spi_setbits(dev, config->width); esp32c3_spi_setmode(dev, config->mode); @@ -1030,7 +1308,7 @@ static void esp32c3_spi_init(FAR struct spi_dev_s *dev) * dev - Device-specific state data * * Returned Value: - * None + * None. * ****************************************************************************/ @@ -1038,6 +1316,10 @@ static void esp32c3_spi_deinit(FAR struct spi_dev_s *dev) { FAR struct esp32c3_spi_priv_s *priv = (FAR struct esp32c3_spi_priv_s *)dev; +#ifdef CONFIG_ESP32C3_SPI2_DMA + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->dma_clk_bit, 0); +#endif + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, priv->config->clk_bit); modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->clk_bit, 0); @@ -1047,6 +1329,34 @@ static void esp32c3_spi_deinit(FAR struct spi_dev_s *dev) priv->nbits = 0; } +/**************************************************************************** + * Name: esp32c3_spi_interrupt + * + * Description: + * Common SPI DMA interrupt handler. + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info + * arg - SPI controller private data + * + * Returned Value: + * Standard interrupt return value. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +static int esp32c3_spi_interrupt(int irq, void *context, FAR void *arg) +{ + FAR struct esp32c3_spi_priv_s *priv = (FAR struct esp32c3_spi_priv_s *)arg; + + esp32c3_spi_clr_regbits(SPI_DMA_INT_RAW_REG, SPI_TRANS_DONE_INT_RAW_M); + nxsem_post(&priv->sem_isr); + + return 0; +} +#endif + /**************************************************************************** * Name: esp32c3_spibus_initialize * @@ -1057,7 +1367,7 @@ static void esp32c3_spi_deinit(FAR struct spi_dev_s *dev) * port - Port number (for hardware that has multiple SPI interfaces) * * Returned Value: - * Valid SPI device structure reference on success; NULL on failure + * Valid SPI device structure reference on success; NULL on failure. * ****************************************************************************/ @@ -1089,6 +1399,42 @@ FAR struct spi_dev_s *esp32c3_spibus_initialize(int port) return spi_dev; } +#ifdef CONFIG_ESP32C3_SPI2_DMA + if (priv->cpuint != -ENOMEM) + { + /* Disable the provided CPU Interrupt to configure it. */ + + up_disable_irq(priv->cpuint); + } + + priv->cpuint = esp32c3_request_irq(priv->config->periph, + ESP32C3_INT_PRIO_DEF, + ESP32C3_INT_LEVEL); + if (priv->cpuint < 0) + { + /* Failed to allocate a CPU interrupt of this type. */ + + leave_critical_section(flags); + + return NULL; + } + + if (irq_attach(priv->config->irq, esp32c3_spi_interrupt, priv) != OK) + { + /* Failed to attach IRQ, so CPU interrupt must be freed. */ + + esp32c3_free_cpuint(priv->config->periph); + priv->cpuint = -ENOMEM; + leave_critical_section(flags); + + return NULL; + } + + /* Enable the CPU interrupt that is linked to the SPI device. */ + + up_enable_irq(priv->cpuint); +#endif + esp32c3_spi_init(spi_dev); priv->refs++; @@ -1108,7 +1454,7 @@ FAR struct spi_dev_s *esp32c3_spibus_initialize(int port) * dev - Device-specific state data * * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * Zero (OK) is returned on success. Otherwise -1 (ERROR). * ****************************************************************************/ @@ -1134,6 +1480,14 @@ int esp32c3_spibus_uninitialize(FAR struct spi_dev_s *dev) leave_critical_section(flags); +#ifdef CONFIG_ESP32C3_SPI2_DMA + up_disable_irq(priv->cpuint); + esp32c3_free_cpuint(priv->config->periph); + priv->cpuint = -ENOMEM; + + nxsem_destroy(&priv->sem_isr); +#endif + esp32c3_spi_deinit(dev); nxsem_destroy(&priv->exclsem); diff --git a/arch/risc-v/src/esp32c3/esp32c3_spi.h b/arch/risc-v/src/esp32c3/esp32c3_spi.h index 443a0f224ee..7876fbb714e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_spi.h +++ b/arch/risc-v/src/esp32c3/esp32c3_spi.h @@ -126,6 +126,39 @@ int esp32c3_spi2_cmddata(FAR struct spi_dev_s *dev, int esp32c3_spibus_uninitialize(FAR struct spi_dev_s *dev); +/**************************************************************************** + * Name: esp32c3_spislave_ctrlr_initialize + * + * Description: + * Initialize the selected SPI Slave bus. + * + * Input Parameters: + * port - Port number (for hardware that has multiple SPI Slave interfaces) + * + * Returned Value: + * Valid SPI Slave controller structure reference on success; + * NULL on failure. + * + ****************************************************************************/ + +FAR struct spi_slave_ctrlr_s *esp32c3_spislave_ctrlr_initialize(int port); + +/**************************************************************************** + * Name: esp32c3_spislave_ctrlr_uninitialize + * + * Description: + * Uninitialize an SPI Slave bus. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_spislave_ctrlr_uninitialize(FAR struct spi_slave_ctrlr_s *ctrlr); + #endif /* CONFIG_ESP32C3_SPI */ #ifdef __cplusplus diff --git a/arch/risc-v/src/esp32c3/esp32c3_spi_slave.c b/arch/risc-v/src/esp32c3/esp32c3_spi_slave.c new file mode 100644 index 00000000000..0a29072ba56 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_spi_slave.c @@ -0,0 +1,1518 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_spi_slave.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ESP32C3_SPI) && defined(CONFIG_SPI_SLAVE) + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "esp32c3.h" +#include "esp32c3_spi.h" +#include "esp32c3_irq.h" +#include "esp32c3_gpio.h" + +#ifdef CONFIG_ESP32C3_SPI2_DMA +#include "esp32c3_dma.h" +#endif + +#include "riscv_arch.h" +#include "hardware/esp32c3_gpio_sigmap.h" +#include "hardware/esp32c3_pinmap.h" +#include "hardware/esp32c3_spi.h" +#include "hardware/esp32c3_soc.h" +#include "hardware/esp32c3_system.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#define SPI_SLAVE_BUFSIZE (CONFIG_ESP32C3_SPI2_SLAVE_BUFSIZE) + +#ifdef CONFIG_ESP32C3_SPI2_DMA +/* SPI DMA RX/TX number of descriptors */ + +#if (SPI_SLAVE_BUFSIZE % ESP32C3_DMA_BUFLEN_MAX) > 0 +# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / ESP32C3_DMA_BUFLEN_MAX + 1) +#else +# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / ESP32C3_DMA_BUFLEN_MAX) +#endif + +#endif /* CONFIG_ESP32C3_SPI2_DMA */ + +/* Verify whether SPI has been assigned IOMUX pins. + * Otherwise, SPI signals will be routed via GPIO Matrix. + */ + +#define SPI_IS_CS_IOMUX (CONFIG_ESP32C3_SPI2_CSPIN == SPI2_IOMUX_CSPIN) +#define SPI_IS_CLK_IOMUX (CONFIG_ESP32C3_SPI2_CLKPIN == SPI2_IOMUX_CLKPIN) +#define SPI_IS_MOSI_IOMUX (CONFIG_ESP32C3_SPI2_MOSIPIN == SPI2_IOMUX_MOSIPIN) +#define SPI_IS_MISO_IOMUX (CONFIG_ESP32C3_SPI2_MISOPIN == SPI2_IOMUX_MISOPIN) + +#define SPI_VIA_IOMUX (SPI_IS_CS_IOMUX) && (SPI_IS_CLK_IOMUX) && \ + (SPI_IS_MOSI_IOMUX) && (SPI_IS_MISO_IOMUX) + +/* SPI Slave interrupt mask */ + +#define SPI_INT_MASK (SPI_TRANS_DONE_INT_ENA_M | \ + SPI_SLV_WR_DMA_DONE_INT_ENA_M | \ + SPI_SLV_RD_DMA_DONE_INT_ENA_M | \ + SPI_SLV_WR_BUF_DONE_INT_ENA_M | \ + SPI_SLV_RD_BUF_DONE_INT_ENA_M) + +/* SPI Slave default width */ + +#define SPI_SLAVE_DEFAULT_WIDTH (8) + +/* SPI Slave default mode */ + +#define SPI_SLAVE_DEFAULT_MODE (SPISLAVE_MODE0) + +/* SPI Slave maximum buffer size in bytes */ + +#define SPI_SLAVE_HW_BUF_SIZE (64) + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#define WORDS2BYTES(_priv, _wn) ((_wn) * ((_priv)->nbits / 8)) +#define BYTES2WORDS(_priv, _bn) ((_bn) / ((_priv)->nbits / 8)) + +/* SPI Slave controller hardware configuration */ + +struct spislave_config_s +{ + int32_t width; /* SPI Slave default width */ + enum spi_slave_mode_e mode; /* SPI Slave default mode */ + + uint8_t cs_pin; /* GPIO configuration for CS */ + uint8_t mosi_pin; /* GPIO configuration for MOSI */ + uint8_t miso_pin; /* GPIO configuration for MISO */ + uint8_t clk_pin; /* GPIO configuration for CLK */ + uint8_t periph; /* Peripheral ID */ + uint8_t irq; /* Interrupt ID */ + uint32_t clk_bit; /* Clock enable bit */ + uint32_t rst_bit; /* SPI reset bit */ +#ifdef CONFIG_ESP32C3_SPI2_DMA + uint32_t dma_clk_bit; /* DMA clock enable bit */ + uint32_t dma_rst_bit; /* DMA reset bit */ +#endif + uint32_t cs_insig; /* SPI CS input signal index */ + uint32_t cs_outsig; /* SPI CS output signal index */ + uint32_t mosi_insig; /* SPI MOSI input signal index */ + uint32_t mosi_outsig; /* SPI MOSI output signal index */ + uint32_t miso_insig; /* SPI MISO input signal index */ + uint32_t miso_outsig; /* SPI MISO output signal index */ + uint32_t clk_insig; /* SPI CLK input signal index */ + uint32_t clk_outsig; /* SPI CLK output signal index */ +}; + +struct spislave_priv_s +{ + /* Externally visible part of the SPI Slave controller interface */ + + struct spi_slave_ctrlr_s ctrlr; + + /* Reference to SPI Slave device interface */ + + struct spi_slave_dev_s *dev; + + /* Port configuration */ + + const struct spislave_config_s *config; + int refs; /* Reference count */ + int cpuint; /* SPI interrupt ID */ +#ifdef CONFIG_ESP32C3_SPI2_DMA + int32_t dma_channel; /* Channel assigned by the GDMA driver */ +#endif + enum spi_slave_mode_e mode; /* Current SPI Slave hardware mode */ + uint8_t nbits; /* Current configured bit width */ + uint32_t tx_length; /* Location of next TX value */ + + /* SPI Slave TX queue buffer */ + + uint8_t tx_buffer[SPI_SLAVE_BUFSIZE]; + uint32_t rx_length; /* Location of next RX value */ + + /* SPI Slave RX queue buffer */ + + uint8_t rx_buffer[SPI_SLAVE_BUFSIZE]; + + /* Flag that indicates whether SPI Slave is currently processing */ + + bool is_processing; + + /* Flag that indicates whether SPI Slave TX is currently enabled */ + + bool is_tx_enabled; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* SPI Slave controller interrupt handlers */ + +static int spislave_cs_interrupt(int irq, void *context, FAR void *arg); +static int spislave_periph_interrupt(int irq, void *context, FAR void *arg); + +/* SPI Slave controller internal functions */ + +static void spislave_setmode(FAR struct spi_slave_ctrlr_s *ctrlr, + enum spi_slave_mode_e mode); +static void spislave_setbits(FAR struct spi_slave_ctrlr_s *ctrlr, int nbits); +static void spislave_store_result(FAR struct spislave_priv_s *priv, + uint32_t recv_bytes); +static void spislave_prepare_next_rx(FAR struct spislave_priv_s *priv); +static void spislave_evict_sent_data(FAR struct spislave_priv_s *priv, + uint32_t sent_bytes); +#ifdef CONFIG_ESP32C3_SPI2_DMA +static void spislave_setup_rx_dma(FAR struct spislave_priv_s *priv); +static void spislave_setup_tx_dma(FAR struct spislave_priv_s *priv); +static void spislave_prepare_next_tx(FAR struct spislave_priv_s *priv); +#else +static void spislave_write_tx_buffer(FAR struct spislave_priv_s *priv); +#endif +static void spislave_initialize(FAR struct spi_slave_ctrlr_s *ctrlr); +static void spislave_deinitialize(FAR struct spi_slave_ctrlr_s *ctrlr); + +/* SPI Slave controller operations */ + +static void spislave_bind(FAR struct spi_slave_ctrlr_s *ctrlr, + FAR struct spi_slave_dev_s *dev, + enum spi_slave_mode_e mode, + int nbits); +static void spislave_unbind(FAR struct spi_slave_ctrlr_s *ctrlr); +static int spislave_enqueue(FAR struct spi_slave_ctrlr_s *ctrlr, + FAR const void *data, + size_t nwords); +static bool spislave_qfull(FAR struct spi_slave_ctrlr_s *ctrlr); +static void spislave_qflush(FAR struct spi_slave_ctrlr_s *ctrlr); +static size_t spislave_qpoll(FAR struct spi_slave_ctrlr_s *ctrlr); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2 +static const struct spislave_config_s esp32c3_spi2slave_config = +{ + .width = SPI_SLAVE_DEFAULT_WIDTH, + .mode = SPI_SLAVE_DEFAULT_MODE, + .cs_pin = CONFIG_ESP32C3_SPI2_CSPIN, + .mosi_pin = CONFIG_ESP32C3_SPI2_MOSIPIN, + .miso_pin = CONFIG_ESP32C3_SPI2_MISOPIN, + .clk_pin = CONFIG_ESP32C3_SPI2_CLKPIN, + .periph = ESP32C3_PERIPH_SPI2, + .irq = ESP32C3_IRQ_SPI2, + .clk_bit = SYSTEM_SPI2_CLK_EN, + .rst_bit = SYSTEM_SPI2_RST, +#ifdef CONFIG_ESP32C3_SPI2_DMA + .dma_clk_bit = SYSTEM_SPI2_DMA_CLK_EN, + .dma_rst_bit = SYSTEM_SPI2_DMA_RST, +#endif + .cs_insig = FSPICS0_IN_IDX, + .cs_outsig = FSPICS0_OUT_IDX, + .mosi_insig = FSPID_IN_IDX, + .mosi_outsig = FSPID_OUT_IDX, + .miso_insig = FSPIQ_IN_IDX, + .miso_outsig = FSPIQ_OUT_IDX, + .clk_insig = FSPICLK_IN_IDX, + .clk_outsig = FSPICLK_OUT_IDX +}; + +static const struct spi_slave_ctrlrops_s esp32c3_spi2slave_ops = +{ + .bind = spislave_bind, + .unbind = spislave_unbind, + .enqueue = spislave_enqueue, + .qfull = spislave_qfull, + .qflush = spislave_qflush, + .qpoll = spislave_qpoll +}; + +static struct spislave_priv_s esp32c3_spi2slave_priv = +{ + .ctrlr = + { + .ops = &esp32c3_spi2slave_ops + }, + .dev = NULL, + .config = &esp32c3_spi2slave_config, + .refs = 0, + .cpuint = -ENOMEM, +#ifdef CONFIG_ESP32C3_SPI2_DMA + .dma_channel = -ENOMEM, +#endif + .mode = SPISLAVE_MODE0, + .nbits = 0, + .tx_length = 0, + .tx_buffer = + { + 0 + }, + .rx_length = 0, + .rx_buffer = + { + 0 + }, + .is_processing = false, + .is_tx_enabled = false +}; +#endif /* CONFIG_ESP32C3_SPI2 */ + +#ifdef CONFIG_ESP32C3_SPI2_DMA + +/* SPI DMA RX/TX description */ + +static struct esp32c3_dmadesc_s dma_rxdesc[SPI_DMA_DESC_NUM]; +static struct esp32c3_dmadesc_s dma_txdesc[SPI_DMA_DESC_NUM]; + +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spislave_peripheral_reset + * + * Description: + * Reset the SPI Slave peripheral before next transaction. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void spislave_peripheral_reset(void) +{ + setbits(SPI_SOFT_RESET_M, SPI_SLAVE_REG); + resetbits(SPI_SOFT_RESET_M, SPI_SLAVE_REG); +} + +/**************************************************************************** + * Name: spislave_cpu_tx_fifo_reset + * + * Description: + * Reset the BUF TX AFIFO, which is used to send data out in SPI Slave + * CPU-controlled mode transfer. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifndef CONFIG_ESP32C3_SPI2_DMA +static inline void spislave_cpu_tx_fifo_reset(void) +{ + setbits(SPI_BUF_AFIFO_RST_M, SPI_DMA_CONF_REG); + resetbits(SPI_BUF_AFIFO_RST_M, SPI_DMA_CONF_REG); +} +#endif + +/**************************************************************************** + * Name: spislave_dma_tx_fifo_reset + * + * Description: + * Reset the DMA TX AFIFO, which is used to send data out in SPI Slave + * DMA-controlled mode transfer. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +static inline void spislave_dma_tx_fifo_reset(void) +{ + setbits(SPI_DMA_AFIFO_RST_M, SPI_DMA_CONF_REG); + resetbits(SPI_DMA_AFIFO_RST_M, SPI_DMA_CONF_REG); +} +#endif + +/**************************************************************************** + * Name: spislave_dma_rx_fifo_reset + * + * Description: + * Reset the RX AFIFO, which is used to receive data in SPI Slave mode + * transfer. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +static inline void spislave_dma_rx_fifo_reset(void) +{ + setbits(SPI_RX_AFIFO_RST_M, SPI_DMA_CONF_REG); + resetbits(SPI_RX_AFIFO_RST_M, SPI_DMA_CONF_REG); +} +#endif + +/**************************************************************************** + * Name: spislave_setmode + * + * Description: + * Set the SPI Slave mode. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * mode - Requested SPI Slave mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_setmode(FAR struct spi_slave_ctrlr_s *ctrlr, + enum spi_slave_mode_e mode) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + + spiinfo("mode=%d\n", mode); + + /* Has the mode changed? */ + + if (mode != priv->mode) + { + uint32_t ck_idle_edge; + uint32_t rsck_i_edge; + uint32_t tsck_i_edge; + uint32_t clk_mode_13; + + switch (mode) + { + case SPISLAVE_MODE0: /* CPOL=0; CPHA=0 */ + ck_idle_edge = 0; + rsck_i_edge = 0; + tsck_i_edge = 0; + clk_mode_13 = 0; + break; + + case SPISLAVE_MODE1: /* CPOL=0; CPHA=1 */ + ck_idle_edge = 0; + rsck_i_edge = 1; + tsck_i_edge = 1; + clk_mode_13 = 1; + break; + + case SPISLAVE_MODE2: /* CPOL=1; CPHA=0 */ + ck_idle_edge = 1; + rsck_i_edge = 1; + tsck_i_edge = 1; + clk_mode_13 = 0; + break; + + case SPISLAVE_MODE3: /* CPOL=1; CPHA=1 */ + ck_idle_edge = 1; + rsck_i_edge = 0; + tsck_i_edge = 0; + clk_mode_13 = 1; + break; + + default: + spierr("Invalid mode: %d\n", mode); + DEBUGASSERT(false); + return; + } + + modifyreg32(SPI_MISC_REG, + SPI_CK_IDLE_EDGE_M, + VALUE_TO_FIELD(ck_idle_edge, SPI_CK_IDLE_EDGE)); + + modifyreg32(SPI_USER_REG, + SPI_RSCK_I_EDGE_M | SPI_TSCK_I_EDGE_M, + VALUE_TO_FIELD(rsck_i_edge, SPI_RSCK_I_EDGE) | + VALUE_TO_FIELD(tsck_i_edge, SPI_TSCK_I_EDGE)); + + modifyreg32(SPI_SLAVE_REG, + SPI_CLK_MODE_13_M | SPI_RSCK_DATA_OUT_M, + VALUE_TO_FIELD(clk_mode_13, SPI_CLK_MODE_13)); + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: spislave_setbits + * + * Description: + * Set the number of bits per word. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * nbits - The number of bits in an SPI word + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_setbits(FAR struct spi_slave_ctrlr_s *ctrlr, int nbits) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + + spiinfo("nbits=%d\n", nbits); + + priv->nbits = nbits; +} + +/**************************************************************************** + * Name: spislave_cs_interrupt + * + * Description: + * Handler for the GPIO interrupt which is triggered when the chip select + * has toggled to inactive state (active high). + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info + * arg - SPI Slave controller private data + * + * Returned Value: + * Standard interrupt return value. + * + ****************************************************************************/ + +static int spislave_cs_interrupt(int irq, void *context, FAR void *arg) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)arg; + + if (priv->is_processing) + { + priv->is_processing = false; + SPIS_DEV_SELECT(priv->dev, false); + } + + return 0; +} + +/**************************************************************************** + * Name: spislave_store_result + * + * Description: + * Fetch data from the SPI hardware data buffer and record the length. + * This is a post transaction operation. + * + * Input Parameters: + * priv - Private SPI Slave controller structure + * recv_bytes - Number of received bytes + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_store_result(FAR struct spislave_priv_s *priv, + uint32_t recv_bytes) +{ + uint32_t remaining_space = SPI_SLAVE_BUFSIZE - priv->rx_length; + uint32_t bytes_to_copy = recv_bytes; + + if (bytes_to_copy > remaining_space) + { + spiwarn("RX buffer full! Discarded %" PRIu32 " received bytes\n", + bytes_to_copy - remaining_space); + + bytes_to_copy = remaining_space; + } + +#ifndef CONFIG_ESP32C3_SPI2_DMA + /* If DMA is not enabled, software should copy incoming data from data + * buffer registers to receive buffer. + */ + + { + /* Set data_buf_reg with the address of the first data buffer + * register (W0). + */ + + uintptr_t data_buf_reg = SPI_W0_REG; + + /* Read received data words from SPI hardware data buffer. */ + + for (int i = 0; i < bytes_to_copy; i += sizeof(uint32_t)) + { + uint32_t r_wd = getreg32(data_buf_reg); + + memcpy(priv->rx_buffer + priv->rx_length + i, &r_wd, + sizeof(uint32_t)); + + /* Update data_buf_reg to point to the next data buffer register. */ + + data_buf_reg += sizeof(uintptr_t); + } + + /* Clear hardware data buffer to avoid echoing on the next transfer. */ + + data_buf_reg = SPI_W0_REG; + + for (int i = 0; i < recv_bytes; i += sizeof(uint32_t)) + { + putreg32(0, data_buf_reg); + + data_buf_reg += sizeof(uintptr_t); + } + } +#endif /* CONFIG_ESP32C3_SPI2_DMA */ + + priv->rx_length += bytes_to_copy; +} + +/**************************************************************************** + * Name: spislave_prepare_next_rx + * + * Description: + * Prepare the SPI Slave controller for receiving data on the next + * transaction. + * + * Input Parameters: + * priv - Private SPI Slave controller structure + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_prepare_next_rx(FAR struct spislave_priv_s *priv) +{ + if (priv->rx_length < SPI_SLAVE_BUFSIZE) + { +#ifdef CONFIG_ESP32C3_SPI2_DMA + spislave_setup_rx_dma(priv); +#endif + } +} + +/**************************************************************************** + * Name: spislave_evict_sent_data + * + * Description: + * Evict from the TX buffer data sent on the latest transaction and update + * the length. This is a post transaction operation. + * + * Input Parameters: + * priv - Private SPI Slave controller structure + * sent_bytes - Number of transmitted bytes + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_evict_sent_data(FAR struct spislave_priv_s *priv, + uint32_t sent_bytes) +{ + if (sent_bytes < priv->tx_length) + { + priv->tx_length -= sent_bytes; + + memmove(priv->tx_buffer, priv->tx_buffer + sent_bytes, + priv->tx_length); + + memset(priv->tx_buffer + priv->tx_length, 0, sent_bytes); + } + else + { + priv->tx_length = 0; + } +} + +/**************************************************************************** + * Name: spislave_write_tx_buffer + * + * Description: + * Write to SPI Slave peripheral hardware data buffer. + * + * Input Parameters: + * priv - Private SPI Slave controller structure + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifndef CONFIG_ESP32C3_SPI2_DMA +static void spislave_write_tx_buffer(FAR struct spislave_priv_s *priv) +{ + /* Initialize data_buf_reg with the address of the first data buffer + * register (W0). + */ + + uintptr_t data_buf_reg = SPI_W0_REG; + + uint32_t transfer_size = MIN(SPI_SLAVE_HW_BUF_SIZE, priv->tx_length); + + /* Write data words to hardware data buffer. + * SPI peripheral contains 16 registers (W0 - W15). + */ + + for (int i = 0; i < transfer_size; i += sizeof(uint32_t)) + { + uint32_t w_wd = UINT32_MAX; + + memcpy(&w_wd, priv->tx_buffer + i, sizeof(uint32_t)); + + putreg32(w_wd, data_buf_reg); + + /* Update data_buf_reg to point to the next data buffer register. */ + + data_buf_reg += sizeof(uintptr_t); + } +} +#endif + +/**************************************************************************** + * Name: spislave_setup_rx_dma + * + * Description: + * Configure the SPI Slave peripheral to perform the next RX data transfer + * via DMA. + * + * Input Parameters: + * priv - Private SPI Slave controller structure + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +static void spislave_setup_rx_dma(FAR struct spislave_priv_s *priv) +{ + uint32_t length = SPI_SLAVE_BUFSIZE - priv->rx_length; + + esp32c3_dma_setup(priv->dma_channel, false, dma_rxdesc, SPI_DMA_DESC_NUM, + priv->rx_buffer + priv->rx_length, length); + + spislave_dma_rx_fifo_reset(); + + spislave_peripheral_reset(); + + /* Clear input FIFO full error */ + + setbits(SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M, SPI_DMA_INT_CLR_REG); + + /* Enable SPI DMA RX */ + + setbits(SPI_DMA_RX_ENA_M, SPI_DMA_CONF_REG); + + esp32c3_dma_enable(priv->dma_channel, false); +} +#endif + +/**************************************************************************** + * Name: spislave_setup_tx_dma + * + * Description: + * Configure the SPI Slave peripheral to perform the next TX data transfer + * via DMA. + * + * Input Parameters: + * priv - Private SPI Slave controller structure + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +static void spislave_setup_tx_dma(FAR struct spislave_priv_s *priv) +{ + esp32c3_dma_setup(priv->dma_channel, true, dma_txdesc, SPI_DMA_DESC_NUM, + priv->tx_buffer, SPI_SLAVE_BUFSIZE); + + spislave_dma_tx_fifo_reset(); + + spislave_peripheral_reset(); + + /* Clear output FIFO empty error */ + + setbits(SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M, SPI_DMA_INT_CLR_REG); + + /* Enable SPI DMA TX */ + + setbits(SPI_DMA_TX_ENA_M, SPI_DMA_CONF_REG); + + esp32c3_dma_enable(priv->dma_channel, true); +} +#endif + +/**************************************************************************** + * Name: spislave_prepare_next_tx + * + * Description: + * Prepare the SPI Slave controller for transmitting data on the next + * transaction. + * + * Input Parameters: + * priv - Private SPI Slave controller structure + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_prepare_next_tx(FAR struct spislave_priv_s *priv) +{ + if (priv->tx_length != 0) + { +#ifdef CONFIG_ESP32C3_SPI2_DMA + spislave_setup_tx_dma(priv); +#else + spislave_peripheral_reset(); + + spislave_write_tx_buffer(priv); + + spislave_cpu_tx_fifo_reset(); +#endif + + priv->is_tx_enabled = true; + } + else + { + spiwarn("TX buffer empty! Disabling TX for next transaction\n"); + +#ifndef CONFIG_ESP32C3_SPI2_DMA + spislave_cpu_tx_fifo_reset(); +#endif + + priv->is_tx_enabled = false; + } +} + +/**************************************************************************** + * Name: spislave_periph_interrupt + * + * Description: + * Handler for the SPI Slave controller interrupt which is triggered when a + * transfer is finished. + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info + * arg - SPI Slave controller private data + * + * Returned Value: + * Standard interrupt return value. + * + ****************************************************************************/ + +static int spislave_periph_interrupt(int irq, void *context, FAR void *arg) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)arg; + + uint32_t regval = getreg32(SPI_SLAVE1_REG); + uint32_t transfer_size = REG_MASK(regval, SPI_SLV_DATA_BITLEN) / 8; + + if (!priv->is_processing) + { + SPIS_DEV_SELECT(priv->dev, true); + priv->is_processing = true; + } + + /* RX process */ + + if (transfer_size > 0) + { + spislave_store_result(priv, transfer_size); + } + + spislave_prepare_next_rx(priv); + + /* TX process */ + + if (transfer_size > 0 && priv->is_tx_enabled) + { + spislave_evict_sent_data(priv, transfer_size); + } + + spislave_prepare_next_tx(priv); + + if (priv->is_processing && esp32c3_gpioread(priv->config->cs_pin)) + { + priv->is_processing = false; + SPIS_DEV_SELECT(priv->dev, false); + } + + /* Clear the trans_done interrupt flag */ + + setbits(SPI_TRANS_DONE_INT_CLR_M, SPI_DMA_INT_CLR_REG); + + /* Trigger the start of user-defined transaction */ + + setbits(SPI_USR_M, SPI_CMD_REG); + + return 0; +} + +/**************************************************************************** + * Name: spislave_dma_init + * + * Description: + * Initialize ESP32-C3 SPI Slave connection to GDMA engine. + * + * Input Parameters: + * priv - Private SPI Slave controller structure + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2_DMA +void spislave_dma_init(FAR struct spislave_priv_s *priv) +{ + /* Enable GDMA clock for the SPI peripheral */ + + setbits(priv->config->dma_clk_bit, SYSTEM_PERIP_CLK_EN0_REG); + + /* Reset GDMA for the SPI peripheral */ + + resetbits(priv->config->dma_rst_bit, SYSTEM_PERIP_RST_EN0_REG); + + /* Initialize GDMA controller */ + + esp32c3_dma_init(); + + /* Request a GDMA channel for SPI peripheral */ + + priv->dma_channel = esp32c3_dma_request(ESP32C3_DMA_PERIPH_SPI, 1, 1, + true); + if (priv->dma_channel < 0) + { + spierr("Failed to allocate GDMA channel\n"); + + DEBUGASSERT(false); + } + + /* Disable segment transaction mode for SPI Slave */ + + resetbits(SPI_DMA_SLV_SEG_TRANS_EN_M, SPI_DMA_CONF_REG); + + /* Configure DMA In-Link EOF to be generated by trans_done */ + + resetbits(SPI_RX_EOF_EN_M, SPI_DMA_CONF_REG); +} +#endif + +/**************************************************************************** + * Name: spislave_initialize + * + * Description: + * Initialize ESP32-C3 SPI Slave hardware interface. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_initialize(FAR struct spi_slave_ctrlr_s *ctrlr) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + const struct spislave_config_s *config = priv->config; + + spiinfo("ctrlr=%p\n", ctrlr); + + esp32c3_gpiowrite(config->cs_pin, 1); + esp32c3_gpiowrite(config->mosi_pin, 1); + esp32c3_gpiowrite(config->miso_pin, 1); + esp32c3_gpiowrite(config->clk_pin, 1); + +#if SPI_VIA_IOMUX + esp32c3_configgpio(config->cs_pin, INPUT_FUNCTION_2 | PULLUP); + esp32c3_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + + esp32c3_configgpio(config->mosi_pin, INPUT_FUNCTION_2 | PULLUP); + esp32c3_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); + + esp32c3_configgpio(config->miso_pin, OUTPUT_FUNCTION_2); + esp32c3_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); + + esp32c3_configgpio(config->clk_pin, INPUT_FUNCTION_2 | PULLUP); + esp32c3_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); +#else + esp32c3_configgpio(config->cs_pin, INPUT_FUNCTION_1 | PULLUP); + esp32c3_gpio_matrix_in(config->cs_pin, config->cs_insig, 0); + + esp32c3_configgpio(config->mosi_pin, INPUT_FUNCTION_1 | PULLUP); + esp32c3_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); + + esp32c3_configgpio(config->miso_pin, OUTPUT_FUNCTION_1); + esp32c3_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); + + esp32c3_configgpio(config->clk_pin, INPUT_FUNCTION_1 | PULLUP); + esp32c3_gpio_matrix_in(config->clk_pin, config->clk_insig, 0); +#endif + + setbits(config->clk_bit, SYSTEM_PERIP_CLK_EN0_REG); + resetbits(config->rst_bit, SYSTEM_PERIP_RST_EN0_REG); + + /* Configure SPI Slave peripheral */ + + putreg32(0, SPI_CLOCK_REG); + + putreg32(SPI_DOUTDIN_M, SPI_USER_REG); + + putreg32(0, SPI_CTRL_REG); + + putreg32(SPI_SLAVE_MODE_M, SPI_SLAVE_REG); + + spislave_peripheral_reset(); + + /* Use all 64 bytes of the SPI hardware data buffer */ + + resetbits(SPI_USR_MISO_HIGHPART_M | SPI_USR_MOSI_HIGHPART_M, SPI_USER_REG); + + /* Disable interrupts */ + + resetbits(SPI_INT_MASK, SPI_DMA_INT_ENA_REG); + +#ifdef CONFIG_ESP32C3_SPI2_DMA + spislave_dma_init(priv); +#endif + + esp32c3_gpioirqenable(ESP32C3_PIN2IRQ(config->cs_pin), RISING); + + /* Force a transaction done interrupt. + * This interrupt won't fire yet because we initialized the SPI interrupt + * as disabled. This way, we can just enable the SPI interrupt and the + * interrupt handler will kick in, handling any transactions that are + * queued. + */ + + setbits(SPI_TRANS_DONE_INT_RAW_M, SPI_DMA_INT_RAW_REG); + setbits(SPI_TRANS_DONE_INT_ENA_M, SPI_DMA_INT_ENA_REG); +} + +/**************************************************************************** + * Name: spislave_deinitialize + * + * Description: + * Deinitialize ESP32-C3 SPI Slave hardware interface. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_deinitialize(FAR struct spi_slave_ctrlr_s *ctrlr) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + + esp32c3_gpioirqdisable(ESP32C3_PIN2IRQ(priv->config->cs_pin)); + + /* Disable the trans_done interrupt */ + + resetbits(SPI_TRANS_DONE_INT_ENA_M, SPI_DMA_INT_ENA_REG); + +#ifdef CONFIG_ESP32C3_SPI2_DMA + resetbits(priv->config->dma_clk_bit, SYSTEM_PERIP_CLK_EN0_REG); +#endif + + setbits(priv->config->clk_bit, SYSTEM_PERIP_RST_EN0_REG); + resetbits(priv->config->clk_bit, SYSTEM_PERIP_CLK_EN0_REG); + + priv->mode = SPISLAVE_MODE0; + priv->nbits = 0; + priv->tx_length = 0; + priv->rx_length = 0; + priv->is_processing = false; + priv->is_tx_enabled = false; +} + +/**************************************************************************** + * Name: spislave_bind + * + * Description: + * Bind the SPI Slave device interface to the SPI Slave controller + * interface and configure the SPI interface. Upon return, the SPI + * slave controller driver is fully operational and ready to perform + * transfers. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * dev - SPI Slave device interface instance + * mode - The SPI mode requested + * nbits - The number of bits requests. + * If value is greater than 0, then it implies MSB first + * If value is less than 0, then it implies LSB first with -nbits + * + * Returned Value: + * None. + * + * Assumptions: + * This implementation currently supports only positive "nbits" values, + * i.e., it always configures the SPI Slave controller driver as MSB first. + * + ****************************************************************************/ + +static void spislave_bind(FAR struct spi_slave_ctrlr_s *ctrlr, + FAR struct spi_slave_dev_s *dev, + enum spi_slave_mode_e mode, + int nbits) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + FAR const void *data = NULL; + irqstate_t flags; + size_t num_words; + + spiinfo("ctrlr=%p dev=%p mode=%d nbits=%d\n", ctrlr, dev, mode, nbits); + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv->dev == NULL); + DEBUGASSERT(dev != NULL); + DEBUGASSERT(nbits > 0); + + flags = enter_critical_section(); + + priv->dev = dev; + + SPIS_DEV_SELECT(dev, false); + + SPIS_DEV_CMDDATA(dev, false); + + priv->rx_length = 0; + priv->tx_length = 0; + priv->is_tx_enabled = false; + + spislave_initialize(ctrlr); + + spislave_setmode(ctrlr, mode); + spislave_setbits(ctrlr, nbits); + + num_words = SPIS_DEV_GETDATA(dev, &data); + + if (data != NULL && num_words > 0) + { + size_t num_bytes = WORDS2BYTES(priv, num_words); + memcpy(priv->tx_buffer, data, num_bytes); + priv->tx_length += num_bytes; + } + + /* Enable the CPU interrupt that is linked to the SPI Slave controller */ + + up_enable_irq(priv->cpuint); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: spislave_unbind + * + * Description: + * Un-bind the SPI Slave device interface from the SPI Slave controller + * interface. Reset the SPI interface and restore the SPI Slave + * controller driver to its initial state. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_unbind(FAR struct spi_slave_ctrlr_s *ctrlr) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + irqstate_t flags; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv->dev != NULL); + + spiinfo("Unbinding %p\n", priv->dev); + + flags = enter_critical_section(); + + up_disable_irq(priv->cpuint); + + esp32c3_gpioirqdisable(ESP32C3_PIN2IRQ(priv->config->cs_pin)); + + /* Disable the trans_done interrupt */ + + resetbits(SPI_TRANS_DONE_INT_ENA_M, SPI_DMA_INT_ENA_REG); + +#ifdef CONFIG_ESP32C3_SPI2_DMA + resetbits(priv->config->dma_clk_bit, SYSTEM_PERIP_CLK_EN0_REG); +#endif + + resetbits(priv->config->clk_bit, SYSTEM_PERIP_CLK_EN0_REG); + + priv->dev = NULL; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: spislave_enqueue + * + * Description: + * Enqueue the next value to be shifted out from the interface. This adds + * the word to the controller driver for a subsequent transfer but has no + * effect on any in-process or currently "committed" transfers. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * data - Pointer to the command/data mode data to be shifted out. + * The data width must be aligned to the nbits parameter which was + * previously provided to the bind() method. + * len - Number of units of "nbits" wide to enqueue, + * "nbits" being the data width previously provided to the bind() + * method. + * + * Returned Value: + * Number of data items successfully queued, or a negated errno: + * - "len" if all the data was successfully queued + * - "0..len-1" if queue is full + * - "-errno" in any other error + * + ****************************************************************************/ + +static int spislave_enqueue(FAR struct spi_slave_ctrlr_s *ctrlr, + FAR const void *data, + size_t len) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + size_t num_bytes = WORDS2BYTES(priv, len); + size_t bufsize; + irqstate_t flags; + int enqueued_words; + + spiinfo("ctrlr=%p, data=%p, num_bytes=%zu\n", ctrlr, data, num_bytes); + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv->dev != NULL); + + flags = enter_critical_section(); + + bufsize = SPI_SLAVE_BUFSIZE - priv->tx_length; + if (bufsize == 0) + { + leave_critical_section(flags); + return -ENOSPC; + } + + num_bytes = MIN(num_bytes, bufsize); + memcpy(priv->tx_buffer + priv->tx_length, data, num_bytes); + priv->tx_length += num_bytes; + + enqueued_words = BYTES2WORDS(priv, num_bytes); + + if (!priv->is_processing) + { + spislave_prepare_next_tx(priv); + } + + leave_critical_section(flags); + + return enqueued_words; +} + +/**************************************************************************** + * Name: spislave_qfull + * + * Description: + * Return true if the queue is full or false if there is space to add an + * additional word to the queue. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * true if the output queue is full, false otherwise. + * + ****************************************************************************/ + +static bool spislave_qfull(FAR struct spi_slave_ctrlr_s *ctrlr) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + irqstate_t flags; + bool is_full = false; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv->dev != NULL); + + spiinfo("ctrlr=%p\n", ctrlr); + + flags = enter_critical_section(); + is_full = priv->tx_length == SPI_SLAVE_BUFSIZE; + leave_critical_section(flags); + + return is_full; +} + +/**************************************************************************** + * Name: spislave_qflush + * + * Description: + * Discard all saved values in the output queue. On return from this + * function the output queue will be empty. Any in-progress or otherwise + * "committed" output values may not be flushed. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void spislave_qflush(FAR struct spi_slave_ctrlr_s *ctrlr) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + irqstate_t flags; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv->dev != NULL); + + spiinfo("ctrlr=%p\n", ctrlr); + + flags = enter_critical_section(); + priv->tx_length = 0; + priv->is_tx_enabled = false; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: spislave_qpoll + * + * Description: + * Tell the controller to output all the receive queue data. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * Number of units of width "nbits" left in the RX queue. If the device + * accepted all the data, the return value will be 0. + * + ****************************************************************************/ + +static size_t spislave_qpoll(FAR struct spi_slave_ctrlr_s *ctrlr) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + irqstate_t flags; + uint32_t tmp; + uint32_t recv_n; + size_t remaining_words; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv->dev != NULL); + + spiinfo("ctrlr=%p\n", ctrlr); + + flags = enter_critical_section(); + + tmp = SPIS_DEV_RECEIVE(priv->dev, priv->rx_buffer, + BYTES2WORDS(priv, priv->rx_length)); + recv_n = WORDS2BYTES(priv, tmp); + if (recv_n < priv->rx_length) + { + /* If the upper layer does not receive all of the data from the receive + * buffer, move the remaining data to the head of the buffer. + */ + + priv->rx_length -= recv_n; + memmove(priv->rx_buffer, priv->rx_buffer + recv_n, priv->rx_length); + } + else + { + priv->rx_length = 0; + } + + remaining_words = BYTES2WORDS(priv, priv->rx_length); + + leave_critical_section(flags); + + return remaining_words; +} + +/**************************************************************************** + * Name: esp32c3_spislave_ctrlr_initialize + * + * Description: + * Initialize the selected SPI Slave bus. + * + * Input Parameters: + * port - Port number (for hardware that has multiple SPI Slave interfaces) + * + * Returned Value: + * Valid SPI Slave controller structure reference on success; + * NULL on failure. + * + ****************************************************************************/ + +FAR struct spi_slave_ctrlr_s *esp32c3_spislave_ctrlr_initialize(int port) +{ + FAR struct spi_slave_ctrlr_s *spislave_dev; + FAR struct spislave_priv_s *priv; + irqstate_t flags; + + switch (port) + { +#ifdef CONFIG_ESP32C3_SPI2 + case ESP32C3_SPI2: + priv = &esp32c3_spi2slave_priv; + break; +#endif + default: + return NULL; + } + + spislave_dev = (FAR struct spi_slave_ctrlr_s *)priv; + + flags = enter_critical_section(); + + if ((volatile int)priv->refs != 0) + { + leave_critical_section(flags); + + return spislave_dev; + } + + /* Attach IRQ for CS pin interrupt */ + + DEBUGVERIFY(irq_attach(ESP32C3_PIN2IRQ(priv->config->cs_pin), + spislave_cs_interrupt, + priv)); + + if (priv->cpuint != -ENOMEM) + { + /* Disable the provided CPU Interrupt to configure it. */ + + up_disable_irq(priv->cpuint); + } + + priv->cpuint = esp32c3_request_irq(priv->config->periph, + ESP32C3_INT_PRIO_DEF, + ESP32C3_INT_LEVEL); + if (priv->cpuint < 0) + { + /* Failed to allocate a CPU interrupt of this type. */ + + leave_critical_section(flags); + + return NULL; + } + + if (irq_attach(priv->config->irq, spislave_periph_interrupt, priv) != OK) + { + /* Failed to attach IRQ, so CPU interrupt must be freed. */ + + esp32c3_free_cpuint(priv->config->periph); + priv->cpuint = -ENOMEM; + leave_critical_section(flags); + + return NULL; + } + + priv->refs++; + + leave_critical_section(flags); + + return spislave_dev; +} + +/**************************************************************************** + * Name: esp32c3_spislave_ctrlr_uninitialize + * + * Description: + * Uninitialize an SPI Slave bus. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_spislave_ctrlr_uninitialize(FAR struct spi_slave_ctrlr_s *ctrlr) +{ + FAR struct spislave_priv_s *priv = (FAR struct spislave_priv_s *)ctrlr; + irqstate_t flags; + + DEBUGASSERT(ctrlr != NULL); + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(flags); + return OK; + } + + up_disable_irq(priv->cpuint); + esp32c3_free_cpuint(priv->config->periph); + priv->cpuint = -ENOMEM; + + spislave_deinitialize(ctrlr); + + leave_critical_section(flags); + + return OK; +} + +#endif /* defined(CONFIG_ESP32C3_SPI) && defined (CONFIG_SPI_SLAVE) */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_spiflash.c b/arch/risc-v/src/esp32c3/esp32c3_spiflash.c index 96f19ad30ff..ecd9ad86c95 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_spiflash.c +++ b/arch/risc-v/src/esp32c3/esp32c3_spiflash.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -36,13 +37,41 @@ #include #include +#include "esp32c3_attr.h" #include "esp32c3_spiflash.h" #include "rom/esp32c3_spiflash.h" +#include "hardware/esp32c3_soc.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* RO data page in MMU index */ + +#define DROM0_PAGES_START (2) +#define DROM0_PAGES_END (128) + +/* MMU invalid value */ + +#define INVALID_MMU_VAL (0x100) + +/* MMU page size */ + +#define SPI_FLASH_MMU_PAGE_SIZE (0x10000) + +/* MMU base virtual mapped address */ + +#define VADDR0_START_ADDR (0x3c020000) + +/* Flash MMU table for CPU */ + +#define MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE) + +#define MMU_ADDR2PAGE(_addr) ((_addr) / SPI_FLASH_MMU_PAGE_SIZE) +#define MMU_ADDR2OFF(_addr) ((_addr) % SPI_FLASH_MMU_PAGE_SIZE) +#define MMU_BYTES2PAGES(_n) (((_n) + SPI_FLASH_MMU_PAGE_SIZE - 1) / \ + SPI_FLASH_MMU_PAGE_SIZE) + #define SPI_FLASH_BLK_SIZE 256 #define SPI_FLASH_ERASE_SIZE 4096 #define SPI_FLASH_SIZE (4 * 1024 * 1024) @@ -72,6 +101,37 @@ struct esp32c3_spiflash_s const struct spiflash_legacy_data_s **data; }; +/* SPI Flash map request data */ + +struct spiflash_map_req_s +{ + /* Request mapping SPI Flash base address */ + + uint32_t src_addr; + + /* Request mapping SPI Flash size */ + + uint32_t size; + + /* Mapped memory pointer */ + + void *ptr; + + /* Mapped started MMU page index */ + + uint32_t start_page; + + /* Mapped MMU page count */ + + uint32_t page_cnt; +}; + +struct spiflash_cachestate_s +{ + irqstate_t flags; + uint32_t val; +}; + /**************************************************************************** * Private Functions Prototypes ****************************************************************************/ @@ -103,6 +163,14 @@ static ssize_t esp32c3_bwrite_encrypt(struct mtd_dev_s *dev, static int esp32c3_ioctl(struct mtd_dev_s *dev, int cmd, unsigned long arg); +/**************************************************************************** + * Public Functions Declaration + ****************************************************************************/ + +extern int cache_invalidate_addr(uint32_t addr, uint32_t size); +extern uint32_t cache_suspend_icache(void); +extern void cache_resume_icache(uint32_t val); + /**************************************************************************** * Public Data ****************************************************************************/ @@ -154,6 +222,175 @@ static sem_t g_exclsem = SEM_INITIALIZER(1); * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: spiflash_opstart + * + * Description: + * Prepare for an SPIFLASH operation. + * + ****************************************************************************/ + +static inline void spiflash_opstart(struct spiflash_cachestate_s *state) +{ + state->flags = enter_critical_section(); + state->val = cache_suspend_icache() << 16; +} + +/**************************************************************************** + * Name: spiflash_opdone + * + * Description: + * Undo all the steps of opstart. + * + ****************************************************************************/ + +static inline void spiflash_opdone(const struct spiflash_cachestate_s *state) +{ + cache_resume_icache(state->val >> 16); + leave_critical_section(state->flags); +} + +/**************************************************************************** + * Name: esp32c3_mmap + * + * Description: + * Mapped SPI Flash address to ESP32-C3's address bus, so that software + * can read SPI Flash data by reading data from memory access. + * + * If SPI Flash hardware encryption is enable, the read from mapped + * address is decrypted. + * + * Input Parameters: + * req - SPI Flash mapping requesting parameters + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32c3_mmap(struct spiflash_map_req_s *req) +{ + int ret; + int i; + int start_page; + int flash_page; + int page_cnt; + uint32_t mapped_addr; + struct spiflash_cachestate_s state; + + spiflash_opstart(&state); + + for (start_page = DROM0_PAGES_START; + start_page < DROM0_PAGES_END; + ++start_page) + { + if (MMU_TABLE[start_page] == INVALID_MMU_VAL) + { + break; + } + } + + flash_page = MMU_ADDR2PAGE(req->src_addr); + page_cnt = MMU_BYTES2PAGES(req->size); + + if (start_page + page_cnt < DROM0_PAGES_END) + { + mapped_addr = (start_page - DROM0_PAGES_START) * + SPI_FLASH_MMU_PAGE_SIZE + + VADDR0_START_ADDR; + + for (i = 0; i < page_cnt; i++) + { + MMU_TABLE[start_page + i] = flash_page + i; + cache_invalidate_addr(mapped_addr + i * SPI_FLASH_MMU_PAGE_SIZE, + SPI_FLASH_MMU_PAGE_SIZE); + } + + req->start_page = start_page; + req->page_cnt = page_cnt; + req->ptr = (void *)(mapped_addr + MMU_ADDR2OFF(req->src_addr)); + ret = OK; + } + else + { + ret = -ENOBUFS; + } + + spiflash_opdone(&state); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_ummap + * + * Description: + * Unmap SPI Flash address in ESP32-C3's address bus, and free resource. + * + * Input Parameters: + * req - SPI Flash mapping requesting parameters + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void IRAM_ATTR esp32c3_ummap(const struct spiflash_map_req_s *req) +{ + int i; + struct spiflash_cachestate_s state; + + spiflash_opstart(&state); + + for (i = req->start_page; i < req->start_page + req->page_cnt; ++i) + { + MMU_TABLE[i] = INVALID_MMU_VAL; + } + + spiflash_opdone(&state); +} + +/**************************************************************************** + * Name: esp32c3_readdata_encrypted + * + * Description: + * Read decrypted data from SPI Flash at designated address when + * enable SPI Flash hardware encryption. + * + * Input Parameters: + * addr - target address + * buffer - data buffer pointer + * size - data number + * + * Returned Value: + * OK if success or a negative value if fail. + * + ****************************************************************************/ + +static IRAM_ATTR int esp32c3_readdata_encrypted(uint32_t addr, + uint8_t *buffer, + uint32_t size) +{ + int ret; + struct spiflash_map_req_s req = + { + .src_addr = addr, + .size = size + }; + + ret = esp32c3_mmap(&req); + if (ret < 0) + { + return ret; + } + + memcpy(buffer, req.ptr, size); + + esp32c3_ummap(&req); + + return OK; +} + /**************************************************************************** * Name: esp32c3_erase * @@ -359,7 +596,7 @@ static ssize_t esp32c3_read_decrypt(struct mtd_dev_s *dev, return ret; } - ret = spi_flash_read_encrypted(offset, buffer, nbytes); + ret = esp32c3_readdata_encrypted(offset, buffer, nbytes); nxsem_post(&g_exclsem); @@ -393,9 +630,9 @@ static ssize_t esp32c3_read_decrypt(struct mtd_dev_s *dev, ****************************************************************************/ static ssize_t esp32c3_bread_decrypt(struct mtd_dev_s *dev, - off_t startblock, - size_t nblocks, - uint8_t *buffer) + off_t startblock, + size_t nblocks, + uint8_t *buffer) { ssize_t ret; uint32_t addr = startblock * SPI_FLASH_BLK_SIZE; @@ -412,7 +649,7 @@ static ssize_t esp32c3_bread_decrypt(struct mtd_dev_s *dev, return ret; } - ret = spi_flash_read_encrypted(addr, buffer, size); + ret = esp32c3_readdata_encrypted(addr, buffer, size); nxsem_post(&g_exclsem); diff --git a/arch/risc-v/src/esp32c3/esp32c3_textheap.c b/arch/risc-v/src/esp32c3/esp32c3_textheap.c new file mode 100644 index 00000000000..2bc65bf3891 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_textheap.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_textheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "hardware/esp32c3_soc.h" + +#ifdef CONFIG_ESP32C3_RTC_HEAP +#include "esp32c3_rtcheap.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define D_I_BUS_OFFSET 0x700000 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_textheap_memalign() + * + * Description: + * Allocate memory for module text with the specified alignment. + * + ****************************************************************************/ + +FAR void *up_textheap_memalign(size_t align, size_t size) +{ + FAR void *ret = NULL; + + /* Prioritise allocating from RTC. If that fails, allocate from the + * main heap. + */ + +#ifdef CONFIG_ESP32C3_RTC_HEAP + ret = esp32c3_rtcheap_memalign(align, size); +#endif + + if (ret == NULL) + { + ret = kmm_memalign(align, size); + if (ret) + { + /* kmm_memalign buffer is at the Data bus offset. Adjust it so we + * can access it from the Instruction bus. + */ + + ret += D_I_BUS_OFFSET; + } + } + + return ret; +} + +/**************************************************************************** + * Name: up_textheap_free() + * + * Description: + * Free memory for module text. + * + ****************************************************************************/ + +void up_textheap_free(FAR void *p) +{ + if (p) + { +#ifdef CONFIG_ESP32C3_RTC_HEAP + if (esp32c3_ptr_rtc(p)) + { + esp32c3_rtcheap_free(p); + } + else +#endif + { + p -= D_I_BUS_OFFSET; + kmm_free(p); + } + } +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_tickless.c b/arch/risc-v/src/esp32c3/esp32c3_tickless.c new file mode 100644 index 00000000000..12c756699ee --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_tickless.c @@ -0,0 +1,608 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_tickless.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Tickless OS Support. + * + * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts + * is suppressed and the platform specific code is expected to provide the + * following custom functions. + * + * void up_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_initialize()). + * int up_timer_gettime(FAR struct timespec *ts): Returns the current + * time from the platform specific time source. + * int up_timer_cancel(void): Cancels the interval timer. + * int up_timer_start(FAR const struct timespec *ts): Start (or re-starts) + * the interval timer. + * + * The RTOS will provide the following interfaces for use by the platform- + * specific interval timer implementation: + * + * void sched_timer_expiration(void): Called by the platform-specific + * logic when the interval timer expires. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "esp32c3_attr.h" +#include "chip.h" +#include "esp32c3.h" +#include "esp32c3_irq.h" +#include "hardware/esp32c3_systimer.h" +#include "hardware/esp32c3_system.h" +#include "hardware/esp32c3_soc.h" + +#include "esp32c3_rtc.h" + +#ifdef CONFIG_SCHED_TICKLESS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_SYSTIMER_TICKS_PER_SEC (16 * 1000 * 1000) + +#define CTICK_PER_SEC (ESP32C3_SYSTIMER_TICKS_PER_SEC) +#define CTICK_PER_USEC (CTICK_PER_SEC / USEC_PER_SEC) + +#define SEC_2_CTICK(s) ((s) * CTICK_PER_SEC) +#define USEC_2_CTICK(us) ((us) * CTICK_PER_USEC) +#define NSEC_2_CTICK(nsec) (((nsec) * CTICK_PER_USEC) / NSEC_PER_USEC) + +#define CTICK_2_SEC(tick) ((tick) / CTICK_PER_SEC) +#define CTICK_2_USEC(tick) ((tick) / CTICK_PER_USEC) +#define CTICK_2_NSEC(tick) ((tick) * 1000 / CTICK_PER_USEC) + +#define CPU_TICKS_MAX (UINT32_MAX / 4 * 3) + +/* The structure of the counter value in systimer */ + +struct systimer_counter_value_s +{ + union + { + struct + { + uint64_t lo : SOC_SYSTIMER_BIT_WIDTH_LO; /* Low part of counter value */ + uint64_t hi : SOC_SYSTIMER_BIT_WIDTH_HI; /* High part of counter value */ + }; + uint64_t val; /* counter value */ + }; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint64_t up_tmr_getcounter(void); +static inline uint64_t up_tmr_getalarmvalue(void); +static inline void up_tmr_counter_advance(uint64_t tick); +static void IRAM_ATTR up_tmr_setcounter(uint64_t ticks); +static void IRAM_ATTR up_timer_expire(int irq, void *regs, FAR void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_timer_started; /* Whether an interval timer is being started */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_tmr_getcounter + * + * Description: + * Return the total ticks of system since power-on. + * + * Input Parameters: + * None + * + * Returned Value: + * Total system ticks + * + ****************************************************************************/ + +static inline uint64_t up_tmr_getcounter(void) +{ + uint32_t lo; + uint32_t lo_start; + uint32_t hi; + + /* Set the "update" bit and wait for acknowledgment */ + + REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG, 1 << 30); + while (!REG_GET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG, 1 << 29)); + + /* Read LO, HI, then LO again, check that LO returns the same value. + * This accounts for the case when an interrupt may happen between reading + * HI and LO values, and this function may get called from the ISR. + * In this case, the repeated read will return consistent values. + */ + + lo_start = getreg32(SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG); + do + { + lo = lo_start; + hi = getreg32(SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG); + lo_start = getreg32(SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG); + } + while (lo_start != lo); + + struct systimer_counter_value_s result = + { + .lo = lo, + .hi = hi + }; + + return result.val; +} + +/**************************************************************************** + * Name: up_tmr_getalarmvalue + * + * Description: + * Return the remaining ticks in the currently running timer. + * + * Input Parameters: + * None + * + * Returned Value: + * Remaining ticks + * + ****************************************************************************/ + +static inline uint64_t up_tmr_getalarmvalue(void) +{ + return ((uint64_t) getreg32(SYS_TIMER_SYSTIMER_TARGET0_HI_REG) << 32) \ + | getreg32(SYS_TIMER_SYSTIMER_TARGET0_LO_REG); +} + +/**************************************************************************** + * Name: up_tmr_counter_advance + * + * Description: + * Adjust current system tick by a certain value + * + * Input Parameters: + * ticks - Adjustment to apply to system time, in microseconds + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void up_tmr_counter_advance(uint64_t tick) +{ + /* set_counter_value */ + + putreg32(tick & 0xffffffff, SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG); + putreg32((tick >> 32) & 0xfffff, SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG); + + /* apply_counter_value */ + + REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG, SYS_TIMER_TIMER_UNIT0_LOAD); +} + +/**************************************************************************** + * Name: up_tmr_setcounter + * + * Description: + * Set the new value of the compare register + * + * Input Parameters: + * ticks - ticks for a timer operation + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR up_tmr_setcounter(uint64_t ticks) +{ + uint64_t alarm_ticks = up_tmr_getcounter() + ticks; + + /* select_alarm_mode */ + + REG_CLR_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG, + SYS_TIMER_TARGET0_PERIOD_MODE); + + /* set alarm value */ + + putreg32(alarm_ticks & 0xffffffff, SYS_TIMER_SYSTIMER_TARGET0_LO_REG); + putreg32((alarm_ticks >> 32) & 0xfffff, SYS_TIMER_SYSTIMER_TARGET0_HI_REG); + + /* apply alarm vaule */ + + REG_SET_BIT(SYS_TIMER_SYSTIMER_COMP0_LOAD_REG, SYS_TIMER_TIMER_COMP0_LOAD); + + /* Enable alarm */ + + REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, SYS_TIMER_TARGET0_WORK_EN); + + /* Enable interrupt */ + + REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_CLR_REG, SYS_TIMER_TARGET0_INT_CLR); + REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_ENA_REG, SYS_TIMER_TARGET0_INT_ENA); +} + +/**************************************************************************** + * Name: up_timer_expire + * + * Description: + * Called as the IRQ handler for timer expiration. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR up_timer_expire(int irq, void *regs, FAR void *arg) +{ + g_timer_started = false; + setbits(SYS_TIMER_TARGET0_INT_CLR, SYS_TIMER_SYSTIMER_INT_CLR_REG); + nxsched_timer_expiration(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * up_timer_initialize() was called). This function is functionally + * equivalent to: + * + * int clock_gettime(clockid_t clockid, FAR struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int IRAM_ATTR up_timer_gettime(FAR struct timespec *ts) +{ + uint64_t ticks; + irqstate_t flags; + + flags = enter_critical_section(); + + ticks = up_tmr_getcounter(); + ts->tv_sec = CTICK_2_SEC(ticks); + ts->tv_nsec = CTICK_2_NSEC(ticks % CTICK_PER_SEC); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: up_timer_cancel + * + * Description: + * Cancel the interval timer and return the time remaining on the timer. + * These two steps need to be as nearly atomic as possible. + * nxsched_timer_expiration() will not be called unless the timer is + * restarted with up_timer_start(). + * + * If, as a race condition, the timer has already expired when this + * function is called, then that pending interrupt must be cleared so + * that up_timer_start() and the remaining time of zero should be + * returned. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Location to return the remaining time. Zero should be returned + * if the timer is not active. ts may be zero in which case the + * time remaining is not returned. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int IRAM_ATTR up_timer_cancel(FAR struct timespec *ts) +{ + uint64_t alarm_value; + uint64_t counter; + irqstate_t flags; + + flags = enter_critical_section(); + + if (ts != NULL) + { + if (g_timer_started == false) + { + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + else + { + alarm_value = up_tmr_getalarmvalue(); + counter = up_tmr_getcounter(); + if (alarm_value <= counter) + { + alarm_value = 0; + } + else + { + alarm_value -= counter; + } + + ts->tv_sec = CTICK_2_SEC(alarm_value); + ts->tv_nsec = CTICK_2_NSEC(alarm_value % CTICK_PER_SEC); + } + } + + g_timer_started = false; + REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, SYS_TIMER_TARGET0_WORK_EN); + REG_CLR_BIT(SYS_TIMER_SYSTIMER_INT_ENA_REG, SYS_TIMER_TARGET0_INT_ENA); + REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_CLR_REG, SYS_TIMER_TARGET0_INT_CLR); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: up_timer_start + * + * Description: + * Start the interval timer. nxsched_timer_expiration() will be + * called at the completion of the timeout (unless up_timer_cancel + * is called to stop the timing. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the time interval until nxsched_timer_expiration() is + * called. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int IRAM_ATTR up_timer_start(FAR const struct timespec *ts) +{ + uint64_t cpu_ticks; + irqstate_t flags; + + flags = enter_critical_section(); + + if (g_timer_started == true) + { + up_timer_cancel(NULL); + } + + cpu_ticks = SEC_2_CTICK((uint64_t)ts->tv_sec) + + NSEC_2_CTICK((uint64_t)ts->tv_nsec); + + up_tmr_setcounter(cpu_ticks); + g_timer_started = true; + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * Initializes all platform-specific timer facilities. This function is + * called early in the initialization sequence by up_initialize(). + * On return, the current up-time should be available from + * up_timer_gettime() and the interval timer is ready for use (but not + * actively timing. + * + * Provided by platform-specific code and called from the architecture- + * specific logic. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * Called early in the initialization sequence before any special + * concurrency protections are required. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + int cpuint; + + g_timer_started = false; + + /* Enable timer clock */ + + setbits(SYSTEM_SYSTIMER_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG); + resetbits(SYSTEM_SYSTIMER_RST, SYSTEM_PERIP_RST_EN0_REG); + + setbits(SYS_TIMER_CLK_EN, SYS_TIMER_SYSTIMER_CONF_REG); + + /* Stall timer when stall CPU, specially when using JTAG to debug */ + + setbits(SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN, SYS_TIMER_SYSTIMER_CONF_REG); + + /* NOTE: Timer 0 is an internal interrupt source so we do not need to + * attach any peripheral ID to the dedicated CPU interrupt. + */ + + /* Attach the timer interrupt */ + + cpuint = esp32c3_request_irq(ESP32C3_PERIPH_SYSTIMER_T0, + ESP32C3_INT_PRIO_DEF, + ESP32C3_INT_LEVEL); + + /* Attach the timer interrupt. */ + + irq_attach(ESP32C3_IRQ_SYSTIMER_T0, (xcpt_t)up_timer_expire, NULL); + + /* Enable the allocated CPU interrupt. */ + + up_enable_irq(cpuint); +} + +/**************************************************************************** + * Name: up_get_idletime + * + * Description: + * This function returns the idle time. + * + * Input Parameters: + * None + * + * Returned Value: + * The time in system ticks remaining for idle. + * Zero means system is busy. + * + ****************************************************************************/ + +uint32_t IRAM_ATTR up_get_idletime(void) +{ + uint32_t us; + uint64_t alarm_value; + uint64_t counter; + irqstate_t flags; + + flags = enter_critical_section(); + if (g_timer_started == false) + { + us = 0; + } + else + { + alarm_value = up_tmr_getalarmvalue(); + counter = up_tmr_getcounter(); + if (alarm_value > counter) + { + us = CTICK_2_USEC(alarm_value - counter); + } + else + { + us = 0; + } + } + + leave_critical_section(flags); + + return us; +} + +/**************************************************************************** + * Name: up_step_idletime + * + * Description: + * Add system time by idletime_us. + * + * Input Parameters: + * us - Idle time(us) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR up_step_idletime(uint32_t us) +{ + uint64_t step_counter; + uint64_t alarm_value; + irqstate_t flags; + + DEBUGASSERT(g_timer_started); + + flags = enter_critical_section(); + + alarm_value = up_tmr_getalarmvalue(); + step_counter = USEC_2_CTICK((uint64_t)us) + up_tmr_getcounter(); + if (step_counter > alarm_value) + { + DEBUGASSERT(0); + } + + up_tmr_counter_advance(step_counter); + + leave_critical_section(flags); +} + +#endif /* CONFIG_SCHED_TICKLESS */ \ No newline at end of file diff --git a/arch/risc-v/src/esp32c3/esp32c3_tickless.h b/arch/risc-v/src/esp32c3/esp32c3_tickless.h new file mode 100644 index 00000000000..7c0609eac6a --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_tickless.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_tickless.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TICKLESS_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TICKLESS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_get_idletime + * + * Description: + * This function returns the idle time. + * + * Input Parameters: + * None + * + * Returned Value: + * The time in system ticks remaining for idle. + * Zero means system is busy. + * + ****************************************************************************/ + +uint32_t up_get_idletime(void); + +/**************************************************************************** + * Name: up_step_idletime + * + * Description: + * Add system time by idletime_us. + * + * Input Parameters: + * idletime_us - Idle time(us) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_step_idletime(uint32_t idletime_us); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TICKLESS_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_tim.c b/arch/risc-v/src/esp32c3/esp32c3_tim.c index 5acb8983e6c..a8379fd7702 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_tim.c +++ b/arch/risc-v/src/esp32c3/esp32c3_tim.c @@ -27,6 +27,7 @@ #include #include +#include #include #include "riscv_arch.h" @@ -34,6 +35,7 @@ #include "esp32c3_tim.h" #include "esp32c3_irq.h" +#include "esp32c3_gpio.h" /**************************************************************************** * Private Types @@ -82,6 +84,7 @@ static int esp32c3_tim_setisr(FAR struct esp32c3_tim_dev_s *dev, static void esp32c3_tim_enableint(FAR struct esp32c3_tim_dev_s *dev); static void esp32c3_tim_disableint(FAR struct esp32c3_tim_dev_s *dev); static void esp32c3_tim_ackint(FAR struct esp32c3_tim_dev_s *dev); +static int esp32c3_tim_checkint(FAR struct esp32c3_tim_dev_s *dev); /**************************************************************************** * Private Data @@ -107,7 +110,8 @@ struct esp32c3_tim_ops_s esp32c3_tim_ops = .setisr = esp32c3_tim_setisr, .enableint = esp32c3_tim_enableint, .disableint = esp32c3_tim_disableint, - .ackint = esp32c3_tim_ackint + .ackint = esp32c3_tim_ackint, + .checkint = esp32c3_tim_checkint }; #ifdef CONFIG_ESP32C3_TIMER0 @@ -654,6 +658,31 @@ static void esp32c3_tim_ackint(FAR struct esp32c3_tim_dev_s *dev) modifyreg32(TIMG_INT_CLR_TIMERS_REG(priv->id), 0, TIMG_T0_INT_CLR_M); } +/**************************************************************************** + * Name: esp32c3_tim_checkint + * + * Description: + * Check the interrupt status bit. + * + * Parameters: + * dev - Pointer to the timer driver struct. + * + * Returned Values: + * Return 1 in case of an interrupt is triggered, otherwise 0. + * + ****************************************************************************/ + +static int esp32c3_tim_checkint(FAR struct esp32c3_tim_dev_s *dev) +{ + struct esp32c3_tim_priv_s *priv = (struct esp32c3_tim_priv_s *)dev; + uint32_t reg_value; + + DEBUGASSERT(dev != NULL); + + reg_value = getreg32(TIMG_INT_ST_TIMERS_REG(priv->id)); + return ((reg_value & TIMG_T0_INT_ST_V) >> TIMG_T0_INT_ST_S); +} + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/esp32c3/esp32c3_tim.h b/arch/risc-v/src/esp32c3/esp32c3_tim.h index e3a00989cff..12ad92ad6ea 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_tim.h +++ b/arch/risc-v/src/esp32c3/esp32c3_tim.h @@ -53,6 +53,7 @@ #define ESP32C3_TIM_ENABLEINT(d) ((d)->ops->enableint(d)) #define ESP32C3_TIM_DISABLEINT(d) ((d)->ops->disableint(d)) #define ESP32C3_TIM_ACKINT(d) ((d)->ops->ackint(d)) +#define ESP32C3_TIM_CHECKINT(d) ((d)->ops->checkint(d)) /**************************************************************************** * Public Types @@ -126,6 +127,7 @@ struct esp32c3_tim_ops_s CODE void (*enableint)(FAR struct esp32c3_tim_dev_s *dev); CODE void (*disableint)(FAR struct esp32c3_tim_dev_s *dev); CODE void (*ackint)(FAR struct esp32c3_tim_dev_s *dev); + CODE int (*checkint)(FAR struct esp32c3_tim_dev_s *dev); }; /**************************************************************************** diff --git a/arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c b/arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c index ba6488b5dca..23b7dd0726c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c +++ b/arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/risc-v/src/esp32c3/esp32c3_uid.c b/arch/risc-v/src/esp32c3/esp32c3_uid.c new file mode 100644 index 00000000000..71da0b6bb40 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_uid.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_uid.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "hardware/esp32c3_efuse.h" +#include "esp32c3.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_get_uniqueid + * + * Description: + * Get CPU unique ID. + * + * Parameters: + * uniqueid - unique ID buffer + * + ****************************************************************************/ + +void esp32c3_get_uniqueid(uint8_t *uniqueid) +{ + int i; + + for (i = 0; i < 16; i++) + { + uniqueid[i] = getreg8(EFUSE_RD_SYS_DATA_PART1_0_REG + i); + } +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_uid.h b/arch/risc-v/src/esp32c3/esp32c3_uid.h new file mode 100644 index 00000000000..51c113c3e61 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_uid.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_uid.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_UID_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_UID_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_get_uniqueid + * + * Description: + * Get CPU unique ID. + * + * Parameters: + * uniqueid - unique ID buffer + * + ****************************************************************************/ + +void esp32c3_get_uniqueid(uint8_t *uniqueid); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_UID_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt.c b/arch/risc-v/src/esp32c3/esp32c3_wdt.c index 319e0f58018..f53b8382322 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wdt.c +++ b/arch/risc-v/src/esp32c3/esp32c3_wdt.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include "riscv_arch.h" #include "hardware/esp32c3_rtccntl.h" diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c b/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c index 74f78368d5d..147f77a8ba5 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c +++ b/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c b/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c index 1fd00c0e167..c4f03cf8dcb 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c +++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -49,6 +50,7 @@ #include #include +#include "hardware/esp32c3_rtccntl.h" #include "hardware/esp32c3_syscon.h" #include "esp32c3.h" #include "esp32c3_attr.h" @@ -56,9 +58,19 @@ #include "esp32c3_wifi_adapter.h" #include "esp32c3_rt_timer.h" #include "esp32c3_wifi_utils.h" +#include "esp32c3_wlan.h" + +#ifdef CONFIG_PM +#include "esp32c3_pm.h" +#endif #include "espidf_wifi.h" +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST +# include "esp_coexist_internal.h" +# include "esp_coexist_adapter.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -89,6 +101,27 @@ #define ESP_MAX_STA_CONN (4) #define ESP_WIFI_CHANNEL (6) +#ifndef CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL +#define CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL 3 +#endif + +#define DEFAULT_LISTEN_INTERVAL CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL + +/* CONFIG_POWER_SAVE_MODEM */ + +#if defined(CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM) +# define DEFAULT_PS_MODE WIFI_PS_MIN_MODEM +#elif defined(CONFIG_EXAMPLE_POWER_SAVE_MAX_MODEM) +# define DEFAULT_PS_MODE WIFI_PS_MAX_MODEM +#elif defined(CONFIG_EXAMPLE_POWER_SAVE_NONE) +# define DEFAULT_PS_MODE WIFI_PS_NONE +#else +# define DEFAULT_PS_MODE WIFI_PS_NONE +#endif + +#define RTC_CLK_CAL_FRACT (19) +#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -200,6 +233,11 @@ static void *esp_semphr_create(uint32_t max, uint32_t init); static void esp_semphr_delete(void *semphr); static int32_t esp_semphr_take(void *semphr, uint32_t block_time_tick); static int32_t esp_semphr_give(void *semphr); +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST +static int32_t esp_semphr_take_from_isr(void *semphr, void *hptw); +static int32_t esp_semphr_give_from_isr(void *semphr, void *hptw); +static int wifi_is_in_isr(void); +#endif static void *esp_thread_semphr_get(void); static void *esp_mutex_create(void); static void *esp_recursive_mutex_create(void); @@ -326,6 +364,14 @@ static void *wifi_coex_get_schm_curr_phase(void); static int wifi_coex_set_schm_curr_phase_idx(int idx); static int wifi_coex_get_schm_curr_phase_idx(void); +/**************************************************************************** + * Extern Functions declaration + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_BLE +extern void coex_pti_v2(void); +#endif + /**************************************************************************** * Public Functions declaration ****************************************************************************/ @@ -408,6 +454,27 @@ static bool g_softap_started; static wifi_txdone_cb_t g_softap_txdone_cb; #endif +/* Wi-Fi and BT coexistance OS adapter data */ + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST +coex_adapter_funcs_t g_coex_adapter_funcs = +{ + ._version = COEX_ADAPTER_VERSION, + ._task_yield_from_isr = esp_task_yield_from_isr, + ._semphr_create = esp_semphr_create, + ._semphr_delete = esp_semphr_delete, + ._semphr_take_from_isr = esp_semphr_take_from_isr, + ._semphr_give_from_isr = esp_semphr_give_from_isr, + ._semphr_take = esp_semphr_take, + ._semphr_give = esp_semphr_give, + ._is_in_isr = wifi_is_in_isr, + ._malloc_internal = esp_malloc_internal, + ._free = esp_free, + ._esp_timer_get_time = esp_timer_get_time, + ._magic = COEX_ADAPTER_MAGIC, +}; +#endif + /**************************************************************************** * Public Data ****************************************************************************/ @@ -1103,6 +1170,69 @@ static int32_t esp_semphr_give(void *semphr) return osi_errno_trans(ret); } +/**************************************************************************** + * Name: esp_semphr_take_from_isr + * + * Description: + * Try to task semaphore in interrupt + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST +static int32_t esp_semphr_take_from_isr(void *semphr, void *hptw) +{ + *(int *)hptw = 0; + + return esp_semphr_take(semphr, 0); +} + +/**************************************************************************** + * Name: esp_semphr_give_from_isr + * + * Description: + * Post semaphore in interrupt + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t esp_semphr_give_from_isr(void *semphr, void *hptw) +{ + *(int *)hptw = 0; + + return esp_semphr_give(semphr); +} + +/**************************************************************************** + * Name: wifi_is_in_isr + * + * Description: + * Check current is in interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * true if in interrupt or false if not + * + ****************************************************************************/ + +static int IRAM_ATTR wifi_is_in_isr(void) +{ + return up_interrupt_context(); +} +#endif + /**************************************************************************** * Name: esp_thread_semphr_get * @@ -1935,16 +2065,7 @@ static void *esp_malloc(unsigned int size) static void esp_free(void *ptr) { -#ifdef CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP - if (xtensa_imm_heapmember(ptr)) - { - xtensa_imm_free(ptr); - } - else -#endif - { - kmm_free(ptr); - } + kmm_free(ptr); } /**************************************************************************** @@ -2038,6 +2159,7 @@ static void esp_evt_work_cb(FAR void *arg) irqstate_t flags; struct evt_adpt *evt_adpt; struct wifi_notify *notify; + wifi_event_sta_disconnected_t *disconnected; while (1) { @@ -2061,7 +2183,7 @@ static void esp_evt_work_cb(FAR void *arg) case WIFI_ADPT_EVT_STA_START: wlinfo("INFO: Wi-Fi sta start\n"); g_sta_connected = false; - ret = esp_wifi_set_ps(WIFI_PS_NONE); + ret = esp_wifi_set_ps(DEFAULT_PS_MODE); if (ret) { wlerr("ERROR: Failed to close PS\n"); @@ -2071,11 +2193,25 @@ static void esp_evt_work_cb(FAR void *arg) case WIFI_ADPT_EVT_STA_CONNECT: wlinfo("INFO: Wi-Fi sta connect\n"); g_sta_connected = true; + ret = esp32c3_wlan_sta_set_linkstatus(true); + if (ret < 0) + { + wlerr("ERROR: Failed to set Wi-Fi station link status\n"); + } + break; case WIFI_ADPT_EVT_STA_DISCONNECT: - wlinfo("INFO: Wi-Fi sta disconnect\n"); + disconnected = (wifi_event_sta_disconnected_t *)evt_adpt->buf; + wlinfo("INFO: Wi-Fi sta disconnect, reason code: %d\n", + disconnected->reason); g_sta_connected = false; + ret = esp32c3_wlan_sta_set_linkstatus(false); + if (ret < 0) + { + wlerr("ERROR: Failed to set Wi-Fi station link status\n"); + } +#ifdef CONFIG_ESP32C3_WIFI_RECONNECT if (g_sta_reconnect) { ret = esp_wifi_connect(); @@ -2084,6 +2220,7 @@ static void esp_evt_work_cb(FAR void *arg) wlerr("ERROR: Failed to connect AP error=%d\n", ret); } } +#endif break; case WIFI_ADPT_EVT_STA_STOP: @@ -2326,24 +2463,30 @@ static void esp_dport_access_stall_other_cpu_end(void) * Name: wifi_apb80m_request * * Description: - * Don't support + * Take Wi-Fi lock in auto-sleep * ****************************************************************************/ static void wifi_apb80m_request(void) { +#ifdef CONFIG_ESP32C3_AUTO_SLEEP + esp32c3_pm_lockacquire(); +#endif } /**************************************************************************** * Name: wifi_apb80m_release * * Description: - * Don't support + * Release Wi-Fi lock in auto-sleep * ****************************************************************************/ static void wifi_apb80m_release(void) { +#ifdef CONFIG_ESP32C3_AUTO_SLEEP + esp32c3_pm_lockrelease(); +#endif } /**************************************************************************** @@ -2420,6 +2563,9 @@ static void wifi_phy_enable(void) esp_phy_enable_clock(); phy_set_wifi_mode_only(0); register_chipv7_phy(&phy_init_data, cal_data, PHY_RF_CAL_NONE); +#ifdef CONFIG_ESP32C3_BLE + coex_pti_v2(); +#endif } g_phy_access_ref++; @@ -2536,7 +2682,7 @@ esp_err_t esp_read_mac(uint8_t *mac, esp_mac_type_t type) regval[0] = getreg32(MAC_ADDR0_REG); regval[1] = getreg32(MAC_ADDR1_REG); - for (i = 0; i < 6; i++) + for (i = 0; i < MAC_LEN; i++) { mac[i] = data[5 - i]; } @@ -3411,11 +3557,26 @@ static int esp_get_time(void *t) /**************************************************************************** * Name: esp_clk_slowclk_cal_get_wrapper + * + * Description: + * Get the calibration value of RTC slow clock + * + * Input Parameters: + * None + * + * Returned Value: + * The calibration value obtained using rtc_clk_cal + * ****************************************************************************/ static uint32_t esp_clk_slowclk_cal_get_wrapper(void) { - return 28639; + /* The bit width of Wi-Fi light sleep clock calibration is 12 while the one + * of system is 19. It should shift 19 - 12 = 7. + */ + + return (getreg32(RTC_SLOW_CLK_CAL_REG) >> (RTC_CLK_CAL_FRACT - + SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH)); } /**************************************************************************** @@ -3750,7 +3911,11 @@ static void esp_wifi_delete_queue(void *queue) static int wifi_coex_init(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_init(); +#else return 0; +#endif } /**************************************************************************** @@ -3763,6 +3928,9 @@ static int wifi_coex_init(void) static void wifi_coex_deinit(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_deinit(); +#endif } /**************************************************************************** @@ -3775,7 +3943,11 @@ static void wifi_coex_deinit(void) static int wifi_coex_enable(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_enable(); +#else return 0; +#endif } /**************************************************************************** @@ -3788,6 +3960,9 @@ static int wifi_coex_enable(void) static void wifi_coex_disable(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_disable(); +#endif } /**************************************************************************** @@ -3800,7 +3975,11 @@ static void wifi_coex_disable(void) static uint32_t esp_coex_status_get(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_status_get(); +#else return 0; +#endif } /**************************************************************************** @@ -3813,6 +3992,9 @@ static uint32_t esp_coex_status_get(void) static void esp_coex_condition_set(uint32_t type, bool dissatisfy) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_condition_set(type, dissatisfy); +#endif } /**************************************************************************** @@ -3824,9 +4006,13 @@ static void esp_coex_condition_set(uint32_t type, bool dissatisfy) ****************************************************************************/ static int esp_coex_wifi_request(uint32_t event, uint32_t latency, - uint32_t duration) + uint32_t duration) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_wifi_request(event, latency, duration); +#else return 0; +#endif } /**************************************************************************** @@ -3839,7 +4025,11 @@ static int esp_coex_wifi_request(uint32_t event, uint32_t latency, static int esp_coex_wifi_release(uint32_t event) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_wifi_release(event); +#else return 0; +#endif } /**************************************************************************** @@ -3852,7 +4042,11 @@ static int esp_coex_wifi_release(uint32_t event) static int wifi_coex_wifi_set_channel(uint8_t primary, uint8_t secondary) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_wifi_channel_set(primary, secondary); +#else return 0; +#endif } /**************************************************************************** @@ -3865,7 +4059,11 @@ static int wifi_coex_wifi_set_channel(uint8_t primary, uint8_t secondary) static int wifi_coex_get_event_duration(uint32_t event, uint32_t *duration) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_event_duration_get(event, duration); +#else return 0; +#endif } /**************************************************************************** @@ -3878,7 +4076,11 @@ static int wifi_coex_get_event_duration(uint32_t event, uint32_t *duration) static int wifi_coex_get_pti(uint32_t event, uint8_t *pti) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_pti_get(event, pti); +#else return 0; +#endif } /**************************************************************************** @@ -3891,6 +4093,9 @@ static int wifi_coex_get_pti(uint32_t event, uint8_t *pti) static void wifi_coex_clear_schm_status_bit(uint32_t type, uint32_t status) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_schm_status_bit_clear(type, status); +#endif } /**************************************************************************** @@ -3903,6 +4108,9 @@ static void wifi_coex_clear_schm_status_bit(uint32_t type, uint32_t status) static void wifi_coex_set_schm_status_bit(uint32_t type, uint32_t status) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_schm_status_bit_set(type, status); +#endif } /**************************************************************************** @@ -3915,7 +4123,11 @@ static void wifi_coex_set_schm_status_bit(uint32_t type, uint32_t status) static int wifi_coex_set_schm_interval(uint32_t interval) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_schm_interval_set(interval); +#else return 0; +#endif } /**************************************************************************** @@ -3928,7 +4140,11 @@ static int wifi_coex_set_schm_interval(uint32_t interval) static uint32_t wifi_coex_get_schm_interval(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_schm_interval_get(); +#else return 0; +#endif } /**************************************************************************** @@ -3941,7 +4157,11 @@ static uint32_t wifi_coex_get_schm_interval(void) static uint8_t wifi_coex_get_schm_curr_period(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_schm_curr_period_get(); +#else return 0; +#endif } /**************************************************************************** @@ -3954,7 +4174,11 @@ static uint8_t wifi_coex_get_schm_curr_period(void) static void *wifi_coex_get_schm_curr_phase(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_schm_curr_phase_get(); +#else return NULL; +#endif } /**************************************************************************** @@ -3968,6 +4192,11 @@ static void *wifi_coex_get_schm_curr_phase(void) static int wifi_coex_set_schm_curr_phase_idx(int idx) { return -1; +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_schm_curr_phase_idx_set(idx); +#else + return 0; +#endif } /**************************************************************************** @@ -3980,7 +4209,11 @@ static int wifi_coex_set_schm_curr_phase_idx(int idx) static int wifi_coex_get_schm_curr_phase_idx(void) { +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + return coex_schm_curr_phase_idx_get(); +#else return 0; +#endif } /**************************************************************************** @@ -4316,6 +4549,35 @@ int pp_printf(const char *format, ...) return 0; } +/**************************************************************************** + * Name: coexist_printf + * + * Description: + * Output format string and its arguments + * + * Input Parameters: + * format - format string + * + * Returned Value: + * 0 + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST +int coexist_printf(const char * format, ...) +{ +#ifdef CONFIG_DEBUG_WIRELESS_INFO + va_list arg; + + va_start(arg, format); + vsyslog(LOG_INFO, format, arg); + va_end(arg); +#endif + + return 0; +} +#endif + /**************************************************************************** * Functions needed by libnet80211.a ****************************************************************************/ @@ -4366,19 +4628,6 @@ int esp_mesh_send_event_internal(int32_t event_id, return -1; } -/**************************************************************************** - * Name: esp_mesh_get_topology - * - * Description: - * Don't support - * - ****************************************************************************/ - -void *esp_mesh_get_topology(void) -{ - return NULL; -} - /**************************************************************************** * Functions needed by libwpa_supplicant.a ****************************************************************************/ @@ -4593,10 +4842,22 @@ esp_err_t esp_wifi_init(const wifi_init_config_t *config) { esp_err_t ret; +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + ret = coex_init(); + if (ret) + { + wlerr("ERROR: Failed to initialize coex error=%d\n", ret); + return ret; + } +#endif + ret = esp_wifi_init_internal(config); if (ret) { wlerr("ERROR: Failed to initialize Wi-Fi error=%d\n", ret); +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_deinit(); +#endif return ret; } @@ -4605,9 +4866,32 @@ esp_err_t esp_wifi_init(const wifi_init_config_t *config) { wlerr("ERROR: Failed to initialize WPA supplicant error=%d\n", ret); esp_wifi_deinit_internal(); +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + coex_deinit(); +#endif return ret; } +#ifdef CONFIG_PM + ret = esp32c3_pm_register_skip_sleep_callback( + esp_wifi_internal_is_tsf_active); + if (ret != OK) + { + wlerr("ERROR: Failed to register skip sleep callback (0x%x)", ret); + return ret; + } + + ret = esp32c3_pm_register_inform_out_sleep_overhead_callback( + esp_wifi_internal_update_light_sleep_wake_ahead_time); + if (ret != OK) + { + wlerr("ERROR: Failed to register overhead callback (0x%x)", ret); + return ret; + } + + esp32c3_sleep_enable_wifi_wakeup(); +#endif + return 0; } @@ -4643,6 +4927,12 @@ esp_err_t esp_wifi_deinit(void) return ret; } +#ifdef CONFIG_PM + esp32c3_pm_unregister_skip_sleep_callback( + esp_wifi_internal_is_tsf_active); + esp32c3_pm_unregister_inform_out_sleep_overhead_callback( + esp_wifi_internal_update_light_sleep_wake_ahead_time); +#endif return ret; } @@ -4785,13 +5075,6 @@ int esp_wifi_adapter_init(void) return OK; } - ret = esp32c3_rt_timer_init(); - if (ret < 0) - { - wlerr("ERROR: Failed to initialize RT timer error=%d\n", ret); - goto errout_init_timer; - } - sq_init(&g_wifi_evt_queue); #ifdef CONFIG_ESP32C3_WIFI_SAVE_PARAM @@ -4859,8 +5142,6 @@ int esp_wifi_adapter_init(void) errout_init_txdone: esp_wifi_deinit(); errout_init_wifi: - esp32c3_rt_timer_deinit(); -errout_init_timer: esp_wifi_lock(false); return ret; } @@ -5134,9 +5415,11 @@ int esp_wifi_sta_password(struct iwreq *iwr, bool set) return -EINVAL; } + memset(wifi_cfg.sta.password, 0x0, PWD_MAX_LEN); memcpy(wifi_cfg.sta.password, pdata, len); wifi_cfg.sta.pmf_cfg.capable = true; + wifi_cfg.sta.listen_interval = DEFAULT_LISTEN_INTERVAL; ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); if (ret) @@ -5259,6 +5542,7 @@ int esp_wifi_sta_essid(struct iwreq *iwr, bool set) if (set) { + memset(wifi_cfg.sta.ssid, 0x0, SSID_MAX_LEN); memcpy(wifi_cfg.sta.ssid, pdata, len); ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); @@ -5337,7 +5621,7 @@ int esp_wifi_sta_bssid(struct iwreq *iwr, bool set) if (set) { wifi_cfg.sta.bssid_set = true; - memcpy(wifi_cfg.sta.bssid, pdata, 6); + memcpy(wifi_cfg.sta.bssid, pdata, MAC_LEN); ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); if (ret) @@ -5348,7 +5632,7 @@ int esp_wifi_sta_bssid(struct iwreq *iwr, bool set) } else { - memcpy(pdata, wifi_cfg.sta.bssid, 6); + memcpy(pdata, wifi_cfg.sta.bssid, MAC_LEN); } return OK; @@ -6215,8 +6499,8 @@ int esp_wifi_softap_password(struct iwreq *iwr, bool set) if (set) { wifi_cfg.ap.max_connection = ESP_MAX_STA_CONN; + memset(wifi_cfg.ap.password, 0x0, PWD_MAX_LEN); memcpy(wifi_cfg.ap.password, pdata, len); - wifi_cfg.ap.password[len] = '\0'; if (len) { wifi_cfg.ap.authmode = WIFI_AUTH_WPA_WPA2_PSK; @@ -6300,6 +6584,7 @@ int esp_wifi_softap_essid(struct iwreq *iwr, bool set) if (set) { + memset(wifi_cfg.ap.ssid, 0x0, SSID_MAX_LEN); memcpy(wifi_cfg.ap.ssid, pdata, len); ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); @@ -6693,3 +6978,28 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set) return -ENOSYS; } #endif + +/**************************************************************************** + * Name: esp32c3_wifi_bt_coexist_init + * + * Description: + * Initialize ESP32-C3 Wi-Fi and BT coexistance module. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST +int esp32c3_wifi_bt_coexist_init(void) +{ + esp_coex_adapter_register(&g_coex_adapter_funcs); + coex_pre_init(); + + return 0; +} +#endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h b/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h index 237c249229d..0e9e8408c4f 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h +++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h @@ -62,6 +62,7 @@ extern "C" #define SSID_MAX_LEN (32) #define PWD_MAX_LEN (64) +#define MAC_LEN (6) /* Wi-Fi event ID */ @@ -816,6 +817,25 @@ int esp_wifi_softap_country(struct iwreq *iwr, bool set); int esp_wifi_softap_rssi(struct iwreq *iwr, bool set); #endif +/**************************************************************************** + * Name: esp32c3_wifi_bt_coexist_init + * + * Description: + * Initialize ESP32-C3 Wi-Fi and BT coexistance module. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST +int esp32c3_wifi_bt_coexist_init(void); +#endif + #ifdef __cplusplus } #endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c index 5fd5c31acb1..4636045345b 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c +++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c @@ -24,6 +24,9 @@ #include +#include +#include + #include #include #include @@ -53,6 +56,10 @@ # define MIN(a,b) ((a) < (b) ? (a) : (b)) #endif +/* Maximum number of channels for Wi-Fi 2.4Ghz */ + +#define CHANNEL_MAX_NUM (14) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -79,6 +86,8 @@ struct wifi_scan_result_s ****************************************************************************/ static struct wifi_scan_result_s g_scan_priv; +static uint8_t g_channel_num = 0; +static uint8_t g_channel_list[CHANNEL_MAX_NUM]; /**************************************************************************** * Public Functions @@ -105,6 +114,8 @@ int esp_wifi_start_scan(struct iwreq *iwr) wifi_scan_config_t *config = NULL; struct iw_scan_req *req; int ret = 0; + int i; + uint8_t target_mac[MAC_LEN]; uint8_t target_ssid[SSID_MAX_LEN + 1] = { 0 @@ -128,6 +139,9 @@ int esp_wifi_start_scan(struct iwreq *iwr) return -ENOMEM; } + g_channel_num = 0; + memset(g_channel_list, 0x0, CHANNEL_MAX_NUM); + if (iwr->u.data.pointer && iwr->u.data.length >= sizeof(struct iw_scan_req)) { @@ -143,6 +157,35 @@ int esp_wifi_start_scan(struct iwreq *iwr) config->ssid = &target_ssid[0]; config->ssid[req->essid_len] = '\0'; } + + if (iwr->u.data.flags & IW_SCAN_THIS_FREQ && + req->num_channels > 0) + { + /* Scan specific channels */ + + DEBUGASSERT(req->num_channels <= CHANNEL_MAX_NUM); + g_channel_num = req->num_channels; + if (req->num_channels == 1) + { + config->channel = req->channel_list[0].m; + } + else + { + for (i = 0; i < req->num_channels; i++) + { + g_channel_list[i] = req->channel_list[i].m; + } + } + } + + memset(target_mac, 0xff, MAC_LEN); + if (memcmp(req->bssid.sa_data, target_mac, MAC_LEN) != 0) + { + /* Scan specific bssid */ + + memcpy(target_mac, req->bssid.sa_data, MAC_LEN); + config->bssid = &target_mac[0]; + } } else { @@ -319,6 +362,7 @@ void esp_wifi_scan_event_parse(void) esp_wifi_scan_get_ap_num(&bss_total); if (bss_total == 0) { + priv->scan_status = ESP_SCAN_DONE; wlinfo("INFO: None AP is scanned\n"); return; } @@ -326,6 +370,7 @@ void esp_wifi_scan_event_parse(void) ap_list_buffer = kmm_calloc(bss_total, sizeof(wifi_ap_record_t)); if (ap_list_buffer == NULL) { + priv->scan_status = ESP_SCAN_DONE; wlerr("ERROR: Failed to calloc buffer to print scan results"); return; } @@ -337,127 +382,153 @@ void esp_wifi_scan_event_parse(void) unsigned int result_size; size_t essid_len; size_t essid_len_aligned; + bool is_target_channel = true; + int i; + for (bss_count = 0; bss_count < bss_total; bss_count++) { - result_size = WIFI_SCAN_RESULT_SIZE - priv->scan_result_size; - - /* Copy BSSID */ - - if (result_size < ESP_IW_EVENT_SIZE(ap_addr)) + if (g_channel_num > 1) { - goto scan_result_full; + is_target_channel = false; + for (i = 0; i < g_channel_num; i++) + { + if (g_channel_list[i] == ap_list_buffer[bss_count].primary) + { + is_target_channel = true; + break; + } + } + } + else + { + is_target_channel = true; } - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(ap_addr); - iwe->cmd = SIOCGIWAP; - memcpy(&iwe->u.ap_addr.sa_data, ap_list_buffer[bss_count].bssid, - sizeof(ap_list_buffer[bss_count].bssid)); - iwe->u.ap_addr.sa_family = ARPHRD_ETHER; - priv->scan_result_size += ESP_IW_EVENT_SIZE(ap_addr); - result_size -= ESP_IW_EVENT_SIZE(ap_addr); - - /* Copy ESSID */ - - essid_len = MIN(strlen((const char *) - ap_list_buffer[bss_count].ssid), SSID_MAX_LEN); - essid_len_aligned = (essid_len + 3) & -4; - if (result_size < ESP_IW_EVENT_SIZE(essid) + essid_len_aligned) + if (is_target_channel == true) { - goto scan_result_full; + result_size = WIFI_SCAN_RESULT_SIZE - priv->scan_result_size; + + /* Copy BSSID */ + + if (result_size < ESP_IW_EVENT_SIZE(ap_addr)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(ap_addr); + iwe->cmd = SIOCGIWAP; + memcpy(&iwe->u.ap_addr.sa_data, + ap_list_buffer[bss_count].bssid, + sizeof(ap_list_buffer[bss_count].bssid)); + iwe->u.ap_addr.sa_family = ARPHRD_ETHER; + priv->scan_result_size += ESP_IW_EVENT_SIZE(ap_addr); + result_size -= ESP_IW_EVENT_SIZE(ap_addr); + + /* Copy ESSID */ + + essid_len = MIN(strlen((const char *) + ap_list_buffer[bss_count].ssid), SSID_MAX_LEN); + essid_len_aligned = (essid_len + 3) & -4; + if (result_size < ESP_IW_EVENT_SIZE(essid) + essid_len_aligned) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; + iwe->cmd = SIOCGIWESSID; + iwe->u.essid.flags = 0; + iwe->u.essid.length = essid_len; + + /* Special processing for iw_point, set offset + * in pointer field. + */ + + iwe->u.essid.pointer = (FAR void *)sizeof(iwe->u.essid); + memcpy(&iwe->u.essid + 1, + ap_list_buffer[bss_count].ssid, essid_len); + + wlinfo("INFO: ssid %s\n", ap_list_buffer[bss_count].ssid); + + priv->scan_result_size += + ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; + result_size -= ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; + + /* Copy link quality info */ + + if (result_size < ESP_IW_EVENT_SIZE(qual)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(qual); + iwe->cmd = IWEVQUAL; + iwe->u.qual.qual = 0x00; + + wlinfo("INFO: signal %d\n", ap_list_buffer[bss_count].rssi); + + iwe->u.qual.level = ap_list_buffer[bss_count].rssi; + iwe->u.qual.noise = 0x00; + iwe->u.qual.updated = IW_QUAL_DBM | IW_QUAL_ALL_UPDATED; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(qual); + result_size -= ESP_IW_EVENT_SIZE(qual); + + /* Copy AP mode */ + + if (result_size < ESP_IW_EVENT_SIZE(mode)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(mode); + iwe->cmd = SIOCGIWMODE; + iwe->u.mode = IW_MODE_MASTER; + priv->scan_result_size += ESP_IW_EVENT_SIZE(mode); + result_size -= ESP_IW_EVENT_SIZE(mode); + + /* Copy AP encryption mode */ + + if (result_size < ESP_IW_EVENT_SIZE(data)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(data); + iwe->cmd = SIOCGIWENCODE; + iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + iwe->u.data.length = 0; + iwe->u.essid.pointer = NULL; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(data); + result_size -= ESP_IW_EVENT_SIZE(data); + + /* Copy AP channel */ + + if (result_size < ESP_IW_EVENT_SIZE(freq)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(freq); + iwe->cmd = SIOCGIWFREQ; + iwe->u.freq.e = 0; + iwe->u.freq.m = ap_list_buffer[bss_count].primary; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(freq); + result_size -= ESP_IW_EVENT_SIZE(freq); } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; - iwe->cmd = SIOCGIWESSID; - iwe->u.essid.flags = 0; - iwe->u.essid.length = essid_len; - - /* Special processing for iw_point, set offset in pointer field */ - - iwe->u.essid.pointer = (FAR void *)sizeof(iwe->u.essid); - memcpy(&iwe->u.essid + 1, - ap_list_buffer[bss_count].ssid, essid_len); - - wlinfo("INFO: ssid %s\n", ap_list_buffer[bss_count].ssid); - - priv->scan_result_size += - ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; - result_size -= ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; - - /* Copy link quality info */ - - if (result_size < ESP_IW_EVENT_SIZE(qual)) - { - goto scan_result_full; - } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(qual); - iwe->cmd = IWEVQUAL; - iwe->u.qual.qual = 0x00; - - wlinfo("INFO: signal %d\n", ap_list_buffer[bss_count].rssi); - - iwe->u.qual.level = ap_list_buffer[bss_count].rssi; - iwe->u.qual.noise = 0x00; - iwe->u.qual.updated = IW_QUAL_DBM | IW_QUAL_ALL_UPDATED; - - priv->scan_result_size += ESP_IW_EVENT_SIZE(qual); - result_size -= ESP_IW_EVENT_SIZE(qual); - - /* Copy AP mode */ - - if (result_size < ESP_IW_EVENT_SIZE(mode)) - { - goto scan_result_full; - } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(mode); - iwe->cmd = SIOCGIWMODE; - iwe->u.mode = IW_MODE_MASTER; - priv->scan_result_size += ESP_IW_EVENT_SIZE(mode); - result_size -= ESP_IW_EVENT_SIZE(mode); - - /* Copy AP encryption mode */ - - if (result_size < ESP_IW_EVENT_SIZE(data)) - { - goto scan_result_full; - } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(data); - iwe->cmd = SIOCGIWENCODE; - iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; - iwe->u.data.length = 0; - iwe->u.essid.pointer = NULL; - - priv->scan_result_size += ESP_IW_EVENT_SIZE(data); - result_size -= ESP_IW_EVENT_SIZE(data); - - /* Copy AP channel */ - - if (result_size < ESP_IW_EVENT_SIZE(freq)) - { - goto scan_result_full; - } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(freq); - iwe->cmd = SIOCGIWFREQ; - iwe->u.freq.e = 0; - iwe->u.freq.m = ap_list_buffer[bss_count].primary; - - priv->scan_result_size += ESP_IW_EVENT_SIZE(freq); - result_size -= ESP_IW_EVENT_SIZE(freq); } parse_done = true; @@ -478,7 +549,7 @@ scan_result_full: ap_list_buffer = NULL; } - g_scan_priv.scan_status = ESP_SCAN_DONE; + priv->scan_status = ESP_SCAN_DONE; nxsem_post(&priv->scan_signal); } diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h index bfce2ac63e7..8408aeeb201 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h +++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h @@ -117,4 +117,4 @@ int esp_wifi_scan_init(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_UTILS_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_UTILS_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wlan.c b/arch/risc-v/src/esp32c3/esp32c3_wlan.c index 295d0df4baf..d71221ddca0 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wlan.c +++ b/arch/risc-v/src/esp32c3/esp32c3_wlan.c @@ -24,9 +24,10 @@ #include -#ifdef CONFIG_ESP32C3_WIRELESS +#ifdef CONFIG_ESP32C3_WIFI #include +#include #include #include #include @@ -92,8 +93,6 @@ # endif #endif -#define MAC_LEN (6) - /**************************************************************************** * Private Types ****************************************************************************/ @@ -266,11 +265,6 @@ static int wlan_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg); #endif -#ifdef ESP32C3_WLAN_HAS_STA -static int wlan_sta_set_linkstatus(FAR struct net_driver_s *dev, - bool linkstatus); -#endif - #ifdef CONFIG_NET_ICMPv6 static void wlan_ipv6multicast(FAR struct wlan_priv_s *priv); #endif @@ -1537,15 +1531,6 @@ static int wlan_ioctl(FAR struct net_driver_s *dev, nerr("ERROR: Failed to connect\n"); break; } - -#ifdef ESP32C3_WLAN_HAS_STA - ret = wlan_sta_set_linkstatus(dev, true); - if (ret < 0) - { - nerr("ERROR: Failed to set linkstatus\n"); - break; - } -#endif } } else @@ -1556,15 +1541,6 @@ static int wlan_ioctl(FAR struct net_driver_s *dev, nerr("ERROR: Failed to disconnect\n"); break; } - -#ifdef ESP32C3_WLAN_HAS_STA - ret = wlan_sta_set_linkstatus(dev, false); - if (ret < 0) - { - nerr("ERROR: Failed to set linkstatus\n"); - break; - } -#endif } break; @@ -1591,15 +1567,6 @@ static int wlan_ioctl(FAR struct net_driver_s *dev, nerr("ERROR: Failed to connect\n"); break; } - -#ifdef ESP32C3_WLAN_HAS_STA - ret = wlan_sta_set_linkstatus(dev, true); - if (ret < 0) - { - nerr("ERROR: Failed to set linkstatus\n"); - break; - } -#endif } else { @@ -1609,15 +1576,6 @@ static int wlan_ioctl(FAR struct net_driver_s *dev, nerr("ERROR: Failed to disconnect\n"); break; } - -#ifdef ESP32C3_WLAN_HAS_STA - ret = wlan_sta_set_linkstatus(dev, false); - if (ret < 0) - { - nerr("ERROR: Failed to set linkstatus\n"); - break; - } -#endif } break; @@ -1815,40 +1773,6 @@ static void wlan_sta_tx_done(uint8_t *data, uint16_t *len, bool status) wlan_tx_done(priv); } -/**************************************************************************** - * Name: wlan_sta_set_linkstatus - * - * Description: - * Set Wi-Fi station link status - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * 0:Success; negated errno on failure - * - ****************************************************************************/ - -static int wlan_sta_set_linkstatus(FAR struct net_driver_s *dev, - bool linkstatus) -{ - if (dev) - { - if (linkstatus == true) - { - dev->d_flags |= IFF_RUNNING; - } - else - { - dev->d_flags &= ~IFF_RUNNING; - } - - return OK; - } - - return -EINVAL; -} - #endif /**************************************************************************** @@ -1906,6 +1830,48 @@ static void wlan_softap_tx_done(uint8_t *data, uint16_t *len, bool status) * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp32c3_wlan_sta_set_linkstatus + * + * Description: + * Set Wi-Fi station link status + * + * Parameters: + * linkstatus - true Notifies the networking layer about an available + * carrier, false Notifies the networking layer about an + * disappeared carrier. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +#ifdef ESP32C3_WLAN_HAS_STA +int esp32c3_wlan_sta_set_linkstatus(bool linkstatus) +{ + int ret = -EINVAL; + FAR struct wlan_priv_s *priv = &g_wlan_priv[ESP32C3_WLAN_STA_DEVNO]; + + if (priv != NULL) + { + if (linkstatus == true) + { + ret = netdev_carrier_on(&priv->dev); + } + else + { + ret = netdev_carrier_off(&priv->dev); + } + + if (ret < 0) + { + nerr("ERROR: Failed to notify the networking layer\n"); + } + } + + return ret; +} + /**************************************************************************** * Name: esp32c3_wlan_sta_initialize * @@ -1920,7 +1886,6 @@ static void wlan_softap_tx_done(uint8_t *data, uint16_t *len, bool status) * ****************************************************************************/ -#ifdef ESP32C3_WLAN_HAS_STA int esp32c3_wlan_sta_initialize(void) { int ret; @@ -2027,4 +1992,4 @@ int esp32c3_wlan_softap_initialize(void) } #endif -#endif /* CONFIG_ESP32C3_WIRELESS */ +#endif /* CONFIG_ESP32C3_WIFI */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wlan.h b/arch/risc-v/src/esp32c3/esp32c3_wlan.h index 54cdf9ad064..029aff1b0e5 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wlan.h +++ b/arch/risc-v/src/esp32c3/esp32c3_wlan.h @@ -40,12 +40,32 @@ extern "C" #define EXTERN extern #endif -#ifdef CONFIG_ESP32C3_WIRELESS +#ifdef CONFIG_ESP32C3_WIFI /**************************************************************************** * Public Function Prototypes ****************************************************************************/ +#ifdef ESP32C3_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp32c3_wlan_sta_set_linkstatus + * + * Description: + * Set Wi-Fi station link status + * + * Parameters: + * linkstatus - true Notifies the networking layer about an available + * carrier, false Notifies the networking layer about an + * disappeared carrier. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_wlan_sta_set_linkstatus(bool linkstatus); + /**************************************************************************** * Name: esp32c3_wlan_sta_initialize * @@ -60,7 +80,6 @@ extern "C" * ****************************************************************************/ -#ifdef ESP32C3_WLAN_HAS_STA int esp32c3_wlan_sta_initialize(void); #endif @@ -82,7 +101,7 @@ int esp32c3_wlan_sta_initialize(void); int esp32c3_wlan_softap_initialize(void); #endif -#endif /* CONFIG_ESP32C3_WIRELESS */ +#endif /* CONFIG_ESP32C3_WIFI */ #ifdef __cplusplus } #endif diff --git a/arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h b/arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h new file mode 100644 index 00000000000..808a95761cf --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C) + +#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0x0AC) + +#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0) + +/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ + +#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_DC_MEM_FORCE_PU_S 4 + +/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ + +#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2 + +/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_AGC_MEM_FORCE_PU_S 0 + +/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ + +#define APB_CTRL_SRAM_POWER_UP 0x0000000F +#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S)) +#define APB_CTRL_SRAM_POWER_UP_V 0xF +#define APB_CTRL_SRAM_POWER_UP_S 2 + +/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ + +#define APB_CTRL_ROM_POWER_UP 0x00000003 +#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S)) +#define APB_CTRL_ROM_POWER_UP_V 0x3 +#define APB_CTRL_ROM_POWER_UP_S 0 + +/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ + +#define APB_CTRL_RETENTION_LINK_ADDR 0x07FFFFFF +#define APB_CTRL_RETENTION_LINK_ADDR_M ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S)) +#define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF +#define APB_CTRL_RETENTION_LINK_ADDR_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/bb_reg.h b/arch/risc-v/src/esp32c3/hardware/bb_reg.h new file mode 100644 index 00000000000..262814eeeb6 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/bb_reg.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/bb_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some of the baseband control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) +#define BB_FFT_FORCE_PU (BIT(3)) +#define BB_FFT_FORCE_PU_M (BIT(3)) +#define BB_FFT_FORCE_PU_V 1 +#define BB_FFT_FORCE_PU_S 3 + +#define BB_DC_EST_FORCE_PU (BIT(1)) +#define BB_DC_EST_FORCE_PU_M (BIT(1)) +#define BB_DC_EST_FORCE_PU_V 1 +#define BB_DC_EST_FORCE_PU_S 1 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_aes.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_aes.h new file mode 100644 index 00000000000..ee1034b9150 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_aes.h @@ -0,0 +1,780 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_AES_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_AES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AES_KEY_0_REG register + * AES key register 0 + */ + +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) + +/* AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_0 0xFFFFFFFF +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFF +#define AES_KEY_0_S 0 + +/* AES_KEY_1_REG register + * AES key register 1 + */ + +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) + +/* AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_1 0xFFFFFFFF +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFF +#define AES_KEY_1_S 0 + +/* AES_KEY_2_REG register + * AES key register 2 + */ + +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) + +/* AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_2 0xFFFFFFFF +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFF +#define AES_KEY_2_S 0 + +/* AES_KEY_3_REG register + * AES key register 3 + */ + +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) + +/* AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_3 0xFFFFFFFF +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFF +#define AES_KEY_3_S 0 + +/* AES_KEY_4_REG register + * AES key register 4 + */ + +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) + +/* AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_4 0xFFFFFFFF +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFF +#define AES_KEY_4_S 0 + +/* AES_KEY_5_REG register + * AES key register 5 + */ + +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) + +/* AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_5 0xFFFFFFFF +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFF +#define AES_KEY_5_S 0 + +/* AES_KEY_6_REG register + * AES key register 6 + */ + +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) + +/* AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_6 0xFFFFFFFF +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFF +#define AES_KEY_6_S 0 + +/* AES_KEY_7_REG register + * AES key register 7 + */ + +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) + +/* AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_7 0xFFFFFFFF +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFF +#define AES_KEY_7_S 0 + +/* AES_TEXT_IN_0_REG register + * Source data register 0 + */ + +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) + +/* AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_0 0xFFFFFFFF +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFF +#define AES_TEXT_IN_0_S 0 + +/* AES_TEXT_IN_1_REG register + * Source data register 1 + */ + +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) + +/* AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_1 0xFFFFFFFF +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFF +#define AES_TEXT_IN_1_S 0 + +/* AES_TEXT_IN_2_REG register + * Source data register 2 + */ + +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) + +/* AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_2 0xFFFFFFFF +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFF +#define AES_TEXT_IN_2_S 0 + +/* AES_TEXT_IN_3_REG register + * Source data register 3 + */ + +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) + +/* AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_3 0xFFFFFFFF +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFF +#define AES_TEXT_IN_3_S 0 + +/* AES_TEXT_OUT_0_REG register + * Result data register 0 + */ + +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) + +/* AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_0 0xFFFFFFFF +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFF +#define AES_TEXT_OUT_0_S 0 + +/* AES_TEXT_OUT_1_REG register + * Result data register 1 + */ + +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) + +/* AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_1 0xFFFFFFFF +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFF +#define AES_TEXT_OUT_1_S 0 + +/* AES_TEXT_OUT_2_REG register + * Result data register 2 + */ + +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) + +/* AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_2 0xFFFFFFFF +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFF +#define AES_TEXT_OUT_2_S 0 + +/* AES_TEXT_OUT_3_REG register + * Result data register 3 + */ + +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) + +/* AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_3 0xFFFFFFFF +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFF +#define AES_TEXT_OUT_3_S 0 + +/* AES_MODE_REG register + * AES working mode configuration register + */ + +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) + +/* AES_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * Typical AES working mode. + * & + * 0x0(AES_EN_128): AES-EN-128 # + * 0x1(AES_EN_192): AES-EN-192 # + * 0x2(AES_EN_256): AES-EN-256 # + * 0x4(AES_DE_128): AES-DE-128 # + * 0x5(AES_DE_192): AES-DE-192 # + * 0x6(AES_DE_256): AES-DE-256 + * & + */ + +#define AES_MODE 0x00000007 +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007 +#define AES_MODE_S 0 + +/* AES_ENDIAN_REG register + * Endian configuration register + */ + +#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) + +/* AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; + * Defines the endianness of input and output texts. + * & + * [1:0] key endian # + * [3:2] text_in endian or in_stream endian # + * [5:4] text_out endian or out_stream endian # + * & + */ + +#define AES_ENDIAN 0x0000003F +#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) +#define AES_ENDIAN_V 0x0000003F +#define AES_ENDIAN_S 0 + +/* AES_TRIGGER_REG register + * Operation start controlling register + */ + +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) + +/* AES_TRIGGER : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start AES operation. + */ + +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001 +#define AES_TRIGGER_S 0 + +/* AES_STATE_REG register + * Operation status register + */ + +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) + +/* AES_STATE : RO; bitpos: [1:0]; default: 0; + * Stores the working status of the AES Accelerator. For details, see Table + * 3 for Typical AES working mode and Table 9 for DMA AES working mode. + * For typical AES; 0 = idle; 1 = busy. + * For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. + */ + +#define AES_STATE 0x00000003 +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003 +#define AES_STATE_S 0 + +/* AES_IV_0_REG register + * initialization vector + */ + +#define AES_IV_0_REG (DR_REG_AES_BASE + 0x50) + +/* AES_IV_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_0 0xFFFFFFFF +#define AES_IV_0_M (AES_IV_0_V << AES_IV_0_S) +#define AES_IV_0_V 0xFFFFFFFF +#define AES_IV_0_S 0 + +/* AES_IV_1_REG register + * initialization vector + */ + +#define AES_IV_1_REG (DR_REG_AES_BASE + 0x54) + +/* AES_IV_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_1 0xFFFFFFFF +#define AES_IV_1_M (AES_IV_1_V << AES_IV_1_S) +#define AES_IV_1_V 0xFFFFFFFF +#define AES_IV_1_S 0 + +/* AES_IV_2_REG register + * initialization vector + */ + +#define AES_IV_2_REG (DR_REG_AES_BASE + 0x58) + +/* AES_IV_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_2 0xFFFFFFFF +#define AES_IV_2_M (AES_IV_2_V << AES_IV_2_S) +#define AES_IV_2_V 0xFFFFFFFF +#define AES_IV_2_S 0 + +/* AES_IV_3_REG register + * initialization vector + */ + +#define AES_IV_3_REG (DR_REG_AES_BASE + 0x5c) + +/* AES_IV_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_3 0xFFFFFFFF +#define AES_IV_3_M (AES_IV_3_V << AES_IV_3_S) +#define AES_IV_3_V 0xFFFFFFFF +#define AES_IV_3_S 0 + +/* AES_H_0_REG register + * GCM hash subkey + */ + +#define AES_H_0_REG (DR_REG_AES_BASE + 0x60) + +/* AES_H_0 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_0 0xFFFFFFFF +#define AES_H_0_M (AES_H_0_V << AES_H_0_S) +#define AES_H_0_V 0xFFFFFFFF +#define AES_H_0_S 0 + +/* AES_H_1_REG register + * GCM hash subkey + */ + +#define AES_H_1_REG (DR_REG_AES_BASE + 0x64) + +/* AES_H_1 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_1 0xFFFFFFFF +#define AES_H_1_M (AES_H_1_V << AES_H_1_S) +#define AES_H_1_V 0xFFFFFFFF +#define AES_H_1_S 0 + +/* AES_H_2_REG register + * GCM hash subkey + */ + +#define AES_H_2_REG (DR_REG_AES_BASE + 0x68) + +/* AES_H_2 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_2 0xFFFFFFFF +#define AES_H_2_M (AES_H_2_V << AES_H_2_S) +#define AES_H_2_V 0xFFFFFFFF +#define AES_H_2_S 0 + +/* AES_H_3_REG register + * GCM hash subkey + */ + +#define AES_H_3_REG (DR_REG_AES_BASE + 0x6c) + +/* AES_H_3 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_3 0xFFFFFFFF +#define AES_H_3_M (AES_H_3_V << AES_H_3_S) +#define AES_H_3_V 0xFFFFFFFF +#define AES_H_3_S 0 + +/* AES_J0_0_REG register + * J0 + */ + +#define AES_J0_0_REG (DR_REG_AES_BASE + 0x70) + +/* AES_J0_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_0 0xFFFFFFFF +#define AES_J0_0_M (AES_J0_0_V << AES_J0_0_S) +#define AES_J0_0_V 0xFFFFFFFF +#define AES_J0_0_S 0 + +/* AES_J0_1_REG register + * J0 + */ + +#define AES_J0_1_REG (DR_REG_AES_BASE + 0x74) + +/* AES_J0_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_1 0xFFFFFFFF +#define AES_J0_1_M (AES_J0_1_V << AES_J0_1_S) +#define AES_J0_1_V 0xFFFFFFFF +#define AES_J0_1_S 0 + +/* AES_J0_2_REG register + * J0 + */ + +#define AES_J0_2_REG (DR_REG_AES_BASE + 0x78) + +/* AES_J0_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_2 0xFFFFFFFF +#define AES_J0_2_M (AES_J0_2_V << AES_J0_2_S) +#define AES_J0_2_V 0xFFFFFFFF +#define AES_J0_2_S 0 + +/* AES_J0_3_REG register + * J0 + */ + +#define AES_J0_3_REG (DR_REG_AES_BASE + 0x7c) + +/* AES_J0_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_3 0xFFFFFFFF +#define AES_J0_3_M (AES_J0_3_V << AES_J0_3_S) +#define AES_J0_3_V 0xFFFFFFFF +#define AES_J0_3_S 0 + +/* AES_T0_0_REG register + * T0 + */ + +#define AES_T0_0_REG (DR_REG_AES_BASE + 0x80) + +/* AES_T0_0 : RO; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_0 0xFFFFFFFF +#define AES_T0_0_M (AES_T0_0_V << AES_T0_0_S) +#define AES_T0_0_V 0xFFFFFFFF +#define AES_T0_0_S 0 + +/* AES_T0_1_REG register + * T0 + */ + +#define AES_T0_1_REG (DR_REG_AES_BASE + 0x84) + +/* AES_T0_1 : RO; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_1 0xFFFFFFFF +#define AES_T0_1_M (AES_T0_1_V << AES_T0_1_S) +#define AES_T0_1_V 0xFFFFFFFF +#define AES_T0_1_S 0 + +/* AES_T0_2_REG register + * T0 + */ + +#define AES_T0_2_REG (DR_REG_AES_BASE + 0x88) + +/* AES_T0_2 : RO; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_2 0xFFFFFFFF +#define AES_T0_2_M (AES_T0_2_V << AES_T0_2_S) +#define AES_T0_2_V 0xFFFFFFFF +#define AES_T0_2_S 0 + +/* AES_T0_3_REG register + * T0 + */ + +#define AES_T0_3_REG (DR_REG_AES_BASE + 0x8c) + +/* AES_T0_3 : RO; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_3 0xFFFFFFFF +#define AES_T0_3_M (AES_T0_3_V << AES_T0_3_S) +#define AES_T0_3_V 0xFFFFFFFF +#define AES_T0_3_S 0 + +/* AES_DMA_ENABLE_REG register + * DMA enable register + */ + +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) + +/* AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * Defines the working mode of the AES Accelerator. For details, see Table 1. + * 1'h0: typical AES operation + * 1'h1: DMA-AES operation + */ + +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001 +#define AES_DMA_ENABLE_S 0 + +/* AES_BLOCK_MODE_REG register + * Block operation type register + */ + +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) + +/* AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * DMA-AES working mode. For details, see Table 8. + * & + * 3'h0(BLOCK_MODE_ECB): ECB # + * 3'h1(BLOCK_MODE_CBC): CBC # + * 3'h2(BLOCK_MODE_OFB): OFB # + * 3'h3(BLOCK_MODE_CTR): CTR # + * 3'h4(BLOCK_MODE_CFB8): CFB-8 # + * 3'h5(BLOCK_MODE_CFB128): CFB-128 # + * 3'h6(BLOCK_MODE_GCM): GCM + * & + */ + +#define AES_BLOCK_MODE 0x00000007 +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007 +#define AES_BLOCK_MODE_S 0 + +/* AES_BLOCK_NUM_REG register + * Block number configuration register + */ + +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) + +/* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the Block Number of plaintext or cipertext when the AES + * Accelerator operates under the DMA-AES working mode. For details, see + * Section 1.5.4. + */ + +#define AES_BLOCK_NUM 0xFFFFFFFF +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFF +#define AES_BLOCK_NUM_S 0 + +/* AES_INC_SEL_REG register + * Standard incrementing function register + */ + +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) + +/* AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * Defines the Standard Incrementing Function for CTR block operation. Set + * this bit to 0 or 1 to choose INC 32 or INC 128 . + */ + +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001 +#define AES_INC_SEL_S 0 + +/* AES_AAD_BLOCK_NUM_REG register + * AAD block number configuration register + */ + +#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) + +/* AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the ADD Block Number for the GCM operation. + */ + +#define AES_AAD_BLOCK_NUM 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) +#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_S 0 + +/* AES_REMAINDER_BIT_NUM_REG register + * Remainder bit number of plaintext/ciphertext + */ + +#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) + +/* AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; + * Stores the Remainder Bit Number for the GCM operation. + */ + +#define AES_REMAINDER_BIT_NUM 0x0000007F +#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) +#define AES_REMAINDER_BIT_NUM_V 0x0000007F +#define AES_REMAINDER_BIT_NUM_S 0 + +/* AES_CONTINUE_REG register + * Operation continue controlling register + */ + +#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) + +/* AES_CONTINUE : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to continue AES operation. + */ + +#define AES_CONTINUE (BIT(0)) +#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) +#define AES_CONTINUE_V 0x00000001 +#define AES_CONTINUE_S 0 + +/* AES_INT_CLR_REG register + * DMA-AES interrupt clear register + */ + +#define AES_INT_CLR_REG (DR_REG_AES_BASE + 0xac) + +/* AES_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear AES interrupt. + */ + +#define AES_INT_CLR (BIT(0)) +#define AES_INT_CLR_M (AES_INT_CLR_V << AES_INT_CLR_S) +#define AES_INT_CLR_V 0x00000001 +#define AES_INT_CLR_S 0 + +/* AES_INT_ENA_REG register + * DMA-AES interrupt enable register + */ + +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) + +/* AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. + */ + +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001 +#define AES_INT_ENA_S 0 + +/* AES_DATE_REG register + * Version control register + */ + +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) + +/* AES_DATE : R/W; bitpos: [29:0]; default: 538510612; + * Version control register + */ + +#define AES_DATE 0x3FFFFFFF +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFF +#define AES_DATE_S 0 + +/* AES_DMA_EXIT_REG register + * Operation exit controlling register + */ + +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) + +/* AES_DMA_EXIT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to exit AES operation. This register is only effective + * for DMA-AES operation. + */ + +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001 +#define AES_DMA_EXIT_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_AES_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h new file mode 100644 index 00000000000..78b5746d34f --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h @@ -0,0 +1,3898 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* DMA_INT_RAW_CH0_REG register + * DMA_INT_RAW_CH0_REG. + */ + +#define DMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) + +/* DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 0 is underflow. + */ + +#define DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_M (DMA_OUTFIFO_UDF_CH0_INT_RAW_V << DMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_S 12 + +/* DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 0 is overflow. + */ + +#define DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_M (DMA_OUTFIFO_OVF_CH0_INT_RAW_V << DMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_S 11 + +/* DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 0 is underflow. + */ + +#define DMA_INFIFO_UDF_CH0_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_RAW_M (DMA_INFIFO_UDF_CH0_INT_RAW_V << DMA_INFIFO_UDF_CH0_INT_RAW_S) +#define DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001 +#define DMA_INFIFO_UDF_CH0_INT_RAW_S 10 + +/* DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 0 is overflow. + */ + +#define DMA_INFIFO_OVF_CH0_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_RAW_M (DMA_INFIFO_OVF_CH0_INT_RAW_V << DMA_INFIFO_OVF_CH0_INT_RAW_S) +#define DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001 +#define DMA_INFIFO_OVF_CH0_INT_RAW_S 9 + +/* DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a + * outlink (includes one link descriptor or few link descriptors) is + * transmitted out for Tx channel 0. + */ + +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8 + +/* DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by + * inlink is full and receiving data is not completed, but there is no more + * inlink for Rx channel 0. + */ + +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7 + +/* DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink + * descriptor error, including owner error, the second and third word error + * of outlink descriptor for Tx channel 0. + */ + +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6 + +/* DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink + * descriptor error, including owner error, the second and third word error + * of inlink descriptor for Rx channel 0. + */ + +#define DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_M (DMA_IN_DSCR_ERR_CH0_INT_RAW_V << DMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_S 5 + +/* DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been read from memory for Tx channel 0. + */ + +#define DMA_OUT_EOF_CH0_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_RAW_M (DMA_OUT_EOF_CH0_INT_RAW_V << DMA_OUT_EOF_CH0_INT_RAW_S) +#define DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001 +#define DMA_OUT_EOF_CH0_INT_RAW_S 4 + +/* DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been transmitted to peripherals for Tx channel + * 0. + */ + +#define DMA_OUT_DONE_CH0_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_RAW_M (DMA_OUT_DONE_CH0_INT_RAW_V << DMA_OUT_DONE_CH0_INT_RAW_S) +#define DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001 +#define DMA_OUT_DONE_CH0_INT_RAW_S 3 + +/* DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected + * only in the case that the peripheral is UHCI0 for Rx channel 0. For other + * peripherals, this raw interrupt is reserved. + */ + +#define DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_RAW_M (DMA_IN_ERR_EOF_CH0_INT_RAW_V << DMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 + +/* DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 0. For UHCI0, the + * raw interrupt bit turns to high level when the last data pointed by one + * inlink descriptor has been received and no data error is detected for Rx + * channel 0. + */ + +#define DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_RAW_M (DMA_IN_SUC_EOF_CH0_INT_RAW_V << DMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 + +/* DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 0. + */ + +#define DMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH0_INT_RAW_M (DMA_IN_DONE_CH0_INT_RAW_V << DMA_IN_DONE_CH0_INT_RAW_S) +#define DMA_IN_DONE_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_DONE_CH0_INT_RAW_S 0 + +/* DMA_INT_ST_CH0_REG register + * DMA_INT_ST_CH0_REG. + */ + +#define DMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) + +/* DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_ST_M (DMA_OUTFIFO_UDF_CH0_INT_ST_V << DMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH0_INT_ST_S 12 + +/* DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_ST_M (DMA_OUTFIFO_OVF_CH0_INT_ST_V << DMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH0_INT_ST_S 11 + +/* DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH0_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_ST_M (DMA_INFIFO_UDF_CH0_INT_ST_V << DMA_INFIFO_UDF_CH0_INT_ST_S) +#define DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001 +#define DMA_INFIFO_UDF_CH0_INT_ST_S 10 + +/* DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH0_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_ST_M (DMA_INFIFO_OVF_CH0_INT_ST_V << DMA_INFIFO_OVF_CH0_INT_ST_S) +#define DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001 +#define DMA_INFIFO_OVF_CH0_INT_ST_S 9 + +/* DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8 + +/* DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7 + +/* DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_M (DMA_OUT_DSCR_ERR_CH0_INT_ST_V << DMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_S 6 + +/* DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ST_M (DMA_IN_DSCR_ERR_CH0_INT_ST_V << DMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH0_INT_ST_S 5 + +/* DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH0_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ST_M (DMA_OUT_EOF_CH0_INT_ST_V << DMA_OUT_EOF_CH0_INT_ST_S) +#define DMA_OUT_EOF_CH0_INT_ST_V 0x00000001 +#define DMA_OUT_EOF_CH0_INT_ST_S 4 + +/* DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH0_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ST_M (DMA_OUT_DONE_CH0_INT_ST_V << DMA_OUT_DONE_CH0_INT_ST_S) +#define DMA_OUT_DONE_CH0_INT_ST_V 0x00000001 +#define DMA_OUT_DONE_CH0_INT_ST_S 3 + +/* DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ST_M (DMA_IN_ERR_EOF_CH0_INT_ST_V << DMA_IN_ERR_EOF_CH0_INT_ST_S) +#define DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001 +#define DMA_IN_ERR_EOF_CH0_INT_ST_S 2 + +/* DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ST_M (DMA_IN_SUC_EOF_CH0_INT_ST_V << DMA_IN_SUC_EOF_CH0_INT_ST_S) +#define DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001 +#define DMA_IN_SUC_EOF_CH0_INT_ST_S 1 + +/* DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ST_M (DMA_IN_DONE_CH0_INT_ST_V << DMA_IN_DONE_CH0_INT_ST_S) +#define DMA_IN_DONE_CH0_INT_ST_V 0x00000001 +#define DMA_IN_DONE_CH0_INT_ST_S 0 + +/* DMA_INT_ENA_CH0_REG register + * DMA_INT_ENA_CH0_REG. + */ + +#define DMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) + +/* DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_M (DMA_OUTFIFO_UDF_CH0_INT_ENA_V << DMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_S 12 + +/* DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_M (DMA_OUTFIFO_OVF_CH0_INT_ENA_V << DMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_S 11 + +/* DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH0_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_ENA_M (DMA_INFIFO_UDF_CH0_INT_ENA_V << DMA_INFIFO_UDF_CH0_INT_ENA_S) +#define DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001 +#define DMA_INFIFO_UDF_CH0_INT_ENA_S 10 + +/* DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH0_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_ENA_M (DMA_INFIFO_OVF_CH0_INT_ENA_V << DMA_INFIFO_OVF_CH0_INT_ENA_S) +#define DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001 +#define DMA_INFIFO_OVF_CH0_INT_ENA_S 9 + +/* DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8 + +/* DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7 + +/* DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6 + +/* DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_M (DMA_IN_DSCR_ERR_CH0_INT_ENA_V << DMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_S 5 + +/* DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH0_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ENA_M (DMA_OUT_EOF_CH0_INT_ENA_V << DMA_OUT_EOF_CH0_INT_ENA_S) +#define DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001 +#define DMA_OUT_EOF_CH0_INT_ENA_S 4 + +/* DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH0_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ENA_M (DMA_OUT_DONE_CH0_INT_ENA_V << DMA_OUT_DONE_CH0_INT_ENA_S) +#define DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001 +#define DMA_OUT_DONE_CH0_INT_ENA_S 3 + +/* DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ENA_M (DMA_IN_ERR_EOF_CH0_INT_ENA_V << DMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 + +/* DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ENA_M (DMA_IN_SUC_EOF_CH0_INT_ENA_V << DMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 + +/* DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ENA_M (DMA_IN_DONE_CH0_INT_ENA_V << DMA_IN_DONE_CH0_INT_ENA_S) +#define DMA_IN_DONE_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_DONE_CH0_INT_ENA_S 0 + +/* DMA_INT_CLR_CH0_REG register + * DMA_INT_CLR_CH0_REG. + */ + +#define DMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) + +/* DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_M (DMA_OUTFIFO_UDF_CH0_INT_CLR_V << DMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_S 12 + +/* DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_M (DMA_OUTFIFO_OVF_CH0_INT_CLR_V << DMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_S 11 + +/* DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH0_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_CLR_M (DMA_INFIFO_UDF_CH0_INT_CLR_V << DMA_INFIFO_UDF_CH0_INT_CLR_S) +#define DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001 +#define DMA_INFIFO_UDF_CH0_INT_CLR_S 10 + +/* DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH0_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_CLR_M (DMA_INFIFO_OVF_CH0_INT_CLR_V << DMA_INFIFO_OVF_CH0_INT_CLR_S) +#define DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001 +#define DMA_INFIFO_OVF_CH0_INT_CLR_S 9 + +/* DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8 + +/* DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7 + +/* DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6 + +/* DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_M (DMA_IN_DSCR_ERR_CH0_INT_CLR_V << DMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_S 5 + +/* DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH0_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_CLR_M (DMA_OUT_EOF_CH0_INT_CLR_V << DMA_OUT_EOF_CH0_INT_CLR_S) +#define DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001 +#define DMA_OUT_EOF_CH0_INT_CLR_S 4 + +/* DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH0_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_CLR_M (DMA_OUT_DONE_CH0_INT_CLR_V << DMA_OUT_DONE_CH0_INT_CLR_S) +#define DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001 +#define DMA_OUT_DONE_CH0_INT_CLR_S 3 + +/* DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_CLR_M (DMA_IN_ERR_EOF_CH0_INT_CLR_V << DMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 + +/* DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_CLR_M (DMA_IN_SUC_EOF_CH0_INT_CLR_V << DMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 + +/* DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH0_INT_CLR_M (DMA_IN_DONE_CH0_INT_CLR_V << DMA_IN_DONE_CH0_INT_CLR_S) +#define DMA_IN_DONE_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_DONE_CH0_INT_CLR_S 0 + +/* DMA_INT_RAW_CH1_REG register + * DMA_INT_RAW_CH1_REG. + */ + +#define DMA_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) + +/* DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 1 is underflow. + */ + +#define DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_M (DMA_OUTFIFO_UDF_CH1_INT_RAW_V << DMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_S 12 + +/* DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 1 is overflow. + */ + +#define DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_M (DMA_OUTFIFO_OVF_CH1_INT_RAW_V << DMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_S 11 + +/* DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 1 is underflow. + */ + +#define DMA_INFIFO_UDF_CH1_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_RAW_M (DMA_INFIFO_UDF_CH1_INT_RAW_V << DMA_INFIFO_UDF_CH1_INT_RAW_S) +#define DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001 +#define DMA_INFIFO_UDF_CH1_INT_RAW_S 10 + +/* DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 1 is overflow. + */ + +#define DMA_INFIFO_OVF_CH1_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_RAW_M (DMA_INFIFO_OVF_CH1_INT_RAW_V << DMA_INFIFO_OVF_CH1_INT_RAW_S) +#define DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001 +#define DMA_INFIFO_OVF_CH1_INT_RAW_S 9 + +/* DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a + * outlink (includes one link descriptor or few link descriptors) is + * transmitted out for Tx channel 1. + */ + +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 8 + +/* DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by + * inlink is full and receiving data is not completed, but there is no more + * inlink for Rx channel 1. + */ + +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 7 + +/* DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink + * descriptor error, including owner error, the second and third word error + * of outlink descriptor for Tx channel 1. + */ + +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 6 + +/* DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink + * descriptor error, including owner error, the second and third word error + * of inlink descriptor for Rx channel 1. + */ + +#define DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_M (DMA_IN_DSCR_ERR_CH1_INT_RAW_V << DMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_S 5 + +/* DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been read from memory for Tx channel 1. + */ + +#define DMA_OUT_EOF_CH1_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_RAW_M (DMA_OUT_EOF_CH1_INT_RAW_V << DMA_OUT_EOF_CH1_INT_RAW_S) +#define DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001 +#define DMA_OUT_EOF_CH1_INT_RAW_S 4 + +/* DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been transmitted to peripherals for Tx channel + * 1. + */ + +#define DMA_OUT_DONE_CH1_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_RAW_M (DMA_OUT_DONE_CH1_INT_RAW_V << DMA_OUT_DONE_CH1_INT_RAW_S) +#define DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001 +#define DMA_OUT_DONE_CH1_INT_RAW_S 3 + +/* DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected + * only in the case that the peripheral is UHCI0 for Rx channel 1. For other + * peripherals, this raw interrupt is reserved. + */ + +#define DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_RAW_M (DMA_IN_ERR_EOF_CH1_INT_RAW_V << DMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 + +/* DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 1. For UHCI0, the + * raw interrupt bit turns to high level when the last data pointed by one + * inlink descriptor has been received and no data error is detected for Rx + * channel 1. + */ + +#define DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_RAW_M (DMA_IN_SUC_EOF_CH1_INT_RAW_V << DMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 + +/* DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 1. + */ + +#define DMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH1_INT_RAW_M (DMA_IN_DONE_CH1_INT_RAW_V << DMA_IN_DONE_CH1_INT_RAW_S) +#define DMA_IN_DONE_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_DONE_CH1_INT_RAW_S 0 + +/* DMA_INT_ST_CH1_REG register + * DMA_INT_ST_CH1_REG. + */ + +#define DMA_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) + +/* DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_ST_M (DMA_OUTFIFO_UDF_CH1_INT_ST_V << DMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH1_INT_ST_S 12 + +/* DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_ST_M (DMA_OUTFIFO_OVF_CH1_INT_ST_V << DMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH1_INT_ST_S 11 + +/* DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH1_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_ST_M (DMA_INFIFO_UDF_CH1_INT_ST_V << DMA_INFIFO_UDF_CH1_INT_ST_S) +#define DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001 +#define DMA_INFIFO_UDF_CH1_INT_ST_S 10 + +/* DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH1_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_ST_M (DMA_INFIFO_OVF_CH1_INT_ST_V << DMA_INFIFO_OVF_CH1_INT_ST_S) +#define DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001 +#define DMA_INFIFO_OVF_CH1_INT_ST_S 9 + +/* DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 8 + +/* DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 7 + +/* DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_M (DMA_OUT_DSCR_ERR_CH1_INT_ST_V << DMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_S 6 + +/* DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ST_M (DMA_IN_DSCR_ERR_CH1_INT_ST_V << DMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH1_INT_ST_S 5 + +/* DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH1_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ST_M (DMA_OUT_EOF_CH1_INT_ST_V << DMA_OUT_EOF_CH1_INT_ST_S) +#define DMA_OUT_EOF_CH1_INT_ST_V 0x00000001 +#define DMA_OUT_EOF_CH1_INT_ST_S 4 + +/* DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH1_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ST_M (DMA_OUT_DONE_CH1_INT_ST_V << DMA_OUT_DONE_CH1_INT_ST_S) +#define DMA_OUT_DONE_CH1_INT_ST_V 0x00000001 +#define DMA_OUT_DONE_CH1_INT_ST_S 3 + +/* DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ST_M (DMA_IN_ERR_EOF_CH1_INT_ST_V << DMA_IN_ERR_EOF_CH1_INT_ST_S) +#define DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001 +#define DMA_IN_ERR_EOF_CH1_INT_ST_S 2 + +/* DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ST_M (DMA_IN_SUC_EOF_CH1_INT_ST_V << DMA_IN_SUC_EOF_CH1_INT_ST_S) +#define DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001 +#define DMA_IN_SUC_EOF_CH1_INT_ST_S 1 + +/* DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ST_M (DMA_IN_DONE_CH1_INT_ST_V << DMA_IN_DONE_CH1_INT_ST_S) +#define DMA_IN_DONE_CH1_INT_ST_V 0x00000001 +#define DMA_IN_DONE_CH1_INT_ST_S 0 + +/* DMA_INT_ENA_CH1_REG register + * DMA_INT_ENA_CH1_REG. + */ + +#define DMA_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) + +/* DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_M (DMA_OUTFIFO_UDF_CH1_INT_ENA_V << DMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_S 12 + +/* DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_M (DMA_OUTFIFO_OVF_CH1_INT_ENA_V << DMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_S 11 + +/* DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH1_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_ENA_M (DMA_INFIFO_UDF_CH1_INT_ENA_V << DMA_INFIFO_UDF_CH1_INT_ENA_S) +#define DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001 +#define DMA_INFIFO_UDF_CH1_INT_ENA_S 10 + +/* DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH1_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_ENA_M (DMA_INFIFO_OVF_CH1_INT_ENA_V << DMA_INFIFO_OVF_CH1_INT_ENA_S) +#define DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001 +#define DMA_INFIFO_OVF_CH1_INT_ENA_S 9 + +/* DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 8 + +/* DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 7 + +/* DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 6 + +/* DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_M (DMA_IN_DSCR_ERR_CH1_INT_ENA_V << DMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_S 5 + +/* DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH1_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ENA_M (DMA_OUT_EOF_CH1_INT_ENA_V << DMA_OUT_EOF_CH1_INT_ENA_S) +#define DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001 +#define DMA_OUT_EOF_CH1_INT_ENA_S 4 + +/* DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH1_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ENA_M (DMA_OUT_DONE_CH1_INT_ENA_V << DMA_OUT_DONE_CH1_INT_ENA_S) +#define DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001 +#define DMA_OUT_DONE_CH1_INT_ENA_S 3 + +/* DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ENA_M (DMA_IN_ERR_EOF_CH1_INT_ENA_V << DMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 + +/* DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ENA_M (DMA_IN_SUC_EOF_CH1_INT_ENA_V << DMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 + +/* DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ENA_M (DMA_IN_DONE_CH1_INT_ENA_V << DMA_IN_DONE_CH1_INT_ENA_S) +#define DMA_IN_DONE_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_DONE_CH1_INT_ENA_S 0 + +/* DMA_INT_CLR_CH1_REG register + * DMA_INT_CLR_CH1_REG. + */ + +#define DMA_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) + +/* DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_M (DMA_OUTFIFO_UDF_CH1_INT_CLR_V << DMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_S 12 + +/* DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_M (DMA_OUTFIFO_OVF_CH1_INT_CLR_V << DMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_S 11 + +/* DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH1_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_CLR_M (DMA_INFIFO_UDF_CH1_INT_CLR_V << DMA_INFIFO_UDF_CH1_INT_CLR_S) +#define DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001 +#define DMA_INFIFO_UDF_CH1_INT_CLR_S 10 + +/* DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH1_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_CLR_M (DMA_INFIFO_OVF_CH1_INT_CLR_V << DMA_INFIFO_OVF_CH1_INT_CLR_S) +#define DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001 +#define DMA_INFIFO_OVF_CH1_INT_CLR_S 9 + +/* DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 8 + +/* DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 7 + +/* DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 6 + +/* DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_M (DMA_IN_DSCR_ERR_CH1_INT_CLR_V << DMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_S 5 + +/* DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH1_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_CLR_M (DMA_OUT_EOF_CH1_INT_CLR_V << DMA_OUT_EOF_CH1_INT_CLR_S) +#define DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001 +#define DMA_OUT_EOF_CH1_INT_CLR_S 4 + +/* DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH1_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_CLR_M (DMA_OUT_DONE_CH1_INT_CLR_V << DMA_OUT_DONE_CH1_INT_CLR_S) +#define DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001 +#define DMA_OUT_DONE_CH1_INT_CLR_S 3 + +/* DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_CLR_M (DMA_IN_ERR_EOF_CH1_INT_CLR_V << DMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 + +/* DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_CLR_M (DMA_IN_SUC_EOF_CH1_INT_CLR_V << DMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 + +/* DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH1_INT_CLR_M (DMA_IN_DONE_CH1_INT_CLR_V << DMA_IN_DONE_CH1_INT_CLR_S) +#define DMA_IN_DONE_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_DONE_CH1_INT_CLR_S 0 + +/* DMA_INT_RAW_CH2_REG register + * DMA_INT_RAW_CH2_REG. + */ + +#define DMA_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) + +/* DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 2 is underflow. + */ + +#define DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_M (DMA_OUTFIFO_UDF_CH2_INT_RAW_V << DMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_S 12 + +/* DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 2 is overflow. + */ + +#define DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_M (DMA_OUTFIFO_OVF_CH2_INT_RAW_V << DMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_S 11 + +/* DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 2 is underflow. + */ + +#define DMA_INFIFO_UDF_CH2_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_RAW_M (DMA_INFIFO_UDF_CH2_INT_RAW_V << DMA_INFIFO_UDF_CH2_INT_RAW_S) +#define DMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001 +#define DMA_INFIFO_UDF_CH2_INT_RAW_S 10 + +/* DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 2 is overflow. + */ + +#define DMA_INFIFO_OVF_CH2_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_RAW_M (DMA_INFIFO_OVF_CH2_INT_RAW_V << DMA_INFIFO_OVF_CH2_INT_RAW_S) +#define DMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001 +#define DMA_INFIFO_OVF_CH2_INT_RAW_S 9 + +/* DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a + * outlink (includes one link descriptor or few link descriptors) is + * transmitted out for Tx channel 2. + */ + +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 8 + +/* DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by + * inlink is full and receiving data is not completed, but there is no more + * inlink for Rx channel 2. + */ + +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 7 + +/* DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink + * descriptor error, including owner error, the second and third word error + * of outlink descriptor for Tx channel 2. + */ + +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 6 + +/* DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink + * descriptor error, including owner error, the second and third word error + * of inlink descriptor for Rx channel 2. + */ + +#define DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_M (DMA_IN_DSCR_ERR_CH2_INT_RAW_V << DMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_S 5 + +/* DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been read from memory for Tx channel 2. + */ + +#define DMA_OUT_EOF_CH2_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_RAW_M (DMA_OUT_EOF_CH2_INT_RAW_V << DMA_OUT_EOF_CH2_INT_RAW_S) +#define DMA_OUT_EOF_CH2_INT_RAW_V 0x00000001 +#define DMA_OUT_EOF_CH2_INT_RAW_S 4 + +/* DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been transmitted to peripherals for Tx channel + * 2. + */ + +#define DMA_OUT_DONE_CH2_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_RAW_M (DMA_OUT_DONE_CH2_INT_RAW_V << DMA_OUT_DONE_CH2_INT_RAW_S) +#define DMA_OUT_DONE_CH2_INT_RAW_V 0x00000001 +#define DMA_OUT_DONE_CH2_INT_RAW_S 3 + +/* DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected + * only in the case that the peripheral is UHCI0 for Rx channel 2. For other + * peripherals, this raw interrupt is reserved. + */ + +#define DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_RAW_M (DMA_IN_ERR_EOF_CH2_INT_RAW_V << DMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 + +/* DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 2. For UHCI0, the + * raw interrupt bit turns to high level when the last data pointed by one + * inlink descriptor has been received and no data error is detected for Rx + * channel 2. + */ + +#define DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_RAW_M (DMA_IN_SUC_EOF_CH2_INT_RAW_V << DMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 + +/* DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 2. + */ + +#define DMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH2_INT_RAW_M (DMA_IN_DONE_CH2_INT_RAW_V << DMA_IN_DONE_CH2_INT_RAW_S) +#define DMA_IN_DONE_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_DONE_CH2_INT_RAW_S 0 + +/* DMA_INT_ST_CH2_REG register + * DMA_INT_ST_CH2_REG. + */ + +#define DMA_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) + +/* DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_ST_M (DMA_OUTFIFO_UDF_CH2_INT_ST_V << DMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH2_INT_ST_S 12 + +/* DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_ST_M (DMA_OUTFIFO_OVF_CH2_INT_ST_V << DMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH2_INT_ST_S 11 + +/* DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH2_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_ST_M (DMA_INFIFO_UDF_CH2_INT_ST_V << DMA_INFIFO_UDF_CH2_INT_ST_S) +#define DMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001 +#define DMA_INFIFO_UDF_CH2_INT_ST_S 10 + +/* DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH2_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_ST_M (DMA_INFIFO_OVF_CH2_INT_ST_V << DMA_INFIFO_OVF_CH2_INT_ST_S) +#define DMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001 +#define DMA_INFIFO_OVF_CH2_INT_ST_S 9 + +/* DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 8 + +/* DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 7 + +/* DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_M (DMA_OUT_DSCR_ERR_CH2_INT_ST_V << DMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_S 6 + +/* DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ST_M (DMA_IN_DSCR_ERR_CH2_INT_ST_V << DMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH2_INT_ST_S 5 + +/* DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH2_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ST_M (DMA_OUT_EOF_CH2_INT_ST_V << DMA_OUT_EOF_CH2_INT_ST_S) +#define DMA_OUT_EOF_CH2_INT_ST_V 0x00000001 +#define DMA_OUT_EOF_CH2_INT_ST_S 4 + +/* DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH2_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ST_M (DMA_OUT_DONE_CH2_INT_ST_V << DMA_OUT_DONE_CH2_INT_ST_S) +#define DMA_OUT_DONE_CH2_INT_ST_V 0x00000001 +#define DMA_OUT_DONE_CH2_INT_ST_S 3 + +/* DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ST_M (DMA_IN_ERR_EOF_CH2_INT_ST_V << DMA_IN_ERR_EOF_CH2_INT_ST_S) +#define DMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001 +#define DMA_IN_ERR_EOF_CH2_INT_ST_S 2 + +/* DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ST_M (DMA_IN_SUC_EOF_CH2_INT_ST_V << DMA_IN_SUC_EOF_CH2_INT_ST_S) +#define DMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001 +#define DMA_IN_SUC_EOF_CH2_INT_ST_S 1 + +/* DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ST_M (DMA_IN_DONE_CH2_INT_ST_V << DMA_IN_DONE_CH2_INT_ST_S) +#define DMA_IN_DONE_CH2_INT_ST_V 0x00000001 +#define DMA_IN_DONE_CH2_INT_ST_S 0 + +/* DMA_INT_ENA_CH2_REG register + * DMA_INT_ENA_CH2_REG. + */ + +#define DMA_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) + +/* DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_M (DMA_OUTFIFO_UDF_CH2_INT_ENA_V << DMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_S 12 + +/* DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_M (DMA_OUTFIFO_OVF_CH2_INT_ENA_V << DMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_S 11 + +/* DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH2_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_ENA_M (DMA_INFIFO_UDF_CH2_INT_ENA_V << DMA_INFIFO_UDF_CH2_INT_ENA_S) +#define DMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001 +#define DMA_INFIFO_UDF_CH2_INT_ENA_S 10 + +/* DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH2_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_ENA_M (DMA_INFIFO_OVF_CH2_INT_ENA_V << DMA_INFIFO_OVF_CH2_INT_ENA_S) +#define DMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001 +#define DMA_INFIFO_OVF_CH2_INT_ENA_S 9 + +/* DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 8 + +/* DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 7 + +/* DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 6 + +/* DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_M (DMA_IN_DSCR_ERR_CH2_INT_ENA_V << DMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_S 5 + +/* DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH2_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ENA_M (DMA_OUT_EOF_CH2_INT_ENA_V << DMA_OUT_EOF_CH2_INT_ENA_S) +#define DMA_OUT_EOF_CH2_INT_ENA_V 0x00000001 +#define DMA_OUT_EOF_CH2_INT_ENA_S 4 + +/* DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH2_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ENA_M (DMA_OUT_DONE_CH2_INT_ENA_V << DMA_OUT_DONE_CH2_INT_ENA_S) +#define DMA_OUT_DONE_CH2_INT_ENA_V 0x00000001 +#define DMA_OUT_DONE_CH2_INT_ENA_S 3 + +/* DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ENA_M (DMA_IN_ERR_EOF_CH2_INT_ENA_V << DMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 + +/* DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ENA_M (DMA_IN_SUC_EOF_CH2_INT_ENA_V << DMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 + +/* DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ENA_M (DMA_IN_DONE_CH2_INT_ENA_V << DMA_IN_DONE_CH2_INT_ENA_S) +#define DMA_IN_DONE_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_DONE_CH2_INT_ENA_S 0 + +/* DMA_INT_CLR_CH2_REG register + * DMA_INT_CLR_CH2_REG. + */ + +#define DMA_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) + +/* DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_M (DMA_OUTFIFO_UDF_CH2_INT_CLR_V << DMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_S 12 + +/* DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_M (DMA_OUTFIFO_OVF_CH2_INT_CLR_V << DMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_S 11 + +/* DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH2_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_CLR_M (DMA_INFIFO_UDF_CH2_INT_CLR_V << DMA_INFIFO_UDF_CH2_INT_CLR_S) +#define DMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001 +#define DMA_INFIFO_UDF_CH2_INT_CLR_S 10 + +/* DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH2_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_CLR_M (DMA_INFIFO_OVF_CH2_INT_CLR_V << DMA_INFIFO_OVF_CH2_INT_CLR_S) +#define DMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001 +#define DMA_INFIFO_OVF_CH2_INT_CLR_S 9 + +/* DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 8 + +/* DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 7 + +/* DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 6 + +/* DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_M (DMA_IN_DSCR_ERR_CH2_INT_CLR_V << DMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_S 5 + +/* DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH2_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_CLR_M (DMA_OUT_EOF_CH2_INT_CLR_V << DMA_OUT_EOF_CH2_INT_CLR_S) +#define DMA_OUT_EOF_CH2_INT_CLR_V 0x00000001 +#define DMA_OUT_EOF_CH2_INT_CLR_S 4 + +/* DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH2_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_CLR_M (DMA_OUT_DONE_CH2_INT_CLR_V << DMA_OUT_DONE_CH2_INT_CLR_S) +#define DMA_OUT_DONE_CH2_INT_CLR_V 0x00000001 +#define DMA_OUT_DONE_CH2_INT_CLR_S 3 + +/* DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_CLR_M (DMA_IN_ERR_EOF_CH2_INT_CLR_V << DMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 + +/* DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_CLR_M (DMA_IN_SUC_EOF_CH2_INT_CLR_V << DMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 + +/* DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH2_INT_CLR_M (DMA_IN_DONE_CH2_INT_CLR_V << DMA_IN_DONE_CH2_INT_CLR_S) +#define DMA_IN_DONE_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_DONE_CH2_INT_CLR_S 0 + +/* DMA_AHB_TEST_REG register + * DMA_AHB_TEST_REG. + */ + +#define DMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x40) + +/* DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + +#define DMA_AHB_TESTADDR 0x00000003 +#define DMA_AHB_TESTADDR_M (DMA_AHB_TESTADDR_V << DMA_AHB_TESTADDR_S) +#define DMA_AHB_TESTADDR_V 0x00000003 +#define DMA_AHB_TESTADDR_S 4 + +/* DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + +#define DMA_AHB_TESTMODE 0x00000007 +#define DMA_AHB_TESTMODE_M (DMA_AHB_TESTMODE_V << DMA_AHB_TESTMODE_S) +#define DMA_AHB_TESTMODE_V 0x00000007 +#define DMA_AHB_TESTMODE_S 0 + +/* DMA_MISC_CONF_REG register + * DMA_MISC_CONF_REG. + */ + +#define DMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x44) + +/* DMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * reg_clk_en + */ + +#define DMA_CLK_EN (BIT(3)) +#define DMA_CLK_EN_M (DMA_CLK_EN_V << DMA_CLK_EN_S) +#define DMA_CLK_EN_V 0x00000001 +#define DMA_CLK_EN_S 3 + +/* DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ + +#define DMA_ARB_PRI_DIS (BIT(2)) +#define DMA_ARB_PRI_DIS_M (DMA_ARB_PRI_DIS_V << DMA_ARB_PRI_DIS_S) +#define DMA_ARB_PRI_DIS_V 0x00000001 +#define DMA_ARB_PRI_DIS_S 2 + +/* DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Set this bit, then clear this bit to reset the internal ahb FSM. + */ + +#define DMA_AHBM_RST_INTER (BIT(0)) +#define DMA_AHBM_RST_INTER_M (DMA_AHBM_RST_INTER_V << DMA_AHBM_RST_INTER_S) +#define DMA_AHBM_RST_INTER_V 0x00000001 +#define DMA_AHBM_RST_INTER_S 0 + +/* DMA_DATE_REG register + * DMA_DATE_REG. + */ + +#define DMA_DATE_REG (DR_REG_GDMA_BASE + 0x48) + +/* DMA_DATE : R/W; bitpos: [31:0]; default: 33587792; + * register version. + */ + +#define DMA_DATE 0xFFFFFFFF +#define DMA_DATE_M (DMA_DATE_V << DMA_DATE_S) +#define DMA_DATE_V 0xFFFFFFFF +#define DMA_DATE_S 0 + +/* DMA_IN_CONF0_CH0_REG register + * DMA_IN_CONF0_CH0_REG. + */ + +#define DMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) + +/* DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to + * memory via DMA. + */ + +#define DMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH0_M (DMA_MEM_TRANS_EN_CH0_V << DMA_MEM_TRANS_EN_CH0_S) +#define DMA_MEM_TRANS_EN_CH0_V 0x00000001 +#define DMA_MEM_TRANS_EN_CH0_S 4 + +/* DMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 + * receiving data when accessing internal SRAM. + */ + +#define DMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH0_M (DMA_IN_DATA_BURST_EN_CH0_V << DMA_IN_DATA_BURST_EN_CH0_S) +#define DMA_IN_DATA_BURST_EN_CH0_V 0x00000001 +#define DMA_IN_DATA_BURST_EN_CH0_S 3 + +/* DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH0_M (DMA_INDSCR_BURST_EN_CH0_V << DMA_INDSCR_BURST_EN_CH0_S) +#define DMA_INDSCR_BURST_EN_CH0_V 0x00000001 +#define DMA_INDSCR_BURST_EN_CH0_S 2 + +/* DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH0_M (DMA_IN_LOOP_TEST_CH0_V << DMA_IN_LOOP_TEST_CH0_S) +#define DMA_IN_LOOP_TEST_CH0_V 0x00000001 +#define DMA_IN_LOOP_TEST_CH0_S 1 + +/* DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ + +#define DMA_IN_RST_CH0 (BIT(0)) +#define DMA_IN_RST_CH0_M (DMA_IN_RST_CH0_V << DMA_IN_RST_CH0_S) +#define DMA_IN_RST_CH0_V 0x00000001 +#define DMA_IN_RST_CH0_S 0 + +/* DMA_IN_CONF1_CH0_REG register + * DMA_IN_CONF1_CH0_REG. + */ + +#define DMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) + +/* DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH0_M (DMA_IN_CHECK_OWNER_CH0_V << DMA_IN_CHECK_OWNER_CH0_S) +#define DMA_IN_CHECK_OWNER_CH0_V 0x00000001 +#define DMA_IN_CHECK_OWNER_CH0_S 12 + +/* DMA_INFIFO_STATUS_CH0_REG register + * DMA_INFIFO_STATUS_CH0_REG. + */ + +#define DMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) + +/* DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ + +#define DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH0_M (DMA_IN_BUF_HUNGRY_CH0_V << DMA_IN_BUF_HUNGRY_CH0_S) +#define DMA_IN_BUF_HUNGRY_CH0_V 0x00000001 +#define DMA_IN_BUF_HUNGRY_CH0_S 27 + +/* DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH0_M (DMA_IN_REMAIN_UNDER_4B_CH0_V << DMA_IN_REMAIN_UNDER_4B_CH0_S) +#define DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_4B_CH0_S 26 + +/* DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH0_M (DMA_IN_REMAIN_UNDER_3B_CH0_V << DMA_IN_REMAIN_UNDER_3B_CH0_S) +#define DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_3B_CH0_S 25 + +/* DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH0_M (DMA_IN_REMAIN_UNDER_2B_CH0_V << DMA_IN_REMAIN_UNDER_2B_CH0_S) +#define DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_2B_CH0_S 24 + +/* DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH0_M (DMA_IN_REMAIN_UNDER_1B_CH0_V << DMA_IN_REMAIN_UNDER_1B_CH0_S) +#define DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_1B_CH0_S 23 + +/* DMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx + * channel 0. + */ + +#define DMA_INFIFO_CNT_CH0 0x0000003F +#define DMA_INFIFO_CNT_CH0_M (DMA_INFIFO_CNT_CH0_V << DMA_INFIFO_CNT_CH0_S) +#define DMA_INFIFO_CNT_CH0_V 0x0000003F +#define DMA_INFIFO_CNT_CH0_S 2 + +/* DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ + +#define DMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH0_M (DMA_INFIFO_EMPTY_CH0_V << DMA_INFIFO_EMPTY_CH0_S) +#define DMA_INFIFO_EMPTY_CH0_V 0x00000001 +#define DMA_INFIFO_EMPTY_CH0_S 1 + +/* DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ + +#define DMA_INFIFO_FULL_CH0 (BIT(0)) +#define DMA_INFIFO_FULL_CH0_M (DMA_INFIFO_FULL_CH0_V << DMA_INFIFO_FULL_CH0_S) +#define DMA_INFIFO_FULL_CH0_V 0x00000001 +#define DMA_INFIFO_FULL_CH0_S 0 + +/* DMA_IN_POP_CH0_REG register + * DMA_IN_POP_CH0_REG. + */ + +#define DMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) + +/* DMA_INFIFO_POP_CH0 : R/W/SC; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + +#define DMA_INFIFO_POP_CH0 (BIT(12)) +#define DMA_INFIFO_POP_CH0_M (DMA_INFIFO_POP_CH0_V << DMA_INFIFO_POP_CH0_S) +#define DMA_INFIFO_POP_CH0_V 0x00000001 +#define DMA_INFIFO_POP_CH0_S 12 + +/* DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + +#define DMA_INFIFO_RDATA_CH0 0x00000FFF +#define DMA_INFIFO_RDATA_CH0_M (DMA_INFIFO_RDATA_CH0_V << DMA_INFIFO_RDATA_CH0_S) +#define DMA_INFIFO_RDATA_CH0_V 0x00000FFF +#define DMA_INFIFO_RDATA_CH0_S 0 + +/* DMA_IN_LINK_CH0_REG register + * DMA_IN_LINK_CH0_REG. + */ + +#define DMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) + +/* DMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink + * descriptor's FSM is working. + */ + +#define DMA_INLINK_PARK_CH0 (BIT(24)) +#define DMA_INLINK_PARK_CH0_M (DMA_INLINK_PARK_CH0_V << DMA_INLINK_PARK_CH0_S) +#define DMA_INLINK_PARK_CH0_V 0x00000001 +#define DMA_INLINK_PARK_CH0_S 24 + +/* DMA_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + +#define DMA_INLINK_RESTART_CH0 (BIT(23)) +#define DMA_INLINK_RESTART_CH0_M (DMA_INLINK_RESTART_CH0_V << DMA_INLINK_RESTART_CH0_S) +#define DMA_INLINK_RESTART_CH0_V 0x00000001 +#define DMA_INLINK_RESTART_CH0_S 23 + +/* DMA_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + +#define DMA_INLINK_START_CH0 (BIT(22)) +#define DMA_INLINK_START_CH0_M (DMA_INLINK_START_CH0_V << DMA_INLINK_START_CH0_S) +#define DMA_INLINK_START_CH0_V 0x00000001 +#define DMA_INLINK_START_CH0_S 22 + +/* DMA_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + +#define DMA_INLINK_STOP_CH0 (BIT(21)) +#define DMA_INLINK_STOP_CH0_M (DMA_INLINK_STOP_CH0_V << DMA_INLINK_STOP_CH0_S) +#define DMA_INLINK_STOP_CH0_V 0x00000001 +#define DMA_INLINK_STOP_CH0_S 21 + +/* DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address, when there + * are some errors in current receiving data. + */ + +#define DMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH0_M (DMA_INLINK_AUTO_RET_CH0_V << DMA_INLINK_AUTO_RET_CH0_S) +#define DMA_INLINK_AUTO_RET_CH0_V 0x00000001 +#define DMA_INLINK_AUTO_RET_CH0_S 20 + +/* DMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink + * descriptor's address. + */ + +#define DMA_INLINK_ADDR_CH0 0x000FFFFF +#define DMA_INLINK_ADDR_CH0_M (DMA_INLINK_ADDR_CH0_V << DMA_INLINK_ADDR_CH0_S) +#define DMA_INLINK_ADDR_CH0_V 0x000FFFFF +#define DMA_INLINK_ADDR_CH0_S 0 + +/* DMA_IN_STATE_CH0_REG register + * DMA_IN_STATE_CH0_REG. + */ + +#define DMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) + +/* DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_IN_STATE_CH0 0x00000007 +#define DMA_IN_STATE_CH0_M (DMA_IN_STATE_CH0_V << DMA_IN_STATE_CH0_S) +#define DMA_IN_STATE_CH0_V 0x00000007 +#define DMA_IN_STATE_CH0_S 20 + +/* DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_IN_DSCR_STATE_CH0 0x00000003 +#define DMA_IN_DSCR_STATE_CH0_M (DMA_IN_DSCR_STATE_CH0_V << DMA_IN_DSCR_STATE_CH0_S) +#define DMA_IN_DSCR_STATE_CH0_V 0x00000003 +#define DMA_IN_DSCR_STATE_CH0_S 18 + +/* DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + +#define DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH0_M (DMA_INLINK_DSCR_ADDR_CH0_V << DMA_INLINK_DSCR_ADDR_CH0_S) +#define DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH0_S 0 + +/* DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) + +/* DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_M (DMA_IN_SUC_EOF_DES_ADDR_CH0_V << DMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/* DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) + +/* DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are + * some errors in current receiving data. Only used when peripheral is UHCI0. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_M (DMA_IN_ERR_EOF_DES_ADDR_CH0_V << DMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/* DMA_IN_DSCR_CH0_REG register + * DMA_IN_DSCR_CH0_REG. + */ + +#define DMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) + +/* DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + +#define DMA_INLINK_DSCR_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH0_M (DMA_INLINK_DSCR_CH0_V << DMA_INLINK_DSCR_CH0_S) +#define DMA_INLINK_DSCR_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH0_S 0 + +/* DMA_IN_DSCR_BF0_CH0_REG register + * DMA_IN_DSCR_BF0_CH0_REG. + */ + +#define DMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) + +/* DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + +#define DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH0_M (DMA_INLINK_DSCR_BF0_CH0_V << DMA_INLINK_DSCR_BF0_CH0_S) +#define DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH0_S 0 + +/* DMA_IN_DSCR_BF1_CH0_REG register + * DMA_IN_DSCR_BF1_CH0_REG. + */ + +#define DMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) + +/* DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH0_M (DMA_INLINK_DSCR_BF1_CH0_V << DMA_INLINK_DSCR_BF1_CH0_S) +#define DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH0_S 0 + +/* DMA_IN_PRI_CH0_REG register + * DMA_IN_PRI_CH0_REG. + */ + +#define DMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) + +/* DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value, the higher of the + * priority. + */ + +#define DMA_RX_PRI_CH0 0x0000000F +#define DMA_RX_PRI_CH0_M (DMA_RX_PRI_CH0_V << DMA_RX_PRI_CH0_S) +#define DMA_RX_PRI_CH0_V 0x0000000F +#define DMA_RX_PRI_CH0_S 0 + +/* DMA_IN_PERI_SEL_CH0_REG register + * DMA_IN_PERI_SEL_CH0_REG. + */ + +#define DMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) + +/* DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_IN_SEL_CH0 0x0000003F +#define DMA_PERI_IN_SEL_CH0_M (DMA_PERI_IN_SEL_CH0_V << DMA_PERI_IN_SEL_CH0_S) +#define DMA_PERI_IN_SEL_CH0_V 0x0000003F +#define DMA_PERI_IN_SEL_CH0_S 0 + +/* DMA_OUT_CONF0_CH0_REG register + * DMA_OUT_CONF0_CH0_REG. + */ + +#define DMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) + +/* DMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 + * transmitting data when accessing internal SRAM. + */ + +#define DMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH0_M (DMA_OUT_DATA_BURST_EN_CH0_V << DMA_OUT_DATA_BURST_EN_CH0_S) +#define DMA_OUT_DATA_BURST_EN_CH0_V 0x00000001 +#define DMA_OUT_DATA_BURST_EN_CH0_S 5 + +/* DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH0_M (DMA_OUTDSCR_BURST_EN_CH0_V << DMA_OUTDSCR_BURST_EN_CH0_S) +#define DMA_OUTDSCR_BURST_EN_CH0_V 0x00000001 +#define DMA_OUTDSCR_BURST_EN_CH0_S 4 + +/* DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx + * channel 0 is generated when data need to transmit has been popped from + * FIFO in DMA + */ + +#define DMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH0_M (DMA_OUT_EOF_MODE_CH0_V << DMA_OUT_EOF_MODE_CH0_S) +#define DMA_OUT_EOF_MODE_CH0_V 0x00000001 +#define DMA_OUT_EOF_MODE_CH0_S 3 + +/* DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in + * tx buffer has been transmitted. + */ + +#define DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH0_M (DMA_OUT_AUTO_WRBACK_CH0_V << DMA_OUT_AUTO_WRBACK_CH0_S) +#define DMA_OUT_AUTO_WRBACK_CH0_V 0x00000001 +#define DMA_OUT_AUTO_WRBACK_CH0_S 2 + +/* DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH0_M (DMA_OUT_LOOP_TEST_CH0_V << DMA_OUT_LOOP_TEST_CH0_S) +#define DMA_OUT_LOOP_TEST_CH0_V 0x00000001 +#define DMA_OUT_LOOP_TEST_CH0_S 1 + +/* DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ + +#define DMA_OUT_RST_CH0 (BIT(0)) +#define DMA_OUT_RST_CH0_M (DMA_OUT_RST_CH0_V << DMA_OUT_RST_CH0_S) +#define DMA_OUT_RST_CH0_V 0x00000001 +#define DMA_OUT_RST_CH0_S 0 + +/* DMA_OUT_CONF1_CH0_REG register + * DMA_OUT_CONF1_CH0_REG. + */ + +#define DMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) + +/* DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH0_M (DMA_OUT_CHECK_OWNER_CH0_V << DMA_OUT_CHECK_OWNER_CH0_S) +#define DMA_OUT_CHECK_OWNER_CH0_V 0x00000001 +#define DMA_OUT_CHECK_OWNER_CH0_S 12 + +/* DMA_OUTFIFO_STATUS_CH0_REG register + * DMA_OUTFIFO_STATUS_CH0_REG. + */ + +#define DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) + +/* DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH0_M (DMA_OUT_REMAIN_UNDER_4B_CH0_V << DMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define DMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/* DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH0_M (DMA_OUT_REMAIN_UNDER_3B_CH0_V << DMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 + +/* DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH0_M (DMA_OUT_REMAIN_UNDER_2B_CH0_V << DMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 + +/* DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH0_M (DMA_OUT_REMAIN_UNDER_1B_CH0_V << DMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 + +/* DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx + * channel 0. + */ + +#define DMA_OUTFIFO_CNT_CH0 0x0000003F +#define DMA_OUTFIFO_CNT_CH0_M (DMA_OUTFIFO_CNT_CH0_V << DMA_OUTFIFO_CNT_CH0_S) +#define DMA_OUTFIFO_CNT_CH0_V 0x0000003F +#define DMA_OUTFIFO_CNT_CH0_S 2 + +/* DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ + +#define DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH0_M (DMA_OUTFIFO_EMPTY_CH0_V << DMA_OUTFIFO_EMPTY_CH0_S) +#define DMA_OUTFIFO_EMPTY_CH0_V 0x00000001 +#define DMA_OUTFIFO_EMPTY_CH0_S 1 + +/* DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ + +#define DMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH0_M (DMA_OUTFIFO_FULL_CH0_V << DMA_OUTFIFO_FULL_CH0_S) +#define DMA_OUTFIFO_FULL_CH0_V 0x00000001 +#define DMA_OUTFIFO_FULL_CH0_S 0 + +/* DMA_OUT_PUSH_CH0_REG register + * DMA_OUT_PUSH_CH0_REG. + */ + +#define DMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) + +/* DMA_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + +#define DMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH0_M (DMA_OUTFIFO_PUSH_CH0_V << DMA_OUTFIFO_PUSH_CH0_S) +#define DMA_OUTFIFO_PUSH_CH0_V 0x00000001 +#define DMA_OUTFIFO_PUSH_CH0_S 9 + +/* DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + +#define DMA_OUTFIFO_WDATA_CH0 0x000001FF +#define DMA_OUTFIFO_WDATA_CH0_M (DMA_OUTFIFO_WDATA_CH0_V << DMA_OUTFIFO_WDATA_CH0_S) +#define DMA_OUTFIFO_WDATA_CH0_V 0x000001FF +#define DMA_OUTFIFO_WDATA_CH0_S 0 + +/* DMA_OUT_LINK_CH0_REG register + * DMA_OUT_LINK_CH0_REG. + */ + +#define DMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) + +/* DMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink + * descriptor's FSM is working. + */ + +#define DMA_OUTLINK_PARK_CH0 (BIT(23)) +#define DMA_OUTLINK_PARK_CH0_M (DMA_OUTLINK_PARK_CH0_V << DMA_OUTLINK_PARK_CH0_S) +#define DMA_OUTLINK_PARK_CH0_V 0x00000001 +#define DMA_OUTLINK_PARK_CH0_S 23 + +/* DMA_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + +#define DMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH0_M (DMA_OUTLINK_RESTART_CH0_V << DMA_OUTLINK_RESTART_CH0_S) +#define DMA_OUTLINK_RESTART_CH0_V 0x00000001 +#define DMA_OUTLINK_RESTART_CH0_S 22 + +/* DMA_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_START_CH0 (BIT(21)) +#define DMA_OUTLINK_START_CH0_M (DMA_OUTLINK_START_CH0_V << DMA_OUTLINK_START_CH0_S) +#define DMA_OUTLINK_START_CH0_V 0x00000001 +#define DMA_OUTLINK_START_CH0_S 21 + +/* DMA_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_STOP_CH0 (BIT(20)) +#define DMA_OUTLINK_STOP_CH0_M (DMA_OUTLINK_STOP_CH0_V << DMA_OUTLINK_STOP_CH0_S) +#define DMA_OUTLINK_STOP_CH0_V 0x00000001 +#define DMA_OUTLINK_STOP_CH0_S 20 + +/* DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + +#define DMA_OUTLINK_ADDR_CH0 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH0_M (DMA_OUTLINK_ADDR_CH0_V << DMA_OUTLINK_ADDR_CH0_S) +#define DMA_OUTLINK_ADDR_CH0_V 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH0_S 0 + +/* DMA_OUT_STATE_CH0_REG register + * DMA_OUT_STATE_CH0_REG. + */ + +#define DMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) + +/* DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_OUT_STATE_CH0 0x00000007 +#define DMA_OUT_STATE_CH0_M (DMA_OUT_STATE_CH0_V << DMA_OUT_STATE_CH0_S) +#define DMA_OUT_STATE_CH0_V 0x00000007 +#define DMA_OUT_STATE_CH0_S 20 + +/* DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_OUT_DSCR_STATE_CH0 0x00000003 +#define DMA_OUT_DSCR_STATE_CH0_M (DMA_OUT_DSCR_STATE_CH0_V << DMA_OUT_DSCR_STATE_CH0_S) +#define DMA_OUT_DSCR_STATE_CH0_V 0x00000003 +#define DMA_OUT_DSCR_STATE_CH0_S 18 + +/* DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + +#define DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH0_M (DMA_OUTLINK_DSCR_ADDR_CH0_V << DMA_OUTLINK_DSCR_ADDR_CH0_S) +#define DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH0_S 0 + +/* DMA_OUT_EOF_DES_ADDR_CH0_REG register + * DMA_OUT_EOF_DES_ADDR_CH0_REG. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) + +/* DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH0_M (DMA_OUT_EOF_DES_ADDR_CH0_V << DMA_OUT_EOF_DES_ADDR_CH0_S) +#define DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the + * last outlink descriptor. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_M (DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << DMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/* DMA_OUT_DSCR_CH0_REG register + * DMA_OUT_DSCR_CH0_REG. + */ + +#define DMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) + +/* DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + +#define DMA_OUTLINK_DSCR_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH0_M (DMA_OUTLINK_DSCR_CH0_V << DMA_OUTLINK_DSCR_CH0_S) +#define DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH0_S 0 + +/* DMA_OUT_DSCR_BF0_CH0_REG register + * DMA_OUT_DSCR_BF0_CH0_REG. + */ + +#define DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) + +/* DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + +#define DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH0_M (DMA_OUTLINK_DSCR_BF0_CH0_V << DMA_OUTLINK_DSCR_BF0_CH0_S) +#define DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/* DMA_OUT_DSCR_BF1_CH0_REG register + * DMA_OUT_DSCR_BF1_CH0_REG. + */ + +#define DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) + +/* DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH0_M (DMA_OUTLINK_DSCR_BF1_CH0_V << DMA_OUTLINK_DSCR_BF1_CH0_S) +#define DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/* DMA_OUT_PRI_CH0_REG register + * DMA_OUT_PRI_CH0_REG. + */ + +#define DMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) + +/* DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value, the higher of the + * priority. + */ + +#define DMA_TX_PRI_CH0 0x0000000F +#define DMA_TX_PRI_CH0_M (DMA_TX_PRI_CH0_V << DMA_TX_PRI_CH0_S) +#define DMA_TX_PRI_CH0_V 0x0000000F +#define DMA_TX_PRI_CH0_S 0 + +/* DMA_OUT_PERI_SEL_CH0_REG register + * DMA_OUT_PERI_SEL_CH0_REG. + */ + +#define DMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) + +/* DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_OUT_SEL_CH0 0x0000003F +#define DMA_PERI_OUT_SEL_CH0_M (DMA_PERI_OUT_SEL_CH0_V << DMA_PERI_OUT_SEL_CH0_S) +#define DMA_PERI_OUT_SEL_CH0_V 0x0000003F +#define DMA_PERI_OUT_SEL_CH0_S 0 + +/* DMA_IN_CONF0_CH1_REG register + * DMA_IN_CONF0_CH1_REG. + */ + +#define DMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) + +/* DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to + * memory via DMA. + */ + +#define DMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH1_M (DMA_MEM_TRANS_EN_CH1_V << DMA_MEM_TRANS_EN_CH1_S) +#define DMA_MEM_TRANS_EN_CH1_V 0x00000001 +#define DMA_MEM_TRANS_EN_CH1_S 4 + +/* DMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 + * receiving data when accessing internal SRAM. + */ + +#define DMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH1_M (DMA_IN_DATA_BURST_EN_CH1_V << DMA_IN_DATA_BURST_EN_CH1_S) +#define DMA_IN_DATA_BURST_EN_CH1_V 0x00000001 +#define DMA_IN_DATA_BURST_EN_CH1_S 3 + +/* DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH1_M (DMA_INDSCR_BURST_EN_CH1_V << DMA_INDSCR_BURST_EN_CH1_S) +#define DMA_INDSCR_BURST_EN_CH1_V 0x00000001 +#define DMA_INDSCR_BURST_EN_CH1_S 2 + +/* DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH1_M (DMA_IN_LOOP_TEST_CH1_V << DMA_IN_LOOP_TEST_CH1_S) +#define DMA_IN_LOOP_TEST_CH1_V 0x00000001 +#define DMA_IN_LOOP_TEST_CH1_S 1 + +/* DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + */ + +#define DMA_IN_RST_CH1 (BIT(0)) +#define DMA_IN_RST_CH1_M (DMA_IN_RST_CH1_V << DMA_IN_RST_CH1_S) +#define DMA_IN_RST_CH1_V 0x00000001 +#define DMA_IN_RST_CH1_S 0 + +/* DMA_IN_CONF1_CH1_REG register + * DMA_IN_CONF1_CH1_REG. + */ + +#define DMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) + +/* DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH1_M (DMA_IN_CHECK_OWNER_CH1_V << DMA_IN_CHECK_OWNER_CH1_S) +#define DMA_IN_CHECK_OWNER_CH1_V 0x00000001 +#define DMA_IN_CHECK_OWNER_CH1_S 12 + +/* DMA_INFIFO_STATUS_CH1_REG register + * DMA_INFIFO_STATUS_CH1_REG. + */ + +#define DMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) + +/* DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ + +#define DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH1_M (DMA_IN_BUF_HUNGRY_CH1_V << DMA_IN_BUF_HUNGRY_CH1_S) +#define DMA_IN_BUF_HUNGRY_CH1_V 0x00000001 +#define DMA_IN_BUF_HUNGRY_CH1_S 27 + +/* DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH1_M (DMA_IN_REMAIN_UNDER_4B_CH1_V << DMA_IN_REMAIN_UNDER_4B_CH1_S) +#define DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_4B_CH1_S 26 + +/* DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH1_M (DMA_IN_REMAIN_UNDER_3B_CH1_V << DMA_IN_REMAIN_UNDER_3B_CH1_S) +#define DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_3B_CH1_S 25 + +/* DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH1_M (DMA_IN_REMAIN_UNDER_2B_CH1_V << DMA_IN_REMAIN_UNDER_2B_CH1_S) +#define DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_2B_CH1_S 24 + +/* DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH1_M (DMA_IN_REMAIN_UNDER_1B_CH1_V << DMA_IN_REMAIN_UNDER_1B_CH1_S) +#define DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_1B_CH1_S 23 + +/* DMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx + * channel 1. + */ + +#define DMA_INFIFO_CNT_CH1 0x0000003F +#define DMA_INFIFO_CNT_CH1_M (DMA_INFIFO_CNT_CH1_V << DMA_INFIFO_CNT_CH1_S) +#define DMA_INFIFO_CNT_CH1_V 0x0000003F +#define DMA_INFIFO_CNT_CH1_S 2 + +/* DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ + +#define DMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH1_M (DMA_INFIFO_EMPTY_CH1_V << DMA_INFIFO_EMPTY_CH1_S) +#define DMA_INFIFO_EMPTY_CH1_V 0x00000001 +#define DMA_INFIFO_EMPTY_CH1_S 1 + +/* DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ + +#define DMA_INFIFO_FULL_CH1 (BIT(0)) +#define DMA_INFIFO_FULL_CH1_M (DMA_INFIFO_FULL_CH1_V << DMA_INFIFO_FULL_CH1_S) +#define DMA_INFIFO_FULL_CH1_V 0x00000001 +#define DMA_INFIFO_FULL_CH1_S 0 + +/* DMA_IN_POP_CH1_REG register + * DMA_IN_POP_CH1_REG. + */ + +#define DMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) + +/* DMA_INFIFO_POP_CH1 : R/W/SC; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + +#define DMA_INFIFO_POP_CH1 (BIT(12)) +#define DMA_INFIFO_POP_CH1_M (DMA_INFIFO_POP_CH1_V << DMA_INFIFO_POP_CH1_S) +#define DMA_INFIFO_POP_CH1_V 0x00000001 +#define DMA_INFIFO_POP_CH1_S 12 + +/* DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + +#define DMA_INFIFO_RDATA_CH1 0x00000FFF +#define DMA_INFIFO_RDATA_CH1_M (DMA_INFIFO_RDATA_CH1_V << DMA_INFIFO_RDATA_CH1_S) +#define DMA_INFIFO_RDATA_CH1_V 0x00000FFF +#define DMA_INFIFO_RDATA_CH1_S 0 + +/* DMA_IN_LINK_CH1_REG register + * DMA_IN_LINK_CH1_REG. + */ + +#define DMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) + +/* DMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink + * descriptor's FSM is working. + */ + +#define DMA_INLINK_PARK_CH1 (BIT(24)) +#define DMA_INLINK_PARK_CH1_M (DMA_INLINK_PARK_CH1_V << DMA_INLINK_PARK_CH1_S) +#define DMA_INLINK_PARK_CH1_V 0x00000001 +#define DMA_INLINK_PARK_CH1_S 24 + +/* DMA_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + +#define DMA_INLINK_RESTART_CH1 (BIT(23)) +#define DMA_INLINK_RESTART_CH1_M (DMA_INLINK_RESTART_CH1_V << DMA_INLINK_RESTART_CH1_S) +#define DMA_INLINK_RESTART_CH1_V 0x00000001 +#define DMA_INLINK_RESTART_CH1_S 23 + +/* DMA_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + +#define DMA_INLINK_START_CH1 (BIT(22)) +#define DMA_INLINK_START_CH1_M (DMA_INLINK_START_CH1_V << DMA_INLINK_START_CH1_S) +#define DMA_INLINK_START_CH1_V 0x00000001 +#define DMA_INLINK_START_CH1_S 22 + +/* DMA_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + +#define DMA_INLINK_STOP_CH1 (BIT(21)) +#define DMA_INLINK_STOP_CH1_M (DMA_INLINK_STOP_CH1_V << DMA_INLINK_STOP_CH1_S) +#define DMA_INLINK_STOP_CH1_V 0x00000001 +#define DMA_INLINK_STOP_CH1_S 21 + +/* DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address, when there + * are some errors in current receiving data. + */ + +#define DMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH1_M (DMA_INLINK_AUTO_RET_CH1_V << DMA_INLINK_AUTO_RET_CH1_S) +#define DMA_INLINK_AUTO_RET_CH1_V 0x00000001 +#define DMA_INLINK_AUTO_RET_CH1_S 20 + +/* DMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink + * descriptor's address. + */ + +#define DMA_INLINK_ADDR_CH1 0x000FFFFF +#define DMA_INLINK_ADDR_CH1_M (DMA_INLINK_ADDR_CH1_V << DMA_INLINK_ADDR_CH1_S) +#define DMA_INLINK_ADDR_CH1_V 0x000FFFFF +#define DMA_INLINK_ADDR_CH1_S 0 + +/* DMA_IN_STATE_CH1_REG register + * DMA_IN_STATE_CH1_REG. + */ + +#define DMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) + +/* DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_IN_STATE_CH1 0x00000007 +#define DMA_IN_STATE_CH1_M (DMA_IN_STATE_CH1_V << DMA_IN_STATE_CH1_S) +#define DMA_IN_STATE_CH1_V 0x00000007 +#define DMA_IN_STATE_CH1_S 20 + +/* DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_IN_DSCR_STATE_CH1 0x00000003 +#define DMA_IN_DSCR_STATE_CH1_M (DMA_IN_DSCR_STATE_CH1_V << DMA_IN_DSCR_STATE_CH1_S) +#define DMA_IN_DSCR_STATE_CH1_V 0x00000003 +#define DMA_IN_DSCR_STATE_CH1_S 18 + +/* DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + +#define DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH1_M (DMA_INLINK_DSCR_ADDR_CH1_V << DMA_INLINK_DSCR_ADDR_CH1_S) +#define DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH1_S 0 + +/* DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) + +/* DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_M (DMA_IN_SUC_EOF_DES_ADDR_CH1_V << DMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/* DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) + +/* DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are + * some errors in current receiving data. Only used when peripheral is UHCI0. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_M (DMA_IN_ERR_EOF_DES_ADDR_CH1_V << DMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/* DMA_IN_DSCR_CH1_REG register + * DMA_IN_DSCR_CH1_REG. + */ + +#define DMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) + +/* DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + +#define DMA_INLINK_DSCR_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH1_M (DMA_INLINK_DSCR_CH1_V << DMA_INLINK_DSCR_CH1_S) +#define DMA_INLINK_DSCR_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH1_S 0 + +/* DMA_IN_DSCR_BF0_CH1_REG register + * DMA_IN_DSCR_BF0_CH1_REG. + */ + +#define DMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) + +/* DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + +#define DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH1_M (DMA_INLINK_DSCR_BF0_CH1_V << DMA_INLINK_DSCR_BF0_CH1_S) +#define DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH1_S 0 + +/* DMA_IN_DSCR_BF1_CH1_REG register + * DMA_IN_DSCR_BF1_CH1_REG. + */ + +#define DMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) + +/* DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH1_M (DMA_INLINK_DSCR_BF1_CH1_V << DMA_INLINK_DSCR_BF1_CH1_S) +#define DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH1_S 0 + +/* DMA_IN_PRI_CH1_REG register + * DMA_IN_PRI_CH1_REG. + */ + +#define DMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) + +/* DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value, the higher of the + * priority. + */ + +#define DMA_RX_PRI_CH1 0x0000000F +#define DMA_RX_PRI_CH1_M (DMA_RX_PRI_CH1_V << DMA_RX_PRI_CH1_S) +#define DMA_RX_PRI_CH1_V 0x0000000F +#define DMA_RX_PRI_CH1_S 0 + +/* DMA_IN_PERI_SEL_CH1_REG register + * DMA_IN_PERI_SEL_CH1_REG. + */ + +#define DMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) + +/* DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_IN_SEL_CH1 0x0000003F +#define DMA_PERI_IN_SEL_CH1_M (DMA_PERI_IN_SEL_CH1_V << DMA_PERI_IN_SEL_CH1_S) +#define DMA_PERI_IN_SEL_CH1_V 0x0000003F +#define DMA_PERI_IN_SEL_CH1_S 0 + +/* DMA_OUT_CONF0_CH1_REG register + * DMA_OUT_CONF0_CH1_REG. + */ + +#define DMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) + +/* DMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 + * transmitting data when accessing internal SRAM. + */ + +#define DMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH1_M (DMA_OUT_DATA_BURST_EN_CH1_V << DMA_OUT_DATA_BURST_EN_CH1_S) +#define DMA_OUT_DATA_BURST_EN_CH1_V 0x00000001 +#define DMA_OUT_DATA_BURST_EN_CH1_S 5 + +/* DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH1_M (DMA_OUTDSCR_BURST_EN_CH1_V << DMA_OUTDSCR_BURST_EN_CH1_S) +#define DMA_OUTDSCR_BURST_EN_CH1_V 0x00000001 +#define DMA_OUTDSCR_BURST_EN_CH1_S 4 + +/* DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx + * channel 1 is generated when data need to transmit has been popped from + * FIFO in DMA + */ + +#define DMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH1_M (DMA_OUT_EOF_MODE_CH1_V << DMA_OUT_EOF_MODE_CH1_S) +#define DMA_OUT_EOF_MODE_CH1_V 0x00000001 +#define DMA_OUT_EOF_MODE_CH1_S 3 + +/* DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in + * tx buffer has been transmitted. + */ + +#define DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH1_M (DMA_OUT_AUTO_WRBACK_CH1_V << DMA_OUT_AUTO_WRBACK_CH1_S) +#define DMA_OUT_AUTO_WRBACK_CH1_V 0x00000001 +#define DMA_OUT_AUTO_WRBACK_CH1_S 2 + +/* DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH1_M (DMA_OUT_LOOP_TEST_CH1_V << DMA_OUT_LOOP_TEST_CH1_S) +#define DMA_OUT_LOOP_TEST_CH1_V 0x00000001 +#define DMA_OUT_LOOP_TEST_CH1_S 1 + +/* DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + */ + +#define DMA_OUT_RST_CH1 (BIT(0)) +#define DMA_OUT_RST_CH1_M (DMA_OUT_RST_CH1_V << DMA_OUT_RST_CH1_S) +#define DMA_OUT_RST_CH1_V 0x00000001 +#define DMA_OUT_RST_CH1_S 0 + +/* DMA_OUT_CONF1_CH1_REG register + * DMA_OUT_CONF1_CH1_REG. + */ + +#define DMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) + +/* DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH1_M (DMA_OUT_CHECK_OWNER_CH1_V << DMA_OUT_CHECK_OWNER_CH1_S) +#define DMA_OUT_CHECK_OWNER_CH1_V 0x00000001 +#define DMA_OUT_CHECK_OWNER_CH1_S 12 + +/* DMA_OUTFIFO_STATUS_CH1_REG register + * DMA_OUTFIFO_STATUS_CH1_REG. + */ + +#define DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) + +/* DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH1_M (DMA_OUT_REMAIN_UNDER_4B_CH1_V << DMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define DMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/* DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH1_M (DMA_OUT_REMAIN_UNDER_3B_CH1_V << DMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 + +/* DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH1_M (DMA_OUT_REMAIN_UNDER_2B_CH1_V << DMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 + +/* DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH1_M (DMA_OUT_REMAIN_UNDER_1B_CH1_V << DMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 + +/* DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx + * channel 1. + */ + +#define DMA_OUTFIFO_CNT_CH1 0x0000003F +#define DMA_OUTFIFO_CNT_CH1_M (DMA_OUTFIFO_CNT_CH1_V << DMA_OUTFIFO_CNT_CH1_S) +#define DMA_OUTFIFO_CNT_CH1_V 0x0000003F +#define DMA_OUTFIFO_CNT_CH1_S 2 + +/* DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ + +#define DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH1_M (DMA_OUTFIFO_EMPTY_CH1_V << DMA_OUTFIFO_EMPTY_CH1_S) +#define DMA_OUTFIFO_EMPTY_CH1_V 0x00000001 +#define DMA_OUTFIFO_EMPTY_CH1_S 1 + +/* DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ + +#define DMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH1_M (DMA_OUTFIFO_FULL_CH1_V << DMA_OUTFIFO_FULL_CH1_S) +#define DMA_OUTFIFO_FULL_CH1_V 0x00000001 +#define DMA_OUTFIFO_FULL_CH1_S 0 + +/* DMA_OUT_PUSH_CH1_REG register + * DMA_OUT_PUSH_CH1_REG. + */ + +#define DMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) + +/* DMA_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + +#define DMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH1_M (DMA_OUTFIFO_PUSH_CH1_V << DMA_OUTFIFO_PUSH_CH1_S) +#define DMA_OUTFIFO_PUSH_CH1_V 0x00000001 +#define DMA_OUTFIFO_PUSH_CH1_S 9 + +/* DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + +#define DMA_OUTFIFO_WDATA_CH1 0x000001FF +#define DMA_OUTFIFO_WDATA_CH1_M (DMA_OUTFIFO_WDATA_CH1_V << DMA_OUTFIFO_WDATA_CH1_S) +#define DMA_OUTFIFO_WDATA_CH1_V 0x000001FF +#define DMA_OUTFIFO_WDATA_CH1_S 0 + +/* DMA_OUT_LINK_CH1_REG register + * DMA_OUT_LINK_CH1_REG. + */ + +#define DMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) + +/* DMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink + * descriptor's FSM is working. + */ + +#define DMA_OUTLINK_PARK_CH1 (BIT(23)) +#define DMA_OUTLINK_PARK_CH1_M (DMA_OUTLINK_PARK_CH1_V << DMA_OUTLINK_PARK_CH1_S) +#define DMA_OUTLINK_PARK_CH1_V 0x00000001 +#define DMA_OUTLINK_PARK_CH1_S 23 + +/* DMA_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + +#define DMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH1_M (DMA_OUTLINK_RESTART_CH1_V << DMA_OUTLINK_RESTART_CH1_S) +#define DMA_OUTLINK_RESTART_CH1_V 0x00000001 +#define DMA_OUTLINK_RESTART_CH1_S 22 + +/* DMA_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_START_CH1 (BIT(21)) +#define DMA_OUTLINK_START_CH1_M (DMA_OUTLINK_START_CH1_V << DMA_OUTLINK_START_CH1_S) +#define DMA_OUTLINK_START_CH1_V 0x00000001 +#define DMA_OUTLINK_START_CH1_S 21 + +/* DMA_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_STOP_CH1 (BIT(20)) +#define DMA_OUTLINK_STOP_CH1_M (DMA_OUTLINK_STOP_CH1_V << DMA_OUTLINK_STOP_CH1_S) +#define DMA_OUTLINK_STOP_CH1_V 0x00000001 +#define DMA_OUTLINK_STOP_CH1_S 20 + +/* DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + +#define DMA_OUTLINK_ADDR_CH1 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH1_M (DMA_OUTLINK_ADDR_CH1_V << DMA_OUTLINK_ADDR_CH1_S) +#define DMA_OUTLINK_ADDR_CH1_V 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH1_S 0 + +/* DMA_OUT_STATE_CH1_REG register + * DMA_OUT_STATE_CH1_REG. + */ + +#define DMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) + +/* DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_OUT_STATE_CH1 0x00000007 +#define DMA_OUT_STATE_CH1_M (DMA_OUT_STATE_CH1_V << DMA_OUT_STATE_CH1_S) +#define DMA_OUT_STATE_CH1_V 0x00000007 +#define DMA_OUT_STATE_CH1_S 20 + +/* DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_OUT_DSCR_STATE_CH1 0x00000003 +#define DMA_OUT_DSCR_STATE_CH1_M (DMA_OUT_DSCR_STATE_CH1_V << DMA_OUT_DSCR_STATE_CH1_S) +#define DMA_OUT_DSCR_STATE_CH1_V 0x00000003 +#define DMA_OUT_DSCR_STATE_CH1_S 18 + +/* DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + +#define DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH1_M (DMA_OUTLINK_DSCR_ADDR_CH1_V << DMA_OUTLINK_DSCR_ADDR_CH1_S) +#define DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH1_S 0 + +/* DMA_OUT_EOF_DES_ADDR_CH1_REG register + * DMA_OUT_EOF_DES_ADDR_CH1_REG. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) + +/* DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH1_M (DMA_OUT_EOF_DES_ADDR_CH1_V << DMA_OUT_EOF_DES_ADDR_CH1_S) +#define DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the + * last outlink descriptor. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_M (DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << DMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/* DMA_OUT_DSCR_CH1_REG register + * DMA_OUT_DSCR_CH1_REG. + */ + +#define DMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) + +/* DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + +#define DMA_OUTLINK_DSCR_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH1_M (DMA_OUTLINK_DSCR_CH1_V << DMA_OUTLINK_DSCR_CH1_S) +#define DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH1_S 0 + +/* DMA_OUT_DSCR_BF0_CH1_REG register + * DMA_OUT_DSCR_BF0_CH1_REG. + */ + +#define DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) + +/* DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + +#define DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH1_M (DMA_OUTLINK_DSCR_BF0_CH1_V << DMA_OUTLINK_DSCR_BF0_CH1_S) +#define DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/* DMA_OUT_DSCR_BF1_CH1_REG register + * DMA_OUT_DSCR_BF1_CH1_REG. + */ + +#define DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) + +/* DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH1_M (DMA_OUTLINK_DSCR_BF1_CH1_V << DMA_OUTLINK_DSCR_BF1_CH1_S) +#define DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/* DMA_OUT_PRI_CH1_REG register + * DMA_OUT_PRI_CH1_REG. + */ + +#define DMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) + +/* DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value, the higher of the + * priority. + */ + +#define DMA_TX_PRI_CH1 0x0000000F +#define DMA_TX_PRI_CH1_M (DMA_TX_PRI_CH1_V << DMA_TX_PRI_CH1_S) +#define DMA_TX_PRI_CH1_V 0x0000000F +#define DMA_TX_PRI_CH1_S 0 + +/* DMA_OUT_PERI_SEL_CH1_REG register + * DMA_OUT_PERI_SEL_CH1_REG. + */ + +#define DMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) + +/* DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_OUT_SEL_CH1 0x0000003F +#define DMA_PERI_OUT_SEL_CH1_M (DMA_PERI_OUT_SEL_CH1_V << DMA_PERI_OUT_SEL_CH1_S) +#define DMA_PERI_OUT_SEL_CH1_V 0x0000003F +#define DMA_PERI_OUT_SEL_CH1_S 0 + +/* DMA_IN_CONF0_CH2_REG register + * DMA_IN_CONF0_CH2_REG. + */ + +#define DMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) + +/* DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to + * memory via DMA. + */ + +#define DMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH2_M (DMA_MEM_TRANS_EN_CH2_V << DMA_MEM_TRANS_EN_CH2_S) +#define DMA_MEM_TRANS_EN_CH2_V 0x00000001 +#define DMA_MEM_TRANS_EN_CH2_S 4 + +/* DMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 + * receiving data when accessing internal SRAM. + */ + +#define DMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH2_M (DMA_IN_DATA_BURST_EN_CH2_V << DMA_IN_DATA_BURST_EN_CH2_S) +#define DMA_IN_DATA_BURST_EN_CH2_V 0x00000001 +#define DMA_IN_DATA_BURST_EN_CH2_S 3 + +/* DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH2_M (DMA_INDSCR_BURST_EN_CH2_V << DMA_INDSCR_BURST_EN_CH2_S) +#define DMA_INDSCR_BURST_EN_CH2_V 0x00000001 +#define DMA_INDSCR_BURST_EN_CH2_S 2 + +/* DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH2_M (DMA_IN_LOOP_TEST_CH2_V << DMA_IN_LOOP_TEST_CH2_S) +#define DMA_IN_LOOP_TEST_CH2_V 0x00000001 +#define DMA_IN_LOOP_TEST_CH2_S 1 + +/* DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + */ + +#define DMA_IN_RST_CH2 (BIT(0)) +#define DMA_IN_RST_CH2_M (DMA_IN_RST_CH2_V << DMA_IN_RST_CH2_S) +#define DMA_IN_RST_CH2_V 0x00000001 +#define DMA_IN_RST_CH2_S 0 + +/* DMA_IN_CONF1_CH2_REG register + * DMA_IN_CONF1_CH2_REG. + */ + +#define DMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) + +/* DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH2_M (DMA_IN_CHECK_OWNER_CH2_V << DMA_IN_CHECK_OWNER_CH2_S) +#define DMA_IN_CHECK_OWNER_CH2_V 0x00000001 +#define DMA_IN_CHECK_OWNER_CH2_S 12 + +/* DMA_INFIFO_STATUS_CH2_REG register + * DMA_INFIFO_STATUS_CH2_REG. + */ + +#define DMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) + +/* DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ + +#define DMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH2_M (DMA_IN_BUF_HUNGRY_CH2_V << DMA_IN_BUF_HUNGRY_CH2_S) +#define DMA_IN_BUF_HUNGRY_CH2_V 0x00000001 +#define DMA_IN_BUF_HUNGRY_CH2_S 27 + +/* DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH2_M (DMA_IN_REMAIN_UNDER_4B_CH2_V << DMA_IN_REMAIN_UNDER_4B_CH2_S) +#define DMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_4B_CH2_S 26 + +/* DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH2_M (DMA_IN_REMAIN_UNDER_3B_CH2_V << DMA_IN_REMAIN_UNDER_3B_CH2_S) +#define DMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_3B_CH2_S 25 + +/* DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH2_M (DMA_IN_REMAIN_UNDER_2B_CH2_V << DMA_IN_REMAIN_UNDER_2B_CH2_S) +#define DMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_2B_CH2_S 24 + +/* DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH2_M (DMA_IN_REMAIN_UNDER_1B_CH2_V << DMA_IN_REMAIN_UNDER_1B_CH2_S) +#define DMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_1B_CH2_S 23 + +/* DMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx + * channel 2. + */ + +#define DMA_INFIFO_CNT_CH2 0x0000003F +#define DMA_INFIFO_CNT_CH2_M (DMA_INFIFO_CNT_CH2_V << DMA_INFIFO_CNT_CH2_S) +#define DMA_INFIFO_CNT_CH2_V 0x0000003F +#define DMA_INFIFO_CNT_CH2_S 2 + +/* DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ + +#define DMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH2_M (DMA_INFIFO_EMPTY_CH2_V << DMA_INFIFO_EMPTY_CH2_S) +#define DMA_INFIFO_EMPTY_CH2_V 0x00000001 +#define DMA_INFIFO_EMPTY_CH2_S 1 + +/* DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ + +#define DMA_INFIFO_FULL_CH2 (BIT(0)) +#define DMA_INFIFO_FULL_CH2_M (DMA_INFIFO_FULL_CH2_V << DMA_INFIFO_FULL_CH2_S) +#define DMA_INFIFO_FULL_CH2_V 0x00000001 +#define DMA_INFIFO_FULL_CH2_S 0 + +/* DMA_IN_POP_CH2_REG register + * DMA_IN_POP_CH2_REG. + */ + +#define DMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) + +/* DMA_INFIFO_POP_CH2 : R/W/SC; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + +#define DMA_INFIFO_POP_CH2 (BIT(12)) +#define DMA_INFIFO_POP_CH2_M (DMA_INFIFO_POP_CH2_V << DMA_INFIFO_POP_CH2_S) +#define DMA_INFIFO_POP_CH2_V 0x00000001 +#define DMA_INFIFO_POP_CH2_S 12 + +/* DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + +#define DMA_INFIFO_RDATA_CH2 0x00000FFF +#define DMA_INFIFO_RDATA_CH2_M (DMA_INFIFO_RDATA_CH2_V << DMA_INFIFO_RDATA_CH2_S) +#define DMA_INFIFO_RDATA_CH2_V 0x00000FFF +#define DMA_INFIFO_RDATA_CH2_S 0 + +/* DMA_IN_LINK_CH2_REG register + * DMA_IN_LINK_CH2_REG. + */ + +#define DMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) + +/* DMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink + * descriptor's FSM is working. + */ + +#define DMA_INLINK_PARK_CH2 (BIT(24)) +#define DMA_INLINK_PARK_CH2_M (DMA_INLINK_PARK_CH2_V << DMA_INLINK_PARK_CH2_S) +#define DMA_INLINK_PARK_CH2_V 0x00000001 +#define DMA_INLINK_PARK_CH2_S 24 + +/* DMA_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + +#define DMA_INLINK_RESTART_CH2 (BIT(23)) +#define DMA_INLINK_RESTART_CH2_M (DMA_INLINK_RESTART_CH2_V << DMA_INLINK_RESTART_CH2_S) +#define DMA_INLINK_RESTART_CH2_V 0x00000001 +#define DMA_INLINK_RESTART_CH2_S 23 + +/* DMA_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + +#define DMA_INLINK_START_CH2 (BIT(22)) +#define DMA_INLINK_START_CH2_M (DMA_INLINK_START_CH2_V << DMA_INLINK_START_CH2_S) +#define DMA_INLINK_START_CH2_V 0x00000001 +#define DMA_INLINK_START_CH2_S 22 + +/* DMA_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + +#define DMA_INLINK_STOP_CH2 (BIT(21)) +#define DMA_INLINK_STOP_CH2_M (DMA_INLINK_STOP_CH2_V << DMA_INLINK_STOP_CH2_S) +#define DMA_INLINK_STOP_CH2_V 0x00000001 +#define DMA_INLINK_STOP_CH2_S 21 + +/* DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address, when there + * are some errors in current receiving data. + */ + +#define DMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH2_M (DMA_INLINK_AUTO_RET_CH2_V << DMA_INLINK_AUTO_RET_CH2_S) +#define DMA_INLINK_AUTO_RET_CH2_V 0x00000001 +#define DMA_INLINK_AUTO_RET_CH2_S 20 + +/* DMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink + * descriptor's address. + */ + +#define DMA_INLINK_ADDR_CH2 0x000FFFFF +#define DMA_INLINK_ADDR_CH2_M (DMA_INLINK_ADDR_CH2_V << DMA_INLINK_ADDR_CH2_S) +#define DMA_INLINK_ADDR_CH2_V 0x000FFFFF +#define DMA_INLINK_ADDR_CH2_S 0 + +/* DMA_IN_STATE_CH2_REG register + * DMA_IN_STATE_CH2_REG. + */ + +#define DMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) + +/* DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_IN_STATE_CH2 0x00000007 +#define DMA_IN_STATE_CH2_M (DMA_IN_STATE_CH2_V << DMA_IN_STATE_CH2_S) +#define DMA_IN_STATE_CH2_V 0x00000007 +#define DMA_IN_STATE_CH2_S 20 + +/* DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_IN_DSCR_STATE_CH2 0x00000003 +#define DMA_IN_DSCR_STATE_CH2_M (DMA_IN_DSCR_STATE_CH2_V << DMA_IN_DSCR_STATE_CH2_S) +#define DMA_IN_DSCR_STATE_CH2_V 0x00000003 +#define DMA_IN_DSCR_STATE_CH2_S 18 + +/* DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + +#define DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH2_M (DMA_INLINK_DSCR_ADDR_CH2_V << DMA_INLINK_DSCR_ADDR_CH2_S) +#define DMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH2_S 0 + +/* DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) + +/* DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_M (DMA_IN_SUC_EOF_DES_ADDR_CH2_V << DMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/* DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) + +/* DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are + * some errors in current receiving data. Only used when peripheral is UHCI0. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_M (DMA_IN_ERR_EOF_DES_ADDR_CH2_V << DMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/* DMA_IN_DSCR_CH2_REG register + * DMA_IN_DSCR_CH2_REG. + */ + +#define DMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) + +/* DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + +#define DMA_INLINK_DSCR_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH2_M (DMA_INLINK_DSCR_CH2_V << DMA_INLINK_DSCR_CH2_S) +#define DMA_INLINK_DSCR_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH2_S 0 + +/* DMA_IN_DSCR_BF0_CH2_REG register + * DMA_IN_DSCR_BF0_CH2_REG. + */ + +#define DMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) + +/* DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + +#define DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH2_M (DMA_INLINK_DSCR_BF0_CH2_V << DMA_INLINK_DSCR_BF0_CH2_S) +#define DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH2_S 0 + +/* DMA_IN_DSCR_BF1_CH2_REG register + * DMA_IN_DSCR_BF1_CH2_REG. + */ + +#define DMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) + +/* DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH2_M (DMA_INLINK_DSCR_BF1_CH2_V << DMA_INLINK_DSCR_BF1_CH2_S) +#define DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH2_S 0 + +/* DMA_IN_PRI_CH2_REG register + * DMA_IN_PRI_CH2_REG. + */ + +#define DMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) + +/* DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value, the higher of the + * priority. + */ + +#define DMA_RX_PRI_CH2 0x0000000F +#define DMA_RX_PRI_CH2_M (DMA_RX_PRI_CH2_V << DMA_RX_PRI_CH2_S) +#define DMA_RX_PRI_CH2_V 0x0000000F +#define DMA_RX_PRI_CH2_S 0 + +/* DMA_IN_PERI_SEL_CH2_REG register + * DMA_IN_PERI_SEL_CH2_REG. + */ + +#define DMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) + +/* DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_IN_SEL_CH2 0x0000003F +#define DMA_PERI_IN_SEL_CH2_M (DMA_PERI_IN_SEL_CH2_V << DMA_PERI_IN_SEL_CH2_S) +#define DMA_PERI_IN_SEL_CH2_V 0x0000003F +#define DMA_PERI_IN_SEL_CH2_S 0 + +/* DMA_OUT_CONF0_CH2_REG register + * DMA_OUT_CONF0_CH2_REG. + */ + +#define DMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) + +/* DMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 + * transmitting data when accessing internal SRAM. + */ + +#define DMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH2_M (DMA_OUT_DATA_BURST_EN_CH2_V << DMA_OUT_DATA_BURST_EN_CH2_S) +#define DMA_OUT_DATA_BURST_EN_CH2_V 0x00000001 +#define DMA_OUT_DATA_BURST_EN_CH2_S 5 + +/* DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH2_M (DMA_OUTDSCR_BURST_EN_CH2_V << DMA_OUTDSCR_BURST_EN_CH2_S) +#define DMA_OUTDSCR_BURST_EN_CH2_V 0x00000001 +#define DMA_OUTDSCR_BURST_EN_CH2_S 4 + +/* DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx + * channel 2 is generated when data need to transmit has been popped from + * FIFO in DMA + */ + +#define DMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH2_M (DMA_OUT_EOF_MODE_CH2_V << DMA_OUT_EOF_MODE_CH2_S) +#define DMA_OUT_EOF_MODE_CH2_V 0x00000001 +#define DMA_OUT_EOF_MODE_CH2_S 3 + +/* DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in + * tx buffer has been transmitted. + */ + +#define DMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH2_M (DMA_OUT_AUTO_WRBACK_CH2_V << DMA_OUT_AUTO_WRBACK_CH2_S) +#define DMA_OUT_AUTO_WRBACK_CH2_V 0x00000001 +#define DMA_OUT_AUTO_WRBACK_CH2_S 2 + +/* DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH2_M (DMA_OUT_LOOP_TEST_CH2_V << DMA_OUT_LOOP_TEST_CH2_S) +#define DMA_OUT_LOOP_TEST_CH2_V 0x00000001 +#define DMA_OUT_LOOP_TEST_CH2_S 1 + +/* DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + */ + +#define DMA_OUT_RST_CH2 (BIT(0)) +#define DMA_OUT_RST_CH2_M (DMA_OUT_RST_CH2_V << DMA_OUT_RST_CH2_S) +#define DMA_OUT_RST_CH2_V 0x00000001 +#define DMA_OUT_RST_CH2_S 0 + +/* DMA_OUT_CONF1_CH2_REG register + * DMA_OUT_CONF1_CH2_REG. + */ + +#define DMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) + +/* DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH2_M (DMA_OUT_CHECK_OWNER_CH2_V << DMA_OUT_CHECK_OWNER_CH2_S) +#define DMA_OUT_CHECK_OWNER_CH2_V 0x00000001 +#define DMA_OUT_CHECK_OWNER_CH2_S 12 + +/* DMA_OUTFIFO_STATUS_CH2_REG register + * DMA_OUTFIFO_STATUS_CH2_REG. + */ + +#define DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) + +/* DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH2_M (DMA_OUT_REMAIN_UNDER_4B_CH2_V << DMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define DMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/* DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH2_M (DMA_OUT_REMAIN_UNDER_3B_CH2_V << DMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_3B_CH2_S 25 + +/* DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH2_M (DMA_OUT_REMAIN_UNDER_2B_CH2_V << DMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_2B_CH2_S 24 + +/* DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH2_M (DMA_OUT_REMAIN_UNDER_1B_CH2_V << DMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_1B_CH2_S 23 + +/* DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx + * channel 2. + */ + +#define DMA_OUTFIFO_CNT_CH2 0x0000003F +#define DMA_OUTFIFO_CNT_CH2_M (DMA_OUTFIFO_CNT_CH2_V << DMA_OUTFIFO_CNT_CH2_S) +#define DMA_OUTFIFO_CNT_CH2_V 0x0000003F +#define DMA_OUTFIFO_CNT_CH2_S 2 + +/* DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ + +#define DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH2_M (DMA_OUTFIFO_EMPTY_CH2_V << DMA_OUTFIFO_EMPTY_CH2_S) +#define DMA_OUTFIFO_EMPTY_CH2_V 0x00000001 +#define DMA_OUTFIFO_EMPTY_CH2_S 1 + +/* DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ + +#define DMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH2_M (DMA_OUTFIFO_FULL_CH2_V << DMA_OUTFIFO_FULL_CH2_S) +#define DMA_OUTFIFO_FULL_CH2_V 0x00000001 +#define DMA_OUTFIFO_FULL_CH2_S 0 + +/* DMA_OUT_PUSH_CH2_REG register + * DMA_OUT_PUSH_CH2_REG. + */ + +#define DMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) + +/* DMA_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + +#define DMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH2_M (DMA_OUTFIFO_PUSH_CH2_V << DMA_OUTFIFO_PUSH_CH2_S) +#define DMA_OUTFIFO_PUSH_CH2_V 0x00000001 +#define DMA_OUTFIFO_PUSH_CH2_S 9 + +/* DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + +#define DMA_OUTFIFO_WDATA_CH2 0x000001FF +#define DMA_OUTFIFO_WDATA_CH2_M (DMA_OUTFIFO_WDATA_CH2_V << DMA_OUTFIFO_WDATA_CH2_S) +#define DMA_OUTFIFO_WDATA_CH2_V 0x000001FF +#define DMA_OUTFIFO_WDATA_CH2_S 0 + +/* DMA_OUT_LINK_CH2_REG register + * DMA_OUT_LINK_CH2_REG. + */ + +#define DMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) + +/* DMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink + * descriptor's FSM is working. + */ + +#define DMA_OUTLINK_PARK_CH2 (BIT(23)) +#define DMA_OUTLINK_PARK_CH2_M (DMA_OUTLINK_PARK_CH2_V << DMA_OUTLINK_PARK_CH2_S) +#define DMA_OUTLINK_PARK_CH2_V 0x00000001 +#define DMA_OUTLINK_PARK_CH2_S 23 + +/* DMA_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + +#define DMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH2_M (DMA_OUTLINK_RESTART_CH2_V << DMA_OUTLINK_RESTART_CH2_S) +#define DMA_OUTLINK_RESTART_CH2_V 0x00000001 +#define DMA_OUTLINK_RESTART_CH2_S 22 + +/* DMA_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_START_CH2 (BIT(21)) +#define DMA_OUTLINK_START_CH2_M (DMA_OUTLINK_START_CH2_V << DMA_OUTLINK_START_CH2_S) +#define DMA_OUTLINK_START_CH2_V 0x00000001 +#define DMA_OUTLINK_START_CH2_S 21 + +/* DMA_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_STOP_CH2 (BIT(20)) +#define DMA_OUTLINK_STOP_CH2_M (DMA_OUTLINK_STOP_CH2_V << DMA_OUTLINK_STOP_CH2_S) +#define DMA_OUTLINK_STOP_CH2_V 0x00000001 +#define DMA_OUTLINK_STOP_CH2_S 20 + +/* DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + +#define DMA_OUTLINK_ADDR_CH2 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH2_M (DMA_OUTLINK_ADDR_CH2_V << DMA_OUTLINK_ADDR_CH2_S) +#define DMA_OUTLINK_ADDR_CH2_V 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH2_S 0 + +/* DMA_OUT_STATE_CH2_REG register + * DMA_OUT_STATE_CH2_REG. + */ + +#define DMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) + +/* DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_OUT_STATE_CH2 0x00000007 +#define DMA_OUT_STATE_CH2_M (DMA_OUT_STATE_CH2_V << DMA_OUT_STATE_CH2_S) +#define DMA_OUT_STATE_CH2_V 0x00000007 +#define DMA_OUT_STATE_CH2_S 20 + +/* DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_OUT_DSCR_STATE_CH2 0x00000003 +#define DMA_OUT_DSCR_STATE_CH2_M (DMA_OUT_DSCR_STATE_CH2_V << DMA_OUT_DSCR_STATE_CH2_S) +#define DMA_OUT_DSCR_STATE_CH2_V 0x00000003 +#define DMA_OUT_DSCR_STATE_CH2_S 18 + +/* DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + +#define DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH2_M (DMA_OUTLINK_DSCR_ADDR_CH2_V << DMA_OUTLINK_DSCR_ADDR_CH2_S) +#define DMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH2_S 0 + +/* DMA_OUT_EOF_DES_ADDR_CH2_REG register + * DMA_OUT_EOF_DES_ADDR_CH2_REG. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) + +/* DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH2_M (DMA_OUT_EOF_DES_ADDR_CH2_V << DMA_OUT_EOF_DES_ADDR_CH2_S) +#define DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the + * last outlink descriptor. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_M (DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << DMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/* DMA_OUT_DSCR_CH2_REG register + * DMA_OUT_DSCR_CH2_REG. + */ + +#define DMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) + +/* DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + +#define DMA_OUTLINK_DSCR_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH2_M (DMA_OUTLINK_DSCR_CH2_V << DMA_OUTLINK_DSCR_CH2_S) +#define DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH2_S 0 + +/* DMA_OUT_DSCR_BF0_CH2_REG register + * DMA_OUT_DSCR_BF0_CH2_REG. + */ + +#define DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) + +/* DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + +#define DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH2_M (DMA_OUTLINK_DSCR_BF0_CH2_V << DMA_OUTLINK_DSCR_BF0_CH2_S) +#define DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/* DMA_OUT_DSCR_BF1_CH2_REG register + * DMA_OUT_DSCR_BF1_CH2_REG. + */ + +#define DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) + +/* DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH2_M (DMA_OUTLINK_DSCR_BF1_CH2_V << DMA_OUTLINK_DSCR_BF1_CH2_S) +#define DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/* DMA_OUT_PRI_CH2_REG register + * DMA_OUT_PRI_CH2_REG. + */ + +#define DMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) + +/* DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value, the higher of the + * priority. + */ + +#define DMA_TX_PRI_CH2 0x0000000F +#define DMA_TX_PRI_CH2_M (DMA_TX_PRI_CH2_V << DMA_TX_PRI_CH2_S) +#define DMA_TX_PRI_CH2_V 0x0000000F +#define DMA_TX_PRI_CH2_S 0 + +/* DMA_OUT_PERI_SEL_CH2_REG register + * DMA_OUT_PERI_SEL_CH2_REG. + */ + +#define DMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) + +/* DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_OUT_SEL_CH2 0x0000003F +#define DMA_PERI_OUT_SEL_CH2_M (DMA_PERI_OUT_SEL_CH2_V << DMA_PERI_OUT_SEL_CH2_S) +#define DMA_PERI_OUT_SEL_CH2_V 0x0000003F +#define DMA_PERI_OUT_SEL_CH2_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_efuse.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_efuse.h new file mode 100644 index 00000000000..ef92134a3d4 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_efuse.h @@ -0,0 +1,3282 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_EFUSE_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) + +/* EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_S 0 + +/* EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) + +/* EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_S 0 + +/* EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) + +/* EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_S 0 + +/* EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) + +/* EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_3 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_S 0 + +/* EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) + +/* EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_4 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_S 0 + +/* EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) + +/* EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_5 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_S 0 + +/* EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) + +/* EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_6 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_S 0 + +/* EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) + +/* EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_7 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_S 0 + +/* EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) + +/* EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_S 0 + +/* EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) + +/* EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_S 0 + +/* EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) + +/* EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_S 0 + +/* EFUSE_RD_WR_DIS_REG register + * Register 0 of BLOCK0. + */ + +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) + +/* EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disables programming of individual eFuses. + */ + +#define EFUSE_WR_DIS 0xFFFFFFFF +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFF +#define EFUSE_WR_DIS_S 0 + +/* EFUSE_RD_REPEAT_DATA0_REG register + * Register 1 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) + +/* EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Disables software reading from individual eFuse blocks (BLOCK4-10). + */ + +#define EFUSE_RD_DIS 0x0000007F +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007F +#define EFUSE_RD_DIS_S 0 + +/* EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001 +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 + +/* EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001 +#define EFUSE_DIS_ICACHE_S 8 + +/* EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + +#define EFUSE_DIS_DCACHE (BIT(9)) +#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) +#define EFUSE_DIS_DCACHE_V 0x00000001 +#define EFUSE_DIS_DCACHE_S 9 + +/* EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Disables Icache when SoC is in Download mode. + */ + +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 + +/* EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; + * Disables Dcache when SoC is in Download mode. + */ + +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 + +/* EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001 +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 + +/* EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ + +#define EFUSE_DIS_USB (BIT(13)) +#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) +#define EFUSE_DIS_USB_V 0x00000001 +#define EFUSE_DIS_USB_S 13 + +/* EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + +#define EFUSE_DIS_CAN (BIT(14)) +#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) +#define EFUSE_DIS_CAN_V 0x00000001 +#define EFUSE_DIS_CAN_S 14 + +/* EFUSE_DIS_BOOT_REMAP : RO; bitpos: [15]; default: 0; + * Disables capability to Remap RAM to ROM address space. + */ + +#define EFUSE_DIS_BOOT_REMAP (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_M (EFUSE_DIS_BOOT_REMAP_V << EFUSE_DIS_BOOT_REMAP_S) +#define EFUSE_DIS_BOOT_REMAP_V 0x00000001 +#define EFUSE_DIS_BOOT_REMAP_S 15 + +/* EFUSE_DIS_EFUSE_ATE_WR : RO; bitpos: [16]; default: 0; */ + +#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_M (EFUSE_DIS_EFUSE_ATE_WR_V << EFUSE_DIS_EFUSE_ATE_WR_S) +#define EFUSE_DIS_EFUSE_ATE_WR_V 0x00000001 +#define EFUSE_DIS_EFUSE_ATE_WR_S 16 + +/* EFUSE_SOFT_DIS_JTAG : RO; bitpos: [17]; default: 0; + * Software disables JTAG. When software disabled, JTAG can be activated + * temporarily by HMAC peripheral. + */ + +#define EFUSE_SOFT_DIS_JTAG (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000001 +#define EFUSE_SOFT_DIS_JTAG_S 17 + +/* EFUSE_HARD_DIS_JTAG : RO; bitpos: [18]; default: 0; + * Hardware disables JTAG permanently. + */ + +#define EFUSE_HARD_DIS_JTAG (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_M (EFUSE_HARD_DIS_JTAG_V << EFUSE_HARD_DIS_JTAG_S) +#define EFUSE_HARD_DIS_JTAG_V 0x00000001 +#define EFUSE_HARD_DIS_JTAG_S 18 + +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [19]; default: 0; + * Disables flash encryption when in download boot modes. + */ + +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 + +/* EFUSE_USB_DREFH : RO; bitpos: [21:20]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 + * mV, stored in eFuse. + */ + +#define EFUSE_USB_DREFH 0x00000003 +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003 +#define EFUSE_USB_DREFH_S 20 + +/* EFUSE_USB_DREFL : RO; bitpos: [23:22]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of + * 80 mV, stored in eFuse. + */ + +#define EFUSE_USB_DREFL 0x00000003 +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003 +#define EFUSE_USB_DREFL_S 22 + +/* EFUSE_USB_EXCHG_PINS : RO; bitpos: [24]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + +#define EFUSE_USB_EXCHG_PINS (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001 +#define EFUSE_USB_EXCHG_PINS_S 24 + +/* EFUSE_EXT_PHY_ENABLE : RO; bitpos: [25]; default: 0; + * Set this bit to enable external USB PHY. + */ + +#define EFUSE_EXT_PHY_ENABLE (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_M (EFUSE_EXT_PHY_ENABLE_V << EFUSE_EXT_PHY_ENABLE_S) +#define EFUSE_EXT_PHY_ENABLE_V 0x00000001 +#define EFUSE_EXT_PHY_ENABLE_S 25 + +/* EFUSE_USB_FORCE_NOPERSIST : RO; bitpos: [26]; default: 0; + * If set, forces USB BVALID to 1. + */ + +#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_M (EFUSE_USB_FORCE_NOPERSIST_V << EFUSE_USB_FORCE_NOPERSIST_S) +#define EFUSE_USB_FORCE_NOPERSIST_V 0x00000001 +#define EFUSE_USB_FORCE_NOPERSIST_S 26 + +/* EFUSE_RPT4_RESERVED0 : RO; bitpos: [28:27]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED0 0x00000003 +#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) +#define EFUSE_RPT4_RESERVED0_V 0x00000003 +#define EFUSE_RPT4_RESERVED0_S 27 + +/* EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001 +#define EFUSE_VDD_SPI_MODECURLIM_S 29 + +/* EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFH 0x00000003 +#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) +#define EFUSE_VDD_SPI_DREFH_V 0x00000003 +#define EFUSE_VDD_SPI_DREFH_S 30 + +/* EFUSE_RD_REPEAT_DATA1_REG register + * Register 2 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) + +/* EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFM 0x00000003 +#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) +#define EFUSE_VDD_SPI_DREFM_V 0x00000003 +#define EFUSE_VDD_SPI_DREFM_S 0 + +/* EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFL 0x00000003 +#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) +#define EFUSE_VDD_SPI_DREFL_V 0x00000003 +#define EFUSE_VDD_SPI_DREFL_S 2 + +/* EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; + * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is + * powered on. + */ + +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) +#define EFUSE_VDD_SPI_XPD_V 0x00000001 +#define EFUSE_VDD_SPI_XPD_S 4 + +/* EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; + * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to + * 1.8 V LDO; 1: VDD_SPI connects to VDD_RTC_IO. + */ + +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) +#define EFUSE_VDD_SPI_TIEH_V 0x00000001 +#define EFUSE_VDD_SPI_TIEH_S 5 + +/* EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; + * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI + * LDO. + */ + +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) +#define EFUSE_VDD_SPI_FORCE_V 0x00000001 +#define EFUSE_VDD_SPI_FORCE_S 6 + +/* EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) +#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001 +#define EFUSE_VDD_SPI_EN_INIT_S 7 + +/* EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001 +#define EFUSE_VDD_SPI_ENCURLIM_S 8 + +/* EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 + * mA/(8+d). + */ + +#define EFUSE_VDD_SPI_DCURLIM 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) +#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_S 9 + +/* EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance; 1: 6 K; 2: 4 + * K; 3: 2 K. + */ + +#define EFUSE_VDD_SPI_INIT 0x00000003 +#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) +#define EFUSE_VDD_SPI_INIT_V 0x00000003 +#define EFUSE_VDD_SPI_INIT_S 12 + +/* EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + +#define EFUSE_VDD_SPI_DCAP 0x00000003 +#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) +#define EFUSE_VDD_SPI_DCAP_V 0x00000003 +#define EFUSE_VDD_SPI_DCAP_S 14 + +/* EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock + * cycles; 1: 80,000 slow clock cycles; 2: 160,000 slow clock cycles; 3: + * 320,000 slow clock cycles. + */ + +#define EFUSE_WDT_DELAY_SEL 0x00000003 +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003 +#define EFUSE_WDT_DELAY_SEL_S 16 + +/* EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Enables encryption and decryption, when an SPI boot mode is set. Feature + * is enabled 1 or 3 bits are set in the eFuse, disabled otherwise. + */ + +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * If set, revokes use of secure boot key digest 0. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * If set, revokes use of secure boot key digest 1. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * If set, revokes use of secure boot key digest 2. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 + +/* EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of KEY0. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_0 0x0000000F +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000F +#define EFUSE_KEY_PURPOSE_0_S 24 + +/* EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of KEY1. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_1 0x0000000F +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000F +#define EFUSE_KEY_PURPOSE_1_S 28 + +/* EFUSE_RD_REPEAT_DATA2_REG register + * Register 3 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) + +/* EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of KEY2. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_2 0x0000000F +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000F +#define EFUSE_KEY_PURPOSE_2_S 0 + +/* EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of KEY3. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_3 0x0000000F +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000F +#define EFUSE_KEY_PURPOSE_3_S 4 + +/* EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of KEY4. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_4 0x0000000F +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000F +#define EFUSE_KEY_PURPOSE_4_S 8 + +/* EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of KEY5. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_5 0x0000000F +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000F +#define EFUSE_KEY_PURPOSE_5_S 12 + +/* EFUSE_KEY_PURPOSE_6 : RO; bitpos: [19:16]; default: 0; + * Purpose of KEY6. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_6 0x0000000F +#define EFUSE_KEY_PURPOSE_6_M (EFUSE_KEY_PURPOSE_6_V << EFUSE_KEY_PURPOSE_6_S) +#define EFUSE_KEY_PURPOSE_6_V 0x0000000F +#define EFUSE_KEY_PURPOSE_6_S 16 + +/* EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001 +#define EFUSE_SECURE_BOOT_EN_S 20 + +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable aggressive secure boot key revocation mode. + */ + +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 + +/* EFUSE_RPT4_RESERVED1 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED1 0x0000003F +#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) +#define EFUSE_RPT4_RESERVED1_V 0x0000003F +#define EFUSE_RPT4_RESERVED1_S 22 + +/* EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash startup delay after SoC power-up, in unit of (ms/2). + * When the value is 15, delay is 7.5 ms. + */ + +#define EFUSE_FLASH_TPUW 0x0000000F +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000F +#define EFUSE_FLASH_TPUW_S 28 + +/* EFUSE_RD_REPEAT_DATA3_REG register + * Register 4 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) + +/* EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable all download boot modes. + */ + +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 + +/* EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; + * Set this bit to disable Legacy SPI boot mode. + */ + +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001 +#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 + +/* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; + * Selects the default UART for printing boot messages. 0: UART0; 1: UART1. + */ + +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) +#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001 +#define EFUSE_UART_PRINT_CHANNEL_S 2 + +/* EFUSE_RPT4_RESERVED3 : RO; bitpos: [3]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED3 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) +#define EFUSE_RPT4_RESERVED3_V 0x00000001 +#define EFUSE_RPT4_RESERVED3_S 3 + +/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Set this bit to disable use of USB in UART download boot mode. + */ + +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 + +/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode (read/write flash only). + */ + +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 + +/* EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UART boot message output mode. + * & + * 00: Enabled.# + * 01: Enable when GPIO46 is low at reset.# + * 10: Enable when GPIO46 is high at reset.# + * 11: Disabled. + * & + */ + +#define EFUSE_UART_PRINT_CONTROL 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_S 6 + +/* EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * Set default power supply for GPIO33-GPIO37, set when SPI flash is + * initialized. 0: VDD3P3_CPU; 1: VDD_SPI. + */ + +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001 +#define EFUSE_PIN_POWER_SELECTION_S 8 + +/* EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * SPI flash type. 0: maximum four data lines, 1: eight data lines. + */ + +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001 +#define EFUSE_FLASH_TYPE_S 9 + +/* EFUSE_FORCE_SEND_RESUME : RO; bitpos: [10]; default: 0; + * If set, forces ROM code to send an SPI flash resume command during SPI + * boot. + */ + +#define EFUSE_FORCE_SEND_RESUME (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001 +#define EFUSE_FORCE_SEND_RESUME_S 10 + +/* EFUSE_SECURE_VERSION : RO; bitpos: [26:11]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + +#define EFUSE_SECURE_VERSION 0x0000FFFF +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFF +#define EFUSE_SECURE_VERSION_S 11 + +/* EFUSE_RPT4_RESERVED2 : RO; bitpos: [31:27]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED2 0x0000001F +#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) +#define EFUSE_RPT4_RESERVED2_V 0x0000001F +#define EFUSE_RPT4_RESERVED2_S 27 + +/* EFUSE_RD_REPEAT_DATA4_REG register + * Register 5 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) + +/* EFUSE_RPT4_RESERVED4 : RO; bitpos: [23:0]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED4 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_M (EFUSE_RPT4_RESERVED4_V << EFUSE_RPT4_RESERVED4_S) +#define EFUSE_RPT4_RESERVED4_V 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_0_REG register + * Register 0 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) + +/* EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + +#define EFUSE_MAC_0 0xFFFFFFFF +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFF +#define EFUSE_MAC_0_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_1_REG register + * Register 1 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) + +/* EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + +#define EFUSE_MAC_1 0x0000FFFF +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFF +#define EFUSE_MAC_1_S 0 + +/* EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0; + * Stores the zeroth part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S) +#define EFUSE_SPI_PAD_CONF_0_V 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_S 16 + +/* EFUSE_RD_MAC_SPI_SYS_2_REG register + * Register 2 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) + +/* EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) +#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_3_REG register + * Register 3 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) + +/* EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; + * Stores the second part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) +#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 + +/* EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the zeroth part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_0 0x00003FFF +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFF +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/* EFUSE_RD_MAC_SPI_SYS_4_REG register + * Register 4 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) + +/* EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the fist part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_5_REG register + * Register 5 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) + +/* EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_0_REG register + * Register 0 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_0_REG (DR_REG_EFUSE_BASE + 0x5c) + +/* EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_1_REG register + * Register 1 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_1_REG (DR_REG_EFUSE_BASE + 0x60) + +/* EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_2_REG register + * Register 2 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_2_REG (DR_REG_EFUSE_BASE + 0x64) + +/* EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_3_REG register + * Register 3 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_3_REG (DR_REG_EFUSE_BASE + 0x68) + +/* EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_4_REG register + * Register 4 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_4_REG (DR_REG_EFUSE_BASE + 0x6c) + +/* EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_5_REG register + * Register 5 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_5_REG (DR_REG_EFUSE_BASE + 0x70) + +/* EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_6_REG register + * Register 6 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_6_REG (DR_REG_EFUSE_BASE + 0x74) + +/* EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_7_REG register + * Register 7 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_7_REG (DR_REG_EFUSE_BASE + 0x78) + +/* EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/* EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) + +/* EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA0 0xFFFFFFFF +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFF +#define EFUSE_USR_DATA0_S 0 + +/* EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) + +/* EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA1 0xFFFFFFFF +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFF +#define EFUSE_USR_DATA1_S 0 + +/* EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) + +/* EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA2 0xFFFFFFFF +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFF +#define EFUSE_USR_DATA2_S 0 + +/* EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) + +/* EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA3 0xFFFFFFFF +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFF +#define EFUSE_USR_DATA3_S 0 + +/* EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) + +/* EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA4 0xFFFFFFFF +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFF +#define EFUSE_USR_DATA4_S 0 + +/* EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) + +/* EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA5 0xFFFFFFFF +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFF +#define EFUSE_USR_DATA5_S 0 + +/* EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) + +/* EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA6 0xFFFFFFFF +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFF +#define EFUSE_USR_DATA6_S 0 + +/* EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) + +/* EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA7 0xFFFFFFFF +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFF +#define EFUSE_USR_DATA7_S 0 + +/* EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) + +/* EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA0 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_S 0 + +/* EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) + +/* EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA1 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_S 0 + +/* EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) + +/* EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA2 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_S 0 + +/* EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) + +/* EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA3 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_S 0 + +/* EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) + +/* EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA4 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_S 0 + +/* EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) + +/* EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA5 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_S 0 + +/* EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) + +/* EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA6 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_S 0 + +/* EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) + +/* EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA7 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_S 0 + +/* EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) + +/* EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA0 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_S 0 + +/* EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) + +/* EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA1 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_S 0 + +/* EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) + +/* EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA2 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_S 0 + +/* EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) + +/* EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA3 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_S 0 + +/* EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) + +/* EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA4 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_S 0 + +/* EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) + +/* EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA5 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_S 0 + +/* EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) + +/* EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA6 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_S 0 + +/* EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) + +/* EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA7 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_S 0 + +/* EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) + +/* EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA0 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_S 0 + +/* EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) + +/* EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA1 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_S 0 + +/* EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) + +/* EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA2 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_S 0 + +/* EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) + +/* EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA3 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_S 0 + +/* EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) + +/* EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA4 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_S 0 + +/* EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) + +/* EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA5 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_S 0 + +/* EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) + +/* EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA6 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_S 0 + +/* EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) + +/* EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA7 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_S 0 + +/* EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) + +/* EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA0 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_S 0 + +/* EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) + +/* EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA1 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_S 0 + +/* EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) + +/* EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA2 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_S 0 + +/* EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) + +/* EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA3 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_S 0 + +/* EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) + +/* EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA4 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_S 0 + +/* EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) + +/* EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA5 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_S 0 + +/* EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) + +/* EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA6 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_S 0 + +/* EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) + +/* EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA7 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_S 0 + +/* EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) + +/* EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA0 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_S 0 + +/* EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) + +/* EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA1 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_S 0 + +/* EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) + +/* EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA2 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_S 0 + +/* EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) + +/* EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA3 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_S 0 + +/* EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) + +/* EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA4 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_S 0 + +/* EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) + +/* EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA5 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_S 0 + +/* EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) + +/* EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA6 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_S 0 + +/* EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) + +/* EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA7 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_S 0 + +/* EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) + +/* EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA0 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_S 0 + +/* EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) + +/* EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA1 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_S 0 + +/* EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) + +/* EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA2 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_S 0 + +/* EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) + +/* EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA3 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_S 0 + +/* EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) + +/* EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA4 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_S 0 + +/* EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) + +/* EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA5 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_S 0 + +/* EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) + +/* EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA6 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_S 0 + +/* EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) + +/* EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA7 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_0_REG register + * Register 0 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_0_REG (DR_REG_EFUSE_BASE + 0x15c) + +/* EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_1_REG register + * Register 1 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_1_REG (DR_REG_EFUSE_BASE + 0x160) + +/* EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_2_REG register + * Register 2 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_2_REG (DR_REG_EFUSE_BASE + 0x164) + +/* EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_3_REG register + * Register 3 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_3_REG (DR_REG_EFUSE_BASE + 0x168) + +/* EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_4_REG register + * Register 4 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_4_REG (DR_REG_EFUSE_BASE + 0x16c) + +/* EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_5_REG register + * Register 5 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_5_REG (DR_REG_EFUSE_BASE + 0x170) + +/* EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_6_REG register + * Register 6 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_6_REG (DR_REG_EFUSE_BASE + 0x174) + +/* EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_7_REG register + * Register 7 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_7_REG (DR_REG_EFUSE_BASE + 0x178) + +/* EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/* EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) + +/* EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RD_DIS. + */ + +#define EFUSE_RD_DIS_ERR 0x0000007F +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007F +#define EFUSE_RD_DIS_ERR_S 0 + +/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_RTC_RAM_BOOT. + */ + +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001 +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 + +/* EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_ICACHE. + */ + +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001 +#define EFUSE_DIS_ICACHE_ERR_S 8 + +/* EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DCACHE. + */ + +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) +#define EFUSE_DIS_DCACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DCACHE_ERR_S 9 + +/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_ICACHE. + */ + +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 + +/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_DCACHE. + */ + +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 + +/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_FORCE_DOWNLOAD. + */ + +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001 +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 + +/* EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_USB. + */ + +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) +#define EFUSE_DIS_USB_ERR_V 0x00000001 +#define EFUSE_DIS_USB_ERR_S 13 + +/* EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_CAN. + */ + +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001 +#define EFUSE_DIS_CAN_ERR_S 14 + +/* EFUSE_DIS_BOOT_REMAP_ERR : RO; bitpos: [15]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_BOOT_REMAP. + */ + +#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_ERR_M (EFUSE_DIS_BOOT_REMAP_ERR_V << EFUSE_DIS_BOOT_REMAP_ERR_S) +#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x00000001 +#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 + +/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO; bitpos: [16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_EFUSE_ATE_WR. + */ + +#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (EFUSE_DIS_EFUSE_ATE_WR_ERR_V << EFUSE_DIS_EFUSE_ATE_WR_ERR_S) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x00000001 +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 + +/* EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [17]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SOFT_DIS_JTAG. + */ + +#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000001 +#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 + +/* EFUSE_HARD_DIS_JTAG_ERR : RO; bitpos: [18]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_HARD_DIS_JTAG. + */ + +#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_ERR_M (EFUSE_HARD_DIS_JTAG_ERR_V << EFUSE_HARD_DIS_JTAG_ERR_S) +#define EFUSE_HARD_DIS_JTAG_ERR_V 0x00000001 +#define EFUSE_HARD_DIS_JTAG_ERR_S 18 + +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [19]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 + +/* EFUSE_USB_DREFH_ERR : RO; bitpos: [21:20]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_DREFH. + */ + +#define EFUSE_USB_DREFH_ERR 0x00000003 +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003 +#define EFUSE_USB_DREFH_ERR_S 20 + +/* EFUSE_USB_DREFL_ERR : RO; bitpos: [23:22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_DREFL. + */ + +#define EFUSE_USB_DREFL_ERR 0x00000003 +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003 +#define EFUSE_USB_DREFL_ERR_S 22 + +/* EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [24]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_EXCHG_PINS. + */ + +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001 +#define EFUSE_USB_EXCHG_PINS_ERR_S 24 + +/* EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [25]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_EXT_PHY_ENABLE. + */ + +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001 +#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 + +/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO; bitpos: [26]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_FORCE_NOPERSIST. + */ + +#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (EFUSE_USB_FORCE_NOPERSIST_ERR_V << EFUSE_USB_FORCE_NOPERSIST_ERR_S) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x00000001 +#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 + +/* EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [28:27]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED0. + */ + +#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_S 27 + +/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_MODECURLIM. + */ + +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 + +/* EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFH. + */ + +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 + +/* EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) + +/* EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFM. + */ + +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_S 0 + +/* EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFL. + */ + +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 + +/* EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_XPD. + */ + +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_XPD_ERR_S 4 + +/* EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_TIEH. + */ + +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 + +/* EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_FORCE. + */ + +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 + +/* EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_EN_INIT. + */ + +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 + +/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_ENCURLIM. + */ + +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 + +/* EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DCURLIM. + */ + +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 + +/* EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_INIT. + */ + +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_S 12 + +/* EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DCAP. + */ + +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 + +/* EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_WDT_DELAY_SEL. + */ + +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 + +/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SPI_BOOT_CRYPT_CNT. + */ + +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE0. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE1. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE2. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 + +/* EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_0. + */ + +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 + +/* EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_1. + */ + +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 + +/* EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) + +/* EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_2. + */ + +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 + +/* EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_3. + */ + +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 + +/* EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_4. + */ + +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 + +/* EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_5. + */ + +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 + +/* EFUSE_KEY_PURPOSE_6_ERR : RO; bitpos: [19:16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_6. + */ + +#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_M (EFUSE_KEY_PURPOSE_6_ERR_V << EFUSE_KEY_PURPOSE_6_ERR_S) +#define EFUSE_KEY_PURPOSE_6_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_S 16 + +/* EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_EN. + */ + +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 + +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 + +/* EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [27:22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED1. + */ + +#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_S 22 + +/* EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FLASH_TPUW. + */ + +#define EFUSE_FLASH_TPUW_ERR 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/* EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) + +/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_MODE. + */ + +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 + +/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_LEGACY_SPI_BOOT. + */ + +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001 +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 + +/* EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_UART_PRINT_CHANNEL. + */ + +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001 +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 + +/* EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [3]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED3. + */ + +#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x00000001 +#define EFUSE_RPT4_RESERVED3_ERR_S 3 + +/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_USB_DOWNLOAD_MODE. + */ + +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 + +/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_ENABLE_SECURITY_DOWNLOAD. + */ + +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 + +/* EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_UART_PRINT_CONTROL. + */ + +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 + +/* EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_PIN_POWER_SELECTION. + */ + +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001 +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 + +/* EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FLASH_TYPE. + */ + +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001 +#define EFUSE_FLASH_TYPE_ERR_S 9 + +/* EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [10]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FORCE_SEND_RESUME. + */ + +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001 +#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 + +/* EFUSE_SECURE_VERSION_ERR : RO; bitpos: [26:11]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_VERSION. + */ + +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_S 11 + +/* EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [31:27]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED2. + */ + +#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_S 27 + +/* EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) + +/* EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED4. + */ + +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) +#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_S 0 + +/* EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ + +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) + +/* EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in BLOCK1. + */ + +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 + +/* EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of BLOCK1 is reliable; 1: Means + * that programming BLOCK1 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001 +#define EFUSE_MAC_SPI_8M_FAIL_S 3 + +/* EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK2. + */ + +#define EFUSE_SYS_PART1_NUM 0x00000007 +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007 +#define EFUSE_SYS_PART1_NUM_S 4 + +/* EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK2 is reliable; 1: Means + * that programming BLOCK2 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001 +#define EFUSE_SYS_PART1_FAIL_S 7 + +/* EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in BLOCK3. + */ + +#define EFUSE_USR_DATA_ERR_NUM 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_S 8 + +/* EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the data of BLOCK3 is reliable; 1: Means + * that programming BLOCK3 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001 +#define EFUSE_USR_DATA_FAIL_S 11 + +/* EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes in KEY0. + */ + +#define EFUSE_KEY0_ERR_NUM 0x00000007 +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007 +#define EFUSE_KEY0_ERR_NUM_S 12 + +/* EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of KEY0 is reliable; 1: Means that + * programming KEY0 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001 +#define EFUSE_KEY0_FAIL_S 15 + +/* EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes in KEY1. + */ + +#define EFUSE_KEY1_ERR_NUM 0x00000007 +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007 +#define EFUSE_KEY1_ERR_NUM_S 16 + +/* EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of KEY1 is reliable; 1: Means that + * programming KEY1 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001 +#define EFUSE_KEY1_FAIL_S 19 + +/* EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes in KEY2. + */ + +#define EFUSE_KEY2_ERR_NUM 0x00000007 +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007 +#define EFUSE_KEY2_ERR_NUM_S 20 + +/* EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of KEY2 is reliable; 1: Means that + * programming KEY2 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001 +#define EFUSE_KEY2_FAIL_S 23 + +/* EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes in KEY3. + */ + +#define EFUSE_KEY3_ERR_NUM 0x00000007 +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007 +#define EFUSE_KEY3_ERR_NUM_S 24 + +/* EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of KEY3 is reliable; 1: Means that + * programming KEY3 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001 +#define EFUSE_KEY3_FAIL_S 27 + +/* EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes in KEY4. + */ + +#define EFUSE_KEY4_ERR_NUM 0x00000007 +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007 +#define EFUSE_KEY4_ERR_NUM_S 28 + +/* EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of KEY4 is reliable; 1: Means that + * programming KEY4 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001 +#define EFUSE_KEY4_FAIL_S 31 + +/* EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ + +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) + +/* EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in KEY5. + */ + +#define EFUSE_KEY5_ERR_NUM 0x00000007 +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007 +#define EFUSE_KEY5_ERR_NUM_S 0 + +/* EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable; 1: Means that + * programming user data failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001 +#define EFUSE_KEY5_FAIL_S 3 + +/* EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK10. + */ + +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_S 4 + +/* EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK10 is reliable; 1: Means + * that programming BLOCK10 data failed and the number of error bytes is + * over 5. + */ + +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001 +#define EFUSE_SYS_PART2_FAIL_S 7 + +/* EFUSE_CLK_REG register + * eFuse clock configuration register. + */ + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) + +/* EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * If set, forces eFuse SRAM into power-saving mode. + */ + +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001 +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 + +/* EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * If set, forces to activate clock signal of eFuse SRAM. + */ + +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001 +#define EFUSE_MEM_CLK_FORCE_ON_S 1 + +/* EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * If set, forces eFuse SRAM into working mode. + */ + +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001 +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 + +/* EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * If set, forces to enable clock signal of eFuse memory. + */ + +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001 +#define EFUSE_CLK_EN_S 16 + +/* EFUSE_CONF_REG register + * eFuse operation mode configuration register. + */ + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) + +/* EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command; 0x5AA5: Operate read command. + */ + +#define EFUSE_OP_CODE 0x0000FFFF +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFF +#define EFUSE_OP_CODE_S 0 + +/* EFUSE_STATUS_REG register + * eFuse status register. + */ + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) + +/* EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + +#define EFUSE_STATE 0x0000000F +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000F +#define EFUSE_STATE_S 0 + +/* EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001 +#define EFUSE_OTP_LOAD_SW_S 4 + +/* EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001 +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 + +/* EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001 +#define EFUSE_OTP_STROBE_SW_S 6 + +/* EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001 +#define EFUSE_OTP_CSB_SW_S 7 + +/* EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001 +#define EFUSE_OTP_PGENB_SW_S 8 + +/* EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001 +#define EFUSE_OTP_VDDQ_IS_SW_S 9 + +/* EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + +#define EFUSE_REPEAT_ERR_CNT 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_S 10 + +/* EFUSE_CMD_REG register + * eFuse command register. + */ + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) + +/* EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001 +#define EFUSE_READ_CMD_S 0 + +/* EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001 +#define EFUSE_PGM_CMD_S 1 + +/* EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. + */ + +#define EFUSE_BLK_NUM 0x0000000F +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000F +#define EFUSE_BLK_NUM_S 2 + +/* EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) + +/* EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +/* EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/* EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) + +/* EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001 +#define EFUSE_READ_DONE_INT_ST_S 0 + +/* EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/* EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) + +/* EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +/* EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/* EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) + +/* EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +/* EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/* EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) + +/* EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming + * voltage. + */ + +#define EFUSE_DAC_CLK_DIV 0x000000FF +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FF +#define EFUSE_DAC_CLK_DIV_S 0 + +/* EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 + +/* EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + +#define EFUSE_DAC_NUM 0x000000FF +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FF +#define EFUSE_DAC_NUM_S 9 + +/* EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001 +#define EFUSE_OE_CLR_S 17 + +/* EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ + +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) + +/* EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of read operation. + */ + +#define EFUSE_THR_A 0x000000FF +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FF +#define EFUSE_THR_A_S 0 + +/* EFUSE_TRD : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse of read operation. + */ + +#define EFUSE_TRD 0x000000FF +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FF +#define EFUSE_TRD_S 8 + +/* EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the setup time of read operation. + */ + +#define EFUSE_TSUR_A 0x000000FF +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FF +#define EFUSE_TSUR_A_S 16 + +/* EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + +#define EFUSE_READ_INIT_NUM 0x000000FF +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FF +#define EFUSE_READ_INIT_NUM_S 24 + +/* EFUSE_WR_TIM_CONF0_REG register + * Configuration register 0 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) + +/* EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of programming operation. + */ + +#define EFUSE_THP_A 0x000000FF +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FF +#define EFUSE_THP_A_S 0 + +/* EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse during programming 0 to eFuse. + */ + +#define EFUSE_TPGM_INACTIVE 0x000000FF +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FF +#define EFUSE_TPGM_INACTIVE_S 8 + +/* EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures the length of pulse during programming 1 to eFuse. + */ + +#define EFUSE_TPGM 0x0000FFFF +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFF +#define EFUSE_TPGM_S 16 + +/* EFUSE_WR_TIM_CONF1_REG register + * Configuration register 1 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) + +/* EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the setup time of programming operation. + */ + +#define EFUSE_TSUP_A 0x000000FF +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FF +#define EFUSE_TSUP_A_S 0 + +/* EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + +#define EFUSE_PWR_ON_NUM 0x0000FFFF +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFF +#define EFUSE_PWR_ON_NUM_S 8 + +/* EFUSE_WR_TIM_CONF2_REG register + * Configuration register 2 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) + +/* EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + +#define EFUSE_PWR_OFF_NUM 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_S 0 + +/* EFUSE_DATE_REG register + * eFuse version register. + */ + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) + +/* EFUSE_EFUSE_DATE : R/W; bitpos: [31:0]; default: 419959040; + * Stores eFuse version. + */ + +#define EFUSE_EFUSE_DATE 0xFFFFFFFF +#define EFUSE_EFUSE_DATE_M (EFUSE_EFUSE_DATE_V << EFUSE_EFUSE_DATE_S) +#define EFUSE_EFUSE_DATE_V 0xFFFFFFFF +#define EFUSE_EFUSE_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_EFUSE_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h index d05c9dafc61..588ed1bd7b4 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32c3_soc.h" +#include "esp32c3_soc.h" /**************************************************************************** * Pre-preprocessor Definitions diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h index ce40a865b88..675a584e4c3 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32c3_soc.h" +#include "esp32c3_soc.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h new file mode 100644 index 00000000000..6b8846b75be --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h @@ -0,0 +1,2742 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ + +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) + +/* LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 0. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH0 0x00000003 +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003 +#define LEDC_TIMER_SEL_CH0_S 0 + +/* LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 0. + */ + +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH0_S 2 + +/* LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 0 is inactive. + */ + +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001 +#define LEDC_IDLE_LV_CH0_S 3 + +/* LEDC_PARA_UP_CH0 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH0_HPOINT and LEDC_CH0_DUTY for + * channel 0. + */ + +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001 +#define LEDC_PARA_UP_CH0_S 4 + +/* LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH0_INT interrupt will be triggered when channel 0 + * overflows for (LEDC_OVF_NUM_CH0 + 1) times. + */ + +#define LEDC_OVF_NUM_CH0 0x000003FF +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FF +#define LEDC_OVF_NUM_CH0_S 5 + +/* LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 0. + */ + +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH0_S 15 + +/* LEDC_OVF_CNT_RESET_CH0 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 0. + */ + +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH0 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH0. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH0 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH0_M (LEDC_OVF_CNT_RESET_ST_CH0_V << LEDC_OVF_CNT_RESET_ST_CH0_S) +#define LEDC_OVF_CNT_RESET_ST_CH0_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH0_S 17 + +/* LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ + +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) + +/* LEDC_HPOINT_CH0 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH0 0x00003FFF +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x00003FFF +#define LEDC_HPOINT_CH0_S 0 + +/* LEDC_CH0_DUTY_REG register + * Initial duty cycle for channel 0 + */ + +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) + +/* LEDC_DUTY_CH0 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH0 0x0007FFFF +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x0007FFFF +#define LEDC_DUTY_CH0_S 0 + +/* LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ + +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) + +/* LEDC_DUTY_SCALE_CH0 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 0. + */ + +#define LEDC_DUTY_SCALE_CH0 0x000003FF +#define LEDC_DUTY_SCALE_CH0_M (LEDC_DUTY_SCALE_CH0_V << LEDC_DUTY_SCALE_CH0_S) +#define LEDC_DUTY_SCALE_CH0_V 0x000003FF +#define LEDC_DUTY_SCALE_CH0_S 0 + +/* LEDC_DUTY_CYCLE_CH0 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH0 on channel 0. + */ + +#define LEDC_DUTY_CYCLE_CH0 0x000003FF +#define LEDC_DUTY_CYCLE_CH0_M (LEDC_DUTY_CYCLE_CH0_V << LEDC_DUTY_CYCLE_CH0_S) +#define LEDC_DUTY_CYCLE_CH0_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH0_S 10 + +/* LEDC_DUTY_NUM_CH0 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH0 0x000003FF +#define LEDC_DUTY_NUM_CH0_M (LEDC_DUTY_NUM_CH0_V << LEDC_DUTY_NUM_CH0_S) +#define LEDC_DUTY_NUM_CH0_V 0x000003FF +#define LEDC_DUTY_NUM_CH0_S 20 + +/* LEDC_DUTY_INC_CH0 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 0. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH0 (BIT(30)) +#define LEDC_DUTY_INC_CH0_M (LEDC_DUTY_INC_CH0_V << LEDC_DUTY_INC_CH0_S) +#define LEDC_DUTY_INC_CH0_V 0x00000001 +#define LEDC_DUTY_INC_CH0_S 30 + +/* LEDC_DUTY_START_CH0 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH0_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001 +#define LEDC_DUTY_START_CH0_S 31 + +/* LEDC_CH0_DUTY_R_REG register + * Current duty cycle for channel 0 + */ + +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) + +/* LEDC_DUTY_R_CH0 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 0. + */ + +#define LEDC_DUTY_R_CH0 0x0007FFFF +#define LEDC_DUTY_R_CH0_M (LEDC_DUTY_R_CH0_V << LEDC_DUTY_R_CH0_S) +#define LEDC_DUTY_R_CH0_V 0x0007FFFF +#define LEDC_DUTY_R_CH0_S 0 + +/* LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ + +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) + +/* LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 1. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH1 0x00000003 +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003 +#define LEDC_TIMER_SEL_CH1_S 0 + +/* LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 1. + */ + +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH1_S 2 + +/* LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 1 is inactive. + */ + +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001 +#define LEDC_IDLE_LV_CH1_S 3 + +/* LEDC_PARA_UP_CH1 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH1_HPOINT and LEDC_CH1_DUTY for + * channel 1. + */ + +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001 +#define LEDC_PARA_UP_CH1_S 4 + +/* LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH1_INT interrupt will be triggered when channel 1 + * overflows for (LEDC_OVF_NUM_CH1 + 1) times. + */ + +#define LEDC_OVF_NUM_CH1 0x000003FF +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FF +#define LEDC_OVF_NUM_CH1_S 5 + +/* LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 1. + */ + +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH1_S 15 + +/* LEDC_OVF_CNT_RESET_CH1 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 1. + */ + +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH1 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH1. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH1 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH1_M (LEDC_OVF_CNT_RESET_ST_CH1_V << LEDC_OVF_CNT_RESET_ST_CH1_S) +#define LEDC_OVF_CNT_RESET_ST_CH1_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH1_S 17 + +/* LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ + +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) + +/* LEDC_HPOINT_CH1 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH1 0x00003FFF +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x00003FFF +#define LEDC_HPOINT_CH1_S 0 + +/* LEDC_CH1_DUTY_REG register + * Initial duty cycle for channel 1 + */ + +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) + +/* LEDC_DUTY_CH1 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH1 0x0007FFFF +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x0007FFFF +#define LEDC_DUTY_CH1_S 0 + +/* LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ + +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) + +/* LEDC_DUTY_SCALE_CH1 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 1. + */ + +#define LEDC_DUTY_SCALE_CH1 0x000003FF +#define LEDC_DUTY_SCALE_CH1_M (LEDC_DUTY_SCALE_CH1_V << LEDC_DUTY_SCALE_CH1_S) +#define LEDC_DUTY_SCALE_CH1_V 0x000003FF +#define LEDC_DUTY_SCALE_CH1_S 0 + +/* LEDC_DUTY_CYCLE_CH1 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH1 on channel 1. + */ + +#define LEDC_DUTY_CYCLE_CH1 0x000003FF +#define LEDC_DUTY_CYCLE_CH1_M (LEDC_DUTY_CYCLE_CH1_V << LEDC_DUTY_CYCLE_CH1_S) +#define LEDC_DUTY_CYCLE_CH1_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH1_S 10 + +/* LEDC_DUTY_NUM_CH1 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH1 0x000003FF +#define LEDC_DUTY_NUM_CH1_M (LEDC_DUTY_NUM_CH1_V << LEDC_DUTY_NUM_CH1_S) +#define LEDC_DUTY_NUM_CH1_V 0x000003FF +#define LEDC_DUTY_NUM_CH1_S 20 + +/* LEDC_DUTY_INC_CH1 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 1. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH1 (BIT(30)) +#define LEDC_DUTY_INC_CH1_M (LEDC_DUTY_INC_CH1_V << LEDC_DUTY_INC_CH1_S) +#define LEDC_DUTY_INC_CH1_V 0x00000001 +#define LEDC_DUTY_INC_CH1_S 30 + +/* LEDC_DUTY_START_CH1 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH1_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001 +#define LEDC_DUTY_START_CH1_S 31 + +/* LEDC_CH1_DUTY_R_REG register + * Current duty cycle for channel 1 + */ + +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) + +/* LEDC_DUTY_R_CH1 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 1. + */ + +#define LEDC_DUTY_R_CH1 0x0007FFFF +#define LEDC_DUTY_R_CH1_M (LEDC_DUTY_R_CH1_V << LEDC_DUTY_R_CH1_S) +#define LEDC_DUTY_R_CH1_V 0x0007FFFF +#define LEDC_DUTY_R_CH1_S 0 + +/* LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ + +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) + +/* LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 2. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH2 0x00000003 +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003 +#define LEDC_TIMER_SEL_CH2_S 0 + +/* LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 2. + */ + +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH2_S 2 + +/* LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 2 is inactive. + */ + +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001 +#define LEDC_IDLE_LV_CH2_S 3 + +/* LEDC_PARA_UP_CH2 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH2_HPOINT and LEDC_CH2_DUTY for + * channel 2. + */ + +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001 +#define LEDC_PARA_UP_CH2_S 4 + +/* LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH2_INT interrupt will be triggered when channel 2 + * overflows for (LEDC_OVF_NUM_CH2 + 1) times. + */ + +#define LEDC_OVF_NUM_CH2 0x000003FF +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FF +#define LEDC_OVF_NUM_CH2_S 5 + +/* LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 2. + */ + +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH2_S 15 + +/* LEDC_OVF_CNT_RESET_CH2 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 2. + */ + +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH2 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH2. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH2 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH2_M (LEDC_OVF_CNT_RESET_ST_CH2_V << LEDC_OVF_CNT_RESET_ST_CH2_S) +#define LEDC_OVF_CNT_RESET_ST_CH2_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH2_S 17 + +/* LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ + +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) + +/* LEDC_HPOINT_CH2 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH2 0x00003FFF +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x00003FFF +#define LEDC_HPOINT_CH2_S 0 + +/* LEDC_CH2_DUTY_REG register + * Initial duty cycle for channel 2 + */ + +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) + +/* LEDC_DUTY_CH2 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH2 0x0007FFFF +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x0007FFFF +#define LEDC_DUTY_CH2_S 0 + +/* LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ + +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) + +/* LEDC_DUTY_SCALE_CH2 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 2. + */ + +#define LEDC_DUTY_SCALE_CH2 0x000003FF +#define LEDC_DUTY_SCALE_CH2_M (LEDC_DUTY_SCALE_CH2_V << LEDC_DUTY_SCALE_CH2_S) +#define LEDC_DUTY_SCALE_CH2_V 0x000003FF +#define LEDC_DUTY_SCALE_CH2_S 0 + +/* LEDC_DUTY_CYCLE_CH2 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH2 on channel 2. + */ + +#define LEDC_DUTY_CYCLE_CH2 0x000003FF +#define LEDC_DUTY_CYCLE_CH2_M (LEDC_DUTY_CYCLE_CH2_V << LEDC_DUTY_CYCLE_CH2_S) +#define LEDC_DUTY_CYCLE_CH2_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH2_S 10 + +/* LEDC_DUTY_NUM_CH2 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH2 0x000003FF +#define LEDC_DUTY_NUM_CH2_M (LEDC_DUTY_NUM_CH2_V << LEDC_DUTY_NUM_CH2_S) +#define LEDC_DUTY_NUM_CH2_V 0x000003FF +#define LEDC_DUTY_NUM_CH2_S 20 + +/* LEDC_DUTY_INC_CH2 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 2. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH2 (BIT(30)) +#define LEDC_DUTY_INC_CH2_M (LEDC_DUTY_INC_CH2_V << LEDC_DUTY_INC_CH2_S) +#define LEDC_DUTY_INC_CH2_V 0x00000001 +#define LEDC_DUTY_INC_CH2_S 30 + +/* LEDC_DUTY_START_CH2 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH2_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001 +#define LEDC_DUTY_START_CH2_S 31 + +/* LEDC_CH2_DUTY_R_REG register + * Current duty cycle for channel 2 + */ + +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) + +/* LEDC_DUTY_R_CH2 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 2. + */ + +#define LEDC_DUTY_R_CH2 0x0007FFFF +#define LEDC_DUTY_R_CH2_M (LEDC_DUTY_R_CH2_V << LEDC_DUTY_R_CH2_S) +#define LEDC_DUTY_R_CH2_V 0x0007FFFF +#define LEDC_DUTY_R_CH2_S 0 + +/* LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ + +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) + +/* LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 3. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH3 0x00000003 +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003 +#define LEDC_TIMER_SEL_CH3_S 0 + +/* LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 3. + */ + +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH3_S 2 + +/* LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 3 is inactive. + */ + +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001 +#define LEDC_IDLE_LV_CH3_S 3 + +/* LEDC_PARA_UP_CH3 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH3_HPOINT and LEDC_CH3_DUTY for + * channel 3. + */ + +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001 +#define LEDC_PARA_UP_CH3_S 4 + +/* LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH3_INT interrupt will be triggered when channel 3 + * overflows for (LEDC_OVF_NUM_CH3 + 1) times. + */ + +#define LEDC_OVF_NUM_CH3 0x000003FF +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FF +#define LEDC_OVF_NUM_CH3_S 5 + +/* LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 3. + */ + +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH3_S 15 + +/* LEDC_OVF_CNT_RESET_CH3 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 3. + */ + +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH3 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH3. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH3 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH3_M (LEDC_OVF_CNT_RESET_ST_CH3_V << LEDC_OVF_CNT_RESET_ST_CH3_S) +#define LEDC_OVF_CNT_RESET_ST_CH3_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH3_S 17 + +/* LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ + +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) + +/* LEDC_HPOINT_CH3 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH3 0x00003FFF +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x00003FFF +#define LEDC_HPOINT_CH3_S 0 + +/* LEDC_CH3_DUTY_REG register + * Initial duty cycle for channel 3 + */ + +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) + +/* LEDC_DUTY_CH3 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH3 0x0007FFFF +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x0007FFFF +#define LEDC_DUTY_CH3_S 0 + +/* LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ + +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) + +/* LEDC_DUTY_SCALE_CH3 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 3. + */ + +#define LEDC_DUTY_SCALE_CH3 0x000003FF +#define LEDC_DUTY_SCALE_CH3_M (LEDC_DUTY_SCALE_CH3_V << LEDC_DUTY_SCALE_CH3_S) +#define LEDC_DUTY_SCALE_CH3_V 0x000003FF +#define LEDC_DUTY_SCALE_CH3_S 0 + +/* LEDC_DUTY_CYCLE_CH3 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH3 on channel 3. + */ + +#define LEDC_DUTY_CYCLE_CH3 0x000003FF +#define LEDC_DUTY_CYCLE_CH3_M (LEDC_DUTY_CYCLE_CH3_V << LEDC_DUTY_CYCLE_CH3_S) +#define LEDC_DUTY_CYCLE_CH3_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH3_S 10 + +/* LEDC_DUTY_NUM_CH3 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH3 0x000003FF +#define LEDC_DUTY_NUM_CH3_M (LEDC_DUTY_NUM_CH3_V << LEDC_DUTY_NUM_CH3_S) +#define LEDC_DUTY_NUM_CH3_V 0x000003FF +#define LEDC_DUTY_NUM_CH3_S 20 + +/* LEDC_DUTY_INC_CH3 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 3. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH3 (BIT(30)) +#define LEDC_DUTY_INC_CH3_M (LEDC_DUTY_INC_CH3_V << LEDC_DUTY_INC_CH3_S) +#define LEDC_DUTY_INC_CH3_V 0x00000001 +#define LEDC_DUTY_INC_CH3_S 30 + +/* LEDC_DUTY_START_CH3 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH3_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001 +#define LEDC_DUTY_START_CH3_S 31 + +/* LEDC_CH3_DUTY_R_REG register + * Current duty cycle for channel 3 + */ + +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) + +/* LEDC_DUTY_R_CH3 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 3. + */ + +#define LEDC_DUTY_R_CH3 0x0007FFFF +#define LEDC_DUTY_R_CH3_M (LEDC_DUTY_R_CH3_V << LEDC_DUTY_R_CH3_S) +#define LEDC_DUTY_R_CH3_V 0x0007FFFF +#define LEDC_DUTY_R_CH3_S 0 + +/* LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ + +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) + +/* LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 4. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH4 0x00000003 +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003 +#define LEDC_TIMER_SEL_CH4_S 0 + +/* LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 4. + */ + +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH4_S 2 + +/* LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 4 is inactive. + */ + +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001 +#define LEDC_IDLE_LV_CH4_S 3 + +/* LEDC_PARA_UP_CH4 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH4_HPOINT and LEDC_CH4_DUTY for + * channel 4. + */ + +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001 +#define LEDC_PARA_UP_CH4_S 4 + +/* LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH4_INT interrupt will be triggered when channel 4 + * overflows for (LEDC_OVF_NUM_CH4 + 1) times. + */ + +#define LEDC_OVF_NUM_CH4 0x000003FF +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FF +#define LEDC_OVF_NUM_CH4_S 5 + +/* LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 4. + */ + +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH4_S 15 + +/* LEDC_OVF_CNT_RESET_CH4 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 4. + */ + +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH4 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH4. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH4 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH4_M (LEDC_OVF_CNT_RESET_ST_CH4_V << LEDC_OVF_CNT_RESET_ST_CH4_S) +#define LEDC_OVF_CNT_RESET_ST_CH4_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH4_S 17 + +/* LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ + +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) + +/* LEDC_HPOINT_CH4 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH4 0x00003FFF +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x00003FFF +#define LEDC_HPOINT_CH4_S 0 + +/* LEDC_CH4_DUTY_REG register + * Initial duty cycle for channel 4 + */ + +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) + +/* LEDC_DUTY_CH4 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH4 0x0007FFFF +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x0007FFFF +#define LEDC_DUTY_CH4_S 0 + +/* LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ + +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) + +/* LEDC_DUTY_SCALE_CH4 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 4. + */ + +#define LEDC_DUTY_SCALE_CH4 0x000003FF +#define LEDC_DUTY_SCALE_CH4_M (LEDC_DUTY_SCALE_CH4_V << LEDC_DUTY_SCALE_CH4_S) +#define LEDC_DUTY_SCALE_CH4_V 0x000003FF +#define LEDC_DUTY_SCALE_CH4_S 0 + +/* LEDC_DUTY_CYCLE_CH4 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH4 on channel 4. + */ + +#define LEDC_DUTY_CYCLE_CH4 0x000003FF +#define LEDC_DUTY_CYCLE_CH4_M (LEDC_DUTY_CYCLE_CH4_V << LEDC_DUTY_CYCLE_CH4_S) +#define LEDC_DUTY_CYCLE_CH4_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH4_S 10 + +/* LEDC_DUTY_NUM_CH4 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH4 0x000003FF +#define LEDC_DUTY_NUM_CH4_M (LEDC_DUTY_NUM_CH4_V << LEDC_DUTY_NUM_CH4_S) +#define LEDC_DUTY_NUM_CH4_V 0x000003FF +#define LEDC_DUTY_NUM_CH4_S 20 + +/* LEDC_DUTY_INC_CH4 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 4. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH4 (BIT(30)) +#define LEDC_DUTY_INC_CH4_M (LEDC_DUTY_INC_CH4_V << LEDC_DUTY_INC_CH4_S) +#define LEDC_DUTY_INC_CH4_V 0x00000001 +#define LEDC_DUTY_INC_CH4_S 30 + +/* LEDC_DUTY_START_CH4 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH4_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001 +#define LEDC_DUTY_START_CH4_S 31 + +/* LEDC_CH4_DUTY_R_REG register + * Current duty cycle for channel 4 + */ + +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) + +/* LEDC_DUTY_R_CH4 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 4. + */ + +#define LEDC_DUTY_R_CH4 0x0007FFFF +#define LEDC_DUTY_R_CH4_M (LEDC_DUTY_R_CH4_V << LEDC_DUTY_R_CH4_S) +#define LEDC_DUTY_R_CH4_V 0x0007FFFF +#define LEDC_DUTY_R_CH4_S 0 + +/* LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ + +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) + +/* LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 5. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH5 0x00000003 +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003 +#define LEDC_TIMER_SEL_CH5_S 0 + +/* LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 5. + */ + +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH5_S 2 + +/* LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 5 is inactive. + */ + +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001 +#define LEDC_IDLE_LV_CH5_S 3 + +/* LEDC_PARA_UP_CH5 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH5_HPOINT and LEDC_CH5_DUTY for + * channel 5. + */ + +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001 +#define LEDC_PARA_UP_CH5_S 4 + +/* LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH5_INT interrupt will be triggered when channel 5 + * overflows for (LEDC_OVF_NUM_CH5 + 1) times. + */ + +#define LEDC_OVF_NUM_CH5 0x000003FF +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FF +#define LEDC_OVF_NUM_CH5_S 5 + +/* LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 5. + */ + +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH5_S 15 + +/* LEDC_OVF_CNT_RESET_CH5 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 5. + */ + +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH5 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH5. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH5 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH5_M (LEDC_OVF_CNT_RESET_ST_CH5_V << LEDC_OVF_CNT_RESET_ST_CH5_S) +#define LEDC_OVF_CNT_RESET_ST_CH5_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH5_S 17 + +/* LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ + +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) + +/* LEDC_HPOINT_CH5 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH5 0x00003FFF +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x00003FFF +#define LEDC_HPOINT_CH5_S 0 + +/* LEDC_CH5_DUTY_REG register + * Initial duty cycle for channel 5 + */ + +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) + +/* LEDC_DUTY_CH5 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH5 0x0007FFFF +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x0007FFFF +#define LEDC_DUTY_CH5_S 0 + +/* LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ + +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) + +/* LEDC_DUTY_SCALE_CH5 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 5. + */ + +#define LEDC_DUTY_SCALE_CH5 0x000003FF +#define LEDC_DUTY_SCALE_CH5_M (LEDC_DUTY_SCALE_CH5_V << LEDC_DUTY_SCALE_CH5_S) +#define LEDC_DUTY_SCALE_CH5_V 0x000003FF +#define LEDC_DUTY_SCALE_CH5_S 0 + +/* LEDC_DUTY_CYCLE_CH5 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH5 on channel 5. + */ + +#define LEDC_DUTY_CYCLE_CH5 0x000003FF +#define LEDC_DUTY_CYCLE_CH5_M (LEDC_DUTY_CYCLE_CH5_V << LEDC_DUTY_CYCLE_CH5_S) +#define LEDC_DUTY_CYCLE_CH5_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH5_S 10 + +/* LEDC_DUTY_NUM_CH5 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH5 0x000003FF +#define LEDC_DUTY_NUM_CH5_M (LEDC_DUTY_NUM_CH5_V << LEDC_DUTY_NUM_CH5_S) +#define LEDC_DUTY_NUM_CH5_V 0x000003FF +#define LEDC_DUTY_NUM_CH5_S 20 + +/* LEDC_DUTY_INC_CH5 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 5. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH5 (BIT(30)) +#define LEDC_DUTY_INC_CH5_M (LEDC_DUTY_INC_CH5_V << LEDC_DUTY_INC_CH5_S) +#define LEDC_DUTY_INC_CH5_V 0x00000001 +#define LEDC_DUTY_INC_CH5_S 30 + +/* LEDC_DUTY_START_CH5 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH5_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001 +#define LEDC_DUTY_START_CH5_S 31 + +/* LEDC_CH5_DUTY_R_REG register + * Current duty cycle for channel 5 + */ + +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) + +/* LEDC_DUTY_R_CH5 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 5. + */ + +#define LEDC_DUTY_R_CH5 0x0007FFFF +#define LEDC_DUTY_R_CH5_M (LEDC_DUTY_R_CH5_V << LEDC_DUTY_R_CH5_S) +#define LEDC_DUTY_R_CH5_V 0x0007FFFF +#define LEDC_DUTY_R_CH5_S 0 + +/* LEDC_CH6_CONF0_REG register + * Configuration register 0 for channel 6 + */ + +#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) + +/* LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 6. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH6 0x00000003 +#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) +#define LEDC_TIMER_SEL_CH6_V 0x00000003 +#define LEDC_TIMER_SEL_CH6_S 0 + +/* LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 6. + */ + +#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) +#define LEDC_SIG_OUT_EN_CH6_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH6_S 2 + +/* LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 6 is inactive. + */ + +#define LEDC_IDLE_LV_CH6 (BIT(3)) +#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) +#define LEDC_IDLE_LV_CH6_V 0x00000001 +#define LEDC_IDLE_LV_CH6_S 3 + +/* LEDC_PARA_UP_CH6 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH6_HPOINT and LEDC_CH6_DUTY for + * channel 6. + */ + +#define LEDC_PARA_UP_CH6 (BIT(4)) +#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) +#define LEDC_PARA_UP_CH6_V 0x00000001 +#define LEDC_PARA_UP_CH6_S 4 + +/* LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH6_INT interrupt will be triggered when channel 6 + * overflows for (LEDC_OVF_NUM_CH6 + 1) times. + */ + +#define LEDC_OVF_NUM_CH6 0x000003FF +#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) +#define LEDC_OVF_NUM_CH6_V 0x000003FF +#define LEDC_OVF_NUM_CH6_S 5 + +/* LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 6. + */ + +#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) +#define LEDC_OVF_CNT_EN_CH6_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH6_S 15 + +/* LEDC_OVF_CNT_RESET_CH6 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 6. + */ + +#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) +#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH6_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH6 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH6. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH6 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH6_M (LEDC_OVF_CNT_RESET_ST_CH6_V << LEDC_OVF_CNT_RESET_ST_CH6_S) +#define LEDC_OVF_CNT_RESET_ST_CH6_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH6_S 17 + +/* LEDC_CH6_HPOINT_REG register + * High point register for channel 6 + */ + +#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) + +/* LEDC_HPOINT_CH6 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH6 0x00003FFF +#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) +#define LEDC_HPOINT_CH6_V 0x00003FFF +#define LEDC_HPOINT_CH6_S 0 + +/* LEDC_CH6_DUTY_REG register + * Initial duty cycle for channel 6 + */ + +#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) + +/* LEDC_DUTY_CH6 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH6 0x0007FFFF +#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) +#define LEDC_DUTY_CH6_V 0x0007FFFF +#define LEDC_DUTY_CH6_S 0 + +/* LEDC_CH6_CONF1_REG register + * Configuration register 1 for channel 6 + */ + +#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) + +/* LEDC_DUTY_SCALE_CH6 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 6. + */ + +#define LEDC_DUTY_SCALE_CH6 0x000003FF +#define LEDC_DUTY_SCALE_CH6_M (LEDC_DUTY_SCALE_CH6_V << LEDC_DUTY_SCALE_CH6_S) +#define LEDC_DUTY_SCALE_CH6_V 0x000003FF +#define LEDC_DUTY_SCALE_CH6_S 0 + +/* LEDC_DUTY_CYCLE_CH6 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH6 on channel 6. + */ + +#define LEDC_DUTY_CYCLE_CH6 0x000003FF +#define LEDC_DUTY_CYCLE_CH6_M (LEDC_DUTY_CYCLE_CH6_V << LEDC_DUTY_CYCLE_CH6_S) +#define LEDC_DUTY_CYCLE_CH6_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH6_S 10 + +/* LEDC_DUTY_NUM_CH6 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH6 0x000003FF +#define LEDC_DUTY_NUM_CH6_M (LEDC_DUTY_NUM_CH6_V << LEDC_DUTY_NUM_CH6_S) +#define LEDC_DUTY_NUM_CH6_V 0x000003FF +#define LEDC_DUTY_NUM_CH6_S 20 + +/* LEDC_DUTY_INC_CH6 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 6. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH6 (BIT(30)) +#define LEDC_DUTY_INC_CH6_M (LEDC_DUTY_INC_CH6_V << LEDC_DUTY_INC_CH6_S) +#define LEDC_DUTY_INC_CH6_V 0x00000001 +#define LEDC_DUTY_INC_CH6_S 30 + +/* LEDC_DUTY_START_CH6 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH6_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH6 (BIT(31)) +#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) +#define LEDC_DUTY_START_CH6_V 0x00000001 +#define LEDC_DUTY_START_CH6_S 31 + +/* LEDC_CH6_DUTY_R_REG register + * Current duty cycle for channel 6 + */ + +#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) + +/* LEDC_DUTY_R_CH6 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 6. + */ + +#define LEDC_DUTY_R_CH6 0x0007FFFF +#define LEDC_DUTY_R_CH6_M (LEDC_DUTY_R_CH6_V << LEDC_DUTY_R_CH6_S) +#define LEDC_DUTY_R_CH6_V 0x0007FFFF +#define LEDC_DUTY_R_CH6_S 0 + +/* LEDC_CH7_CONF0_REG register + * Configuration register 0 for channel 7 + */ + +#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) + +/* LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 7. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH7 0x00000003 +#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) +#define LEDC_TIMER_SEL_CH7_V 0x00000003 +#define LEDC_TIMER_SEL_CH7_S 0 + +/* LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 7. + */ + +#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) +#define LEDC_SIG_OUT_EN_CH7_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH7_S 2 + +/* LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 7 is inactive. + */ + +#define LEDC_IDLE_LV_CH7 (BIT(3)) +#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) +#define LEDC_IDLE_LV_CH7_V 0x00000001 +#define LEDC_IDLE_LV_CH7_S 3 + +/* LEDC_PARA_UP_CH7 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH7_HPOINT and LEDC_CH7_DUTY for + * channel 7. + */ + +#define LEDC_PARA_UP_CH7 (BIT(4)) +#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) +#define LEDC_PARA_UP_CH7_V 0x00000001 +#define LEDC_PARA_UP_CH7_S 4 + +/* LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH7_INT interrupt will be triggered when channel 7 + * overflows for (LEDC_OVF_NUM_CH7 + 1) times. + */ + +#define LEDC_OVF_NUM_CH7 0x000003FF +#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) +#define LEDC_OVF_NUM_CH7_V 0x000003FF +#define LEDC_OVF_NUM_CH7_S 5 + +/* LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 7. + */ + +#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) +#define LEDC_OVF_CNT_EN_CH7_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH7_S 15 + +/* LEDC_OVF_CNT_RESET_CH7 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 7. + */ + +#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) +#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH7_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH7 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH7. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH7 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH7_M (LEDC_OVF_CNT_RESET_ST_CH7_V << LEDC_OVF_CNT_RESET_ST_CH7_S) +#define LEDC_OVF_CNT_RESET_ST_CH7_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH7_S 17 + +/* LEDC_CH7_HPOINT_REG register + * High point register for channel 7 + */ + +#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) + +/* LEDC_HPOINT_CH7 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH7 0x00003FFF +#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) +#define LEDC_HPOINT_CH7_V 0x00003FFF +#define LEDC_HPOINT_CH7_S 0 + +/* LEDC_CH7_DUTY_REG register + * Initial duty cycle for channel 7 + */ + +#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) + +/* LEDC_DUTY_CH7 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH7 0x0007FFFF +#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) +#define LEDC_DUTY_CH7_V 0x0007FFFF +#define LEDC_DUTY_CH7_S 0 + +/* LEDC_CH7_CONF1_REG register + * Configuration register 1 for channel 7 + */ + +#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) + +/* LEDC_DUTY_SCALE_CH7 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 7. + */ + +#define LEDC_DUTY_SCALE_CH7 0x000003FF +#define LEDC_DUTY_SCALE_CH7_M (LEDC_DUTY_SCALE_CH7_V << LEDC_DUTY_SCALE_CH7_S) +#define LEDC_DUTY_SCALE_CH7_V 0x000003FF +#define LEDC_DUTY_SCALE_CH7_S 0 + +/* LEDC_DUTY_CYCLE_CH7 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH7 on channel 7. + */ + +#define LEDC_DUTY_CYCLE_CH7 0x000003FF +#define LEDC_DUTY_CYCLE_CH7_M (LEDC_DUTY_CYCLE_CH7_V << LEDC_DUTY_CYCLE_CH7_S) +#define LEDC_DUTY_CYCLE_CH7_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH7_S 10 + +/* LEDC_DUTY_NUM_CH7 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH7 0x000003FF +#define LEDC_DUTY_NUM_CH7_M (LEDC_DUTY_NUM_CH7_V << LEDC_DUTY_NUM_CH7_S) +#define LEDC_DUTY_NUM_CH7_V 0x000003FF +#define LEDC_DUTY_NUM_CH7_S 20 + +/* LEDC_DUTY_INC_CH7 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 7. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH7 (BIT(30)) +#define LEDC_DUTY_INC_CH7_M (LEDC_DUTY_INC_CH7_V << LEDC_DUTY_INC_CH7_S) +#define LEDC_DUTY_INC_CH7_V 0x00000001 +#define LEDC_DUTY_INC_CH7_S 30 + +/* LEDC_DUTY_START_CH7 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH7_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH7 (BIT(31)) +#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) +#define LEDC_DUTY_START_CH7_V 0x00000001 +#define LEDC_DUTY_START_CH7_S 31 + +/* LEDC_CH7_DUTY_R_REG register + * Current duty cycle for channel 7 + */ + +#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) + +/* LEDC_DUTY_R_CH7 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 7. + */ + +#define LEDC_DUTY_R_CH7 0x0007FFFF +#define LEDC_DUTY_R_CH7_M (LEDC_DUTY_R_CH7_V << LEDC_DUTY_R_CH7_S) +#define LEDC_DUTY_R_CH7_V 0x0007FFFF +#define LEDC_DUTY_R_CH7_S 0 + +/* LEDC_TIMER0_CONF_REG register + * Timer 0 configuration + */ + +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) + +/* LEDC_TIMER0_DUTY_RES : R/W; bitpos: [3:0]; default: 0; + * This register is used to control the range of the counter in timer 0. + */ + +#define LEDC_TIMER0_DUTY_RES 0x0000000F +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000000F +#define LEDC_TIMER0_DUTY_RES_S 0 + +/* LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [21:4]; default: 0; + * This register is used to configure the divisor for the divider in timer 0. + * + * The least significant eight bits represent the fractional part. + */ + +#define LEDC_CLK_DIV_TIMER0 0x0003FFFF +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFF +#define LEDC_CLK_DIV_TIMER0_S 4 + +/* LEDC_TIMER0_PAUSE : R/W; bitpos: [22]; default: 0; + * This bit is used to suspend the counter in timer 0. + */ + +#define LEDC_TIMER0_PAUSE (BIT(22)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001 +#define LEDC_TIMER0_PAUSE_S 22 + +/* LEDC_TIMER0_RST : R/W; bitpos: [23]; default: 1; + * This bit is used to reset timer 0. The counter will show 0 after reset. + */ + +#define LEDC_TIMER0_RST (BIT(23)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001 +#define LEDC_TIMER0_RST_S 23 + +/* LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [24]; default: 0; + * This bit is used to select clock for timer 0. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not + * accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + +#define LEDC_TICK_SEL_TIMER0 (BIT(24)) +#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) +#define LEDC_TICK_SEL_TIMER0_V 0x00000001 +#define LEDC_TICK_SEL_TIMER0_S 24 + +/* LEDC_TIMER0_PARA_UP : WO; bitpos: [25]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. + */ + +#define LEDC_TIMER0_PARA_UP (BIT(25)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001 +#define LEDC_TIMER0_PARA_UP_S 25 + +/* LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value + */ + +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) + +/* LEDC_TIMER0_CNT : RO; bitpos: [13:0]; default: 0; + * This register stores the current counter value of timer 0. + */ + +#define LEDC_TIMER0_CNT 0x00003FFF +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x00003FFF +#define LEDC_TIMER0_CNT_S 0 + +/* LEDC_TIMER1_CONF_REG register + * Timer 1 configuration + */ + +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) + +/* LEDC_TIMER1_DUTY_RES : R/W; bitpos: [3:0]; default: 0; + * This register is used to control the range of the counter in timer 1. + */ + +#define LEDC_TIMER1_DUTY_RES 0x0000000F +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000000F +#define LEDC_TIMER1_DUTY_RES_S 0 + +/* LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [21:4]; default: 0; + * This register is used to configure the divisor for the divider in timer 1. + * + * The least significant eight bits represent the fractional part. + */ + +#define LEDC_CLK_DIV_TIMER1 0x0003FFFF +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFF +#define LEDC_CLK_DIV_TIMER1_S 4 + +/* LEDC_TIMER1_PAUSE : R/W; bitpos: [22]; default: 0; + * This bit is used to suspend the counter in timer 1. + */ + +#define LEDC_TIMER1_PAUSE (BIT(22)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001 +#define LEDC_TIMER1_PAUSE_S 22 + +/* LEDC_TIMER1_RST : R/W; bitpos: [23]; default: 1; + * This bit is used to reset timer 1. The counter will show 0 after reset. + */ + +#define LEDC_TIMER1_RST (BIT(23)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001 +#define LEDC_TIMER1_RST_S 23 + +/* LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [24]; default: 0; + * This bit is used to select clock for timer 1. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not + * accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + +#define LEDC_TICK_SEL_TIMER1 (BIT(24)) +#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) +#define LEDC_TICK_SEL_TIMER1_V 0x00000001 +#define LEDC_TICK_SEL_TIMER1_S 24 + +/* LEDC_TIMER1_PARA_UP : WO; bitpos: [25]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. + */ + +#define LEDC_TIMER1_PARA_UP (BIT(25)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001 +#define LEDC_TIMER1_PARA_UP_S 25 + +/* LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value + */ + +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) + +/* LEDC_TIMER1_CNT : RO; bitpos: [13:0]; default: 0; + * This register stores the current counter value of timer 1. + */ + +#define LEDC_TIMER1_CNT 0x00003FFF +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x00003FFF +#define LEDC_TIMER1_CNT_S 0 + +/* LEDC_TIMER2_CONF_REG register + * Timer 2 configuration + */ + +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) + +/* LEDC_TIMER2_DUTY_RES : R/W; bitpos: [3:0]; default: 0; + * This register is used to control the range of the counter in timer 2. + */ + +#define LEDC_TIMER2_DUTY_RES 0x0000000F +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000000F +#define LEDC_TIMER2_DUTY_RES_S 0 + +/* LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [21:4]; default: 0; + * This register is used to configure the divisor for the divider in timer 2. + * + * The least significant eight bits represent the fractional part. + */ + +#define LEDC_CLK_DIV_TIMER2 0x0003FFFF +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFF +#define LEDC_CLK_DIV_TIMER2_S 4 + +/* LEDC_TIMER2_PAUSE : R/W; bitpos: [22]; default: 0; + * This bit is used to suspend the counter in timer 2. + */ + +#define LEDC_TIMER2_PAUSE (BIT(22)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001 +#define LEDC_TIMER2_PAUSE_S 22 + +/* LEDC_TIMER2_RST : R/W; bitpos: [23]; default: 1; + * This bit is used to reset timer 2. The counter will show 0 after reset. + */ + +#define LEDC_TIMER2_RST (BIT(23)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001 +#define LEDC_TIMER2_RST_S 23 + +/* LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [24]; default: 0; + * This bit is used to select clock for timer 2. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not + * accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + +#define LEDC_TICK_SEL_TIMER2 (BIT(24)) +#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) +#define LEDC_TICK_SEL_TIMER2_V 0x00000001 +#define LEDC_TICK_SEL_TIMER2_S 24 + +/* LEDC_TIMER2_PARA_UP : WO; bitpos: [25]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. + */ + +#define LEDC_TIMER2_PARA_UP (BIT(25)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001 +#define LEDC_TIMER2_PARA_UP_S 25 + +/* LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value + */ + +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) + +/* LEDC_TIMER2_CNT : RO; bitpos: [13:0]; default: 0; + * This register stores the current counter value of timer 2. + */ + +#define LEDC_TIMER2_CNT 0x00003FFF +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x00003FFF +#define LEDC_TIMER2_CNT_S 0 + +/* LEDC_TIMER3_CONF_REG register + * Timer 3 configuration + */ + +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) + +/* LEDC_TIMER3_DUTY_RES : R/W; bitpos: [3:0]; default: 0; + * This register is used to control the range of the counter in timer 3. + */ + +#define LEDC_TIMER3_DUTY_RES 0x0000000F +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000000F +#define LEDC_TIMER3_DUTY_RES_S 0 + +/* LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [21:4]; default: 0; + * This register is used to configure the divisor for the divider in timer 3. + * + * The least significant eight bits represent the fractional part. + */ + +#define LEDC_CLK_DIV_TIMER3 0x0003FFFF +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFF +#define LEDC_CLK_DIV_TIMER3_S 4 + +/* LEDC_TIMER3_PAUSE : R/W; bitpos: [22]; default: 0; + * This bit is used to suspend the counter in timer 3. + */ + +#define LEDC_TIMER3_PAUSE (BIT(22)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001 +#define LEDC_TIMER3_PAUSE_S 22 + +/* LEDC_TIMER3_RST : R/W; bitpos: [23]; default: 1; + * This bit is used to reset timer 3. The counter will show 0 after reset. + */ + +#define LEDC_TIMER3_RST (BIT(23)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001 +#define LEDC_TIMER3_RST_S 23 + +/* LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [24]; default: 0; + * This bit is used to select clock for timer 3. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not + * accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + +#define LEDC_TICK_SEL_TIMER3 (BIT(24)) +#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) +#define LEDC_TICK_SEL_TIMER3_V 0x00000001 +#define LEDC_TICK_SEL_TIMER3_S 24 + +/* LEDC_TIMER3_PARA_UP : WO; bitpos: [25]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. + */ + +#define LEDC_TIMER3_PARA_UP (BIT(25)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001 +#define LEDC_TIMER3_PARA_UP_S 25 + +/* LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value + */ + +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) + +/* LEDC_TIMER3_CNT : RO; bitpos: [13:0]; default: 0; + * This register stores the current counter value of timer 3. + */ + +#define LEDC_TIMER3_CNT 0x00003FFF +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x00003FFF +#define LEDC_TIMER3_CNT_S 0 + +/* LEDC_INT_RAW_REG register + * Raw interrupt status + */ + +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) + +/* LEDC_TIMER0_OVF_INT_RAW : RO; bitpos: [0]; default: 0; + * Triggered when the timer0 has reached its maximum counter value. + */ + +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001 +#define LEDC_TIMER0_OVF_INT_RAW_S 0 + +/* LEDC_TIMER1_OVF_INT_RAW : RO; bitpos: [1]; default: 0; + * Triggered when the timer1 has reached its maximum counter value. + */ + +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001 +#define LEDC_TIMER1_OVF_INT_RAW_S 1 + +/* LEDC_TIMER2_OVF_INT_RAW : RO; bitpos: [2]; default: 0; + * Triggered when the timer2 has reached its maximum counter value. + */ + +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001 +#define LEDC_TIMER2_OVF_INT_RAW_S 2 + +/* LEDC_TIMER3_OVF_INT_RAW : RO; bitpos: [3]; default: 0; + * Triggered when the timer3 has reached its maximum counter value. + */ + +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001 +#define LEDC_TIMER3_OVF_INT_RAW_S 3 + +/* LEDC_DUTY_CHNG_END_CH0_INT_RAW : RO; bitpos: [4]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 + +/* LEDC_DUTY_CHNG_END_CH1_INT_RAW : RO; bitpos: [5]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 + +/* LEDC_DUTY_CHNG_END_CH2_INT_RAW : RO; bitpos: [6]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 + +/* LEDC_DUTY_CHNG_END_CH3_INT_RAW : RO; bitpos: [7]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 + +/* LEDC_DUTY_CHNG_END_CH4_INT_RAW : RO; bitpos: [8]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 + +/* LEDC_DUTY_CHNG_END_CH5_INT_RAW : RO; bitpos: [9]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 + +/* LEDC_DUTY_CHNG_END_CH6_INT_RAW : RO; bitpos: [10]; default: 0; + * Interrupt raw bit for channel 6. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10 + +/* LEDC_DUTY_CHNG_END_CH7_INT_RAW : RO; bitpos: [11]; default: 0; + * Interrupt raw bit for channel 7. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11 + +/* LEDC_OVF_CNT_CH0_INT_RAW : RO; bitpos: [12]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH0. + */ + +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 + +/* LEDC_OVF_CNT_CH1_INT_RAW : RO; bitpos: [13]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH1. + */ + +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 + +/* LEDC_OVF_CNT_CH2_INT_RAW : RO; bitpos: [14]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH2. + */ + +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 + +/* LEDC_OVF_CNT_CH3_INT_RAW : RO; bitpos: [15]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH3. + */ + +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 + +/* LEDC_OVF_CNT_CH4_INT_RAW : RO; bitpos: [16]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH4. + */ + +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 + +/* LEDC_OVF_CNT_CH5_INT_RAW : RO; bitpos: [17]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH5. + */ + +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 + +/* LEDC_OVF_CNT_CH6_INT_RAW : RO; bitpos: [18]; default: 0; + * Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH6. + */ + +#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S) +#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH6_INT_RAW_S 18 + +/* LEDC_OVF_CNT_CH7_INT_RAW : RO; bitpos: [19]; default: 0; + * Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH7. + */ + +#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S) +#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH7_INT_RAW_S 19 + +/* LEDC_INT_ST_REG register + * Masked interrupt status + */ + +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) + +/* LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT + * interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001 +#define LEDC_TIMER0_OVF_INT_ST_S 0 + +/* LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT + * interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001 +#define LEDC_TIMER1_OVF_INT_ST_S 1 + +/* LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT + * interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001 +#define LEDC_TIMER2_OVF_INT_ST_S 2 + +/* LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT + * interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001 +#define LEDC_TIMER3_OVF_INT_ST_S 3 + +/* LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH0_INT interrupt when + * LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 + +/* LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH1_INT interrupt when + * LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 + +/* LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH2_INT interrupt when + * LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 + +/* LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH3_INT interrupt when + * LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 + +/* LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH4_INT interrupt when + * LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 + +/* LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH5_INT interrupt when + * LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 + +/* LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH6_INT interrupt when + * LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10 + +/* LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH7_INT interrupt when + * LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11 + +/* LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT + * interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 + +/* LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT + * interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 + +/* LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT + * interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 + +/* LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT + * interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 + +/* LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT + * interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 + +/* LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT + * interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 + +/* LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT + * interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S) +#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH6_INT_ST_S 18 + +/* LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT + * interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S) +#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH7_INT_ST_S 19 + +/* LEDC_INT_ENA_REG register + * Interrupt enable bits + */ + +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) + +/* LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + */ + +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001 +#define LEDC_TIMER0_OVF_INT_ENA_S 0 + +/* LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + */ + +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001 +#define LEDC_TIMER1_OVF_INT_ENA_S 1 + +/* LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + */ + +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001 +#define LEDC_TIMER2_OVF_INT_ENA_S 2 + +/* LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + */ + +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001 +#define LEDC_TIMER3_OVF_INT_ENA_S 3 + +/* LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 + +/* LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 + +/* LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 + +/* LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 + +/* LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 + +/* LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 + +/* LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10 + +/* LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11 + +/* LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 + +/* LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 + +/* LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 + +/* LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 + +/* LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 + +/* LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 + +/* LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S) +#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH6_INT_ENA_S 18 + +/* LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S) +#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH7_INT_ENA_S 19 + +/* LEDC_INT_CLR_REG register + * Interrupt clear bits + */ + +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) + +/* LEDC_TIMER0_OVF_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + */ + +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001 +#define LEDC_TIMER0_OVF_INT_CLR_S 0 + +/* LEDC_TIMER1_OVF_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + */ + +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001 +#define LEDC_TIMER1_OVF_INT_CLR_S 1 + +/* LEDC_TIMER2_OVF_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + */ + +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001 +#define LEDC_TIMER2_OVF_INT_CLR_S 2 + +/* LEDC_TIMER3_OVF_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + */ + +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001 +#define LEDC_TIMER3_OVF_INT_CLR_S 3 + +/* LEDC_DUTY_CHNG_END_CH0_INT_CLR : WO; bitpos: [4]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 + +/* LEDC_DUTY_CHNG_END_CH1_INT_CLR : WO; bitpos: [5]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 + +/* LEDC_DUTY_CHNG_END_CH2_INT_CLR : WO; bitpos: [6]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 + +/* LEDC_DUTY_CHNG_END_CH3_INT_CLR : WO; bitpos: [7]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 + +/* LEDC_DUTY_CHNG_END_CH4_INT_CLR : WO; bitpos: [8]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 + +/* LEDC_DUTY_CHNG_END_CH5_INT_CLR : WO; bitpos: [9]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 + +/* LEDC_DUTY_CHNG_END_CH6_INT_CLR : WO; bitpos: [10]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10 + +/* LEDC_DUTY_CHNG_END_CH7_INT_CLR : WO; bitpos: [11]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11 + +/* LEDC_OVF_CNT_CH0_INT_CLR : WO; bitpos: [12]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 + +/* LEDC_OVF_CNT_CH1_INT_CLR : WO; bitpos: [13]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 + +/* LEDC_OVF_CNT_CH2_INT_CLR : WO; bitpos: [14]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 + +/* LEDC_OVF_CNT_CH3_INT_CLR : WO; bitpos: [15]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 + +/* LEDC_OVF_CNT_CH4_INT_CLR : WO; bitpos: [16]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 + +/* LEDC_OVF_CNT_CH5_INT_CLR : WO; bitpos: [17]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 + +/* LEDC_OVF_CNT_CH6_INT_CLR : WO; bitpos: [18]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S) +#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH6_INT_CLR_S 18 + +/* LEDC_OVF_CNT_CH7_INT_CLR : WO; bitpos: [19]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S) +#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH7_INT_CLR_S 19 + +/* LEDC_CONF_REG register + * Global ledc configuration register + */ + +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0xd0) + +/* LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * This bit is used to select clock source for the 4 timers . + * + * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + */ + +#define LEDC_APB_CLK_SEL 0x00000003 +#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) +#define LEDC_APB_CLK_SEL_V 0x00000003 +#define LEDC_APB_CLK_SEL_S 0 + +/* LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for register. 1'h0: Support clock only when + * application writes registers. + */ + +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001 +#define LEDC_CLK_EN_S 31 + +/* LEDC_DATE_REG register + * Version control register + */ + +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0xfc) + +/* LEDC_DATE : R/W; bitpos: [31:0]; default: 419898881; + * This is the version control register. + */ + +#define LEDC_DATE 0xFFFFFFFF +#define LEDC_DATE_M (LEDC_DATE_V << LEDC_DATE_S) +#define LEDC_DATE_V 0xFFFFFFFF +#define LEDC_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h index 51a80589ae2..c9cf552438a 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h @@ -21,12 +21,6 @@ #ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_MEMORYMAP_H #define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_MEMORYMAP_H -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_rsa.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_rsa.h new file mode 100644 index 00000000000..e11582c7f3e --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_rsa.h @@ -0,0 +1,308 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_rsa.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RSA_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RSA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RSA_MEM_M_BLOCK_REG register + * Memory M + */ + +#define RSA_MEM_M_BLOCK_REG (DR_REG_RSA_BASE + 0x0) + +/* RSA_M_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory M + */ + +#define RSA_M_MEMORY 0x0001FFFF +#define RSA_M_MEMORY_M (RSA_M_MEMORY_V << RSA_M_MEMORY_S) +#define RSA_M_MEMORY_V 0x0001FFFF +#define RSA_M_MEMORY_S 0 + +/* RSA_MEM_RB_BLOCK_REG register + * Memory RB + */ + +#define RSA_MEM_RB_BLOCK_REG (DR_REG_RSA_BASE + 0x200) + +/* RSA_RB_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory RB + */ + +#define RSA_RB_MEMORY 0x0001FFFF +#define RSA_RB_MEMORY_M (RSA_RB_MEMORY_V << RSA_RB_MEMORY_S) +#define RSA_RB_MEMORY_V 0x0001FFFF +#define RSA_RB_MEMORY_S 0 + +/* RSA_MEM_Z_BLOCK_REG register + * Memory Z + */ + +#define RSA_MEM_Z_BLOCK_REG (DR_REG_RSA_BASE + 0x200) + +/* RSA_Z_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory Z + */ + +#define RSA_Z_MEMORY 0x0001FFFF +#define RSA_Z_MEMORY_M (RSA_Z_MEMORY_V << RSA_Z_MEMORY_S) +#define RSA_Z_MEMORY_V 0x0001FFFF +#define RSA_Z_MEMORY_S 0 + +/* RSA_MEM_Y_BLOCK_REG register + * Memory Y + */ + +#define RSA_MEM_Y_BLOCK_REG (DR_REG_RSA_BASE + 0x400) + +/* RSA_Y_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory Y + */ + +#define RSA_Y_MEMORY 0x0001FFFF +#define RSA_Y_MEMORY_M (RSA_Y_MEMORY_V << RSA_Y_MEMORY_S) +#define RSA_Y_MEMORY_V 0x0001FFFF +#define RSA_Y_MEMORY_S 0 + +/* RSA_MEM_X_BLOCK_REG register + * Memory X + */ + +#define RSA_MEM_X_BLOCK_REG (DR_REG_RSA_BASE + 0x600) + +/* RSA_X_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory X + */ + +#define RSA_X_MEMORY 0x0001FFFF +#define RSA_X_MEMORY_M (RSA_X_MEMORY_V << RSA_X_MEMORY_S) +#define RSA_X_MEMORY_V 0x0001FFFF +#define RSA_X_MEMORY_S 0 + +/* RSA_M_PRIME_REG register + * Register to store M' + */ + +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) + +/* RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Stores M' + */ + +#define RSA_M_PRIME 0xFFFFFFFF +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFF +#define RSA_M_PRIME_S 0 + +/* RSA_MODE_REG register + * RSA length mode + */ + +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) + +/* RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Stores the mode of modular exponentiation. + */ + +#define RSA_MODE 0x0000007F +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007F +#define RSA_MODE_S 0 + +/* RSA_CLEAN_REG register + * RSA clean register + */ + +#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x808) + +/* RSA_CLEAN : RO; bitpos: [0]; default: 0; + * The content of this bit is 1 when memories complete initialization. + */ + +#define RSA_CLEAN (BIT(0)) +#define RSA_CLEAN_M (RSA_CLEAN_V << RSA_CLEAN_S) +#define RSA_CLEAN_V 0x00000001 +#define RSA_CLEAN_S 0 + +/* RSA_MODEXP_START_REG register + * Modular exponentiation starting bit + */ + +#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) + +/* RSA_MODEXP_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the modular exponentiation. + */ + +#define RSA_MODEXP_START (BIT(0)) +#define RSA_MODEXP_START_M (RSA_MODEXP_START_V << RSA_MODEXP_START_S) +#define RSA_MODEXP_START_V 0x00000001 +#define RSA_MODEXP_START_S 0 + +/* RSA_MODMULT_START_REG register + * Modular multiplication starting bit + */ + +#define RSA_MODMULT_START_REG (DR_REG_RSA_BASE + 0x810) + +/* RSA_MODMULT_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the modular multiplication. + */ + +#define RSA_MODMULT_START (BIT(0)) +#define RSA_MODMULT_START_M (RSA_MODMULT_START_V << RSA_MODMULT_START_S) +#define RSA_MODMULT_START_V 0x00000001 +#define RSA_MODMULT_START_S 0 + +/* RSA_MULT_START_REG register + * Normal multiplicaiton starting bit + */ + +#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) + +/* RSA_MULT_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the multiplication. + */ + +#define RSA_MULT_START (BIT(0)) +#define RSA_MULT_START_M (RSA_MULT_START_V << RSA_MULT_START_S) +#define RSA_MULT_START_V 0x00000001 +#define RSA_MULT_START_S 0 + +/* RSA_IDLE_REG register + * RSA idle register + */ + +#define RSA_IDLE_REG (DR_REG_RSA_BASE + 0x818) + +/* RSA_IDLE : RO; bitpos: [0]; default: 0; + * The content of this bit is 1 when the RSA accelerator is idle. + */ + +#define RSA_IDLE (BIT(0)) +#define RSA_IDLE_M (RSA_IDLE_V << RSA_IDLE_S) +#define RSA_IDLE_V 0x00000001 +#define RSA_IDLE_S 0 + +/* RSA_CLEAR_INTERRUPT_REG register + * RSA clear interrupt register + */ + +#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81c) + +/* RSA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear the RSA interrupts. + */ + +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001 +#define RSA_CLEAR_INTERRUPT_S 0 + +/* RSA_CONSTANT_TIME_REG register + * The constant_time option + */ + +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) + +/* RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Set this bit to 0 to enable the acceleration option of constant_time for + * modular exponentiation. Set to 1 to disable the acceleration (by default). + */ + +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001 +#define RSA_CONSTANT_TIME_S 0 + +/* RSA_SEARCH_ENABLE_REG register + * The search option + */ + +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) + +/* RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable the acceleration option of search for modular + * exponentiation. Set to 0 to disable the acceleration (by default). + */ + +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001 +#define RSA_SEARCH_ENABLE_S 0 + +/* RSA_SEARCH_POS_REG register + * The search position + */ + +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) + +/* RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Is used to configure the starting address when the acceleration option of + * search is used. + */ + +#define RSA_SEARCH_POS 0x00000FFF +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFF +#define RSA_SEARCH_POS_S 0 + +/* RSA_INTERRUPT_ENA_REG register + * RSA interrupt enable register + */ + +#define RSA_INTERRUPT_ENA_REG (DR_REG_RSA_BASE + 0x82c) + +/* RSA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable the RSA interrupt. This option is enabled by + * default. + */ + +#define RSA_INTERRUPT_ENA (BIT(0)) +#define RSA_INTERRUPT_ENA_M (RSA_INTERRUPT_ENA_V << RSA_INTERRUPT_ENA_S) +#define RSA_INTERRUPT_ENA_V 0x00000001 +#define RSA_INTERRUPT_ENA_S 0 + +/* RSA_DATE_REG register + * Version control register + */ + +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) + +/* RSA_DATE : R/W; bitpos: [29:0]; default: 538510373; + * Version control register + */ + +#define RSA_DATE 0x3FFFFFFF +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFF +#define RSA_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RSA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h index 90520ff238b..9f9282a17df 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h @@ -3615,4 +3615,13 @@ #define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF #define RTC_CNTL_CNTL_DATE_S 0 +#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG +#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG +#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG +#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG + #endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RTCCNTL_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h new file mode 100644 index 00000000000..d0f110b8340 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h @@ -0,0 +1,912 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SARADC_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SARADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) + +/** APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; + * description: wait arbit signal stable after sar_done + */ + +#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 +#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S)) +#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 +#define APB_SARADC_WAIT_ARB_CYCLE_S 30 + +/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ + +/* description: force option to xpd sar blocks */ + +#define APB_SARADC_XPD_SAR_FORCE 0x00000003 +#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S)) +#define APB_SARADC_XPD_SAR_FORCE_V 0x3 +#define APB_SARADC_XPD_SAR_FORCE_S 27 + +/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ + +/* description: clear the pointer of pattern table for DIG ADC1 CTRL */ + +#define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SAR_PATT_P_CLEAR_M (BIT(23)) +#define APB_SARADC_SAR_PATT_P_CLEAR_V 0x1 +#define APB_SARADC_SAR_PATT_P_CLEAR_S 23 + +/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */ + +/* description: 0 ~ 15 means length 1 ~ 16 */ + +#define APB_SARADC_SAR_PATT_LEN 0x00000007 +#define APB_SARADC_SAR_PATT_LEN_M ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S)) +#define APB_SARADC_SAR_PATT_LEN_V 0x7 +#define APB_SARADC_SAR_PATT_LEN_S 15 + +/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ + +/* description: SAR clock divider */ + +#define APB_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S)) +#define APB_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_SARADC_SAR_CLK_DIV_S 7 + +/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ + +/* description: */ + +#define APB_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_SARADC_SAR_CLK_GATED_S 6 + +/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ + +/* description: */ + +#define APB_SARADC_START (BIT(1)) +#define APB_SARADC_START_M (BIT(1)) +#define APB_SARADC_START_V 0x1 +#define APB_SARADC_START_S 1 + +/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ + +/* description: */ + +#define APB_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_START_FORCE_M (BIT(0)) +#define APB_SARADC_START_FORCE_V 0x1 +#define APB_SARADC_START_FORCE_S 0 + +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) + +/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ + +/* description: to enable saradc timer trigger */ + +#define APB_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_TIMER_EN_M (BIT(24)) +#define APB_SARADC_TIMER_EN_V 0x1 +#define APB_SARADC_TIMER_EN_S 24 + +/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ + +/* description: to set saradc timer target */ + +#define APB_SARADC_TIMER_TARGET 0x00000FFF +#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S)) +#define APB_SARADC_TIMER_TARGET_V 0xFFF +#define APB_SARADC_TIMER_TARGET_S 12 + +/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ + +/* description: 1: data to DIG ADC2 CTRL is inverted otherwise not */ + +#define APB_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SAR2_INV_M (BIT(10)) +#define APB_SARADC_SAR2_INV_V 0x1 +#define APB_SARADC_SAR2_INV_S 10 + +/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ + +/* description: 1: data to DIG ADC1 CTRL is inverted otherwise not */ + +#define APB_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SAR1_INV_M (BIT(9)) +#define APB_SARADC_SAR1_INV_V 0x1 +#define APB_SARADC_SAR1_INV_S 9 + +/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ + +/* description: max conversion number */ + +#define APB_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S)) +#define APB_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_SARADC_MAX_MEAS_NUM_S 1 + +/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ + +/* description: */ + +#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_SARADC_MEAS_NUM_LIMIT_S 0 + +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008) + +/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ + +/* description: */ + +#define APB_SARADC_FILTER_FACTOR0 0x00000007 +#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S)) +#define APB_SARADC_FILTER_FACTOR0_V 0x7 +#define APB_SARADC_FILTER_FACTOR0_S 29 + +/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ + +/* description: */ + +#define APB_SARADC_FILTER_FACTOR1 0x00000007 +#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S)) +#define APB_SARADC_FILTER_FACTOR1_V 0x7 +#define APB_SARADC_FILTER_FACTOR1_S 26 + +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C) + +/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ + +/* description: */ + +#define APB_SARADC_STANDBY_WAIT 0x000000FF +#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S)) +#define APB_SARADC_STANDBY_WAIT_V 0xFF +#define APB_SARADC_STANDBY_WAIT_S 16 + +/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ + +/* description: */ + +#define APB_SARADC_RSTB_WAIT 0x000000FF +#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S)) +#define APB_SARADC_RSTB_WAIT_V 0xFF +#define APB_SARADC_RSTB_WAIT_S 8 + +/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ + +/* description: */ + +#define APB_SARADC_XPD_WAIT 0x000000FF +#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S)) +#define APB_SARADC_XPD_WAIT_V 0xFF +#define APB_SARADC_XPD_WAIT_S 0 + +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010) + +/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ + +/* description: */ + +#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S)) +#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_S 0 + +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014) + +/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ + +/* description: */ + +#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S)) +#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_S 0 + +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018) + +/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ + +/* description: item 0 ~ 3 for pattern table 1 (each item one byte) */ + +#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF +#define APB_SARADC_SAR_PATT_TAB1_M ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S)) +#define APB_SARADC_SAR_PATT_TAB1_V 0xFFFFFF +#define APB_SARADC_SAR_PATT_TAB1_S 0 + +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C) + +/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ + +/* description: Item 4 ~ 7 for pattern table 1 (each item one byte) */ + +#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF +#define APB_SARADC_SAR_PATT_TAB2_M ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S)) +#define APB_SARADC_SAR_PATT_TAB2_V 0xFFFFFF +#define APB_SARADC_SAR_PATT_TAB2_S 0 + +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x020) + +/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define APB_SARADC1_ONETIME_SAMPLE_M (BIT(31)) +#define APB_SARADC1_ONETIME_SAMPLE_V 0x1 +#define APB_SARADC1_ONETIME_SAMPLE_S 31 + +/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define APB_SARADC2_ONETIME_SAMPLE_M (BIT(30)) +#define APB_SARADC2_ONETIME_SAMPLE_V 0x1 +#define APB_SARADC2_ONETIME_SAMPLE_S 30 + +/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ONETIME_START (BIT(29)) +#define APB_SARADC_ONETIME_START_M (BIT(29)) +#define APB_SARADC_ONETIME_START_V 0x1 +#define APB_SARADC_ONETIME_START_S 29 + +/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */ + +/* description: */ + +#define APB_SARADC_ONETIME_CHANNEL 0x0000000F +#define APB_SARADC_ONETIME_CHANNEL_M ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S)) +#define APB_SARADC_ONETIME_CHANNEL_V 0xF +#define APB_SARADC_ONETIME_CHANNEL_S 25 + +/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ + +/* description: */ + +#define APB_SARADC_ONETIME_ATTEN 0x00000003 +#define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S)) +#define APB_SARADC_ONETIME_ATTEN_V 0x3 +#define APB_SARADC_ONETIME_ATTEN_S 23 + +#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x024) + +/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* description: adc2 arbiter uses fixed priority */ + +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 + +/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ + +/* description: Set adc2 arbiter wifi priority */ + +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 + +/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ + +/* description: Set adc2 arbiter rtc priority */ + +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 + +/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ + +/* description: Set adc2 arbiterapb priority */ + +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 + +/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* description: adc2 arbiter force grant */ + +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 + +/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* description: adc2 arbiter force to enable wifi controller */ + +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 + +/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* description: adc2 arbiter force to enable rtc controller */ + +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 + +/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'fb0 ; */ + +/* description: adc2 arbiter force to enableapb controller */ + +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 + +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x028) + +/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* description: enable apb_adc1_filter */ + +#define APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_FILTER_RESET_M (BIT(31)) +#define APB_SARADC_FILTER_RESET_V 0x1 +#define APB_SARADC_FILTER_RESET_S 31 + +/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */ + +/* description: apb_adc1_filter_factor */ + +#define APB_SARADC_FILTER_CHANNEL0 0x0000000F +#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S)) +#define APB_SARADC_FILTER_CHANNEL0_V 0xF +#define APB_SARADC_FILTER_CHANNEL0_S 22 + +/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */ + +/* description: */ + +#define APB_SARADC_FILTER_CHANNEL1 0x0000000F +#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S)) +#define APB_SARADC_FILTER_CHANNEL1_V 0xF +#define APB_SARADC_FILTER_CHANNEL1_S 18 + +#define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x02C) + +/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ + +/* description: */ + +#define APB_SARADC_ADC1_DATA 0x0001FFFF +#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S)) +#define APB_SARADC_ADC1_DATA_V 0x1FFFF +#define APB_SARADC_ADC1_DATA_S 0 + +#define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x030) + +/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ + +/* description: */ + +#define APB_SARADC_ADC2_DATA 0x0001FFFF +#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S)) +#define APB_SARADC_ADC2_DATA_V 0x1FFFF +#define APB_SARADC_ADC2_DATA_S 0 + +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x034) + +/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ + +/* description: saradc1's thres0 monitor thres */ + +#define APB_SARADC_THRES0_LOW 0x00001FFF +#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S)) +#define APB_SARADC_THRES0_LOW_V 0x1FFF +#define APB_SARADC_THRES0_LOW_S 18 + +/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ + +/* description: saradc1's thres0 monitor thres */ + +#define APB_SARADC_THRES0_HIGH 0x00001FFF +#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S)) +#define APB_SARADC_THRES0_HIGH_V 0x1FFF +#define APB_SARADC_THRES0_HIGH_S 5 + +/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_CHANNEL 0x0000000F +#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S)) +#define APB_SARADC_THRES0_CHANNEL_V 0xF +#define APB_SARADC_THRES0_CHANNEL_S 0 + +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038) + +/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ + +/* description: saradc1's thres0 monitor thres */ + +#define APB_SARADC_THRES1_LOW 0x00001FFF +#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S)) +#define APB_SARADC_THRES1_LOW_V 0x1FFF +#define APB_SARADC_THRES1_LOW_S 18 + +/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ + +/* description: saradc1's thres0 monitor thres */ + +#define APB_SARADC_THRES1_HIGH 0x00001FFF +#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S)) +#define APB_SARADC_THRES1_HIGH_V 0x1FFF +#define APB_SARADC_THRES1_HIGH_S 5 + +/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_CHANNEL 0x0000000F +#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S)) +#define APB_SARADC_THRES1_CHANNEL_V 0xF +#define APB_SARADC_THRES1_CHANNEL_S 0 + +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C) + +/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_THRES0_EN_M (BIT(31)) +#define APB_SARADC_THRES0_EN_V 0x1 +#define APB_SARADC_THRES0_EN_S 31 + +/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_THRES1_EN_M (BIT(30)) +#define APB_SARADC_THRES1_EN_V 0x1 +#define APB_SARADC_THRES1_EN_S 30 + +/* description: */ + +#define APB_SARADC_THRES_ALL_EN (BIT(27)) +#define APB_SARADC_THRES_ALL_EN_M (BIT(27)) +#define APB_SARADC_THRES_ALL_EN_V 0x1 +#define APB_SARADC_THRES_ALL_EN_S 27 + +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x040) + +/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ENA_S 31 + +/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ENA_S 30 + +/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 + +/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 + +/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_ENA_S 27 + +/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ENA_S 26 + +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x044) + +/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_RAW_S 31 + +/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_RAW_S 30 + +/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 + +/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 + +/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_RAW_S 27 + +/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_RAW_S 26 + +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x048) + +/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ST_S 31 + +/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ST_S 30 + +/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_ST_S 29 + +/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_ST_S 28 + +/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_ST_S 27 + +/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ST_S 26 + +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x04C) + +/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_CLR_S 31 + +/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_CLR_S 30 + +/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 + +/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 + +/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_CLR_S 27 + +/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_CLR_S 26 + +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x050) + +/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ + +/* description: enable apb_adc use spi_dma */ + +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_V 0x1 +#define APB_SARADC_APB_ADC_TRANS_S 31 + +/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* description: reset_apb_adc_state */ + +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 + +/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ + +/* description: the dma_in_suc_eof gen when sample cnt = spi_eof_num */ + +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF +#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S)) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 + +#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x054) + +/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ + +/* description: Set this bit to enable clk_apll */ + +#define APB_SARADC_CLK_SEL 0x00000003 +#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S)) +#define APB_SARADC_CLK_SEL_V 0x3 +#define APB_SARADC_CLK_SEL_S 21 + +/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ + +/* description: */ + +#define APB_SARADC_CLK_EN (BIT(20)) +#define APB_SARADC_CLK_EN_M (BIT(20)) +#define APB_SARADC_CLK_EN_V 0x1 +#define APB_SARADC_CLK_EN_S 20 + +/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ + +/* description: Fractional clock divider denominator value */ + +#define APB_SARADC_CLKM_DIV_A 0x0000003F +#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S)) +#define APB_SARADC_CLKM_DIV_A_V 0x3F +#define APB_SARADC_CLKM_DIV_A_S 14 + +/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ + +/* description: Fractional clock divider numerator value */ + +#define APB_SARADC_CLKM_DIV_B 0x0000003F +#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S)) +#define APB_SARADC_CLKM_DIV_B_V 0x3F +#define APB_SARADC_CLKM_DIV_B_S 8 + +/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ + +/* description: Integral I2S clock divider value */ + +#define APB_SARADC_CLKM_DIV_NUM 0x000000FF +#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S)) +#define APB_SARADC_CLKM_DIV_NUM_V 0xFF +#define APB_SARADC_CLKM_DIV_NUM_S 0 + +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058) + +/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_TSENS_PU (BIT(22)) +#define APB_SARADC_TSENS_PU_M (BIT(22)) +#define APB_SARADC_TSENS_PU_V 0x1 +#define APB_SARADC_TSENS_PU_S 22 + +/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ + +/* description: */ + +#define APB_SARADC_TSENS_CLK_DIV 0x000000FF +#define APB_SARADC_TSENS_CLK_DIV_M ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S)) +#define APB_SARADC_TSENS_CLK_DIV_V 0xFF +#define APB_SARADC_TSENS_CLK_DIV_S 14 + +/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_TSENS_IN_INV (BIT(13)) +#define APB_SARADC_TSENS_IN_INV_M (BIT(13)) +#define APB_SARADC_TSENS_IN_INV_V 0x1 +#define APB_SARADC_TSENS_IN_INV_S 13 + +/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ + +/* description: */ + +#define APB_SARADC_TSENS_OUT 0x000000FF +#define APB_SARADC_TSENS_OUT_M ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S)) +#define APB_SARADC_TSENS_OUT_V 0xFF +#define APB_SARADC_TSENS_OUT_S 0 + +#define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x05C) + +/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* description: */ + +#define APB_SARADC_TSENS_CLK_SEL (BIT(15)) +#define APB_SARADC_TSENS_CLK_SEL_M (BIT(15)) +#define APB_SARADC_TSENS_CLK_SEL_V 0x1 +#define APB_SARADC_TSENS_CLK_SEL_S 15 + +/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ + +/* description: */ + +#define APB_SARADC_TSENS_CLK_INV (BIT(14)) +#define APB_SARADC_TSENS_CLK_INV_M (BIT(14)) +#define APB_SARADC_TSENS_CLK_INV_V 0x1 +#define APB_SARADC_TSENS_CLK_INV_S 14 + +/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ + +/* description: */ + +#define APB_SARADC_TSENS_XPD_FORCE 0x00000003 +#define APB_SARADC_TSENS_XPD_FORCE_M ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S)) +#define APB_SARADC_TSENS_XPD_FORCE_V 0x3 +#define APB_SARADC_TSENS_XPD_FORCE_S 12 + +/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ + +/* description: */ + +#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF +#define APB_SARADC_TSENS_XPD_WAIT_M ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S)) +#define APB_SARADC_TSENS_XPD_WAIT_V 0xFFF +#define APB_SARADC_TSENS_XPD_WAIT_S 0 + +#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x060) + +/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */ + +/* description: */ + +#define APB_SARADC_CALI_CFG 0x0001FFFF +#define APB_SARADC_CALI_CFG_M ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S)) +#define APB_SARADC_CALI_CFG_V 0x1FFFF +#define APB_SARADC_CALI_CFG_S 0 + +#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) + +/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */ + +/* description: */ + +#define APB_SARADC_DATE 0xFFFFFFFF +#define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S)) +#define APB_SARADC_DATE_V 0xFFFFFFFF +#define APB_SARADC_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SARADC_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h new file mode 100644 index 00000000000..f4d81898342 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h @@ -0,0 +1,938 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SHA_MODE_REG register + * Defines the algorithm of SHA accelerator + */ + +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) + +/* SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the SHA algorithm. + */ + +#define SHA_MODE 0x00000007 +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007 +#define SHA_MODE_S 0 + +/* SHA_T_STRING_REG register + * String content register for calculating initial Hash Value (only + * effective for SHA-512/t) + */ + +#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) + +/* SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; + * Defines t_string for calculating the initial Hash value for SHA-512/t. + */ + +#define SHA_T_STRING 0xFFFFFFFF +#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) +#define SHA_T_STRING_V 0xFFFFFFFF +#define SHA_T_STRING_S 0 + +/* SHA_T_LENGTH_REG register + * String length register for calculating initial Hash Value (only effective + * for SHA-512/t) + */ + +#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) + +/* SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; + * Defines t_string for calculating the initial Hash value for SHA-512/t. + */ + +#define SHA_T_LENGTH 0x0000003F +#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) +#define SHA_T_LENGTH_V 0x0000003F +#define SHA_T_LENGTH_S 0 + +/* SHA_DMA_BLOCK_NUM_REG register + * Block number register (only effective for DMA-SHA) + */ + +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) + +/* SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Defines the DMA-SHA block number. + */ + +#define SHA_DMA_BLOCK_NUM 0x0000003F +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003F +#define SHA_DMA_BLOCK_NUM_S 0 + +/* SHA_START_REG register + * Starts the SHA accelerator for Typical SHA operation + */ + +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) + +/* SHA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start Typical SHA calculation. + */ + +#define SHA_START (BIT(0)) +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x00000001 +#define SHA_START_S 0 + +/* SHA_CONTINUE_REG register + * Continues SHA operation (only effective in Typical SHA mode) + */ + +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) + +/* SHA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue Typical SHA calculation. + */ + +#define SHA_CONTINUE (BIT(0)) +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x00000001 +#define SHA_CONTINUE_S 0 + +/* SHA_BUSY_REG register + * Indicates if SHA Accelerator is busy or not + */ + +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) + +/* SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Indicates the states of SHA accelerator. + * #1'h0: idle + * #1'h1: busy + */ + +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001 +#define SHA_BUSY_STATE_S 0 + +/* SHA_DMA_START_REG register + * Starts the SHA accelerator for DMA-SHA operation + */ + +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) + +/* SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ + +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001 +#define SHA_DMA_START_S 0 + +/* SHA_DMA_CONTINUE_REG register + * Continues SHA operation (only effective in DMA-SHA mode) + */ + +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) + +/* SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ + +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001 +#define SHA_DMA_CONTINUE_S 0 + +/* SHA_INT_CLEAR_REG register + * DMA-SHA interrupt clear register + */ + +#define SHA_INT_CLEAR_REG (DR_REG_SHA_BASE + 0x24) + +/* SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Clears DMA-SHA interrupt. + */ + +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001 +#define SHA_CLEAR_INTERRUPT_S 0 + +/* SHA_INT_ENA_REG register + * DMA-SHA interrupt enable register + */ + +#define SHA_INT_ENA_REG (DR_REG_SHA_BASE + 0x28) + +/* SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Enables DMA-SHA interrupt. + */ + +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001 +#define SHA_INTERRUPT_ENA_S 0 + +/* SHA_DATE_REG register + * Version control register. + */ + +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) + +/* SHA_DATE : R/W; bitpos: [29:0]; default: 538510338; + * Version control register + */ + +#define SHA_DATE 0x3FFFFFFF +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFF +#define SHA_DATE_S 0 + +/* SHA_H_0_REG register + * Hash value + */ + +#define SHA_H_0_REG (DR_REG_SHA_BASE + 0x40) + +/* SHA_H_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the 0th 32-bit piece of the Hash value. + */ + +#define SHA_H_0 0xFFFFFFFF +#define SHA_H_0_M (SHA_H_0_V << SHA_H_0_S) +#define SHA_H_0_V 0xFFFFFFFF +#define SHA_H_0_S 0 + +/* SHA_H_1_REG register + * Hash value + */ + +#define SHA_H_1_REG (DR_REG_SHA_BASE + 0x44) + +/* SHA_H_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the 1th 32-bit piece of the Hash value. + */ + +#define SHA_H_1 0xFFFFFFFF +#define SHA_H_1_M (SHA_H_1_V << SHA_H_1_S) +#define SHA_H_1_V 0xFFFFFFFF +#define SHA_H_1_S 0 + +/* SHA_H_2_REG register + * Hash value + */ + +#define SHA_H_2_REG (DR_REG_SHA_BASE + 0x48) + +/* SHA_H_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the 2th 32-bit piece of the Hash value. + */ + +#define SHA_H_2 0xFFFFFFFF +#define SHA_H_2_M (SHA_H_2_V << SHA_H_2_S) +#define SHA_H_2_V 0xFFFFFFFF +#define SHA_H_2_S 0 + +/* SHA_H_3_REG register + * Hash value + */ + +#define SHA_H_3_REG (DR_REG_SHA_BASE + 0x4c) + +/* SHA_H_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the 3th 32-bit piece of the Hash value. + */ + +#define SHA_H_3 0xFFFFFFFF +#define SHA_H_3_M (SHA_H_3_V << SHA_H_3_S) +#define SHA_H_3_V 0xFFFFFFFF +#define SHA_H_3_S 0 + +/* SHA_H_4_REG register + * Hash value + */ + +#define SHA_H_4_REG (DR_REG_SHA_BASE + 0x50) + +/* SHA_H_4 : R/W; bitpos: [31:0]; default: 0; + * Stores the 4th 32-bit piece of the Hash value. + */ + +#define SHA_H_4 0xFFFFFFFF +#define SHA_H_4_M (SHA_H_4_V << SHA_H_4_S) +#define SHA_H_4_V 0xFFFFFFFF +#define SHA_H_4_S 0 + +/* SHA_H_5_REG register + * Hash value + */ + +#define SHA_H_5_REG (DR_REG_SHA_BASE + 0x54) + +/* SHA_H_5 : R/W; bitpos: [31:0]; default: 0; + * Stores the 5th 32-bit piece of the Hash value. + */ + +#define SHA_H_5 0xFFFFFFFF +#define SHA_H_5_M (SHA_H_5_V << SHA_H_5_S) +#define SHA_H_5_V 0xFFFFFFFF +#define SHA_H_5_S 0 + +/* SHA_H_6_REG register + * Hash value + */ + +#define SHA_H_6_REG (DR_REG_SHA_BASE + 0x58) + +/* SHA_H_6 : R/W; bitpos: [31:0]; default: 0; + * Stores the 6th 32-bit piece of the Hash value. + */ + +#define SHA_H_6 0xFFFFFFFF +#define SHA_H_6_M (SHA_H_6_V << SHA_H_6_S) +#define SHA_H_6_V 0xFFFFFFFF +#define SHA_H_6_S 0 + +/* SHA_H_7_REG register + * Hash value + */ + +#define SHA_H_7_REG (DR_REG_SHA_BASE + 0x5c) + +/* SHA_H_7 : R/W; bitpos: [31:0]; default: 0; + * Stores the 7th 32-bit piece of the Hash value. + */ + +#define SHA_H_7 0xFFFFFFFF +#define SHA_H_7_M (SHA_H_7_V << SHA_H_7_S) +#define SHA_H_7_V 0xFFFFFFFF +#define SHA_H_7_S 0 + +/* SHA_H_8_REG register + * Hash value + */ + +#define SHA_H_8_REG (DR_REG_SHA_BASE + 0x60) + +/* SHA_H_8 : R/W; bitpos: [31:0]; default: 0; + * Stores the 8th 32-bit piece of the Hash value. + */ + +#define SHA_H_8 0xFFFFFFFF +#define SHA_H_8_M (SHA_H_8_V << SHA_H_8_S) +#define SHA_H_8_V 0xFFFFFFFF +#define SHA_H_8_S 0 + +/* SHA_H_9_REG register + * Hash value + */ + +#define SHA_H_9_REG (DR_REG_SHA_BASE + 0x64) + +/* SHA_H_9 : R/W; bitpos: [31:0]; default: 0; + * Stores the 9th 32-bit piece of the Hash value. + */ + +#define SHA_H_9 0xFFFFFFFF +#define SHA_H_9_M (SHA_H_9_V << SHA_H_9_S) +#define SHA_H_9_V 0xFFFFFFFF +#define SHA_H_9_S 0 + +/* SHA_H_10_REG register + * Hash value + */ + +#define SHA_H_10_REG (DR_REG_SHA_BASE + 0x68) + +/* SHA_H_10 : R/W; bitpos: [31:0]; default: 0; + * Stores the 10th 32-bit piece of the Hash value. + */ + +#define SHA_H_10 0xFFFFFFFF +#define SHA_H_10_M (SHA_H_10_V << SHA_H_10_S) +#define SHA_H_10_V 0xFFFFFFFF +#define SHA_H_10_S 0 + +/* SHA_H_11_REG register + * Hash value + */ + +#define SHA_H_11_REG (DR_REG_SHA_BASE + 0x6c) + +/* SHA_H_11 : R/W; bitpos: [31:0]; default: 0; + * Stores the 11th 32-bit piece of the Hash value. + */ + +#define SHA_H_11 0xFFFFFFFF +#define SHA_H_11_M (SHA_H_11_V << SHA_H_11_S) +#define SHA_H_11_V 0xFFFFFFFF +#define SHA_H_11_S 0 + +/* SHA_H_12_REG register + * Hash value + */ + +#define SHA_H_12_REG (DR_REG_SHA_BASE + 0x70) + +/* SHA_H_12 : R/W; bitpos: [31:0]; default: 0; + * Stores the 12th 32-bit piece of the Hash value. + */ + +#define SHA_H_12 0xFFFFFFFF +#define SHA_H_12_M (SHA_H_12_V << SHA_H_12_S) +#define SHA_H_12_V 0xFFFFFFFF +#define SHA_H_12_S 0 + +/* SHA_H_13_REG register + * Hash value + */ + +#define SHA_H_13_REG (DR_REG_SHA_BASE + 0x74) + +/* SHA_H_13 : R/W; bitpos: [31:0]; default: 0; + * Stores the 13th 32-bit piece of the Hash value. + */ + +#define SHA_H_13 0xFFFFFFFF +#define SHA_H_13_M (SHA_H_13_V << SHA_H_13_S) +#define SHA_H_13_V 0xFFFFFFFF +#define SHA_H_13_S 0 + +/* SHA_H_14_REG register + * Hash value + */ + +#define SHA_H_14_REG (DR_REG_SHA_BASE + 0x78) + +/* SHA_H_14 : R/W; bitpos: [31:0]; default: 0; + * Stores the 14th 32-bit piece of the Hash value. + */ + +#define SHA_H_14 0xFFFFFFFF +#define SHA_H_14_M (SHA_H_14_V << SHA_H_14_S) +#define SHA_H_14_V 0xFFFFFFFF +#define SHA_H_14_S 0 + +/* SHA_H_15_REG register + * Hash value + */ + +#define SHA_H_15_REG (DR_REG_SHA_BASE + 0x7c) + +/* SHA_H_15 : R/W; bitpos: [31:0]; default: 0; + * Stores the 15th 32-bit piece of the Hash value. + */ + +#define SHA_H_15 0xFFFFFFFF +#define SHA_H_15_M (SHA_H_15_V << SHA_H_15_S) +#define SHA_H_15_V 0xFFFFFFFF +#define SHA_H_15_S 0 + +/* SHA_M_0_REG register + * Message + */ + +#define SHA_M_0_REG (DR_REG_SHA_BASE + 0x80) + +/* SHA_M_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the 0th 32-bit piece of the message. + */ + +#define SHA_M_0 0xFFFFFFFF +#define SHA_M_0_M (SHA_M_0_V << SHA_M_0_S) +#define SHA_M_0_V 0xFFFFFFFF +#define SHA_M_0_S 0 + +/* SHA_M_1_REG register + * Message + */ + +#define SHA_M_1_REG (DR_REG_SHA_BASE + 0x84) + +/* SHA_M_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the 1th 32-bit piece of the message. + */ + +#define SHA_M_1 0xFFFFFFFF +#define SHA_M_1_M (SHA_M_1_V << SHA_M_1_S) +#define SHA_M_1_V 0xFFFFFFFF +#define SHA_M_1_S 0 + +/* SHA_M_2_REG register + * Message + */ + +#define SHA_M_2_REG (DR_REG_SHA_BASE + 0x88) + +/* SHA_M_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the 2th 32-bit piece of the message. + */ + +#define SHA_M_2 0xFFFFFFFF +#define SHA_M_2_M (SHA_M_2_V << SHA_M_2_S) +#define SHA_M_2_V 0xFFFFFFFF +#define SHA_M_2_S 0 + +/* SHA_M_3_REG register + * Message + */ + +#define SHA_M_3_REG (DR_REG_SHA_BASE + 0x8c) + +/* SHA_M_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the 3th 32-bit piece of the message. + */ + +#define SHA_M_3 0xFFFFFFFF +#define SHA_M_3_M (SHA_M_3_V << SHA_M_3_S) +#define SHA_M_3_V 0xFFFFFFFF +#define SHA_M_3_S 0 + +/* SHA_M_4_REG register + * Message + */ + +#define SHA_M_4_REG (DR_REG_SHA_BASE + 0x90) + +/* SHA_M_4 : R/W; bitpos: [31:0]; default: 0; + * Stores the 4th 32-bit piece of the message. + */ + +#define SHA_M_4 0xFFFFFFFF +#define SHA_M_4_M (SHA_M_4_V << SHA_M_4_S) +#define SHA_M_4_V 0xFFFFFFFF +#define SHA_M_4_S 0 + +/* SHA_M_5_REG register + * Message + */ + +#define SHA_M_5_REG (DR_REG_SHA_BASE + 0x94) + +/* SHA_M_5 : R/W; bitpos: [31:0]; default: 0; + * Stores the 5th 32-bit piece of the message. + */ + +#define SHA_M_5 0xFFFFFFFF +#define SHA_M_5_M (SHA_M_5_V << SHA_M_5_S) +#define SHA_M_5_V 0xFFFFFFFF +#define SHA_M_5_S 0 + +/* SHA_M_6_REG register + * Message + */ + +#define SHA_M_6_REG (DR_REG_SHA_BASE + 0x98) + +/* SHA_M_6 : R/W; bitpos: [31:0]; default: 0; + * Stores the 6th 32-bit piece of the message. + */ + +#define SHA_M_6 0xFFFFFFFF +#define SHA_M_6_M (SHA_M_6_V << SHA_M_6_S) +#define SHA_M_6_V 0xFFFFFFFF +#define SHA_M_6_S 0 + +/* SHA_M_7_REG register + * Message + */ + +#define SHA_M_7_REG (DR_REG_SHA_BASE + 0x9c) + +/* SHA_M_7 : R/W; bitpos: [31:0]; default: 0; + * Stores the 7th 32-bit piece of the message. + */ + +#define SHA_M_7 0xFFFFFFFF +#define SHA_M_7_M (SHA_M_7_V << SHA_M_7_S) +#define SHA_M_7_V 0xFFFFFFFF +#define SHA_M_7_S 0 + +/* SHA_M_8_REG register + * Message + */ + +#define SHA_M_8_REG (DR_REG_SHA_BASE + 0xa0) + +/* SHA_M_8 : R/W; bitpos: [31:0]; default: 0; + * Stores the 8th 32-bit piece of the message. + */ + +#define SHA_M_8 0xFFFFFFFF +#define SHA_M_8_M (SHA_M_8_V << SHA_M_8_S) +#define SHA_M_8_V 0xFFFFFFFF +#define SHA_M_8_S 0 + +/* SHA_M_9_REG register + * Message + */ + +#define SHA_M_9_REG (DR_REG_SHA_BASE + 0xa4) + +/* SHA_M_9 : R/W; bitpos: [31:0]; default: 0; + * Stores the 9th 32-bit piece of the message. + */ + +#define SHA_M_9 0xFFFFFFFF +#define SHA_M_9_M (SHA_M_9_V << SHA_M_9_S) +#define SHA_M_9_V 0xFFFFFFFF +#define SHA_M_9_S 0 + +/* SHA_M_10_REG register + * Message + */ + +#define SHA_M_10_REG (DR_REG_SHA_BASE + 0xa8) + +/* SHA_M_10 : R/W; bitpos: [31:0]; default: 0; + * Stores the 10th 32-bit piece of the message. + */ + +#define SHA_M_10 0xFFFFFFFF +#define SHA_M_10_M (SHA_M_10_V << SHA_M_10_S) +#define SHA_M_10_V 0xFFFFFFFF +#define SHA_M_10_S 0 + +/* SHA_M_11_REG register + * Message + */ + +#define SHA_M_11_REG (DR_REG_SHA_BASE + 0xac) + +/* SHA_M_11 : R/W; bitpos: [31:0]; default: 0; + * Stores the 11th 32-bit piece of the message. + */ + +#define SHA_M_11 0xFFFFFFFF +#define SHA_M_11_M (SHA_M_11_V << SHA_M_11_S) +#define SHA_M_11_V 0xFFFFFFFF +#define SHA_M_11_S 0 + +/* SHA_M_12_REG register + * Message + */ + +#define SHA_M_12_REG (DR_REG_SHA_BASE + 0xb0) + +/* SHA_M_12 : R/W; bitpos: [31:0]; default: 0; + * Stores the 12th 32-bit piece of the message. + */ + +#define SHA_M_12 0xFFFFFFFF +#define SHA_M_12_M (SHA_M_12_V << SHA_M_12_S) +#define SHA_M_12_V 0xFFFFFFFF +#define SHA_M_12_S 0 + +/* SHA_M_13_REG register + * Message + */ + +#define SHA_M_13_REG (DR_REG_SHA_BASE + 0xb4) + +/* SHA_M_13 : R/W; bitpos: [31:0]; default: 0; + * Stores the 13th 32-bit piece of the message. + */ + +#define SHA_M_13 0xFFFFFFFF +#define SHA_M_13_M (SHA_M_13_V << SHA_M_13_S) +#define SHA_M_13_V 0xFFFFFFFF +#define SHA_M_13_S 0 + +/* SHA_M_14_REG register + * Message + */ + +#define SHA_M_14_REG (DR_REG_SHA_BASE + 0xb8) + +/* SHA_M_14 : R/W; bitpos: [31:0]; default: 0; + * Stores the 14th 32-bit piece of the message. + */ + +#define SHA_M_14 0xFFFFFFFF +#define SHA_M_14_M (SHA_M_14_V << SHA_M_14_S) +#define SHA_M_14_V 0xFFFFFFFF +#define SHA_M_14_S 0 + +/* SHA_M_15_REG register + * Message + */ + +#define SHA_M_15_REG (DR_REG_SHA_BASE + 0xbc) + +/* SHA_M_15 : R/W; bitpos: [31:0]; default: 0; + * Stores the 15th 32-bit piece of the message. + */ + +#define SHA_M_15 0xFFFFFFFF +#define SHA_M_15_M (SHA_M_15_V << SHA_M_15_S) +#define SHA_M_15_V 0xFFFFFFFF +#define SHA_M_15_S 0 + +/* SHA_M_16_REG register + * Message + */ + +#define SHA_M_16_REG (DR_REG_SHA_BASE + 0xc0) + +/* SHA_M_16 : R/W; bitpos: [31:0]; default: 0; + * Stores the 16th 32-bit piece of the message. + */ + +#define SHA_M_16 0xFFFFFFFF +#define SHA_M_16_M (SHA_M_16_V << SHA_M_16_S) +#define SHA_M_16_V 0xFFFFFFFF +#define SHA_M_16_S 0 + +/* SHA_M_17_REG register + * Message + */ + +#define SHA_M_17_REG (DR_REG_SHA_BASE + 0xc4) + +/* SHA_M_17 : R/W; bitpos: [31:0]; default: 0; + * Stores the 17th 32-bit piece of the message. + */ + +#define SHA_M_17 0xFFFFFFFF +#define SHA_M_17_M (SHA_M_17_V << SHA_M_17_S) +#define SHA_M_17_V 0xFFFFFFFF +#define SHA_M_17_S 0 + +/* SHA_M_18_REG register + * Message + */ + +#define SHA_M_18_REG (DR_REG_SHA_BASE + 0xc8) + +/* SHA_M_18 : R/W; bitpos: [31:0]; default: 0; + * Stores the 18th 32-bit piece of the message. + */ + +#define SHA_M_18 0xFFFFFFFF +#define SHA_M_18_M (SHA_M_18_V << SHA_M_18_S) +#define SHA_M_18_V 0xFFFFFFFF +#define SHA_M_18_S 0 + +/* SHA_M_19_REG register + * Message + */ + +#define SHA_M_19_REG (DR_REG_SHA_BASE + 0xcc) + +/* SHA_M_19 : R/W; bitpos: [31:0]; default: 0; + * Stores the 19th 32-bit piece of the message. + */ + +#define SHA_M_19 0xFFFFFFFF +#define SHA_M_19_M (SHA_M_19_V << SHA_M_19_S) +#define SHA_M_19_V 0xFFFFFFFF +#define SHA_M_19_S 0 + +/* SHA_M_20_REG register + * Message + */ + +#define SHA_M_20_REG (DR_REG_SHA_BASE + 0xd0) + +/* SHA_M_20 : R/W; bitpos: [31:0]; default: 0; + * Stores the 20th 32-bit piece of the message. + */ + +#define SHA_M_20 0xFFFFFFFF +#define SHA_M_20_M (SHA_M_20_V << SHA_M_20_S) +#define SHA_M_20_V 0xFFFFFFFF +#define SHA_M_20_S 0 + +/* SHA_M_21_REG register + * Message + */ + +#define SHA_M_21_REG (DR_REG_SHA_BASE + 0xd4) + +/* SHA_M_21 : R/W; bitpos: [31:0]; default: 0; + * Stores the 21th 32-bit piece of the message. + */ + +#define SHA_M_21 0xFFFFFFFF +#define SHA_M_21_M (SHA_M_21_V << SHA_M_21_S) +#define SHA_M_21_V 0xFFFFFFFF +#define SHA_M_21_S 0 + +/* SHA_M_22_REG register + * Message + */ + +#define SHA_M_22_REG (DR_REG_SHA_BASE + 0xd8) + +/* SHA_M_22 : R/W; bitpos: [31:0]; default: 0; + * Stores the 22th 32-bit piece of the message. + */ + +#define SHA_M_22 0xFFFFFFFF +#define SHA_M_22_M (SHA_M_22_V << SHA_M_22_S) +#define SHA_M_22_V 0xFFFFFFFF +#define SHA_M_22_S 0 + +/* SHA_M_23_REG register + * Message + */ + +#define SHA_M_23_REG (DR_REG_SHA_BASE + 0xdc) + +/* SHA_M_23 : R/W; bitpos: [31:0]; default: 0; + * Stores the 23th 32-bit piece of the message. + */ + +#define SHA_M_23 0xFFFFFFFF +#define SHA_M_23_M (SHA_M_23_V << SHA_M_23_S) +#define SHA_M_23_V 0xFFFFFFFF +#define SHA_M_23_S 0 + +/* SHA_M_24_REG register + * Message + */ + +#define SHA_M_24_REG (DR_REG_SHA_BASE + 0xe0) + +/* SHA_M_24 : R/W; bitpos: [31:0]; default: 0; + * Stores the 24th 32-bit piece of the message. + */ + +#define SHA_M_24 0xFFFFFFFF +#define SHA_M_24_M (SHA_M_24_V << SHA_M_24_S) +#define SHA_M_24_V 0xFFFFFFFF +#define SHA_M_24_S 0 + +/* SHA_M_25_REG register + * Message + */ + +#define SHA_M_25_REG (DR_REG_SHA_BASE + 0xe4) + +/* SHA_M_25 : R/W; bitpos: [31:0]; default: 0; + * Stores the 25th 32-bit piece of the message. + */ + +#define SHA_M_25 0xFFFFFFFF +#define SHA_M_25_M (SHA_M_25_V << SHA_M_25_S) +#define SHA_M_25_V 0xFFFFFFFF +#define SHA_M_25_S 0 + +/* SHA_M_26_REG register + * Message + */ + +#define SHA_M_26_REG (DR_REG_SHA_BASE + 0xe8) + +/* SHA_M_26 : R/W; bitpos: [31:0]; default: 0; + * Stores the 26th 32-bit piece of the message. + */ + +#define SHA_M_26 0xFFFFFFFF +#define SHA_M_26_M (SHA_M_26_V << SHA_M_26_S) +#define SHA_M_26_V 0xFFFFFFFF +#define SHA_M_26_S 0 + +/* SHA_M_27_REG register + * Message + */ + +#define SHA_M_27_REG (DR_REG_SHA_BASE + 0xec) + +/* SHA_M_27 : R/W; bitpos: [31:0]; default: 0; + * Stores the 27th 32-bit piece of the message. + */ + +#define SHA_M_27 0xFFFFFFFF +#define SHA_M_27_M (SHA_M_27_V << SHA_M_27_S) +#define SHA_M_27_V 0xFFFFFFFF +#define SHA_M_27_S 0 + +/* SHA_M_28_REG register + * Message + */ + +#define SHA_M_28_REG (DR_REG_SHA_BASE + 0xf0) + +/* SHA_M_28 : R/W; bitpos: [31:0]; default: 0; + * Stores the 28th 32-bit piece of the message. + */ + +#define SHA_M_28 0xFFFFFFFF +#define SHA_M_28_M (SHA_M_28_V << SHA_M_28_S) +#define SHA_M_28_V 0xFFFFFFFF +#define SHA_M_28_S 0 + +/* SHA_M_29_REG register + * Message + */ + +#define SHA_M_29_REG (DR_REG_SHA_BASE + 0xf4) + +/* SHA_M_29 : R/W; bitpos: [31:0]; default: 0; + * Stores the 29th 32-bit piece of the message. + */ + +#define SHA_M_29 0xFFFFFFFF +#define SHA_M_29_M (SHA_M_29_V << SHA_M_29_S) +#define SHA_M_29_V 0xFFFFFFFF +#define SHA_M_29_S 0 + +/* SHA_M_30_REG register + * Message + */ + +#define SHA_M_30_REG (DR_REG_SHA_BASE + 0xf8) + +/* SHA_M_30 : R/W; bitpos: [31:0]; default: 0; + * Stores the 30th 32-bit piece of the message. + */ + +#define SHA_M_30 0xFFFFFFFF +#define SHA_M_30_M (SHA_M_30_V << SHA_M_30_S) +#define SHA_M_30_V 0xFFFFFFFF +#define SHA_M_30_S 0 + +/* SHA_M_31_REG register + * Message + */ + +#define SHA_M_31_REG (DR_REG_SHA_BASE + 0xfc) + +/* SHA_M_31 : R/W; bitpos: [31:0]; default: 0; + * Stores the 31th 32-bit piece of the message. + */ + +#define SHA_M_31 0xFFFFFFFF +#define SHA_M_31_M (SHA_M_31_V << SHA_M_31_S) +#define SHA_M_31_V 0xFFFFFFFF +#define SHA_M_31_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h index dca4a1d80f1..6818bc5ab9c 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h @@ -25,6 +25,8 @@ #include #include +#include "esp32c3_attr.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -119,12 +121,8 @@ #define SOC_IRAM_HIGH 0x403e0000 #define SOC_DRAM_LOW 0x3fc80000 #define SOC_DRAM_HIGH 0x3fce0000 -#define SOC_RTC_IRAM_LOW 0x50000000 /* ESP32-C3 only has RTC fast memory */ -#define SOC_RTC_IRAM_HIGH 0x50002000 -#define SOC_RTC_DRAM_LOW 0x50000000 -#define SOC_RTC_DRAM_HIGH 0x50002000 -#define SOC_RTC_DATA_LOW 0x50000000 -#define SOC_RTC_DATA_HIGH 0x50002000 +#define SOC_RTC_RAM_LOW 0x50000000 /* ESP32-C3 only has RTC fast memory */ +#define SOC_RTC_RAM_HIGH 0x50002000 /* First and last words of the D/IRAM region, for both the DRAM address as * well as the IRAM alias. @@ -257,4 +255,71 @@ #define BIT(nr) (1UL << (nr)) +/* Extract the field from the register and shift it to avoid wrong reading */ + +#define REG_MASK(_reg, _field) (((_reg) & (_field##_M)) >> (_field##_S)) + +/* Helper to place a value in a field */ + +#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M)) +#define DPORT_CPUPERIOD_SEL_80 0 +#define DPORT_CPUPERIOD_SEL_160 1 + +#define DPORT_SOC_CLK_SEL_XTAL 0 +#define DPORT_SOC_CLK_SEL_PLL 1 +#define DPORT_SOC_CLK_SEL_8M 2 + +/* Write value to register */ + +#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +/* Read value from register */ + +#define REG_READ(_r) (*(volatile uint32_t *)(_r)) + +/* Get bit or get bits from register */ + +#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) + +/* Set bit or set bits to register */ + +#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) + +/* Clear bit or clear bits of register */ + +#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) + +/* Get field from register, + * used when _f is not left shifted by _f##_S + */ + +#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +/* Set field to register, + * used when _f is not left shifted by _f##_S + */ + +#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))) + +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) /* Bit width of systimer low part */ +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) /* Bit width of systimer high part */ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ptr_rtc + * + * Description: + * Check if the buffer comes from the RTC RAM. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32c3_ptr_rtc(const void *p) +{ + return ((intptr_t)p >= SOC_RTC_RAM_LOW && + (intptr_t)p < SOC_RTC_RAM_HIGH); +} + #endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SOC_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h index 8e8dd9a18ae..34ede266fb3 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32c3_soc.h" +#include "esp32c3_soc.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h index 7d32e04fb1d..ef317cb0201 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32c3_soc.h" +#include "esp32c3_soc.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h index b9846d816b9..d4d080c54f8 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h @@ -72,7 +72,7 @@ /* Maximum value in the high 22 bits from timer counters */ #define LOW_32_MASK 0xffffffff -#define LOW_22_MASK 0x3fffff +#define LOW_22_MASK 0x003fffff #define SHIFT_32 32 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h index e31343ecfc9..511104ff112 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h @@ -2182,4 +2182,25 @@ #define UART_REG_UPDATE_V 0x00000001 #define UART_REG_UPDATE_S 31 +/* ESP32-C3 have 2 UART: UART0-1 */ + +#define ESP32C3_NUARTS 2 + +/* UART has an extra TX_WAIT_SEND state when the + * FIFO is not empty and XOFF is enabled. + */ + +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) +#define UART_FSM_IDLE (0x0) +#define UART_FSM_TX_WAIT_SEND (0xf) + +/* Software write 1 would synchronize registers into UART Core clock + * domain and would be cleared by hardware after synchronization is done. + */ + +#define UART_UPDATE (BIT(31)) +#define UART_UPDATE_M (BIT(31)) +#define UART_UPDATE_V 0x1 +#define UART_UPDATE_S 31 + #endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_UART_H */ \ No newline at end of file diff --git a/arch/risc-v/src/esp32c3/hardware/extmem_reg.h b/arch/risc-v/src/esp32c3/hardware/extmem_reg.h new file mode 100644 index 00000000000..88ce7f7c10c --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/extmem_reg.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/extmem_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0AC) +#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) + +/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1. + * The bit is used to enable clock gating to save + * power when access mmu memory 0: enable 1: disable + */ + +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 + +/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1. + * description: The bit is used to close clock gating of icache tag memory. + * 1: close gating 0: open clock gating. + */ + +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/fe_reg.h b/arch/risc-v/src/esp32c3/hardware/fe_reg.h new file mode 100644 index 00000000000..97e60498493 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/fe_reg.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/fe_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some of the RF frontend control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) +#define FE_IQ_EST_FORCE_PU (BIT(5)) +#define FE_IQ_EST_FORCE_PU_M (BIT(5)) +#define FE_IQ_EST_FORCE_PU_V 1 +#define FE_IQ_EST_FORCE_PU_S 5 + +#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) +#define FE2_TX_INF_FORCE_PU (BIT(10)) +#define FE2_TX_INF_FORCE_PU_M (BIT(10)) +#define FE2_TX_INF_FORCE_PU_V 1 +#define FE2_TX_INF_FORCE_PU_S 10 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/nrx_reg.h b/arch/risc-v/src/esp32c3/hardware/nrx_reg.h new file mode 100644 index 00000000000..68a55cc47e9 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/nrx_reg.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/nrx_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some of the Wi-Fi RX control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) +#define NRX_RX_ROT_FORCE_PU (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_M (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_V 1 +#define NRX_RX_ROT_FORCE_PU_S 5 +#define NRX_VIT_FORCE_PU (BIT(3)) +#define NRX_VIT_FORCE_PU_M (BIT(3)) +#define NRX_VIT_FORCE_PU_V 1 +#define NRX_VIT_FORCE_PU_S 3 +#define NRX_DEMAP_FORCE_PU (BIT(1)) +#define NRX_DEMAP_FORCE_PU_M (BIT(1)) +#define NRX_DEMAP_FORCE_PU_V 1 +#define NRX_DEMAP_FORCE_PU_S 1 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h b/arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h new file mode 100644 index 00000000000..375dc1a4cde --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h @@ -0,0 +1,75 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H_ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register definitions for digital PLL (BBPLL). This file lists + * register fields of BBPLL, located on an internal configuration bus. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_OC_VCO_DBIAS 9 +#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1 +#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H_ */ \ No newline at end of file diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h b/arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h new file mode 100644 index 00000000000..24807b3f1f9 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Analog function control register */ + +#define I2C_MST_ANA_CONF0_REG 0x6000E040 +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) + +/* ROM functions which read/write internal control bus */ + +extern uint8_t rom_i2c_readreg(uint8_t block, uint8_t host_id, + uint8_t reg_add); +extern uint8_t rom_i2c_readreg_mask(uint8_t block, uint8_t host_id, + uint8_t reg_add, uint8_t msb, uint8_t lsb); +extern void rom_i2c_writereg(uint8_t block, uint8_t host_id, + uint8_t reg_add, uint8_t data); +extern void rom_i2c_writereg_mask(uint8_t block, uint8_t host_id, + uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); + +/* Convenience macros for the above functions, these use register + * definitions from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/ + * regi2c_bias.h header files. + */ + +#define REGI2C_WRITE_MASK(block, reg_add, indata) \ + rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) + +#define REGI2C_READ_MASK(block, reg_add) \ + rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) + +#define REGI2C_WRITE(block, reg_add, indata) \ + rom_i2c_writereg(block, block##_HOSTID, reg_add, indata) + +#define REGI2C_READ(block, reg_add) \ + rom_i2c_readreg(block, block##_HOSTID, reg_add) + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h b/arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h new file mode 100644 index 00000000000..027f4250a2d --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H_ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_DIG_REG 0x6D +#define I2C_DIG_REG_HOSTID 0 + +#define I2C_DIG_REG_EXT_RTC_DREG 4 +#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0 + +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_EXT_DIG_DREG 6 +#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0 + +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_XPD_RTC_REG 13 +#define I2C_DIG_REG_XPD_RTC_REG_MSB 2 +#define I2C_DIG_REG_XPD_RTC_REG_LSB 2 + +#define I2C_DIG_REG_XPD_DIG_REG 13 +#define I2C_DIG_REG_XPD_DIG_REG_MSB 3 +#define I2C_DIG_REG_XPD_DIG_REG_LSB 3 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h b/arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h new file mode 100644 index 00000000000..40298635437 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H_ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register definitions for analog to calibrate o_code for getting a more + * precise voltage. This file lists register fields of low power dbais, + * located on an internal configuration bus. + */ + +#define I2C_ULP 0x61 +#define I2C_ULP_HOSTID 0 + +#define I2C_ULP_IR_FORCE_XPD_CK 0 +#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2 +#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h b/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h new file mode 100644 index 00000000000..6447c395130 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_SARADC_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_SARADC_H_ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/** + * Register definitions for analog to calibrate initial code for getting a + * more precise voltage of SAR ADC. + */ + +#define I2C_ADC (0x69) +#define I2C_ADC_HOSTID (0) + +#define I2C_ADC1_ENCAL_GND (0x7) +#define I2C_ADC1_ENCAL_GND_MSB (0x5) +#define I2C_ADC1_ENCAL_GND_LSB (0x5) + +#define I2C_ADC1_INITVAL_L (0x0) +#define I2C_ADC1_INITVAL_L_MSB (0x7) +#define I2C_ADC1_INITVAL_L_LSB (0x0) + +#define I2C_ADC1_INITVAL_H (0x1) +#define I2C_ADC1_INITVAL_H_MSB (0x3) +#define I2C_ADC1_INITVAL_H_LSB (0x0) + +#define I2C_ADC1_DEF (0x2) +#define I2C_ADC1_DEF_MSB (0x6) +#define I2C_ADC1_DEF_LSB (0x4) + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_SARADC_H_ */ diff --git a/arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h b/arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h new file mode 100644 index 00000000000..0e479a684ab --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H_ +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000) +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0DC) + +/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1. + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H_ */ diff --git a/arch/risc-v/src/fe310/fe310_head.S b/arch/risc-v/src/fe310/fe310_head.S index 642f3383250..5e74364e474 100644 --- a/arch/risc-v/src/fe310/fe310_head.S +++ b/arch/risc-v/src/fe310/fe310_head.S @@ -57,19 +57,6 @@ __start: la t0, __trap_vec csrw mtvec, t0 -#ifdef CONFIG_STACK_COLORATION - /* t0 = start of IDLE stack; t1 = top of the stack; t2 = coloration */ - - la t0, FE310_IDLESTACK_BASE - la t1, FE310_IDLESTACK_TOP - li t2, STACK_COLOR - -1: - sw t2, 0(t0) - addi t0, t0, 4 - bne t0, t1, 1b -#endif - /* Jump to __fe310_start */ jal x1, __fe310_start @@ -139,7 +126,7 @@ exception_common: mv a1, sp /* context = sp */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 /* Switch to interrupt stack */ lui sp, %hi(g_intstacktop) diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c index 7a496081467..258bb3286d3 100644 --- a/arch/risc-v/src/fe310/fe310_irq.c +++ b/arch/risc-v/src/fe310/fe310_irq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -59,8 +60,8 @@ void up_irqinitialize(void) /* Colorize the interrupt stack for debug purposes */ -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 - size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); riscv_stack_color((FAR void *)&g_intstackalloc, intstack_size); #endif @@ -197,39 +198,6 @@ void riscv_ack_irq(int irq) board_autoled_on(LED_CPU); } -/**************************************************************************** - * Name: up_irq_save - * - * Description: - * Return the current interrupt state and disable interrupts - * - ****************************************************************************/ - -irqstate_t up_irq_save(void) -{ - uint32_t oldstat; - - /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ - - asm volatile ("csrrc %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE)); - return oldstat; -} - -/**************************************************************************** - * Name: up_irq_restore - * - * Description: - * Restore previous IRQ mask state - * - ****************************************************************************/ - -void up_irq_restore(irqstate_t flags) -{ - /* Write flags to mstatus */ - - asm volatile("csrw mstatus, %0" : /* no output */ : "r" (flags)); -} - /**************************************************************************** * Name: up_irq_enable * diff --git a/arch/risc-v/src/fe310/fe310_serial.c b/arch/risc-v/src/fe310/fe310_serial.c index 1c53ee4fdb4..c234b4d8360 100644 --- a/arch/risc-v/src/fe310/fe310_serial.c +++ b/arch/risc-v/src/fe310/fe310_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/k210/Make.defs b/arch/risc-v/src/k210/Make.defs index 5c5cb22de5f..56c986d35bc 100644 --- a/arch/risc-v/src/k210/Make.defs +++ b/arch/risc-v/src/k210/Make.defs @@ -29,7 +29,7 @@ CMN_ASRCS += riscv_testset.S # Specify C code within the common directory to be included CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_fault.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c @@ -57,7 +57,8 @@ CHIP_CSRCS += k210_cpupause.c k210_cpustart.c endif ifeq ($(CONFIG_BUILD_PROTECTED),y) -CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c +CMN_CSRCS += riscv_task_start.c +CMN_CSRCS += riscv_pthread_start.c riscv_pthread_exit.c CMN_CSRCS += riscv_signal_dispatch.c CMN_UASRCS += riscv_signal_handler.S diff --git a/arch/risc-v/src/k210/k210_allocateheap.c b/arch/risc-v/src/k210/k210_allocateheap.c index b435a4aadcc..a45f4f81db0 100644 --- a/arch/risc-v/src/k210/k210_allocateheap.c +++ b/arch/risc-v/src/k210/k210_allocateheap.c @@ -24,10 +24,13 @@ #include +#include + #include #include #include +#include #include #include "k210.h" @@ -42,6 +45,28 @@ * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)K210_HEAP_START; + *heap_size = CONFIG_RAM_END - K210_HEAP_START; +} + /**************************************************************************** * Name: up_allocate_kheap * diff --git a/arch/risc-v/src/k210/k210_cpuidlestack.c b/arch/risc-v/src/k210/k210_cpuidlestack.c index bb6901e9d38..eec32a9e62a 100644 --- a/arch/risc-v/src/k210/k210_cpuidlestack.c +++ b/arch/risc-v/src/k210/k210_cpuidlestack.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/risc-v/src/k210/k210_cpustart.c b/arch/risc-v/src/k210/k210_cpustart.c index 89a88c71176..c3e47af4062 100644 --- a/arch/risc-v/src/k210/k210_cpustart.c +++ b/arch/risc-v/src/k210/k210_cpustart.c @@ -112,6 +112,17 @@ void k210_cpu_boot(int cpu) showprogress('b'); DPRINTF("CPU%d Started\n", this_cpu()); +#ifdef CONFIG_STACK_COLORATION + FAR struct tcb_s *tcb = this_task(); + + /* If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + + riscv_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size); +#endif + /* TODO: Setup FPU */ /* Clear machine software interrupt for CPU(cpu) */ diff --git a/arch/risc-v/src/k210/k210_head.S b/arch/risc-v/src/k210/k210_head.S index f5bdc32ba9a..10f48f77338 100644 --- a/arch/risc-v/src/k210/k210_head.S +++ b/arch/risc-v/src/k210/k210_head.S @@ -72,25 +72,6 @@ __start: la t0, __trap_vec csrw mtvec, t0 -#ifdef CONFIG_STACK_COLORATION - /* t0 = start of IDLE stack; t1 = top of the stack; t2 = coloration */ - - bnez a0, 3f /* a0: hartid */ - la t0, K210_IDLESTACK0_BASE - j 4f -3: - la t0, K210_IDLESTACK1_BASE -4: - - mv t1, sp - li t2, STACK_COLOR - -5: - sw t2, 0(t0) - addi t0, t0, 4 - bne t0, t1, 5b -#endif - /* Jump to __k210_start with mhartid */ j __k210_start @@ -170,7 +151,7 @@ normal_irq: mv a1, sp /* context = sp */ -#if CONFIG_ARCH_INTERRUPTSTACK > 7 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 /* Load mhartid (cpuid) */ csrr s0, mhartid @@ -182,7 +163,7 @@ normal_irq: j 4f 3: la sp, g_intstacktop - addi sp, sp, -(CONFIG_ARCH_INTERRUPTSTACK & ~7) + addi sp, sp, -(CONFIG_ARCH_INTERRUPTSTACK & ~15) 4: #endif diff --git a/arch/risc-v/src/k210/k210_irq.c b/arch/risc-v/src/k210/k210_irq.c index 4c0a484db7c..2ebaa5be32e 100644 --- a/arch/risc-v/src/k210/k210_irq.c +++ b/arch/risc-v/src/k210/k210_irq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -80,8 +81,13 @@ void up_irqinitialize(void) /* Colorize the interrupt stack for debug purposes */ -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 7 - size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~7); +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 + size_t intstack_size = 0; +#ifndef CONFIG_SMP + intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); +#else + intstack_size = ((CONFIG_ARCH_INTERRUPTSTACK * CONFIG_SMP_NCPUS) & ~15); +#endif riscv_stack_color((FAR void *)&g_intstackalloc, intstack_size); #endif @@ -248,39 +254,6 @@ void riscv_ack_irq(int irq) { } -/**************************************************************************** - * Name: up_irq_save - * - * Description: - * Return the current interrupt state and disable interrupts - * - ****************************************************************************/ - -irqstate_t up_irq_save(void) -{ - uint64_t oldstat; - - /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ - - asm volatile ("csrrc %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE)); - return oldstat; -} - -/**************************************************************************** - * Name: up_irq_restore - * - * Description: - * Restore previous IRQ mask state - * - ****************************************************************************/ - -void up_irq_restore(irqstate_t flags) -{ - /* Write flags to mstatus */ - - asm volatile("csrw mstatus, %0" : /* no output */ : "r" (flags)); -} - /**************************************************************************** * Name: up_irq_enable * diff --git a/arch/risc-v/src/k210/k210_memorymap.h b/arch/risc-v/src/k210/k210_memorymap.h index 18365f4832d..4b7c3ecfee5 100644 --- a/arch/risc-v/src/k210/k210_memorymap.h +++ b/arch/risc-v/src/k210/k210_memorymap.h @@ -51,9 +51,9 @@ extern uintptr_t *_default_stack_limit; #define K210_IDLESTACK1_TOP (K210_IDLESTACK1_BASE + CONFIG_IDLETHREAD_STACKSIZE) #if defined(CONFIG_SMP) && (CONFIG_SMP_NCPUS > 1) -#define K210_IDLESTACK_TOP (K210_IDLESTACK1_TOP) +#define K210_HEAP_START (K210_IDLESTACK1_TOP) #else -#define K210_IDLESTACK_TOP (K210_IDLESTACK0_TOP) +#define K210_HEAP_START (K210_IDLESTACK0_TOP) #endif #endif /* _ARCH_RISCV_SRC_K210_K210_MEMORYMAP_H */ diff --git a/arch/risc-v/src/k210/k210_serial.c b/arch/risc-v/src/k210/k210_serial.c index a8bcc35a60f..85fbc216719 100644 --- a/arch/risc-v/src/k210/k210_serial.c +++ b/arch/risc-v/src/k210/k210_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/k210/k210_start.c b/arch/risc-v/src/k210/k210_start.c index 7c1113ae44f..427c7143cbd 100644 --- a/arch/risc-v/src/k210/k210_start.c +++ b/arch/risc-v/src/k210/k210_start.c @@ -48,17 +48,11 @@ * Public Data ****************************************************************************/ -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. +/* NOTE: g_idle_topstack needs to point the top of the idle stack + * for CPU0 and this value is used in up_initial_state() */ -uintptr_t g_idle_topstack = K210_IDLESTACK_TOP; +uintptr_t g_idle_topstack = K210_IDLESTACK0_TOP; volatile bool g_serial_ok = false; extern void k210_cpu_boot(uint32_t); diff --git a/arch/risc-v/src/litex/litex_head.S b/arch/risc-v/src/litex/litex_head.S index c44e9895bfc..e9a514e5949 100644 --- a/arch/risc-v/src/litex/litex_head.S +++ b/arch/risc-v/src/litex/litex_head.S @@ -126,7 +126,7 @@ exception_common: mv a1, sp /* context = sp */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 /* Switch to interrupt stack */ lui sp, %hi(g_intstacktop) diff --git a/arch/risc-v/src/litex/litex_irq.c b/arch/risc-v/src/litex/litex_irq.c index 150783837ab..0751131925b 100644 --- a/arch/risc-v/src/litex/litex_irq.c +++ b/arch/risc-v/src/litex/litex_irq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -58,8 +59,8 @@ void up_irqinitialize(void) /* Colorize the interrupt stack for debug purposes */ -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 - size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); riscv_stack_color((FAR void *)&g_intstackalloc, intstack_size); #endif @@ -202,39 +203,6 @@ void riscv_ack_irq(int irq) { } -/**************************************************************************** - * Name: up_irq_save - * - * Description: - * Return the current interrupt state and disable interrupts - * - ****************************************************************************/ - -irqstate_t up_irq_save(void) -{ - uint32_t oldstat; - - /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ - - asm volatile ("csrrc %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE)); - return oldstat; -} - -/**************************************************************************** - * Name: up_irq_restore - * - * Description: - * Restore previous IRQ mask state - * - ****************************************************************************/ - -void up_irq_restore(irqstate_t flags) -{ - /* Write flags to mstatus */ - - asm volatile("csrw mstatus, %0" : /* no output */ : "r" (flags)); -} - /**************************************************************************** * Name: up_irq_enable * diff --git a/arch/risc-v/src/litex/litex_serial.c b/arch/risc-v/src/litex/litex_serial.c index 9916d030e13..05bfe30899d 100644 --- a/arch/risc-v/src/litex/litex_serial.c +++ b/arch/risc-v/src/litex/litex_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig new file mode 100755 index 00000000000..dc8ced74850 --- /dev/null +++ b/arch/risc-v/src/mpfs/Kconfig @@ -0,0 +1,119 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "Polarfire Configuration Options" + +config MPFS_ENABLE_DPFPU + bool "MPFS DP_FPU Support" + default n + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + ---help--- + Enable the RISC-V Double-Precision Floating Point Unit (DP-FPU). + +menu "MPFS Peripheral Support" + +# These "hidden" settings determine whether a peripheral option is available +# for the selected MCU + +config MPFS_HAVE_UART0 + bool + default n + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config MPFS_HAVE_UART1 + bool + default n + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config MPFS_HAVE_UART2 + bool + default n + select UART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config MPFS_HAVE_UART3 + bool + default n + select UART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config MPFS_HAVE_UART4 + bool + default n + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +# These are the peripheral selections proper + +config MPFS_SPI0 + bool "SPI 0" + default n + +config MPFS_SPI1 + bool "SPI 1" + default n + +config MPFS_UART0 + bool "UART 0" + default n + select ARCH_HAVE_UART0 + select ARCH_HAVE_SERIAL_TERMIOS + select MPFS_HAVE_UART0 + +config MPFS_UART1 + bool "UART 1" + default n + select ARCH_HAVE_UART1 + select ARCH_HAVE_SERIAL_TERMIOS + select MPFS_HAVE_UART1 + +config MPFS_UART2 + bool "UART 2" + default n + select ARCH_HAVE_UART2 + select ARCH_HAVE_SERIAL_TERMIOS + select MPFS_HAVE_UART2 + +config MPFS_UART3 + bool "UART 3" + default n + select ARCH_HAVE_UART3 + select ARCH_HAVE_SERIAL_TERMIOS + select MPFS_HAVE_UART3 + +config MPFS_UART4 + bool "UART 4" + default n + select ARCH_HAVE_UART4 + select ARCH_HAVE_SERIAL_TERMIOS + select MPFS_HAVE_UART4 + +config MPFS_I2C0 + bool "I2C 0" + select ARCH_HAVE_I2CRESET + default n + +config MPFS_I2C1 + bool "I2C 1" + select ARCH_HAVE_I2CRESET + default n + +endmenu + +config MPFS_DMA + bool "MPFS DMA (PDMA)" + default n + select ARCH_DMA + ---help--- + Enable DMA Support. MPFS DMA is Memory-to-Memory only. + +menu "MPFS Others" + +endmenu + + diff --git a/arch/risc-v/src/mpfs/Make.defs b/arch/risc-v/src/mpfs/Make.defs new file mode 100755 index 00000000000..35bbc0019c7 --- /dev/null +++ b/arch/risc-v/src/mpfs/Make.defs @@ -0,0 +1,75 @@ +############################################################################ +# arch/risc-v/src/mpfs/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Specify our HEAD assembly file. This will be linked as +# the first object file, so it will appear at address 0 +HEAD_ASRC = mpfs_vectors.S + +# Specify our general Assembly files +CHIP_ASRCS = mpfs_head.S + +# Specify C code within the common directory to be included +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_mdelay.c riscv_copyfullstate.c + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += riscv_checkstack.c +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CMN_ASRCS += riscv_fpu.S +endif + +ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) +CMN_CSRCS += riscv_vfork.c +endif + +# Specify our C code within this directory to be included +CHIP_CSRCS = mpfs_allocateheap.c mpfs_clockconfig.c +CHIP_CSRCS += mpfs_idle.c mpfs_irq.c mpfs_irq_dispatch.c +CHIP_CSRCS += mpfs_lowputc.c mpfs_serial.c +CHIP_CSRCS += mpfs_start.c mpfs_timerisr.c +CHIP_CSRCS += mpfs_gpio.c mpfs_systemreset.c + +ifeq ($(CONFIG_MPFS_DMA),y) +CHIP_CSRCS += mpfs_dma.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c +CMN_CSRCS += riscv_signal_dispatch.c riscv_pmp.c +CMN_UASRCS += riscv_signal_handler.S + +CHIP_CSRCS += mpfs_userspace.c +endif + +ifeq ($(CONFIG_SPI),y) +CHIP_CSRCS += mpfs_spi.c +endif + +ifeq ($(CONFIG_I2C),y) +CHIP_CSRCS += mpfs_i2c.c +endif diff --git a/arch/risc-v/src/mpfs/chip.h b/arch/risc-v/src/mpfs/chip.h new file mode 100755 index 00000000000..960c76b8f23 --- /dev/null +++ b/arch/risc-v/src/mpfs/chip.h @@ -0,0 +1,32 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_CHIP_H +#define __ARCH_RISCV_SRC_MPFS_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "mpfs_memorymap.h" + +#endif /* __ARCH_RISCV_SRC_MPFS_CHIP_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_clint.h b/arch/risc-v/src/mpfs/hardware/mpfs_clint.h new file mode 100755 index 00000000000..a15d8492679 --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_clint.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_clint.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MPFS_CLINT_MSIP0 (MPFS_CLINT_BASE + 0x0000) +#define MPFS_CLINT_MSIP1 (MPFS_CLINT_BASE + 0x0004) +#define MPFS_CLINT_MSIP2 (MPFS_CLINT_BASE + 0x0008) +#define MPFS_CLINT_MSIP3 (MPFS_CLINT_BASE + 0x000C) +#define MPFS_CLINT_MSIP4 (MPFS_CLINT_BASE + 0x0010) + +#define MPFS_CLINT_MTIMECMP0 (MPFS_CLINT_BASE + 0x4000) +#define MPFS_CLINT_MTIMECMP1 (MPFS_CLINT_BASE + 0x4008) +#define MPFS_CLINT_MTIMECMP2 (MPFS_CLINT_BASE + 0x4010) +#define MPFS_CLINT_MTIMECMP3 (MPFS_CLINT_BASE + 0x4018) +#define MPFS_CLINT_MTIMECMP4 (MPFS_CLINT_BASE + 0x4020) + +#define MPFS_CLINT_MTIME (MPFS_CLINT_BASE + 0xbff8) + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_dma.h b/arch/risc-v/src/mpfs/hardware/mpfs_dma.h new file mode 100755 index 00000000000..422652966fc --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_dma.h @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_dma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_DMA_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/mpfs_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define MPFS_DMA_CONTROL_OFFSET 0x0000 /* Channel control register */ +#define MPFS_DMA_NEXT_CONFIG_OFFSET 0x0004 /* Next transfer type */ +#define MPFS_DMA_NEXT_BYTES_OFFSET 0x0008 /* Number of bytes to move */ +#define MPFS_DMA_NEXT_DESTINATION_OFFSET 0x0010 /* Destination start address */ +#define MPFS_DMA_NEXT_SOURCE_OFFSET 0x0018 /* Source start address */ +#define MPFS_DMA_EXEC_CONFIG_OFFSET 0x0104 /* Active transfer type */ +#define MPFS_DMA_EXEC_BYTES_OFFSET 0x0108 /* Number of bytes remaining */ +#define MPFS_DMA_EXEC_DESTINATION_OFFSET 0x0110 /* Destination current address */ +#define MPFS_DMA_EXEC_SOURCE_OFFSET 0x0118 /* Source current address */ + +#define MPFS_DMA_CHANNEL_OFFSET 0x1000 /* Offset to channels */ + +#define MPFS_DMA_REG_OFFSET(x) \ + (uint64_t)(MPFS_PDMA_BASE + (MPFS_DMA_CHANNEL_OFFSET * (x))) + +/* Register bit field definitions *******************************************/ + +/* Control register */ + +/* Indicates that the channel is in use. Setting this bit clears all of the + * channel’s Next registers (NextConfig, NextBytes, NextDestination, and + * NextSource). This bit can only be cleared when run (CR bit 0) is low. + */ + +#define DMA_CONTROL_CLAIM_SHIFT (0) /* Bit: 0: claim */ +#define DMA_CONTROL_CLAIM_MASK (1 << DMA_CONTROL_CLAIM_SHIFT) +# define DMA_CONTROL_CLAIM (0 << DMA_CONTROL_CLAIM_SHIFT) + +/* Setting this bit starts a DMA transfer by copying the Next registers + * into their Exec counterparts. + */ + +#define DMA_CONTROL_RUN_SHIFT (1) /* Bit: 1: run */ +#define DMA_CONTROL_RUN_MASK (1 << DMA_CONTROL_RUN_SHIFT) +# define DMA_CONTROL_RUN (1 << DMA_CONTROL_RUN_SHIFT) + +/* Setting this bit will trigger the channel’s Done interrupt once + * a transfer is complete. + */ + +#define DMA_CONTROL_DONEIE_SHIFT (14) /* Bit: 14: Done Irq enable */ +#define DMA_CONTROL_DONEIE_MASK (1 << DMA_CONTROL_DONEIE_SHIFT) +# define DMA_CONTROL_DONEIE (1 << DMA_CONTROL_DONEIE_SHIFT) + +/* Setting this bit will trigger the channel’s Done interrupt once + * a transfer is complete. + */ + +#define DMA_CONTROL_ERRORIE_SHIFT (15) /* Bit: 15: Error Irq enable */ +#define DMA_CONTROL_ERRORIE_MASK (1 << DMA_CONTROL_ERRORIE_SHIFT) +# define DMA_CONTROL_ERRORIE (1 << DMA_CONTROL_ERRORIE_SHIFT) + +/* Indicates that a transfer has completed since the channel was claimed */ + +#define DMA_CONTROL_DONE_SHIFT (30) /* Bit: 30: Done */ +#define DMA_CONTROL_DONE_MASK (1 << DMA_CONTROL_DONE_SHIFT) +# define DMA_CONTROL_DONE (1 << DMA_CONTROL_DONE_SHIFT) + +/* Indicates that a transfer error has occurred since the channel + * was claimed + */ + +#define DMA_CONTROL_ERROR_SHIFT (31) /* Bit: 31: Error */ +#define DMA_CONTROL_ERROR_MASK (1 << DMA_CONTROL_ERROR_SHIFT) +# define DMA_CONTROL_ERROR (1 << DMA_CONTROL_ERROR_SHIFT) + +/* Channel Next Configuration Register */ + +/* If set, the Exec registers are reloaded from the Next registers once a + * transfer is complete. The repeat bit must be cleared by software + * for the sequence to stop + */ + +#define DMA_NEXT_CONFIG_REPEAT_SHIFT (2) /* Bit: 2: repeat */ +#define DMA_NEXT_CONFIG_REPEAT_MASK (1 << DMA_NEXT_CONFIG_REPEAT_SHIFT) +# define DMA_NEXT_CONFIG_REPEAT (1 << DMA_NEXT_CONFIG_REPEAT_SHIFT) + +/* Enforces strict ordering by only allowing one of each transfer type + * in-flight at a time + */ + +#define DMA_NEXT_CONFIG_ORDER_SHIFT (3) /* Bit: 3: order */ +#define DMA_NEXT_CONFIG_ORDER_MASK (1 << DMA_NEXT_CONFIG_ORDER_SHIFT) +# define DMA_NEXT_CONFIG_ORDER (1 << DMA_NEXT_CONFIG_ORDER_SHIFT) + +/* WSIZE and RSIZE. Base 2 Logarithm of DMA transaction sizes. + * Example: 0 is 1 byte, 3 is 8 bytes, 5 is 32 bytes + * These fields are WARL (Write-Any Read-Legal), so the actual size used + * can be determined by reading the field after writing the requested size. + * */ + +#define DMA_NEXT_CONFIG_WSIZE_SHIFT (24) /* Bits: 24-27: write size */ +#define DMA_NEXT_CONFIG_WSIZE_MASK (15 << DMA_NEXT_CONFIG_WSIZE_SHIFT) +# define DMA_NEXT_CONFIG_WSIZE(x) (x << DMA_NEXT_CONFIG_WSIZE_SHIFT) + +#define DMA_NEXT_CONFIG_RSIZE_SHIFT (28) /* Bits: 28-31: read size */ +#define DMA_NEXT_CONFIG_RSIZE_MASK (15 << DMA_NEXT_CONFIG_RSIZE_SHIFT) +# define DMA_NEXT_CONFIG_RSIZE(x) (x << DMA_NEXT_CONFIG_RSIZE_SHIFT) + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_DMA_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_gpio.h b/arch/risc-v/src/mpfs/hardware/mpfs_gpio.h new file mode 100755 index 00000000000..6f40fcae9bb --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_gpio.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/mpfs_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define MPFS_GPIO_CONFIG_0_OFFSET 0x0000 /* GPIO Config 0 */ +#define MPFS_GPIO_CONFIG_1_OFFSET 0x0004 /* GPIO Config 1 */ +#define MPFS_GPIO_CONFIG_2_OFFSET 0x0008 /* GPIO Config 2 */ +#define MPFS_GPIO_CONFIG_3_OFFSET 0x000C /* GPIO Config 3 */ +#define MPFS_GPIO_CONFIG_4_OFFSET 0x0010 /* GPIO Config 4 */ +#define MPFS_GPIO_CONFIG_5_OFFSET 0x0014 /* GPIO Config 5 */ +#define MPFS_GPIO_CONFIG_6_OFFSET 0x0018 /* GPIO Config 6 */ +#define MPFS_GPIO_CONFIG_7_OFFSET 0x001C /* GPIO Config 7 */ +#define MPFS_GPIO_CONFIG_8_OFFSET 0x0020 /* GPIO Config 8 */ +#define MPFS_GPIO_CONFIG_9_OFFSET 0x0024 /* GPIO Config 9 */ +#define MPFS_GPIO_CONFIG_10_OFFSET 0x0028 /* GPIO Config 10 */ +#define MPFS_GPIO_CONFIG_11_OFFSET 0x002C /* GPIO Config 11 */ +#define MPFS_GPIO_CONFIG_12_OFFSET 0x0020 /* GPIO Config 12 */ +#define MPFS_GPIO_CONFIG_13_OFFSET 0x0024 /* GPIO Config 13 */ +#define MPFS_GPIO_CONFIG_14_OFFSET 0x0028 /* GPIO Config 14 */ +#define MPFS_GPIO_CONFIG_15_OFFSET 0x002C /* GPIO Config 15 */ +#define MPFS_GPIO_CONFIG_16_OFFSET 0x0040 /* GPIO Config 16 */ +#define MPFS_GPIO_CONFIG_17_OFFSET 0x0044 /* GPIO Config 17 */ +#define MPFS_GPIO_CONFIG_18_OFFSET 0x0048 /* GPIO Config 18 */ +#define MPFS_GPIO_CONFIG_19_OFFSET 0x004C /* GPIO Config 19 */ +#define MPFS_GPIO_CONFIG_20_OFFSET 0x0050 /* GPIO Config 20 */ +#define MPFS_GPIO_CONFIG_21_OFFSET 0x0054 /* GPIO Config 21 */ +#define MPFS_GPIO_CONFIG_22_OFFSET 0x0058 /* GPIO Config 22 */ +#define MPFS_GPIO_CONFIG_23_OFFSET 0x005C /* GPIO Config 23 */ +#define MPFS_GPIO_CONFIG_24_OFFSET 0x0060 /* GPIO Config 24 */ +#define MPFS_GPIO_CONFIG_25_OFFSET 0x0064 /* GPIO Config 25 */ +#define MPFS_GPIO_CONFIG_26_OFFSET 0x0068 /* GPIO Config 26 */ +#define MPFS_GPIO_CONFIG_27_OFFSET 0x006C /* GPIO Config 27 */ +#define MPFS_GPIO_CONFIG_28_OFFSET 0x0070 /* GPIO Config 28 */ +#define MPFS_GPIO_CONFIG_29_OFFSET 0x0074 /* GPIO Config 29 */ +#define MPFS_GPIO_CONFIG_30_OFFSET 0x0078 /* GPIO Config 30 */ +#define MPFS_GPIO_CONFIG_31_OFFSET 0x007C /* GPIO Config 31 */ +#define MPFS_GPIO_INTR_OFFSET 0x0080 /* GPIO Irq state */ +#define MPFS_GPIO_GPIN_OFFSET 0x0084 /* GPIO Input states */ +#define MPFS_GPIO_GPOUT_OFFSET 0x0088 /* GPIO Ouput states */ +#define MPFS_GPIO_CONFIG_ALL_OFFSET 0x008C /* GPIO set all configs */ +#define MPFS_GPIO_CONFIG_BYTE0_OFFSET 0x0090 /* GPIO set all configs in byte-0 */ +#define MPFS_GPIO_CONFIG_BYTE1_OFFSET 0x0094 /* GPIO set all configs in byte-1 */ +#define MPFS_GPIO_CONFIG_BYTE2_OFFSET 0x0098 /* GPIO set all configs in byte-3 */ +#define MPFS_GPIO_CONFIG_BYTE3_OFFSET 0x009C /* GPIO set all configs in byte-4 */ +#define MPFS_GPIO_CLEAR_BITS_OFFSET 0x00A0 /* GPIO Clear bits */ +#define MPFS_GPIO_SET_BITS_OFFSET 0x00A4 /* GPIO Set bits */ + +/* Register bit field definitions *******************************************/ + +/* CONFIG_X */ + +#define GPIO_CONFIG_EN_OUT (1 << 0) /* Output enable */ +#define GPIO_CONFIG_EN_IN (1 << 1) /* Input enable */ +#define GPIO_CONFIG_EN_OE_BUF (1 << 2) /* Output buffer enable */ +#define GPIO_CONFIG_EN_INT (1 << 3) /* Interrupt enable */ +#define GPIO_CONFIG_INT_SHIFT (5) /* Bits: 5-7: Interrupt Types */ +#define GPIO_CONFIG_INT_MASK (7) +# define GPIO_CONFIG_INT_HIGH (0 << GPIO_CONFIG_INT_SHIFT) +# define GPIO_CONFIG_INT_LOW (1 << GPIO_CONFIG_INT_SHIFT) +# define GPIO_CONFIG_INT_EDGE_POS (2 << GPIO_CONFIG_INT_SHIFT) +# define GPIO_CONFIG_INT_EDGE_NEG (3 << GPIO_CONFIG_INT_SHIFT) +# define GPIO_CONFIG_INT_EDGE_BOTH (4 << GPIO_CONFIG_INT_SHIFT) + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_i2c.h b/arch/risc-v/src/mpfs/hardware/mpfs_i2c.h new file mode 100755 index 00000000000..d90fcde550a --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_i2c.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_i2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_I2C_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_I2C_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MPFS_I2C_CTRL_CR2 7 +#define MPFS_I2C_CTRL_ENS1 6 +#define MPFS_I2C_CTRL_STA 5 +#define MPFS_I2C_CTRL_STO 4 +#define MPFS_I2C_CTRL_SI 3 +#define MPFS_I2C_CTRL_AA 2 +#define MPFS_I2C_CTRL_CR1 1 +#define MPFS_I2C_CTRL_CR0 0 + +#define MPFS_I2C_CTRL_CR2_MASK (1 << 7) +#define MPFS_I2C_CTRL_ENS1_MASK (1 << 6) +#define MPFS_I2C_CTRL_STA_MASK (1 << 5) +#define MPFS_I2C_CTRL_STO_MASK (1 << 4) +#define MPFS_I2C_CTRL_SI_MASK (1 << 3) +#define MPFS_I2C_CTRL_AA_MASK (1 << 2) +#define MPFS_I2C_CTRL_CR1_MASK (1 << 1) +#define MPFS_I2C_CTRL_CR0_MASK (1 << 0) + +#define MPFS_I2C_ST_RESET_ACTIVATED 0xD0 /* Master reset is activated */ +#define MPFS_I2C_ST_RX_DATA_NACK 0x58 /* Data received, NACK sent */ +#define MPFS_I2C_ST_RX_DATA_ACK 0x50 /* Data received, ACK sent */ +#define MPFS_I2C_ST_SLAR_NACK 0x48 /* SLA+R sent, NACK'ed */ +#define MPFS_I2C_ST_SLAR_ACK 0x40 /* SLA+R sent, ACK'ed */ +#define MPFS_I2C_ST_LOST_ARB 0x38 /* Master lost arbitration */ +#define MPFS_I2C_ST_TX_DATA_NACK 0x30 /* Data sent, NACK'ed */ +#define MPFS_I2C_ST_TX_DATA_ACK 0x28 /* Data sent, ACK'ed */ +#define MPFS_I2C_ST_SLAW_NACK 0x20 /* SLA + W sent, nack received */ +#define MPFS_I2C_ST_SLAW_ACK 0x18 /* SLA + W sent, ack received */ +#define MPFS_I2C_ST_RESTART 0x10 /* Repeated start */ +#define MPFS_I2C_ST_START 0x08 /* Start condition sent */ +#define MPFS_I2C_ST_BUS_ERROR 0x00 /* Bus error */ + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_I2C_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_memorymap.h b/arch/risc-v/src/mpfs/hardware/mpfs_memorymap.h new file mode 100755 index 00000000000..ff7c0e6f873 --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_memorymap.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_MEMORYMAP_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Base Address ****************************************************/ + +#define MPFS_CLINT_BASE (0x02000000UL) +#define MPFS_PDMA_BASE (0x03000000UL) +#define MPFS_PLIC_BASE (0x0C000000UL) + +#define MPFS_UART0_LO_BASE (0x20000000UL) +#define MPFS_WDOG0_LO_BASE (0x20001000UL) +#define MPFS_SYSREG_BASE (0x20002000UL) +#define MPFS_SYSREGSCB_BASE (0x20003000UL) +#define MPFS_AXISW_BASE (0x20004000UL) +#define MPFS_MPUCFG_BASE (0x20005000UL) +#define MPFS_FMETER_BASE (0x20006000UL) +#define MPFS_CFG_DDR_SGMII_PHY_BASE (0x20007000UL) +#define MPFS_EMMC_SD_BASE (0x20008000UL) +#define MPFS_DDRCFG_BASE (0x20080000UL) +#define MPFS_UART1_LO_BASE (0x20100000UL) +#define MPFS_WDOG1_LO_BASE (0x20101000UL) +#define MPFS_UART2_LO_BASE (0x20102000UL) +#define MPFS_WDOG2_LO_BASE (0x20103000UL) +#define MPFS_UART3_LO_BASE (0x20104000UL) +#define MPFS_WDOG3_LO_BASE (0x20105000UL) +#define MPFS_UART4_LO_BASE (0x20106000UL) +#define MPFS_WDOG4_LO_BASE (0x20107000UL) +#define MPFS_SPI0_LO_BASE (0x20108000UL) +#define MPFS_SPI1_LO_BASE (0x20109000UL) +#define MPFS_I2C0_LO_BASE (0x2010A000UL) +#define MPFS_I2C1_LO_BASE (0x2010B000UL) +#define MPFS_CAN0_LO_BASE (0x2010C000UL) +#define MPFS_CAN1_LO_BASE (0x2010D000UL) +#define MPFS_GEM0_LO_BASE (0x20110000UL) +#define MPFS_GEM1_LO_BASE (0x20112000UL) +#define MPFS_GPIO0_LO_BASE (0x20120000UL) +#define MPFS_GPIO1_LO_BASE (0x20121000UL) +#define MPFS_GPIO2_LO_BASE (0x20122000UL) +#define MPFS_MSRTC_LO_BASE (0x20124000UL) +#define MPFS_MSTIMER_LO_BASE (0x20125000UL) +#define MPFS_H2FINT_LO_BASE (0x20126000UL) +#define MPFS_CRYPTO_BASE (0x20127000UL) +#define MPFS_ENVMCFG_BASE (0x20200000UL) +#define MPFS_USB_BASE (0x20201000UL) +#define MPFS_QSPIXIP_BASE (0x21000000UL) +#define MPFS_ATHENA_BASE (0x22000000UL) +#define MPFS_TRACE_BASE (0x23000000UL) + +/* These are high base */ + +#define MPFS_UART0_HI_BASE (0x28000000UL) +#define MPFS_WDOG0_HI_BASE (0x28001000UL) +#define MPFS_UART1_HI_BASE (0x28100000UL) +#define MPFS_WDOG1_HI_BASE (0x28101000UL) +#define MPFS_UART2_HI_BASE (0x28102000UL) +#define MPFS_WDOG2_HI_BASE (0x28103000UL) +#define MPFS_UART3_HI_BASE (0x28104000UL) +#define MPFS_WDOG3_HI_BASE (0x28105000UL) +#define MPFS_UART4_HI_BASE (0x28106000UL) +#define MPFS_WDOG4_HI_BASE (0x28107000UL) +#define MPFS_SPI0_HI_BASE (0x28108000UL) +#define MPFS_SPI1_HI_BASE (0x28109000UL) +#define MPFS_I2C0_HI_BASE (0x2810A000UL) +#define MPFS_I2C1_HI_BASE (0x2810B000UL) +#define MPFS_CAN0_HI_BASE (0x2810C000UL) +#define MPFS_CAN1_HI_BASE (0x2810D000UL) +#define MPFS_GEM0_HI_BASE (0x28110000UL) +#define MPFS_GEM1_HI_BASE (0x28112000UL) +#define MPFS_GPIO0_HI_BASE (0x28120000UL) +#define MPFS_GPIO1_HI_BASE (0x28121000UL) +#define MPFS_GPIO2_HI_BASE (0x28122000UL) +#define MPFS_MSRTC_HI_BASE (0x28124000UL) +#define MPFS_MSTIMER_HI_BASE (0x28125000UL) +#define MPFS_H2FINT_HI_BASE (0x28126000UL) + +#define MPFS_IOSCBCFG_BASE (0x37080000UL) + +/* TODO: How to select if peripheral is on HI base address kconfig? + * + * On PolarFire SoC an AXI switch forms a bus matrix interconnect among + * multiple masters and multiple slaves. Five RISC-V CPUs connect to the + * Master ports M10 to M14 of the AXI switch. By default, all the APB + * peripherals are accessible on AXI-Slave 5 of the AXI switch via the AXI to + * AHB and AHB to APB bridges (referred as main APB bus). + * However, to support logical separation in the Asymmetric Multi-Processing + * (AMP) mode of operation, the APB peripherals can alternatively be accessed + * on the AXI-Slave 6 via the AXI to AHB and AHB to APB bridges + * (referred as the AMP APB bus). + */ + +#define MPFS_UART0_BASE MPFS_UART0_LO_BASE +#define MPFS_UART1_BASE MPFS_UART1_LO_BASE +#define MPFS_UART2_BASE MPFS_UART2_LO_BASE +#define MPFS_UART3_BASE MPFS_UART3_LO_BASE +#define MPFS_UART4_BASE MPFS_UART4_LO_BASE + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_MEMORYMAP_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_plic.h b/arch/risc-v/src/mpfs/hardware/mpfs_plic.h new file mode 100755 index 00000000000..17895244361 --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_plic.h @@ -0,0 +1,131 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_plic.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_PLIC_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_PLIC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* following 187 uint32_t for irq priority */ + +#define MPFS_PLIC_PRIORITY (MPFS_PLIC_BASE + 0x000000) + +#define MPFS_PLIC_IP0 (MPFS_PLIC_BASE + 0x001000) +#define MPFS_PLIC_IP1 (MPFS_PLIC_BASE + 0x001004) +#define MPFS_PLIC_IP2 (MPFS_PLIC_BASE + 0x001008) +#define MPFS_PLIC_IP3 (MPFS_PLIC_BASE + 0x00100C) +#define MPFS_PLIC_IP4 (MPFS_PLIC_BASE + 0x001010) +#define MPFS_PLIC_I51 (MPFS_PLIC_BASE + 0x001014) + +#define MPFS_HART_MIE_OFFSET (0x100) + +#define MPFS_PLIC_H0_MIE0 (MPFS_PLIC_BASE + 0x002000) +#define MPFS_PLIC_H0_MIE1 (MPFS_PLIC_BASE + 0x002004) +#define MPFS_PLIC_H0_MIE2 (MPFS_PLIC_BASE + 0x002008) +#define MPFS_PLIC_H0_MIE3 (MPFS_PLIC_BASE + 0x00200C) +#define MPFS_PLIC_H0_MIE4 (MPFS_PLIC_BASE + 0x002010) +#define MPFS_PLIC_H0_MIE5 (MPFS_PLIC_BASE + 0x002014) + +#define MPFS_PLIC_H1_MIE0 (MPFS_PLIC_BASE + 0x002080) +#define MPFS_PLIC_H1_MIE1 (MPFS_PLIC_BASE + 0x002084) +#define MPFS_PLIC_H1_MIE2 (MPFS_PLIC_BASE + 0x002088) +#define MPFS_PLIC_H1_MIE3 (MPFS_PLIC_BASE + 0x00208C) +#define MPFS_PLIC_H1_MIE4 (MPFS_PLIC_BASE + 0x002090) +#define MPFS_PLIC_H1_MIE5 (MPFS_PLIC_BASE + 0x002094) +#define MPFS_PLIC_H1_SIE0 (MPFS_PLIC_BASE + 0x002100) +#define MPFS_PLIC_H1_SIE1 (MPFS_PLIC_BASE + 0x002104) +#define MPFS_PLIC_H1_SIE2 (MPFS_PLIC_BASE + 0x002108) +#define MPFS_PLIC_H1_SIE3 (MPFS_PLIC_BASE + 0x00210C) +#define MPFS_PLIC_H1_SIE4 (MPFS_PLIC_BASE + 0x002110) +#define MPFS_PLIC_H1_SIE5 (MPFS_PLIC_BASE + 0x002114) + +#define MPFS_PLIC_H2_MIE0 (MPFS_PLIC_BASE + 0x002180) +#define MPFS_PLIC_H2_MIE1 (MPFS_PLIC_BASE + 0x002184) +#define MPFS_PLIC_H2_MIE2 (MPFS_PLIC_BASE + 0x002188) +#define MPFS_PLIC_H2_MIE3 (MPFS_PLIC_BASE + 0x00218C) +#define MPFS_PLIC_H2_MIE4 (MPFS_PLIC_BASE + 0x002190) +#define MPFS_PLIC_H2_MIE5 (MPFS_PLIC_BASE + 0x002194) +#define MPFS_PLIC_H2_SIE0 (MPFS_PLIC_BASE + 0x002200) +#define MPFS_PLIC_H2_SIE1 (MPFS_PLIC_BASE + 0x002204) +#define MPFS_PLIC_H2_SIE2 (MPFS_PLIC_BASE + 0x002208) +#define MPFS_PLIC_H2_SIE3 (MPFS_PLIC_BASE + 0x00220C) +#define MPFS_PLIC_H2_SIE4 (MPFS_PLIC_BASE + 0x002210) +#define MPFS_PLIC_H2_SIE5 (MPFS_PLIC_BASE + 0x002214) + +#define MPFS_PLIC_H3_MIE0 (MPFS_PLIC_BASE + 0x002280) +#define MPFS_PLIC_H3_MIE1 (MPFS_PLIC_BASE + 0x002284) +#define MPFS_PLIC_H3_MIE2 (MPFS_PLIC_BASE + 0x002288) +#define MPFS_PLIC_H3_MIE3 (MPFS_PLIC_BASE + 0x00228C) +#define MPFS_PLIC_H3_MIE4 (MPFS_PLIC_BASE + 0x002290) +#define MPFS_PLIC_H3_MIE5 (MPFS_PLIC_BASE + 0x002294) +#define MPFS_PLIC_H3_SIE0 (MPFS_PLIC_BASE + 0x002300) +#define MPFS_PLIC_H3_SIE1 (MPFS_PLIC_BASE + 0x002304) +#define MPFS_PLIC_H3_SIE2 (MPFS_PLIC_BASE + 0x002308) +#define MPFS_PLIC_H3_SIE3 (MPFS_PLIC_BASE + 0x00230C) +#define MPFS_PLIC_H3_SIE4 (MPFS_PLIC_BASE + 0x002310) +#define MPFS_PLIC_H3_SIE5 (MPFS_PLIC_BASE + 0x002314) + +#define MPFS_PLIC_H4_MIE0 (MPFS_PLIC_BASE + 0x002380) +#define MPFS_PLIC_H4_MIE1 (MPFS_PLIC_BASE + 0x002384) +#define MPFS_PLIC_H4_MIE2 (MPFS_PLIC_BASE + 0x002388) +#define MPFS_PLIC_H4_MIE3 (MPFS_PLIC_BASE + 0x00238C) +#define MPFS_PLIC_H4_MIE4 (MPFS_PLIC_BASE + 0x002390) +#define MPFS_PLIC_H4_MIE5 (MPFS_PLIC_BASE + 0x002394) +#define MPFS_PLIC_H4_SIE0 (MPFS_PLIC_BASE + 0x002400) +#define MPFS_PLIC_H4_SIE1 (MPFS_PLIC_BASE + 0x002404) +#define MPFS_PLIC_H4_SIE2 (MPFS_PLIC_BASE + 0x002408) +#define MPFS_PLIC_H4_SIE3 (MPFS_PLIC_BASE + 0x00240C) +#define MPFS_PLIC_H4_SIE4 (MPFS_PLIC_BASE + 0x002410) +#define MPFS_PLIC_H4_SIE5 (MPFS_PLIC_BASE + 0x002414) + +#define MPFS_PLIC_CTRL (MPFS_PLIC_BASE + 0x1FFFFC) + +#define MPFS_PLIC_NEXTHART_OFFSET (0x2000) +#define MPFS_PLIC_MTHRESHOLD_OFFSET (0x0000) +#define MPFS_PLIC_MCLAIM_OFFSET (0x0004) +#define MPFS_PLIC_STHRESHOLD_OFFSET (0x1000) +#define MPFS_PLIC_SCLAIM_OFFSET (0x1004) + +#define MPFS_PLIC_H0_MTHRESHOLD (MPFS_PLIC_BASE + 0x200000) +#define MPFS_PLIC_H0_MCLAIM (MPFS_PLIC_BASE + 0x200004) + +#define MPFS_PLIC_H1_MTHRESHOLD (MPFS_PLIC_BASE + 0x201000) +#define MPFS_PLIC_H1_MCLAIM (MPFS_PLIC_BASE + 0x201004) +#define MPFS_PLIC_H1_STHRESHOLD (MPFS_PLIC_BASE + 0x202000) +#define MPFS_PLIC_H1_SCLAIM (MPFS_PLIC_BASE + 0x202004) + +#define MPFS_PLIC_H2_MTHRESHOLD (MPFS_PLIC_BASE + 0x203000) +#define MPFS_PLIC_H2_MCLAIM (MPFS_PLIC_BASE + 0x203004) +#define MPFS_PLIC_H2_STHRESHOLD (MPFS_PLIC_BASE + 0x204000) +#define MPFS_PLIC_H2_SCLAIM (MPFS_PLIC_BASE + 0x204004) + +#define MPFS_PLIC_H3_MTHRESHOLD (MPFS_PLIC_BASE + 0x205000) +#define MPFS_PLIC_H3_MCLAIM (MPFS_PLIC_BASE + 0x205004) +#define MPFS_PLIC_H3_STHRESHOLD (MPFS_PLIC_BASE + 0x206000) +#define MPFS_PLIC_H3_SCLAIM (MPFS_PLIC_BASE + 0x206004) + +#define MPFS_PLIC_H4_MTHRESHOLD (MPFS_PLIC_BASE + 0x207000) +#define MPFS_PLIC_H4_MCLAIM (MPFS_PLIC_BASE + 0x207004) +#define MPFS_PLIC_H4_STHRESHOLD (MPFS_PLIC_BASE + 0x208000) +#define MPFS_PLIC_H4_SCLAIM (MPFS_PLIC_BASE + 0x208004) + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_PLIC_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_spi.h b/arch/risc-v/src/mpfs/hardware/mpfs_spi.h new file mode 100755 index 00000000000..8b50e39264c --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_spi.h @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SPI_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SPI_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CONTROL register */ + +#define MPFS_SPI_RESET (1 << 31) +#define MPFS_SPI_OENOFF (1 << 30) +#define MPFS_SPI_BIGFIFO (1 << 29) +#define MPFS_SPI_CLKMODE (1 << 28) +#define MPFS_SPI_FRAMEURUN (1 << 27) +#define MPFS_SPI_SPS (1 << 26) +#define MPFS_SPI_SPH (1 << 25) +#define MPFS_SPI_SPO (1 << 24) +#define MPFS_SPI_FRAMECNT (0xffff << 8) +#define MPFS_SPI_INTTXTURUN (1 << 7) +#define MPFS_SPI_INTRXOVRFLOW (1 << 6) +#define MPFS_SPI_INTTXDATA (1 << 5) +#define MPFS_SPI_INTRXDATA (1 << 4) +#define MPFS_SPI_TRANSFPRTL (1 << 2) | (1 << 3) +#define MPFS_SPI_MODE (1 << 1) +#define MPFS_SPI_ENABLE (1 << 0) + +/* FRAMESIZE register */ + +#define MPFS_SPI_FRAMESIZE (0x3F) + +/* STATUS register */ + +#define MPFS_SPI_ACTIVE (1 << 14) +#define MPFS_SPI_SSEL (1 << 13) +#define MPFS_SPI_FRAMESTART (1 << 12) +#define MPFS_SPI_TXFIFOEMPNXT (1 << 11) +#define MPFS_SPI_TXFIFOEMP (1 << 10) +#define MPFS_SPI_TXFIFOFULNXT (1 << 9) +#define MPFS_SPI_TXFIFOFUL (1 << 8) +#define MPFS_SPI_RXFIFOEMPNXT (1 << 7) +#define MPFS_SPI_RXFIFOEMP (1 << 6) +#define MPFS_SPI_RXFIFOFULNXT (1 << 5) +#define MPFS_SPI_RXFIFOFUL (1 << 4) +#define MPFS_SPI_TXUNDERRUN (1 << 3) +#define MPFS_SPI_RXOVERFLOW (1 << 2) +#define MPFS_SPI_RXDATRCED (1 << 1) +#define MPFS_SPI_TXDATSENT (1 << 0) + +/* INT_CLEAR register */ + +#define MPFS_SPI_SSEND (1 << 5) +#define MPFS_SPI_CMDINT (1 << 4) +#define MPFS_SPI_TXCHUNDRUN (1 << 3) +#define MPFS_SPI_RXCHOVRFLW (1 << 2) +#define MPFS_SPI_RXRDONECLR (1 << 1) +#define MPFS_SPI_TXDONECLR (1 << 0) + +/* INTMASK register */ + +#define MPFS_SPI_SSENDMSKINT (1 << 5) +#define MPFS_SPI_CMDMSKINT (1 << 4) +#define MPFS_SPI_TXCHUNDDMSKINT (1 << 3) +#define MPFS_SPI_RXCHOVRFMSKINT (1 << 2) +#define MPFS_SPI_RXRDYMSKINT (1 << 1) +#define MPFS_SPI_TXDONEMSKINT (1 << 0) + +/* INTRAW register */ + +#define MPFS_SPI_TXCHUNDR (1 << 3) +#define MPFS_SPI_RXOVRFLW (1 << 2) +#define MPFS_SPI_RXRDY (1 << 1) +#define MPFS_SPI_TXDONE (1 << 0) + +/* CONTROL2 register */ + +#define MPFS_SPI_INTEN_SSEND (1 << 5) +#define MPFS_SPI_INTEN_CMD (1 << 4) +#define MPFS_SPI_DISFRMCNT (1 << 2) +#define MPFS_SPI_AUTOPOLL (1 << 1) +#define MPFS_SPI_AUTOSTATUS (1 << 0) + +/* COMMAND register */ + +#define MPFS_SPI_TXNOW (1 << 6) +#define MPFS_SPI_AUTOSTALL (1 << 5) +#define MPFS_SPI_CLRFRAMECNT (1 << 4) +#define MPFS_SPI_TXFIFORST (1 << 3) +#define MPFS_SPI_RXFIFORST (1 << 2) +#define MPFS_SPI_AUTOEMPTY (1 << 1) +#define MPFS_SPI_AUTOFILL (1 << 0) + +/* HWSTATUS register */ + +#define MPFS_SPI_USER (1 << 2) | (1 << 3) +#define MPFS_SPI_TXBUSY (1 << 1) +#define MPFS_SPI_RXBUSY (1 << 0) + +/* STAT8 register */ + +#define MPFS_SPI_S8_ACTIVEL (1 << 6) +#define MPFS_SPI_S8_SSEL (1 << 6) +#define MPFS_SPI_S8_TXUNDERRUN (1 << 5) +#define MPFS_SPI_S8_RXOVERFLOW (1 << 4) +#define MPFS_SPI_S8_TXFIFOFUL (1 << 3) +#define MPFS_SPI_S8_RXFIFOEMP (1 << 2) +#define MPFS_SPI_S8_DONE (1 << 1) +#define MPFS_SPI_S8_FRAMESTART (1 << 0) + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SPI_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_sysctl.h b/arch/risc-v/src/mpfs/hardware/mpfs_sysctl.h new file mode 100755 index 00000000000..a8d51039dc7 --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_sysctl.h @@ -0,0 +1,34 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_sysctl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SYSCTL_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SYSCTL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SYSCTL_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_sysreg.h b/arch/risc-v/src/mpfs/hardware/mpfs_sysreg.h new file mode 100755 index 00000000000..c74753fb96c --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_sysreg.h @@ -0,0 +1,320 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_sysreg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SYSREG_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SYSREG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define MPFS_SYSREG_TEMP0_OFFSET 0x0000 /* Register for software use */ +#define MPFS_SYSREG_TEMP1_OFFSET 0x0004 /* Register for software use */ +#define MPFS_SYSREG_CLOCK_CONFIG_CR_OFFSET 0x0008 /* Master clock configuration */ +#define MPFS_SYSREG_RTC_CLOCK_CR_OFFSET 0x000C /* RTC clock divider */ +#define MPFS_SYSREG_FABRIC_RESET_CR_OFFSET 0x0010 /* Fabric Reset mask */ +#define MPFS_SYSREG_BOOT_FAIL_CR_OFFSET 0x0014 /* */ +#define MPFS_SYSREG_MSS_RESET_CR_OFFSET 0x0018 /* write 0xDEAD to reset */ +#define MPFS_SYSREG_CONFIG_LOCK_CR_OFFSET 0x001C /* Configuration lock */ +#define MPFS_SYSREG_RESET_SR_OFFSET 0x0020 /* reset reason */ +#define MPFS_SYSREG_DEVICE_STATUS_OFFSET 0x0024 /* device status */ +#define MPFS_SYSREG_MSS_BUILD_OFFSET 0x0028 /* MSS Build Info */ +#define MPFS_SYSREG_FAB_INTEN_U54_1_OFFSET 0x0040 /* U54-1 Fabric interrupt enable */ +#define MPFS_SYSREG_FAB_INTEN_U54_2_OFFSET 0x0044 /* U54-2 Fabric interrupt enable */ +#define MPFS_SYSREG_FAB_INTEN_U54_3_OFFSET 0x0048 /* U54-3 Fabric interrupt enable */ +#define MPFS_SYSREG_FAB_INTEN_U54_4_OFFSET 0x004C /* U54-4 Fabric interrupt enable */ +#define MPFS_SYSREG_FAB_INTEN_MISC_OFFSET 0x0050 /* Allow Eth direct irq routing to U54 CPUs */ +#define MPFS_SYSREG_GPIO_INTERRUPT_FAB_CR_OFFSET 0x0054 /* Switches GPIO interrupt from PAD to Fabric GPIO */ +#define MPFS_SYSREG_APBBUS_CR_OFFSET 0x0080 /* AMP Mode peripheral mapping */ +#define MPFS_SYSREG_SUBBLK_CLOCK_CR_OFFSET 0x0084 /* Enables the clock to the MSS peripheral */ +#define MPFS_SYSREG_SOFT_RESET_CR_OFFSET 0x0088 /* Holds the MSS peripherals in reset */ +#define MPFS_SYSREG_AHBAXI_CR_OFFSET 0x008C /* AXI-AHB bridges transfers */ +#define MPFS_SYSREG_AHBAPB_CR_OFFSET 0x0090 /* Configures the two AHB-APB bridges on S5 and S6 */ +#define MPFS_SYSREG_DFIAPB_CR_OFFSET 0x0098 /* MSS Corner APB interface controls */ +#define MPFS_SYSREG_GPIO_CR_OFFSET 0x009C /* GPIO Blocks reset control */ +#define MPFS_SYSREG_MAC0_CR_OFFSET 0x00A4 /* MAC0 configuration */ +#define MPFS_SYSREG_MAC1_CR_OFFSET 0x00A8 /* MAC1 configuration */ +#define MPFS_SYSREG_USB_CR_OFFSET 0x00AC /* USB Configuration */ +#define MPFS_SYSREG_MESH_CR_OFFSET 0x00B0 /* Crypto Mesh control and status */ +#define MPFS_SYSREG_MESH_SEED_CR_OFFSET 0x00B4 /* Crypto mesh seed and update rate */ +#define MPFS_SYSREG_ENVM_CR_OFFSET 0x00B8 /* ENVM AHB Controller setup */ +#define MPFS_SYSREG_RESERVED_BC_OFFSET 0x00BC /* Reserved */ +#define MPFS_SYSREG_QOS_PERIPHERAL_CR_OFFSET 0x00C0 /* QOS Athena USB & MMC Configuration */ +#define MPFS_SYSREG_QOS_CPLEXIO_CR_OFFSET 0x00C4 /* QOS Configuration Coreplex */ +#define MPFS_SYSREG_QOS_CPLEXDDR_CR_OFFSET 0x00C8 /* QOS configuration DDRC */ +#define MPFS_SYSREG_MPU_VIOLATION_SR_OFFSET 0x00F0 /* Indicates that a master caused a MPU violation */ +#define MPFS_SYSREG_MPU_VIOLATION_INTEN_CR_OFFSET 0x00F4 /* Enables interrupts on MPU violations */ +#define MPFS_SYSREG_SW_FAIL_ADDR0_CR_OFFSET 0x00F8 /* AXI switch decode fail */ +#define MPFS_SYSREG_SW_FAIL_ADDR1_CR_OFFSET 0x00FC /* AXI switch decode fail */ +#define MPFS_SYSREG_EDAC_SR_OFFSET 0x0100 /* Set when an ECC event happens */ +#define MPFS_SYSREG_EDAC_INTEN_CR_OFFSET 0x0104 /* Enables ECC interrupt on event */ +#define MPFS_SYSREG_EDAC_CNT_MMC_OFFSET 0x0108 /* Count off single bit errors */ +#define MPFS_SYSREG_EDAC_CNT_DDRC_OFFSET 0x010C /* Count off single bit errors */ +#define MPFS_SYSREG_EDAC_CNT_MAC0_OFFSET 0x0110 /* Count off single bit errors */ +#define MPFS_SYSREG_EDAC_CNT_MAC1_OFFSET 0x0114 /* Count off single bit errors */ +#define MPFS_SYSREG_EDAC_CNT_USB_OFFSET 0x0118 /* Count off single bit errors */ +#define MPFS_SYSREG_EDAC_CNT_CAN0_OFFSET 0x011C /* Count off single bit errors */ +#define MPFS_SYSREG_EDAC_CNT_CAN1_OFFSET 0x0120 /* Count off single bit errors */ +#define MPFS_SYSREG_EDAC_INJECT_CR_OFFSET 0x0124 /* Will Corrupt write data to rams */ +#define MPFS_SYSREG_MAINTENANCE_INTEN_CR_OFFSET 0x0140 /* Maintenance Interrupt Enable */ +#define MPFS_SYSREG_PLL_STATUS_INTEN_CR_OFFSET 0x0144 /* PLL Status interrupt enables */ +#define MPFS_SYSREG_MAINTENANCE_INT_SR_OFFSET 0x0148 /* Maintenance interrupt fault and status events*/ +#define MPFS_SYSREG_PLL_STATUS_SR_OFFSET 0x014C /* PLL interrupt register */ +#define MPFS_SYSREG_CFM_TIMER_CR_OFFSET 0x0150 /* Enable to CFM Timer */ +#define MPFS_SYSREG_MISC_SR_OFFSET 0x0154 /* Miscellaneous Register */ +#define MPFS_SYSREG_DLL_STATUS_CR_OFFSET 0x0158 /* DLL Interrupt enables */ +#define MPFS_SYSREG_DLL_STATUS_SR_OFFSET 0x015C /* DLL interrupt status */ +#define MPFS_SYSREG_RAM_LIGHTSLEEP_CR_OFFSET 0x0168 /* Puts all the RAMS in that block into low leakage mode */ +#define MPFS_SYSREG_RAM_DEEPSLEEP_CR_OFFSET 0x016C /* Puts all the RAMS in that block into deep sleep mode */ +#define MPFS_SYSREG_RAM_SHUTDOWN_CR_OFFSET 0x0170 /* Puts all the RAMS in that block into shut down mode */ +#define MPFS_SYSREG_L2_SHUTDOWN_CR_OFFSET 0x0174 /* Allows each bank of the L2 Cache to be powered down */ +#define MPFS_SYSREG_IOMUX0_CR_OFFSET 0x0200 /* Is peripheral connected to the Fabric or IOMUX structure */ +#define MPFS_SYSREG_IOMUX1_CR_OFFSET 0x0204 /* Configures the IO Mux structure for each IO pad */ +#define MPFS_SYSREG_IOMUX2_CR_OFFSET 0x0208 /* Configures the IO Mux structure for each IO pad */ +#define MPFS_SYSREG_IOMUX3_CR_OFFSET 0x020C /* Configures the IO Mux structure for each IO pad */ +#define MPFS_SYSREG_IOMUX4_CR_OFFSET 0x0210 /* Configures the IO Mux structure for each IO pad */ +#define MPFS_SYSREG_IOMUX5_CR_OFFSET 0x0214 /* Configures the IO Mux structure for each IO pad */ +#define MPFS_SYSREG_IOMUX6_CR_OFFSET 0x0218 /* Inverter MMC/SD Voltage select lines to the IOMUX structure */ +#define MPFS_SYSREG_MSSIO_BANK4_CFG_CR 0x0230 /* Configures the MSSIO block */ +#define MPFS_SYSREG_MSSIO_BANK4_IO_CFG_0_1_CR_OFFSET 0x0234 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK4_IO_CFG_2_3_CR_OFFSET 0x0238 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK4_IO_CFG_4_5_CR_OFFSET 0x023C /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK4_IO_CFG_6_7_CR_OFFSET 0x0240 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK4_IO_CFG_8_9_CR_OFFSET 0x0244 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK4_IO_CFG_10_11_CR_OFFSET 0x0248 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK4_IO_CFG_12_13_CR_OFFSET 0x024C /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_CFG_CR 0x0250 /* Configures the MSSIO block */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_0_1_CR_OFFSET 0x0254 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_2_3_CR_OFFSET 0x0258 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_4_5_CR_OFFSET 0x025C /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_6_7_CR_OFFSET 0x0260 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_8_9_CR_OFFSET 0x0264 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_10_11_CR_OFFSET 0x0268 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_12_13_CR_OFFSET 0x026C /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_14_15_CR_OFFSET 0x0270 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_16_17_CR_OFFSET 0x0274 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_18_19_CR_OFFSET 0x0278 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_20_21_CR_OFFSET 0x027C /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSSIO_BANK2_IO_CFG_22_23_CR_OFFSET 0x0280 /* IO electrical configuration for MSSIO pad */ +#define MPFS_SYSREG_MSS_SPARE0_CR_OFFSET 0x02A8 /* Sets H2F [31:0] Spares out signals */ +#define MPFS_SYSREG_MSS_SPARE1_CR_OFFSET 0x02AC /* Sets H2F [37:32] Spares out signals */ +#define MPFS_SYSREG_MSS_SPARE0_SR_OFFSET 0x02B0 /* Read H2F [31:0] Spares out signals */ +#define MPFS_SYSREG_MSS_SPARE1_SR_OFFSET 0x02B4 /* Read H2F [37:32] Spares out signals */ +#define MPFS_SYSREG_MSS_SPARE2_SR_OFFSET 0x02B8 /* Read F2H [31:0] Spares in1 signals */ +#define MPFS_SYSREG_MSS_SPARE3_SR_OFFSET 0x02BC /* Read F2H [37:32] Spares in1 signals */ +#define MPFS_SYSREG_MSS_SPARE4_SR_OFFSET 0x02C0 /* Read F2H [31:0] Spares in2 signals */ +#define MPFS_SYSREG_MSS_SPARE5_SR_OFFSET 0x02C4 /* Read F2H [37:32] Spares in2 signals */ +#define MPFS_SYSREG_SPARE_REGISTER_RW_OFFSET 0x02D0 /* Register for ECO usage */ +#define MPFS_SYSREG_SPARE_REGISTER_W1P_OFFSET 0x02D4 /* Register for ECO usage */ +#define MPFS_SYSREG_SPARE_REGISTER_RO_OFFSET 0x02D8 /* Register for ECO usage */ +#define MPFS_SYSREG_SPARE_PERIM_RW_OFFSET 0x02DC /* Spare signal back to G5C */ +#define MPFS_SYSREG_SPARE_FIC_OFFSET 0x02E0 /* Unused FIC resets */ + +/* Register bit field definitions *******************************************/ + +/* Master clock configuration */ + +#define SYSREG_CLOCK_CONFIG_CR_DIVIDER_SHIFT (0) /* Bits: 0-5: master synchronous clock divider */ +#define SYSREG_CLOCK_CONFIG_CR_DIVIDER_MASK (0x3f << SYSREG_CLOCK_CONFIG_CR_DIVIDER_SHIFT) +#define SYSREG_CLOCK_CONFIG_CR_ENABLE_1MHZ_SHIFT (8) /* Bit: 8: enable the 1mHz (2MHz) on-chip oscillator */ +#define SYSREG_CLOCK_CONFIG_CR_ENABLE_1MHZ_MASK (1 << SYSREG_CLOCK_CONFIG_CR_ENABLE_1MHZ_SHIFT) +#define SYSREG_CLOCK_CONFIG_CR_ENABLE_1MHZ (1 << SYSREG_CLOCK_CONFIG_CR_ENABLE_1MHZ_SHIFT) + +/* RTC clock divider */ + +#define SYSREG_RTC_CLOCK_CR_PERIOD_SHIFT (0) /* Bits: 0-11: period */ +#define SYSREG_RTC_CLOCK_CR_PERIOD_MASK (0xfff << SYSREG_CLOCK_CONFIG_CR_DIVIDER_SHIFT) +#define SYSREG_RTC_CLOCK_CR_ENABLE_SHIFT (16) /* Bit: 16: RTC Clock enable */ +#define SYSREG_RTC_CLOCK_CR_ENABLE_MASK (1 << SYSREG_CLOCK_CONFIG_CR_DIVIDER_SHIFT) +#define SYSREG_RTC_CLOCK_CR_ENABLE (1 << SYSREG_CLOCK_CONFIG_CR_DIVIDER_SHIFT) + +/* TODO: + * FABRIC_RESET_CR + * BOOT_FAIL_CR + * MSS_RESET_CR + * CONFIG_LOCK_CR + * RESET_SR + * DEVICE_STATUS + * MSS_BUILD + * FAB_INTEN_U54_1 + * FAB_INTEN_U54_2 + * FAB_INTEN_U54_3 + * FAB_INTEN_U54_4 + * FAB_INTEN_MISC + * GPIO_INTERRUPT_FAB_CR + * APBBUS_CR + */ + +/* Enables the clock to the MSS peripheral */ + +#define SYSREG_SUBBLK_CLOCK_CR_SHIFT (0) /* Bit: 0-29: Clock enable (17 is reserved) */ +#define SYSREG_SUBBLK_CLOCK_CR_MASK (0x3ffdffff << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_ENVM (0 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_MAC0 (1 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_MAC1 (2 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_MMC (3 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_TIMER (4 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_MMUART0 (5 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_MMUART1 (6 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_MMUART2 (7 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_MMUART3 (8 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_MMUART4 (9 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_SPI0 (10 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_SPI1 (11 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_I2C0 (12 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_I2C1 (13 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_CAN0 (14 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_CAN1 (15 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_USB (16 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_RTC (18 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_QSPI (19 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_GPIO0 (20 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_GPIO1 (21 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_GPIO2 (22 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_DDRC (23 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_FIC0 (24 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_FIC1 (25 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_FIC2 (26 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_FIC3 (27 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_ATHENA (28 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SUBBLK_CLOCK_CR_CFM (29 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) + +/* Holds the MSS peripherals in reset */ + +#define SYSREG_SOFT_RESET_CR_SHIFT (0) /* Bit: 0-30: Holds the MSS peripherals in reset */ +#define SYSREG_SOFT_RESET_CR_MASK (0x7fffffff << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_ENVM (0 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_MAC0 (1 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_MAC1 (2 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_MMC (3 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_TIMER (4 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_MMUART0 (5 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_MMUART1 (6 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_MMUART2 (7 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_MMUART3 (8 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_MMUART4 (9 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_SPI0 (10 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_SPI1 (11 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_I2C0 (12 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_I2C1 (13 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_CAN0 (14 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_CAN1 (15 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_USB (16 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_FPGA (17 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_RTC (18 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_QSPI (19 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_GPIO0 (20 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_GPIO1 (21 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_GPIO2 (22 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_DDRC (23 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_FIC0 (24 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_FIC1 (25 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_FIC2 (26 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_FIC3 (27 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_ATHENA (28 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_CFM (29 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) +#define SYSREG_SOFT_RESET_CR_SGMII (30 << SYSREG_SUBBLK_CLOCK_CR_SHIFT) + +/* TODO: + * AHBAXI_CR + * AHBAPB_CR + * DFIAPB_CR + * GPIO_CR + * MAC0_CR + * MAC1_CR + * USB_CR + * MESH_CR + * MESH_SEED_CR + * ENVM_CR + * QOS_PERIPHERAL_CR + * QOS_CPLEXIO_CR + * QOS_CPLEXDDR_CR + * MPU_VIOLATION_SR + * MPU_VIOLATION_INTEN_CR + * SW_FAIL_ADDR0_CR + * SW_FAIL_ADDR1_CR + * EDAC_SR + * EDAC_INTEN_CR + * EDAC_CNT_MMC + * EDAC_CNT_DDRC + * EDAC_CNT_MAC0 + * EDAC_CNT_MAC1 + * EDAC_CNT_USB + * EDAC_CNT_CAN0 + * EDAC_CNT_CAN1 + * EDAC_INJECT_CR + * MAINTENANCE_INTEN_CR + * PLL_STATUS_INTEN_CR + * MAINTENANCE_INT_SR + * PLL_STATUS_SR + * CFM_TIMER_CR + * MISC_SR + * PLL_STATUS_CR + * DLL_STATUS_SR + * RAM_LIGHTSLEEP_CR + * RAM_DEEPSLEEP_CR + * RAM_SHUTDOWN_CR + * L2_SHUTDOWN_CR + * IOMUX0_CR + * IOMUX1_CR + * IOMUX2_CR + * IOMUX3_CR + * IOMUX4_CR + * IOMUX5_CR + * IOMUX6_CR + * MSSIO_BANK4_IO_CFG_0_1_CR + * MSSIO_BANK4_IO_CFG_2_3_CR + * MSSIO_BANK4_IO_CFG_4_5_CR + * MSSIO_BANK4_IO_CFG_6_7_CR + * MSSIO_BANK4_IO_CFG_8_9_CR + * MSSIO_BANK4_IO_CFG_10_11_CR + * MSSIO_BANK4_IO_CFG_12_13_CR + * MSSIO_BANK2_IO_CFG_0_1_CR + * MSSIO_BANK2_IO_CFG_2_3_CR + * MSSIO_BANK2_IO_CFG_4_5_CR + * MSSIO_BANK2_IO_CFG_6_7_CR + * MSSIO_BANK2_IO_CFG_8_9_CR + * MSSIO_BANK2_IO_CFG_10_11_CR + * MSSIO_BANK2_IO_CFG_12_13_CR + * MSSIO_BANK2_IO_CFG_14_15_CR + * MSSIO_BANK2_IO_CFG_16_17_CR + * MSSIO_BANK2_IO_CFG_18_19_CR + * MSSIO_BANK2_IO_CFG_20_21_CR + * MSSIO_BANK2_IO_CFG_22_23_CR + * MSS_SPARE0_CR + * MSS_SPARE1_CR + * MSS_SPARE0_SR + * MSS_SPARE1_SR + * MSS_SPARE2_SR + * MSS_SPARE3_SR + * MSS_SPARE4_SR + * MSS_SPARE5_SR + * SPARE_PERIM_RW + */ + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_SYSREG_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_timer.h b/arch/risc-v/src/mpfs/hardware/mpfs_timer.h new file mode 100644 index 00000000000..7a9d0ca59cd --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_timer.h @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_timer.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_TIMER_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_TIMER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define MPFS_MSTIMER_TIM1VALUE_OFFSET 0x000 /* Current value of timer 1 */ +#define MPFS_MSTIMER_TIM1LOADVAL_OFFSET 0x004 /* Load value for timer 1 */ +#define MPFS_MSTIMER_TIM1BGLOADVAL_OFFSET 0x008 /* Background load value for timer 1 */ +#define MPFS_MSTIMER_TIM1CONTROL_OFFSET 0x00C /* Timer 1 Control Register */ +#define MPFS_MSTIMER_TIM1RIS_OFFSET 0x010 /* Raw interrupt status bit for timer 1 */ +#define MPFS_MSTIMER_TIM1MIS_OFFSET 0x014 /* Masked interrupt status bit for timer 1 */ +#define MPFS_MSTIMER_TIM2VALUE_OFFSET 0x018 /* Current value of timer 2 */ +#define MPFS_MSTIMER_TIM2LOADVAL_OFFSET 0x01C /* Load value for timer 2 */ +#define MPFS_MSTIMER_TIM2BGLOADVAL_OFFSET 0x020 /* Background load value for timer 2 */ +#define MPFS_MSTIMER_TIM2CONTROL_OFFSET 0x024 /* Timer 2 Control Register */ +#define MPFS_MSTIMER_TIM2RIS_OFFSET 0x028 /* Raw interrupt status bit for timer 2 */ +#define MPFS_MSTIMER_TIM2MIS_OFFSET 0x02C /* Masked interrupt status bit for timer 2 */ +#define MPFS_MSTIMER_TIM64VALUEU_OFFSET 0x030 /* Current value of the upper 32 bit word of the 64 bit timer */ +#define MPFS_MSTIMER_TIM64VALUEL_OFFSET 0x034 /* Current value of the lower 32 bit word of the 64 bit timer */ +#define MPFS_MSTIMER_TIM64LOADVALU_OFFSET 0x038 /* Load value for upper 32 bits of 64 bit timer */ +#define MPFS_MSTIMER_TIM64LOADVALL_OFFSET 0x03C /* Load value for lower 32 bits of 64 bit timer */ +#define MPFS_MSTIMER_TIM64BGLOADVALU_OFFSET 0x040 /* Background load value for upper 32bits of 64 bit mode timer */ +#define MPFS_MSTIMER_TIM64BGLOADVALL_OFFSET 0x044 /* Background load value for lower 32bits of 64 bit mode timer */ +#define MPFS_MSTIMER_TIM64CONTROL_OFFSET 0x048 /* 64 bit Timer Control Register */ +#define MPFS_MSTIMER_TIM64RIS_OFFSET 0x04C /* Raw interrupt status bit for 64 bit mode timer */ +#define MPFS_MSTIMER_TIM64MIS_OFFSET 0x050 /* Masked interrupt status bit for 64 bit mode timer */ +#define MPFS_MSTIMER_TIM64MODE_OFFSET 0x054 /* Register to enable/disable 64 bit mode timer */ + +/* Timer Control Registers */ +#define MPFS_MSTIMER_ENABLE_MASK (1 << 0) /* Bit 0: Enable bit for timer */ +#define MPFS_MSTIMER_MODE_MASK (1 << 1) /* Bit 1: Operating mode for timer */ +#define MPFS_MSTIMER_INTEN_MASK (1 << 2) /* Bit 2: Timer interrupt enable bit */ + +/* Raw interrupt status bit for timers */ +#define MPFS_MSTIMER_RIS_MASK (1 << 0) /* Bit 0: Raw interrupt status bit for timer */ + +/* Timer 64bit mode register */ +#define MPFS_MSTIMER_64BITMODE_MASK (1 << 0) /* Bit 0: Enable/disable 64 bit mode timer */ + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_TIMER_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_uart.h b/arch/risc-v/src/mpfs/hardware/mpfs_uart.h new file mode 100755 index 00000000000..2d3b0ccf91e --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_uart.h @@ -0,0 +1,207 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_UART_H +#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/mpfs_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define MPFS_UART_RBR_OFFSET 0x0000 /* UART Receive Buffer Register */ +#define MPFS_UART_THR_OFFSET 0x0000 /* UART Transmit Holding Register */ +#define MPFS_UART_DLL_OFFSET 0x0000 /* UART Divisor Latch Low Register */ +#define MPFS_UART_DLH_OFFSET 0x0004 /* UART Divisor Latch High Register */ +#define MPFS_UART_IER_OFFSET 0x0004 /* UART Interrupt Enable Register */ +#define MPFS_UART_IIR_OFFSET 0x0008 /* UART Interrupt Identity Register */ +#define MPFS_UART_FCR_OFFSET 0x0008 /* UART FIFO Control Register */ +#define MPFS_UART_LCR_OFFSET 0x000c /* UART Line Control Register */ +#define MPFS_UART_MCR_OFFSET 0x0010 /* UART Modem Control Register */ +#define MPFS_UART_LSR_OFFSET 0x0014 /* UART Line Status Register */ +#define MPFS_UART_MSR_OFFSET 0x0018 /* UART Modem Status Register */ +#define MPFS_UART_SCH_OFFSET 0x001c /* UART Scratch Register */ +#define MPFS_UART_IEM_OFFSET 0x0024 /* UART Multi-mode interrupt enable register */ +#define MPFS_UART_IIM_OFFSET 0x0028 /* UART Multi-mode interrupt identification register */ +#define MPFS_UART_MM0_OFFSET 0x0030 /* UART Multi-mode control register 0 */ +#define MPFS_UART_MM1_OFFSET 0x0034 /* UART Multi-mode control register 1 */ +#define MPFS_UART_MM2_OFFSET 0x0038 /* UART Multi-mode control register 2 */ +#define MPFS_UART_DFR_OFFSET 0x003C /* UART Fractional divisor register */ +#define MPFS_UART_GFR_OFFSET 0x0044 /* UART Glitch filter register */ +#define MPFS_UART_TTG_OFFSET 0x0048 /* UART Transmitter time guard register */ +#define MPFS_UART_RTO_OFFSET 0x004C /* UART Receiver time-out register */ +#define MPFS_UART_ADR_OFFSET 0x0050 /* UART Address register */ + +/* Register virtual addresses ***********************************************/ + +#define MPFS250_UART0_VADDR MPFS_UART0_BASE +#define MPFS250_UART1_VADDR MPFS_UART1_BASE +#define MPFS250_UART2_VADDR MPFS_UART2_BASE +#define MPFS250_UART3_VADDR MPFS_UART3_BASE +#define MPFS250_UART4_VADDR MPFS_UART4_BASE + +/* Register bit field definitions *******************************************/ + +/* UART Receive Buffer Register */ + +#define UART_RBR_MASK 0x000000ff + +/* UART Transmit Holding Register */ + +#define UART_THR_MASK 0x000000ff + +/* UART Divisor Latch Low Register */ + +#define UART_DLL_MASK 0x000000ff + +/* UART Divisor Latch High Register */ + +#define UART_DLH_MASK 0x000000ff + +/* UART Interrupt Enable Register */ + +#define UART_IER_ERBFI (1 << 0) /* Bit 0: Enable Received Data Available Interrupt */ +#define UART_IER_ETBEI (1 << 1) /* Bit 1: Enable Transmit Holding Register Empty Interrupt */ +#define UART_IER_ELSI (1 << 2) /* Bit 2: Enable Receiver Line Status Interrupt */ +#define UART_IER_EDSSI (1 << 3) /* Bit 3: Enable Modem Status Interrupt */ +#define UART_IER_PTIME (1 << 7) /* Bit 7: Programmable THRE Interrupt Mode Enable */ +#define UART_IER_ALLIE 0x0000008f + +/* UART Interrupt Identity Register */ + +#define UART_IIR_IID_SHIFT (0) /* Bits: 0-3: Interrupt ID */ +#define UART_IIR_IID_MASK (15 << UART_IIR_IID_SHIFT) +# define UART_IIR_IID_MODEM (0 << UART_IIR_IID_SHIFT) /* Modem status */ +# define UART_IIR_IID_NONE (1 << UART_IIR_IID_SHIFT) /* No interrupt pending */ +# define UART_IIR_IID_TXEMPTY (2 << UART_IIR_IID_SHIFT) /* THR empty */ +# define UART_IIR_IID_RECV (4 << UART_IIR_IID_SHIFT) /* Received data available */ +# define UART_IIR_IID_LINESTATUS (6 << UART_IIR_IID_SHIFT) /* Receiver line status */ +# define UART_IIR_IID_TIMEOUT (12 << UART_IIR_IID_SHIFT) /* Character timeout */ + +#define UART_IIR_FEFLAG_SHIFT (6) /* Bits 6-7: FIFOs Enable Flag */ +#define UART_IIR_FEFLAG_MASK (3 << UART_IIR_FEFLAG_SHIFT) +# define UART_IIR_FEFLAG_DISABLE (0 << UART_IIR_FEFLAG_SHIFT) +# define UART_IIR_FEFLAG_ENABLE (3 << UART_IIR_FEFLAG_SHIFT) + +/* UART FIFO Control Register */ + +#define UART_FCR_FIFOE (1 << 0) /* Bit 0: Enable FIFOs */ +#define UART_FCR_RFIFOR (1 << 1) /* Bit 1: RCVR FIFO Reset */ +#define UART_FCR_XFIFOR (1 << 2) /* Bit 2: XMIT FIFO reset */ +#define UART_FCR_DMAM (1 << 3) /* Bit 3: DMA mode */ +#define UART_FCR_TFT_SHIFT (4) /* Bits 4-5: TX Empty Trigger */ +#define UART_FCR_TFT_MASK (3 << UART_FCR_TFT_SHIFT) +# define UART_FCR_TFT_EMPTY (0 << UART_FCR_TFT_SHIFT) /* FIFO empty */ +# define UART_FCR_TFT_TWO (1 << UART_FCR_TFT_SHIFT) /* 2 characters in the FIFO */ +# define UART_FCR_TFT_QUARTER (2 << UART_FCR_TFT_SHIFT) /* FIFO 1/4 full */ +# define UART_FCR_TFT_HALF (3 << UART_FCR_TFT_SHIFT) /* FIFO 1/2 full */ + +#define UART_FCR_RT_SHIFT (6) /* Bits 6-7: RCVR Trigger */ +#define UART_FCR_RT_MASK (3 << UART_FCR_RT_SHIFT) +# define UART_FCR_RT_ONE (0 << UART_FCR_RT_SHIFT) /* 1 character in the FIFO */ +# define UART_FCR_RT_QUARTER (1 << UART_FCR_RT_SHIFT) /* FIFO 1/4 full */ +# define UART_FCR_RT_HALF (2 << UART_FCR_RT_SHIFT) /* FIFO 1/2 full */ +# define UART_FCR_RT_MINUS2 (3 << UART_FCR_RT_SHIFT) /* FIFO-2 less than full */ + +/* UART Line Control Register */ + +#define UART_LCR_DLS_SHIFT (0) /* Bits 0-1: Data Length Select */ +#define UART_LCR_DLS_MASK (3 << UART_LCR_DLS_SHIFT) +# define UART_LCR_DLS_5BITS (0 << UART_LCR_DLS_SHIFT) /* 5 bits */ +# define UART_LCR_DLS_6BITS (1 << UART_LCR_DLS_SHIFT) /* 6 bits */ +# define UART_LCR_DLS_7BITS (2 << UART_LCR_DLS_SHIFT) /* 7 bits */ +# define UART_LCR_DLS_8BITS (3 << UART_LCR_DLS_SHIFT) /* 8 bits */ + +#define UART_LCR_STOP (1 << 2) /* Bit 2: Number of stop bits */ +#define UART_LCR_PEN (1 << 3) /* Bit 3: Parity Enable */ +#define UART_LCR_EPS (1 << 4) /* Bit 4: Even Parity Select */ +#define UART_LCR_BC (1 << 6) /* Bit 6: Break Control Bit */ +#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit */ + +/* UART Modem Control Register */ + +#define UART_MCR_DTR (1 << 0) /* Bit 0: Data Terminal Ready */ +#define UART_MCR_RTS (1 << 1) /* Bit 1: Request to Send */ +#define UART_MCR_LOOP (1 << 4) /* Bit 4: Loop Back Mode */ +#define UART_MCR_AFCE (1 << 5) /* Bit 5: Auto Flow Control Enable */ +#define UART_MCR_SIRE (1 << 6) /* Bit 6: SIR Mode Enable */ + +/* UART Line Status Register */ + +#define UART_LSR_DR (1 << 0) /* Bit 0: Data Ready */ +#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */ +#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ +#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ +#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ +#define UART_LSR_THRE (1 << 5) /* Bit 5: TX Holding Register Empty */ +#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ +#define UART_LSR_FIFOERR (1 << 7) /* Bit 7: RX Data Error in FIFO */ + +/* UART Modem Status Register */ + +#define UART_MSR_DCTS (1 << 0) /* Bit 0: Delta Clear to Send */ +#define UART_MSR_DDSR (1 << 1) /* Bit 1: Delta Data Set Ready */ +#define UART_MSR_TERI (1 << 2) /* Bit 2: Trailing Edge Ring Indicator */ +#define UART_MSR_DDCD (1 << 3) /* Bit 3: Delta Data Carrier Detect */ +#define UART_MSR_CTS (1 << 4) /* Bit 4: Line State of Clear To Send */ +#define UART_MSR_DSR (1 << 5) /* Bit 5: Line State of Data Set Ready */ +#define UART_MSR_RI (1 << 6) /* Bit 6: Line State of Ring Indicator */ +#define UART_MSR_DCD (1 << 7) /* Bit 7: Line State of Data Carrier Detect */ + +/* UART Scratch Register */ + +#define UART_SCH_MASK 0x000000ff + +/* UART Status Register */ + +#define UART_USR_BUSY (1 << 0) /* Bit 0: UART Busy Bit */ +#define UART_USR_TFNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */ +#define UART_USR_TFE (1 << 2) /* Bit 2: Transmit FIFO Empty */ +#define UART_USR_RFNE (1 << 3) /* Bit 3: Receive FIFO Not Empty */ +#define UART_USR_RFF (1 << 4) /* Bit 4: Receive FIFO Full */ + +/* UART Transmit FIFO Level */ + +#define UART_TFL_SHIFT (0) /* Bits 0-6: Transmit FIFO Level */ +#define UART_TFL_MASK (0x7f << UART_TFL_SHIFT) +# define UART_TFL(n) ((uint32_t)(n) << UART_TFL_SHIFT) + +/* UART Receive FIFO Level */ + +#define UART_RFL_SHIFT (0) /* Bits 0-6: Receive FIFO Level */ +#define UART_RFL_MASK (0x7f << UART_RFL_SHIFT) +# define UART_RFL(n) ((uint32_t)(n) << UART_RFL_SHIFT) + +/* Multimode register 0 */ + +#define UART_MM0_ELIN (1 << 3) /* Bit 3: Enable LIN header detection */ +#define UART_MM0_ETIG (1 << 5) /* Bit 5: Enable transmitter time guard */ +#define UART_MM0_ERTO (1 << 6) /* Bit 6: Enable receiver time-out */ +#define UART_MM0_EFBR (1 << 7) /* Bit 7: Enable fractional baud rate mode */ + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_UART_H */ diff --git a/arch/risc-v/src/mpfs/mpfs.h b/arch/risc-v/src/mpfs/mpfs.h new file mode 100755 index 00000000000..8d78f2c6060 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "chip.h" +#include "mpfs_lowputc.h" +#include "riscv_internal.h" +#include + +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_allocateheap.c b/arch/risc-v/src/mpfs/mpfs_allocateheap.c new file mode 100755 index 00000000000..c6bb153fb83 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_allocateheap.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "mpfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define KRAM_END CONFIG_RAM_END + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of User SRAM. + * + * The following memory map is assumed for the protect build. + * The kernel and user space have it's own dedicated heap space. + * + * User .data region Size determined at link time + * User .bss region Size determined at link time + * User heap Extends to the end of User SRAM + * Kernel .data region Size determined at link time + * Kernel .bss region Size determined at link time + * Kernel IDLE thread stack Size determined by CONFIG_IDLETHREAD_STACKSIZE + * Kernel heap Size determined by CONFIG_MM_KERNEL_HEAPSIZE + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the size and position of the user-space heap. + * This heap begins after the user-space .bss section. + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend; + size_t usize = (uintptr_t)USERSPACE->us_heapend - ubase; + + /* Return the user-space heap settings */ + + *heap_start = (FAR void *)ubase; + *heap_size = usize; + + /* Allow user-mode access to the user heap memory in PMP + * is already done in mpfs_userspace(). + */ + +#else + /* Return the heap settings */ + + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = KRAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * (and protects) the kernel-space heap. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +{ + /* Return the kernel heap settings. */ + + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = KRAM_END - g_idle_topstack; +} +#endif + +/**************************************************************************** + * Name: up_addregion + ****************************************************************************/ + +void up_addregion(void) +{ +} diff --git a/arch/xtensa/src/esp32/esp32_modtext.c b/arch/risc-v/src/mpfs/mpfs_clockconfig.c old mode 100644 new mode 100755 similarity index 66% rename from arch/xtensa/src/esp32/esp32_modtext.c rename to arch/risc-v/src/mpfs/mpfs_clockconfig.c index 2c738d45f6b..90aaee60fd3 --- a/arch/xtensa/src/esp32/esp32_modtext.c +++ b/arch/risc-v/src/mpfs/mpfs_clockconfig.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32/esp32_modtext.c + * arch/risc-v/src/mpfs/mpfs_clockconfig.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -23,74 +23,58 @@ ****************************************************************************/ #include -#include -#include -#include -#include +#include +#include #include +#include +#include + +#include "mpfs_clockconfig.h" +#include "riscv_arch.h" + /**************************************************************************** - * Public Data + * Pre-processor Definitions ****************************************************************************/ -extern uint32_t _smodtext; -extern uint32_t _emodtext; +#define OSC_FREQ 80000000UL /**************************************************************************** * Private Data ****************************************************************************/ -struct mm_heap_s g_module_text; +static uint64_t g_cpu_clock = MPFS_MSS_COREPLEX_CPU_CLK; /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: up_module_text_init - * - * Description: - * Initialize the module text allocator - * + * Name: mpfs_get_cpuclk ****************************************************************************/ -void up_module_text_init() +uint64_t mpfs_get_cpuclk(void) { - mm_initialize(&g_module_text, &_smodtext, &_emodtext - &_smodtext); + return g_cpu_clock; +} -#if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_FS_PROCFS_EXCLUDE_MEMINFO) - static struct procfs_meminfo_entry_s g_modtext_procfs; +/**************************************************************************** + * Name: mpfs_get_pll0clk + ****************************************************************************/ - g_modtext_procfs.name = "modtext"; - g_modtext_procfs.mallinfo = (void *)mm_mallinfo; - g_modtext_procfs.user_data = &g_module_text; - procfs_register_meminfo(&g_modtext_procfs); +#ifndef CONFIG_MPFS_WITH_QEMU +uint64_t mpfs_get_pll0clk(void) +{ + return 0; +} #endif -} /**************************************************************************** - * Name: up_module_text_memalign - * - * Description: - * Allocate memory for module text with the specified alignment. - * + * Name: mpfs_clockconfig ****************************************************************************/ -FAR void *up_module_text_memalign(size_t align, size_t size) +void mpfs_clockconfig(void) { - return mm_memalign(&g_module_text, align, size); -} - -/**************************************************************************** - * Name: up_module_text_free - * - * Description: - * Free memory for module text. - * - ****************************************************************************/ - -void up_module_text_free(FAR void *p) -{ - return mm_free(&g_module_text, p); + /* All is currently done in bootloader HSS */ } diff --git a/arch/risc-v/src/mpfs/mpfs_clockconfig.h b/arch/risc-v/src/mpfs/mpfs_clockconfig.h new file mode 100755 index 00000000000..2e317a76be8 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_clockconfig.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_CLOCKCONFIG_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "mpfs_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +EXTERN uint64_t mpfs_get_cpuclk(void); +EXTERN uint64_t mpfs_get_pll0clk(void); +EXTERN void mpfs_clockconfig(void); + +#if defined(__cplusplus) +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_CLOCKCONFIG_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_config.h b/arch/risc-v/src/mpfs/mpfs_config.h new file mode 100755 index 00000000000..48020199b69 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_config.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_config.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_CONFIG_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_MPFS_UART0) || defined(CONFIG_MPFS_UART1) || \ + defined(CONFIG_MPFS_UART2) || defined(CONFIG_MPFS_UART3) || \ + defined(CONFIG_MPFS_UART4) +# define HAVE_UART_DEVICE 1 +#endif + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_MPFS_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_MPFS_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_MPFS_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_CONFIG_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_dma.c b/arch/risc-v/src/mpfs/mpfs_dma.c new file mode 100755 index 00000000000..d2454c5ce47 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_dma.c @@ -0,0 +1,516 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_dma.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "riscv_arch.h" +#include "hardware/mpfs_dma.h" +#include "mpfs_dma.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DMA_MAX_TRANSACTION_SIZE (0x0f) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t g_channel_nextcfg_wsize[MPFS_DMA_NUM_CHANNELS] = +{ + DMA_MAX_TRANSACTION_SIZE, DMA_MAX_TRANSACTION_SIZE, + DMA_MAX_TRANSACTION_SIZE, DMA_MAX_TRANSACTION_SIZE +}; + +static uint8_t g_channel_nextcfg_rsize[MPFS_DMA_NUM_CHANNELS] = +{ + DMA_MAX_TRANSACTION_SIZE, DMA_MAX_TRANSACTION_SIZE, + DMA_MAX_TRANSACTION_SIZE, DMA_MAX_TRANSACTION_SIZE +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_dma_setup_transfer + * + * Description: + * Set DMA transfer config for channel. + * + * Parameters: + * channel - Channel number 0-3 + * config - Pointer to the config structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int mpfs_dma_setup_transfer(unsigned int channel, + struct mpfs_dma_channel_config *config) +{ + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel"); + return -EINVAL; + } + + if (config->src_addr == 0) + { + dmawarn("Illegal source address\n"); + return -EINVAL; + } + + if (config->dest_addr == 0) + { + dmawarn("Illegal destination address\n"); + return -EINVAL; + } + + /* If transaction is in progress, return error. */ + + if (getreg32(MPFS_DMA_REG_OFFSET(channel)) & DMA_CONTROL_RUN_MASK) + { + dmawarn("channel busy\n"); + return -EBUSY; + } + + /* Set or clear the interrupts for the transfer. */ + + if (config->enable_done_int) + { + dmainfo("enable done irq\n"); + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + 0, DMA_CONTROL_DONEIE); + } + else + { + dmainfo("disable done irq\n"); + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + DMA_CONTROL_DONEIE_MASK, 0); + } + + if (config->enable_err_int) + { + dmainfo("enable err irq\n"); + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + 0, DMA_CONTROL_ERRORIE); + } + else + { + dmainfo("disable err irq\n"); + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + DMA_CONTROL_ERRORIE_MASK, 0); + } + + /* clear Next registers. */ + + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + 0, DMA_CONTROL_CLAIM); + + /* clear Done and Error */ + + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + DMA_CONTROL_DONE_MASK | DMA_CONTROL_ERROR_MASK, 0); + + /* Setup the source and destination addresses. */ + + putreg64(config->dest_addr, + MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_DESTINATION_OFFSET); + putreg64(config->src_addr, + MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_SOURCE_OFFSET); + + /* Set the transfer size. */ + + putreg64(config->num_bytes, + MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_BYTES_OFFSET); + + /* Setup repeat and force order requirements. */ + + if (config->repeat) + { + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_CONFIG_OFFSET, + 0, DMA_NEXT_CONFIG_REPEAT); + } + else + { + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_CONFIG_OFFSET, + DMA_NEXT_CONFIG_REPEAT_MASK, 0); + } + + if (config->force_order) + { + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_CONFIG_OFFSET, + 0, DMA_NEXT_CONFIG_ORDER); + } + else + { + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_CONFIG_OFFSET, + DMA_NEXT_CONFIG_ORDER_MASK, 0); + } + + /* Set PDMA transaction size to maximum. */ + + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_CONFIG_OFFSET, + DMA_NEXT_CONFIG_WSIZE_MASK, + DMA_NEXT_CONFIG_WSIZE(g_channel_nextcfg_wsize[channel])); + + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_NEXT_CONFIG_OFFSET, + DMA_NEXT_CONFIG_RSIZE_MASK, + DMA_NEXT_CONFIG_RSIZE(g_channel_nextcfg_wsize[channel])); + + dmainfodumpbuffer("dma regs", (uint8_t *)MPFS_DMA_REG_OFFSET(channel), + MPFS_DMA_NEXT_SOURCE_OFFSET + 8); + + return OK; +} + +/**************************************************************************** + * Name: mpfs_dma_set_transaction_size + * + * Description: + * Set read and write transaction size for mpfs_dma_setup_transfer() + * + * Parameters: + * channel - Channel number 0-3 + * write_size - Write transaction size + * read_size - Read transaction size + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int mpfs_dma_set_transaction_size(unsigned int channel, + uint8_t write_size, uint8_t read_size) +{ + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return -EINVAL; + } + + if (write_size > DMA_MAX_TRANSACTION_SIZE) + { + dmawarn("Illegal write size\n"); + return -EINVAL; + } + + if (read_size > DMA_MAX_TRANSACTION_SIZE) + { + dmawarn("Illegal write size\n"); + return -EINVAL; + } + + dmainfo("new default dma transaction size. channel:%d write:%d, read:%d\n", + channel, write_size, read_size); + g_channel_nextcfg_wsize[channel] = write_size; + g_channel_nextcfg_rsize[channel] = read_size; + + return OK; +} + +/**************************************************************************** + * Name: mpfs_dma_start + * + * Description: + * Start DMA transfer. + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int mpfs_dma_start(unsigned int channel) +{ + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return -EINVAL; + } + + dmainfo("start dma channel:%d\n", channel); + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + 0, DMA_CONTROL_RUN); + + return OK; +} + +/**************************************************************************** + * Name: mpfs_dma_get_transfer_type + * + * Description: + * Return channels active config. + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * 0 - Illegal channel + * bit 2 - Repeat + * bit 3 - Strict ordering + * + ****************************************************************************/ + +uint32_t mpfs_dma_get_transfer_type(unsigned int channel) +{ + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return 0; + } + + return getreg32(MPFS_DMA_REG_OFFSET(channel) + + MPFS_DMA_EXEC_CONFIG_OFFSET); +} + +/**************************************************************************** + * Name: mpfs_dma_get_bytes_remaining + * + * Description: + * Return number of bytes remaining on transfer. + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * Number of bytes remaining + * + ****************************************************************************/ + +uint64_t mpfs_dma_get_bytes_remaining(unsigned int channel) +{ + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return 0; + } + + return getreg64(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_EXEC_BYTES_OFFSET); +} + +/**************************************************************************** + * Name: mpfs_dma_get_current_dest + * + * Description: + * Return current destination address of transfer + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * Current destination address + * + ****************************************************************************/ + +uint64_t mpfs_dma_get_current_destination(unsigned int channel) +{ + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return 0; + } + + return getreg64(MPFS_DMA_REG_OFFSET(channel) + + MPFS_DMA_EXEC_DESTINATION_OFFSET); +} + +/**************************************************************************** + * Name: mpfs_dma_get_current_source + * + * Description: + * Return current sourceaddress of transfer + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * Current source address + * + ****************************************************************************/ + +uint64_t mpfs_dma_get_current_source(unsigned int channel) +{ + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return 0; + } + + return getreg64(MPFS_DMA_REG_OFFSET(channel) + + MPFS_DMA_EXEC_SOURCE_OFFSET); +} + +/**************************************************************************** + * Name: mpfs_dma_get_complete_status + * + * Description: + * Return complete status for DMA channel + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * 0 - Not completed + * 1 - Transfer completed + * + ****************************************************************************/ + +int mpfs_dma_get_complete_status(unsigned int channel) +{ + uint32_t control; + + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return 0; + } + + control = getreg32(MPFS_DMA_REG_OFFSET(channel) + + MPFS_DMA_CONTROL_OFFSET); + + return ((control & DMA_CONTROL_DONE_MASK) >> DMA_CONTROL_DONE_SHIFT); +} + +/**************************************************************************** + * Name: mpfs_dma_get_error_status + * + * Description: + * Return error status for DMA channel + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * 0 - No Error + * 1 - Transfer Errror + * + ****************************************************************************/ + +int mpfs_dma_get_error_status(unsigned int channel) +{ + uint32_t control; + + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return 0; + } + + control = getreg32(MPFS_DMA_REG_OFFSET(channel) + + MPFS_DMA_CONTROL_OFFSET); + + return ((control & DMA_CONTROL_ERROR_MASK) >> DMA_CONTROL_ERROR_SHIFT); +} + +/**************************************************************************** + * Name: mpfs_dma_clear_complete_status + * + * Description: + * Clear and return complete status for DMA channel + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * 0 - Not completed + * 1 - Transfer completed + * + ****************************************************************************/ + +int mpfs_dma_clear_complete_status(unsigned int channel) +{ + int status = 0; + uint32_t control; + + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return 0; + } + + control = getreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET); + if (control & DMA_CONTROL_DONE) + { + status = 1; + } + + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + DMA_CONTROL_DONE_MASK, 0); + + return status; +} + +/**************************************************************************** + * Name: mpfs_dma_clear_error_status + * + * Description: + * Clear and return error status for DMA channel + * + * Parameters: + * channel - Channel number 0-3 + * + * Returned Value: + * 0 - No Error + * 1 - Transfer Errror + * + ****************************************************************************/ + +int mpfs_dma_clear_error_status(unsigned int channel) +{ + int status = 0; + uint32_t control; + + if (channel >= MPFS_DMA_NUM_CHANNELS) + { + dmawarn("Illegal channel\n"); + return 0; + } + + control = getreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET); + if (control & DMA_CONTROL_ERROR) + { + status = 1; + } + + modifyreg32(MPFS_DMA_REG_OFFSET(channel) + MPFS_DMA_CONTROL_OFFSET, + DMA_CONTROL_ERROR, 0); + + return status; +} diff --git a/arch/risc-v/src/mpfs/mpfs_dma.h b/arch/risc-v/src/mpfs/mpfs_dma.h new file mode 100755 index 00000000000..7f401a79383 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_dma.h @@ -0,0 +1,93 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_dma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_DMA_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "mpfs_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MPFS_DMA_NUM_CHANNELS (4) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +struct mpfs_dma_channel_config +{ + uint64_t src_addr; /* source address */ + uint64_t dest_addr; /* destination address */ + uint64_t num_bytes; /* Number of bytes to be transfered. (Base-2) */ + uint8_t enable_done_int; /* enable transfer complete interrupt */ + uint8_t enable_err_int; /* enable transfer error interrupt */ + uint8_t repeat; /* repeat the transaction */ + uint8_t force_order; /* Enforces strict ordering by only + * allowing one of each transfer type + * in-flight at a time */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +EXTERN int mpfs_dma_setup_transfer(unsigned int channel, + struct mpfs_dma_channel_config *config); +EXTERN int mpfs_dma_set_transaction_size(unsigned int channel, + uint8_t write_size, + uint8_t read_size); +EXTERN int mpfs_dma_start(unsigned int channel); +EXTERN uint32_t mpfs_dma_get_transfer_type(unsigned int channel); +EXTERN uint64_t mpfs_dma_get_bytes_remaining(unsigned int channel); +EXTERN uint64_t mpfs_dma_get_current_destination(unsigned int channel); +EXTERN uint64_t mpfs_dma_get_current_source(unsigned int channel); +EXTERN int mpfs_dma_get_complete_status(unsigned int channel); +EXTERN int mpfs_dma_get_error_status(unsigned int channel); +EXTERN int mpfs_dma_clear_complete_status(unsigned int channel); +EXTERN int mpfs_dma_clear_error_status(unsigned int channel); + +#if defined(__cplusplus) +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_DMA_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_gpio.c b/arch/risc-v/src/mpfs/mpfs_gpio.c new file mode 100644 index 00000000000..8e9e74be846 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_gpio.c @@ -0,0 +1,184 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "riscv_arch.h" + +#include "hardware/mpfs_gpio.h" +#include "mpfs_gpio.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +static uintptr_t g_gpio_base[] = +{ + MPFS_GPIO0_LO_BASE, /* Bank-0 Normal GPIO */ + MPFS_GPIO1_LO_BASE, /* Bank-1 Normal GPIO */ + MPFS_GPIO2_LO_BASE /* Bank-2 Fabric only */ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + * Returned Value: + * OK on success + * ERROR on invalid port. + * + ****************************************************************************/ + +int mpfs_configgpio(gpio_pinset_t cfgset) +{ + uintptr_t baseaddr; + uint32_t cfg = 0; + uint8_t pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint8_t bank = (cfgset & GPIO_BANK_MASK) >> GPIO_BANK_SHIFT; + uint8_t irq_mode = (cfgset & GPIO_IRQ_MASK) >> GPIO_IRQ_SHIFT; + + if (bank == 3) + { + return ERROR; + } + + /* REVISIT: limit the gpios as + * bank0 0 - 13 + * bank1 0 - 23 + * bank2 0 - 31 + */ + + baseaddr = g_gpio_base[bank] + (pin * sizeof(uint32_t)); + + if (cfgset & GPIO_INPUT) + { + cfg |= GPIO_CONFIG_EN_IN; + } + + if (cfgset & GPIO_OUTPUT) + { + cfg |= GPIO_CONFIG_EN_OUT; + } + + if (cfgset & GPIO_BUFFER_ENABLE) + { + cfg |= GPIO_CONFIG_EN_OE_BUF; + } + + if (cfgset & GPIO_IRQ_ENABLE) + { + cfg |= GPIO_CONFIG_EN_INT; + + /* Clear irq bit */ + + putreg32(1 << pin, baseaddr + MPFS_GPIO_INTR_OFFSET); + } + + /* set irq mode bits */ + + irq_mode &= 7; + cfg |= irq_mode << 5; + + putreg32(cfg, baseaddr); + + return OK; +} + +/**************************************************************************** + * Name: mpfs_gpio_deinit + * + * Description: + * Deinit a GPIO (Set GPIO to input state) + * + * Returned Value: + * OK on success + * ERROR on invalid port. + * + ****************************************************************************/ + +/* REVISIT: */ + +int mpfs_gpio_deinit(uint8_t pin) +{ + mpfs_configgpio(pin); + return OK; +} + +/**************************************************************************** + * Name: mpfs_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void mpfs_gpiowrite(gpio_pinset_t pinset, bool value) +{ + uint8_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint8_t bank = (pinset & GPIO_BANK_MASK) >> GPIO_BANK_SHIFT; + uintptr_t baseaddr = g_gpio_base[bank]; + + if (bank == 3) + { + return; + } + + if (value) + { + putreg32((1 << pin), baseaddr + MPFS_GPIO_SET_BITS_OFFSET); + } + else + { + putreg32((1 << pin), baseaddr + MPFS_GPIO_CLEAR_BITS_OFFSET); + } +} + +/**************************************************************************** + * Name: mpfs_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool mpfs_gpioread(gpio_pinset_t pinset) +{ + uint8_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint8_t bank = (pinset & GPIO_BANK_MASK) >> GPIO_BANK_SHIFT; + uintptr_t baseaddr = g_gpio_base[bank]; + + if (bank == 3) + { + return 0; + } + + return ((getreg32(baseaddr + MPFS_GPIO_GPIN_OFFSET) & (1 << pin)) ? 1 : 0); +} + diff --git a/arch/risc-v/src/mpfs/mpfs_gpio.h b/arch/risc-v/src/mpfs/mpfs_gpio.h new file mode 100644 index 00000000000..2c15ef084e2 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_gpio.h @@ -0,0 +1,272 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_GPIO_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +#include +#include +#endif + +#include +#include + +#include "chip.h" +#include "hardware/mpfs_gpio.h" + +/**************************************************************************** + * Pre-Processor Declarations + ****************************************************************************/ + +/* Bit-encoded input to mpfs_configgpio() */ + +/* Each port bit of the general-purpose I/O (GPIO) ports can be individually + * configured by software in several modes: + * + * - Input + * - Output + * - Output with buffer enable + * - Output with buffer disable + * - Input with irq level high + * - Input with irq level low + * - Input with irq edge positive + * - Input with irq edge negative + * + * 16-bit Encoding: 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * MMBI III. .bbP PPPP + */ + +/* Mode: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * MM.. .... .... .... + */ + +#define GPIO_MODE_SHIFT (14) /* Bit 14-15: IO Mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_NOINOUT (0 << GPIO_MODE_SHIFT) /* No input or output */ +# define GPIO_INPUT (1 << GPIO_MODE_SHIFT) /* Input Enable */ +# define GPIO_OUTPUT (2 << GPIO_MODE_SHIFT) /* Output Enable */ + +/* Output buffer: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * ..B. .... .... .... + */ + +#define GPIO_BUFFER_SHIFT (13) /* Bit 13: Output buffer enabled */ +#define GPIO_BUFFER_MASK (1 << GPIO_BUFFER_SHIFT) +#define GPIO_BUFFER_DISABLE (0 << GPIO_BUFFER_SHIFT) /* Disable Output buffer */ +#define GPIO_BUFFER_ENABLE (1 << GPIO_BUFFER_SHIFT) /* Enable Output buffer */ + +/* Irq: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * ...I III. .... .... + */ + +#define GPIO_IRQ_SHIFT (9) /* Bits 9-12: Irq Mode */ +#define GPIO_IRQ_MASK (15 << GPIO_IRQ_SHIFT) +#define GPIO_IRQ_HIGH (0 << GPIO_IRQ_SHIFT) +#define GPIO_IRQ_LOW (1 << GPIO_IRQ_SHIFT) +#define GPIO_IRQ_EDGE_POS (2 << GPIO_IRQ_SHIFT) +#define GPIO_IRQ_EDGE_NEG (3 << GPIO_IRQ_SHIFT) +#define GPIO_IRQ_EDGE_BOTH (4 << GPIO_IRQ_SHIFT) +#define GPIO_IRQ_ENABLE (8 << GPIO_IRQ_SHIFT) +#define GPIO_IRQ_DISABLE (0 << GPIO_IRQ_SHIFT) + +/* Bank: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * .... .... .bb. .... + */ + +#define GPIO_BANK_SHIFT (5) /* Bits 5-6: Bank */ +#define GPIO_BANK_MASK (3 << GPIO_BANK_SHIFT) +#define GPIO_BANK0 (0 << GPIO_BANK_SHIFT) +#define GPIO_BANK1 (1 << GPIO_BANK_SHIFT) +#define GPIO_BANK2 (2 << GPIO_BANK_SHIFT) + +/* This identifies the bit in the bank: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * .... .... ...P PPPP + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The smallest integer type that can hold the GPIO encoding */ + +typedef uint16_t gpio_pinset_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + * Returned Value: + * OK on success + * ERROR on invalid port. + * + ****************************************************************************/ + +int mpfs_configgpio(gpio_pinset_t cfgset); + +/**************************************************************************** + * Name: mpfs_gpio_deinit + * + * Description: + * Deinit a GPIO (Set GPIO to floating input state) + * + * Returned Value: + * OK on success + * ERROR on invalid port. + * + ****************************************************************************/ + +int mpfs_gpio_deinit(uint8_t pin); + +/**************************************************************************** + * Name: mpfs_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void mpfs_gpiowrite(gpio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: mpfs_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool mpfs_gpioread(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: mpfs_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int mpfs_gpio_initialize(void); + +/**************************************************************************** + * Function: mpfs_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO_INFO +int mpfs_dumpgpio(gpio_pinset_t pinset, const char *msg); +#else +#define mpfs_dumpgpio(p, m) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_GPIO_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_head.S b/arch/risc-v/src/mpfs/mpfs_head.S new file mode 100755 index 00000000000..14e76506408 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_head.S @@ -0,0 +1,307 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_head.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "chip.h" +#include "mpfs_memorymap.h" +#include "riscv_internal.h" + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .global exception_common + + /* Imported symbols */ + + .extern __trap_vec + + .section .text + .global __start_mpfs + +__start_mpfs: + + /* invalid all MMU TLB Entry */ + + sfence.vma x0, x0 + + /* Disable all interrupts (i.e. timer, external) in mie */ + + csrw mie, zero + csrw mip, zero + + /* Initialize the Machine Trap Vector */ + + la t0, __trap_vec + csrw mtvec, t0 + + /* Make sure that mtvec is updated before continuing */ + +1: + csrr t1, mtvec + bne t0, t1, 1b + + /* Init delegation registers, mideleg, medeleg, if a U54 + * These are not initialised by the hardware and come up in a random state + */ + + csrr a0, mhartid + beqz a0, .skip_e51 + csrw mideleg, 0 + csrw medeleg, 0 +.skip_e51: + + /* mscratch must be init to zero- we are not using scratch memory */ + + csrw mscratch, zero + csrw mcause, zero + csrw mepc, zero + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + /* enable FPU and accelerator if present, setting ignored on E51 + * 15,16 = MSTATUS_XS, 17,18 = MSTATUS_MPRV + * not defined on riscv-v/include/csr.h + */ + + li t0, MSTATUS_FS_DIRTY | (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18) + csrs mstatus, t0 + + /* Init floating point control register to zero. skip if E51 */ + + csrr a0, mhartid + beqz a0, .no_float +#ifdef __riscv_flen + fscsr x0 +#endif +.no_float: + + /* Set stack pointer to the idle thread stack */ + + la sp, MPFS_IDLESTACK_TOP + + +/* initialize global pointer, global data + * The __global_pointer is allocated in the linker script. + * It points to a location between _sdata and _edata as the offsets used in the gp are +/- 2k + * See https://www.sifive.com/blog/2017/08/28/all-aboard-part-3-linker-relaxation-in-riscv-toolchain/ + * see: http://www.rowleydownload.co.uk/arm/documentation/gnu/as/RISC_002dV_002dDirectives.html + */ + +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + + /* Jump to __mpfs_start with mhartid in a0 */ + + j __mpfs_start + + /* We shouldn't return from __mpfs_start + * in case of return, loop forever. nop's added so can be seen in debugger + */ + +1: + nop + nop + j 1b + + .global _init + .global _fini + +_init: +_fini: + + /* These don't have to do anything since we use init_array/fini_array. */ + + ret + +/**************************************************************************** + * Name: exception_common + ****************************************************************************/ + +exception_common: + + addi sp, sp, -XCPTCONTEXT_SIZE + + sd x1, 1*8(sp) /* ra */ + + /* leave gp(x3) in 3*8(sp) untouched */ + + sd x4, 4*8(sp) /* tp */ + sd x5, 5*8(sp) /* t0 */ + sd x6, 6*8(sp) /* t1 */ + sd x7, 7*8(sp) /* t2 */ + sd x8, 8*8(sp) /* s0 */ + sd x9, 9*8(sp) /* s1 */ + sd x10, 10*8(sp) /* a0 */ + sd x11, 11*8(sp) /* a1 */ + sd x12, 12*8(sp) /* a2 */ + sd x13, 13*8(sp) /* a3 */ + sd x14, 14*8(sp) /* a4 */ + sd x15, 15*8(sp) /* a5 */ + sd x16, 16*8(sp) /* a6 */ + sd x17, 17*8(sp) /* a7 */ + sd x18, 18*8(sp) /* s2 */ + sd x19, 19*8(sp) /* s3 */ + sd x20, 20*8(sp) /* s4 */ + sd x21, 21*8(sp) /* s5 */ + sd x22, 22*8(sp) /* s6 */ + sd x23, 23*8(sp) /* s7 */ + sd x24, 24*8(sp) /* s8 */ + sd x25, 25*8(sp) /* s9 */ + sd x26, 26*8(sp) /* s10 */ + sd x27, 27*8(sp) /* s11 */ + sd x28, 28*8(sp) /* t3 */ + sd x29, 29*8(sp) /* t4 */ + sd x30, 30*8(sp) /* t5 */ + sd x31, 31*8(sp) /* t6 */ + + csrr s0, mstatus + sd s0, 32*8(sp) /* mstatus */ + + addi s0, sp, XCPTCONTEXT_SIZE + sd s0, 2*8(sp) /* original SP */ + + /* Setup arg0(exception cause), arg1(context) */ + + csrr a0, mcause /* exception cause */ + csrr s0, mepc + sd s0, 0(sp) /* exception PC */ + + mv a1, sp /* context = sp */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 + /* Load mhartid (cpuid) */ + + csrr s0, mhartid + + /* Switch to interrupt stack TODO: select correct for hart */ + + la sp, g_intstacktop + +#endif + + /* Call interrupt handler in C */ + + jal x1, mpfs_dispatch_irq + + /* If context switch is needed, return a new sp */ + + mv sp, a0 + ld s0, 0(sp) /* restore mepc */ + csrw mepc, s0 + + ld s0, 32*8(sp) /* restore mstatus */ + csrw mstatus, s0 + + /* leave gp(x3) in 3*8(sp) untouched */ + + ld x4, 4*8(sp) /* tp */ + ld x5, 5*8(sp) /* t0 */ + ld x6, 6*8(sp) /* t1 */ + ld x7, 7*8(sp) /* t2 */ + ld x8, 8*8(sp) /* s0 */ + ld x9, 9*8(sp) /* s1 */ + ld x10, 10*8(sp) /* a0 */ + ld x11, 11*8(sp) /* a1 */ + ld x12, 12*8(sp) /* a2 */ + ld x13, 13*8(sp) /* a3 */ + ld x14, 14*8(sp) /* a4 */ + ld x15, 15*8(sp) /* a5 */ + ld x16, 16*8(sp) /* a6 */ + ld x17, 17*8(sp) /* a7 */ + ld x18, 18*8(sp) /* s2 */ + ld x19, 19*8(sp) /* s3 */ + ld x20, 20*8(sp) /* s4 */ + ld x21, 21*8(sp) /* s5 */ + ld x22, 22*8(sp) /* s6 */ + ld x23, 23*8(sp) /* s7 */ + ld x24, 24*8(sp) /* s8 */ + ld x25, 25*8(sp) /* s9 */ + ld x26, 26*8(sp) /* s10 */ + ld x27, 27*8(sp) /* s11 */ + ld x28, 28*8(sp) /* t3 */ + ld x29, 29*8(sp) /* t4 */ + ld x30, 30*8(sp) /* t5 */ + ld x31, 31*8(sp) /* t6 */ + + ld x1, 1*8(sp) /* ra */ + + ld sp, 2*8(sp) /* restore original sp */ + + /* Return from Machine Interrupt */ + + mret + +/************************************************************************************ + * Name: g_intstackalloc and g_intstackbase + ************************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 + .bss + .balign 16 + .global g_intstackalloc + .global g_intstacktop + .type g_intstackalloc, object + .type g_intstacktop, object +g_intstackalloc: + .skip (((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)) +g_intstacktop: + .size g_intstacktop, 0 + .size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15) +#endif diff --git a/arch/risc-v/src/mpfs/mpfs_i2c.c b/arch/risc-v/src/mpfs/mpfs_i2c.c new file mode 100755 index 00000000000..55e49e6748c --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_i2c.c @@ -0,0 +1,852 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "mpfs_i2c.h" + +#include "riscv_arch.h" +#include "hardware/mpfs_i2c.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MPFS_SYSREG_SOFT_RESET_CR (MPFS_SYSREG_BASE + \ + MPFS_SYSREG_SOFT_RESET_CR_OFFSET) +#define MPFS_SYSREG_SUBBLK_CLOCK_CR (MPFS_SYSREG_BASE + \ + MPFS_SYSREG_SUBBLK_CLOCK_CR_OFFSET) + +#define MPFS_I2C_CTRL_OFFSET 0x00 +#define MPFS_I2C_STATUS_OFFSET 0x04 +#define MPFS_I2C_DATA_OFFSET 0x08 +#define MPFS_I2C_SLAVE0ADR_OFFSET 0x0C +#define MPFS_I2C_SMBUS_OFFSET 0x10 +#define MPFS_I2C_FREQ_OFFSET 0x14 + +#define MPFS_I2C_CTRL (priv->hw_base + MPFS_I2C_CTRL_OFFSET) +#define MPFS_I2C_STATUS (priv->hw_base + MPFS_I2C_STATUS_OFFSET) +#define MPFS_I2C_DATA (priv->hw_base + MPFS_I2C_DATA_OFFSET) +#define MPFS_I2C_ADDR (priv->hw_base + MPFS_I2C_SLAVE0ADR_OFFSET) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef enum mpfs_i2c_status +{ + MPFS_I2C_SUCCESS = 0u, + MPFS_I2C_IN_PROGRESS, + MPFS_I2C_FAILED, + MPFS_I2C_TIMED_OUT +} mpfs_i2c_status_t; + +typedef enum mpfs_i2c_clock_divider +{ + MPFS_I2C_PCLK_DIV_256 = 0u, + MPFS_I2C_PCLK_DIV_224, + MPFS_I2C_PCLK_DIV_192, + MPFS_I2C_PCLK_DIV_160, + MPFS_I2C_PCLK_DIV_960, + MPFS_I2C_PCLK_DIV_120, + MPFS_I2C_PCLK_DIV_60, + MPFS_I2C_BCLK_DIV_8 +} mpfs_i2c_clk_div_t; + +static int mpfs_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, + int count); + +#ifdef CONFIG_I2C_RESET +static int mpfs_i2c_reset(struct i2c_master_s *dev); +#endif + +static const struct i2c_ops_s mpfs_i2c_ops = +{ + .transfer = mpfs_i2c_transfer, +#ifdef CONFIG_I2C_RESET + .reset = mpfs_i2c_reset, +#endif +}; + +struct mpfs_i2c_priv_s +{ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + uint32_t id; /* I2C hardware identification */ + uintptr_t hw_base; /* I2C bus base address */ + uint16_t plic_irq; /* Platform PLIC irq */ + struct i2c_msg_s *msgv; /* Message list */ + mpfs_i2c_clk_div_t bus_divider; /* Bus divider */ + + uint8_t msgid; /* Current message ID */ + ssize_t bytes; /* Processed data bytes */ + + uint8_t ser_address; /* Own i2c address */ + uint8_t target_addr; /* Target i2c address */ + sem_t sem_excl; /* Mutual exclusion semaphore */ + sem_t sem_isr; /* Interrupt wait semaphore */ + int refs; /* Reference count */ + + const uint8_t *tx_buffer; /* Tx buffer location */ + uint16_t tx_size; /* Tx buffer size */ + uint16_t tx_idx; /* Currently accessed index */ + + uint8_t *rx_buffer; /* Rx buffer location */ + uint16_t rx_size; /* Rx buffer size */ + uint16_t rx_idx; /* Currently accessed index */ + + mpfs_i2c_status_t status; /* Bus driver status */ +}; + +#ifdef CONFIG_MPFS_I2C0 +static struct mpfs_i2c_priv_s g_mpfs_i2c0_lo_priv = +{ + .ops = &mpfs_i2c_ops, + .id = 0, + .hw_base = MPFS_I2C0_LO_BASE, + .plic_irq = MPFS_IRQ_I2C0_MAIN, + .msgv = NULL, + .bus_divider = MPFS_I2C_PCLK_DIV_256, + .ser_address = 0x21, + .target_addr = 0, + .refs = 0, + .tx_size = 0, + .tx_idx = 0, + .rx_size = 0, + .rx_idx = 0, + .status = MPFS_I2C_SUCCESS +}; +#endif /* CONFIG_MPFS_I2C0 */ + +#ifdef CONFIG_MPFS_I2C1 +static struct mpfs_i2c_priv_s g_mpfs_i2c1_lo_priv = +{ + .ops = &mpfs_i2c_ops, + .id = 1, + .hw_base = MPFS_I2C1_LO_BASE, + .plic_irq = MPFS_IRQ_I2C1_MAIN, + .msgv = NULL, + .bus_divider = MPFS_I2C_PCLK_DIV_256, + .ser_address = 0x21, + .target_addr = 0, + .refs = 0, + .tx_size = 0, + .tx_idx = 0, + .rx_size = 0, + .rx_idx = 0, + .status = MPFS_I2C_SUCCESS +}; +#endif /* CONFIG_MPFS_I2C1 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_disable_interrupts + * + * Description: + * Disable all interrupts. + * + * Returned Value: + * primask (current interrupt status) + * + ****************************************************************************/ + +static irqstate_t mpfs_disable_interrupts(void) +{ + irqstate_t primask; + primask = up_irq_save(); + return primask; +} + +/**************************************************************************** + * Name: mpfs_restore_interrupts + * + * Description: + * Restore interrupts. + * + * Parameters: + * primask - Earlier stored irqstate + * + ****************************************************************************/ + +static void mpfs_restore_interrupts(irqstate_t primask) +{ + up_irq_restore(primask); +} + +/**************************************************************************** + * Name: mpfs_i2c_init + * + * Description: + * Initialize and enable an I2C bus + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void mpfs_i2c_init(struct mpfs_i2c_priv_s *priv) +{ + uint32_t clock_speed; + uint32_t primask; + + primask = mpfs_disable_interrupts(); + + if (priv->id == 0) + { + modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0, + (1 << SYSREG_SOFT_RESET_CR_I2C0)); + + modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, + (1 << SYSREG_SOFT_RESET_CR_I2C0), 0); + + modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0, + (1 << SYSREG_SUBBLK_CLOCK_CR_I2C0)); + } + else + { + modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0, + (1 << SYSREG_SOFT_RESET_CR_I2C1)); + + modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, + (1 << SYSREG_SOFT_RESET_CR_I2C1), 0); + + modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0, + (1 << SYSREG_SUBBLK_CLOCK_CR_I2C1)); + } + + clock_speed = priv->bus_divider; + + /* Update the clock divider */ + + modifyreg32(MPFS_I2C_CTRL, + MPFS_I2C_CTRL_CR2_MASK | + MPFS_I2C_CTRL_CR1_MASK | + MPFS_I2C_CTRL_CR0_MASK, + (((clock_speed >> 2u) & 0x01u) << MPFS_I2C_CTRL_CR2) | + (((clock_speed >> 1u) & 0x01u) << MPFS_I2C_CTRL_CR1) | + (((clock_speed & 0x01u) << MPFS_I2C_CTRL_CR0))); + + /* This is our own address, not the target chip */ + + putreg32(priv->ser_address, MPFS_I2C_ADDR); + + /* Enable i2c bus */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_ENS1_MASK, + MPFS_I2C_CTRL_ENS1_MASK); + + mpfs_restore_interrupts(primask); +} + +/**************************************************************************** + * Name: mpfs_i2c_deinit + * + * Description: + * Disable I2C hardware. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void mpfs_i2c_deinit(struct mpfs_i2c_priv_s *priv) +{ + up_disable_irq(priv->plic_irq); + irq_detach(priv->plic_irq); +} + +/**************************************************************************** + * Name: mpfs_i2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int mpfs_i2c_sem_waitdone(struct mpfs_i2c_priv_s *priv) +{ + struct timespec abstime; + int ret; + + clock_gettime(CLOCK_REALTIME, &abstime); + + abstime.tv_sec += 10; + abstime.tv_nsec += 0; + + ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime); + + return ret; +} + +/**************************************************************************** + * Name: mpfs_i2c_sem_wait + * + * Description: + * Take the exclusive access, waiting as necessary. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int mpfs_i2c_sem_wait(struct mpfs_i2c_priv_s *priv) +{ + return nxsem_wait_uninterruptible(&priv->sem_excl); +} + +/**************************************************************************** + * Name: mpfs_i2c_sem_post + * + * Description: + * Release the mutual exclusion semaphore. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void mpfs_i2c_sem_post(struct mpfs_i2c_priv_s *priv) +{ + nxsem_post(&priv->sem_excl); +} + +/**************************************************************************** + * Name: mpfs_i2c_sem_destroy + * + * Description: + * Destroy semaphores. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void mpfs_i2c_sem_destroy(struct mpfs_i2c_priv_s *priv) +{ + nxsem_destroy(&priv->sem_excl); + nxsem_destroy(&priv->sem_isr); +} + +/**************************************************************************** + * Name: mpfs_i2c_sem_init + * + * Description: + * Initialize semaphores. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static inline void mpfs_i2c_sem_init(struct mpfs_i2c_priv_s *priv) +{ + nxsem_init(&priv->sem_excl, 0, 1); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + nxsem_init(&priv->sem_isr, 0, 0); + nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE); +} + +/**************************************************************************** + * Name: mpfs_i2c_irq + * + * Description: + * This is the common I2C interrupt handler. It will be invoked when an + * interrupt is received on the device. + * + * Parameters: + * cpuint - CPU interrupt index + * context - Context data from the ISR + * arg - Opaque pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int mpfs_i2c_irq(int cpuint, void *context, void *arg) +{ + struct mpfs_i2c_priv_s *priv = (struct mpfs_i2c_priv_s *)arg; + struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; + volatile uint32_t status; + uint8_t clear_irq = 1u; + + DEBUGASSERT(msg != NULL); + + status = getreg32(MPFS_I2C_STATUS); + + switch (status) + { + case MPFS_I2C_ST_START: + case MPFS_I2C_ST_RESTART: + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STA_MASK, 0); + putreg32((priv->target_addr << 1) | (msg->flags & I2C_M_READ), + MPFS_I2C_DATA); + + if (msg->flags & I2C_M_READ) + { + priv->rx_idx = 0u; + } + else + { + priv->tx_idx = 0u; + } + break; + + case MPFS_I2C_ST_LOST_ARB: + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STA_MASK, + MPFS_I2C_CTRL_STA_MASK); + break; + + case MPFS_I2C_ST_SLAW_NACK: + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STO_MASK, + MPFS_I2C_CTRL_STO_MASK); + priv->status = MPFS_I2C_FAILED; + break; + + case MPFS_I2C_ST_SLAW_ACK: + case MPFS_I2C_ST_TX_DATA_ACK: + if (priv->tx_idx < priv->tx_size) + { + DEBUGASSERT(priv->tx_buffer != NULL); + putreg32(priv->tx_buffer[priv->tx_idx], MPFS_I2C_DATA); + priv->tx_idx++; + } + else if (msg->flags & I2C_M_NOSTOP) + { + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STA_MASK, + MPFS_I2C_CTRL_STA_MASK); + + /* Jump to the next message */ + + priv->msgid++; + } + else + { + /* Send stop condition */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STO_MASK, + MPFS_I2C_CTRL_STO_MASK); + priv->status = MPFS_I2C_SUCCESS; + } + break; + + case MPFS_I2C_ST_TX_DATA_NACK: + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STO_MASK, + MPFS_I2C_CTRL_STO_MASK); + priv->status = MPFS_I2C_FAILED; + break; + + case MPFS_I2C_ST_SLAR_ACK: /* SLA+R tx'ed. */ + if (priv->rx_size > 1u) + { + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_AA_MASK, + MPFS_I2C_CTRL_AA_MASK); + } + else if (priv->rx_size == 1u) + { + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_AA_MASK, 0); + } + else /* priv->rx_size == 0u */ + { + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_AA_MASK, + MPFS_I2C_CTRL_AA_MASK); + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STO_MASK, + MPFS_I2C_CTRL_STO_MASK); + priv->status = MPFS_I2C_SUCCESS; + } + break; + + case MPFS_I2C_ST_SLAR_NACK: /* SLA+R tx'ed; send a stop condition */ + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STO_MASK, + MPFS_I2C_CTRL_STO_MASK); + priv->status = MPFS_I2C_FAILED; + break; + + case MPFS_I2C_ST_RX_DATA_ACK: + + /* Data byte received, ACK returned */ + + DEBUGASSERT(priv->rx_buffer != NULL); + priv->rx_buffer[priv->rx_idx] = (uint8_t)getreg32(MPFS_I2C_DATA); + priv->rx_idx++; + + if (priv->rx_idx >= (priv->rx_size - 1u)) + { + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_AA_MASK, 0); + } + break; + + case MPFS_I2C_ST_RX_DATA_NACK: + + /* Data byte received, NACK returned */ + + DEBUGASSERT(priv->rx_buffer != NULL); + priv->rx_buffer[priv->rx_idx] = (uint8_t)getreg32(MPFS_I2C_DATA); + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STO_MASK, + MPFS_I2C_CTRL_STO_MASK); + + priv->status = MPFS_I2C_SUCCESS; + break; + + case MPFS_I2C_ST_RESET_ACTIVATED: + case MPFS_I2C_ST_BUS_ERROR: /* Bus errors */ + default: + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STA_MASK, 0); + + if (priv->status == MPFS_I2C_IN_PROGRESS) + { + priv->status = MPFS_I2C_FAILED; + } + + break; + } + + if (priv->status != MPFS_I2C_IN_PROGRESS) + { + nxsem_post(&priv->sem_isr); + } + + if (clear_irq) + { + /* Clear interrupt. */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0); + } + + /* Read back the status register to ensure the last I2C registers write + * took place in a system built around a bus making use of posted writes. + */ + + status = getreg32(MPFS_I2C_STATUS); + + return 0; +} + +/**************************************************************************** + * Name: mpfs_i2c_sendstart + * + * Description: + * Send I2C start condition and enable the PLIC irq + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void mpfs_i2c_sendstart(struct mpfs_i2c_priv_s *priv) +{ + uint32_t primask; + + primask = mpfs_disable_interrupts(); + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STA_MASK, MPFS_I2C_CTRL_STA_MASK); + + up_enable_irq(priv->plic_irq); + + mpfs_restore_interrupts(primask); +} + +static int mpfs_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, + int count) +{ + struct mpfs_i2c_priv_s *priv = (struct mpfs_i2c_priv_s *)dev; + int ret = OK; + + i2cinfo("Starting transfer request of %d message(s):\n", count); + DEBUGASSERT(count > 0); + + ret = mpfs_i2c_sem_wait(priv); + if (ret < 0) + { + return ret; + } + + if (priv->status != MPFS_I2C_SUCCESS) + { + priv->status = MPFS_I2C_SUCCESS; + } + + priv->msgv = msgs; + + for (int i = 0; i < count; i++) + { + priv->bytes = 0; + priv->msgid = i; + priv->status = MPFS_I2C_IN_PROGRESS; + priv->target_addr = msgs[i].addr; + + if (msgs[i].flags & I2C_M_READ) + { + priv->rx_buffer = msgs[i].buffer; + priv->rx_size = msgs[i].length; + priv->rx_idx = 0; + } + else + { + priv->tx_buffer = msgs[i].buffer; + priv->tx_size = msgs[i].length; + priv->tx_idx = 0; + + if (msgs[i].flags & I2C_M_NOSTOP) + { + /* Support only write + read combinations */ + + DEBUGASSERT(!(msgs[i].flags & I2C_M_READ)); + + /* Combine write + read transaction into one */ + + if (((i + 1) < count) && (msgs[i + 1].flags & I2C_M_READ)) + { + priv->rx_buffer = msgs[i + 1].buffer; + priv->rx_size = msgs[i + 1].length; + priv->rx_idx = 0; + i++; + } + } + } + + i2cinfo("Sending message %" PRIu8 "...\n", priv->msgid); + + mpfs_i2c_sendstart(priv); + + if (mpfs_i2c_sem_waitdone(priv) < 0) + { + i2cinfo("Message %" PRIu8 " timed out.\n", priv->msgid); + ret = -ETIMEDOUT; + break; + } + else + { + if (priv->status != MPFS_I2C_SUCCESS) + { + i2cinfo("Transfer error %" PRIu32 "\n", priv->status); + ret = -EIO; + break; + } + else + { + priv->status = MPFS_I2C_SUCCESS; + ret = OK; + } + } + + i2cinfo("Message %" PRIu8 " transfer complete.\n", priv->msgid); + } + + mpfs_i2c_sem_post(priv); + + return ret; +} + +/**************************************************************************** + * Name: mpfs_i2c_reset + * + * Description: + * Performs an I2C bus reset. This may be used to recover from a buggy + * situation. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) on success; this should not fail. + * + ****************************************************************************/ +#ifdef CONFIG_I2C_RESET +static int mpfs_i2c_reset(struct i2c_master_s *dev) +{ + struct mpfs_i2c_priv_s *priv = (struct mpfs_i2c_priv_s *)dev; + + DEBUGASSERT(priv != NULL); + + up_disable_irq(priv->plic_irq); + mpfs_i2c_init(priv); + + priv->tx_size = 0; + priv->tx_idx = 0; + priv->rx_size = 0; + priv->rx_idx = 0; + + /* up_enable_irq() will be called at mpfs_i2c_sendstart() */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a pointer to an unique + * instance of struct i2c_master_s. This function may be called to obtain + * multiple instances of the interface. + * + * Parameters: + * port - Port number of the I2C interface to be initialized. + * + * Returned Value: + * Pointer to valid I2C device structure is returned on success. + * A NULL pointer is returned on failure. + * + ****************************************************************************/ + +struct i2c_master_s *mpfs_i2cbus_initialize(int port) +{ + struct mpfs_i2c_priv_s *priv; + irqstate_t flags; + int ret; + + switch (port) + { +#ifdef CONFIG_MPFS_I2C0 + case 0: + priv = &g_mpfs_i2c0_lo_priv; + break; +#endif /* CONFIG_MPFS_I2C0 */ +#ifdef CONFIG_MPFS_I2C0 + case 1: + priv = &g_mpfs_i2c1_lo_priv; + break; +#endif /* CONFIG_MPFS_I2C0 */ + default: + return NULL; + } + + flags = enter_critical_section(); + + if ((volatile int)priv->refs++ != 0) + { + leave_critical_section(flags); + + i2cinfo("Returning previously initialized I2C bus. " + "Handler: %" PRIxPTR "\n", + (uintptr_t)priv); + + return (struct i2c_master_s *)priv; + } + + ret = irq_attach(priv->plic_irq, mpfs_i2c_irq, priv); + if (ret != OK) + { + leave_critical_section(flags); + return NULL; + } + + mpfs_i2c_sem_init(priv); + mpfs_i2c_init(priv); + + leave_critical_section(flags); + + i2cinfo("I2C bus initialized! Handler: %" PRIxPTR "\n", (uintptr_t)priv); + + return (struct i2c_master_s *)priv; +} + +/**************************************************************************** + * Name: mpfs_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C bus. + * + * Parameters: + * dev - Device structure as returned by + * mpfs_i2cbus_initialize() + * + * Returned Value: + * OK is returned on success. ERROR is returned when internal reference + * count mismatches or dev points to invalid hardware device. + * + ****************************************************************************/ + +int mpfs_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + struct mpfs_i2c_priv_s *priv = (struct mpfs_i2c_priv_s *)dev; + irqstate_t flags; + + DEBUGASSERT(dev); + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(flags); + return OK; + } + + leave_critical_section(flags); + + mpfs_i2c_deinit(priv); + mpfs_i2c_sem_destroy(priv); + + return OK; +} diff --git a/arch/risc-v/src/mpfs/mpfs_i2c.h b/arch/risc-v/src/mpfs/mpfs_i2c.h new file mode 100755 index 00000000000..3761acbb8fe --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_i2c.h @@ -0,0 +1,93 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_i2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_I2C_H +#define __ARCH_RISCV_SRC_MPFS_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a pointer to an unique + * instance of struct i2c_master_s. This function may be called to obtain + * multiple instances of the interface. + * + * Input Parameters: + * port - Port number of the I2C interface to be initialized. + * + * Returned Value: + * Pointer to valid I2C device structure is returned on success. + * A NULL pointer is returned on failure. + * + ****************************************************************************/ + +struct i2c_master_s *mpfs_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: mpfs_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port and power down the device. + * + * Input Parameters: + * dev - Device structure as returned by + * mpfs_i2cbus_initialize() + * + * Returned Value: + * OK is returned on success. ERROR is returned when internal reference + * count mismatches or dev points to invalid hardware device. + * + ****************************************************************************/ + +int mpfs_i2cbus_uninitialize(struct i2c_master_s *dev); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_MPFS_I2C_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_idle.c b/arch/risc-v/src/mpfs/mpfs_idle.c new file mode 100755 index 00000000000..53960bb5276 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_idle.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "riscv_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + asm("WFI"); + +#endif +} diff --git a/arch/risc-v/src/mpfs/mpfs_irq.c b/arch/risc-v/src/mpfs/mpfs_irq.c new file mode 100755 index 00000000000..cde61155b06 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_irq.c @@ -0,0 +1,284 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "riscv_internal.h" +#include "riscv_arch.h" + +#include "mpfs.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint64_t *g_current_regs[1]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Disable Machine interrupts */ + + up_irq_save(); + + /* Disable timer interrupt (in case of hotloading with debugger) */ + + up_disable_irq(MPFS_IRQ_MTIMER); + + /* enable access from supervisor mode */ + + putreg32(0x1, MPFS_PLIC_CTRL); + + /* Disable all global interrupts for current hart */ + + uint64_t hart_id = READ_CSR(mhartid); + + /* hart0 is E51 we can't run on that (need different irq handling) */ + + DEBUGASSERT(hart_id != 0); + + uint32_t *miebase = (uint32_t *)(MPFS_PLIC_H1_MIE0 + + (hart_id - 1) * MPFS_HART_MIE_OFFSET); + + putreg32(0x0, miebase + 0); + putreg32(0x0, miebase + 1); + putreg32(0x0, miebase + 2); + putreg32(0x0, miebase + 3); + putreg32(0x0, miebase + 4); + putreg32(0x0, miebase + 5); + + /* Clear pendings in PLIC (for current hart) */ + + uintptr_t claim_address = MPFS_PLIC_H1_MCLAIM + + ((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET); + uint32_t val = getreg32(claim_address); + putreg32(val, claim_address); + + /* Colorize the interrupt stack for debug purposes */ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); + riscv_stack_color((FAR void *)&g_intstackalloc, intstack_size); +#endif + + /* Set priority for all global interrupts to 1 (lowest) */ + + int id; + + for (id = 1; id <= NR_IRQS; id++) + { + putreg32(1, (uintptr_t)(MPFS_PLIC_PRIORITY + (4 * id))); + } + + /* Set irq threshold to 0 (permits all global interrupts) */ + + uint32_t *threshold_address = (uint32_t *)(MPFS_PLIC_H1_MTHRESHOLD + + ((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET)); + putreg32(0, threshold_address); + + /* currents_regs is non-NULL only while processing an interrupt */ + + CURRENT_REGS = NULL; + + /* Attach the ecall interrupt handler */ + + irq_attach(MPFS_IRQ_ECALLM, riscv_swint, NULL); + +#ifdef CONFIG_BUILD_PROTECTED + irq_attach(MPFS_IRQ_ECALLU, riscv_swint, NULL); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + int extirq = 0; + uint64_t oldstat = 0; + + if (irq == MPFS_IRQ_MSOFT) + { + /* Read mstatus & clear machine software interrupt enable in mie */ + + asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE)); + } + else if (irq == MPFS_IRQ_MTIMER) + { + /* Read mstatus & clear machine timer interrupt enable in mie */ + + asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE)); + } + else if (irq >= MPFS_IRQ_EXT_START) + { + extirq = irq - MPFS_IRQ_EXT_START; + + /* Clear enable bit for the irq */ + + uint64_t hart_id = READ_CSR(mhartid); + uintptr_t miebase = MPFS_PLIC_H1_MIE0 + + ((hart_id - 1) * MPFS_HART_MIE_OFFSET); + + if (0 <= extirq && extirq <= NR_IRQS - MPFS_IRQ_EXT_START) + { + modifyreg32(miebase + (4 * (extirq / 32)), 1 << (extirq % 32), 0); + } + else + { + ASSERT(false); + } + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + int extirq; + uint64_t oldstat; + + if (irq == MPFS_IRQ_MSOFT) + { + /* Read mstatus & set machine software interrupt enable in mie */ + + asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE)); + } + else if (irq == MPFS_IRQ_MTIMER) + { + /* Read mstatus & set machine timer interrupt enable in mie */ + + asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE)); + } + else if (irq >= MPFS_IRQ_EXT_START) + { + extirq = irq - MPFS_IRQ_EXT_START; + + /* Set enable bit for the irq */ + + uint64_t hart_id = READ_CSR(mhartid); + uintptr_t miebase = MPFS_PLIC_H1_MIE0 + + ((hart_id - 1) * MPFS_HART_MIE_OFFSET); + + if (0 <= extirq && extirq <= NR_IRQS - MPFS_IRQ_EXT_START) + { + modifyreg32(miebase + (4 * (extirq / 32)), 0, 1 << (extirq % 32)); + } + else + { + ASSERT(false); + } + } +} + +/**************************************************************************** + * Name: riscv_get_newintctx + * + * Description: + * Return initial mstatus when a task is created. + * + ****************************************************************************/ + +uint32_t riscv_get_newintctx(void) +{ + /* Set machine previous privilege mode to machine mode. Reegardless of + * how NuttX is configured and of what kind of thread is being started. + * That is because all threads, even user-mode threads will start in + * kernel trampoline at nxtask_start() or pthread_start(). + * The thread's privileges will be dropped before transitioning to + * user code. Also set machine previous interrupt enable. + */ + +#ifdef CONFIG_ARCH_FPU + return (MSTATUS_FS_INIT | MSTATUS_MPPM | MSTATUS_MPIE); +#else + return (MSTATUS_MPPM | MSTATUS_MPIE); +#endif +} + +/**************************************************************************** + * Name: riscv_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void riscv_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Return the current interrupt state and enable interrupts + * + ****************************************************************************/ + +irqstate_t up_irq_enable(void) +{ + uint64_t oldstat; + + /* Enable MEIE (machine external interrupt enable) */ + + asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE)); + + /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ + + asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE)); + return oldstat; +} diff --git a/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c b/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c new file mode 100755 index 00000000000..2632aa6589c --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c @@ -0,0 +1,175 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_irq_dispatch.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "riscv_internal.h" + +#include "group/group.h" +#include "hardware/mpfs_memorymap.h" +#include "hardware/mpfs_plic.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern void up_fault(int irq, uint64_t *regs); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * mpfs_dispatch_irq + ****************************************************************************/ + +void *mpfs_dispatch_irq(uint64_t vector, uint64_t *regs) +{ + uint32_t irq = (vector & 0x3f); + uint64_t *mepc = regs; + + board_autoled_on(LED_INIRQ); + + /* Check if fault happened */ + + if (vector < MPFS_IRQ_ECALLU || + vector == MPFS_IRQ_INSTRUCTIONPF || + vector == MPFS_IRQ_LOADPF || + vector == MPFS_IRQ_SROREPF || + vector == MPFS_IRQ_RESERVED) + { + up_fault((int)irq, regs); + } + + if (vector & 0x8000000000000000) + { + irq += MPFS_IRQ_ASYNC; + } + + /* Firstly, check if the irq is machine external interrupt */ + + uint64_t hart_id = READ_CSR(mhartid); + uintptr_t claim_address = MPFS_PLIC_H1_MCLAIM + + ((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET); + + if (irq == MPFS_IRQ_MEXT) + { + uint32_t ext = getreg32(claim_address); + + /* Add the value to nuttx irq which is offset to the mext */ + + irq = MPFS_IRQ_EXT_START + ext; + } + + /* NOTE: In case of ecall, we need to adjust mepc in the context */ + + if (irq == MPFS_IRQ_ECALLM || irq == MPFS_IRQ_ECALLU) + { + *mepc += 4; + } + + /* Acknowledge the interrupt */ + + riscv_ack_irq(irq); + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Current regs non-zero indicates that we are processing an interrupt; + * CURRENT_REGS is also used to manage interrupt level context switches. + * + * Nested interrupts are not supported + */ + + ASSERT(CURRENT_REGS == NULL); + CURRENT_REGS = regs; + + /* MEXT means no interrupt */ + + if (irq != MPFS_IRQ_MEXT && irq != MPFS_IRQ_INVALID) + { + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + } + + if (irq > MPFS_IRQ_EXT_START) + { + /* Then write PLIC_CLAIM to clear pending in PLIC */ + + putreg32(irq - MPFS_IRQ_EXT_START, claim_address); + } + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * CURRENT_REGS will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != CURRENT_REGS) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + riscv_restorefpu((uint64_t *)CURRENT_REGS); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + group_addrenv(NULL); +#endif + } +#endif + +#endif + + /* If a context switch occurred while processing the interrupt then + * CURRENT_REGS may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint64_t *)CURRENT_REGS; + CURRENT_REGS = NULL; + + board_autoled_off(LED_INIRQ); + + return regs; +} diff --git a/arch/risc-v/src/mpfs/mpfs_lowputc.c b/arch/risc-v/src/mpfs/mpfs_lowputc.c new file mode 100755 index 00000000000..a294e720298 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_lowputc.c @@ -0,0 +1,228 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "riscv_internal.h" +#include "riscv_arch.h" + +#include "hardware/mpfs_memorymap.h" +#include "hardware/mpfs_uart.h" +#include "mpfs.h" +#include "mpfs_clockconfig.h" +#include "mpfs_config.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select UART parameters for the selected console */ +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define MPFS_CONSOLE_BASE MPFS_UART0_BASE +# define MPFS_CONSOLE_BAUD CONFIG_UART0_BAUD +# define MPFS_CONSOLE_BITS CONFIG_UART0_BITS +# define MPFS_CONSOLE_PARITY CONFIG_UART0_PARITY +# define MPFS_CONSOLE_2STOP CONFIG_UART0_2STOP +# define HAVE_UART +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define MPFS_CONSOLE_BASE MPFS_UART1_BASE +# define MPFS_CONSOLE_BAUD CONFIG_UART1_BAUD +# define MPFS_CONSOLE_BITS CONFIG_UART1_BITS +# define MPFS_CONSOLE_PARITY CONFIG_UART1_PARITY +# define MPFS_CONSOLE_2STOP CONFIG_UART1_2STOP +# define HAVE_UART +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define MPFS_CONSOLE_BASE MPFS_UART2_BASE +# define MPFS_CONSOLE_BAUD CONFIG_UART2_BAUD +# define MPFS_CONSOLE_BITS CONFIG_UART2_BITS +# define MPFS_CONSOLE_PARITY CONFIG_UART2_PARITY +# define MPFS_CONSOLE_2STOP CONFIG_UART2_2STOP +# define HAVE_UART +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define MPFS_CONSOLE_BASE MPFS_UART3_BASE +# define MPFS_CONSOLE_BAUD CONFIG_UART3_BAUD +# define MPFS_CONSOLE_BITS CONFIG_UART3_BITS +# define MPFS_CONSOLE_PARITY CONFIG_UART3_PARITY +# define MPFS_CONSOLE_2STOP CONFIG_UART3_2STOP +# define HAVE_UART +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define MPFS_CONSOLE_BASE MPFS_UART4_BASE +# define MPFS_CONSOLE_BAUD CONFIG_UART4_BAUD +# define MPFS_CONSOLE_BITS CONFIG_UART4BITS +# define MPFS_CONSOLE_PARITY CONFIG_UART4_PARITY +# define MPFS_CONSOLE_2STOP CONFIG_UART4_2STOP +# define HAVE_UART +# elif defined(HAVE_UART) +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +# endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if !defined(CONFIG_SUPPRESS_UART_CONFIG) + +/**************************************************************************** + * Name: config_baud_divisors + * + * Description: + * Configure the UART baudrate divisors. + * + ****************************************************************************/ + +static void config_baud_divisors(void) +{ + uint32_t baud_value; + uint32_t baud_value_by_64; + uint32_t baud_value_by_128; + uint32_t fractional_baud_value; + uint64_t pclk_freq; + + pclk_freq = MPFS_MSS_APB_AHB_CLK; + + /* Compute baud value based on requested baud rate and PCLK frequency. + * The baud value is computed using the following equation: + * baud_value = PCLK_Frequency / (baud_rate * 16) + */ + + baud_value_by_128 = (uint32_t)((8UL * pclk_freq) / MPFS_CONSOLE_BAUD); + baud_value_by_64 = baud_value_by_128 / 2U; + baud_value = baud_value_by_64 / 64U; + fractional_baud_value = baud_value_by_64 - (baud_value * 64U); + fractional_baud_value += (baud_value_by_128 - (baud_value * 128U)) + - (fractional_baud_value * 2U); + + if (baud_value <= (uint32_t)UINT16_MAX) + { + putreg32(baud_value >> 8, MPFS_CONSOLE_BASE + MPFS_UART_DLH_OFFSET); + putreg32(baud_value & 0xff, MPFS_CONSOLE_BASE + MPFS_UART_DLH_OFFSET); + + if (baud_value > 1) + { + /* Enable Fractional baud rate */ + + uint8_t mm0 = getreg32(MPFS_CONSOLE_BASE + MPFS_UART_MM0_OFFSET); + mm0 |= UART_MM0_EFBR; + putreg32(mm0, MPFS_CONSOLE_BASE + MPFS_UART_MM0_OFFSET); + putreg32(fractional_baud_value, + MPFS_CONSOLE_BASE + MPFS_UART_DFR_OFFSET); + } + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: riscv_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void riscv_lowputc(char ch) +{ +#if defined HAVE_UART && defined HAVE_SERIAL_CONSOLE + /* Wait for the transmitter to be available */ + + while ((getreg32(MPFS_CONSOLE_BASE + MPFS_UART_LSR_OFFSET) + & UART_LSR_THRE) == 0); + + /* Send the character */ + + putreg32((uint32_t)ch, MPFS_CONSOLE_BASE + MPFS_UART_THR_OFFSET); +#endif +} + +/**************************************************************************** + * Name: mpfs_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void mpfs_lowsetup(void) +{ +#if defined(HAVE_UART) + + /* Enable and configure the selected console device */ + + /* REVISIT: bringup UART from reset and set clocking. + * Currently done by HSS bootloader + */ + +#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t lcr = 0; + + lcr = 0; + switch (MPFS_CONSOLE_BITS) + { + case 5: + lcr |= UART_LCR_DLS_5BITS; + break; + + case 6: + lcr |= UART_LCR_DLS_6BITS; + break; + + case 7: + lcr |= UART_LCR_DLS_7BITS; + break; + + case 8: + default: + lcr |= UART_LCR_DLS_8BITS; + break; + } + +#ifdef MPFS_CONSOLE_2STOP + lcr |= UART_LCR_STOP; +#endif + + if (MPFS_CONSOLE_PARITY == 1) + { + lcr |= UART_LCR_PEN; + } + else if (MPFS_CONSOLE_PARITY == 2) + { + lcr |= (UART_LCR_PEN | UART_LCR_EPS); + } + + putreg32(lcr | UART_LCR_DLAB, MPFS_CONSOLE_BASE + MPFS_UART_LCR_OFFSET); + config_baud_divisors(); + putreg32(lcr, MPFS_CONSOLE_BASE + MPFS_UART_LCR_OFFSET); + +#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_UART */ +} diff --git a/arch/risc-v/src/mpfs/mpfs_lowputc.h b/arch/risc-v/src/mpfs/mpfs_lowputc.h new file mode 100755 index 00000000000..710a16c866d --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_lowputc.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_LOWPUTC_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: mpfs_lowsetup + ****************************************************************************/ + +EXTERN void mpfs_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_LOWPUTC_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_memorymap.h b/arch/risc-v/src/mpfs/mpfs_memorymap.h new file mode 100755 index 00000000000..df7e28ee53e --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_memorymap.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef _ARCH_RISCV_SRC_MPFS_MPFS_MEMORYMAP_H +#define _ARCH_RISCV_SRC_MPFS_MPFS_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/mpfs_clint.h" +#include "hardware/mpfs_memorymap.h" +#include "hardware/mpfs_plic.h" +#include "hardware/mpfs_sysreg.h" +#include "hardware/mpfs_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Idle thread stack starts from _default_stack_limit */ + +#ifndef __ASSEMBLY__ +extern uintptr_t *_default_stack_limit; +#define MPFS_IDLESTACK_BASE (uintptr_t)&_default_stack_limit +#else +#define MPFS_IDLESTACK_BASE _default_stack_limit +#endif + +#define MPFS_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~15) + +#define MPFS_IDLESTACK0_TOP (MPFS_IDLESTACK_BASE + MPFS_IDLESTACK_SIZE) + +#define MPFS_IDLESTACK_TOP (MPFS_IDLESTACK0_TOP) + +#endif /* _ARCH_RISCV_SRC_MPFS_MPFS_MEMORYMAP_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_serial.c b/arch/risc-v/src/mpfs/mpfs_serial.c new file mode 100755 index 00000000000..4bee2bc2616 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_serial.c @@ -0,0 +1,1070 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "riscv_arch.h" +#include "riscv_internal.h" + +#include "chip.h" +#include "mpfs.h" +#include "mpfs_config.h" +#include "mpfs_clockconfig.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define SERIAL_CONSOLE 1 +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define SERIAL_CONSOLE 2 +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +# define SERIAL_CONSOLE 3 +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* UART3 is console */ +# define SERIAL_CONSOLE 4 +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4port /* UART4 is console */ +# define SERIAL_CONSOLE 5 +# else +# error "I'm confused... Do we have a serial console or not?" +# endif +#else +# undef CONSOLE_DEV /* No console */ +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# if defined(CONFIG_MPFS_UART0) +# define SERIAL_CONSOLE 1 +# elif defined(CONFIG_MPFS_UART1) +# define SERIAL_CONSOLE 2 +# elif defined(CONFIG_MPFS_UART2) +# define SERIAL_CONSOLE 3 +# elif defined(CONFIG_MPFS_UART3) +# define SERIAL_CONSOLE 4 +# elif defined(CONFIG_MPFS_UART4) +# define SERIAL_CONSOLE 5 +# else +# undef TTYS0_DEV +# undef TTYS1_DEV +# endif +#endif + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of riscv_earlyserialinit(), riscv_serialinit(), and + * up_putc(). + */ + +#ifdef HAVE_UART_DEVICE + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t ier; /* Saved IER value */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int uart_interrupt(int irq, void *context, void *arg); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_MPFS_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif + +#ifdef CONFIG_MPFS_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +#ifdef CONFIG_MPFS_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif + +#ifdef CONFIG_MPFS_UART3 +static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; +#endif + +#ifdef CONFIG_MPFS_UART4 +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +#endif + +#ifdef CONFIG_MPFS_UART0 +static struct up_dev_s g_uart0priv = +{ + .uartbase = MPFS_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = MPFS_IRQ_MMUART0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ +#if SERIAL_CONSOLE == 1 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +#ifdef CONFIG_MPFS_UART1 +static struct up_dev_s g_uart1priv = +{ + .uartbase = MPFS_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq = MPFS_IRQ_MMUART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ +#if SERIAL_CONSOLE == 2 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +#ifdef CONFIG_MPFS_UART2 +static struct up_dev_s g_uart2priv = +{ + .uartbase = MPFS_UART2_BASE, + .baud = CONFIG_UART2_BAUD, + .irq = MPFS_IRQ_MMUART2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ +#if SERIAL_CONSOLE == 3 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +#ifdef CONFIG_MPFS_UART3 +static struct up_dev_s g_uart3priv = +{ + .uartbase = MPFS_UART3_BASE, + .baud = CONFIG_UART3_BAUD, + .irq = MPFS_IRQ_MMUART3, + .parity = CONFIG_UART3_PARITY, + .bits = CONFIG_UART3_BITS, + .stopbits2 = CONFIG_UART3_2STOP, +}; + +static uart_dev_t g_uart3port = +{ +#if SERIAL_CONSOLE == 4 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +#ifdef CONFIG_MPFS_UART4 +static struct up_dev_s g_uart4priv = +{ + .uartbase = MPFS_UART4_BASE, + .baud = CONFIG_UART4_BAUD, + .irq = MPFS_IRQ_MMUART4, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stopbits2 = CONFIG_UART4_2STOP, +}; + +static uart_dev_t g_uart4port = +{ +#if SERIAL_CONSOLE == 5 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, uint32_t offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ier) +{ + if (ier) + { + *ier = priv->ier & UART_IER_ALLIE; + } + + priv->ier &= ~UART_IER_ALLIE; + up_serialout(priv, MPFS_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier) +{ + priv->ier |= ier & UART_IER_ALLIE; + up_serialout(priv, MPFS_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_enablebreaks + ****************************************************************************/ + +static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) +{ + uint32_t lcr = up_serialin(priv, MPFS_UART_LCR_OFFSET); + + if (enable) + { + lcr |= UART_LCR_BC; + } + else + { + lcr &= ~UART_LCR_BC; + } + + up_serialout(priv, MPFS_UART_LCR_OFFSET, lcr); +} + +/**************************************************************************** + * Name: up_config_baud_divisors + * + * Description: + * Configure the UART baudrate divisors. + * + ****************************************************************************/ + +static void up_config_baud_divisors(struct up_dev_s *priv, uint32_t baudrate) +{ + uint32_t baud_value; + uint32_t baud_value_by_64; + uint32_t baud_value_by_128; + uint32_t fractional_baud_value; + uint64_t pclk_freq; + + pclk_freq = MPFS_MSS_APB_AHB_CLK; + + /* Compute baud value based on requested baud rate and PCLK frequency. + * The baud value is computed using the following equation: + * baud_value = PCLK_Frequency / (baud_rate * 16) + */ + + baud_value_by_128 = (uint32_t)((8UL * pclk_freq) / baudrate); + baud_value_by_64 = baud_value_by_128 / 2U; + baud_value = baud_value_by_64 / 64U; + fractional_baud_value = baud_value_by_64 - (baud_value * 64U); + fractional_baud_value += (baud_value_by_128 - (baud_value * 128U)) + - (fractional_baud_value * 2U); + + if (baud_value <= (uint32_t)UINT16_MAX) + { + up_serialout(priv, MPFS_UART_DLH_OFFSET, baud_value >> 8); + up_serialout(priv, MPFS_UART_DLL_OFFSET, baud_value & 0xff); + + if (baud_value > 1) + { + /* Enable Fractional baud rate */ + + uint8_t mm0 = up_serialin(priv, MPFS_UART_MM0_OFFSET); + mm0 |= UART_MM0_EFBR; + up_serialout(priv, MPFS_UART_MM0_OFFSET, mm0); + up_serialout(priv, MPFS_UART_DFR_OFFSET, fractional_baud_value); + } + } +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t lcr; + + /* Clear fifos */ + + up_serialout(priv, MPFS_UART_FCR_OFFSET, + (UART_FCR_RFIFOR | UART_FCR_XFIFOR)); + + /* set filter to minimum value */ + + up_serialout(priv, MPFS_UART_GFR_OFFSET, 0); + + /* set default TX time guard */ + + up_serialout(priv, MPFS_UART_TTG_OFFSET, 0); + + /* Set trigger */ + + up_serialout(priv, MPFS_UART_FCR_OFFSET, + (UART_FCR_FIFOE | UART_FCR_RT_HALF)); + + /* Set up the IER */ + + priv->ier = up_serialin(priv, MPFS_UART_IER_OFFSET); + + /* Set up the LCR */ + + lcr = 0; + + switch (priv->bits) + { + case 5: + lcr |= UART_LCR_DLS_5BITS; + break; + + case 6: + lcr |= UART_LCR_DLS_6BITS; + break; + + case 7: + lcr |= UART_LCR_DLS_7BITS; + break; + + case 8: + default: + lcr |= UART_LCR_DLS_8BITS; + break; + } + + if (priv->stopbits2) + { + lcr |= UART_LCR_STOP; + } + + if (priv->parity == 1) + { + lcr |= UART_LCR_PEN; + } + else if (priv->parity == 2) + { + lcr |= (UART_LCR_PEN | UART_LCR_EPS); + } + + /* Enter DLAB=1 */ + + up_serialout(priv, MPFS_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); + + /* Set the BAUD divisor */ + + up_config_baud_divisors(priv, priv->baud); + + /* Clear DLAB */ + + up_serialout(priv, MPFS_UART_LCR_OFFSET, lcr); + + /* Configure the FIFOs */ + + up_serialout(priv, MPFS_UART_FCR_OFFSET, + (UART_FCR_RT_HALF | UART_FCR_XFIFOR | UART_FCR_RFIFOR | + UART_FCR_FIFOE)); + + /* Enable Auto-Flow Control in the Modem Control Register */ + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) +# warning Missing logic +#endif + +#endif + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, uart_interrupt, dev); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); + + /* Detach from the interrupt */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int uart_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct up_dev_s *priv; + uint32_t status; + int passes; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct up_dev_s *)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + for (passes = 0; passes < 256; passes++) + { + /* Get the current UART status */ + + status = up_serialin(priv, MPFS_UART_IIR_OFFSET); + + /* Handle the interrupt by its interrupt ID field */ + + switch (status & UART_IIR_IID_MASK) + { + /* Handle incoming, receive bytes (with or without timeout) */ + + case UART_IIR_IID_RECV: + case UART_IIR_IID_TIMEOUT: + { + uart_recvchars(dev); + break; + } + + /* Handle outgoing, transmit bytes */ + + case UART_IIR_IID_TXEMPTY: + { + uart_xmitchars(dev); + break; + } + + /* Just clear modem status interrupts */ + + case UART_IIR_IID_MODEM: + { + /* Read the modem status register (MSR) to clear */ + + status = up_serialin(priv, MPFS_UART_MSR_OFFSET); + _info("MSR: %02" PRIx32 "\n", status); + break; + } + + /* Just clear any line status interrupts */ + + case UART_IIR_IID_LINESTATUS: + { + /* Read the line status register (LSR) to clear */ + + status = up_serialin(priv, MPFS_UART_LSR_OFFSET); + _info("LSR: %02" PRIx32 "\n", status); + break; + } + + /* No further interrupts pending... return now */ + + case UART_IIR_IID_NONE: + { + return OK; + } + + /* Otherwise we have received an interrupt + * that we cannot handle + */ + + default: + { + _err("ERROR: Unexpected IIR: %02" PRIx32 "\n", status); + break; + } + } + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t rbr; + + *status = up_serialin(priv, MPFS_UART_LSR_OFFSET); + rbr = up_serialin(priv, MPFS_UART_RBR_OFFSET); + return rbr; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ier |= UART_IER_ERBFI; +#endif + } + else + { + priv->ier &= ~UART_IER_ERBFI; + } + + up_serialout(priv, MPFS_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, MPFS_UART_LSR_OFFSET) & UART_LSR_DR) != 0); +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + while ((up_serialin(priv, MPFS_UART_LSR_OFFSET) + & UART_LSR_THRE) == 0); + + up_serialout(priv, MPFS_UART_THR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ier |= UART_IER_ETBEI; + up_serialout(priv, MPFS_UART_IER_OFFSET, priv->ier); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + priv->ier &= ~UART_IER_ETBEI; + up_serialout(priv, MPFS_UART_IER_OFFSET, priv->ier); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit data register is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, MPFS_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, MPFS_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT + +/**************************************************************************** + * Name: riscv_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before riscv_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock iniialization + * performed in up_clkinitialize(). + * + ****************************************************************************/ + +void riscv_earlyserialinit(void) +{ + /* Disable interrupts from all UARTS. The console is enabled in + * mpfs_consoleinit(). + */ + +#ifdef CONFIG_MPFS_UART0 + up_disableuartint(g_uart0port.priv, NULL); +#endif + +#ifdef CONFIG_MPFS_UART1 + up_disableuartint(g_uart1port.priv, NULL); +#endif + +#ifdef CONFIG_MPFS_UART2 + up_disableuartint(g_uart2port.priv, NULL); +#endif + +#ifdef CONFIG_MPFS_UART3 + up_disableuartint(g_uart3port.priv, NULL); +#endif + +#ifdef CONFIG_MPFS_UART4 + up_disableuartint(g_uart4port.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_SERIAL_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: riscv_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that riscv_earlyserialinit was called previously. + * + ****************************************************************************/ + +void riscv_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_SERIAL_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs NOTE: we don't reorganize the numbering */ + +#ifdef CONFIG_MPFS_UART0 + uart_register("/dev/ttyS0", &g_uart0port); +#endif +#ifdef CONFIG_MPFS_UART1 + uart_register("/dev/ttyS1", &g_uart1port); +#endif +#ifdef CONFIG_MPFS_UART2 + uart_register("/dev/ttyS2", &g_uart2port); +#endif +#ifdef CONFIG_MPFS_UART3 + uart_register("/dev/ttyS3", &g_uart3port); +#endif +#ifdef CONFIG_MPFS_UART4 + uart_register("/dev/ttyS4", &g_uart4port); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; + uint32_t ier; + up_disableuartint(priv, &ier); +#endif + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + riscv_lowputc('\r'); + } + + riscv_lowputc(ch); +#ifdef HAVE_SERIAL_CONSOLE + up_restoreuartint(priv, ier); +#endif + return ch; +} + +/**************************************************************************** + * Name: riscv_earlyserialinit, riscv_serialinit, and up_putc + * + * Description: + * stubs that may be needed. These stubs would be used if all UARTs are + * disabled. In that case, the logic in common/up_initialize() is not + * smart enough to know that there are not UARTs and will still expect + * these interfaces to be provided. + * + ****************************************************************************/ + +#else /* HAVE_UART_DEVICE */ +void riscv_earlyserialinit(void) +{ +} + +void riscv_serialinit(void) +{ +} + +int up_putc(int ch) +{ + return ch; +} + +#endif /* HAVE_UART_DEVICE */ +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + riscv_lowputc('\r'); + } + + riscv_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/risc-v/src/mpfs/mpfs_spi.c b/arch/risc-v/src/mpfs/mpfs_spi.c new file mode 100644 index 00000000000..ffcb476f416 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_spi.c @@ -0,0 +1,1519 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "mpfs_spi.h" +#include "hardware/mpfs_spi.h" +#include "hardware/mpfs_sysreg.h" +#include "riscv_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MPFS_SPI_FREQ_DEFAULT 4000000 + +#define MPFS_SYSREG_SOFT_RESET_CR (MPFS_SYSREG_BASE + \ + MPFS_SYSREG_SOFT_RESET_CR_OFFSET) +#define MPFS_SYSREG_SUBBLK_CLOCK_CR (MPFS_SYSREG_BASE + \ + MPFS_SYSREG_SUBBLK_CLOCK_CR_OFFSET) + +#define MPFS_SPI_CONTROL_OFFSET 0x00 +#define MPFS_SPI_FRAMESIZE_OFFSET 0x04 +#define MPFS_SPI_STATUS_OFFSET 0x08 +#define MPFS_SPI_INT_CLEAR_OFFSET 0x0C +#define MPFS_SPI_RX_DATA_OFFSET 0x10 +#define MPFS_SPI_TX_DATA_OFFSET 0x14 +#define MPFS_SPI_CLK_GEN_OFFSET 0x18 +#define MPFS_SPI_SLAVE_SELECT_OFFSET 0x1C +#define MPFS_SPI_INTMASK_OFFSET 0x20 +#define MPFS_SPI_INTRAW_OFFSET 0x24 +#define MPFS_SPI_CONTROL2_OFFSET 0x28 +#define MPFS_SPI_COMMAND_OFFSET 0x2C +#define MPFS_SPI_PKTSIZE_OFFSET 0x30 +#define MPFS_SPI_CMD_SIZE_OFFSET 0x34 +#define MPFS_SPI_HWSTATUS_OFFSET 0x38 +#define MPFS_SPI_STATS_OFFSET 0x3C +#define MPFS_SPI_CTRL0_OFFSET 0x40 +#define MPFS_SPI_CTRL1_OFFSET 0x44 +#define MPFS_SPI_CTRL2_OFFSET 0x48 +#define MPFS_SPI_CTRL3_OFFSET 0x4C +#define MPFS_SPI_FRAMESUP_OFFSET 0x50 + +#define MPFS_SPI_CONTROL (priv->hw_base + MPFS_SPI_CONTROL_OFFSET) +#define MPFS_SPI_FSIZE (priv->hw_base + MPFS_SPI_FRAMESIZE_OFFSET) +#define MPFS_SPI_STATUS (priv->hw_base + MPFS_SPI_STATUS_OFFSET) +#define MPFS_SPI_RX_DATA (priv->hw_base + MPFS_SPI_RX_DATA_OFFSET) +#define MPFS_SPI_TX_DATA (priv->hw_base + MPFS_SPI_TX_DATA_OFFSET) +#define MPFS_SPI_INT_CLEAR (priv->hw_base + MPFS_SPI_INT_CLEAR_OFFSET) +#define MPFS_SPI_CLK_GEN (priv->hw_base + MPFS_SPI_CLK_GEN_OFFSET) +#define MPFS_SPI_SSELECT (priv->hw_base + MPFS_SPI_SLAVE_SELECT_OFFSET) +#define MPFS_SPI_INTMASK (priv->hw_base + MPFS_SPI_INTMASK_OFFSET) +#define MPFS_SPI_CONTROL2 (priv->hw_base + MPFS_SPI_CONTROL2_OFFSET) +#define MPFS_SPI_COMMAND (priv->hw_base + MPFS_SPI_COMMAND_OFFSET) +#define MPFS_SPI_PKTSIZE (priv->hw_base + MPFS_SPI_PKTSIZE_OFFSET) +#define MPFS_SPI_CMD_SIZE (priv->hw_base + MPFS_SPI_CMD_SIZE_OFFSET) +#define MPFS_SPI_FRAMESUP (priv->hw_base + MPFS_SPI_FRAMESUP_OFFSET) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* SPI Device hardware configuration */ + +struct mpfs_spi_config_s +{ + uint32_t clk_freq; /* SPI clock frequency */ + enum spi_mode_e mode; /* SPI default mode */ + bool use_irq; /* Use DMA */ +}; + +struct mpfs_spi_priv_s +{ + struct spi_dev_s spi_dev; + const struct mpfs_spi_config_s *config; /* Port configuration */ + + uintptr_t hw_base; /* Bus base address */ + uint16_t plic_irq; /* Platform IRQ */ + + int refs; /* Reference count */ + int enabled; /* Enable flag */ + const int id; /* SPI0 or SPI1 id */ + uint32_t devid; /* SPI CS device 0..7 */ + + sem_t sem_excl; /* Bus usage semaphore */ + sem_t sem_isr; /* Interrupt wait semaphore */ + + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint32_t txwords; /* Words for TX */ + const void *txbuf; /* TX buffer */ + uint32_t tx_pos; /* TX position */ + + uint32_t rxwords; /* Words for RX */ + void *rxbuf; /* RX buffer */ + uint32_t rx_pos; /* RX position */ + + uint32_t fifosize; /* Fifo size */ + uint32_t fifolevel; /* Fifo IRQ level */ + int error; /* Detected error */ + + enum spi_mode_e mode; /* Actual SPI hardware mode */ + + uint8_t nbits; /* Bits per transaction */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int mpfs_spi_lock(struct spi_dev_s *dev, bool lock); + +static void mpfs_spi_select(struct spi_dev_s *dev, uint32_t devid, + bool selected); + +static uint32_t mpfs_spi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency); +static void mpfs_spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode); +static void mpfs_spi_setbits(struct spi_dev_s *dev, int nbits); +#ifdef CONFIG_SPI_HWFEATURES +static int mpfs_spi_hwfeatures(struct spi_dev_s *dev, + spi_hwfeatures_t features); +#endif +static uint8_t mpfs_spi_status(struct spi_dev_s *dev, uint32_t devid); +#ifdef CONFIG_SPI_CMDDATA +static int mpfs_spi_cmddata(struct spi_dev_s *dev, + uint32_t devid, bool cmd); +#endif +static uint32_t mpfs_spi_send(struct spi_dev_s *dev, uint32_t wd); +static void mpfs_spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void mpfs_spi_sndblock(struct spi_dev_s *dev, const void *txbuffer, + size_t nwords); +static void mpfs_spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, + size_t nwords); +#endif +#ifdef CONFIG_SPI_TRIGGER +static int mpfs_spi_trigger(struct spi_dev_s *dev); +#endif +static void mpfs_spi_enable(struct mpfs_spi_priv_s *priv, uint8_t enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct mpfs_spi_config_s mpfs_spi_config = +{ + .clk_freq = MPFS_SPI_FREQ_DEFAULT, + .mode = SPIDEV_MODE0, + .use_irq = true, +}; + +static const struct spi_ops_s mpfs_spi_ops = +{ + .lock = mpfs_spi_lock, + .select = mpfs_spi_select, + .setfrequency = mpfs_spi_setfrequency, +#ifdef CONFIG_SPI_CS_DELAY_CONTROL + .setdelay = mpfs_spi_setdelay, +#endif + .setmode = mpfs_spi_setmode, + .setbits = mpfs_spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = mpfs_spi_hwfeatures, +#endif + .status = mpfs_spi_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = mpfs_spi_cmddata, +#endif + .send = mpfs_spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = mpfs_spi_exchange, +#else + .sndblock = mpfs_spi_sndblock, + .recvblock = mpfs_spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = mpfs_spi_trigger, +#endif + .registercallback = NULL, +}; + +#ifdef CONFIG_MPFS_SPI0 +static struct mpfs_spi_priv_s g_mpfs_spi0_priv = +{ + .spi_dev = + { + .ops = &mpfs_spi_ops + }, + .config = &mpfs_spi_config, + .hw_base = MPFS_SPI0_LO_BASE, + .plic_irq = MPFS_IRQ_SPI0, + .id = 0, + .devid = 0 +}; +#endif /* CONFIG_MPFS_SPI0 */ +#ifdef CONFIG_MPFS_SPI1 +static struct mpfs_spi_priv_s g_mpfs_spi1_priv = +{ + .spi_dev = + { + .ops = &mpfs_spi_ops + }, + .config = &mpfs_spi_config, + .hw_base = MPFS_SPI1_LO_BASE, + .plic_irq = MPFS_IRQ_SPI1, + .id = 1, + .devid = 1 +}; + +#endif /* CONFIG_MPFS_SPI1 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_spi_rxoverflow_recover + * + * Description: + * Recover from RX overflow condition. This resets the whole SPI device. + * + * Input Parameters: + * priv - Private SPI device structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_rxoverflow_recover(struct mpfs_spi_priv_s *priv) +{ + uint32_t control_reg; + uint32_t clk_gen; + uint32_t frame_size; + uint32_t control2; + uint32_t packet_size; + uint32_t cmd_size; + uint32_t slave_select; + + /* Read current SPI hardware block configuration */ + + control_reg = getreg32(MPFS_SPI_CONTROL); + clk_gen = getreg32(MPFS_SPI_CLK_GEN); + frame_size = getreg32(MPFS_SPI_FRAMESIZE); + control2 = getreg32(MPFS_SPI_CONTROL2); + packet_size = getreg32(MPFS_SPI_PKTSIZE); + cmd_size = getreg32(MPFS_SPI_CMD_SIZE); + slave_select = getreg32(MPFS_SPI_SSELECT); + + /* Reset the SPI hardware block */ + + modifyreg32(MPFS_SPI_CONTROL, 0, MPFS_SPI_RESET); + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_RESET, 0); + + mpfs_spi_enable(priv, 0); + + /* Restore SPI hardware block configuration */ + + putreg32(control_reg, MPFS_SPI_CONTROL); + putreg32(clk_gen, MPFS_SPI_CLK_GEN); + putreg32(frame_size, MPFS_SPI_FRAMESIZE); + + mpfs_spi_enable(priv, 1); + + putreg32(control2, MPFS_SPI_CONTROL2); + putreg32(packet_size, MPFS_SPI_PKTSIZE); + putreg32(cmd_size, MPFS_SPI_CMD_SIZE); + putreg32(slave_select, MPFS_SPI_SSELECT); +} + +/**************************************************************************** + * Name: mpfs_spi_lock + * + * Description: + * Lock or unlock the SPI device + * + * Input Parameters: + * priv - Private SPI device structure + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * The result of lock or unlock the SPI device + * + ****************************************************************************/ + +static int mpfs_spi_lock(struct spi_dev_s *dev, bool lock) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + int ret; + + if (lock) + { + ret = nxsem_wait_uninterruptible(&priv->sem_excl); + } + else + { + ret = nxsem_post(&priv->sem_excl); + } + + return ret; +} + +/**************************************************************************** + * Name: mpfs_spi_select + * + * Description: + * Enable/disable the SPI chip select. + * + * Input Parameters: + * priv - Private SPI device structure + * devid - Identifies the device to select + * selected - true: slave selected, false: slave de-selected + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + + priv->devid = devid & 0x1f; + + if (selected) + { + modifyreg32(MPFS_SPI_SSELECT, 0, 1 << (priv->devid)); + } + else + { + modifyreg32(MPFS_SPI_SSELECT, 1 << (priv->devid), 0); + } + + spiinfo("devid: %u, CS: %s\n", devid, selected ? "select" : "free"); +} + +/**************************************************************************** + * Name: mpfs_spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the current actual frequency selected + * + ****************************************************************************/ + +static uint32_t mpfs_spi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + uint32_t divider; + + DEBUGASSERT(frequency > 0); + + if (priv->enabled) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_ENABLE, 0); + } + + priv->frequency = frequency; + divider = (MPFS_MSS_APB_AHB_CLK / frequency) >> 1; + priv->actual = (uint32_t)frequency * divider; + + DEBUGASSERT(divider >= 2u && divider <= 512u); + + putreg32(divider, MPFS_SPI_CLK_GEN); + + spiinfo("frequency=%u, actual=%u\n", priv->frequency, priv->actual); + + if (priv->enabled) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_ENABLE, MPFS_SPI_ENABLE); + } + + return priv->actual; +} + +/**************************************************************************** + * Name: mpfs_spi_setmode + * + * Description: + * Set the SPI mode. + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void mpfs_spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + + spiinfo("mode=%d\n", mode); + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_SPO | MPFS_SPI_SPH, 0); + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_SPO, MPFS_SPI_SPH); + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_SPH, MPFS_SPI_SPO); + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + modifyreg32(MPFS_SPI_CONTROL, 0, MPFS_SPI_SPO | MPFS_SPI_SPH); + break; + + default: + return; + } + + priv->mode = mode; + + /* SPS bit ensures the slave select remains asserted between frames, + * applicable to SPIDEV_MODEx:s. + */ + + modifyreg32(MPFS_SPI_CONTROL, 0, MPFS_SPI_SPS); +} + +/**************************************************************************** + * Name: mpfs_spi_setbits + * + * Description: + * Set the number of bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits in an SPI word. + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void mpfs_spi_setbits(struct spi_dev_s *dev, int nbits) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + + spiinfo("nbits=%d\n", nbits); + + /* SPI must be disabled for FS change to apply */ + + if (priv->enabled) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_ENABLE, 0); + } + + modifyreg32(MPFS_SPI_FSIZE, MPFS_SPI_FRAMESIZE, nbits); + + if (priv->enabled) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_ENABLE, MPFS_SPI_ENABLE); + } + + priv->nbits = nbits; +} + +/**************************************************************************** + * Name: mpfs_spi_status + * + * Description: + * Get SPI/MMC status. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to report status on + * + * Returned Value: + * Returns a bitset of status values (see SPI_STATUS_* defines) + * + ****************************************************************************/ + +static uint8_t mpfs_spi_status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + + return status; +} + +/**************************************************************************** + * Name: mpfs_spi_cmddata + * + * Description: + * Some devices require an additional out-of-band bit to specify if the + * next word sent to the device is a command or data. This feature is not + * implemented. + * + * Input Parameters: + * dev - Device-specific state data + * cmd - TRUE: The following word is a command; FALSE: the following words + * are data. + * + * Returned Value: + * OK unless an error occurs. Then a negated errno value is returned + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +static int mpfs_spi_cmddata(struct spi_dev_s *dev, + uint32_t devid, bool cmd) +{ + spierr("SPI cmddata not supported\n"); + DEBUGPANIC(); + + return -1; +} +#endif + +/**************************************************************************** + * Name: mpfs_spi_hwfeatures + * + * Description: + * Set hardware-specific feature flags. + * + * Input Parameters: + * dev - Device-specific state data + * features - H/W feature flags + * + * Returned Value: + * Zero (OK) if the selected H/W features are enabled; A negated errno + * value if any H/W feature is not supportable. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_HWFEATURES +static int mpfs_spi_hwfeatures(struct spi_dev_s *dev, + spi_hwfeatures_t features) +{ + /* Other H/W features are not supported */ + + spierr("SPI hardware specific feature not supported\n"); + DEBUGPANIC(); + + return -1; +} +#endif + +/**************************************************************************** + * Name: mpfs_spi_sem_waitdone + * + * Description: + * Wait for a transfer to complete. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int mpfs_spi_sem_waitdone(struct mpfs_spi_priv_s *priv) +{ + struct timespec abstime; + int ret; + + clock_gettime(CLOCK_REALTIME, &abstime); + + abstime.tv_sec += 10; + abstime.tv_nsec += 0; + + ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime); + + return ret; +} + +/**************************************************************************** + * Name: mpfs_spi_load_tx_fifo + * + * Description: + * Fill up the TX fifo with nwords (in 8 or 16-bit). + * + * Input Parameters: + * priv - SPI private state data + * txbuffer - A pointer to the buffer of data to be sent + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_load_tx_fifo(struct mpfs_spi_priv_s *priv, + const void *txbuffer, + uint32_t nwords) +{ + uint32_t tx_fifo_full; + uint16_t *data16; + uint8_t *data8; + int i; + + DEBUGASSERT(nwords > 0); + + data16 = (uint16_t *)txbuffer; + data8 = (uint8_t *)txbuffer; + + for (i = 0; i < nwords; i++) + { + if (txbuffer) + { + if (priv->nbits == 8) + { + putreg32((uint32_t)data8[priv->tx_pos], MPFS_SPI_TX_DATA); + } + else + { + putreg32((uint32_t)data16[priv->tx_pos], MPFS_SPI_TX_DATA); + } + } + else + { + putreg32(0, MPFS_SPI_TX_DATA); + } + + priv->tx_pos++; + tx_fifo_full = getreg32(MPFS_SPI_STATUS) & MPFS_SPI_TXFIFOFUL; + + DEBUGASSERT(tx_fifo_full == 0); + } +} + +/**************************************************************************** + * Name: mpfs_spi_unload_rx_fifo + * + * Description: + * Unload the RX fifo with nwords -number of elements. That is, read the + * specified number of elements from the RX fifo. + * + * Input Parameters: + * priv - SPI private state data + * txbuffer - A pointer to the buffer of data for receiving data + * nwords - the length of data that to be exchanged in units of words. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_unload_rx_fifo(struct mpfs_spi_priv_s *priv, + void *rxbuffer, + uint32_t nwords) +{ + uint32_t rx_fifo_empty; + uint16_t *data16; + uint8_t *data8; + int i; + + DEBUGASSERT(nwords > 0); + + data16 = (uint16_t *)rxbuffer; + data8 = (uint8_t *)rxbuffer; + + for (i = 0; i < nwords; i++) + { + rx_fifo_empty = getreg32(MPFS_SPI_STATUS) & MPFS_SPI_RXFIFOEMP; + DEBUGASSERT(rx_fifo_empty == 0); + + if (rxbuffer) + { + if (priv->nbits == 8) + { + data8[priv->rx_pos] = getreg32(MPFS_SPI_RX_DATA); + } + else + { + data16[priv->rx_pos] = getreg32(MPFS_SPI_RX_DATA); + } + } + else + { + getreg32(MPFS_SPI_RX_DATA); + } + + priv->rx_pos++; + + DEBUGASSERT(priv->rx_pos <= priv->rxwords); + } +} + +/**************************************************************************** + * Name: mpfs_spi_irq_exchange + * + * Description: + * Exchange a block of data from SPI by DMA. + * + * Input Parameters: + * priv - SPI private state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_irq_exchange(struct mpfs_spi_priv_s *priv, + const void *txbuffer, + void *rxbuffer, uint32_t nwords) +{ + uint32_t status; + + DEBUGASSERT(nwords >= 1u && nwords < 0xffffu); + + /* SPI fifo clear */ + + modifyreg32(MPFS_SPI_COMMAND, 0, MPFS_SPI_TXFIFORST | MPFS_SPI_RXFIFORST); + + /* Recover from RX overflow condition if present */ + + status = getreg32(MPFS_SPI_STATUS); + if (status & MPFS_SPI_RXOVERFLOW) + { + mpfs_spi_rxoverflow_recover(priv); + } + + DEBUGASSERT(priv->nbits == 8 || priv->nbits == 16); + + priv->fifosize = (256 / priv->nbits); + priv->fifolevel = priv->fifosize / 2; + + priv->txwords = nwords; + priv->txbuf = txbuffer; + priv->tx_pos = 0; + + priv->rxwords = nwords; + priv->rxbuf = rxbuffer; + priv->rx_pos = 0; + priv->error = 0; + + putreg32(0, MPFS_SPI_FRAMESUP); + + if (nwords > priv->fifosize) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_FRAMECNT, + MPFS_SPI_FRAMECNT & (priv->fifolevel << 8)); + mpfs_spi_load_tx_fifo(priv, txbuffer, priv->fifolevel); + } + else + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_FRAMECNT, + MPFS_SPI_FRAMECNT & (nwords << 8)); + mpfs_spi_load_tx_fifo(priv, txbuffer, nwords); + } + + /* Enable TX, RX, underrun and overflow interrupts */ + + putreg32(MPFS_SPI_INT_CLEAR, MPFS_SPI_TXCHUNDRUN | + MPFS_SPI_RXCHOVRFLW | + MPFS_SPI_RXRDONECLR | + MPFS_SPI_TXDONECLR); + + modifyreg32(MPFS_SPI_CONTROL, 0, MPFS_SPI_INTTXTURUN | + MPFS_SPI_INTRXOVRFLOW | + MPFS_SPI_INTRXDATA | + MPFS_SPI_INTTXDATA); + + if (mpfs_spi_sem_waitdone(priv) < 0) + { + spiinfo("Message timed out\n"); + priv->error = -ETIMEDOUT; + } + + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_INTTXTURUN | + MPFS_SPI_INTRXOVRFLOW | + MPFS_SPI_INTRXDATA | + MPFS_SPI_INTTXDATA, + 0); + + putreg32(MPFS_SPI_INT_CLEAR, MPFS_SPI_TXCHUNDRUN | + MPFS_SPI_RXCHOVRFLW | + MPFS_SPI_RXRDONECLR | + MPFS_SPI_TXDONECLR); +} + +/**************************************************************************** + * Name: mpfs_spi_poll_send + * + * Description: + * Exchange one word on SPI by polling mode. + * + * Input Parameters: + * priv - SPI private state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * Received value + * + ****************************************************************************/ + +static uint32_t mpfs_spi_poll_send(struct mpfs_spi_priv_s *priv, + uint32_t wd) +{ + uint32_t max_tx_cnt = 10000; + uint32_t max_rx_cnt = 10000; + uint32_t tx_done = 0; + uint32_t rx_ready = 0; + uint32_t rx_fifo_empty; + + uint32_t val = 0; + + /* Write data to tx fifo */ + + putreg32(wd, MPFS_SPI_TX_DATA); + + /* Wait until TX data is sent */ + + while (!tx_done && max_tx_cnt) + { + tx_done = getreg32(MPFS_SPI_STATUS) & MPFS_SPI_TXDATSENT; + max_tx_cnt--; + } + + /* Wait for rx data */ + + while (!rx_ready && max_rx_cnt) + { + rx_ready = getreg32(MPFS_SPI_STATUS) & MPFS_SPI_RXDATRCED; + max_rx_cnt--; + } + + val = getreg32(MPFS_SPI_RX_DATA); + + /* Flush the RX fifo just in case */ + + rx_fifo_empty = getreg32(MPFS_SPI_STATUS) & MPFS_SPI_RXFIFOEMP; + while (!rx_fifo_empty) + { + getreg32(MPFS_SPI_RX_DATA); + rx_fifo_empty = getreg32(MPFS_SPI_STATUS) & MPFS_SPI_RXFIFOEMP; + } + + spiinfo("send=%x and recv=%x\n", wd, val); + + return val; +} + +/**************************************************************************** + * Name: mpfs_spi_send + * + * Description: + * Exchange one word on SPI. + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * Received value + * + ****************************************************************************/ + +static uint32_t mpfs_spi_send(struct spi_dev_s *dev, uint32_t wd) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + uint32_t rd; + + rd = mpfs_spi_poll_send(priv, wd); + + return rd; +} + +/**************************************************************************** + * Name: mpfs_spi_poll_exchange + * + * Description: + * Exchange a block of data from SPI. + * + * Input Parameters: + * priv - SPI private state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_poll_exchange(struct mpfs_spi_priv_s *priv, + const void *txbuffer, + void *rxbuffer, size_t nwords) +{ + uint32_t w_wd = 0xffff; + uint32_t r_wd; + uint32_t status; + int i; + + /* SPI fifo clear */ + + modifyreg32(MPFS_SPI_COMMAND, 0, MPFS_SPI_TXFIFORST | MPFS_SPI_RXFIFORST); + + /* Recover from RX overflow condition if present */ + + status = getreg32(MPFS_SPI_STATUS); + if (status & MPFS_SPI_RXOVERFLOW) + { + mpfs_spi_rxoverflow_recover(priv); + } + + putreg32(0, MPFS_SPI_FRAMESUP); + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_FRAMECNT, + MPFS_SPI_FRAMECNT & (nwords << 8)); + + for (i = 0; i < nwords; i++) + { + if (txbuffer) + { + if (priv->nbits == 8) + { + w_wd = ((uint8_t *)txbuffer)[i]; + } + else + { + w_wd = ((uint16_t *)txbuffer)[i]; + } + } + + r_wd = mpfs_spi_poll_send(priv, w_wd); + + if (rxbuffer) + { + if (priv->nbits == 8) + { + ((uint8_t *)rxbuffer)[i] = r_wd; + } + else + { + ((uint16_t *)rxbuffer)[i] = r_wd; + } + } + } +} + +/**************************************************************************** + * Name: mpfs_spi_exchange + * + * Description: + * Exchange a block of data from SPI. + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_exchange(struct spi_dev_s *dev, + const void *txbuffer, void *rxbuffer, + size_t nwords) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + + if (priv->config->use_irq) + { + mpfs_spi_irq_exchange(priv, txbuffer, rxbuffer, nwords); + } + else + { + mpfs_spi_poll_exchange(priv, txbuffer, rxbuffer, nwords); + } +} + +#ifndef CONFIG_SPI_EXCHANGE + +/**************************************************************************** + * Name: mpfs_spi_sndblock + * + * Description: + * Send a block of data on SPI. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_sndblock(struct spi_dev_s *dev, + const void *txbuffer, size_t nwords) +{ + spiinfo("txbuffer=%p nwords=%lu\n", txbuffer, nwords); + + mpfs_spi_exchange(dev, txbuffer, NULL, nwords); +} + +/**************************************************************************** + * Name: mpfs_spi_recvblock + * + * Description: + * Receive a block of data from SPI. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits- + * per-word selected for the SPI interface. If nbits <= 8, the + * data is packed into uint8_t's; if nbits >8, the data is packed + * into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_recvblock(struct spi_dev_s *dev, + void *rxbuffer, size_t nwords) +{ + spiinfo("rxbuffer=%p nwords=%lu\n", rxbuffer, nwords); + + mpfs_spi_exchange(dev, NULL, rxbuffer, nwords); +} +#endif + +/**************************************************************************** + * Name: mpfs_spi_trigger + * + * Description: + * Trigger a previously configured DMA transfer. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * OK - Trigger was fired + * -ENOSYS - Trigger not fired due to lack of DMA or low level support + * -EIO - Trigger not fired because not previously primed + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_TRIGGER +static int mpfs_spi_trigger(struct spi_dev_s *dev) +{ + spierr("SPI trigger not supported\n"); + DEBUGPANIC(); + + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: mpfs_spi_set_master_mode + * + * Description: + * set spi mode + * + * Input Parameters: + * master - master or slave + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_set_master_mode(struct mpfs_spi_priv_s *priv, + uint8_t master) +{ + if (priv->enabled) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_ENABLE, 0); + } + + if (master) + { + modifyreg32(MPFS_SPI_CONTROL, 0, MPFS_SPI_MODE); + } + else + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_MODE, 0); + } + + modifyreg32(MPFS_SPI_CONTROL, 0, MPFS_SPI_BIGFIFO | MPFS_SPI_CLKMODE); + + if (priv->enabled) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_ENABLE, MPFS_SPI_ENABLE); + } +} + +/**************************************************************************** + * Name: mpfs_spi_irq + * + * Description: + * This is the common SPI interrupt handler. It will be invoked when an + * interrupt is received on the device. + * + * Parameters: + * cpuint - CPU interrupt index + * context - Context data from the ISR + * arg - Opaque pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int mpfs_spi_irq(int cpuint, void *context, void *arg) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)arg; + uint32_t remaining; + uint32_t status; + + status = getreg32(MPFS_SPI_INTMASK); + + spiinfo("irq status=%x\n", status); + + if (status & MPFS_SPI_RXRDYMSKINT) + { + remaining = priv->rxwords - priv->rx_pos; + + if (remaining <= priv->fifosize) + { + mpfs_spi_unload_rx_fifo(priv, priv->rxbuf, remaining); + } + else + { + mpfs_spi_unload_rx_fifo(priv, priv->rxbuf, priv->fifolevel); + } + + putreg32(MPFS_SPI_RXRDONECLR, MPFS_SPI_INT_CLEAR); + } + + if (status & MPFS_SPI_TXDONEMSKINT) + { + remaining = priv->txwords - priv->tx_pos; + + if (remaining == 0) + { + /* Done sending - finish up */ + + nxsem_post(&priv->sem_isr); + } + else + { + if (remaining <= priv->fifosize) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_FRAMECNT, + MPFS_SPI_FRAMECNT & (remaining << 8)); + mpfs_spi_load_tx_fifo(priv, priv->txbuf, remaining); + } + else + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_FRAMECNT, + MPFS_SPI_FRAMECNT & (priv->fifolevel << 8)); + mpfs_spi_load_tx_fifo(priv, priv->txbuf, priv->fifolevel); + } + } + + putreg32(MPFS_SPI_TXDONECLR, MPFS_SPI_INT_CLEAR); + } + + if (status & MPFS_SPI_RXCHOVRFMSKINT) + { + /* Handle receive overflow */ + + modifyreg32(MPFS_SPI_COMMAND, 0, MPFS_SPI_RXFIFORST); + mpfs_spi_rxoverflow_recover(priv); + + putreg32(MPFS_SPI_RXCHOVRFLW, MPFS_SPI_INT_CLEAR); + } + + if (status & MPFS_SPI_TXCHUNDDMSKINT) + { + /* Handle transmit underrun */ + + modifyreg32(MPFS_SPI_COMMAND, 0, MPFS_SPI_TXFIFORST); + putreg32(MPFS_SPI_TXCHUNDRUN, MPFS_SPI_INT_CLEAR); + } + + if (status & MPFS_SPI_CMDMSKINT) + { + /* Disable command interrupt to avoid retriggering */ + + modifyreg32(MPFS_SPI_CONTROL2, MPFS_SPI_INTEN_CMD, 0); + putreg32(MPFS_SPI_CMDINT, MPFS_SPI_INT_CLEAR); + } + + if (status & MPFS_SPI_SSENDMSKINT) + { + modifyreg32(MPFS_SPI_COMMAND, 0, MPFS_SPI_TXFIFORST | + MPFS_SPI_RXFIFORST); + putreg32(MPFS_SPI_SSEND, MPFS_SPI_INT_CLEAR); + } + + return OK; +} + +/**************************************************************************** + * Name: mpfs_spi_enable + * + * Description: + * Enable or disable the SPI bus + * + * Input Parameters: + * enable - enable or disable + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_enable(struct mpfs_spi_priv_s *priv, uint8_t enable) +{ + if (enable) + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_ENABLE, MPFS_SPI_ENABLE); + priv->enabled = 1; + } + else + { + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_ENABLE, 0); + priv->enabled = 0; + } +} + +/**************************************************************************** + * Name: mpfs_spi_init + * + * Description: + * Initialize mpfs SPI hardware interface + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_init(struct spi_dev_s *dev) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + const struct mpfs_spi_config_s *config = priv->config; + + /* Initialize the SPI semaphore for mutually exclusive access */ + + nxsem_init(&priv->sem_excl, 0, 1); + + nxsem_init(&priv->sem_isr, 0, 0); + nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE); + + up_disable_irq(priv->plic_irq); + + /* Perform reset and enable clocks */ + + if (priv->id == 0) + { + modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0, + (1 << SYSREG_SOFT_RESET_CR_SPI0)); + + modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, + (1 << SYSREG_SOFT_RESET_CR_SPI0), 0); + + modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0, + (1 << SYSREG_SUBBLK_CLOCK_CR_SPI0)); + } + else + { + modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0, + (1 << SYSREG_SOFT_RESET_CR_SPI1)); + + modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, + (1 << SYSREG_SOFT_RESET_CR_SPI1), 0); + + modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0, + (1 << SYSREG_SUBBLK_CLOCK_CR_SPI1)); + } + + /* Reset the device */ + + modifyreg32(MPFS_SPI_CONTROL, 0, MPFS_SPI_RESET); + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_RESET, 0); + + /* Install some default values */ + + mpfs_spi_setfrequency(dev, config->clk_freq); + mpfs_spi_setbits(dev, 8); + mpfs_spi_setmode(dev, config->mode); + + /* Set master mode */ + + mpfs_spi_set_master_mode(priv, 1); + mpfs_spi_enable(priv, 1); + + up_enable_irq(priv->plic_irq); +} + +/**************************************************************************** + * Name: mpfs_spi_deinit + * + * Description: + * Deinitialize mpfs SPI hardware interface + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mpfs_spi_deinit(struct spi_dev_s *dev) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + + up_disable_irq(priv->plic_irq); + mpfs_spi_enable(priv, 0); + irq_detach(priv->plic_irq); + + /* Disable clock */ + + if (priv->id == 0) + { + modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, + (1 << SYSREG_SUBBLK_CLOCK_CR_SPI0), + 0); + } + else + { + modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, + (1 << SYSREG_SUBBLK_CLOCK_CR_SPI1), + 0); + } + + priv->frequency = 0; + priv->actual = 0; + priv->mode = SPIDEV_MODE0; + priv->nbits = 0; +} + +/**************************************************************************** + * Name: mpfs_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *mpfs_spibus_initialize(int port) +{ + struct spi_dev_s *spi_dev; + struct mpfs_spi_priv_s *priv; + irqstate_t flags; + int ret; + + switch (port) + { +#ifdef CONFIG_MPFS_SPI0 + case 0: + priv = &g_mpfs_spi0_priv; + break; +#endif +#ifdef CONFIG_MPFS_SPI1 + case 1: + priv = &g_mpfs_spi1_priv; + break; +#endif + default: + return NULL; + } + + spi_dev = (struct spi_dev_s *)priv; + + flags = enter_critical_section(); + + if (priv->refs != 0) + { + leave_critical_section(flags); + + return spi_dev; + } + + ret = irq_attach(priv->plic_irq, mpfs_spi_irq, priv); + if (ret != OK) + { + leave_critical_section(flags); + return NULL; + } + + mpfs_spi_init(spi_dev); + + priv->refs++; + + leave_critical_section(flags); + + return spi_dev; +} + +/**************************************************************************** + * Name: mpfs_spibus_uninitialize + * + * Description: + * Uninitialize an SPI bus + * + ****************************************************************************/ + +int mpfs_spibus_uninitialize(struct spi_dev_s *dev) +{ + struct mpfs_spi_priv_s *priv = (struct mpfs_spi_priv_s *)dev; + irqstate_t flags; + + DEBUGASSERT(dev); + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(flags); + return OK; + } + + leave_critical_section(flags); + + mpfs_spi_deinit(dev); + + nxsem_destroy(&priv->sem_excl); + nxsem_destroy(&priv->sem_isr); + + return OK; +} + diff --git a/arch/risc-v/src/mpfs/mpfs_spi.h b/arch/risc-v/src/mpfs/mpfs_spi.h new file mode 100644 index 00000000000..46ad70d7c8d --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_spi.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_SPI_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *mpfs_spibus_initialize(int port); + +/**************************************************************************** + * Name: mpfs_spibus_uninitialize + * + * Description: + * Uninitialize an SPI bus + * + ****************************************************************************/ + +int mpfs_spibus_uninitialize(FAR struct spi_dev_s *dev); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_SPI_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_start.c b/arch/risc-v/src/mpfs/mpfs_start.c new file mode 100755 index 00000000000..487fc398ab4 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_start.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "chip.h" +#include "mpfs.h" +#include "mpfs_clockconfig.h" +#include "mpfs_userspace.h" +#include "riscv_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) riscv_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ + +uintptr_t g_idle_topstack = MPFS_IDLESTACK_TOP; +volatile bool g_serial_ok = false; + +extern void mpfs_cpu_boot(uint32_t); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __mpfs_start + ****************************************************************************/ + +void __mpfs_start(uint32_t mhartid) +{ + const uint32_t *src; + uint32_t *dest; + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + /* Setup PLL */ + + mpfs_clockconfig(); + + /* Configure the UART so we can get debug output */ + + mpfs_lowsetup(); + + showprogress('A'); + +#ifdef USE_EARLYSERIALINIT + riscv_earlyserialinit(); +#endif + + showprogress('B'); + + g_serial_ok = true; + + /* Do board initialization */ + + mpfs_boardinitialize(); + + showprogress('C'); + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + mpfs_userspace(); + showprogress('D'); +#endif + + /* Call nx_start() */ + + nx_start(); + + showprogress('a'); + + while (true) + { + asm("WFI"); + } +} diff --git a/arch/risc-v/src/mpfs/mpfs_systemreset.c b/arch/risc-v/src/mpfs/mpfs_systemreset.c new file mode 100644 index 00000000000..6ad6aff0242 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_systemreset.c @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_systemreset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include +#include "hardware/mpfs_memorymap.h" +#include "hardware/mpfs_sysreg.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_systemreset + * + * Description: + * Internal reset logic. + * + ****************************************************************************/ + +void up_systemreset(void) +{ + putreg32(0xdead, MPFS_SYSREG_BASE + MPFS_SYSREG_MSS_RESET_CR_OFFSET); + + /* Wait for the reset */ + + for (; ; ); +} + diff --git a/arch/risc-v/src/mpfs/mpfs_timerisr.c b/arch/risc-v/src/mpfs/mpfs_timerisr.c new file mode 100755 index 00000000000..444a4c1ad68 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_timerisr.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "riscv_arch.h" + +#include "mpfs.h" +#include "mpfs_clockconfig.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TICK_COUNT (MPFS_MSS_RTC_TOGGLE_CLK / TICK_PER_SEC) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool _b_tick_started = false; +static uint64_t *_mtime_cmp = 0L; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_reload_mtimecmp + ****************************************************************************/ + +static void mpfs_reload_mtimecmp(void) +{ + irqstate_t flags = spin_lock_irqsave(NULL); + + uint64_t current; + uint64_t next; + + if (!_b_tick_started) + { + _b_tick_started = true; + current = getreg64(MPFS_CLINT_MTIME); + } + else + { + current = getreg64(_mtime_cmp); + } + + uint64_t tick = TICK_COUNT; + next = current + tick; + + putreg64(next, _mtime_cmp); + + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: mpfs_timerisr + ****************************************************************************/ + +static int mpfs_timerisr(int irq, void *context, FAR void *arg) +{ + mpfs_reload_mtimecmp(); + + /* Process timer interrupt */ + + nxsched_process_timer(); + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + /* what is our timecmp address for this hart */ + + uint64_t hart_id = READ_CSR(mhartid); + _mtime_cmp = (uint64_t *)MPFS_CLINT_MTIMECMP0 + hart_id; + + /* Attach timer interrupt handler */ + + irq_attach(MPFS_IRQ_MTIMER, mpfs_timerisr, NULL); + + /* Reload CLINT mtimecmp */ + + mpfs_reload_mtimecmp(); + + /* And enable the timer interrupt */ + + up_enable_irq(MPFS_IRQ_MTIMER); +} diff --git a/arch/risc-v/src/mpfs/mpfs_userspace.c b/arch/risc-v/src/mpfs/mpfs_userspace.c new file mode 100755 index 00000000000..eb3c5cd16d7 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_userspace.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_userspace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "mpfs_userspace.h" +#include "riscv_internal.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* TODO: get user space mem layout info from ld script or Configuration ? */ + +#ifndef CONFIG_NUTTX_USERSPACE_SIZE +# define CONFIG_NUTTX_USERSPACE_SIZE (0x00100000) +#endif + +#ifndef CONFIG_NUTTX_USERSPACE_RAM_START +# define CONFIG_NUTTX_USERSPACE_RAM_START (0x00100000) +#endif + +#ifndef CONFIG_NUTTX_USERSPACE_RAM_SIZE +# define CONFIG_NUTTX_USERSPACE_RAM_SIZE (0x00100000) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +void mpfs_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } + + /* Configure the PMP to permit user-space access to its ROM and RAM. + * Now this is done by simply adding the whole memory area to PMP. + * 1. no access for the 1st 4KB + * 2. "RX" for the left space until 1MB + * 3. "RW" for the user RAM area + * TODO: more accurate memory size control. + */ + + riscv_config_pmp_region(0, PMPCFG_A_NAPOT, + 0, + 0x1000); + + riscv_config_pmp_region(1, PMPCFG_A_TOR | PMPCFG_X | PMPCFG_R, + 0 + CONFIG_NUTTX_USERSPACE_SIZE, + 0); + + riscv_config_pmp_region(2, PMPCFG_A_NAPOT | PMPCFG_W | PMPCFG_R, + CONFIG_NUTTX_USERSPACE_RAM_START, + CONFIG_NUTTX_USERSPACE_RAM_SIZE); +} + +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/risc-v/src/mpfs/mpfs_userspace.h b/arch/risc-v/src/mpfs/mpfs_userspace.h new file mode 100755 index 00000000000..d59073a7d77 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_userspace.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_userspace.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_USERSPACE_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_USERSPACE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void mpfs_userspace(void); +#endif + +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_USERSPACE_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_vectors.S b/arch/risc-v/src/mpfs/mpfs_vectors.S new file mode 100755 index 00000000000..94a7173fc63 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_vectors.S @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_vectors.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + + .section .text.vec + .global __reset_vec + .global __trap_vec + .global __start + +/**************************************************************************** + * Name: __reset_vec + * + * Description: + * Also __start symbol is defined to be on start of image. This is expected + * by some of Microchip tools, which can be used to e.g. flash the image + * + ****************************************************************************/ + +__start: +__reset_vec: + j __start_mpfs + +/**************************************************************************** + * Name: exception_common + * + * Description: + * All exceptions and interrupts will be handled from here. + * + ****************************************************************************/ + +__trap_vec: + j exception_common + nop diff --git a/arch/risc-v/src/rv32im/Toolchain.defs b/arch/risc-v/src/rv32im/Toolchain.defs index 281225685bd..4f88e099b10 100644 --- a/arch/risc-v/src/rv32im/Toolchain.defs +++ b/arch/risc-v/src/rv32im/Toolchain.defs @@ -49,6 +49,8 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif # Generic GNU RVG toolchain @@ -67,13 +69,6 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) endif endif -# Individual tools may limit the optimization level but, by default, the -# optimization level will be set to -Os - -ifeq ($(CONFIG_DEBUG_SYMBOLS),) -MAXOPTIMIZATION ?= -Os -endif - # Default toolchain CC = $(CROSSDEV)gcc diff --git a/arch/risc-v/src/rv32im/riscv_assert.c b/arch/risc-v/src/rv32im/riscv_assert.c index d9ec381143b..664aa9e13e1 100644 --- a/arch/risc-v/src/rv32im/riscv_assert.c +++ b/arch/risc-v/src/rv32im/riscv_assert.c @@ -59,8 +59,6 @@ * Private Functions ****************************************************************************/ -#ifdef CONFIG_ARCH_STACKDUMP - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -69,6 +67,7 @@ * Name: riscv_stackdump ****************************************************************************/ +#ifdef CONFIG_ARCH_STACKDUMP static void riscv_stackdump(uint32_t sp, uint32_t stack_top) { uint32_t stack; @@ -81,6 +80,9 @@ static void riscv_stackdump(uint32_t sp, uint32_t stack_top) ptr[4], ptr[5], ptr[6], ptr[7]); } } +#else +# define riscv_stackdump(sp, stack_top) +#endif /**************************************************************************** * Name: riscv_taskdump @@ -122,6 +124,7 @@ static inline void riscv_showtasks(void) * Name: riscv_registerdump ****************************************************************************/ +#ifdef CONFIG_ARCH_STACKDUMP static inline void riscv_registerdump(void) { /* Are user registers available from interrupt processing? */ @@ -162,18 +165,22 @@ static inline void riscv_registerdump(void) #endif } } +#else +# define riscv_registerdump() +#endif /**************************************************************************** * Name: riscv_dumpstate ****************************************************************************/ +#ifdef CONFIG_ARCH_STACKDUMP static void riscv_dumpstate(void) { struct tcb_s *rtcb = running_task(); uint32_t sp = up_getsp(); uint32_t ustackbase; uint32_t ustacksize; -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 uint32_t istackbase; uint32_t istacksize; #endif @@ -189,9 +196,9 @@ static void riscv_dumpstate(void) /* Get the limits on the interrupt stack memory */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 istackbase = (uint32_t)&g_intstackalloc; - istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~15); /* Show interrupt stack info */ @@ -248,8 +255,9 @@ static void riscv_dumpstate(void) riscv_stackdump(ustackbase, ustackbase + ustacksize); } } - -#endif /* CONFIG_ARCH_STACKDUMP */ +#else +# define riscv_dumpstate() +#endif /**************************************************************************** * Name: riscv_assert @@ -331,7 +339,7 @@ void up_assert(const char *filename, int lineno) syslog_flush(); -#if CONFIG_TASK_NAME_SIZE > 0 +#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else diff --git a/arch/risc-v/src/rv32im/riscv_blocktask.c b/arch/risc-v/src/rv32im/riscv_blocktask.c index cb6676af14c..c7d65e73191 100644 --- a/arch/risc-v/src/rv32im/riscv_blocktask.c +++ b/arch/risc-v/src/rv32im/riscv_blocktask.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/rv32im/riscv_reprioritizertr.c b/arch/risc-v/src/rv32im/riscv_reprioritizertr.c index 8a32aaa2216..bfff454995a 100644 --- a/arch/risc-v/src/rv32im/riscv_reprioritizertr.c +++ b/arch/risc-v/src/rv32im/riscv_reprioritizertr.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/rv32im/riscv_sigdeliver.c b/arch/risc-v/src/rv32im/riscv_sigdeliver.c index 64125b15802..62438bccd59 100644 --- a/arch/risc-v/src/rv32im/riscv_sigdeliver.c +++ b/arch/risc-v/src/rv32im/riscv_sigdeliver.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/rv32im/riscv_unblocktask.c b/arch/risc-v/src/rv32im/riscv_unblocktask.c index 751da096ea7..57b9160e446 100644 --- a/arch/risc-v/src/rv32im/riscv_unblocktask.c +++ b/arch/risc-v/src/rv32im/riscv_unblocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/risc-v/src/rv32m1/Kconfig b/arch/risc-v/src/rv32m1/Kconfig new file mode 100644 index 00000000000..63b082ba96a --- /dev/null +++ b/arch/risc-v/src/rv32m1/Kconfig @@ -0,0 +1,170 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "RV32M1 Configuration Options" + +choice + prompt "RV32M1 Chip Selection" + default ARCH_CHIP_RV32M1_RI5CY + depends on ARCH_CHIP_RV32M1 + +config ARCH_CHIP_RV32M1_RI5CY + bool "RV32M1_RI5CY" + select RV32M1_HAVE_ITCM + select RV32M1_HAVE_TSTMR + ---help--- + RV32M1 RI5CY, RV32IMC 256KB SRAM, 1MB FLASH. + +endchoice + +menu "RV32M1 Peripheral Support" + +# These "hidden" settings determine whether a peripheral option is available +# for the selected MCU + +config RV32M1_HAVE_LPUART0 + bool + default y + +config RV32M1_HAVE_LPUART1 + bool + default y + +config RV32M1_HAVE_LPUART2 + bool + default y + +config RV32M1_HAVE_LPUART3 + bool + default y + +config RV32M1_HAVE_ITCM + bool + default n + +config RV32M1_HAVE_TSTMR + bool + default y + +config RV32M1_LPUART + bool + default n + +config RV32M1_SERIALDRIVER + bool + default n + +# These are the peripheral selections proper + +config RV32M1_LPUART0 + bool "LPUART0" + default n + depends on RV32M1_HAVE_LPUART0 + select RV32M1_LPUART + +config RV32M1_LPUART1 + bool "LPUART1" + default n + depends on RV32M1_HAVE_LPUART1 + select RV32M1_LPUART + +config RV32M1_LPUART2 + bool "LPUART2" + default n + depends on RV32M1_HAVE_LPUART2 + select RV32M2_LPUART + +config RV32M1_LPUART3 + bool "LPUART3" + default n + depends on RV32M1_HAVE_LPUART3 + select RV32M2_LPUART + +config RV32M1_ITCM + bool "ITCM" + default n + depends on RV32M1_HAVE_ITCM + +config RV32M1_TSTMR + bool "TSTMR" + default n + depends on RV32M1_HAVE_TSTMR + +menu "LPUART Configuration" + depends on RV32M1_LPUART + +comment "LPUART Device Configuration" + +choice + prompt "LPUART0 Driver Configuration" + default RV32M1_LPUART0_SERIALDRIVER + depends on RV32M1_LPUART0 + +config RV32M1_LPUART0_SERIALDRIVER + bool "Standard serial driver" + select ARCH_HAVE_SERIAL_TERMIOS + select RV32M1_SERIALDRIVER + select LPUART0_SERIALDRIVER + +endchoice # LPUART0 Driver Configuration + +if RV32M1_LPUART0_SERIALDRIVER + +endif # RV32M1_LPUART0_SERIALDRIVER + +choice + prompt "LPUART1 Driver Configuration" + default RV32M1_LPUART1_SERIALDRIVER + depends on RV32M1_LPUART1 + +config RV32M1_LPUART1_SERIALDRIVER + bool "Standard serial driver" + select ARCH_HAVE_SERIAL_TERMIOS + select RV32M1_SERIALDRIVER + select LPUART1_SERIALDRIVER + +endchoice # LPUART1 Driver Configuration + +if RV32M1_LPUART1_SERIALDRIVER + +endif # RV32M1_LPUART1_SERIALDRIVER + +choice + prompt "LPUART2 Driver Configuration" + default RV32M1_LPUART2_SERIALDRIVER + depends on RV32M1_LPUART2 + +config RV32M1_LPUART2_SERIALDRIVER + bool "Standard serial driver" + select ARCH_HAVE_SERIAL_TERMIOS + select RV32M1_SERIALDRIVER + select LPUART2_SERIALDRIVER + +endchoice # LPUART2 Driver Configuration + +if RV32M1_LPUART2_SERIALDRIVER + +endif # RV32M1_LPUART2_SERIALDRIVER + +choice + prompt "LPUART3 Driver Configuration" + default RV32M1_LPUART3_SERIALDRIVER + depends on RV32M1_LPUART3 + +config RV32M1_LPUART3_SERIALDRIVER + bool "Standard serial driver" + select ARCH_HAVE_SERIAL_TERMIOS + select RV32M1_SERIALDRIVER + select LPUART3_SERIALDRIVER + +endchoice # LPUART3 Driver Configuration + +if RV32M1_LPUART3_SERIALDRIVER + +endif # RV32M1_LPUART3_SERIALDRIVER + +endmenu # LPUART Configuration Menu + +endmenu diff --git a/arch/risc-v/src/rv32m1/Make.defs b/arch/risc-v/src/rv32m1/Make.defs new file mode 100644 index 00000000000..cc0db880b61 --- /dev/null +++ b/arch/risc-v/src/rv32m1/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# arch/risc-v/src/rv32m1/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Specify our HEAD assembly file. This will be linked as +# the first object file, so it will appear at address 0 +HEAD_ASRC = rv32m1_vectors.S + +# Specify our general Assembly files +CHIP_ASRCS = rv32m1_head.S riscv_syscall.S + +# Specify C code within the common directory to be included +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += riscv_checkstack.c +endif + +ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) +CMN_CSRCS += riscv_vfork.c +endif + +# Specify our C code within this directory to be included +CHIP_CSRCS = rv32m1_allocateheap.c rv32m1_clockconfig.c rv32m1_gpio.c +CHIP_CSRCS += rv32m1_idle.c rv32m1_irq.c rv32m1_irq_dispatch.c +CHIP_CSRCS += rv32m1_lowputc.c rv32m1_serial.c +CHIP_CSRCS += rv32m1_start.c rv32m1_timerisr.c +CHIP_CSRCS += rv32m1_pcc.c +CHIP_CSRCS += rv32m1_delay.c rv32m1_timersvc.c diff --git a/arch/risc-v/src/rv32m1/chip.h b/arch/risc-v/src/rv32m1/chip.h new file mode 100644 index 00000000000..28fd037be0c --- /dev/null +++ b/arch/risc-v/src/rv32m1/chip.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_CHIP_H +#define __ARCH_RISCV_SRC_RV32M1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include the chip capabilities file */ + +#include + +#ifndef __ASSEMBLY__ + +/* Include the chip interrupt definition file */ + +#include + +#endif + +/* Include the chip memmap */ + +#include "rv32m1_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/rv32m1_pinmap.h" + +/* Include the chip pcc */ + +#include "hardware/rv32m1_pcc.h" + +/* Include the chip intmux */ + +#include "hardware/rv32m1_intmux.h" + +/* Incluce the linker file */ + +#include "rv32m1_linker.h" + +#endif /* __ARCH_RISCV_SRC_RV32M1_CHIP_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_eu.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_eu.h new file mode 100644 index 00000000000..c867df40f77 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_eu.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_eu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_EU_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_EU_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_EU_INTPTEN_OFFSET 0x0000 /* Interrupt Enable */ +#define RV32M1_EU_INTPTPEND_OFFSET 0x0004 /* Interrupt Pending */ +#define RV32M1_EU_INTPTPENDSET_OFFSET 0x0008 /* Set Interrupt Pending */ +#define RV32M1_EU_INTPTPENDCLR_OFFSET 0x000c /* Clear Interrupt Pending */ +#define RV32M1_EU_INTPTSECURE_OFFSET 0x0010 /* Interrupt Secure */ +#define RV32M1_EU_INTPTPRI0_OFFSET 0x0014 /* Interrupt Priority 0 */ +#define RV32M1_EU_INTPTPRI1_OFFSET 0x0018 /* Interrupt Priority 1 */ +#define RV32M1_EU_INTPTPRI2_OFFSET 0x001c /* Interrupt Priority 2 */ +#define RV32M1_EU_INTPTPRI3_OFFSET 0x0020 /* Interrupt Priority 3 */ +#define RV32M1_EU_INTPTBASE_OFFSET 0x0024 /* Interrupt Priority Base */ +#define RV32M1_EU_INTPTENACTIVE_OFFSET 0x0028 /* Interrupt Active */ +#define RV32M1_EU_INTACTPRI0_OFFSET 0x002c /* Interrupt Active Priority 0 */ +#define RV32M1_EU_INTACTPRI1_OFFSET 0x0030 /* Interrupt Active Priority 1 */ +#define RV32M1_EU_INTACTPRI2_OFFSET 0x0034 /* Interrupt Active Priority 2 */ +#define RV32M1_EU_INTACTPRI3_OFFSET 0x0038 /* Interrupt Active Priority 2 */ +#define RV32M1_EU_EVENTEN_OFFSET 0x0040 /* Event Enable */ +#define RV32M1_EU_EVENTPEND_OFFSET 0x0044 /* Event Pending */ +#define RV32M1_EU_EVTPENDSET_OFFSET 0x0048 /* Set Event Pending */ +#define RV32M1_EU_EVTPENDCLR_OFFSET 0x004c /* Clear Event Pending */ +#define RV32M1_EU_SLPCTRL_OFFSET 0x0080 /* Sleep Control */ +#define RV32M1_EU_SLPSTAT_OFFST 0x0084 /* Sleep Status */ + +/* Register Addresses *******************************************************/ + +#define RV32M1_EU_INTPTEN (RV32M1_EU_BASE + RV32M1_EU_INTPTEN_OFFSET) +#define RV32M1_EU_INTPTPEND (RV32M1_EU_BASE + RV32M1_EU_INTPTPEND_OFFSET) +#define RV32M1_EU_INTPTPENDSET (RV32M1_EU_BASE + RV32M1_EU_INTPTPENDSET_OFFSET) +#define RV32M1_EU_INTPTPENDCLR (RV32M1_EU_BASE + RV32M1_EU_INTPTPENDCLR_OFFSET) +#define RV32M1_EU_INTPTSECURE (RV32M1_EU_BASE + RV32M1_EU_INTPTSECURE_OFFSET) +#define RV32M1_EU_INTPTPRI0 (RV32M1_EU_BASE + RV32M1_EU_INTPTPRI0_OFFSET) +#define RV32M1_EU_INTPTPRI1 (RV32M1_EU_BASE + RV32M1_EU_INTPTPRI1_OFFSET) +#define RV32M1_EU_INTPTPRI2 (RV32M1_EU_BASE + RV32M1_EU_INTPTPRI2_OFFSET) +#define RV32M1_EU_INTPTPRI3 (RV32M1_EU_BASE + RV32M1_EU_INTPTPRI3_OFFSET) +#define RV32M1_EU_INTPTBASE (RV32M1_EU_BASE + RV32M1_EU_INTPTBASE_OFFSET) +#define RV32M1_EU_INTPTENACTIVE (RV32M1_EU_BASE + RV32M1_EU_INTPTENACTIVE_OFFSET) +#define RV32M1_EU_INTACTPRI0 (RV32M1_EU_BASE + RV32M1_EU_INTACTPRI0_OFFSET) +#define RV32M1_EU_INTACTPRI1 (RV32M1_EU_BASE + RV32M1_EU_INTACTPRI1_OFFSET) +#define RV32M1_EU_INTACTPRI2 (RV32M1_EU_BASE + RV32M1_EU_INTACTPRI2_OFFSET) +#define RV32M1_EU_INTACTPRI3 (RV32M1_EU_BASE + RV32M1_EU_INTACTPRI3_OFFSET) +#define RV32M1_EU_EVENTEN (RV32M1_EU_BASE + RV32M1_EU_EVENTEN_OFFSET) +#define RV32M1_EU_EVENTPEND (RV32M1_EU_BASE + RV32M1_EU_EVENTPEND_OFFSET) +#define RV32M1_EU_EVTPENDSET (RV32M1_EU_BASE + RV32M1_EU_EVTPENDSET_OFFSET) +#define RV32M1_EU_EVTPENDCLR (RV32M1_EU_BASE + RV32M1_EU_EVTPENDCLR_OFFSET) +#define RV32M1_EU_SLPCTRL (RV32M1_EU_BASE + RV32M1_EU_SLPCTRL_OFFSET) +#define RV32M1_EU_SLPSTAT (RV32M1_EU_BASE + RV32M1_EU_SLPSTAT_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define EU_INTPTPRI_BITS (4) +#define EU_INTPTPRI0_SHIFT (0) +#define EU_INTPTPRI0_MASK (0x7 << EU_INTPTPRI0_SHIFT) + +#define EU_INTPRIBASE_IPBASE_SHIFT (0) +#define EU_INTPRIBASE_IPBASE_MASK (0xf << EU_INTPRIBASE_IPBASE_SHIFT) + +#define EU_SLPCTRL_SYSRSTREQST (1 << 31) + +#define EU_SLPCTRL_SLEEP_SHIFT (0) +#define EU_SLPCTRL_SLEEP_MASK (0x3 << EU_SLPCTRL_SLEEP_SHIFT) +#define EU_SLPCTRL_SLEEP (0x1 << EU_SLPCTRL_SLEEP_SHIFT) +#define EU_SLPCTRL_DEEP_SLEEP (0x2 << EU_SLPCTRL_SLEEP_SHIFT) + +#define EU_SLPSTAT_SLEEP_SHIFT (0) +#define EU_SLPSTAT_SLEEP_MASK (0x3 << EU_SLPSTAT_SLEEP_SHIFT) +#define EU_SLPSTAT_SLEEP (0x1 << EU_SLPSTAT_SLEEP_SHIFT) +#define EU_SLPSTAT_DEEP_SLEEP (0x2 << EU_SLPSTAT_SLEEP_SHIFT) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_EU_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_gpio.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_gpio.h new file mode 100644 index 00000000000..6043cc40da5 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_gpio.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_GPIO_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_GPIO_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_GPIO_PDOR_OFFSET 0x0000 /* Port Data Output */ +#define RV32M1_GPIO_PSOR_OFFSET 0x0004 /* Port Set Output */ +#define RV32M1_GPIO_PCOR_OFFSET 0x0008 /* Port Clear Output */ +#define RV32M1_GPIO_PTOR_OFFSET 0x000c /* Port Toggle Output */ +#define RV32M1_GPIO_PDIR_OFFSET 0x0010 /* Port Data Input */ +#define RV32M1_GPIO_PDDR_OFFSET 0x0014 /* Port Data Direction */ + +/* Register Bitfield Definitions ********************************************/ + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_GPIO_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_intmux.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_intmux.h new file mode 100644 index 00000000000..a608017f90e --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_intmux.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_intmux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_INTMUX_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_INTMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_INTMUX_CH0_CSR_OFFSET 0x0000 /* Control Status */ +#define RV32M1_INTMUX_CH0_VEC_OFFSET 0x0004 /* Vector Number */ +#define RV32M1_INTMUX_CH0_IER_OFFSET 0x0010 /* Interrupt Enable */ +#define RV32M1_INTMUX_CH0_IPR_OFFSET 0x0020 /* Interrupt Pending */ +#define RV32M1_INTMUX_CH1_CSR_OFFSET 0x0040 /* Control Status */ +#define RV32M1_INTMUX_CH1_VEC_OFFSET 0x0044 /* Vector Number */ +#define RV32M1_INTMUX_CH1_IER_OFFSET 0x0050 /* Interrupt Enable */ +#define RV32M1_INTMUX_CH1_IPR_OFFSET 0x0060 /* Interrupt Pending */ +#define RV32M1_INTMUX_CH2_CSR_OFFSET 0x0080 /* Control Status */ +#define RV32M1_INTMUX_CH2_VEC_OFFSET 0x0084 /* Vector Number */ +#define RV32M1_INTMUX_CH2_IER_OFFSET 0x0090 /* Interrupt Enable */ +#define RV32M1_INTMUX_CH2_IPR_OFFSET 0x00a0 /* Interrupt Pending */ +#define RV32M1_INTMUX_CH3_CSR_OFFSET 0x00c0 /* Control Status */ +#define RV32M1_INTMUX_CH3_VEC_OFFSET 0x00c4 /* Vector Number */ +#define RV32M1_INTMUX_CH3_IER_OFFSET 0x00d0 /* Interrupt Enable */ +#define RV32M1_INTMUX_CH3_IPR_OFFSET 0x00e0 /* Interrupt Pending */ +#define RV32M1_INTMUX_CH4_CSR_OFFSET 0x0100 /* Control Status */ +#define RV32M1_INTMUX_CH4_VEC_OFFSET 0x0104 /* Vector Number */ +#define RV32M1_INTMUX_CH4_IER_OFFSET 0x0110 /* Interrupt Enable */ +#define RV32M1_INTMUX_CH4_IPR_OFFSET 0x0120 /* Interrupt Pending */ +#define RV32M1_INTMUX_CH5_CSR_OFFSET 0x0140 /* Control Status */ +#define RV32M1_INTMUX_CH5_VEC_OFFSET 0x0144 /* Vector Number */ +#define RV32M1_INTMUX_CH5_IER_OFFSET 0x0150 /* Interrupt Enable */ +#define RV32M1_INTMUX_CH5_IPR_OFFSET 0x0160 /* Interrupt Pending */ +#define RV32M1_INTMUX_CH6_CSR_OFFSET 0x0180 /* Control Status */ +#define RV32M1_INTMUX_CH6_VEC_OFFSET 0x0184 /* Vector Number */ +#define RV32M1_INTMUX_CH6_IER_OFFSET 0x0190 /* Interrupt Enable */ +#define RV32M1_INTMUX_CH6_IPR_OFFSET 0x01a0 /* Interrupt Pending */ +#define RV32M1_INTMUX_CH7_CSR_OFFSET 0x01c0 /* Control Status */ +#define RV32M1_INTMUX_CH7_VEC_OFFSET 0x01c4 /* Vector Number */ +#define RV32M1_INTMUX_CH7_IER_OFFSET 0x01d0 /* Interrupt Enable */ +#define RV32M1_INTMUX_CH7_IPR_OFFSET 0x01e0 /* Interrupt Pending */ + +#define INTMUX_CH_CSR_OFFSET 0x0000 /* Control Status */ +#define INTMUX_CH_VEC_OFFSET 0x0004 /* Vector Number */ +#define INTMUX_CH_IER_OFFSET 0x0010 /* Interrupt Enable */ +#define INTMUX_CH_IPR_OFFSET 0x0020 /* Interrupt Pending */ + +/* Register Address *********************************************************/ + +#define RV32M1_INTMUX0_CH_BASE(n) (RV32M1_INTMUX0_BASE + n * 0x40) +# define RV32M1_INTMUX_CH_BASE RV32M1_INTMUX0_CH_BASE + +/* Register Bitfield Definitions ********************************************/ + +#define INTMUX_CSR_IRQP (1 << 31) /* Bit31: Interrupt Request Pending */ +#define INTMUX_CSR_CHIN_SHIFT (8) /* Bit[11:8]: Channel Instance Number */ +#define INTMUX_CSR_CHIN_MASK (0xf << INTMUX_CSR_CHIN_SHIFT) +#define INTMUX_CSR_CHIN0 (0 << INTMUX_CSR_CHIN_SHIFT) +#define INTMUX_CSR_CHIN1 (1 << INTMUX_CSR_CHIN_SHIFT) +#define INTMUX_CSR_CHIN2 (2 << INTMUX_CSR_CHIN_SHIFT) +#define INTMUX_CSR_CHIN3 (3 << INTMUX_CSR_CHIN_SHIFT) +#define INTMUX_CSR_CHIN4 (4 << INTMUX_CSR_CHIN_SHIFT) +#define INTMUX_CSR_CHIN5 (5 << INTMUX_CSR_CHIN_SHIFT) +#define INTMUX_CSR_CHIN6 (6 << INTMUX_CSR_CHIN_SHIFT) +#define INTMUX_CSR_CHIN7 (7 << INTMUX_CSR_CHIN_SHIFT) + +#define INTMUX_CSR_IRQN_SHIFT (4) +#define INTMUX_CSR_IRQN_MASK (3 << INTMUX_CSR_IRQN_SHIFT) + +#define INTMUX_CSR_AND (1 << 1) +#define INTMUX_CSR_RST (1 << 0) + +#define INTMUX_VEC_VECN_SHIFT (2) +#define INTMUX_VEC_VECN_MASK (0xfff << INTMUX_VEC_VECN_SHIFT) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_INTMUX_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h new file mode 100644 index 00000000000..d4b784cc2c4 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPIT_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_LPIT_VERID_OFFSET 0x0000 /* Version ID */ +#define RV32M1_LPIT_PARAM_OFFSET 0x0004 /* Parameter */ +#define RV32M1_LPIT_MCR_OFFSET 0x0008 /* Module Control */ +#define RV32M1_LPIT_MSR_OFFSET 0x000c /* Module Status Register */ +#define RV32M1_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */ +#define RV32M1_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */ +#define RV32M1_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */ +#define RV32M1_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */ +#define RV32M1_LPIT_CVAL0_OFFSET 0x0024 /* Current Timer Channel 0 Value */ +#define RV32M1_LPIT_TCTRL0_OFFSET 0x0028 /* Timer Channel 0 Control */ +#define RV32M1_LPIT_TVAL1_OFFSET 0x0030 /* Timer Channel 1 Value */ +#define RV32M1_LPIT_CVAL1_OFFSET 0x0034 /* Current Timer Channel 1 Value */ +#define RV32M1_LPIT_TCTRL1_OFFSET 0x0048 /* Timer Channel 1 Control */ +#define RV32M1_LPIT_TVAL2_OFFSET 0x0040 /* Timer Channel 2 Value */ +#define RV32M1_LPIT_CVAL2_OFFSET 0x0044 /* Current Timer Channel 2 Value */ +#define RV32M1_LPIT_TCTRL2_OFFSET 0x0048 /* Timer Channel 2 Control */ +#define RV32M1_LPIT_TVAL3_OFFSET 0x0050 /* Timer Channel 3 Value */ +#define RV32M1_LPIT_CVAL3_OFFSET 0x0054 /* Current Timer Channel 3 Value */ +#define RV32M1_LPIT_TCTRL3_OFFSET 0x0058 /* Timer Channel 3 Control */ + +/* Register Bitfield Definitions ********************************************/ + +#define LPIT_PARAM_EXT_TRIG_SHIFT (8) /* Bit[15:8]: Number of External Trigger Inputs */ +#define LPIT_PARAM_EXT_TRIG_MASK (0xff << LPIT_PARAM_EXT_TRIG_SHIFT) + +#define LPIT_PARAM_CHANNEL_SHIFT (0) /* Bit[7:0]: Number of Timer Channels */ +#define LPIT_PARAM_CHANNEL_MASK (0xff << LPIT_PARAM_CHANNEL_SHIFT) + +#define LPIT_MCR_DBG_EN (1 << 3) /* Stop Timer when in Debug Mode */ +#define LPIT_MCR_DOZE_EN (1 << 2) /* DOZE Mode Enable */ +#define LPIT_MCR_SW_RST (1 << 1) /* Software Reset Bit */ +#define LPIT_MCR_M_CEN (1 << 0) /* Module Clock Enable */ + +#define LPIT_MSR_TIF3 (1 << 3) /* Channel 3 Timer Interrupt Flag */ +#define LPIT_MSR_TIF2 (1 << 2) /* Channel 2 Timer Interrupt Flag */ +#define LPIT_MSR_TIF1 (1 << 1) /* Channel 1 Timer Interrupt Flag */ +#define LPIT_MSR_TIF0 (1 << 0) /* Channel 0 Timer Interrupt Flag */ + +#define LPIT_MIER_TIE3 (1 << 3) /* Channel 3 Timer Interrupt Enable */ +#define LPIT_MIER_TIE2 (1 << 2) /* Channel 2 Timer Interrupt Enable */ +#define LPIT_MIER_TIE1 (1 << 1) /* Channel 1 Timer Interrupt Enable */ +#define LPIT_MIER_TIE0 (1 << 0) /* Channel 0 Timer Interrupt Enable */ + +#define LPIT_TCTRL_TRG_SEL_SHIFT (27) /* Bit[27:24]: Trigger Select */ +#define LPIT_TCTRL_TRG_SEL_MASK (0xf << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN0 (0 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN1 (1 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN2 (2 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN3 (3 << LPIT_TCTRL_TRG_SEL_SHIFT) + +#define LPIT_TCTRL_TRG_SRC_SHIFT (23) /* Bit23: Trigger Source */ +#define LPIT_TCTRL_TRG_SRC_MASK (1 << LPIT_TCTRL_TRG_SRC_SHIFT) +#define LPIT_TCTRL_TRG_SRC_EXTER (0 << LPIT_TCTRL_TRG_SRC_SHIFT) /* external */ +#define LPIT_TCTRL_TRG_SRC_INTER (1 << LPIT_TCTRL_TRG_SRC_SHIFT) /* internal */ + +#define LPIT_TCTRL_TROT (1 << 18) /* Timer Reload On Trigger */ +#define LPIT_TCTRL_TSOI (1 << 17) /* Timer Stop On Interrupt */ +#define LPIT_TCTRL_TSOT (1 << 16) /* Timer Start On Trigger */ + +#define LPIT_TCTRL_MODE_SHIFT (2) +#define LPIT_TCTRL_MODE_MASK (3 << LPIT_TCTRL_MODE_SHIFT) +#define LPIT_TCTRL_MODE_32PC (0 << LPIT_TCTRL_MODE_SHIFT) /* 32 Bit periodic Counter */ +#define LPIT_TCTRL_MODE_D16PC (1 << LPIT_TCTRL_MODE_SHIFT) /* Dual 16-bit periodic Counter */ +#define LPIT_TCTRL_MODE_32TA (2 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Accumulator */ +#define LPIT_TCTRL_MODE_32TIC (3 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Input Capture */ + +#define LPIT_TCTRL_CHAIN (1 << 1) /* Chain Channel */ +#define LPIT_TCTRL_T_EN (1 << 0) /* Timer Enable */ + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPIT_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_lptmr.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_lptmr.h new file mode 100644 index 00000000000..4e386583264 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_lptmr.h @@ -0,0 +1,116 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_lptmr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPTMR_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPTMR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_LPTMR_CSR_OFFSET 0x0000 /* Control Status */ +#define RV32M1_LPTMR_PSR_OFFSET 0x0004 /* Prescale */ +#define RV32M1_LPTMR_CMR_OFFSET 0x0008 /* Compare */ +#define RV32M1_LPTMR_CNR_OFFSET 0x000c /* Counter */ + +/* Register Address *********************************************************/ + +#define RV32M1_LPTMR0_CSR (RV32M1_LPTMR0_BASE + RV32M1_LPTMR_CSR_OFFSET) +#define RV32M1_LPTMR0_PSR (RV32M1_LPTMR0_BASE + RV32M1_LPTMR_PSR_OFFSET) +#define RV32M1_LPTMR0_CMR (RV32M1_LPTMR0_BASE + RV32M1_LPTMR_CMR_OFFSET) +#define RV32M1_LPTMR0_CNR (RV32M1_LPTMR0_BASE + RV32M1_LPTMR_CNR_OFFSET) + +#define RV32M1_LPTMR1_CSR (RV32M1_LPTMR1_BASE + RV32M1_LPTMR_CSR_OFFSET) +#define RV32M1_LPTMR1_PSR (RV32M1_LPTMR1_BASE + RV32M1_LPTMR_PSR_OFFSET) +#define RV32M1_LPTMR1_CMR (RV32M1_LPTMR1_BASE + RV32M1_LPTMR_CMR_OFFSET) +#define RV32M1_LPTMR1_CNR (RV32M1_LPTMR1_BASE + RV32M1_LPTMR_CNR_OFFSET) + +#define RV32M1_LPTMR2_CSR (RV32M1_LPTMR2_BASE + RV32M1_LPTMR_CSR_OFFSET) +#define RV32M1_LPTMR2_PSR (RV32M1_LPTMR2_BASE + RV32M1_LPTMR_PSR_OFFSET) +#define RV32M1_LPTMR2_CMR (RV32M1_LPTMR2_BASE + RV32M1_LPTMR_CMR_OFFSET) +#define RV32M1_LPTMR2_CNR (RV32M1_LPTMR2_BASE + RV32M1_LPTMR_CNR_OFFSET) + +#ifdef CONFIG_ARCH_CHIP_RV32M1_RI5CY +# define RV32M1_LPTMR_BASE RV32M1_LPTMR0_BASE +# define RV32M1_IRQ_LPTMR RV32M1_IRQ_LPTMR0 +#else +# define RV32M1_LPTMR_BASE RV32M1_LPTMR2_BASE +# define RV32M1_IRQ_LPTMR RV32M1_IRQ_LPTMR2 +#endif + +#define RV32M1_LPTMR_CSR (RV32M1_LPTMR_BASE + RV32M1_LPTMR_CSR_OFFSET) +#define RV32M1_LPTMR_PSR (RV32M1_LPTMR_BASE + RV32M1_LPTMR_PSR_OFFSET) +#define RV32M1_LPTMR_CMR (RV32M1_LPTMR_BASE + RV32M1_LPTMR_CMR_OFFSET) +#define RV32M1_LPTMR_CNR (RV32M1_LPTMR_BASE + RV32M1_LPTMR_CNR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define LPTMR_CSR_TDRE (1 << 8) /* Timer DMA Request Enable */ +#define LPTMR_CSR_TCF (1 << 7) /* Timer Compare Flag */ +#define LPTMR_CSR_TIE (1 << 6) /* Timer Interrupt Flag */ + +#define LPTMR_CSR_TPS_SHIFT (4) /* Bit[5:4]: Timer Pin Select */ +#define LPTMR_CSR_TPS_MASK (3 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS0 (0 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS1 (1 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS2 (2 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS3 (3 << LPTMR_CSR_TPS_SHIFT) + +#define LPTMR_CSR_TPP (1 << 3) /* Timer Pin Polarity */ +#define LPTMR_CSR_TFC (1 << 2) /* Timer Free-Running Counter */ +#define LPTMR_CSR_TMS (1 << 1) /* Timer Mode Select */ +#define LPTMR_CSR_TEN (1 << 0) /* Timer Enable */ + +#define LPTMR_PSR_PRESCALE_SHIFT (3) /* Bit[6:3]: Prescale Value */ +#define LPTMR_PSR_PRESCALE_MASK (0xf << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV2 (0 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV4 (1 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV8 (2 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV16 (3 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV32 (4 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV64 (5 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV128 (6 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV256 (7 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV512 (8 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV1024 (9 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV2048 (10 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV4096 (11 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV8192 (12 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV16384 (13 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV32768 (14 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV65536 (15 << LPTMR_PSR_PRESCALE_SHIFT) + +#define LPTMR_PSR_PBYP (1 << 2) /* Prescaler Bypass */ + +#define LPTMR_PSR_PCS_SHIFT (0) /* Bit[1:0]: Prescaler Clock Select */ +#define LPTMR_PSR_PCS_MASK (3 << LPTMR_PSR_PCS_SHIFT) +#define LPTMR_PSR_PCS_SIRCDIV3 (0 << LPTMR_PSR_PCS_SHIFT) +#define LPTMR_PSR_PCS_LPO (1 << LPTMR_PSR_PCS_SHIFT) /* LPO 1K Hz */ +#define LPTMR_PSR_PCS_RTC (2 << LPTMR_PSR_PCS_SHIFT) /* RTC 32768 Hz */ +#define LPTMR_PSR_PCS_RFOSC (3 << LPTMR_PSR_PCS_SHIFT) /* */ +# define LPTMR_PSR_PCS_SOSC LPTMR_PSR_PCS_RFOSC + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPTMR_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h new file mode 100644 index 00000000000..1f986f16946 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h @@ -0,0 +1,254 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPUART_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPUART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_LPUART_VERID_OFFSET 0x0000 /* Version ID */ +#define RV32M1_LPUART_PARAM_OFFSET 0x0004 /* Parameter */ +#define RV32M1_LPUART_GLOBAL_OFFSET 0x0008 /* Global */ +#define RV32M1_LPUART_PINCFG_OFFSET 0x000c /* Pin Configuration */ +#define RV32M1_LPUART_BAUD_OFFSET 0x0010 /* Baud Rate */ +#define RV32M1_LPUART_STAT_OFFSET 0x0014 /* Status */ +#define RV32M1_LPUART_CTRL_OFFSET 0x0018 /* Control */ +#define RV32M1_LPUART_DATA_OFFSET 0x001c /* Data */ +#define RV32M1_LPUART_MATCH_OFFSET 0x0020 /* Match Address */ +#define RV32M1_LPUART_MODIR_OFFSET 0x0024 /* Modem IrDA */ +#define RV32M1_LPUART_FIFO_OFFSET 0x0028 /* FIFO */ +#define RV32M1_LPUART_WATER_OFFSET 0x002c /* Watermark */ + +/* Register Addresses *******************************************************/ + +/* Register Bitfield Definitions ********************************************/ + +#define LPUART_PARAM_RXFIFO_SHIFT (8) +#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT) + +#define LPUART_PARAM_TXFIFO_SHIFT (8) +#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT) + +#define LPUART_GLOBAL_RST (1 << 1) + +#define LPUART_PINCFG_TRGSEL_SHIFT (0) +#define LPUART_PINCFG_TRGSEL_MASK (3 << LPUART_PINCFG_TRGSEL_SHIFT) +#define LPUART_PINCFG_TRGSEL_DISABLED (0 << LPUART_PINCFG_TRGSEL_SHIFT) +#define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) +#define LPUART_PINCFG_TRGSEL_CTS (2 << LPUART_PINCFG_TRGSEL_SHIFT) +#define LPUART_PINCFG_TRGSEL_MTX (3 << LPUART_PINCFG_TRGSEL_SHIFT) + +#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit31: Match Address Mode Enable 1 */ +#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit30: Match Address Mode Enable 2 */ +#define LPUART_BAUD_M10 (1 << 29) /* Bit29: 10-bit Mode select */ + +#define LPUART_BAUD_OSR_SHIFT (24) /* Bit[28:24]: Oversampling Ratio */ +#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_DEFAULT (0 << LPUART_BAUD_OSR_SHIFT) /* ratio of 16 */ +#define LPUART_BAUD_OSR_1_RESERVED (1 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_2_RESERVED (2 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_4 (3 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_5 (4 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_6 (5 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_7 (6 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_8 (7 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_9 (8 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_10 (9 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_11 (10 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_12 (11 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_13 (12 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_14 (13 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_15 (14 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_16 (15 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_17 (16 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_18 (17 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_19 (18 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_20 (19 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_21 (20 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_22 (21 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_23 (22 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_24 (23 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_25 (24 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_26 (25 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_27 (26 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_28 (27 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_29 (28 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_30 (29 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_31 (30 << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR_32 (31 << LPUART_BAUD_OSR_SHIFT) + +#define LPUART_BAUD_TDMAE (1 << 23) /* Bit23: Transmitter DMA Enable */ +#define LPUART_BAUD_RDMAE (1 << 21) /* Bit22: Receiver Full DMA Enable */ +#define LPUART_BAUD_RIDMAE (1 << 20) /* Bit20: Receiver Idle DMA Enable */ +#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bit[19:18]: Match Configuration */ +#define LPUART_BAUD_MATCFG_MASK (0x3 << LPUART_BAUD_MATCFG_SHIFT) +#define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */ +#define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */ +#define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */ +#define LPUART_BAUD_MATCFG_RWU (3 << LPUART_BAUD_MATCFG_SHIFT) + +#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit17: Both Edge Sampling */ +#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit16: Resynchronization Disable */ +#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit15: LIN Break Detect Interrupt Enable */ +#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit14: RX Input Active Edge Interrupt Enable */ +#define LPUART_BAUD_SBNS (1 << 13) /* Bit13: Stop Bit Number Select */ +# define LPUART_BAUD_SBNS_MASK (1 << 13) +# define LPUART_BAUD_SBNS_1 (0 << 13) +# define LPUART_BAUD_SBNS_2 (1 << 13) + +#define LPUART_BAUD_SBR_SHIFT (0) /* Bit[12:0]: Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT) + +#define LPUART_STAT_LBKDIF (1 << 31) /* Bit31: LIN Break Detect Interrupt Flag */ +#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit30: RXD Pin Active Edge Interrupt Flag */ +#define LPUART_STAT_MSBF (1 << 29) /* Bit29: MSB First */ +#define LPUART_STAT_RXINV (1 << 28) /* Bit28: Receive Data Inversion */ +#define LPUART_STAT_RWUID (1 << 27) /* Bit27: Receive Wake Up Idel Detect */ +#define LPUART_STAT_BRK13 (1 << 26) /* Bit26: Break Character Generation Length */ +#define LPUART_STAT_LBKDE (1 << 25) /* Bit25: Lin Break Detection Enable */ +#define LPUART_STAT_RAF (1 << 24) /* Bit24: Receiver Active Flag */ +#define LPUART_STAT_TDRE (1 << 23) /* Bit23: Transmit Data Register Empty Flag */ +#define LPUART_STAT_TC (1 << 22) /* Bit22: Transmission Complete Flag */ +#define LPUART_STAT_RDRF (1 << 21) /* Bit21: Receive Data Register Full Flag */ +#define LPUART_STAT_IDLE (1 << 20) /* Bit20: Idle Line Flag */ +#define LPUART_STAT_OR (1 << 19) /* Bit19: Receiver Overrun Flag */ +#define LPUART_STAT_NF (1 << 18) /* Bit18: Noise Flag */ +#define LPUART_STAT_FE (1 << 17) /* Bit17: Framing Error Flag */ +#define LPUART_STAT_PF (1 << 16) /* Bit16: Parity Error Flag */ +#define LPUART_STAT_MA1F (1 << 15) /* Bit15: Match 1 Flag */ +#define LPUART_STAT_MA2F (1 << 14) /* Bit14: Match 2 Flag */ + +#define LPUART_CTRL_R8T9 (1 << 31) /* Bit31: Receive Bit 8/Transmit Bit 9 */ +#define LPUART_CTRL_R9T8 (1 << 30) /* Bit30: Receive Bit 9/Transmit Bit 8 */ +#define LPUART_CTRL_TXDIR (1 << 29) /* Bit29: TXD Pin Direction In Single-Wire Mode */ +#define LPUART_CTRL_TXINV (1 << 28) /* Bit28: Transmit Data Inversion */ +#define LPUART_CTRL_ORIE (1 << 27) /* Bit27: Overrun Interrupt Enable */ +#define LPUART_CTRL_NEIE (1 << 26) /* Bit26: Noise Error Interrupt Enable */ +#define LPUART_CTRL_FEIE (1 << 25) /* Bit25: Framing Error Interrupt Enable */ +#define LPUART_CTRL_PEIE (1 << 24) /* Bit24: Parity Error Interrupt Enable */ +#define LPUART_CTRL_TIE (1 << 23) /* Bit23: Enable Interrupt if TDRE is 1 */ +#define LPUART_CTRL_TCIE (1 << 22) /* Bit22: Enable Interrupt if TC is 1 */ +#define LPUART_CTRL_RIE (1 << 21) /* Bit21: Receiver Interrupt Enable */ +#define LPUART_CTRL_ILIE (1 << 20) /* Bit20: Idle Line Interrupt Enable */ +#define LPUART_CTRL_TE (1 << 19) /* Bit19: Transmitter Enable */ +#define LPUART_CTRL_RE (1 << 18) /* Bit18: Receiver Enable */ +#define LPUART_CTRL_RWU (1 << 17) /* Bit17: Receiver Wakeup Control */ +#define LPUART_CTRL_SBK (1 << 16) /* Bit16: Send Break */ +#define LPUART_CTRL_MA1IE (1 << 15) /* Bit15: Match 1 Interrupt Enable */ +#define LPUART_CTRL_MA21E (1 << 14) /* Bit14: Match 2 Interrupt Enable */ +#define LPUART_CTRL_M7 (1 << 11) /* Bit11: 7-Bit Mode Select */ + +#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bit[10:8]: Idle Configuration */ +#define LPUART_CTRL_IDLECFG_MASK (0x7 << LPUART_CTRL_IDLECFG_SHIFT) +#define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) +#define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) +#define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) +#define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) +#define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) +#define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) +#define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) +#define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) + +#define LPUART_CTRL_LOOPS (1 << 7) /* Bit7: Loop Mode Select */ +#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit6: Doze Enable */ +#define LPUART_CTRL_RSRC (1 << 5) /* Bit5: Receiver Source Select */ +#define LPUART_CTRL_M (1 << 4) /* Bit4: 9-Bit or 8-Bit Mode Select */ +# define LPUART_CTRL_M_MASK (1 << 4) +# define LPUART_CTRL_M8 (0 << 4) /* 8-Bit Mode */ +# define LPUART_CTRL_M9 (1 << 4) /* 9-Bit Mode */ + +#define LPUART_CTRL_WAKE_SHIFT (1 << 3) /* Bit3: Receiver Wakeup Method Select */ +#define LPUART_CTRL_WAKE_MASK (1 << LPUART_CTRL_WAKE_SHIFT) +#define LPUART_CTRL_WAKE_IDLE (0 << LPUART_CTRL_WAKE_SHIFT) +#define LPUART_CTRL_WAKE_ADRM (1 << LPUART_CTRL_WAKE_SHIFT) + +#define LPUART_CTRL_ILT (1 << 2) +#define LPUART_CTRL_PE (1 << 1) /* Bit1: Parity Enable */ + +#define LPUART_CTRL_PT_SHIFT (0) /* Bit0: Parity Type */ +#define LPUART_CTRL_PT_MASK (1 << LPUART_CTRL_PT_SHIFT) +#define LPUART_CTRL_PT_EVEN (0 << LPUART_CTRL_PT_SHIFT) +#define LPUART_CTRL_PT_ODD (1 << LPUART_CTRL_PT_SHIFT) + +#define LPUART_DATA_NOISY (1 << 15) /* Bit15: NOISY */ +#define LPUART_DATA_PARITYE (1 << 14) /* Bit14: Parity Error */ +#define LPUART_DATA_FRETSC (1 << 13) /* Bit13: Frame Error/Transmit Special Character */ +#define LPUART_DATA_RXEMPT (1 << 12) /* Bit12: Receive Buffer Empty */ +#define LPUART_DATA_IDLINE (1 << 11) /* Bit11: Idle Line */ + +#define LPUART_MATCH_MA2_SHIFT (16) +#define LPUART_MATCH_MA2_MASK (0x3ff << LPUART_MATCH_MA2_SHIFT) + +#define LPUART_MATCH_MA1_SHIFT (0) +#define LPUART_MATCH_MA1_MASK (0x3ff << LPUART_MATCH_MA1_SHIFT) + +/* REVISIT: MODIR */ + +#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit23: TX Buffer/FIFO Empty */ +#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit22: RX Buffer/FIFO Empty */ +#define LPUART_FIFO_TXOF (1 << 17) /* Bit17: TX Buffer Overflow */ +#define LPUART_FIFO_RXUF (1 << 16) /* Bit16: RX Buffer Underflow */ +#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit15: TX Buffer/FIFO Flush */ +#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit14: RX Buffer/FIFO Flush */ + +#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bit[12:10]: Receiver Idle Empty Enable */ +#define LPUART_FIFO_RXIDEN_MASK (0x7 << LPUART_FIFO_RXIDEN_SHIFT) +#define LPUART_FIFO_RXIDEN_DISABLED (0 << LPUART_FIFO_RXIDEN_SHIFT) +#define LPUART_FIFO_RXIDEN_RXRF1 (1 << LPUART_FIFO_RXIDEN_SHIFT) +#define LPUART_FIFO_RXIDEN_RXRF2 (2 << LPUART_FIFO_RXIDEN_SHIFT) +#define LPUART_FIFO_RXIDEN_RXRF4 (3 << LPUART_FIFO_RXIDEN_SHIFT) +#define LPUART_FIFO_RXIDEN_RXRF8 (4 << LPUART_FIFO_RXIDEN_SHIFT) +#define LPUART_FIFO_RXIDEN_RXRF16 (5 << LPUART_FIFO_RXIDEN_SHIFT) +#define LPUART_FIFO_RXIDEN_RXRF32 (6 << LPUART_FIFO_RXIDEN_SHIFT) +#define LPUART_FIFO_RXIDEN_RXRF64 (7 << LPUART_FIFO_RXIDEN_SHIFT) + +#define LPUART_FIFO_TXOFE (1 << 9) /* Bit9: TX FIFO Overflow Interrupt */ +#define LPUART_FIFO_RXUFE (1 << 8) /* Bit8: RXUF generate an Interrupt */ +#define LPUART_FIFO_TXFE (1 << 7) /* Bit7: TX FIFO Enable */ + +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bit[6:4]: TX FIFO Depth */ +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) + +#define LPUART_FIFO_RXFE (1 << 3) /* Bit3: RX FIFO Enable */ + +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bit[2:0]: RX FIFO Depth */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) + +#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bit[27:24]: Receive Counter */ +#define LPUART_WATER_RXCOUNT_MASK (0xf << LPUART_WATER_RXCOUNT_SHIFT) + +#define LPUART_WATER_RXWATER_SHIFT (16) /* Bit[18:16]: Receive Watermark */ +#define LPUART_WATER_RXWATER_MASK (0x7 << LPUART_WATER_RXWATER_SHIFT) + +#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bit[11:8]: Transmit Counter */ +#define LPUART_WATER_TXCOUNT_MASK (0xf << LPUART_WATER_TXCOUNT_SHIFT) + +#define LPUART_WATER_TXWATER_SHIFT (0) /* Bit[2:0]: Transmit Watermark */ +#define LPUART_WATER_TXWATER_MASK (0x7 << LPUART_WATER_TXWATER_SHIFT) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_LPUART_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_memorymap.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_memorymap.h new file mode 100644 index 00000000000..b545771dbda --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_memorymap.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_MEMORYMAP_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_RV32M1_RI5CY) +# include "rv32m1ri5cy_memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_RV32M1_ZERORISCY) +# error "rv32m1 zero-riscy is to be continued..." +#else +# error "Unspported rv32m1 cortex-m cores" +#endif + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_MEMORYMAP_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h new file mode 100644 index 00000000000..cd133b063af --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PCC_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PCC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_PCC0_LPIT0_OFFSET 0x00c0 +#define RV32M1_PCC0_LPUART0_OFFSET 0x0108 +#define RV32M1_PCC0_LPUART1_OFFSET 0x010c +#define RV32M1_PCC0_LPUART2_OFFSET 0x0110 +#define RV32M1_PCC0_PORTA_OFFSET 0x0118 +#define RV32M1_PCC0_PORTB_OFFSET 0x011c +#define RV32M1_PCC0_PORTC_OFFSET 0x0120 +#define RV32M1_PCC0_PORTD_OFFSET 0x0124 +#define RV32M1_PCC0_INTMUX0_OFFSET 0x013c + +#define RV32M2_PCC1_DMA1_OFFSET 0x0020 +#define RV32M1_PCC1_GPIOE_OFFSET 0x003c +#define RV32M1_PCC1_XRDC_PAC_OFFSET 0x0058 +#define RV32M1_PCC1_XRDC_MRC_OFFSET 0x005c +#define RV32M1_PCC1_SEMA42_1_OFFSET 0x006c +#define RV32M1_PCC1_DMAMUX1_OFFSET 0x0084 +#define RV32M1_PCC1_INTMUX1_OFFSET 0x0088 +#define RV32M1_PCC1_MUB_OFFSET 0x0090 +#define RV32M1_PCC1_CAU3_OFFSET 0x00a0 +#define RV32M1_PCC1_TRNG_OFFSET 0x00a4 +#define RV32M1_PCC1_LPIT1_OFFSET 0x00a8 +#define RV32M1_PCC1_TPM3_OFFSET 0x00b4 +#define RV32M1_PCC1_LPI2C3_OFFSET 0x00b8 +#define RV32M1_PCC1_LPSPI3_OFFSET 0x00d4 +#define RV32M1_PCC1_LPUART3_OFFSET 0x00d8 +#define RV32M1_PCC1_PORTE_OFFSET 0x00dc +#define RV32M1_PCC1_MTB_OFFSET 0x0200 +#define RV32M1_PCC1_EXT_CLK_OFFSET 0x0204 + +/* PCC0 Register Addresses **************************************************/ + +#define RV32M1_PCC_LPIT0 (RV32M1_PCC0_BASE + RV32M1_PCC0_LPIT0_OFFSET) +#define RV32M1_PCC_LPUART0 (RV32M1_PCC0_BASE + RV32M1_PCC0_LPUART0_OFFSET) +#define RV32M1_PCC_LPUART1 (RV32M1_PCC0_BASE + RV32M1_PCC0_LPUART1_OFFSET) +#define RV32M1_PCC_LPUART2 (RV32M1_PCC0_BASE + RV32M1_PCC0_LPUART2_OFFSET) +#define RV32M1_PCC_PORTA (RV32M1_PCC0_BASE + RV32M1_PCC0_PORTA_OFFSET) +#define RV32M1_PCC_PORTB (RV32M1_PCC0_BASE + RV32M1_PCC0_PORTB_OFFSET) +#define RV32M1_PCC_PORTC (RV32M1_PCC0_BASE + RV32M1_PCC0_PORTC_OFFSET) +#define RV32M1_PCC_PORTD (RV32M1_PCC0_BASE + RV32M1_PCC0_PORTD_OFFSET) +#define RV32M1_PCC_INTMUX0 (RV32M1_PCC0_BASE + RV32M1_PCC0_INTMUX0_OFFSET) + +/* PCC1 Register Addresses **************************************************/ + +#define RV32M1_PCC_DMA1 (RV32M1_PCC1_BASE + RV32M1_PCC1_DMA1_OFFSET) +#define RV32M1_PCC_GPIOE (RV32M1_PCC1_BASE + RV32M1_PCC1_GPIOE_OFFSET) +#define RV32M1_PCC_XRDC_PAC (RV32M1_PCC1_BASE + RV32M1_PCC1_XRDC_PAC_OFFSET) +#define RV32M1_PCC_XRDC_MRC (RV32M1_PCC1_BASE + RV32M1_PCC1_XRDC_MRC_OFFSET) +#define RV32M1_PCC_SEMA42_1 (RV32M1_PCC1_BASE + RV32M1_PCC1_SEMA42_1_OFFSET) +#define RV32M1_PCC_DMAMUX1 (RV32M1_PCC1_BASE + RV32M1_PCC1_DMAMUX1_OFFSET) +#define RV32M1_PCC_INTMUX1 (RV32M1_PCC1_BASE + RV32M1_PCC1_INTMUX1_OFFSET) +#define RV32M1_PCC_MUB (RV32M1_PCC1_BASE + RV32M1_PCC1_MUB_OFFSET) +#define RV32M1_PCC_CAU3 (RV32M1_PCC1_BASE + RV32M1_PCC1_CAU3_OFFSET) +#define RV32M1_PCC_TRNG (RV32M1_PCC1_BASE + RV32M1_PCC1_TRNG_OFFSET) +#define RV32M1_PCC_LPIT1 (RV32M1_PCC1_BASE + RV32M1_PCC1_LPIT1_OFFSET) +#define RV32M1_PCC_TPM3 (RV32M1_PCC1_BASE + RV32M1_PCC1_TPM3_OFFSET) +#define RV32M1_PCC_LPI2C3 (RV32M1_PCC1_BASE + RV32M1_PCC1_LPI2C3_OFFSET) +#define RV32M1_PCC_LPSPI3 (RV32M1_PCC1_BASE + RV32M1_PCC1_LPSPI3_OFFSET) +#define RV32M1_PCC_LPUART3 (RV32M1_PCC1_BASE + RV32M1_PCC1_LPUART3_OFFSET) +#define RV32M1_PCC_PORTE (RV32M1_PCC1_BASE + RV32M1_PCC1_PORTE_OFFSET) +#define RV32M1_PCC_MTB (RV32M1_PCC1_BASE + RV32M1_PCC1_MTB_OFFSET) +#define RV32M1_PCC_EXT_CLK (RV32M1_PCC1_BASE + RV32M1_PCC1_EXT_CLK_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define PCC_CLKCFG_PCD_SHIFT (0) +#define PCC_CLKCFG_PCD_MASK (7 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_DIV1 (0 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_DIV2 (1 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_DIV3 (2 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_DIV4 (3 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_DIV5 (4 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_DIV6 (5 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_DIV7 (6 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_DIV8 (7 << PCC_CLKCFG_PCD_SHIFT) + +#define PCC_CLKCFG_FRAC (1 << 3) + +#define PCC_CLKCFG_PCS_SHIFT (24) +#define PCC_CLKCFG_PCS_MASK (7 << PCC_CLKCFG_PCS_SHIFT) +#define PCC_CLKCFG_PCS_EXTCLK (0 << PCC_CLKCFG_PCS_SHIFT) +#define PCC_CLKCFG_PCS_SOSC (1 << PCC_CLKCFG_PCS_SHIFT) +#define PCC_CLKCFG_PCS_SIRC (2 << PCC_CLKCFG_PCS_SHIFT) +#define PCC_CLKCFG_PCS_FIRC (3 << PCC_CLKCFG_PCS_SHIFT) +#define PCC_CLKCFG_PCS_LPFLL (6 << PCC_CLKCFG_PCS_SHIFT) + +#define PCC_CLKCFG_INUSE (1 << 29) + +#define PCC_CLKCFG_CGC (1 << 30) /* Bit30: Clock Gate Control */ + +#define PCC_CLKCFG_PR (1 << 31) /* Bit31: Present */ + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PCC_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_pinmap.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_pinmap.h new file mode 100644 index 00000000000..5d7a030ca14 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_pinmap.h @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_pinmap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PINMAP_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PINMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LPUARTs */ + +#define GPIO_LPUART0_RX_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN7) +#define GPIO_LPUART0_RX_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN25) +#define GPIO_LPUART0_RX_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN2) +#define GPIO_LPUART0_TX_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN8) +#define GPIO_LPUART0_TX_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN26) +#define GPIO_LPUART0_TX_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN3) +#define GPIO_LPUART0_RTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN10) +#define GPIO_LPUART0_RTS_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN24) +#define GPIO_LPUART0_RTS_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN4) +#define GPIO_LPUART0_CTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN9) +#define GPIO_LPUART0_CTS_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN22) +#define GPIO_LPUART0_CTS_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN1) + +#define GPIO_LPUART1_RX_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN2) +#define GPIO_LPUART1_RX_2 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN29) +#define GPIO_LPUART1_RX_3 (GPIO_ALT|GPIO_AF4|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN2) +#define GPIO_LPUART1_RX_4 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN25) +#define GPIO_LPUART1_TX_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN3) +#define GPIO_LPUART1_TX_2 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN30) +#define GPIO_LPUART1_TX_3 (GPIO_ALT|GPIO_AF4|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN3) +#define GPIO_LPUART1_TX_4 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN26) +#define GPIO_LPUART1_RTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN5) +#define GPIO_LPUART1_RTS_2 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTD|GPIO_PIN1) +#define GPIO_LPUART1_RTS_3 (GPIO_ALT|GPIO_AF4|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN4) +#define GPIO_LPUART1_RTS_4 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN28) +#define GPIO_LPUART1_CTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN4) +#define GPIO_LPUART1_CTS_2 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTD|GPIO_PIN0) +#define GPIO_LPUART1_CTS_3 (GPIO_ALT|GPIO_AF4|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN1) +#define GPIO_LPUART1_CTS_4 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN27) + +#define GPIO_LPUART2_RX_1 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN11) +#define GPIO_LPUART2_RX_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN18) +#define GPIO_LPUART2_RX_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN1) +#define GPIO_LPUART2_TX_1 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN12) +#define GPIO_LPUART2_TX_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN19) +#define GPIO_LPUART2_TX_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN0) +#define GPIO_LPUART2_RTS_1 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN14) +#define GPIO_LPUART2_RTS_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN21) +#define GPIO_LPUART2_RTS_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN31) +#define GPIO_LPUART2_CTS_1 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN13) +#define GPIO_LPUART2_CTS_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN20) +#define GPIO_LPUART2_CTS_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN30) + +#define GPIO_LPUART3_RX_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN28) +#define GPIO_LPUART3_RX_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN8) +#define GPIO_LPUART3_RX_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN29) +#define GPIO_LPUART3_TX_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN29) +#define GPIO_LPUART3_TX_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN9) +#define GPIO_LPUART3_TX_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN30) +#define GPIO_LPUART3_RTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN17) +#define GPIO_LPUART3_RTS_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN11) +#define GPIO_LPUART3_RTS_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN28) +#define GPIO_LPUART3_CTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN16) +#define GPIO_LPUART3_CTS_2 (GPIO_ALT|GPIO_AF3|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN10) +#define GPIO_LPUART3_CTS_3 (GPIO_ALT|GPIO_AF2|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN27) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PINMAP_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_port.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_port.h new file mode 100644 index 00000000000..0e1cce78008 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_port.h @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_port.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PORT_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PORT_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_PORT_PCR0_OFFSET 0x0000 +#define RV32M1_PORT_PCR1_OFFSET 0x0004 +#define RV32M1_PORT_PCR2_OFFSET 0x0008 +#define RV32M1_PORT_PCR3_OFFSET 0x000c +#define RV32M1_PORT_PCR4_OFFSET 0x0010 +#define RV32M1_PORT_PCR5_OFFSET 0x0014 +#define RV32M1_PORT_PCR6_OFFSET 0x0018 +#define RV32M1_PORT_PCR7_OFFSET 0x001c +#define RV32M1_PORT_PCR8_OFFSET 0x0020 +#define RV32M1_PORT_PCR9_OFFSET 0x0024 +#define RV32M1_PORT_PCR10_OFFSET 0x0028 +#define RV32M1_PORT_PCR11_OFFSET 0x002c +#define RV32M1_PORT_PCR12_OFFSET 0x0030 +#define RV32M1_PORT_PCR13_OFFSET 0x0034 +#define RV32M1_PORT_PCR14_OFFSET 0x0038 +#define RV32M1_PORT_PCR15_OFFSET 0x003c +#define RV32M1_PORT_PCR16_OFFSET 0x0040 +#define RV32M1_PORT_PCR17_OFFSET 0x0044 +#define RV32M1_PORT_PCR18_OFFSET 0x0048 +#define RV32M1_PORT_PCR19_OFFSET 0x004c +#define RV32M1_PORT_PCR20_OFFSET 0x0050 +#define RV32M1_PORT_PCR21_OFFSET 0x0054 +#define RV32M1_PORT_PCR22_OFFSET 0x0058 +#define RV32M1_PORT_PCR23_OFFSET 0x005c +#define RV32M1_PORT_PCR24_OFFSET 0x0060 +#define RV32M1_PORT_PCR25_OFFSET 0x0064 +#define RV32M1_PORT_PCR26_OFFSET 0x0068 +#define RV32M1_PORT_PCR27_OFFSET 0x006c +#define RV32M1_PORT_PCR28_OFFSET 0x0070 +#define RV32M1_PORT_PCR29_OFFSET 0x0074 +#define RV32M1_PORT_PCR30_OFFSET 0x0078 +#define RV32M1_PORT_PCR31_OFFSET 0x007c +#define RV32M1_PORT_GPCLR_OFFSET 0x0080 /* Global Pin Control Low Register */ +#define RV32M1_PORT_GPCHR_OFFSET 0x0084 /* Global Pin Control High Register */ +#define RV32M1_PORT_GICLR_OFFSET 0x0088 /* Global Interrupt Control Low Regisgter */ +#define RV32M1_PORT_GICHR_OFFSET 0x008c /* Global Interrupt Control High Register */ +#define RV32M1_PORT_ISFR_OFFSET 0x00a0 /* Interrupt Status Flag */ + +/* Register Bitfield Definitions ********************************************/ + +#define PORT_PCR_ISF (1 << 24) /* Interrupt Status Flag, W1C */ + +#define PORT_PCR_IRQC_SHIFT (16) /* Bit[19:16]: Interrupt Configuration */ +#define PORT_PCR_IRQC_MASK (0xf << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_ISF_DISABLED (0 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_DMA_RISE (1 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_DMA_FALL (2 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_DMA_EDGE (3 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_4_RESERVED (4 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_FLG_RISE (5 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_FLG_FALL (6 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_FLG_EDGE (7 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_INT_LOW (8 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_INT_RISE (9 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_INT_FALL (10 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_INT_EDGE (11 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_INT_HIGH (12 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_ACT_TRIH (13 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_ACT_TRIL (14 << PORT_PCR_IRQC_SHIFT) +#define PORT_PCR_IRQC_15_RESERVED (15 << PORT_PCR_IRQC_SHIFT) + +#define PORT_PCR_LK (1 << 15) + +#define PORT_PCR_MUX_SHIFT (8) +#define PORT_PCR_MUX_MASK (0x7 << PORT_PCR_MUX_SHIFT) +#define PORT_PCR_MUX_ALT0 (0 << PORT_PCR_MUX_SHIFT) +# define PORT_PCR_MUX_ANALOG PORT_PCR_MUX_ALT0 +#define PORT_PCR_MUX_ALT1 (1 << PORT_PCR_MUX_SHIFT) +# define PORT_PCR_MUX_GPIO PORT_PCR_MUX_ALT1 +#define PORT_PCR_MUX_ALT2 (2 << PORT_PCR_MUX_SHIFT) +#define PORT_PCR_MUX_ALT3 (3 << PORT_PCR_MUX_SHIFT) +#define PORT_PCR_MUX_ALT4 (4 << PORT_PCR_MUX_SHIFT) +#define PORT_PCR_MUX_ALT5 (5 << PORT_PCR_MUX_SHIFT) +#define PORT_PCR_MUX_ALT6 (6 << PORT_PCR_MUX_SHIFT) +#define PORT_PCR_MUX_ALT7 (7 << PORT_PCR_MUX_SHIFT) + +#define PORT_PCR_ODE (1 << 5) /* Open Drain Enable */ +#define PORT_PCR_PFE (1 << 4) /* Passive Filter Enable */ +#define PORT_PCR_SRE (1 << 2) /* Slow Slew Rate Enable */ +#define PORT_PCR_PE (1 << 1) /* Pull Enable */ + +/* if 'PE' bit is enabled, + * 'PS' bit: 0 -> internal pull down, 1: internal pull up + */ + +#define PORT_PCR_PS (1 << 0) /* Pull Select */ + +#define PORT_GPC_WE_SHIFT (16) +#define PORT_GPC_WE_MASK (0xff << PORT_GPC_WE_SHIFT) + +#define PORT_GPC_WD_SHIFT (0) +#define PORT_GPC_WD_MASK (0xff << PORT_GPC_WE_SHIFT) + +#define PORT_GIC_WE_SHIFT (16) +#define PORT_GIC_WE_MASK (0xff << PORT_GPC_WE_SHIFT) + +#define PORT_GIC_WD_SHIFT (0) +#define PORT_GIC_WD_MASK (0xff << PORT_GPC_WE_SHIFT) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_PORT_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_scg.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_scg.h new file mode 100644 index 00000000000..002592dbc8c --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_scg.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_scg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef ARCH_RISCV_SRC_RV32M1_CHIP_RV32M1_SCG_H +#define ARCH_RISCV_SRC_RV32M1_CHIP_RV32M1_SCG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_RV32M1_RI5CY) +# include "rv32m1ri5cy_scg.h" +#elif defined(CONFIG_ARCH_CHIP_RV32M1_ZERORISCY) +# error "rv32m1 zero-riscy is to be continued..." +#else +# error "Unspported rv32m1 cortex-m cores" +#endif + +#endif /* _ARCH_RISCV_SRC_RV32M1_CHIP_RV32M1_SCG_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_smc.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_smc.h new file mode 100644 index 00000000000..25f064a84c9 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_smc.h @@ -0,0 +1,114 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_smc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_SMC_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_SMC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_SMC_VERID_OFFSET 0x0000 /* Version ID */ +#define RV32M1_SMC_PARAM_OFFSET 0x0004 /* Parameter */ +#define RV32M1_SMC_PMPROT_OFFSET 0x0008 /* Power Mode Protection */ +#define RV32M1_SMC_PMCTRL_OFFSET 0x0010 /* Power Mode Control */ +#define RV32M1_SMC_PMSTAT_OFFSET 0x0018 /* Power Mode Status */ +#define RV32M1_SMC_SRS_OFFSET 0x0020 /* System Reset Status */ +#define RV32M1_SMC_RPC_OFFSET 0x0024 /* Reset Pin Control */ +#define RV32M1_SMC_SSRS_OFFSET 0x0028 /* Sticky System Reset */ +#define RV32M1_SMC_SRIE_OFFSET 0x002c /* System Reset Interrupt Enable */ +#define RV32M1_SMC_SRIF_OFFSET 0x0030 /* System Reset Interrupt Flag */ +#define RV32M1_SMC_MR_OFFSET 0x0040 /* Mode Register */ +#define RV32M1_SMC_FM_OFFSET 0x0050 /* Force Mode Register */ +#define RV32M1_SMC_SRAMLPR_OFFSET 0x0060 /* SRAM Low Power */ +#define RV32M1_SMC_SRAMDSR_OFFSET 0x0064 /* SRAM Deep Sleep */ + +/* Register Address *********************************************************/ + +#if defined(CONFIG_ARCH_CHIP_RV32M1_RI5CY) +# define RV32M1_SMC_BASE RV32M1_SMC0_BASE +#else +# define RV32M1_SMC_BASE RV32M1_SMC1_BASE +#endif + +#define RV32M1_SMC_VERID (RV32M1_SMC_BASE + RV32M1_SMC_VERID_OFFSET) +#define RV32M1_SMC_PARAM (RV32M1_SMC_BASE + RV32M1_SMC_PARAM_OFFSET) +#define RV32M1_SMC_PMPROT (RV32M1_SMC_BASE + RV32M1_SMC_PMPROT_OFFSET) +#define RV32M1_SMC_PMCTRL (RV32M1_SMC_BASE + RV32M1_SMC_PMCTRL_OFFSET) +#define RV32M1_SMC_PMSTAT (RV32M1_SMC_BASE + RV32M1_SMC_PMSTAT_OFFSET) +#define RV32M1_SMC_SRS (RV32M1_SMC_BASE + RV32M1_SMC_SRS_OFFSET) +#define RV32M1_SMC_RPC (RV32M1_SMC_BASE + RV32M1_SMC_RPC_OFFSET) +#define RV32M1_SMC_SSRS (RV32M1_SMC_BASE + RV32M1_SMC_SSRS_OFFSET) +#define RV32M1_SMC_SRIE (RV32M1_SMC_BASE + RV32M1_SMC_SRIE_OFFSET) +#define RV32M1_SMC_SRIF (RV32M1_SMC_BASE + RV32M1_SMC_SRIF_OFFSET) +#define RV32M1_SMC_MR (RV32M1_SMC_BASE + RV32M1_SMC_MR_OFFSET) +#define RV32M1_SMC_FM (RV32M1_SMC_BASE + RV32M1_SMC_FM_OFFSET) +#define RV32M1_SMC_SRAMLPR (RV32M1_SMC_BASE + RV32M1_SMC_SRAMLPR_OFFSET) +#define RV32M1_SMC_SRAMDSR (RV32M1_SMC_BASE + RV32M1_SMC_SRAMDSR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define SMC_PARAM_PWRD_INDPT (1 << 1) /* Bit1: Power Domains Independent */ + +#define SMC_PMPROT_AHSRUN (1 << 7) /* Bit7: Allow High Speed Run mode */ +#define SMC_PMPROT_AVLP (1 << 5) /* Bit5: Allow Very-Low-Power Mode */ +#define SMC_PMPROT_ALLS (1 << 3) /* Bit3: Allow Low-Leakage Stop Mode */ +#define SMC_PMPROT_AVLLS_SHIFT (0) /* Bit[1:0]: Allow Very-Low-Leakage Stop Mode */ +#define SMC_PMPROT_AVLLS_MASK (3 << SMC_PMPROT_AVLLS_SHIFT) +#define SMC_PMPROT_AVLLS_NOT_ALLOWED (0 << SMC_PMPROT_AVLLS_SHIFT) /* VLLS mode is dinied */ +#define SMC_PMPROT_AVLLS_0_1_ALLOWED (1 << SMC_PMPROT_AVLLS_SHIFT) /* VLLS0/1 mode is Allowded */ +#define SMC_PMPROT_AVLLS_2_3_ALLOWED (2 << SMC_PMPROT_AVLLS_SHIFT) /* VLLS2/3 mode is Allowed */ +#define SMC_PMPROT_AVLLS_ALL_ALLOWED (3 << SMC_PMPROT_AVLLS_SHIFT) /* VLSS0/1/2/3 mode is Allowed */ + +# define SMC_PMPROT_PM_ALL_ALLOWED \ + (SMC_PMPROT_AHSRUN | SMC_PMPROT_AVLP | \ + SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS_ALL_ALLOWED) + +#define SMC_PMCTRL_PSTOPO_SHIFT (16) /* Bit[17:16]: Partial Stop Option */ +#define SMC_PMCTRL_PSTOPO_MASK (3 << SMC_PMCTRL_PSTOPO_SHIFT) +#define SMC_PMCTRL_PSTOPO_STOP (0 << SMC_PMCTRL_PSTOPO_SHIFT) +#define SMC_PMCTRL_PSTOPO_PSTOP1 (1 << SMC_PMCTRL_PSTOPO_SHIFT) +#define SMC_PMCTRL_PSTOPO_PSTOP2 (2 << SMC_PMCTRL_PSTOPO_SHIFT) +#define SMC_PMCTRL_PSTOPO_PSTOP3 (3 << SMC_PMCTRL_PSTOPO_SHIFT) + +#define SMC_PMCTRL_RUNM_SHIFT (8) /* Bit[9:8]: Run Mode Control */ +#define SMC_PMCTRL_RUNM_MASK (3 << SMC_PMCTRL_RUNM_SHIFT) +#define SMC_PMCTRL_RUNM_RUN (0 << SMC_PMCTRL_RUNM_SHIFT) +#define SMC_PMCTRL_RUNM_VLPR (2 << SMC_PMCTRL_RUNM_SHIFT) +#define SMC_PMCTRL_RUNM_HSRUN (3 << SMC_PMCTRL_RUNM_SHIFT) + +#define SMC_PMCTRL_STOPM_SHIFT (0) /* Bit[2:0]: Stop Mode Control */ +#define SMC_PMCTRL_STOPM_MASK (7 << SMC_PMCTRL_STOPM_SHIFT) +#define SMC_PMCTRL_STOPM_STOP (0 << SMC_PMCTRL_STOPM_SHIFT) +#define SMC_PMCTRL_STOPM_VLPS (2 << SMC_PMCTRL_STOPM_SHIFT) +#define SMC_PMCTRL_STOPM_LLS (3 << SMC_PMCTRL_STOPM_SHIFT) +#define SMC_PMCTRL_STOPM_VLLS_2_3 (4 << SMC_PMCTRL_STOPM_SHIFT) +#define SMC_PMCTRL_STOPM_VLLS_0_1 (6 << SMC_PMCTRL_STOPM_SHIFT) + +#define SMC_PMSTAT_PMSTAT_SHIFT (0) /* Bit[7:0]: Power Mode Status */ +#define SMC_PMSTAT_PMSTAT_MASK (0xff << SMC_PMSTAT_PMSTAT_SHIFT) +#define SMC_PMSTAT_RUN (0x01 << SMC_PMSTAT_PMSTAT_SHIFT) +#define SMC_PMSTAT_STOP (0x02 << SMC_PMSTAT_PMSTAT_SHIFT) +#define SMC_PMSTAT_VLPR (0x04 << SMC_PMSTAT_PMSTAT_SHIFT) +#define SMC_PMSTAT_HSRUN (0x80 << SMC_PMSTAT_PMSTAT_SHIFT) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_SMC_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_tstmr.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_tstmr.h new file mode 100644 index 00000000000..f82d9b05d1e --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_tstmr.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_tstmr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_TSTMR_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_TSTMR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_TSTMR_LOW_OFFSET 0x0000 /* Time Stamp Timer Register Low */ +#define RV32M1_TSTMR_HIGH_OFFSET 0x0004 /* Time Stamp Timer Register High */ + +/* Register Address *********************************************************/ + +#define RV32M1_TSTMRA_LOW (RV32M1_TSTMRA_BASE + RV32M1_TSTMR_LOW_OFFSET) +#define RV32M1_TSTMRA_HIGH (RV32M1_TSTMRA_BASE + RV32M1_TSTMR_HIGH_OFFSET) + +#define RV32M1_TSTMRB_LOW (RV32M1_TSTMRB_BASE + RV32M1_TSTMR_LOW_OFFSET) +#define RV32M1_TSTMRB_HIGH (RV32M1_TSTMRB_BASE + RV32M1_TSTMR_HIGH_OFFSET) + +#ifdef CONFIG_ARCH_CHIP_RV32M1_RI5CY +# define RV32M1_TSTMR_BASE RV32M1_TSTMRA_BASE +#else +# define RV32M1_TSTMR_BASE RV32M1_TSTMRB_BASE +#endif + +#define RV32M1_TSTMR_LOW (RV32M1_TSTMR_BASE + RV32M1_TSTMR_LOW_OFFSET) +#define RV32M1_TSTMR_HIGH (RV32M1_TSTMR_BASE + RV32M1_TSTMR_HIGH_OFFSET) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_TSTMR_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h new file mode 100644 index 00000000000..d7daaa5ae3f --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_WDOG_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_WDOG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define RV32M1_WDOG_CS_OFFSET 0x0000 /* Control and Status */ +#define RV32M1_WDOG_CNT_OFFSET 0x0004 /* Counter */ +#define RV32M1_WDOG_TOVAL_OFFSET 0x0008 /* Timeout Value */ +#define RV32M1_WDOG_WIN_OFFSET 0x000c /* Window */ + +/* Register Address *********************************************************/ + +#if defined(CONFIG_ARCH_CHIP_RV32M1_RI5CY) +# define RV32M1_WDOG_BASE RV32M1_WDOG0_BASE +#elif defined(CONFIG_ARCH_CHIP_RV32M1_ZERORISCY) +# define RV32M1_WDOG_BASE RV32M1_WDOG1_BASE +#else +# error "Unsupported RV32M1 Watch dog" +#endif + +#define RV32M1_WDOG0_CS (RV32M1_WDOG0_BASE + RV32M1_WDOG_CS_OFFSET) +#define RV32M1_WDOG0_CNT (RV32M1_WDOG0_BASE + RV32M1_WDOG_CNT_OFFSET) +#define RV32M1_WDOG0_TOVAL (RV32M1_WDOG0_BASE + RV32M1_WDOG_TOVAL_OFFSET) +#define RV32M1_WDOG0_WIN (RV32M1_WDOG0_BASE + RV32M1_WDOG_WIN_OFFSET) + +#define RV32M1_WDOG_CS (RV32M1_WDOG_BASE + RV32M1_WDOG_CS_OFFSET) +#define RV32M1_WDOG_CNT (RV32M1_WDOG_BASE + RV32M1_WDOG_CNT_OFFSET) +#define RV32M1_WDOG_TOVAL (RV32M1_WDOG_BASE + RV32M1_WDOG_TOVAL_OFFSET) +#define RV32M1_WDOG_WIN (RV32M1_WDOG_BASE + RV32M1_WDOG_WIN_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define WDOG_CS_WIN (1 << 15) /* Bit15: Window */ +#define WDOG_CS_FLG (1 << 14) /* Bit14: Interrupt Flag */ +#define WDOG_CS_CMD32EN (1 << 13) /* Bit13: suport 32bit command */ +#define WDOG_CS_PRES (1 << 12) /* Bit12: Prescaler, '1' enables 256 prescaler */ +#define WDOG_CS_ULK (1 << 11) /* Bit11: Unlock status */ +#define WDOG_CS_RCS (1 << 10) /* Bit10: Reconfiguration Success */ + +#define WDOG_CS_CLK_SHIFT (8) /* Bit[9:8]: Watchdog Clock */ +#define WDOG_CS_CLK_MASK (3 << WDOG_CS_CLK_SHIFT) +#define WDOG_CS_CLK_BUS (0 << WDOG_CS_CLK_SHIFT) /* Bus Clock */ +#define WDOG_CS_CLK_LPO (1 << WDOG_CS_CLK_SHIFT) /* LPO Clock(1KHz) */ +#define WDOG_CS_CLK_INT (1 << WDOG_CS_CLK_SHIFT) /* Internal Clock */ +#define WDOG_CS_CLK_EXR (1 << WDOG_CS_CLK_SHIFT) /* External reference Clock */ + +#define WDOG_CS_EN (1 << 7) /* Bit7: Enable */ +#define WDOG_CS_INT (1 << 6) /* Bit6: Interrupt */ +#define WDOG_CS_UPDATE (1 << 5) /* Bit5: Allow updates */ + +#define WDOG_CS_TST_SHIFT (3) +#define WDOG_CS_TST_MASK (3 << WDOG_CS_TST_SHIFT) +#define WDOG_CS_TST_DISABLED (0 << WDOG_CS_TST_SHIFT) +#define WDOG_CS_TST_UEN (1 << WDOG_CS_TST_SHIFT) /* User Mode Enable */ +#define WDOG_CS_TST_TENL (2 << WDOG_CS_TST_SHIFT) /* Test Mode Enable with the low byte used */ +#define WDOG_CS_TST_TENH (3 << WDOG_CS_TST_SHIFT) /* Test Mode Enable with the high byte used */ + +#define WDOG_CS_DBG (1 << 2) /* Debug Enable */ +#define WDOG_CS_WAIT (1 << 1) /* Wait Enable */ +#define WDOG_CS_STOP (1 << 0) /* Stop Enable */ + +/* The unlock magic number */ + +#define WDOG_CNT_UNLOCK (0xd928c520) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1_WDOG_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_memorymap.h b/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_memorymap.h new file mode 100644 index 00000000000..3de2c52f267 --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_memorymap.h @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1RI5CY_MEMORYMAP_H +#define __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1RI5CY_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Bus Base Address *********************************************************/ + +#define RV32M1_AIPS0_BASE 0x40000000 +#define RV32M1_AIPS1_BASE 0x41000000 +#define RV32M1_FLEXRAM_BASE 0x48000000 +#define RV32M1_USB0RAM_BASE 0x48010000 +#define RV32M1_GPIO_BASE 0x48020000 +#define RV32M1_FLEXBUS_BASE 0xa0000000 +#define RV32M1_PPB0_BASE 0xe0000000 /* ARM SYS Modules */ +#define RV32M1_PPB1_BASE 0xf0000000 /* NXP SYS Modules */ + +/* AIPS0 Peripheral Offset **************************************************/ + +#define RV32M1_MSCM_OFFSET 0x00001000 +#define RV32M1_DMA0CTRL_OFFSET 0x00008000 +#define RV32M1_DMA0DESC_OFFSET 0x00009000 +#define RV32M1_SMC0_OFFSET 0x00020000 +#define RV32M1_FTFE_OFFSET 0x00023000 +#define RV32M1_WDOG0_OFFSET 0x0002a000 +#define RV32M1_PCC0_OFFSET 0x0002b000 +#define RV32M1_SCG_OFFSET 0x0002c000 +#define RV32M1_LPIT0_OFFSET 0x00030000 +#define RV32M1_LPTMR0_OFFSET 0x00032000 +#define RV32M1_LPTMR1_OFFSET 0x00033000 +#define RV32M1_TSTMRA_OFFSET 0x00034000 +#define RV32M1_LPUART0_OFFSET 0x00042000 +#define RV32M1_LPUART1_OFFSET 0x00043000 +#define RV32M1_LPUART2_OFFSET 0x00044000 +#define RV32M1_PORTA_OFFSET 0x00046000 +#define RV32M1_PORTB_OFFSET 0x00047000 +#define RV32M1_PORTC_OFFSET 0x00048000 +#define RV32M1_PORTD_OFFSET 0x00049000 +#define RV32M1_INTMUX0_OFFSET 0x0004f000 + +/* AIPS1 Peripheral Offset **************************************************/ + +#define RV32M1_GPIOE_OFFSET 0x0000f000 +#define RV32M1_PCC1_OFFSET 0x00027000 +#define RV32M1_LPTMR2_OFFSET 0x0002b000 +#define RV32M1_TSTMRB_OFFSET 0x0002c000 +#define RV32M1_RSIM_OFFSET 0x0002f000 +#define RV32M1_LPUART3_OFFSET 0x00036000 +#define RV32M1_PORTE_OFFSET 0x00037000 + +/* GPIO Peripheral Offset ***************************************************/ + +#define RV32M1_GPIOA_OFFSET 0x00000000 +#define RV32M1_GPIOB_OFFSET 0x00000040 +#define RV32M1_GPIOC_OFFSET 0x00000080 +#define RV32M1_GPIOD_OFFSET 0x000000c0 + +/* PPB0 Peripheral Offset ***************************************************/ + +#define RV32M1_EU0_OFFSET 0x00041000 /* Event Unit */ + +/* AIPS0 Peripheral Address *************************************************/ + +#define RV32M1_SMC0_BASE (RV32M1_AIPS0_BASE + RV32M1_SMC0_OFFSET) +#define RV32M1_FTFE_BASE (RV32M1_AIPS0_BASE + RV32M1_FTFE_OFFSET) +#define RV32M1_WDOG0_BASE (RV32M1_AIPS0_BASE + RV32M1_WDOG0_OFFSET) +#define RV32M1_PCC0_BASE (RV32M1_AIPS0_BASE + RV32M1_PCC0_OFFSET) +#define RV32M1_SCG_BASE (RV32M1_AIPS0_BASE + RV32M1_SCG_OFFSET) +#define RV32M1_LPIT0_BASE (RV32M1_AIPS0_BASE + RV32M1_LPIT0_OFFSET) +#define RV32M1_LPTMR0_BASE (RV32M1_AIPS0_BASE + RV32M1_LPTMR0_OFFSET) +#define RV32M1_LPTMR1_BASE (RV32M1_AIPS0_BASE + RV32M1_LPTMR0_OFFSET) +#define RV32M1_TSTMRA_BASE (RV32M1_AIPS0_BASE + RV32M1_TSTMRA_OFFSET) +#define RV32M1_LPUART0_BASE (RV32M1_AIPS0_BASE + RV32M1_LPUART0_OFFSET) +#define RV32M1_LPUART1_BASE (RV32M1_AIPS0_BASE + RV32M1_LPUART1_OFFSET) +#define RV32M1_LPUART2_BASE (RV32M1_AIPS0_BASE + RV32M1_LPUART2_OFFSET) +#define RV32M1_PORTA_BASE (RV32M1_AIPS0_BASE + RV32M1_PORTA_OFFSET) +#define RV32M1_PORTB_BASE (RV32M1_AIPS0_BASE + RV32M1_PORTB_OFFSET) +#define RV32M1_PORTC_BASE (RV32M1_AIPS0_BASE + RV32M1_PORTC_OFFSET) +#define RV32M1_PORTD_BASE (RV32M1_AIPS0_BASE + RV32M1_PORTD_OFFSET) +#define RV32M1_INTMUX0_BASE (RV32M1_AIPS0_BASE + RV32M1_INTMUX0_OFFSET) + +/* AIPS1 Peripheral Address *************************************************/ + +#define RV32M1_PORTE_BASE (RV32M1_AIPS1_BASE + RV32M1_PORTE_OFFSET) +#define RV32M1_PCC1_BASE (RV32M1_AIPS1_BASE + RV32M1_PCC1_OFFSET) +#define RV32M1_LPTMR2_BASE (RV32M1_AIPS1_BASE + RV32M1_LPTMR2_OFFSET) +#define RV32M1_TSTMRB_BASE (RV32M1_AIPS1_BASE + RV32M1_TSTMRB_OFFSET) +#define RV32M1_RSIM_BASE (RV32M1_AIPS1_BASE + RV32M1_RSIM_OFFSET) +#define RV32M1_LPUART3_BASE (RV32M1_AIPS1_BASE + RV32M1_LPUART3_OFFSET) +#define RV32M1_GPIOE_BASE (RV32M1_AIPS1_BASE + RV32M1_GPIOE_OFFSET) + +/* GPIO Peripheral Address **************************************************/ + +#define RV32M1_GPIOA_BASE (RV32M1_GPIO_BASE + RV32M1_GPIOA_OFFSET) +#define RV32M1_GPIOB_BASE (RV32M1_GPIO_BASE + RV32M1_GPIOB_OFFSET) +#define RV32M1_GPIOC_BASE (RV32M1_GPIO_BASE + RV32M1_GPIOC_OFFSET) +#define RV32M1_GPIOD_BASE (RV32M1_GPIO_BASE + RV32M1_GPIOD_OFFSET) + +/* PPB0 Peripheral Address **************************************************/ + +#define RV32M1_EU_BASE (RV32M1_PPB0_BASE + RV32M1_EU0_OFFSET) + +#endif /* __ARCH_RISCV_SRC_RV32M1_HARDWARE_RV32M1RI5CY_MEMORYMAP_H */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_scg.h b/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_scg.h new file mode 100644 index 00000000000..bde0d4b2cce --- /dev/null +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_scg.h @@ -0,0 +1,605 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_scg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef ARCH_RISCV_SRC_RV32M1_CHIP_RV32M1RI5CY_SCG_H +#define ARCH_RISCV_SRC_RV32M1_CHIP_RV32M1RI5CY_SCG_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RV32M1_SCG_VERID_OFFSET 0x0000 /* Version Id */ +#define RV32M1_SCG_PARAM_OFFSET 0x0004 /* Parameter */ +#define RV32M1_SCG_CSR_OFFSET 0x0010 /* Clock Status */ +#define RV32M1_SCG_RCCR_OFFSET 0x0014 /* Run Clock Control */ +#define RV32M1_SCG_VCCR_OFFSET 0x0018 /* VLPR Clock Control */ +#define RV32M1_SCG_HCCR_OFFSET 0x001c /* HSRUN Clock Control */ +#define RV32M1_SCG_CLKOUTCNFG_OFFSET 0x0020 /* Clock Out Control */ +#define RV32M1_SCG_SOSCCSR_OFFSET 0x0100 /* System OSC Control Status */ +#define RV32M1_SCG_SOSCDIV_OFFSET 0x0104 /* System OSC Divider */ +#define RV32M1_SCG_SIRCCSR_OFFSET 0x0200 /* Slow IRC Control Status */ +#define RV32M1_SCG_SIRCDIV_OFFSET 0x0204 /* Slow IRC Divider */ +#define RV32M1_SCG_SIRCCFG_OFFSET 0x0208 /* Slow IRC Configuration */ +#define RV32M1_SCG_FIRCCSR_OFFSET 0x0300 /* Fast IRC Constrol Status */ +#define RV32M1_SCG_FIRCDIV_OFFSET 0x0304 /* Fast IRC Divider */ +#define RV32M1_SCG_FIRCCFG_OFFSET 0x0308 /* Fast IRC Configuration */ +#define RV32M1_SCG_FIRCTCFG_OFFSET 0x030c /* Fast IRC Trim Configuration */ +#define RV32M1_SCG_FIRCSTAT_OFFSET 0x0318 /* Fast IRC Status */ +#define RV32M1_SCG_ROSCCSR_OFFSET 0x0400 /* RTC OSC Control Status */ +#define RV32M1_SCG_LPFLLCSR_OFFSET 0x0500 /* Low Power FLL Control Status */ +#define RV32M1_SCG_LPFLLDIV_OFFSET 0x0504 /* Low Power FLL Divider */ +#define RV32M1_SCG_LPFLLCFG_OFFSET 0x0508 /* Low Power FLL Configuration */ +#define RV32M1_SCG_LPFLLTCFG_OFFSET 0x050c /* Low Power FLL Trim Configuration */ +#define RV32M1_SCG_LPFLLSTAT_OFFSET 0x0514 /* Low Power FLL Status */ + +#define RV32M1_SCG_VERID (RV32M1_SCG_BASE + RV32M1_SCG_VERID_OFFSET) +#define RV32M1_SCG_PARAM (RV32M1_SCG_BASE + RV32M1_SCG_PARAM_OFFSET) +#define RV32M1_SCG_CSR (RV32M1_SCG_BASE + RV32M1_SCG_CSR_OFFSET) +#define RV32M1_SCG_RCCR (RV32M1_SCG_BASE + RV32M1_SCG_RCCR_OFFSET) +#define RV32M1_SCG_VCCR (RV32M1_SCG_BASE + RV32M1_SCG_VCCR_OFFSET) +#define RV32M1_SCG_HCCR (RV32M1_SCG_BASE + RV32M1_SCG_HCCR_OFFSET) +#define RV32M1_SCG_CLKOUTCNFG (RV32M1_SCG_BASE + RV32M1_SCG_CLKOUTCNFG_OFFSET) +#define RV32M1_SCG_SOSCCSR (RV32M1_SCG_BASE + RV32M1_SCG_SOSCCSR_OFFSET) +#define RV32M1_SCG_SOSCDIV (RV32M1_SCG_BASE + RV32M1_SCG_SOSCDIV_OFFSET) +#define RV32M1_SCG_SIRCCSR (RV32M1_SCG_BASE + RV32M1_SCG_SIRCCSR_OFFSET) +#define RV32M1_SCG_SIRCDIV (RV32M1_SCG_BASE + RV32M1_SCG_SIRCDIV_OFFSET) +#define RV32M1_SCG_SIRCCFG (RV32M1_SCG_BASE + RV32M1_SCG_SIRCCFG_OFFSET) +#define RV32M1_SCG_FIRCCSR (RV32M1_SCG_BASE + RV32M1_SCG_FIRCCSR_OFFSET) +#define RV32M1_SCG_FIRCDIV (RV32M1_SCG_BASE + RV32M1_SCG_FIRCDIV_OFFSET) +#define RV32M1_SCG_FIRCCFG (RV32M1_SCG_BASE + RV32M1_SCG_FIRCCFG_OFFSET) +#define RV32M1_SCG_FIRCTCFG (RV32M1_SCG_BASE + RV32M1_SCG_FIRCTCFG_OFFSET) +#define RV32M1_SCG_FIRCSTAT (RV32M1_SCG_BASE + RV32M1_SCG_FIRCSTAT_OFFSET) +#define RV32M1_SCG_ROSCCSR (RV32M1_SCG_BASE + RV32M1_SCG_ROSCCSR_OFFSET) +#define RV32M1_SCG_LPFLLCSR (RV32M1_SCG_BASE + RV32M1_SCG_LPFLLCSR_OFFSET) +#define RV32M1_SCG_LPFLLDIV (RV32M1_SCG_BASE + RV32M1_SCG_LPFLLDIV_OFFSET) +#define RV32M1_SCG_LPFLLCFG (RV32M1_SCG_BASE + RV32M1_SCG_LPFLLCFG_OFFSET) +#define RV32M1_SCG_LPFLLTCFG (RV32M1_SCG_BASE + RV32M1_SCG_LPFLLTCFG_OFFSET) +#define RV32M1_SCG_LPFLLSTAT (RV32M1_SCG_BASE + RV32M1_SCG_LPFLLSTAT_OFFSET) + +#define SCG_PARAM_DIVPRES_SHIFT (27) /* Divier Present */ +#define SCG_PARAM_DIVPRES_MASK (0xf << SCG_PARAM_DIVPRES_SHIFT) +#define SCG_PARAM_DIVPRES_CORE (1 << 31) +#define SCG_PARAM_DIVPRES_EXT (1 << 29) +#define SCG_PARAM_DIVRRES_BUS (1 << 28) +#define SCG_PARAM_DIVPRES_SLOW (1 << 27) + +#define SCG_PARAM_CLKPRES_SHIFT (0) /* Clock Present */ +#define SCG_PARAM_CLKPRES_MASK (0xf << SCG_PARAM_CLKPRES_SHIFT) +#define SCG_PARAM_CLKPRES_LPFLL (1 << 5) /* Low Power FLL is present */ +#define SCG_PARAM_CLKPRES_ROSC (1 << 4) /* RTC OSC is present */ +#define SCG_PARAM_CLKPRES_FIRC (1 << 3) /* Fast IRC is present */ +#define SCG_PARAM_CLKPRES_SIRC (1 << 2) /* Slow IRQ is present */ +#define SCG_PARAM_CLKPRES_SOSC (1 << 1) /* System OSC is present */ + +#define SCG_CSR_SCS_SHIFT (24) /* System Clock Source */ +#define SCG_CSR_SCS_MASK (0xf << SCG_CSR_SCS_SHIFT) +#define SCG_CSR_SCS_SOSC (1 << SCG_CSR_SCS_SHIFT) /* System OSC as source */ +#define SCG_CSR_SCS_SIRC (2 << SCG_CSR_SCS_SHIFT) /* SIRC as source */ +#define SCG_CSR_SCS_FIRC (3 << SCG_CSR_SCS_SHIFT) /* FIRC as source */ +#define SCG_CSR_SCS_ROSC (4 << SCG_CSR_SCS_SHIFT) /* RTC OSC as source */ +#define SCG_CSR_SCS_LPFLL (5 << SCG_CSR_SCS_SHIFT) /* Low Power FLL as source */ + +#define SCG_CSR_DIVCORE_SHIFT (16) /* Core Clock Divide Ratio */ +#define SCG_CSR_DIVCORE_MASK (0xf << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV1 (0 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV2 (1 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV3 (2 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV4 (3 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV5 (4 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV6 (5 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV7 (6 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV8 (7 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV9 (8 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV10 (9 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV11 (10 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV12 (11 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV13 (12 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV14 (13 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV15 (14 << SCG_CSR_DIVCORE_SHIFT) +#define SCG_CSR_DIVCORE_DIV16 (15 << SCG_CSR_DIVCORE_SHIFT) + +#define SCG_CSR_DIVEXT_SHIFT (8) /* External Clock Divide Ratio */ +#define SCG_CSR_DIVEXT_MASK (0xf << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV1 (0 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV2 (1 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV3 (2 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV4 (3 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV5 (4 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV6 (5 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV7 (6 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV8 (7 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV9 (8 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV10 (9 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV11 (10 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV12 (11 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV13 (12 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV14 (13 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV15 (14 << SCG_CSR_DIVEXT_SHIFT) +#define SCG_CSR_DIVEXT_DIV16 (15 << SCG_CSR_DIVEXT_SHIFT) + +#define SCG_CSR_DIVBUS_SHIFT (4) /* Bus Clock Divide Ratio */ +#define SCG_CSR_DIVBUS_MASK (0xf << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV1 (0 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV2 (1 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV3 (2 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV4 (3 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV5 (4 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV6 (5 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV7 (6 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV8 (7 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV9 (8 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV10 (9 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV11 (10 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV12 (11 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV13 (12 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV14 (13 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV15 (14 << SCG_CSR_DIVBUS_SHIFT) +#define SCG_CSR_DIVBUS_DIV16 (15 << SCG_CSR_DIVBUS_SHIFT) + +#define SCG_CSR_DIVSLOW_SHIFT (0) /* Slow Clock Divide Ratio */ +#define SCG_CSR_DIVSLOW_MASK (0xf << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV1 (0 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV2 (1 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV3 (2 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV4 (3 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV5 (4 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV6 (5 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV7 (6 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV8 (7 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV9 (8 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV10 ( 9 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV11 (10 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV12 (11 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV13 (12 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV14 (13 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV15 (14 << SCG_CSR_DIVSLOW_SHIFT) +#define SCG_CSR_DIVSLOW_DIV16 (15 << SCG_CSR_DIVSLOW_SHIFT) + +#define SCG_RCCR_SCS_SHIFT (24) /* System Clock Source */ +#define SCG_RCCR_SCS_MASK (0xf << SCG_RCCR_SCS_SHIFT) +#define SCG_RCCR_SCS_SOSC (1 << SCG_RCCR_SCS_SHIFT) /* System OSC as source */ +#define SCG_RCCR_SCS_SIRC (2 << SCG_RCCR_SCS_SHIFT) /* SIRC as source */ +#define SCG_RCCR_SCS_FIRC (3 << SCG_RCCR_SCS_SHIFT) /* FIRC as source */ +#define SCG_RCCR_SCS_ROSC (4 << SCG_RCCR_SCS_SHIFT) /* RTC OSC as source */ +#define SCG_RCCR_SCS_LPFLL (5 << SCG_RCCR_SCS_SHIFT) /* Low Power FLL as source */ + +#define SCG_RCCR_DIVCORE_SHIFT (16) /* Core Clock Divide Ratio */ +#define SCG_RCCR_DIVCORE_MASK (0xf << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV1 (0 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV2 (1 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV3 (2 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV4 (3 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV5 (4 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV6 (5 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV7 (6 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV8 (7 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV9 (8 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV10 (9 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV11 (10 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV12 (11 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV13 (12 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV14 (13 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV15 (14 << SCG_RCCR_DIVCORE_SHIFT) +#define SCG_RCCR_DIVCORE_DIV16 (15 << SCG_RCCR_DIVCORE_SHIFT) + +#define SCG_RCCR_DIVEXT_SHIFT (8) /* External Clock Divide Ratio */ +#define SCG_RCCR_DIVEXT_MASK (0xf << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV1 (0 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV2 (1 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV3 (2 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV4 (3 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV5 (4 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV6 (5 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV7 (6 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV8 (7 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV9 (8 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV10 (9 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV11 (10 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV12 (11 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV13 (12 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV14 (13 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV15 (14 << SCG_RCCR_DIVEXT_SHIFT) +#define SCG_RCCR_DIVEXT_DIV16 (15 << SCG_RCCR_DIVEXT_SHIFT) + +#define SCG_RCCR_DIVBUS_SHIFT (4) /* Bus Clock Divide Ratio */ +#define SCG_RCCR_DIVBUS_MASK (0xf << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV1 (0 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV2 (1 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV3 (2 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV4 (3 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV5 (4 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV6 (5 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV7 (6 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV8 (7 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV9 (8 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV10 (9 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV11 (10 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV12 (11 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV13 (12 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV14 (13 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV15 (14 << SCG_RCCR_DIVBUS_SHIFT) +#define SCG_RCCR_DIVBUS_DIV16 (15 << SCG_RCCR_DIVBUS_SHIFT) + +#define SCG_RCCR_DIVSLOW_SHIFT (0) /* Slow Clock Divide Ratio */ +#define SCG_RCCR_DIVSLOW_MASK (0xf << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV1 (0 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV2 (1 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV3 (2 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV4 (3 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV5 (4 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV6 (5 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV7 (6 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV8 (7 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV9 (8 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV10 (9 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV11 (10 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV12 (11 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV13 (12 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV14 (13 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV15 (14 << SCG_RCCR_DIVSLOW_SHIFT) +#define SCG_RCCR_DIVSLOW_DIV16 (15 << SCG_RCCR_DIVSLOW_SHIFT) + +#define SCG_HCCR_SCS_SHIFT (24) /* System Clock Source */ +#define SCG_HCCR_SCS_MASK (0xf << SCG_HCCR_SCS_SHIFT) +#define SCG_HCCR_SCS_SOSC (1 << SCG_HCCR_SCS_SHIFT) /* System OSC as source */ +#define SCG_HCCR_SCS_SIRC (2 << SCG_HCCR_SCS_SHIFT) /* SIRC as source */ +#define SCG_HCCR_SCS_FIRC (3 << SCG_HCCR_SCS_SHIFT) /* FIRC as source */ +#define SCG_HCCR_SCS_ROSC (4 << SCG_HCCR_SCS_SHIFT) /* RTC OSC as source */ +#define SCG_HCCR_SCS_LPFLL (5 << SCG_HCCR_SCS_SHIFT) /* Low Power FLL as source */ + +#define SCG_HCCR_DIVCORE_SHIFT (16) /* Core Clock Divide Ratio */ +#define SCG_HCCR_DIVCORE_MASK (0xf << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV1 (0 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV2 (1 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV3 (2 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV4 (3 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV5 (4 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV6 (5 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV7 (6 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV8 (7 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV9 (8 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV10 (9 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV11 (10 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV12 (11 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV13 (12 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV14 (13 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV15 (14 << SCG_HCCR_DIVCORE_SHIFT) +#define SCG_HCCR_DIVCORE_DIV16 (15 << SCG_HCCR_DIVCORE_SHIFT) + +#define SCG_HCCR_DIVEXT_SHIFT (8) /* External Clock Divide Ratio */ +#define SCG_HCCR_DIVEXT_MASK (0xf << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV1 (0 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV2 (1 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV3 (2 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV4 (3 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV5 (4 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV6 (5 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV7 (6 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV8 (7 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV9 (8 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV10 (9 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV11 (10 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV12 (11 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV13 (12 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV14 (13 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV15 (14 << SCG_HCCR_DIVEXT_SHIFT) +#define SCG_HCCR_DIVEXT_DIV16 (15 << SCG_HCCR_DIVEXT_SHIFT) + +#define SCG_HCCR_DIVBUS_SHIFT (4) /* Bus Clock Divide Ratio */ +#define SCG_HCCR_DIVBUS_MASK (0xf << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV1 (0 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV2 (1 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV3 (2 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV4 (3 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV5 (4 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV6 (5 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV7 (6 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV8 (7 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV9 (8 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV10 (9 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV11 (10 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV12 (11 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV13 (12 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV14 (13 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV15 (14 << SCG_HCCR_DIVBUS_SHIFT) +#define SCG_HCCR_DIVBUS_DIV16 (15 << SCG_HCCR_DIVBUS_SHIFT) + +#define SCG_HCCR_DIVSLOW_SHIFT (0) /* Slow Clock Divide Ratio */ +#define SCG_HCCR_DIVSLOW_MASK (0xf << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV1 (0 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV2 (1 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV3 (2 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV4 (3 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV5 (4 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV6 (5 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV7 (6 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV8 (7 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV9 (8 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV10 (9 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV11 (10 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV12 (11 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV13 (12 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV14 (13 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV15 (14 << SCG_HCCR_DIVSLOW_SHIFT) +#define SCG_HCCR_DIVSLOW_DIV16 (15 << SCG_HCCR_DIVSLOW_SHIFT) + +#define SCG_SOSCCSR_ERR (1 << 26) /* Bit26: System OSC Clock Error */ +#define SCG_SOSCCSR_SEL (1 << 25) /* Bit25: System OSC Selected */ +#define SCG_SOSCCSR_VLD (1 << 24) /* Bit24: System OSC Valid */ +#define SCG_SOSCCSR_LK (1 << 23) /* Bit23: System OSC Lock */ +#define SCG_SOSCCSR_CMRE (1 << 17) /* Bit17: System OSC Monitor Reset Enable */ +#define SCG_SOSCCSR_ME (1 << 16) /* Bit16: System OSC Monitor Enable */ +#define SCG_SOSCCSR_LPEN (1 << 2) /* Bit2: System OSC Low Power Enable */ +#define SCG_SOSCCSR_STEN (1 << 1) /* Bit1: System OSC Stop Enable */ +#define SCG_SOSCCSR_EN (1 << 1) /* Bit0: System OSC Enable */ + +#define SCG_SOSCDIV_DIV3_SHIFT (16) +#define SCG_SOSCDIV_DIV3_MASK (7 << SCG_SOSCDIV_DIV3_SHIFT) +#define SCG_SOSCDIV_DIV3_DISABLED (0 << SCG_SOSCDIV_DIV3_SHIFT) +#define SCG_SOSCDIV_DIV3_DIVBY1 (1 << SCG_SOSCDIV_DIV3_SHIFT) +#define SCG_SOSCDIV_DIV3_DIVBY2 (2 << SCG_SOSCDIV_DIV3_SHIFT) +#define SCG_SOSCDIV_DIV3_DIVBY4 (3 << SCG_SOSCDIV_DIV3_SHIFT) +#define SCG_SOSCDIV_DIV3_DIVBY8 (4 << SCG_SOSCDIV_DIV3_SHIFT) +#define SCG_SOSCDIV_DIV3_DIVBY16 (5 << SCG_SOSCDIV_DIV3_SHIFT) +#define SCG_SOSCDIV_DIV3_DIVBY32 (6 << SCG_SOSCDIV_DIV3_SHIFT) +#define SCG_SOSCDIV_DIV3_DIVBY64 (7 << SCG_SOSCDIV_DIV3_SHIFT) + +#define SCG_SOSCDIV_DIV2_SHIFT (8) +#define SCG_SOSCDIV_DIV2_MASK (7 << SCG_SOSCDIV_DIV2_SHIFT) +#define SCG_SOSCDIV_DIV2_DISABLED (0 << SCG_SOSCDIV_DIV2_SHIFT) +#define SCG_SOSCDIV_DIV2_DIVBY1 (1 << SCG_SOSCDIV_DIV2_SHIFT) +#define SCG_SOSCDIV_DIV2_DIVBY2 (2 << SCG_SOSCDIV_DIV2_SHIFT) +#define SCG_SOSCDIV_DIV2_DIVBY4 (3 << SCG_SOSCDIV_DIV2_SHIFT) +#define SCG_SOSCDIV_DIV2_DIVBY8 (4 << SCG_SOSCDIV_DIV2_SHIFT) +#define SCG_SOSCDIV_DIV2_DIVBY16 (5 << SCG_SOSCDIV_DIV2_SHIFT) +#define SCG_SOSCDIV_DIV2_DIVBY32 (6 << SCG_SOSCDIV_DIV2_SHIFT) +#define SCG_SOSCDIV_DIV2_DIVBY64 (7 << SCG_SOSCDIV_DIV2_SHIFT) + +#define SCG_SOSCDIV_DIV1_SHIFT (0) +#define SCG_SOSCDIV_DIV1_MASK (7 << SCG_SOSCDIV_DIV1_SHIFT) +#define SCG_SOSCDIV_DIV1_DISABLED (0 << SCG_SOSCDIV_DIV1_SHIFT) +#define SCG_SOSCDIV_DIV1_DIVBY1 (1 << SCG_SOSCDIV_DIV1_SHIFT) +#define SCG_SOSCDIV_DIV1_DIVBY2 (2 << SCG_SOSCDIV_DIV1_SHIFT) +#define SCG_SOSCDIV_DIV1_DIVBY4 (3 << SCG_SOSCDIV_DIV1_SHIFT) +#define SCG_SOSCDIV_DIV1_DIVBY8 (4 << SCG_SOSCDIV_DIV1_SHIFT) +#define SCG_SOSCDIV_DIV1_DIVBY16 (5 << SCG_SOSCDIV_DIV1_SHIFT) +#define SCG_SOSCDIV_DIV1_DIVBY32 (6 << SCG_SOSCDIV_DIV1_SHIFT) +#define SCG_SOSCDIV_DIV1_DIVBY64 (7 << SCG_SOSCDIV_DIV1_SHIFT) + +#define SCG_SIRCCSR_SEL (1 << 25) /* Bit25: Slow IRC Selected */ +#define SCG_SIRCCSR_VLD (1 << 24) /* Bit24: Slow IRC Valid */ +#define SCG_SIRCCSR_LK (1 << 23) /* Bit23: Lock */ +#define SCG_SIRCCSR_LPEN (1 << 2) /* Bit2: Slow IRC Low Power Enable */ +#define SCG_SIRCCSR_STEN (1 << 1) /* Bit3: Slow IRC Stop Enable */ +#define SCG_SIRCCSR_EN (1 << 0) /* Bit0: Slow IRC Enable */ + +#define SCG_SIRCDIV_DIV3_SHIFT (16) +#define SCG_SIRCDIV_DIV3_MASK (7 << SCG_SIRCDIV_DIV3_SHIFT) +#define SCG_SIRCDIV_DIV3_DISABLED (0 << SCG_SIRCDIV_DIV3_SHIFT) +#define SCG_SIRCDIV_DIV3_DIVBY1 (1 << SCG_SIRCDIV_DIV3_SHIFT) +#define SCG_SIRCDIV_DIV3_DIVBY2 (2 << SCG_SIRCDIV_DIV3_SHIFT) +#define SCG_SIRCDIV_DIV3_DIVBY4 (3 << SCG_SIRCDIV_DIV3_SHIFT) +#define SCG_SIRCDIV_DIV3_DIVBY8 (4 << SCG_SIRCDIV_DIV3_SHIFT) +#define SCG_SIRCDIV_DIV3_DIVBY16 (5 << SCG_SIRCDIV_DIV3_SHIFT) +#define SCG_SIRCDIV_DIV3_DIVBY32 (6 << SCG_SIRCDIV_DIV3_SHIFT) +#define SCG_SIRCDIV_DIV3_DIVBY64 (7 << SCG_SIRCDIV_DIV3_SHIFT) + +#define SCG_SIRCDIV_DIV2_SHIFT (8) +#define SCG_SIRCDIV_DIV2_MASK (7 << SCG_SIRCDIV_DIV2_SHIFT) +#define SCG_SIRCDIV_DIV2_DISABLED (0 << SCG_SIRCDIV_DIV2_SHIFT) +#define SCG_SIRCDIV_DIV2_DIVBY1 (1 << SCG_SIRCDIV_DIV2_SHIFT) +#define SCG_SIRCDIV_DIV2_DIVBY2 (2 << SCG_SIRCDIV_DIV2_SHIFT) +#define SCG_SIRCDIV_DIV2_DIVBY4 (3 << SCG_SIRCDIV_DIV2_SHIFT) +#define SCG_SIRCDIV_DIV2_DIVBY8 (4 << SCG_SIRCDIV_DIV2_SHIFT) +#define SCG_SIRCDIV_DIV2_DIVBY16 (5 << SCG_SIRCDIV_DIV2_SHIFT) +#define SCG_SIRCDIV_DIV2_DIVBY32 (6 << SCG_SIRCDIV_DIV2_SHIFT) +#define SCG_SIRCDIV_DIV2_DIVBY64 (7 << SCG_SIRCDIV_DIV2_SHIFT) + +#define SCG_SIRCDIV_DIV1_SHIFT (0) +#define SCG_SIRCDIV_DIV1_MASK (7 << SCG_SIRCDIV_DIV1_SHIFT) +#define SCG_SIRCDIV_DIV1_DISABLED (0 << SCG_SIRCDIV_DIV1_SHIFT) +#define SCG_SIRCDIV_DIV1_DIVBY1 (1 << SCG_SIRCDIV_DIV1_SHIFT) +#define SCG_SIRCDIV_DIV1_DIVBY2 (2 << SCG_SIRCDIV_DIV1_SHIFT) +#define SCG_SIRCDIV_DIV1_DIVBY4 (3 << SCG_SIRCDIV_DIV1_SHIFT) +#define SCG_SIRCDIV_DIV1_DIVBY8 (4 << SCG_SIRCDIV_DIV1_SHIFT) +#define SCG_SIRCDIV_DIV1_DIVBY16 (5 << SCG_SIRCDIV_DIV1_SHIFT) +#define SCG_SIRCDIV_DIV1_DIVBY32 (6 << SCG_SIRCDIV_DIV1_SHIFT) +#define SCG_SIRCDIV_DIV1_DIVBY64 (7 << SCG_SIRCDIV_DIV1_SHIFT) + +#define SCG_SIRCCFG_RANGE_SHIFT (0) +#define SCG_SIRCCFG_RANGE_MASK (1 << SCG_SIRCCFG_RANGE_SHIFT) +#define SCG_SIRCCFG_RANGE_2MHZ (0 << SCG_SIRCCFG_RANGE_SHIFT) +#define SCG_SIRCCFG_RANGE_8MHZ (1 << SCG_SIRCCFG_RANGE_SHIFT) + +#define SCG_FIRCCSR_ERR (1 << 26) /* Bit26: Fast IRC Clock Error */ +#define SCG_FIRCCSR_SEL (1 << 25) /* Bit25: Fast IRC Selected */ +#define SCG_FIRCCSR_VLD (1 << 24) /* Bit24: Fast IRC Valid */ +#define SCG_FIRCCSR_LK (1 << 23) /* Bit23: Lock */ +#define SCG_FIRCCSR_TRUP (1 << 9) /* Bit9: Fast IRC Trim Update */ +#define SCG_FIRCCSR_TREN (1 << 8) /* Bit8: Fast IRC Trim Enable */ +#define SCG_FIRCCSR_REGOFF (1 << 3) /* Bit3: Fast IRC Regulator Off */ +#define SCG_FIRCCSR_LPEN (1 << 2) /* Bit2: Fast IRC Low Power Enable */ +#define SCG_FIRCCSR_STEN (1 << 1) /* Bit1: Fast IRC Stop Enable */ +#define SCG_FIRCCSR_EN (1 << 0) /* Bit0: Fast IRC Enable */ + +#define SCG_FIRCDIV_DIV3_SHIFT (16) +#define SCG_FIRCDIV_DIV3_MASK (7 << SCG_FIRCDIV_DIV3_SHIFT) +#define SCG_FIRCDIV_DIV3_DISABLED (0 << SCG_FIRCDIV_DIV3_SHIFT) +#define SCG_FIRCDIV_DIV3_DIVBY1 (1 << SCG_FIRCDIV_DIV3_SHIFT) +#define SCG_FIRCDIV_DIV3_DIVBY2 (2 << SCG_FIRCDIV_DIV3_SHIFT) +#define SCG_FIRCDIV_DIV3_DIVBY4 (3 << SCG_FIRCDIV_DIV3_SHIFT) +#define SCG_FIRCDIV_DIV3_DIVBY8 (4 << SCG_FIRCDIV_DIV3_SHIFT) +#define SCG_FIRCDIV_DIV3_DIVBY16 (5 << SCG_FIRCDIV_DIV3_SHIFT) +#define SCG_FIRCDIV_DIV3_DIVBY32 (6 << SCG_FIRCDIV_DIV3_SHIFT) +#define SCG_FIRCDIV_DIV3_DIVBY64 (7 << SCG_FIRCDIV_DIV3_SHIFT) + +#define SCG_FIRCDIV_DIV2_SHIFT (8) +#define SCG_FIRCDIV_DIV2_MASK (7 << SCG_FIRCDIV_DIV2_SHIFT) +#define SCG_FIRCDIV_DIV2_DISABLED (0 << SCG_FIRCDIV_DIV2_SHIFT) +#define SCG_FIRCDIV_DIV2_DIVBY1 (1 << SCG_FIRCDIV_DIV2_SHIFT) +#define SCG_FIRCDIV_DIV2_DIVBY2 (2 << SCG_FIRCDIV_DIV2_SHIFT) +#define SCG_FIRCDIV_DIV2_DIVBY4 (3 << SCG_FIRCDIV_DIV2_SHIFT) +#define SCG_FIRCDIV_DIV2_DIVBY8 (4 << SCG_FIRCDIV_DIV2_SHIFT) +#define SCG_FIRCDIV_DIV2_DIVBY16 (5 << SCG_FIRCDIV_DIV2_SHIFT) +#define SCG_FIRCDIV_DIV2_DIVBY32 (6 << SCG_FIRCDIV_DIV2_SHIFT) +#define SCG_FIRCDIV_DIV2_DIVBY64 (7 << SCG_FIRCDIV_DIV2_SHIFT) + +#define SCG_FIRCDIV_DIV1_SHIFT (0) +#define SCG_FIRCDIV_DIV1_MASK (7 << SCG_FIRCDIV_DIV1_SHIFT) +#define SCG_FIRCDIV_DIV1_DISABLED (0 << SCG_FIRCDIV_DIV1_SHIFT) +#define SCG_FIRCDIV_DIV1_DIVBY1 (1 << SCG_FIRCDIV_DIV1_SHIFT) +#define SCG_FIRCDIV_DIV1_DIVBY2 (2 << SCG_FIRCDIV_DIV1_SHIFT) +#define SCG_FIRCDIV_DIV1_DIVBY4 (3 << SCG_FIRCDIV_DIV1_SHIFT) +#define SCG_FIRCDIV_DIV1_DIVBY8 (4 << SCG_FIRCDIV_DIV1_SHIFT) +#define SCG_FIRCDIV_DIV1_DIVBY16 (5 << SCG_FIRCDIV_DIV1_SHIFT) +#define SCG_FIRCDIV_DIV1_DIVBY32 (6 << SCG_FIRCDIV_DIV1_SHIFT) +#define SCG_FIRCDIV_DIV1_DIVBY64 (7 << SCG_FIRCDIV_DIV1_SHIFT) + +#define SCG_FIRCCFG_RANGE_SHIFT (0) +#define SCG_FIRCCFG_RANGE_MASK (3 << SCG_FIRCCFG_RANGE_SHIFT) +#define SCG_FIRCCFG_RANGE_48MHZ (0 << SCG_FIRCCFG_RANGE_SHIFT) +#define SCG_FIRCCFG_RANGE_52MHZ (1 << SCG_FIRCCFG_RANGE_SHIFT) +#define SCG_FIRCCFG_RANGE_56MHZ (2 << SCG_FIRCCFG_RANGE_SHIFT) +#define SCG_FIRCCFG_RANGE_60MHZ (3 << SCG_FIRCCFG_RANGE_SHIFT) + +/* FIRC Trim Configuration */ + +#define SCG_FIRCTCFG_TRIMDIV_SHIFT (8) /* Divide the System OSC down for Fast IRC Triming */ +#define SCG_FIRCTCFG_TRIMDIV_MASK (7 << SCG_FIRCTCFG_TRIMDIV_SHIFT) +#define SCG_FIRCTCFG_TRIMDIV_DIVBY1 (0 << SCG_FIRCTCFG_TRIMDIV_SHIFT) +#define SCG_FIRCTCFG_TRIMDIV_DIVBY128 (1 << SCG_FIRCTCFG_TRIMDIV_SHIFT) +#define SCG_FIRCTCFG_TRIMDIV_DIVBY256 (2 << SCG_FIRCTCFG_TRIMDIV_SHIFT) +#define SCG_FIRCTCFG_TRIMDIV_DIVBY512 (3 << SCG_FIRCTCFG_TRIMDIV_SHIFT) +#define SCG_FIRCTCFG_TRIMDIV_DIVBY1024 (4 << SCG_FIRCTCFG_TRIMDIV_SHIFT) +#define SCG_FIRCTCFG_TRIMDIV_DIVBY2048 (5 << SCG_FIRCTCFG_TRIMDIV_SHIFT) + +#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0) /* Bit0: Trim Source */ +#define SCG_FIRCTCFG_TRIMSRC_MASK (3 << SCG_FIRCTCFG_TRIMSRC_SHIFT) +#define SCG_FIRCTCFG_TRIMSRC_SOSC (2 << SCG_FIRCTCFG_TRIMSRC_SHIFT) +#define SCG_FIRCTCFG_TRIMSRC_ROSC (3 << SCG_FIRCTCFG_TRIMSRC_SHIFT) + +#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8) +#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3f << SCG_FIRCSTAT_TRIMCOAR_SHIFT) + +#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0) +#define SCG_FIRCSTAT_TRIMFINE_MASK (0x7f << SCG_FIRCSTAT_TRIMFINE_SHIFT) + +#define SCG_ROSCCSR_ERR (1 << 26) /* Bit26: RTC Clock Error */ +#define SCG_ROSCCSR_SEL (1 << 25) /* Bit25: RTC Selected */ +#define SCG_ROSCCSR_VLD (1 << 24) /* Bit24: RTC Valid */ +#define SCG_ROSCCSR_LK (1 << 23) /* Bit23: Lock */ +#define SCG_ROSCCSR_CMRE (1 << 17) /* Bit17: RTC Clock Monitor Reset Enable */ +#define SCG_ROSCCSR_CM (1 << 16) /* Bit16: RTC Clock Monitor Enable */ + +#define SCG_LPFLLCSR_ERR (1 << 26) /* Bit26: LPFLL Clock Error */ +#define SCG_LPFLLCSR_SEL (1 << 25) /* Bit25: LPFLL Selected */ +#define SCG_LPFLLCSR_VLD (1 << 24) /* Bit24: LPFLL Valid */ +#define SCG_LPFLLCSR_LK (1 << 23) /* Bit23: Lock */ +#define SCG_LPFLLCSR_CMRE (1 << 17) /* Bit17: LPFLL Clock Monitor Reset Enable */ +#define SCG_LPFLLCSR_CM (1 << 16) /* Bit16: LPFLL Clock Monitor */ +#define SCG_LPFLLCSR_TRMLOCK (1 << 10) /* Bit10: LPFLL Trim Lock */ +#define SCG_LPFLLCSR_TRUP (1 << 9) /* Bit9: LPFLL Trim Update */ +#define SCG_LPFLLCSR_TREN (1 << 8) /* Bit8: LPFLL Trim Enable */ +#define SCG_LPFLLCSR_STEN (1 << 1) /* Bit1: LPFLL Stop Enable */ +#define SCG_LPFLLCSR_EN (1 << 0) /* Bit0: LPFLL Enable */ + +#define SCG_LPFLLDIV_DIV3_SHIFT (16) +#define SCG_LPFLLDIV_DIV3_MASK (7 << SCG_LPFLLDIV_DIV3_SHIFT) +#define SCG_LPFLLDIV_DIV3_DISABLED (0 << SCG_LPFLLDIV_DIV3_SHIFT) +#define SCG_LPFLLDIV_DIV3_DIVBY1 (1 << SCG_LPFLLDIV_DIV3_SHIFT) +#define SCG_LPFLLDIV_DIV3_DIVBY2 (2 << SCG_LPFLLDIV_DIV3_SHIFT) +#define SCG_LPFLLDIV_DIV3_DIVBY4 (3 << SCG_LPFLLDIV_DIV3_SHIFT) +#define SCG_LPFLLDIV_DIV3_DIVBY8 (4 << SCG_LPFLLDIV_DIV3_SHIFT) +#define SCG_LPFLLDIV_DIV3_DIVBY16 (5 << SCG_LPFLLDIV_DIV3_SHIFT) +#define SCG_LPFLLDIV_DIV3_DIVBY32 (6 << SCG_LPFLLDIV_DIV3_SHIFT) +#define SCG_LPFLLDIV_DIV3_DIVBY64 (7 << SCG_LPFLLDIV_DIV3_SHIFT) + +#define SCG_LPFLLDIV_DIV2_SHIFT (8) +#define SCG_LPFLLDIV_DIV2_MASK (7 << SCG_LPFLLDIV_DIV2_SHIFT) +#define SCG_LPFLLDIV_DIV2_DISABLED (0 << SCG_LPFLLDIV_DIV2_SHIFT) +#define SCG_LPFLLDIV_DIV2_DIVBY1 (1 << SCG_LPFLLDIV_DIV2_SHIFT) +#define SCG_LPFLLDIV_DIV2_DIVBY2 (2 << SCG_LPFLLDIV_DIV2_SHIFT) +#define SCG_LPFLLDIV_DIV2_DIVBY4 (3 << SCG_LPFLLDIV_DIV2_SHIFT) +#define SCG_LPFLLDIV_DIV2_DIVBY8 (4 << SCG_LPFLLDIV_DIV2_SHIFT) +#define SCG_LPFLLDIV_DIV2_DIVBY16 (5 << SCG_LPFLLDIV_DIV2_SHIFT) +#define SCG_LPFLLDIV_DIV2_DIVBY32 (6 << SCG_LPFLLDIV_DIV2_SHIFT) +#define SCG_LPFLLDIV_DIV2_DIVBY64 (7 << SCG_LPFLLDIV_DIV2_SHIFT) + +#define SCG_LPFLLDIV_DIV1_SHIFT (0) +#define SCG_LPFLLDIV_DIV1_MASK (7 << SCG_LPFLLDIV_DIV1_SHIFT) +#define SCG_LPFLLDIV_DIV1_DISABLED (0 << SCG_LPFLLDIV_DIV1_SHIFT) +#define SCG_LPFLLDIV_DIV1_DIVBY1 (1 << SCG_LPFLLDIV_DIV1_SHIFT) +#define SCG_LPFLLDIV_DIV1_DIVBY2 (2 << SCG_LPFLLDIV_DIV1_SHIFT) +#define SCG_LPFLLDIV_DIV1_DIVBY4 (3 << SCG_LPFLLDIV_DIV1_SHIFT) +#define SCG_LPFLLDIV_DIV1_DIVBY8 (4 << SCG_LPFLLDIV_DIV1_SHIFT) +#define SCG_LPFLLDIV_DIV1_DIVBY16 (5 << SCG_LPFLLDIV_DIV1_SHIFT) +#define SCG_LPFLLDIV_DIV1_DIVBY32 (6 << SCG_LPFLLDIV_DIV1_SHIFT) +#define SCG_LPFLLDIV_DIV1_DIVBY64 (7 << SCG_LPFLLDIV_DIV1_SHIFT) + +#define SCG_LPFLLCFG_RANGE_SHIFT (0) /* Bit[1:0]: Frequency Range */ +#define SCG_LPFLLCFG_RANGE_MASK (3 << SCG_LPFLLCFG_RANGE_SHIFT) +#define SCG_LPFLLCFG_RANGE_48MHZ (0 << SCG_LPFLLCFG_RANGE_SHIFT) +#define SCG_LPFLLCFG_RANGE_72MHZ (1 << SCG_LPFLLCFG_RANGE_SHIFT) + +#define SCG_LPFLLTCFG_LOCKW2LSB (1 << 16) /* Bit16: Lock LPFLL with 2 LSBS */ + +#define SCG_LPFLLTCFG_TRIMDIV_SHIFT (8) /* Bit[12:8]: LPFLL Trim Predivide */ +#define SCG_LPFLLTCFG_TRIMDIV_MASK (0x1f << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY1 (0 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY2 (1 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY3 (2 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY4 (3 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY5 (4 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY6 (5 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY7 (6 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY8 (7 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY9 (8 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY10 (9 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY11 (10 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY12 (11 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY13 (12 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY14 (13 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY15 (14 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY16 (15 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY17 (16 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY18 (17 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY19 (18 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY20 (19 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY21 (20 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY22 (21 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY23 (22 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY24 (23 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY25 (24 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY26 (25 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY27 (26 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY28 (27 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY29 (28 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY30 (29 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY31 (30 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) +#define SCG_LPFLLTCFG_TRIMDIV_BY32 (31 << SCG_LPFLLTCFG_TRIMDIV_SHIFT) + +#define SCG_LPFLLTCFG_TRIMSRC_SHIFT (0) +#define SCG_LPFLLTCFG_TRIMSRC_MASK (3 << SCG_LPFLLTCFG_TRIMSRC_SHIFT) +#define SCG_LPFLLTCFG_TRIMSRC_SIRC (0 << SCG_LPFLLTCFG_TRIMSRC_SHIFT) +#define SCG_LPFLLTCFG_TRIMSRC_FIRC (1 << SCG_LPFLLTCFG_TRIMSRC_SHIFT) +#define SCG_LPFLLTCFG_TRIMSRC_SOSC (2 << SCG_LPFLLTCFG_TRIMSRC_SHIFT) +#define SCG_LPFLLTCFG_TRIMSRC_ROSC (3 << SCG_LPFLLTCFG_TRIMSRC_SHIFT) + +#endif /* _ARCH_RISCV_SRC_RV32M1_CHIP_RV32M1RI5CY_SCG_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1.h b/arch/risc-v/src/rv32m1/rv32m1.h new file mode 100644 index 00000000000..35ff060995d --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_RV32M1_H +#define __ARCH_RISCV_SRC_RV32M1_RV32M1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "riscv_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" + +#include "rv32m1_clockconfig.h" +#include "rv32m1_pcc.h" +#include "rv32m1_gpio.h" + +#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_allocateheap.c b/arch/risc-v/src/rv32m1/rv32m1_allocateheap.c new file mode 100644 index 00000000000..ee9ba52ffa9 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_allocateheap.c @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "rv32m1.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: riscv_addregion + * + * Description: + * RAM may be added in non-contiguous chunks. This routine adds all chunks + * that may be used for heap. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void riscv_addregion(void) +{ +} +#endif diff --git a/arch/risc-v/src/rv32m1/rv32m1_clockconfig.c b/arch/risc-v/src/rv32m1/rv32m1_clockconfig.c new file mode 100644 index 00000000000..d11b4852f6b --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_clockconfig.c @@ -0,0 +1,663 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "riscv_arch.h" +#include "chip.h" +#include "hardware/rv32m1_scg.h" +#include "hardware/rv32m1_smc.h" +#include "rv32m1_clockconfig.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_modifyreg32 + ****************************************************************************/ + +static void rv32m1_modifyreg32(uint32_t addr, uint32_t bitclr, + uint32_t bitset) +{ + uint32_t regval = getreg32(addr); + regval &= ~bitclr; + regval |= bitset; + putreg32(regval, addr); +} + +/**************************************************************************** + * Name: rv32m1_sircfreq + ****************************************************************************/ + +static unsigned rv32m1_sircfreq(void) +{ + uint32_t regval = getreg32(RV32M1_SCG_SIRCCSR); + + /* If the SIRC is Invalid or Disabled */ + + if (!(regval & SCG_SIRCCSR_VLD)) + { + return 0u; + } + + regval = getreg32(RV32M1_SCG_SIRCCFG) & SCG_SIRCCFG_RANGE_MASK; + if (regval == SCG_SIRCCFG_RANGE_8MHZ) + { + return 8000000u; + } + + /* SIRC provides 2 options of frequency: 8MHz and 2MHz, + * In this case, it has to be 2MHz. + */ + + return 2000000u; +} + +/**************************************************************************** + * Name: rv32m1_fircfreq + ****************************************************************************/ + +static unsigned rv32m1_fircfreq(void) +{ + uint32_t regval = getreg32(RV32M1_SCG_FIRCCSR); + + /* If the FIRC is Invalid or Disabled */ + + if (!(regval & SCG_FIRCCSR_VLD)) + { + return 0u; + } + + regval = getreg32(RV32M1_SCG_FIRCCFG) & SCG_FIRCCFG_RANGE_MASK; + if (regval == SCG_FIRCCFG_RANGE_48MHZ) + { + return 48000000u; + } + + if (regval == SCG_FIRCCFG_RANGE_52MHZ) + { + return 52000000u; + } + + if (regval == SCG_FIRCCFG_RANGE_56MHZ) + { + return 56000000u; + } + + /* FIRC provides 4 options of frequency: 48MHz, 52MHz, 56MHz, 60MHz, + * In this case, it has to be 60MHz. + */ + + return 60000000u; +} + +/**************************************************************************** + * Name: rv32m1_lpfllfreq + ****************************************************************************/ + +static unsigned rv32m1_lpfllfreq(void) +{ + uint32_t regval = getreg32(RV32M1_SCG_LPFLLCSR); + + /* If the LPFLL is Invalid or Disabled */ + + if (!(regval & SCG_LPFLLCSR_VLD)) + { + return 0u; + } + + regval = getreg32(RV32M1_SCG_LPFLLCFG) & SCG_LPFLLCFG_RANGE_MASK; + if (regval == SCG_LPFLLCFG_RANGE_48MHZ) + { + return 48000000u; + } + + /* LPFLL provides 2 options of frequency: 48MHz, 72MHz, + * In this case, it has to be 72MHz. + */ + + return 72000000u; +} + +/**************************************************************************** + * Name: rv32m1_soscfreq + ****************************************************************************/ + +static unsigned rv32m1_soscfreq(void) +{ + uint32_t regval = getreg32(RV32M1_SCG_SOSCCSR); + + /* If the SOSC is Invalid or Disabled */ + + if (!(regval & SCG_SOSCCSR_VLD)) + { + return 0u; + } + +#ifdef RV32M1_BOARD_XTAL + return RV32M1_BOARD_XTAL; +#else + return 0u; +#endif +} + +/**************************************************************************** + * Name: rv32m1_lpocfreq + ****************************************************************************/ + +static unsigned rv32m1_lpocfreq(void) +{ + return 1000u; +} + +/**************************************************************************** + * Name: rv32m1_roscfreq + ****************************************************************************/ + +static unsigned rv32m1_roscfreq(void) +{ + uint32_t regval = getreg32(RV32M1_SCG_ROSCCSR); + + /* If the ROSC is Invalid or Disabled */ + + if (!(regval & SCG_ROSCCSR_VLD)) + { + return 0; + } + + return 32768u; +} + +/**************************************************************************** + * Name: rv32m1_corefreq + ****************************************************************************/ + +static unsigned rv32m1_corefreq(void) +{ + uint32_t scs; + uint32_t div; + + uint32_t regval = getreg32(RV32M1_SCG_ROSCCSR); + uint32_t freq = 0; + + scs = regval & SCG_CSR_SCS_MASK; + + switch (scs) + { + case SCG_CSR_SCS_SOSC: + freq = rv32m1_soscfreq(); + break; + + case SCG_CSR_SCS_SIRC: + freq = rv32m1_sircfreq(); + break; + + case SCG_CSR_SCS_FIRC: + freq = rv32m1_fircfreq(); + break; + + case SCG_CSR_SCS_ROSC: + freq = rv32m1_roscfreq(); + break; + + case SCG_CSR_SCS_LPFLL: + freq = rv32m1_lpfllfreq(); + break; + + default: + freq = 0; + break; + } + + div = (regval & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT; + div += 1; + + return freq / div; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_clockconfig + ****************************************************************************/ + +void rv32m1_clockconfig(void) +{ + /* Initialize SIRC */ + + putreg32(SCG_SIRCDIV_DIV1_DISABLED | + SCG_SIRCDIV_DIV2_DIVBY1 | + SCG_SIRCDIV_DIV3_DIVBY1 , + RV32M1_SCG_SIRCDIV); + + /* 8MHZ is wanted */ + + putreg32(SCG_SIRCCFG_RANGE_8MHZ, RV32M1_SCG_SIRCCFG); + + /* Enable SIRC with Lower Power Mode support */ + + rv32m1_modifyreg32(RV32M1_SCG_SIRCCSR, 0, + SCG_SIRCCSR_EN | SCG_SIRCCSR_LPEN); + + /* Wait for SIRC to be valid */ + + while (!(getreg32(RV32M1_SCG_SIRCCSR) & SCG_SIRCCSR_VLD)) ; + + /* Switch to SIRC clock as System Clock */ + + putreg32(SCG_RCCR_SCS_SIRC | + SCG_RCCR_DIVCORE_DIV1 | + SCG_RCCR_DIVSLOW_DIV4 , + RV32M1_SCG_RCCR); + + /* Wait for SIRC as System Clock */ + + while ((getreg32(RV32M1_SCG_CSR) & SCG_CSR_SCS_MASK) != + SCG_CSR_SCS_SIRC); + + /* Initialize FIRC */ + + putreg32(SCG_FIRCDIV_DIV1_DIVBY1 | + SCG_FIRCDIV_DIV2_DIVBY1 | + SCG_FIRCDIV_DIV3_DIVBY1 , + RV32M1_SCG_FIRCDIV); + + /* 48MHz is wanted */ + + putreg32(SCG_FIRCCFG_RANGE_48MHZ, RV32M1_SCG_FIRCCFG); + + /* Enable FIRC */ + + rv32m1_modifyreg32(RV32M1_SCG_FIRCCSR, 0, SCG_FIRCCSR_EN); + + /* Wait for FIRC to be valid */ + + while (!(getreg32(RV32M1_SCG_FIRCCSR) & SCG_FIRCCSR_VLD)) ; + + /* Switch FIRC as the RUN Mode System Clock */ + + putreg32(SCG_RCCR_SCS_FIRC | + SCG_RCCR_DIVCORE_DIV1 | + SCG_RCCR_DIVBUS_DIV1 | + SCG_RCCR_DIVEXT_DIV1 | + SCG_RCCR_DIVSLOW_DIV4 , + RV32M1_SCG_RCCR); + + /* Wait for FIRC as System Clock */ + + while ((getreg32(RV32M1_SCG_CSR) & SCG_CSR_SCS_MASK) != + SCG_CSR_SCS_FIRC); + + /* Prepare LPFLL for HSRUN Mode */ + + putreg32(SCG_LPFLLDIV_DIV1_DIVBY1 | + SCG_LPFLLDIV_DIV2_DIVBY1 | + SCG_LPFLLDIV_DIV3_DIVBY1 , + RV32M1_SCG_LPFLLDIV); + + /* 72MHz is wanted */ + + putreg32(SCG_LPFLLCFG_RANGE_72MHZ, RV32M1_SCG_LPFLLCFG); + + /* Trim LPFLL input source */ + + rv32m1_modifyreg32(RV32M1_SCG_LPFLLTCFG, + SCG_LPFLLTCFG_TRIMDIV_MASK | + SCG_LPFLLTCFG_TRIMSRC_MASK, + SCG_LPFLLTCFG_TRIMDIV_BY4 | + SCG_LPFLLTCFG_TRIMSRC_SIRC); + + /* Enable LPFLL */ + + rv32m1_modifyreg32(RV32M1_SCG_LPFLLCSR, 0, SCG_LPFLLCSR_EN); + + /* Wait for LPFLL to be valid */ + + while (!(getreg32(RV32M1_SCG_LPFLLCSR) & SCG_LPFLLCSR_VLD)) ; + + /* Set LPFLL as the HSRUN Mode System Clock */ + + putreg32(SCG_HCCR_SCS_LPFLL | + SCG_HCCR_DIVCORE_DIV1 | + SCG_HCCR_DIVBUS_DIV1 | + SCG_HCCR_DIVEXT_DIV1 | + SCG_HCCR_DIVSLOW_DIV4 , + RV32M1_SCG_HCCR); + + /* Remove the power mode protection */ + + putreg32(SMC_PMPROT_PM_ALL_ALLOWED, RV32M1_SMC_PMPROT); + + /* Enable HSRUN Mode */ + + rv32m1_modifyreg32(RV32M1_SMC_PMCTRL, + SMC_PMCTRL_RUNM_MASK, + SMC_PMCTRL_RUNM_HSRUN); + + /* Wait for High Speed Run Mode stable */ + + while ((getreg32(RV32M1_SMC_PMSTAT) & SMC_PMSTAT_PMSTAT_MASK) != + SMC_PMSTAT_HSRUN); + + /* Wait for LPFLL as System Clock */ + + while ((getreg32(RV32M1_SCG_CSR) & SCG_CSR_SCS_MASK) != + SCG_CSR_SCS_LPFLL); +} + +/**************************************************************************** + * Name: rv32m1_clockfreq + * + * Description: + * Query the frequecy of a given clock source. + * + ****************************************************************************/ + +unsigned rv32m1_clockfreq(enum clk_e clk) +{ + uint32_t freq; + uint32_t div; + + switch (clk) + { + case CLK_SIRC: + return rv32m1_sircfreq(); + + case CLK_SIRCDIV1: + { + freq = rv32m1_sircfreq(); + div = (getreg32(RV32M1_SCG_SIRCDIV) & SCG_SIRCDIV_DIV1_MASK) >> + SCG_SIRCDIV_DIV1_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_SIRCDIV2: + { + freq = rv32m1_sircfreq(); + div = (getreg32(RV32M1_SCG_SIRCDIV) & SCG_SIRCDIV_DIV2_MASK) >> + SCG_SIRCDIV_DIV2_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_SIRCDIV3: + { + freq = rv32m1_sircfreq(); + div = (getreg32(RV32M1_SCG_SIRCDIV) & SCG_SIRCDIV_DIV3_MASK) >> + SCG_SIRCDIV_DIV3_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_FIRC: + return freq = rv32m1_fircfreq(); + + case CLK_FIRCDIV1: + { + freq = rv32m1_fircfreq(); + div = (getreg32(RV32M1_SCG_FIRCDIV) & SCG_FIRCDIV_DIV1_MASK) >> + SCG_FIRCDIV_DIV1_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_FIRCDIV2: + { + freq = rv32m1_fircfreq(); + div = (getreg32(RV32M1_SCG_FIRCDIV) & SCG_FIRCDIV_DIV2_MASK) >> + SCG_FIRCDIV_DIV2_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_FIRCDIV3: + { + freq = rv32m1_fircfreq(); + div = (getreg32(RV32M1_SCG_FIRCDIV) & SCG_FIRCDIV_DIV3_MASK) >> + SCG_FIRCDIV_DIV3_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_LPFLL: + return freq = rv32m1_lpfllfreq(); + + case CLK_LPFLLDIV1: + { + freq = rv32m1_lpfllfreq(); + div = (getreg32(RV32M1_SCG_LPFLLDIV) & SCG_LPFLLDIV_DIV1_MASK) >> + SCG_LPFLLDIV_DIV1_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_LPFLLDIV2: + { + freq = rv32m1_lpfllfreq(); + div = (getreg32(RV32M1_SCG_LPFLLDIV) & SCG_LPFLLDIV_DIV2_MASK) >> + SCG_LPFLLDIV_DIV2_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_LPFLLDIV3: + { + freq = rv32m1_lpfllfreq(); + div = (getreg32(RV32M1_SCG_LPFLLDIV) & SCG_LPFLLDIV_DIV3_MASK) >> + SCG_LPFLLDIV_DIV3_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_SOSC: + return rv32m1_soscfreq(); + + case CLK_SOSCDIV1: + { + freq = rv32m1_soscfreq(); + div = (getreg32(RV32M1_SCG_SOSCDIV) & SCG_SOSCDIV_DIV1_MASK) >> + SCG_LPFLLDIV_DIV1_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_SOSCDIV2: + { + freq = rv32m1_soscfreq(); + div = (getreg32(RV32M1_SCG_SOSCDIV) & SCG_SOSCDIV_DIV2_MASK) >> + SCG_LPFLLDIV_DIV2_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_SOSCDIV3: + { + freq = rv32m1_soscfreq(); + div = (getreg32(RV32M1_SCG_SOSCDIV) & SCG_SOSCDIV_DIV3_MASK) >> + SCG_LPFLLDIV_DIV3_SHIFT; + + /* If div is Zero, the clock source is disabled */ + + if (div == 0) + { + return 0u; + } + + return freq / (1 << (div - 1)); + } + break; + + case CLK_LPOC: + return rv32m1_lpocfreq(); + + case CLK_ROSC: + return rv32m1_roscfreq(); + + case CLK_CORE: + case CLK_PLAT: + case CLK_SYS: + return rv32m1_corefreq(); + + case CLK_BUS: + { + freq = rv32m1_corefreq(); + div = (getreg32(RV32M1_SCG_CSR) & SCG_CSR_DIVBUS_MASK) >> + SCG_CSR_DIVBUS_SHIFT; + + div += 1; + return freq / div; + } + break; + + case CLK_EXT: + { + freq = rv32m1_corefreq(); + div = (getreg32(RV32M1_SCG_CSR) & SCG_CSR_DIVEXT_MASK) >> + SCG_CSR_DIVEXT_SHIFT; + + div += 1; + return freq / div; + } + break; + + case CLK_SLOW: + { + freq = rv32m1_corefreq(); + div = (getreg32(RV32M1_SCG_CSR) & SCG_CSR_DIVSLOW_MASK) >> + SCG_CSR_DIVSLOW_SHIFT; + + div += 1; + return freq / div; + } + break; + + default: + return 0u; + } + + return 0u; +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_clockconfig.h b/arch/risc-v/src/rv32m1/rv32m1_clockconfig.h new file mode 100644 index 00000000000..a45658d7492 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_clockconfig.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_RV32M1_CLOCKCONFIG_H +#define __ARCH_RISCV_SRC_RV32M1_RV32M1_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum clk_e +{ + CLK_SIRC = 0x000, /* Slow IRC Clock */ + CLK_SIRCDIV1, + CLK_SIRCDIV2, + CLK_SIRCDIV3, + + CLK_FIRC = 0x100, /* Fast IRC Clock */ + CLK_FIRCDIV1, + CLK_FIRCDIV2, + CLK_FIRCDIV3, + + CLK_LPFLL = 0x200, /* Low Power FLL Cock */ + CLK_LPFLLDIV1, + CLK_LPFLLDIV2, + CLK_LPFLLDIV3, + + CLK_SOSC = 0x300, /* System Oscillator Clock */ + CLK_SOSCDIV1, + CLK_SOSCDIV2, + CLK_SOSCDIV3, + + CLK_LPOC = 0x400, /* LPO Clock */ + CLK_ROSC = 0x500, /* RTC Clock */ + + CLK_CORE = 0x600, + CLK_PLAT, + CLK_SYS, + + CLK_BUS = 0x700, + CLK_EXT = 0x800, + CLK_SLOW = 0x900, +}; + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +EXTERN void rv32m1_clockconfig(void); +EXTERN unsigned rv32m1_clockfreq(enum clk_e clk); + +#if defined(__cplusplus) +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_CLOCKCONFIG_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_delay.c b/arch/risc-v/src/rv32m1/rv32m1_delay.c new file mode 100644 index 00000000000..7a9d1c700c7 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_delay.c @@ -0,0 +1,236 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_delay.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "rv32m1.h" +#include "rv32m1_timersvc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10) +#define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) +#define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) + +/**************************************************************************** + * Data Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_sw_mdelay + * + * Description: + * Delay inline for the requested number of milliseconds in software + * way. The codes are copies of built-in up_mdelay. + * + ****************************************************************************/ + +static void up_sw_mdelay(unsigned int milliseconds) +{ + volatile unsigned int i; + volatile unsigned int j; + + for (i = 0; i < milliseconds; i++) + { + for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) + { + } + } +} + +/**************************************************************************** + * Name: up_sw_udelay + * + * Description: + * Delay inline for the requested number of microseconds in software + * way. The codes are copies of built-in up_udelay. + * + ****************************************************************************/ + +static void up_sw_udelay(unsigned int microseconds) +{ + volatile int i; + + /* We'll do this a little at a time because we expect that the + * CONFIG_BOARD_LOOPSPERUSEC is very inaccurate during to truncation in + * the divisions of its calculation. We'll use the largest values that + * we can in order to prevent significant error buildup in the loops. + */ + + while (microseconds > 1000) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++) + { + } + + microseconds -= 1000; + } + + while (microseconds > 100) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++) + { + } + + microseconds -= 100; + } + + while (microseconds > 10) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++) + { + } + + microseconds -= 10; + } + + while (microseconds > 0) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++) + { + } + + microseconds--; + } +} + +/**************************************************************************** + * Name: up_hw_delay + ****************************************************************************/ + +static void up_hw_delay(unsigned int period, unsigned int unit, + unsigned int ticks) +{ + uint32_t t; + uint32_t elapsed; + + /* The current value of timer */ + + uint32_t cval = rv32m1_timersvc_value(); + + /* The last value of timer */ + + uint32_t lval = cval; + + elapsed = 0; + + while (ticks > 0) + { + cval = rv32m1_timersvc_value(); + + if (cval != lval) + { + /* Accumulate the elapsed time */ + + elapsed += lval < cval ? cval - lval : cval + period - lval; + lval = cval; + + if (elapsed >= unit) + { + t = elapsed / unit; + elapsed -= t * unit; + + ticks -= t < ticks ? t : ticks; + } + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_mdelay + * + * Description: + * Delay inline for the requested number of milliseconds. + * System Clock Frequency of RV32M1 is variable, the built-in + * up_mdelay doesn't work very well for this chip. A Timer + * Service facilitates the delay function to get better accuracy. + * + * *** NOT multi-tasking friendly *** + * + ****************************************************************************/ + +void up_mdelay(unsigned int milliseconds) +{ + uint32_t freq = rv32m1_timersvc_freq(); + uint32_t period = rv32m1_timersvc_period(); + + /* When Timer Service is up, and its frequency isn't less than 1KHz, + * the granularity of Timer Service can provide 1 ms accuracy. In + * other cases, sofware delay timer is preferred. + */ + + if (!rv32m1_timersvc_up() || freq < 1000u || !period) + { + up_sw_mdelay(milliseconds); + } + else + { + up_hw_delay(period, freq / 1000u, milliseconds); + } +} + +/**************************************************************************** + * Name: up_udelay + * + * Description: + * Delay inline for the requested number of microseconds. + * System Clock Frequency of RV32M1 is variable, the built-in + * up_udelay doesn't work very well for this chip. A Timer + * Service facilitates the delay function to get better accuracy. + * + * *** NOT multi-tasking friendly *** + * + ****************************************************************************/ + +void up_udelay(useconds_t microseconds) +{ + uint32_t freq = rv32m1_timersvc_freq(); + uint32_t period = rv32m1_timersvc_period(); + + /* When Timer Service is up, and its frequency isn't less than 1MHz, + * the granularity of Timer Service can provide 1 us accuracy. In + * other cases, sofware delay timer is preferred. + */ + + if (!rv32m1_timersvc_up() || freq < 1000000u || !period) + { + up_sw_udelay(microseconds); + } + else + { + up_hw_delay(period, freq / 1000000u, microseconds); + } +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_gpio.c b/arch/risc-v/src/rv32m1/rv32m1_gpio.c new file mode 100644 index 00000000000..6b71e34058f --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_gpio.c @@ -0,0 +1,798 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "riscv_arch.h" +#include "chip.h" +#include "hardware/rv32m1_port.h" +#include "hardware/rv32m1_gpio.h" +#include "rv32m1_pcc.h" +#include "rv32m1_gpio.h" + +/**************************************************************************** + * Pre-Processor Declarations + ****************************************************************************/ + +#define RV32M1_NGPIO_PORTS 5 + +/**************************************************************************** + * Data Type Definition + ****************************************************************************/ + +struct rv32m1_ctrlbase_s +{ + const uint32_t portbase; /* Port Configure Base */ + const uint32_t gpiobase; /* GPIO Configure Base */ + const uint32_t portgate; /* Port Clock Control Gate */ + const uint32_t gpiogate; /* GPIO Clock Control Gate */ + const uint32_t irq; /* IRQ Number */ + FAR sq_queue_t *isrchain; /* Interrupt Service Routine Chain */ +}; + +struct rv32m1_isr_s +{ + sq_entry_t link; + xcpt_t isr; + FAR void *arg; + uint32_t pin; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if RV32M1_NGPIO_PORTS > 0 +static sq_queue_t g_porta_isrchain = +{ + .head = NULL, + .tail = NULL +}; +#endif +#if RV32M1_NGPIO_PORTS > 1 +static sq_queue_t g_portb_isrchain = +{ + .head = NULL, + .tail = NULL +}; +#endif +#if RV32M1_NGPIO_PORTS > 2 +static sq_queue_t g_portc_isrchain = +{ + .head = NULL, + .tail = NULL +}; +#endif +#if RV32M1_NGPIO_PORTS > 3 +static sq_queue_t g_portd_isrchain = +{ + .head = NULL, + .tail = NULL +}; +#endif +#if RV32M1_NGPIO_PORTS > 4 +static sq_queue_t g_porte_isrchain = +{ + .head = NULL, + .tail = NULL +}; +#endif + +/* Base addresses for each GPIO block */ + +static struct rv32m1_ctrlbase_s g_ctrlbase[RV32M1_NGPIO_PORTS] = +{ +#if RV32M1_NGPIO_PORTS > 0 + { + .portbase = RV32M1_PORTA_BASE, + .gpiobase = RV32M1_GPIOA_BASE, + .portgate = RV32M1_PCC_PORTA, + .gpiogate = 0, + .irq = RV32M1_IRQ_PORTA, + .isrchain = &g_porta_isrchain, + }, +#endif +#if RV32M1_NGPIO_PORTS > 1 + { + .portbase = RV32M1_PORTB_BASE, + .gpiobase = RV32M1_GPIOB_BASE, + .portgate = RV32M1_PCC_PORTB, + .gpiogate = 0, + .irq = RV32M1_IRQ_PORTB, + .isrchain = &g_portb_isrchain, + }, +#endif +#if RV32M1_NGPIO_PORTS > 2 + { + .portbase = RV32M1_PORTC_BASE, + .gpiobase = RV32M1_GPIOC_BASE, + .portgate = RV32M1_PCC_PORTC, + .gpiogate = 0, + .irq = RV32M1_IRQ_PORTC, + .isrchain = &g_portc_isrchain, + }, +#endif +#if RV32M1_NGPIO_PORTS > 3 + { + .portbase = RV32M1_PORTD_BASE, + .gpiobase = RV32M1_GPIOD_BASE, + .portgate = RV32M1_PCC_PORTD, + .gpiogate = 0, + .irq = RV32M1_IRQ_PORTD, + .isrchain = &g_portd_isrchain, + }, +#endif +#if RV32M1_NGPIO_PORTS > 4 + { + .portbase = RV32M1_PORTE_BASE, + .gpiobase = RV32M1_GPIOE_BASE, + .portgate = RV32M1_PCC_PORTE, + .gpiogate = RV32M1_PCC_GPIOE, + .irq = RV32M1_IRQ_PORTE, + .isrchain = &g_porte_isrchain, + }, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_modifyreg32 + ****************************************************************************/ + +static inline void rv32m1_modifyreg32(uint32_t addr, uint32_t bitclr, + uint32_t bitset) +{ + uint32_t regval = getreg32(addr); + regval &= ~bitclr; + regval |= bitset; + putreg32(regval, addr); +} + +/**************************************************************************** + * Name: rv32m1_gpio_irqconfig + ****************************************************************************/ + +static void rv32m1_gpio_irqconfig(uint32_t cfgset) +{ + uint32_t portbase; + + unsigned int port; + unsigned int pin; + + uint32_t irqc; + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + + /* Get the port base address */ + + portbase = g_ctrlbase[port].portbase; + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + irqc = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT; + + /* Write '1' to clear Interrupt flag */ + + putreg32(pin << 1, portbase + RV32M1_PORT_ISFR_OFFSET); + + rv32m1_modifyreg32(portbase + (pin << 2), PORT_PCR_IRQC_MASK, + (irqc << PORT_PCR_IRQC_SHIFT) & PORT_PCR_IRQC_MASK); +} + +/**************************************************************************** + * Name: rv32m1_gpio_portconfig + ****************************************************************************/ + +static void rv32m1_gpio_portconfig(uint32_t cfgset) +{ + uint32_t portbase; + + unsigned int port; + unsigned int pin; + + uint32_t regval; + uint32_t cfg; + + /* No Sanity check of port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + + /* Get the port base address */ + + portbase = g_ctrlbase[port].portbase; + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + regval = getreg32(portbase + (pin << 2)); + + cfg = cfgset & GPIO_PUPD_MASK; + + if (cfg == GPIO_FLOAT) + { + /* Float */ + + regval &= ~PORT_PCR_PE; + } + else + { + /* Pull Enable */ + + regval |= PORT_PCR_PE; + + if (cfg == GPIO_PULLUP) + { + /* Pull Up */ + + regval |= PORT_PCR_PS; + } + else + { + /* Pull Down */ + + regval &= ~PORT_PCR_PS; + } + } + + if (cfgset & GPIO_OPENDRAIN) + { + /* Open Drain Enable */ + + regval |= PORT_PCR_ODE; + } + else + { + /* Open Drain Disable */ + + regval &= ~PORT_PCR_ODE; + } + + if (cfgset & GPIO_FILTER) + { + /* Passive Filter Enable */ + + regval |= PORT_PCR_PFE; + } + else + { + /* Passive Filter Disable */ + + regval &= ~PORT_PCR_PFE; + } + + if (cfgset & GPIO_SSR) + { + /* Slow Slew Rate Enable */ + + regval |= PORT_PCR_SRE; + } + else + { + /* Fast Slew Rate Enable */ + + regval &= ~PORT_PCR_SRE; + } + + putreg32(regval, portbase + (pin << 2)); +} + +/**************************************************************************** + * Name: rv32m1_gpio_interrupt + ****************************************************************************/ + +LOCATE_ITCM +static int rv32m1_gpio_interrupt(int irq, FAR void *context, FAR void *arg) +{ + const FAR struct rv32m1_ctrlbase_s *ctrl; + const FAR sq_queue_t *isrchain; + const FAR sq_entry_t *e; + const FAR struct rv32m1_isr_s *priv; + + uint32_t portbase; + + uint32_t risf; /* the Read([red]) Interrupt status Flag */ + uint32_t wisf; /* The Interrupt status Flag to write back */ + + ctrl = (const FAR struct rv32m1_ctrlbase_s *)arg; + portbase = ctrl->portbase; + isrchain = ctrl->isrchain; + + risf = getreg32(portbase + RV32M1_PORT_ISFR_OFFSET); + wisf = 0; + + /* Enumerate gpio isr chain to dispatch services */ + + e = sq_peek(isrchain); + while (e) + { + priv = container_of(e, const struct rv32m1_isr_s, link); + + /* Dispatch services to whom has subcribed(registered) the + * corresponding pin. + */ + + if (risf & (1 << priv->pin)) + { + wisf |= 1 << priv->pin; + + /* Double check isr to avoid System Crash */ + + if (priv->isr) + { + priv->isr(irq, context, priv->arg); + } + } + + e = sq_next(e); + } + + /* Write '1' to clear corresponding Interrupt Status bit Flag */ + + putreg32(wisf, portbase + RV32M1_PORT_ISFR_OFFSET); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_gpio_config + ****************************************************************************/ + +int rv32m1_gpio_config(uint32_t cfgset) +{ + uint32_t gpiobase; + uint32_t portbase; + unsigned int port; + unsigned int pin; + unsigned int mode; + + irqstate_t flags; + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return -EINVAL; + } + + /* Get the gpio and port base address */ + + gpiobase = g_ctrlbase[port].gpiobase; + portbase = g_ctrlbase[port].portbase; + + /* Get the pin number and select the port configuration register for that + * pin + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Interrupts must be disabled from here on out so that we have mutually + * exclusive access to all of the GPIO configuration registers. + */ + + flags = enter_critical_section(); + + rv32m1_pcc_clock_enable(g_ctrlbase[port].portgate); + + /* Open the GPIO GATE if required */ + + if (g_ctrlbase[port].gpiogate) + { + rv32m1_pcc_clock_enable(g_ctrlbase[port].gpiogate); + } + + /* Cofigure Open Drain, Pull Up/Down, Filter and Slew Rate abilities */ + + rv32m1_gpio_portconfig(cfgset); + + mode = cfgset & GPIO_MODE_MASK; + + if (mode == GPIO_INPUT) + { + rv32m1_modifyreg32(portbase + (pin << 2), PORT_PCR_MUX_MASK, + PORT_PCR_MUX_GPIO); + rv32m1_modifyreg32(gpiobase + RV32M1_GPIO_PDDR_OFFSET, 1 << pin, 0); + + /* Always configure the irq on this pin, even if the irq configure + * could be None. + */ + + rv32m1_gpio_irqconfig(cfgset); + } + else if (mode == GPIO_OUTPUT) + { + rv32m1_modifyreg32(portbase + (pin << 2), PORT_PCR_MUX_MASK, + PORT_PCR_MUX_GPIO); + rv32m1_modifyreg32(gpiobase + RV32M1_GPIO_PDDR_OFFSET, 0, 1 << pin); + + /* Initialize the output value */ + + if (cfgset & GPIO_OUTPUT_SET) + { + putreg32(1 << pin, gpiobase + RV32M1_GPIO_PSOR_OFFSET); + } + else + { + putreg32(1 << pin, gpiobase + RV32M1_GPIO_PCOR_OFFSET); + } + } + else + { + uint32_t alt = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT; + + rv32m1_modifyreg32(portbase + (pin << 2), PORT_PCR_MUX_MASK, + (alt << PORT_PCR_MUX_SHIFT) & PORT_PCR_MUX_MASK); + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: rv32m1_gpio_write + ****************************************************************************/ + +void rv32m1_gpio_write(uint32_t cfgset, bool value) +{ + uint32_t gpiobase; + unsigned int port; + unsigned int pin; + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return ; + } + + /* Get the gpio base address */ + + gpiobase = g_ctrlbase[port].gpiobase; + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + if (value) + { + putreg32(1 << pin, gpiobase + RV32M1_GPIO_PSOR_OFFSET); + } + else + { + putreg32(1 << pin, gpiobase + RV32M1_GPIO_PCOR_OFFSET); + } +} + +/**************************************************************************** + * Name: rv32m1_gpio_toggle + ****************************************************************************/ + +void rv32m1_gpio_toggle(uint32_t cfgset) +{ + uint32_t gpiobase; + unsigned int port; + unsigned int pin; + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return ; + } + + /* Get the gpio base address */ + + gpiobase = g_ctrlbase[port].gpiobase; + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + putreg32(1 << pin, gpiobase + RV32M1_GPIO_PTOR_OFFSET); +} + +/**************************************************************************** + * Name: rv32m1_gpio_read + ****************************************************************************/ + +bool rv32m1_gpio_read(uint32_t cfgset) +{ + uint32_t gpiobase; + unsigned int port; + unsigned int pin; + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return false; + } + + /* Get the gpio base address */ + + gpiobase = g_ctrlbase[port].gpiobase; + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + return (getreg32(gpiobase + RV32M1_GPIO_PDIR_OFFSET) & (1 << pin)) != 0; +} + +/**************************************************************************** + * Name: rv32m1_gpio_irqenable + ****************************************************************************/ + +void rv32m1_gpio_irqenable(uint32_t cfgset) +{ + uint32_t irq; + unsigned int port; + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return ; + } + + /* Get the irq */ + + irq = g_ctrlbase[port].irq; + + /* Configure the irq on the pin */ + + rv32m1_gpio_irqconfig(cfgset); + + up_enable_irq(irq); +} + +/**************************************************************************** + * Name: rv32m1_gpio_irqdisable + ****************************************************************************/ + +void rv32m1_gpio_irqdisable(uint32_t cfgset) +{ + uint32_t portbase; + unsigned int port; + unsigned int pin; + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return ; + } + + /* Get the port base address */ + + portbase = g_ctrlbase[port].portbase; + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + rv32m1_modifyreg32(portbase + (pin << 2), PORT_PCR_IRQC_MASK, 0); +} + +/**************************************************************************** + * Name: rv32m1_gpio_irqattach + ****************************************************************************/ + +int rv32m1_gpio_irqattach(uint32_t cfgset, xcpt_t isr, FAR void *arg) +{ + unsigned int port; + unsigned int pin; + uint32_t irq; + + int ret; + + irqstate_t flags; + + FAR sq_queue_t *isrchain; + FAR sq_entry_t *e; + + FAR struct rv32m1_isr_s *priv; + + if (!isr) + { + return -EINVAL; + } + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return -EINVAL; + } + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + isrchain = g_ctrlbase[port].isrchain; + irq = g_ctrlbase[port].irq; + + flags = enter_critical_section(); + + e = sq_peek(isrchain); + while (e) + { + priv = container_of(e, struct rv32m1_isr_s, link); + if (priv->isr == isr && priv->pin == pin && priv->arg == arg) + { + /* The isr has been one 'link' of Chain */ + + ret = 0; + goto done; + } + + e = sq_next(e); + } + + priv = (FAR struct rv32m1_isr_s *)kmm_malloc(sizeof(*priv)); + if (priv) + { + /* If it is the first time to attach an isr, the generic gpio + * isr has to be attached. + */ + + if (!sq_peek(isrchain)) + { + irq_attach(irq, rv32m1_gpio_interrupt, &g_ctrlbase[port]); + } + + priv->isr = isr; + priv->arg = arg; + priv->pin = pin; + + /* Append the new isr to Chain */ + + sq_addlast(&priv->link, isrchain); + + ret = 0; + } + else + { + ret = -ENOMEM; + } + +done: + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: rv32m1_gpio_irqdetach + ****************************************************************************/ + +int rv32m1_gpio_irqdetach(uint32_t cfgset, xcpt_t isr, FAR void *arg) +{ + uint32_t port; + uint32_t pin; + + int ret = -1; + + irqstate_t flags; + + FAR sq_queue_t *isrchain; + FAR sq_entry_t *cur; + FAR sq_entry_t *pre; + + FAR struct rv32m1_isr_s *priv; + + if (!isr) + { + return -EINVAL; + } + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return -EINVAL; + } + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Get the isr chain */ + + isrchain = g_ctrlbase[port].isrchain; + + flags = enter_critical_section(); + + pre = NULL; + cur = sq_peek(isrchain); + while (cur) + { + priv = container_of(cur, struct rv32m1_isr_s, link); + if (priv->isr == isr && priv->pin == pin && priv->arg == arg) + { + if (pre) + { + sq_remafter(pre, isrchain); + cur = pre; + } + else + { + sq_remfirst(isrchain); + cur = NULL; + } + + /* Return back resources */ + + kmm_free(priv); + + ret = 0; + } + + pre = cur; + cur = cur ? sq_next(cur) : sq_peek(isrchain); + } + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: rv32m1_gpio_clearpending + ****************************************************************************/ + +void rv32m1_gpio_clearpending(uint32_t cfgset) +{ + uint32_t portbase; + unsigned int port; + unsigned int pin; + + /* Verify that this hardware supports the selected GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= RV32M1_NGPIO_PORTS) + { + return; + } + + /* Get the port base address */ + + portbase = g_ctrlbase[port].portbase; + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Write '1' to clear corresponding Interrupt Status bit Flag */ + + putreg32(1 << pin, portbase + RV32M1_PORT_ISFR_OFFSET); +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_gpio.h b/arch/risc-v/src/rv32m1/rv32m1_gpio.h new file mode 100644 index 00000000000..905eceda971 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_gpio.h @@ -0,0 +1,304 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_RV32M1_GPIO_H +#define __ARCH_RISCV_SRC_RV32M1_RV32M1_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "riscv_internal.h" +#include "chip.h" +#include "hardware/rv32m1_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Each port bit of the general-purpose I/O (GPIO) ports can be + * individually configured by software in several modes: + * + * - Input floating + * - Input pull-up + * - Input-pull-down + * - Output open-drain with pull-up or pull-down capability + * - Output push-pull with pull-up or pull-down capability + * - Alternate function push-pull with pull-up or pull-down capability + * - Alternate function open-drain with pull-up or pull-down capability + * - Analog + * + * 20-bit Encoding: 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * Inputs: MMUU IIII FS.. PPPB BBBB + * Outputs: MMUU .... FSOV PPPB BBBB + * Alternate Functions: MMUU AAAA FSO. PPPB BBBB + * Analog: MM.. .... FS.. PPPB BBBB + */ + +/* Mode: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * MM.. .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ +# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ + +/* Input/output pull-ups/downs (not used with analog): + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * ..UU .... .... .... .... + */ + +#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */ +#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT) +# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */ +# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */ +# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */ + +/* Alternate Functions: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... AAAA .... .... .... + */ + +#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */ +#define GPIO_AF_MASK (7 << GPIO_AF_SHIFT) +# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) +# define GPIO_AF0 (0 << GPIO_AF_SHIFT) /* Analog */ +# define GPIO_AF1 (1 << GPIO_AF_SHIFT) /* GPIO */ +# define GPIO_AF2 (2 << GPIO_AF_SHIFT) +# define GPIO_AF3 (3 << GPIO_AF_SHIFT) +# define GPIO_AF4 (4 << GPIO_AF_SHIFT) +# define GPIO_AF5 (5 << GPIO_AF_SHIFT) +# define GPIO_AF6 (6 << GPIO_AF_SHIFT) +# define GPIO_AF7 (7 << GPIO_AF_SHIFT) + +/* Interrupt for Input pins only: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... IIII .... .... .... + */ + +#define GPIO_INT_SHIFT (12) +#define GPIO_INT_MASK (0xf << GPIO_INT_SHIFT) +#define GPIO_INT_NONE (0 << GPIO_INT_SHIFT) +#define GPIO_INT_LOW (8 << GPIO_INT_SHIFT) +#define GPIO_INT_RISE (9 << GPIO_INT_SHIFT) +#define GPIO_INT_FALL (10 << GPIO_INT_SHIFT) +#define GPIO_INT_EDGE (11 << GPIO_INT_SHIFT) +#define GPIO_INT_HIGH (12 << GPIO_INT_SHIFT) + +/* Passive Filter Enable: + * + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... F... .... .... + */ + +#define GPIO_FILTER (1 << 11) /* Bit11: 1=Passive Filter Enable */ + +/* Slow Slew Rate Enable (Default Fast Slew Rate): + * + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .S.. .... .... + */ + +#define GPIO_SSR (1 << 10) /* Bit10: 1=Slow Slew rate, 0=Fast Slew Rate */ + +/* Output/Alt function type selection: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ..O. .... .... + */ + +#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */ + +/* If the pin is a GPIO digital output, then this identifies the initial + * output value. If the pin is an input, this bit is overloaded to + * provide the qualifier to distinguish input pull-up and -down: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ...V .... .... + */ + +#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */ +#define GPIO_OUTPUT_CLEAR (0) + +/* This identifies the GPIO port: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .... PPP. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ +# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ +# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ +# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ +# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ + +/* This identifies the bit in the port: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .... ...B BBBB + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: rv32m1_gpio_config + ****************************************************************************/ + +EXTERN int rv32m1_gpio_config(uint32_t cfgset); + +/**************************************************************************** + * Name: rv32m1_gpio_write + ****************************************************************************/ + +EXTERN void rv32m1_gpio_write(uint32_t cfgset, bool value); + +/**************************************************************************** + * Name: rv32m1_gpio_toggle + ****************************************************************************/ + +EXTERN void rv32m1_gpio_toggle(uint32_t cfgset); + +/**************************************************************************** + * Name: rv32m1_gpio_read + ****************************************************************************/ + +EXTERN bool rv32m1_gpio_read(uint32_t cfgset); + +/**************************************************************************** + * Name: rv32m1_gpio_irqenable + ****************************************************************************/ + +EXTERN void rv32m1_gpio_irqenable(uint32_t cfgset); + +/**************************************************************************** + * Name: rv32m1_gpio_irqdisable + ****************************************************************************/ + +EXTERN void rv32m1_gpio_irqdisable(uint32_t cfgset); + +/**************************************************************************** + * Name: rv32m1_gpio_irqattach + ****************************************************************************/ + +EXTERN int rv32m1_gpio_irqattach(uint32_t cfgset, xcpt_t isr, FAR void *arg); + +/**************************************************************************** + * Name: rv32m1_gpio_irqdetach + ****************************************************************************/ + +EXTERN int rv32m1_gpio_irqdetach(uint32_t cfgset, xcpt_t isr, FAR void *arg); + +/**************************************************************************** + * Name: rv32m1_gpio_clearpending + ****************************************************************************/ + +EXTERN void rv32m1_gpio_clearpending(uint32_t cfgset); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_GPIO_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_head.S b/arch/risc-v/src/rv32m1/rv32m1_head.S new file mode 100644 index 00000000000..9663b398eac --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_head.S @@ -0,0 +1,237 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_head.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + /* Exported Symbols */ + + .global exception_common + .global __start + + .section .text + +__start: + + /* Set stack pointer to the idle thread stack */ + + lui sp, %hi(RV32M1_IDLESTACK_TOP) + addi sp, sp, %lo(RV32M1_IDLESTACK_TOP) + + /* Disable all interrupts (i.e. timer, external) in mie */ + + csrci mstatus, 0x8 + csrw mie, zero + + /* Initialize the Machine Trap Vector */ + + lui t0, %hi(_svector) + addi t0, t0, %lo(_svector) + csrw mtvec, t0 + + /* Jump to __rv32m1_start */ + + jal x1, __rv32m1_start + + /* We shouldn't return from __rv32m1_start */ + + .global _init + .global _fini + +_init: +_fini: + + /* These don't have to do anything since we use init_array/fini_array. */ + + ret + +/**************************************************************************** + * Name: exception_common + ****************************************************************************/ + +#ifdef CONFIG_RV32M1_ITCM + .section SECTION_ITCM +#endif + +exception_common: + + addi sp, sp, -XCPTCONTEXT_SIZE + + sw x1, 1*4(sp) /* ra */ + sw x3, 3*4(sp) /* gp */ + sw x4, 4*4(sp) /* tp */ + sw x5, 5*4(sp) /* t0 */ + sw x6, 6*4(sp) /* t1 */ + sw x7, 7*4(sp) /* t2 */ + sw x8, 8*4(sp) /* s0 */ + sw x9, 9*4(sp) /* s1 */ + sw x10, 10*4(sp) /* a0 */ + sw x11, 11*4(sp) /* a1 */ + sw x12, 12*4(sp) /* a2 */ + sw x13, 13*4(sp) /* a3 */ + sw x14, 14*4(sp) /* a4 */ + sw x15, 15*4(sp) /* a5 */ + sw x16, 16*4(sp) /* a6 */ + sw x17, 17*4(sp) /* a7 */ + sw x18, 18*4(sp) /* s2 */ + sw x19, 19*4(sp) /* s3 */ + sw x20, 20*4(sp) /* s4 */ + sw x21, 21*4(sp) /* s5 */ + sw x22, 22*4(sp) /* s6 */ + sw x23, 23*4(sp) /* s7 */ + sw x24, 24*4(sp) /* s8 */ + sw x25, 25*4(sp) /* s9 */ + sw x26, 26*4(sp) /* s10 */ + sw x27, 27*4(sp) /* s11 */ + sw x28, 28*4(sp) /* t3 */ + sw x29, 29*4(sp) /* t4 */ + sw x30, 30*4(sp) /* t5 */ + sw x31, 31*4(sp) /* t6 */ + +#if defined(INT_XCPT_REGS) && INT_XCPT_REGS >= 39 + csrr x28, 0x7b0 + csrr x29, 0x7b1 + csrr x30, 0x7b2 + sw x28, 33*4(sp) + sw x29, 34*4(sp) + sw x30, 35*4(sp) + csrr x28, 0x7b4 + csrr x29, 0x7b5 + csrr x30, 0x7b6 + sw x28, 36*4(sp) + sw x29, 37*4(sp) + sw x30, 38*4(sp) +#endif + + csrr s0, mstatus + sw s0, 32*4(sp) /* mstatus */ + + addi s0, sp, XCPTCONTEXT_SIZE + sw s0, 2*4(sp) /* original SP */ + + /* Setup arg0(exception cause), arg1(context) */ + + csrr a0, mcause /* exception cause */ + csrr s0, mepc + sw s0, 0(sp) /* exception PC */ + + mv a1, sp /* context = sp */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 + /* Switch to interrupt stack */ + + lui sp, %hi(g_intstacktop) + addi sp, sp, %lo(g_intstacktop) +#endif + + /* Call interrupt handler in C */ + + jal x1, rv32m1_dispatch_irq + + /* If context switch is needed, return a new sp */ + + mv sp, a0 + lw s0, 0(sp) /* restore mepc */ + csrw mepc, s0 + + lw s0, 32*4(sp) /* restore mstatus */ + csrw mstatus, s0 + +#if defined(INT_XCPT_REGS) && INT_XCPT_REGS >= 39 + lw x28, 36*4(sp) + lw x29, 37*4(sp) + lw x30, 38*4(sp) + csrrw x0, 0x7b4, x28 + csrrw x0, 0x7b5, x29 + csrrw x0, 0x7b6, x30 + lw x28, 33*4(sp) + lw x29, 34*4(sp) + lw x30, 35*4(sp) + csrrw x0, 0x7b0, x28 + csrrw x0, 0x7b1, x29 + csrrw x0, 0x7b2, x30 +#endif + + lw x3, 3*4(sp) /* gp */ + lw x4, 4*4(sp) /* tp */ + lw x5, 5*4(sp) /* t0 */ + lw x6, 6*4(sp) /* t1 */ + lw x7, 7*4(sp) /* t2 */ + lw x8, 8*4(sp) /* s0 */ + lw x9, 9*4(sp) /* s1 */ + lw x10, 10*4(sp) /* a0 */ + lw x11, 11*4(sp) /* a1 */ + lw x12, 12*4(sp) /* a2 */ + lw x13, 13*4(sp) /* a3 */ + lw x14, 14*4(sp) /* a4 */ + lw x15, 15*4(sp) /* a5 */ + lw x16, 16*4(sp) /* a6 */ + lw x17, 17*4(sp) /* a7 */ + lw x18, 18*4(sp) /* s2 */ + lw x19, 19*4(sp) /* s3 */ + lw x20, 20*4(sp) /* s4 */ + lw x21, 21*4(sp) /* s5 */ + lw x22, 22*4(sp) /* s6 */ + lw x23, 23*4(sp) /* s7 */ + lw x24, 24*4(sp) /* s8 */ + lw x25, 25*4(sp) /* s9 */ + lw x26, 26*4(sp) /* s10 */ + lw x27, 27*4(sp) /* s11 */ + lw x28, 28*4(sp) /* t3 */ + lw x29, 29*4(sp) /* t4 */ + lw x30, 30*4(sp) /* t5 */ + lw x31, 31*4(sp) /* t6 */ + + lw x1, 1*4(sp) /* ra */ + + lw sp, 2*4(sp) /* restore original sp */ + + /* Return from Machine Interrupt */ + + mret + +/******************************************************************************* + * Name: g_intstackalloc and g_intstacktop +*******************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 + .bss + .balign 16 + .global g_intstackalloc + .global g_intstacktop + .type g_intstackalloc, object + .type g_intstacktop, object +g_intstackalloc: + .skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15) +g_intstacktop: + .skip 4 + .size g_intstacktop, 4 + .size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15) +#endif diff --git a/arch/risc-v/src/rv32m1/rv32m1_idle.c b/arch/risc-v/src/rv32m1/rv32m1_idle.c new file mode 100644 index 00000000000..cb298865182 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_idle.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "riscv_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when there is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + board_autoled_off(LED_CPU); + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + asm("WFI"); + +#endif +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_irq.c b/arch/risc-v/src/rv32m1/rv32m1_irq.c new file mode 100644 index 00000000000..b09abf45847 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_irq.c @@ -0,0 +1,271 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "riscv_internal.h" +#include "riscv_arch.h" + +#include "rv32m1.h" +#include "hardware/rv32m1_eu.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_intmuxisr + ****************************************************************************/ + +LOCATE_ITCM +static int rv32m1_intmuxisr(int irq, void *context, FAR void *arg) +{ + UNUSED(irq); + UNUSED(context); + UNUSED(arg); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + int i; + uint32_t base; + uint32_t regval; + uint32_t regaddr; + + /* Disable Machine interrupts */ + + up_irq_save(); + + rv32m1_pcc_clock_enable(RV32M1_PCC_INTMUX0); + + /* reset all the intmux channels */ + + for (i = 0; i < 8; ++i) + { + base = RV32M1_INTMUX_CH_BASE(i); + regaddr = base + INTMUX_CH_CSR_OFFSET; + regval = getreg32(regaddr); + regval |= INTMUX_CSR_RST; + putreg32(regval, regaddr); + } + + /* Disable all global interrupts */ + + putreg32(0, RV32M1_EU_INTPTEN); + + /* Colorize the interrupt stack for debug purposes */ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); + riscv_stack_color((FAR void *)((uintptr_t)&g_intstacktop - intstack_size), + intstack_size); +#endif + + /* Clear all pending flags */ + + putreg32(0xffffffff, RV32M1_EU_INTPTPENDCLR); + putreg32(0xffffffff, RV32M1_EU_EVTPENDCLR); + putreg32(0xffffffff, RV32M1_EU_INTPTSECURE); + + /* Attach INTMUX ISR */ + + irq_attach(RV32M1_IRQ_INTMUX0, rv32m1_intmuxisr, NULL); + + /* currents_regs is non-NULL only while processing an interrupt */ + + g_current_regs = NULL; + + /* Attach the ecall interrupt handler */ + + irq_attach(RV32M1_IRQ_ECALL_M, riscv_swint, NULL); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +LOCATE_ITCM +void up_disable_irq(int irq) +{ + int extirq; + uint32_t regval; + + if (irq >= RV32M1_IRQ_MEXT) + { + if (irq >= RV32M1_IRQ_INTMUX) + { + int const subirq = irq - RV32M1_IRQ_INTMUX; + int const chn = 0; + uint32_t regaddr = RV32M1_INTMUX_CH_BASE(chn) + + INTMUX_CH_IER_OFFSET; + + regval = getreg32(regaddr); + regval &= ~(1 << subirq); + putreg32(regval, regaddr); + } + else + { + extirq = irq - RV32M1_IRQ_MEXT; + + /* Clear enable bit for the irq */ + + regval = getreg32(RV32M1_EU_INTPTEN); + regval &= ~(1 << extirq); + putreg32(regval, RV32M1_EU_INTPTEN); + } + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +LOCATE_ITCM +void up_enable_irq(int irq) +{ + int extirq; + uint32_t regval; + + if (irq >= RV32M1_IRQ_MEXT) + { + if (irq >= RV32M1_IRQ_INTMUX) + { + int const subirq = irq - RV32M1_IRQ_INTMUX; + int const chn = 0; + uint32_t regaddr = RV32M1_INTMUX_CH_BASE(chn) + + INTMUX_CH_IER_OFFSET; + + regval = getreg32(regaddr); + regval |= 1 << subirq; + putreg32(regval, regaddr); + + extirq = RV32M1_IRQ_INTMUX0 - RV32M1_IRQ_MEXT; + } + else + { + extirq = irq - RV32M1_IRQ_MEXT; + } + + regval = getreg32(RV32M1_EU_INTPTEN); + + /* Set enable bit for the irq */ + + regval |= 1 << extirq; + putreg32(regval, RV32M1_EU_INTPTEN); + + /* Read INTPTEN back to make it sure */ + + (void)getreg32(RV32M1_EU_INTPTEN); + } +} + +/**************************************************************************** + * Name: riscv_get_newintctx + * + * Description: + * Return initial mstatus when a task is created. + * + ****************************************************************************/ + +uint32_t riscv_get_newintctx(void) +{ + /* Set machine previous privilege mode to machine mode. + * Also set machine previous interrupt enable + */ + + return (MSTATUS_MPPM | MSTATUS_MPIE); +} + +/**************************************************************************** + * Name: riscv_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void riscv_ack_irq(int irq) +{ + board_autoled_on(LED_CPU); +} + +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Return the current interrupt state and enable interrupts + * + ****************************************************************************/ + +irqstate_t up_irq_enable(void) +{ + uint32_t oldstat; + +#if 1 + /* Enable MEIE (machine external interrupt enable) */ + + /* TODO: should move to up_enable_irq() */ + + asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE)); +#endif + + /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ + + asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE)); + return oldstat; +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c b/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c new file mode 100644 index 00000000000..aba75551a48 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c @@ -0,0 +1,145 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "riscv_internal.h" + +#include "rv32m1.h" +#include "hardware/rv32m1_eu.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t * g_current_regs; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * rv32m1_dispatch_irq + ****************************************************************************/ + +LOCATE_ITCM +void *rv32m1_dispatch_irq(uint32_t vector, uint32_t *regs) +{ + int vec = vector & 0x1f; + int irq = (vector >> 27) + vec; + uint32_t *mepc = regs; + + int irqofs = 0; + + /* NOTE: In case of ecall, we need to adjust mepc in the context */ + + if (RV32M1_IRQ_ECALL_M == irq) + { + *mepc += 4; + } + + if (RV32M1_IRQ_INTMUX0 <= irq) + { + uint32_t const chn = irq - RV32M1_IRQ_INTMUX0; + uint32_t regaddr = RV32M1_INTMUX_CH_BASE(chn) + INTMUX_CH_VEC_OFFSET; + uint32_t regval = getreg32(regaddr); + + /* CH_VEC coudle be 0 while INTMUX doesn't latch pending source + * interrupts. In that case a spurious interrupt is being serviced, + * and irq Number shouldn't be compensated. + * + * CH_VEC must be checked to account for spurious interrupts. + */ + + if (regval > 0) + { + /* Register VECN[13:2] = 48 x (CPU Vectors + NVIC Vectors) + + * H(The Highest Interrupt of INTMUX), + * + * 1 CPU Vectors for RV32M1 RISCV Cores. + * No NVIC Vectors for RV32M1 RISCV Cores, + * + * H can be obtained easily: + * H = VECN[13:2] - 48 + * + * H has to be offset by 8 to skip INTMUX0~7. + * + */ + + irqofs = (regval >> 2) - 48 + 8; + irq += irqofs; + } + } + + /* Acknowledge the interrupt */ + + riscv_ack_irq(irq); + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Current regs non-zero indicates that we are processing an interrupt; + * g_current_regs is also used to manage interrupt level context switches. + * + * Nested interrupts are not supported + */ + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + + if (RV32M1_IRQ_MEXT <= irq) + { + irq -= irqofs; + + /* Clear the pending flag */ + + putreg32(1 << vec, RV32M1_EU_INTPTPENDCLR); + } + +#endif + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t *)g_current_regs; + g_current_regs = NULL; + + return regs; +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_linker.h b/arch/risc-v/src/rv32m1/rv32m1_linker.h new file mode 100644 index 00000000000..e92b5664de1 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_linker.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_linker.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_RV32M1_LINKER_H +#define __ARCH_RISCV_SRC_RV32M1_RV32M1_LINKER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_RV32M1_ITCM +# define SECTION_ITCM ".itcm" /* System ITCM */ +# define SECTION_UITCM ".uitcm" /* User ITCM */ +#endif + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LOCATE_ITCM is a recommendation rather than a forced command + * to place codes in Section ITCM. It is effective when RV32M1 + * has ITCM. + */ + +#ifdef CONFIG_RV32M1_ITCM +# define LOCATE_ITCM locate_code(SECTION_ITCM) /* System ITCM */ +# define LOCATE_UITCM locate_code(SECTION_UITCM) /* User ITCM */ +#else +# define LOCATE_ITCM +# define LOCATE_UITCM +#endif + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef CONFIG_RV32M1_ITCM + EXTERN uint32_t _slitcm; /* Start of ITCM LMA */ + EXTERN uint32_t _svitcm; /* Start of ITCM VMA */ + EXTERN uint32_t _evitcm; /* End+1 of ITCM VMA */ + EXTERN uint32_t _suvitcm; /* Start of User ITCM VMA */ + EXTERN uint32_t _euvitcm; /* End+1 of User ITCM VMA */ +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_LINKER_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_lowputc.c b/arch/risc-v/src/rv32m1/rv32m1_lowputc.c new file mode 100644 index 00000000000..72ef51683a6 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_lowputc.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "rv32m1.h" +#include "rv32m1_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: riscv_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void riscv_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + rv32m1_console_uart_putc(ch); +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: rv32m1_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void rv32m1_lowsetup(void) +{ +#if defined(HAVE_UART) + + /* Enable and configure the selected console device */ + +#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + rv32m1_console_uart_setup(); +#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_UART */ +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_lowputc.h b/arch/risc-v/src/rv32m1/rv32m1_lowputc.h new file mode 100644 index 00000000000..4f027c50263 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_lowputc.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_RV32M1_LOWPUTC_H +#define __ARCH_RISCV_SRC_RV32M1_RV32M1_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: rv32m1_lowsetup + ****************************************************************************/ + +EXTERN void rv32m1_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_LOWPUTC_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_memorymap.h b/arch/risc-v/src/rv32m1/rv32m1_memorymap.h new file mode 100644 index 00000000000..efdc818fc6b --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_memorymap.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_RV32M1_MEMORYMAP_H +#define __ARCH_RISCV_SRC_RV32M1_RV32M1_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/rv32m1_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Idle thread stack starts from _ebss */ + +#ifndef __ASSEMBLY__ +#define RV32M1_IDLESTACK_BASE (uint32_t)&_ebss +#else +#define RV32M1_IDLESTACK_BASE _ebss +#endif + +#define RV32M1_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) +#define RV32M1_IDLESTACK_TOP (RV32M1_IDLESTACK_BASE + RV32M1_IDLESTACK_SIZE) + +#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_MEMORYMAP_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_pcc.c b/arch/risc-v/src/rv32m1/rv32m1_pcc.c new file mode 100644 index 00000000000..3eafb17a72d --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_pcc.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_pcc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "riscv_arch.h" +#include "rv32m1_pcc.h" + +/**************************************************************************** + * Pre-Processor Declarations + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_pcc_clock_enable + ****************************************************************************/ + +void rv32m1_pcc_clock_enable(uint32_t regaddr) +{ + uint32_t regval = getreg32(regaddr); + regval |= PCC_CLKCFG_CGC; + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: rv32m1_pcc_clock_disable + ****************************************************************************/ + +void rv32m1_pcc_clock_disable(uint32_t regaddr) +{ + uint32_t regval = getreg32(regaddr); + regval &= ~PCC_CLKCFG_CGC; + putreg32(regval, regaddr); +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_pcc.h b/arch/risc-v/src/rv32m1/rv32m1_pcc.h new file mode 100644 index 00000000000..fb5999ac54b --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_pcc.h @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_pcc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_RV32M1_PCC_H +#define __ARCH_RISCV_SRC_RV32M1_RV32M1_PCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" +#include "hardware/rv32m1_pcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: rv32m1_pcc_clock_enable + ****************************************************************************/ + +EXTERN void rv32m1_pcc_clock_enable(uint32_t regaddr); + +/**************************************************************************** + * Name: rv32m1_pcc_clock_disable + ****************************************************************************/ + +EXTERN void rv32m1_pcc_clock_disable(uint32_t regaddr); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_GPIO_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_serial.c b/arch/risc-v/src/rv32m1/rv32m1_serial.c new file mode 100644 index 00000000000..0c1740b1ae8 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_serial.c @@ -0,0 +1,1184 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include + +#include "riscv_arch.h" +#include "riscv_internal.h" + +#include "chip.h" +#include "rv32m1.h" +#include "rv32m1_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rv32m1_tty_s +{ + uart_dev_t * dev; /* TTY Device Reference */ + const int idx; /* TTY Index */ +}; + +#ifdef USE_SERIALDRIVER + +#ifdef HAVE_UART + +#if defined(CONFIG_RV32M1_LPUART0) +# define RV32M1_LPUART0_DEV g_uart0dev +#endif + +#if defined(CONFIG_RV32M1_LPUART1) +# define RV32M1_LPUART1_DEV g_uart1dev +#endif + +#if defined(CONFIG_RV32M1_LPUART2) +# define RV32M1_LPUART2_DEV g_uart2dev +#endif + +#if defined(CONFIG_RV32M1_LPUART3) +# define RV32M1_LPUART3_DEV g_uart3dev +#endif + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#if defined(CONFIG_LPUART0_SERIAL_CONSOLE) +# define CONSOLE_DEV RV32M1_LPUART0_DEV +# define SERIAL_CONSOLE 0 +#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define CONSOLE_DEV RV32M1_LPUART1_DEV +# define SERIAL_CONSOLE 1 +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) +# define CONSOLE_DEV RV32M1_LPUART2_DEV +# define SERIAL_CONSOLE 2 +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) +# define CONSOLE_DEV RV32M1_LPUART3_DEV +# define SERIAL_CONSOLE 3 +#elif defined(HAVE_SERIAL_CONSOLE) +# error "No Serial Consoles for RV32M1" +#endif + +#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONSOLE_DEV) +# error "Serial Console Undefined for RV32M1" +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + const uintptr_t uartbase; /* Base address of UART registers */ + const uintptr_t pcc; /* Address of UART PCC clock gate */ + const uint32_t tx_gpio; /* LPUART TX GPIO pin configuration */ + const uint32_t rx_gpio; /* LPUART RX GPIO pin configuration */ + uint32_t baud; /* Configured baud */ + uint16_t irq; /* IRQ associated with this UART */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers */ + +static uint32_t up_getreg(struct up_dev_s *priv, int offset); +static void up_putreg(struct up_dev_s *priv, int offset, uint32_t value); +static void up_restoreuartint(struct up_dev_s *priv, uint32_t im); +static void up_disableuartint(struct up_dev_s *priv, uint32_t *im); +static void up_clkconfig(struct up_dev_s * priv); +static uint32_t up_clkfreq(struct up_dev_s * priv); + +/* Serial driver methods */ + +static void up_set_format(struct uart_dev_s * dev); +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context, FAR void *arg); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* LPUART Instances */ + +#ifdef CONFIG_RV32M1_LPUART0 +static char g_uart0rxbuffer[CONFIG_LPUART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_LPUART0_TXBUFSIZE]; + +static struct up_dev_s g_uart0priv = +{ + .uartbase = RV32M1_LPUART0_BASE, + .pcc = RV32M1_PCC_LPUART0, + .tx_gpio = GPIO_LPUART0_TX, + .rx_gpio = GPIO_LPUART0_RX, + .baud = CONFIG_LPUART0_BAUD, + .irq = RV32M1_IRQ_LPUART0, +}; + +static uart_dev_t g_uart0dev = +{ +#ifdef SERIAL_CONSOLE + .isconsole = SERIAL_CONSOLE == 0, +#endif + + .recv = + { + .size = CONFIG_LPUART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +#ifdef CONFIG_RV32M1_LPUART1 +static char g_uart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; + +static struct up_dev_s g_uart1priv = +{ + .uartbase = RV32M1_LPUART1_BASE, + .pcc = RV32M1_PCC_LPUART1, + .tx_gpio = GPIO_LPUART1_TX, + .rx_gpio = GPIO_LPUART1_RX, + .baud = CONFIG_LPUART1_BAUD, + .irq = RV32M1_IRQ_LPUART1, +}; + +static uart_dev_t g_uart1dev = +{ +#ifdef SERIAL_CONSOLE + .isconsole = SERIAL_CONSOLE == 1, +#endif + + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +#ifdef CONFIG_RV32M1_LPUART2 +static char g_uart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_LPUART2_TXBUFSIZE]; + +static struct up_dev_s g_uart2priv = +{ + .uartbase = RV32M1_LPUART2_BASE, + .pcc = RV32M1_PCC_LPUART2, + .tx_gpio = GPIO_LPUART2_TX, + .rx_gpio = GPIO_LPUART2_RX, + .baud = CONFIG_LPUART2_BAUD, + .irq = RV32M1_IRQ_LPUART2, +}; + +static uart_dev_t g_uart2dev = +{ +#ifdef SERIAL_CONSOLE + .isconsole = SERIAL_CONSOLE == 2, +#endif + + .recv = + { + .size = CONFIG_LPUART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +#ifdef CONFIG_RV32M1_LPUART3 +static char g_uart3rxbuffer[CONFIG_LPUART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_LPUART3_TXBUFSIZE]; + +static struct up_dev_s g_uart3priv = +{ + .uartbase = RV32M1_LPUART3_BASE, + .pcc = RV32M1_PCC_LPUART3, + .tx_gpio = GPIO_LPUART3_TX, + .rx_gpio = GPIO_LPUART3_RX, + .baud = CONFIG_LPUART3_BAUD, + .irq = RV32M1_IRQ_LPUART3, +}; + +static uart_dev_t g_uart3dev = +{ +#ifdef SERIAL_CONSOLE + .isconsole = SERIAL_CONSOLE == 3, +#endif + + .recv = + { + .size = CONFIG_LPUART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_getreg + ****************************************************************************/ + +static uint32_t up_getreg(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_putreg + ****************************************************************************/ + +static void up_putreg(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static void up_restoreuartint(struct up_dev_s *priv, uint32_t im) +{ + irqstate_t flags = enter_critical_section(); + + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, im); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static void up_disableuartint(struct up_dev_s *priv, uint32_t *im) +{ + irqstate_t flags = enter_critical_section(); + uint32_t regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + + /* Return the current interrupt mask value */ + + if (im) + { + *im = regval; + } + + /* Disable all interrupts */ + + regval &= ~(LPUART_CTRL_TCIE | LPUART_CTRL_TIE | LPUART_CTRL_RIE); + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_clkconfig + ****************************************************************************/ + +static void up_clkconfig(struct up_dev_s * priv) +{ + uint32_t regval; + + rv32m1_pcc_clock_disable(priv->pcc); + + regval = getreg32(priv->pcc); + regval &= ~PCC_CLKCFG_PCS_MASK; + regval |= PCC_CLKCFG_PCS_FIRC; + putreg32(regval, priv->pcc); + + /* Open the uart pcc clock gate */ + + rv32m1_pcc_clock_enable(priv->pcc); +} + +/**************************************************************************** + * Name: up_clkfreq + ****************************************************************************/ + +static uint32_t up_clkfreq(struct up_dev_s * priv) +{ + uint32_t regval; + uint32_t pcs; + + regval = getreg32(priv->pcc); + pcs = regval & PCC_CLKCFG_PCS_MASK; + + switch (pcs) + { + case PCC_CLKCFG_PCS_SOSC: + return rv32m1_clockfreq(CLK_SOSCDIV2); + + case PCC_CLKCFG_PCS_SIRC: + return rv32m1_clockfreq(CLK_SIRCDIV2); + + case PCC_CLKCFG_PCS_FIRC: + return rv32m1_clockfreq(CLK_FIRCDIV2); + + case PCC_CLKCFG_PCS_LPFLL: + return rv32m1_clockfreq(CLK_LPFLLDIV2); + + default: + return 0u; + } + + return 0u; +} + +/**************************************************************************** + * Name: up_setup_format + * + * Description: + * Configure the UART baud, bits, parity, etc. + * + ****************************************************************************/ + +static void up_set_format(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + uint32_t const freq = up_clkfreq(priv); + + uint32_t diff; + uint16_t sbr; + uint16_t osr; + uint16_t tosr; + + uint32_t ctrl; + uint32_t regval; + + /* 'This LPUART instantiation uses a slightly different baud rate + * calculation. The idea is to use the best OSR (over-sampling rate) + * possible. Note, OSR is typically hard-set to 16 in other LPUART + * instantiations loop to find the best OSR value possible, one that + * generates minimum baudDiff iterate through the rest of the supported + * values of OSR.' + * from rv32m1sdk. + */ + + diff = priv->baud; + + osr = 0; + sbr = 0; + + for (tosr = 4; tosr <= 32; ++tosr) + { + uint32_t baud; + uint32_t tdiff; + + /* Calculate the temporary sbr value */ + + uint32_t tsbr = freq / (priv->baud * tosr); + if (tsbr == 0) + { + tsbr = 1; + } + + baud = freq / (tosr * tsbr); + tdiff = baud - priv->baud; + + /* Select the better value between sbr and (sbr + 1) */ + + baud = freq / (tosr * (tsbr + 1)); + + if (tdiff > (priv->baud - baud)) + { + /* Get the closer one. i.e. the minimum difference */ + + tdiff = priv->baud - baud; + tsbr ++; + } + + /* Pick up the best osr and sbr with the minimum diff */ + + if (tdiff <= diff) + { + diff = tdiff; + osr = tosr; + sbr = tsbr; + } + } + + /* We don't check the baud error rate here even it is out of 3% + * which will cause undesired performance. + */ + + regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + ctrl = regval; + + /* Stop the Receiver and Transmitter before Baud rate update */ + + regval &= ~(LPUART_CTRL_TE | LPUART_CTRL_RE); + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); + + regval = up_getreg(priv, RV32M1_LPUART_BAUD_OFFSET); + + /* BOTHEDGE is required if osr is below 8 */ + + if (osr > 3 && osr < 8) + { + regval |= LPUART_BAUD_BOTHEDGE; + } + + /* Update OSR */ + + regval &= ~LPUART_BAUD_OSR_MASK; + regval |= ((osr - 1) << LPUART_BAUD_OSR_SHIFT) & LPUART_BAUD_OSR_MASK; + + /* Update SBR */ + + regval &= ~LPUART_BAUD_SBR_MASK; + regval |= (sbr << LPUART_BAUD_SBR_SHIFT) & LPUART_BAUD_SBR_MASK; + + /* Disable 10-bit Mode */ + + regval &= ~LPUART_BAUD_M10; + + /* FIXME: Parity, 1-Wire and Stop bits are configuralbe, + * for the initial(started) version, they are fixed + * (hard coded): No Parity, Full-duplex, and 1 Stop bit. + * Fix the missing pieces later. + */ + + /* 1 Stop bit */ + + regval &= ~LPUART_BAUD_SBNS_MASK; + regval |= LPUART_BAUD_SBNS_1; + + /* Set Baud Register */ + + up_putreg(priv, RV32M1_LPUART_BAUD_OFFSET, regval); + + regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + + /* No parity, 8-Bit mode */ + + regval &= ~(LPUART_CTRL_PE | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | + LPUART_CTRL_M7 | LPUART_CTRL_IDLECFG_MASK | + LPUART_CTRL_ILT); + + regval |= LPUART_CTRL_M8 | LPUART_CTRL_IDLECFG_1; + + regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + if (ctrl & LPUART_CTRL_TE) + { + regval |= LPUART_CTRL_TE; + } + else + { + regval &= ~LPUART_CTRL_TE; + } + + if (ctrl & LPUART_CTRL_RE) + { + regval |= LPUART_CTRL_RE; + } + else + { + regval &= ~LPUART_CTRL_RE; + } + + /* Restore the Control Register */ + + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t regval; + + /* Configure GPIO */ + + rv32m1_gpio_config(priv->tx_gpio); + rv32m1_gpio_config(priv->rx_gpio); + + /* Configure the clock source and open the clock gate */ + + up_clkconfig(priv); + + /* Reset the Uart */ + + regval = up_getreg(priv, RV32M1_LPUART_GLOBAL_OFFSET); + regval |= LPUART_GLOBAL_RST; + up_putreg(priv, RV32M1_LPUART_GLOBAL_OFFSET, regval); + regval &= ~LPUART_GLOBAL_RST; + up_putreg(priv, RV32M1_LPUART_GLOBAL_OFFSET, regval); + + /* Setup the Baudrate, Line */ + + up_set_format(dev); + + /* Set Watermark Zero Level for this version */ + + regval = up_getreg(priv, RV32M1_LPUART_WATER_OFFSET); + regval &= ~(LPUART_WATER_RXWATER_MASK | LPUART_WATER_TXWATER_MASK); + up_putreg(priv, RV32M1_LPUART_WATER_OFFSET, regval); + + regval = up_getreg(priv, RV32M1_LPUART_FIFO_OFFSET); + + /* Enable RX and TX FIFO */ + + regval |= LPUART_FIFO_TXFE | LPUART_FIFO_RXFE; + up_putreg(priv, RV32M1_LPUART_FIFO_OFFSET, regval); + + /* Flush FIFO */ + + regval |= LPUART_FIFO_TXFLUSH | LPUART_FIFO_RXFLUSH; + up_putreg(priv, RV32M1_LPUART_FIFO_OFFSET, regval); + + /* Write '1' to Clear all Status Flags */ + + regval = up_getreg(priv, RV32M1_LPUART_STAT_OFFSET); + regval |= LPUART_STAT_LBKDIF | LPUART_STAT_RXEDGIF | LPUART_STAT_IDLE | + LPUART_STAT_OR | LPUART_STAT_NF | LPUART_STAT_FE | + LPUART_STAT_PF | LPUART_STAT_MA1F | LPUART_STAT_MA2F ; + + /* LSB First */ + + regval &= ~LPUART_STAT_MSBF; + up_putreg(priv, RV32M1_LPUART_STAT_OFFSET, regval); + + /* Enable Receiver and Transmitter */ + + regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + regval |= LPUART_CTRL_TE | LPUART_CTRL_RE; + + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + uint32_t regval; + + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disableuartint(priv, NULL); + + /* Disable Transmitter and Receiver. */ + + regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + regval &= ~(LPUART_CTRL_TE | LPUART_CTRL_RE); + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); + + /* Close the uart PCC clock gate */ + + rv32m1_pcc_clock_disable(priv->pcc); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + int ret; + + uint32_t regval; + + regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + regval |= LPUART_CTRL_TCIE | LPUART_CTRL_TIE | LPUART_CTRL_RIE ; + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); + + ret = irq_attach(priv->irq, up_interrupt, dev); + + if (ret == OK) + { + /* Enable the interrupt */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); + + /* Detach from the interrupt */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +LOCATE_ITCM +static int up_interrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct up_dev_s *priv; + uint32_t status; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct up_dev_s *)dev->priv; + + /* Retrieve interrupt pending status */ + + status = up_getreg(priv, RV32M1_LPUART_STAT_OFFSET); + + if (status & LPUART_STAT_RDRF) + { + /* Process incoming bytes */ + + uart_recvchars(dev); + } + + if (status & (LPUART_STAT_TDRE | LPUART_STAT_TC)) + { + /* Process outgoing bytes */ + + uart_xmitchars(dev); + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return status information */ + + if (status) + { + *status = 0; /* We are not yet tracking serial errors */ + } + + /* Return cached data */ + + return up_getreg(priv, RV32M1_LPUART_DATA_OFFSET) & 0xff; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t regval; + + irqstate_t flags = enter_critical_section(); + + regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + regval |= LPUART_CTRL_RIE; +#endif + } + else + { + regval &= ~LPUART_CTRL_RIE; + } + + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return true is data is available in the receive data buffer */ + + uint32_t fifo = up_getreg(priv, RV32M1_LPUART_FIFO_OFFSET); + return (fifo & LPUART_FIFO_RXEMPT) == 0; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + up_putreg(priv, RV32M1_LPUART_DATA_OFFSET, (uint32_t)ch & 0x0ff); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags = enter_critical_section(); + + uint32_t regval; + + regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); + + if (enable) + { + /* Enable the TX interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + regval |= LPUART_CTRL_TCIE | LPUART_CTRL_TIE; +#endif + } + else + { + /* Disable the TX interrupt */ + + regval &= ~(LPUART_CTRL_TCIE | LPUART_CTRL_TIE); + } + + up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit data register is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + uint32_t txvol = (up_getreg(priv, RV32M1_LPUART_FIFO_OFFSET) & + LPUART_FIFO_TXFIFOSIZE_MASK) >> + LPUART_FIFO_TXFIFOSIZE_SHIFT ; + + uint32_t txcnt = (up_getreg(priv, RV32M1_LPUART_WATER_OFFSET) & + LPUART_WATER_TXCOUNT_MASK) >> + LPUART_WATER_TXCOUNT_SHIFT ; + + /* Return TRUE if the TX FIFO is not full */ + + return txcnt < txvol; +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return TRUE if the TX wartermak is pending */ + + return (up_getreg(priv, RV32M1_LPUART_FIFO_OFFSET) & LPUART_FIFO_TXEMPT) + != 0; +} +#endif /* HAVE_UART */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT + +/**************************************************************************** + * Name: riscv_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before riscv_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock + * initialization performed in up_clkinitialize(). + * + ****************************************************************************/ + +void riscv_earlyserialinit(void) +{ + /* Do nothing, we've set up the serial console. + * The function must be provided to get rid of + * linking problem when USE_EARLYSERIALINIT is + * defined. + */ +} +#endif + +/**************************************************************************** + * Name: riscv_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that riscv_earlyserialinit was called previously. + * + ****************************************************************************/ + +void riscv_serialinit(void) +{ + int i; + int nuart; + + char devpath[16] = "/dev/ttyS"; + + /* Device NO. */ + + int devno = 1; + + const struct rv32m1_tty_s ttydevs[] = + { +#ifdef RV32M1_LPUART0_DEV + { + .dev = &RV32M1_LPUART0_DEV, + .idx = RV32M1_LPUART0_DEV.isconsole ? 0 : devno ++, + }, +#endif +#ifdef RV32M1_LPUART1_DEV + { + .dev = &RV32M1_LPUART1_DEV, + .idx = RV32M1_LPUART1_DEV.isconsole ? 0 : devno ++, + }, +#endif +#ifdef RV32M1_LPUART2_DEV + { + .dev = &RV32M1_LPUART2_DEV, + .idx = RV32M1_LPUART2_DEV.isconsole ? 0 : devno ++, + }, +#endif +#ifdef RV32M1_LPUART3_DEV + { + .dev = &RV32M1_LPUART3_DEV, + .idx = RV32M1_LPUART3_DEV.isconsole ? 0 : devno ++, + }, +#endif + + /* Place a dummy One as a Place holder to avoid uartdevs + * to be empty when All above uart devices are undefined, + * in which case a complier error will raise. + */ + + { + .dev = NULL, + .idx = -1, + }, + }; + + nuart = (int)(sizeof(ttydevs) / sizeof(ttydevs[0])); + + /* Register the console */ + +#ifdef CONSOLE_DEV + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register All Uarts */ + + for (i = 0; i < nuart; ++i) + { + const struct rv32m1_tty_s * tty = &ttydevs[i]; + + if (!tty->dev) + { + continue; + } + + /* OS (NuttX) is primordial and so many resources are uninitialized + * while we are in 'riscv_serialinit'. The high level C lib functions + * may not work well. Codes such as the following + * 'snprintf(devpath, "/dev/ttyS%d\n", devno)...' + * would not work as expected. + * + * It is ok to complete the device path manually. + */ + + devno = tty->idx; + + if (devno < 10) + { + devpath[9] = devno + '0'; + + /* Terminate the String */ + + devpath[10] = '\0'; + } + else + { + /* There is one pre-condition that devno doesn't exceed 100 */ + + int d = devno / 10; + devpath[9] = d + '0'; + + d = devno - d * 10; + devpath[10] = d + '0'; + + /* Terminate the String */ + + devpath[11] = '\0'; + } + + uart_register(devpath, tty->dev); + } +} + +#endif /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef CONSOLE_DEV + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; + uint32_t im; + + up_disableuartint(priv, &im); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + riscv_lowputc('\r'); + } + + riscv_lowputc(ch); + up_restoreuartint(priv, im); +#endif + return ch; +} + +#ifdef HAVE_SERIAL_CONSOLE +/**************************************************************************** + * Name: rv32m1_console_uart_setup + ****************************************************************************/ + +void rv32m1_console_uart_setup(void) +{ +#ifdef CONSOLE_DEV + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: rv32m1_console_uart_putc + ****************************************************************************/ + +void rv32m1_console_uart_putc(char ch) +{ +#ifdef CONSOLE_DEV + while (!up_txready(&CONSOLE_DEV)) ; + up_send(&CONSOLE_DEV, ch); +#endif +} +#endif /* HAVE_SERIAL_CONSOLE */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_start.c b/arch/risc-v/src/rv32m1/rv32m1_start.c new file mode 100644 index 00000000000..997bf57678f --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_start.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "riscv_arch.h" +#include "rv32m1_clockconfig.h" +#include "rv32m1.h" +#include "rv32m1_gpio.h" +#include "rv32m1_lowputc.h" +#include "hardware/rv32m1_wdog.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) riscv_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ + +uint32_t g_idle_topstack = RV32M1_IDLESTACK_TOP; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __rv32m1_start + ****************************************************************************/ + +void __rv32m1_start(void) +{ + const uint32_t *src; + uint32_t *dest; + + uint32_t regval; + + /* Watch dog starts automatically after System resets. Stop it */ + + putreg32(WDOG_CNT_UNLOCK, RV32M1_WDOG_CNT); + putreg32(0xffff, RV32M1_WDOG_TOVAL); + + regval = getreg32(RV32M1_WDOG_CS); + regval &= ~WDOG_CS_EN; + regval |= WDOG_CS_UPDATE; + putreg32(regval, RV32M1_WDOG_CS); + +#ifdef CONFIG_RV32M1_ITCM + + src = &_slitcm; + dest = &_svitcm; + + if (src != dest) + { + /* Copy codes from Flash LMA Region to ITCM VMA Region */ + + for (; dest < &_evitcm; ) + { + *dest++ = *src++; + } + } + +#endif + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + /* Setup clock */ + + rv32m1_clockconfig(); + + /* Configure the UART so we can get debug output */ + + rv32m1_lowsetup(); + + showprogress('A'); + +#ifdef USE_EARLYSERIALINIT + riscv_earlyserialinit(); +#endif + + showprogress('B'); + + /* Do board initialization */ + + rv32m1_boardinitialize(); + + showprogress('C'); + + /* Call nx_start() */ + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_timerisr.c b/arch/risc-v/src/rv32m1/rv32m1_timerisr.c new file mode 100644 index 00000000000..91127d5438b --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_timerisr.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "riscv_arch.h" + +#include "rv32m1.h" +#include "hardware/rv32m1_lptmr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Data Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_timerisr + ****************************************************************************/ + +LOCATE_ITCM +static int rv32m1_timerisr(int irq, void *context, FAR void *arg) +{ + /* Write '1' to clear the pending flag */ + + uint32_t regval = getreg32(RV32M1_LPTMR_CSR); + regval |= LPTMR_CSR_TCF; + putreg32(regval, RV32M1_LPTMR_CSR); + + /* Process timer interrupt */ + + nxsched_process_timer(); + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regaddr; + uint32_t regval; + + /* Stop the timer and clear the pending flag */ + + regaddr = RV32M1_LPTMR_CSR; + regval = getreg32(regaddr); + regval &= ~LPTMR_CSR_TEN; + putreg32(regval, regaddr); + + /* Counter mode, + * Reset counter when the compare value is matched, + * No DMA request + */ + + regval &= ~(LPTMR_CSR_TMS | LPTMR_CSR_TFC | + LPTMR_CSR_TDRE | LPTMR_CSR_TPS_MASK); + regval |= LPTMR_CSR_TPS0; + + putreg32(regval, regaddr); + + regaddr = RV32M1_LPTMR_PSR; + regval = LPTMR_PSR_PCS_SIRCDIV3 | LPTMR_PSR_PBYP; + putreg32(regval, regaddr); + + /* Attach timer interrupt handler */ + + irq_attach(RV32M1_IRQ_LPTMR, rv32m1_timerisr, NULL); + + /* Open the timer interrupt gate */ + + up_enable_irq(RV32M1_IRQ_LPTMR); + + /* Set ticks to compare */ + + regval = rv32m1_clockfreq(CLK_SIRCDIV3) / TICK_PER_SEC; + if (regval > 0) + { + /* Fine tune the ticks */ + + --regval; + } + + putreg32(regval, RV32M1_LPTMR_CMR); + + /* Start the timer with interrupt enabled */ + + regval = getreg32(RV32M1_LPTMR_CSR); + regval &= ~LPTMR_CSR_TCF; + regval |= LPTMR_CSR_TEN | LPTMR_CSR_TIE; + putreg32(regval, RV32M1_LPTMR_CSR); +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_timersvc.c b/arch/risc-v/src/rv32m1/rv32m1_timersvc.c new file mode 100644 index 00000000000..4f90e60876b --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_timersvc.c @@ -0,0 +1,98 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_timersvc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "riscv_arch.h" + +#include "rv32m1.h" +#include "hardware/rv32m1_tstmr.h" +#include "rv32m1_timersvc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Data Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_timersvc_up + ****************************************************************************/ + +bool rv32m1_timersvc_up(void) +{ +#ifdef CONFIG_RV32M1_TSTMR + /* TSTMR starts up when System Reset and TSTMR is Enabled by Option Byte. + * Query the Option Byte to check whether TSTMR is enabled. + */ + + return (getreg8(RV32M1_FTFE_BASE + 0x10) & 0x01) != 0; +#else + return false; +#endif +} + +/**************************************************************************** + * Name: rv32m1_timersvc_freq + ****************************************************************************/ + +uint32_t rv32m1_timersvc_freq(void) +{ + /* TSTMR runs off 1MHz */ + + return 1000000u; +} + +/**************************************************************************** + * Name: rv32m1_timersvc_period + ****************************************************************************/ + +uint32_t rv32m1_timersvc_period(void) +{ + return 0xffffffffu; +} + +/**************************************************************************** + * Name: rv32m1_timersvc_value + ****************************************************************************/ + +uint32_t rv32m1_timersvc_value(void) +{ + /* Read High and Low Registers completely for the Right Result */ + + uint64_t value = *(volatile uint64_t *)(RV32M1_TSTMR_BASE); + + /* It is ok to return the ONLY low valud caused the it is accumulated + * outside. + */ + + return (uint32_t)value; +} diff --git a/arch/risc-v/src/rv32m1/rv32m1_timersvc.h b/arch/risc-v/src/rv32m1/rv32m1_timersvc.h new file mode 100644 index 00000000000..6b49929c9bd --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_timersvc.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_timersvc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_RV32M1_RV32M1_TIMERSVC_H +#define __ARCH_RISCV_SRC_RV32M1_RV32M1_TIMERSVC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: rv32m1_timersvc_up + ****************************************************************************/ + +EXTERN bool rv32m1_timersvc_up(void); + +/**************************************************************************** + * Name: rv32m1_timersvc_freq + ****************************************************************************/ + +EXTERN uint32_t rv32m1_timersvc_freq(void); + +/**************************************************************************** + * Name: rv32m1_timersvc_period + ****************************************************************************/ + +EXTERN uint32_t rv32m1_timersvc_period(void); + +/**************************************************************************** + * Name: rv32m1_timersvc_value + ****************************************************************************/ + +EXTERN uint32_t rv32m1_timersvc_value(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_TIMERSVC_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_uart.h b/arch/risc-v/src/rv32m1/rv32m1_uart.h new file mode 100644 index 00000000000..f82e2189571 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_uart.h @@ -0,0 +1,105 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef _ARCH_RISCV_SRC_RV32M1_RV32M1_UART_H +#define _ARCH_RISCV_SRC_RV32M1_RV32M1_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "chip.h" + +#include "hardware/rv32m1_lpuart.h" + +#undef HAVE_UART +#if defined(CONFIG_RV32M1_LPUART0) || \ + defined(CONFIG_RV32M1_LPUART1) || \ + defined(CONFIG_RV32M1_LPUART2) || \ + defined(CONFIG_RV32M1_LPUART3) +# define HAVE_UART 1 +#endif + +#if defined(CONFIG_LPUART0_SERIAL_CONSOLE) && defined(CONFIG_RV32M1_LPUART0) +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_RV32M1_LPUART1) +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) && defined(CONFIG_RV32M1_LPUART2) +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) && defined(CONFIG_RV32M1_LPUART3) +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# undef CONFIG_LPUART2_SERIAL_CONSOLE +# undef CONFIG_LPUART3_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#if defined(HAVE_SERIAL_CONSOLE) +/**************************************************************************** + * Name: rv32m1_console_uart_setup + ****************************************************************************/ + +EXTERN void rv32m1_console_uart_setup(void); + +/**************************************************************************** + * Name: rv32m1_console_uart_putc + ****************************************************************************/ + +EXTERN void rv32m1_console_uart_putc(char); +#endif /* HAVE_SERIAL_CONSOLE */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* _ARCH_RISCV_SRC_RV32M1_RV32M1_UART_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_vectors.S b/arch/risc-v/src/rv32m1/rv32m1_vectors.S new file mode 100644 index 00000000000..41611317533 --- /dev/null +++ b/arch/risc-v/src/rv32m1/rv32m1_vectors.S @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/risc-v/src/rv32m1/rv32m1_vectors.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip.h" + + /* Imported Symbols */ + + .extern __start + .extern exception_common + +#ifdef CONFIG_RV32M1_ITCM + .section .boot, "ax" + .option norvc + .org 0x80 + j __start + + .section SECTION_ITCM +__reset: + lui t0, %hi(__start) + addi t0, t0, %lo(__start) + jalr x0, 0(t0) +#endif + + .section .vectors, "ax" + .option norvc + j exception_common /* 0 */ + j exception_common /* 1 */ + j exception_common /* 2 */ + j exception_common /* 3 */ + j exception_common /* 4 */ + j exception_common /* 5 */ + j exception_common /* 6 */ + j exception_common /* 7 */ + j exception_common /* 8 */ + j exception_common /* 9 */ + j exception_common /* 10 */ + j exception_common /* 11 */ + j exception_common /* 12 */ + j exception_common /* 13 */ + j exception_common /* 14 */ + j exception_common /* 15 */ + j exception_common /* 16 */ + j exception_common /* 17 */ + j exception_common /* 18 */ + j exception_common /* 19 */ + j exception_common /* 20 */ + j exception_common /* 21 */ + j exception_common /* 22 */ + j exception_common /* 23 */ + j exception_common /* 24 */ + j exception_common /* 25 */ + j exception_common /* 26 */ + j exception_common /* 27 */ + j exception_common /* 28 */ + j exception_common /* 29 */ + j exception_common /* 30 */ + j exception_common /* 31 */ +#ifdef CONFIG_RV32M1_ITCM + j __reset +#else + j __start +#endif + j exception_common /* Illegal instruction */ + j exception_common /* Ecall */ + j exception_common /* LSU error */ diff --git a/arch/risc-v/src/rv64gc/Toolchain.defs b/arch/risc-v/src/rv64gc/Toolchain.defs index 9614a4d323a..479ec253525 100644 --- a/arch/risc-v/src/rv64gc/Toolchain.defs +++ b/arch/risc-v/src/rv64gc/Toolchain.defs @@ -49,6 +49,8 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION ?= -Os endif # Generic GNU RVG toolchain @@ -57,13 +59,6 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) CROSSDEV ?= riscv64-unknown-elf- endif -# Individual tools may limit the optimization level but, by default, the -# optimization level will be set to -Os - -ifeq ($(CONFIG_DEBUG_SYMBOLS),) -MAXOPTIMIZATION ?= -Os -endif - # Default toolchain CC = $(CROSSDEV)gcc diff --git a/arch/risc-v/src/rv64gc/riscv_assert.c b/arch/risc-v/src/rv64gc/riscv_assert.c index 74cbf5787e9..f5bdda2f1e0 100644 --- a/arch/risc-v/src/rv64gc/riscv_assert.c +++ b/arch/risc-v/src/rv64gc/riscv_assert.c @@ -78,7 +78,9 @@ static void up_stackdump(uint64_t sp, uintptr_t stack_top) for (stack = sp & ~0x1f; stack < stack_top; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08" PRIxPTR ": %08" PRIx32 " %08" PRIx32 " %08" PRIx32 + " %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " %08" PRIx32 + " %08" PRIx32 "\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -130,44 +132,52 @@ static inline void up_registerdump(void) if (CURRENT_REGS) { - _alert("EPC:%016x \n", + _alert("EPC:%016" PRIx64 " \n", CURRENT_REGS[REG_EPC]); - _alert("A0:%016x A1:%016x A2:%016x A3:%016x \n", + _alert("A0:%016" PRIx64 " A1:%01" PRIx64 "6 A2:%016" PRIx64 + " A3:%016" PRIx64 " \n", CURRENT_REGS[REG_A0], CURRENT_REGS[REG_A1], CURRENT_REGS[REG_A2], CURRENT_REGS[REG_A3]); - _alert("A4:%016x A5:%016x A6:%016x A7:%016x \n", + _alert("A4:%016" PRIx64 " A5:%016" PRIx64 "A6:%016" PRIx64 + " A7:%016" PRIx64 " \n", CURRENT_REGS[REG_A4], CURRENT_REGS[REG_A5], CURRENT_REGS[REG_A6], CURRENT_REGS[REG_A7]); - _alert("T0:%016x T1:%016x T2:%016x T3:%016x \n", + _alert("T0:%016" PRIx64 " T1:%016" PRIx64 " T2:%016" PRIx64 + " T3:%016" PRIx64 " \n", CURRENT_REGS[REG_T0], CURRENT_REGS[REG_T1], CURRENT_REGS[REG_T2], CURRENT_REGS[REG_T3]); - _alert("T4:%016x T5:%016x T6:%016x \n", + _alert("T4:%016" PRIx64 " T5:%016" PRIx64 " T6:%016" PRIx64 " \n", CURRENT_REGS[REG_T4], CURRENT_REGS[REG_T5], CURRENT_REGS[REG_T6]); - _alert("S0:%016x S1:%016x S2:%016x S3:%016x \n", + _alert("S0:%016" PRIx64 " S1:%016" PRIx64 " S2:%016" PRIx64 + " S3:%016" PRIx64 " \n", CURRENT_REGS[REG_S0], CURRENT_REGS[REG_S1], CURRENT_REGS[REG_S2], CURRENT_REGS[REG_S3]); - _alert("S4:%016x S5:%016x S6:%016x S7:%016x \n", + _alert("S4:%016" PRIx64 " S5:%016" PRIx64 " S6:%016" PRIx64 + " S7:%016" PRIx64 " \n", CURRENT_REGS[REG_S4], CURRENT_REGS[REG_S5], CURRENT_REGS[REG_S6], CURRENT_REGS[REG_S7]); - _alert("S8:%016x S9:%016x S10:%016x S11:%016x \n", + _alert("S8:%016" PRIx64 " S9:%016" PRIx64 " S10:%016" PRIx64 + " S11:%016" PRIx64 " \n", CURRENT_REGS[REG_S8], CURRENT_REGS[REG_S9], CURRENT_REGS[REG_S10], CURRENT_REGS[REG_S11]); #ifdef RISCV_SAVE_GP - _alert("GP:%016x SP:%016x FP:%016x TP:%016x RA:%016x \n", + _alert("GP:%016" PRIx64 " SP:%016" PRIx64 " FP:%016" PRIx64 + " TP:%016" PRIx64 " RA:%016" PRIx64 " \n", CURRENT_REGS[REG_GP], CURRENT_REGS[REG_SP], CURRENT_REGS[REG_FP], CURRENT_REGS[REG_TP], CURRENT_REGS[REG_RA]); #else - _alert("SP:%016x FP:%016x TP:%016x RA:%016x \n", + _alert("SP:%016" PRIx64 " FP:%016" PRIx64 " TP:%016" PRIx64 + " RA:%016" PRIx64 " \n", CURRENT_REGS[REG_SP], CURRENT_REGS[REG_FP], CURRENT_REGS[REG_TP], CURRENT_REGS[REG_RA]); #endif @@ -184,7 +194,7 @@ static void up_dumpstate(void) uint64_t sp = up_getsp(); uintptr_t ustackbase; uintptr_t ustacksize; -#if CONFIG_ARCH_INTERRUPTSTACK > 7 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 uintptr_t istackbase; uintptr_t istacksize; #endif @@ -200,16 +210,16 @@ static void up_dumpstate(void) /* Get the limits on the interrupt stack memory */ -#if CONFIG_ARCH_INTERRUPTSTACK > 7 +#if CONFIG_ARCH_INTERRUPTSTACK > 15 istackbase = (uintptr_t)&g_intstackalloc; - istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~7); + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~15); /* Show interrupt stack info */ - _alert("sp: %016x\n", sp); + _alert("sp: %016" PRIx64 "\n", sp); _alert("IRQ stack:\n"); - _alert(" base: %016x\n", istackbase); - _alert(" size: %016x\n", istacksize); + _alert(" base: %016" PRIxPTR "\n", istackbase); + _alert(" size: %016" PRIxPTR "\n", istacksize); /* Does the current stack pointer lie within the interrupt * stack? @@ -224,7 +234,7 @@ static void up_dumpstate(void) /* Extract the user stack pointer */ sp = CURRENT_REGS[REG_SP]; - _alert("sp: %016x\n", sp); + _alert("sp: %016" PRIx64 "\n", sp); } else if (CURRENT_REGS) { @@ -235,12 +245,12 @@ static void up_dumpstate(void) /* Show user stack info */ _alert("User stack:\n"); - _alert(" base: %016x\n", ustackbase); - _alert(" size: %016x\n", ustacksize); + _alert(" base: %016" PRIxPTR "\n", ustackbase); + _alert(" size: %016" PRIxPTR "\n", ustacksize); #else - _alert("sp: %016x\n", sp); - _alert("stack base: %016x\n", ustackbase); - _alert("stack size: %016x\n", ustacksize); + _alert("sp: %016" PRIx64 "\n", sp); + _alert("stack base: %016" PRIxPTR "\n", ustackbase); + _alert("stack size: %016" PRIxPTR "\n", ustacksize); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -336,7 +346,7 @@ static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) void up_assert(const char *filename, int lineno) { -#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) +#if CONFIG_TASK_NAME_SIZE > 0 struct tcb_s *rtcb = running_task(); #endif diff --git a/arch/risc-v/src/rv64gc/riscv_blocktask.c b/arch/risc-v/src/rv64gc/riscv_blocktask.c index 82c03515de7..6e67368e672 100644 --- a/arch/risc-v/src/rv64gc/riscv_blocktask.c +++ b/arch/risc-v/src/rv64gc/riscv_blocktask.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/rv64gc/riscv_fault.c b/arch/risc-v/src/rv64gc/riscv_fault.c index d7bd4d3ffb2..88ef5a607b2 100644 --- a/arch/risc-v/src/rv64gc/riscv_fault.c +++ b/arch/risc-v/src/rv64gc/riscv_fault.c @@ -58,48 +58,57 @@ void up_fault(int irq, uint64_t *regs) { CURRENT_REGS = regs; - _alert("EPC:%016x\n", + _alert("EPC:%016" PRIx64 "\n", CURRENT_REGS[REG_EPC]); _alert("Fault IRQ=%d \n", irq); /* Dump register info */ - _alert("A0:%016x A1:%016x A2:%016x A3:%016x \n", + _alert("A0:%016" PRIx64 " A1:%016" PRIx64 " A2:%016" PRIx64 + " A3:%016" PRIx64 "\n", CURRENT_REGS[REG_A0], CURRENT_REGS[REG_A1], CURRENT_REGS[REG_A2], CURRENT_REGS[REG_A3]); - _alert("A4:%016x A5:%016x A6:%016x A7:%016x \n", + _alert("A4:%016" PRIx64 " A5:%016" PRIx64 " A6:%016" PRIx64 + " A7:%016" PRIx64 "\n", CURRENT_REGS[REG_A4], CURRENT_REGS[REG_A5], CURRENT_REGS[REG_A6], CURRENT_REGS[REG_A7]); - _alert("T0:%016x T1:%016x T2:%016x T3:%016x \n", + _alert("T0:%016" PRIx64 " T1:%016" PRIx64 " T2:%016" PRIx64 + " T3:%016" PRIx64 "\n", CURRENT_REGS[REG_T0], CURRENT_REGS[REG_T1], CURRENT_REGS[REG_T2], CURRENT_REGS[REG_T3]); - _alert("T4:%016x T5:%016x T6:%016x \n", + _alert("T4:%016" PRIx64 " T5:%016" PRIx64 + " T6:%016" PRIx64 " \n", CURRENT_REGS[REG_T4], CURRENT_REGS[REG_T5], CURRENT_REGS[REG_T6]); - _alert("S0:%016x S1:%016x S2:%016x S3:%016x \n", + _alert("S0:%016" PRIx64 " S1:%016" PRIx64 " S2:%016" PRIx64 + " S3:%016" PRIx64 "\n", CURRENT_REGS[REG_S0], CURRENT_REGS[REG_S1], CURRENT_REGS[REG_S2], CURRENT_REGS[REG_S3]); - _alert("S4:%016x S5:%016x S6:%016x S7:%016x \n", + _alert("S4:%016" PRIx64 " S5:%016" PRIx64 " S6:%016" PRIx64 + " S7:%016" PRIx64 "\n", CURRENT_REGS[REG_S4], CURRENT_REGS[REG_S5], CURRENT_REGS[REG_S6], CURRENT_REGS[REG_S7]); - _alert("S8:%016x S9:%016x S10:%016x S11:%016x \n", + _alert("S8:%016" PRIx64 " S9:%016" PRIx64 " S10:%016" PRIx64 + " S11:%016" PRIx64 "\n", CURRENT_REGS[REG_S8], CURRENT_REGS[REG_S9], CURRENT_REGS[REG_S10], CURRENT_REGS[REG_S11]); #ifdef RISCV_SAVE_GP - _alert("GP:%016x SP:%016x FP:%016x TP:%016x RA:%016x \n", + _alert("GP:%016" PRIx64 " SP:%016" PRIx64 " FP:%016" PRIx64 + " TP:%016 " PRIx64 "RA:%016" PRIx64 "\n", CURRENT_REGS[REG_GP], CURRENT_REGS[REG_SP], CURRENT_REGS[REG_FP], CURRENT_REGS[REG_TP], CURRENT_REGS[REG_RA]); #else - _alert("SP:%016x FP:%016x TP:%016x RA:%016x \n", + _alert("SP:%016" PRIx64 " FP:%016" PRIx64 " TP:%016" PRIx64 + " RA:%016" PRIx64 "\n", CURRENT_REGS[REG_SP], CURRENT_REGS[REG_FP], CURRENT_REGS[REG_TP], CURRENT_REGS[REG_RA]); #endif diff --git a/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c b/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c index f16096228dc..974bf5ced99 100644 --- a/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c +++ b/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/rv64gc/riscv_schedulesigaction.c b/arch/risc-v/src/rv64gc/riscv_schedulesigaction.c index 4eee0974262..fab6e35994a 100644 --- a/arch/risc-v/src/rv64gc/riscv_schedulesigaction.c +++ b/arch/risc-v/src/rv64gc/riscv_schedulesigaction.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/rv64gc/riscv_sigdeliver.c b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c index 14ccec929ec..a9d94e8c94d 100644 --- a/arch/risc-v/src/rv64gc/riscv_sigdeliver.c +++ b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/risc-v/src/rv64gc/riscv_swint.c b/arch/risc-v/src/rv64gc/riscv_swint.c index 23de0e76293..8cd2528ad7c 100644 --- a/arch/risc-v/src/rv64gc/riscv_swint.c +++ b/arch/risc-v/src/rv64gc/riscv_swint.c @@ -282,33 +282,64 @@ int riscv_swint(int irq, FAR void *context, FAR void *arg) break; #endif - /* R0=SYS_pthread_start: This a user pthread start +#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD) + + /* A0=SYS_pthread_start: This a user pthread start * - * void up_pthread_start(pthread_startroutine_t entrypt, - * pthread_addr_t arg) noreturn_function; + * void up_pthread_start(pthread_trampoline_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) * * At this point, the following values are saved in context: * - * R0 = SYS_pthread_start - * R1 = entrypt - * R2 = arg + * A0 = SYS_pthread_start + * A1 = startup + * A2 = entrypt + * A3 = arg */ -#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_PTHREAD) case SYS_pthread_start: { /* Set up to return to the user-space pthread start-up function in * unprivileged mode. */ - regs[REG_EPC] = (uintptr_t)USERSPACE->pthread_startup & ~1; + regs[REG_EPC] = (uintptr_t)regs[REG_A1] & ~1; /* startup */ - /* Change the parameter ordering to match the expectation of struct - * userpace_s pthread_startup: + /* Change the parameter ordering to match the expectation of the + * user space pthread_startup: */ - regs[REG_A0] = regs[REG_A1]; /* pthread entry */ - regs[REG_A1] = regs[REG_A2]; /* arg */ + regs[REG_A0] = regs[REG_A2]; /* pthread entry */ + regs[REG_A1] = regs[REG_A3]; /* arg */ + regs[REG_INT_CTX] &= ~MSTATUS_MPPM; /* User mode */ + } + break; + + /* R0=SYS_pthread_exit: This pthread_exit call in user-space + * + * void up_pthread_exit(pthread_exitroutine_t exit, + * FAR void *exit_value) + * + * At this point, the following values are saved in context: + * + * R0 = SYS_pthread_exit + * R1 = pthread_exit trampoline routine + * R2 = exit_value + */ + + case SYS_pthread_exit: + { + /* Set up to enter the user-space pthread exit function in + * unprivileged mode. + */ + + regs[REG_EPC] = (uintptr_t)regs[REG_A1] & ~1; /* exit */ + + /* Change the parameter ordering to match the expectation of the + * user space pthread_exit: + */ + + regs[REG_A0] = regs[REG_A2]; /* exit_value */ regs[REG_INT_CTX] &= ~MSTATUS_MPPM; /* User mode */ } break; diff --git a/arch/risc-v/src/rv64gc/riscv_unblocktask.c b/arch/risc-v/src/rv64gc/riscv_unblocktask.c index a86bc501fd5..2e9bb04c362 100644 --- a/arch/risc-v/src/rv64gc/riscv_unblocktask.c +++ b/arch/risc-v/src/rv64gc/riscv_unblocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/risc-v/src/rv64gc/svcall.h b/arch/risc-v/src/rv64gc/svcall.h index 690f5620e4e..6ecb889c678 100644 --- a/arch/risc-v/src/rv64gc/svcall.h +++ b/arch/risc-v/src/rv64gc/svcall.h @@ -46,9 +46,9 @@ #ifdef CONFIG_LIB_SYSCALL # ifdef CONFIG_BUILD_PROTECTED # ifndef CONFIG_SYS_RESERVED -# error "CONFIG_SYS_RESERVED must be defined to have the value 8" -# elif CONFIG_SYS_RESERVED != 8 -# error "CONFIG_SYS_RESERVED must have the value 8" +# error "CONFIG_SYS_RESERVED must be defined to have the value 9" +# elif CONFIG_SYS_RESERVED != 9 +# error "CONFIG_SYS_RESERVED must have the value 9" # endif # else # ifndef CONFIG_SYS_RESERVED @@ -82,6 +82,7 @@ #define SYS_switch_context (2) +#ifndef CONFIG_BUILD_FLAT #ifdef CONFIG_LIB_SYSCALL /* SYS call 3: * @@ -98,15 +99,6 @@ */ #define SYS_task_start (4) - -/* SYS call 5: - * - * void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) - * noreturn_function - */ - -#define SYS_pthread_start (5) - /* SYS call 6: * * void signal_handler(_sa_sigaction_t sighand, int signo, @@ -123,6 +115,24 @@ #define SYS_signal_handler_return (7) #endif /* CONFIG_BUILD_PROTECTED */ + +/* SYS call 5: + * + * void up_pthread_start(pthread_trampoline_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (5) + +/* SYS call 8: + * + * void up_pthread_exit(pthread_exitroutine_t exit, FAR void *exit_value) + */ + +#define SYS_pthread_exit (8) + +#endif /* !CONFIG_BUILD_FLAT */ #endif /* CONFIG_LIB_SYSCALL */ #endif /* __ARCH_RISCV_SRC_RV64GC_SVCALL_H */ diff --git a/arch/sim/Kconfig b/arch/sim/Kconfig index e0213cc5807..52222891223 100644 --- a/arch/sim/Kconfig +++ b/arch/sim/Kconfig @@ -105,11 +105,6 @@ config SIM_X8664_MICROSOFT endchoice -config SIM_WALLTIME - bool "Run the simulation at a fixed cadence in near real-time" - default y - -if SIM_WALLTIME choice prompt "Simulation at a fixed cadence in near real-time" default SIM_WALLTIME_SLEEP @@ -117,12 +112,7 @@ choice config SIM_WALLTIME_SLEEP bool "Execution the simulation in near real-time using host sleep" ---help--- - NOTE: In order to facility fast testing, the sim target's IDLE loop, by default, - calls the system timer "interrupt handler" as fast as possible. As a result, there - really are no noticeable delays when a task sleeps. However, the task really does - sleep -- but the time scale is wrong. If you want behavior that is closer to - normal timing, then you can define SIM_WALLTIME=y in your configuration - file. This configuration setting will cause the sim target's IDLE loop to delay + NOTE: This configuration setting will cause the sim target's IDLE loop to delay on each call so that the system "timer interrupt" is called at a rate approximately correct for the system timer tick rate. With this definition in the configuration, sleep() behavior is more or less normal. @@ -137,14 +127,12 @@ config SIM_WALLTIME_SIGNAL endchoice -endif - config SIM_NETDEV bool "Simulated Network Device" default y select ARCH_HAVE_NETDEV_STATISTICS select SCHED_LPWORK - depends on (NET_ETHERNET && SIM_WALLTIME) + depends on NET_ETHERNET ---help--- Build in support for a simulated network device. @@ -537,7 +525,7 @@ config SIM_QSPIFLASH_PAGESIZE config SIM_HCISOCKET bool "Attach Host Bluetooth" default false - depends on (WIRELESS_BLUETOOTH && HOST_LINUX && SIM_WALLTIME) + depends on (WIRELESS_BLUETOOTH && HOST_LINUX) ---help--- Attached the local bluetooth device to the simulation target via HCI_CHANNEL_USER. This gives NuttX full diff --git a/arch/sim/src/Makefile b/arch/sim/src/Makefile index 49896cbc760..750f9058088 100644 --- a/arch/sim/src/Makefile +++ b/arch/sim/src/Makefile @@ -103,12 +103,6 @@ endif HOSTSRCS += up_simsmp.c endif -ifeq ($(CONFIG_SCHED_INSTRUMENTATION),y) -ifneq ($(CONFIG_SCHED_INSTRUMENTATION_BUFFER),y) - CSRCS += up_schednote.c -endif -endif - ifeq ($(CONFIG_ONESHOT),y) CSRCS += up_oneshot.c endif @@ -241,8 +235,8 @@ OBJS = $(AOBJS) $(COBJS) $(HOSTOBJS) ifneq ($(CONFIG_HOST_MACOS),y) ARCHSCRIPT += -T nuttx.ld - LDSTARTGROUP ?= --start-group - LDENDGROUP ?= --end-group + LDSTARTGROUP ?= -Wl,--start-group + LDENDGROUP ?= -Wl,--end-group endif # Determine which NuttX libraries will need to be linked in diff --git a/arch/sim/src/nuttx-names.in b/arch/sim/src/nuttx-names.in index 2e8d05b67ce..9d405fddc27 100644 --- a/arch/sim/src/nuttx-names.in +++ b/arch/sim/src/nuttx-names.in @@ -51,8 +51,7 @@ NXSYMBOLS(longjmp) NXSYMBOLS(lseek) NXSYMBOLS(malloc) NXSYMBOLS(malloc_size) -NXSYMBOLS(mallinfo) -NXSYMBOLS(memalign) +NXSYMBOLS(malloc_usable_size) NXSYMBOLS(memcpy) NXSYMBOLS(mkdir) NXSYMBOLS(mmap) diff --git a/arch/sim/src/sim/up_alsa.c b/arch/sim/src/sim/up_alsa.c index 5700d79a88e..5f45b346bd0 100644 --- a/arch/sim/src/sim/up_alsa.c +++ b/arch/sim/src/sim/up_alsa.c @@ -27,6 +27,7 @@ #include #include +#include #include #include diff --git a/arch/sim/src/sim/up_assert.c b/arch/sim/src/sim/up_assert.c index ceeda1991d2..6317cc30f5f 100644 --- a/arch/sim/src/sim/up_assert.c +++ b/arch/sim/src/sim/up_assert.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include "up_internal.h" @@ -67,6 +69,10 @@ void up_assert(const char *filename, int line) { + /* Flush any buffered SYSLOG data (from prior to the assertion) */ + + syslog_flush(); + /* Show the location of the failed assertion */ #ifdef CONFIG_SMP @@ -77,12 +83,20 @@ void up_assert(const char *filename, int line) filename, line); #endif + /* Flush any buffered SYSLOG data (from the above) */ + + syslog_flush(); + /* Allow for any board/configuration specific crash information */ #ifdef CONFIG_BOARD_CRASHDUMP board_crashdump(up_getsp(), this_task(), filename, line); #endif + /* Flush any buffered SYSLOG data */ + + syslog_flush(); + if (CURRENT_REGS || (running_task())->flink == NULL) { /* Exit the simulation */ diff --git a/arch/sim/src/sim/up_blocktask.c b/arch/sim/src/sim/up_blocktask.c index bb2a533b932..2924c4c4dbf 100644 --- a/arch/sim/src/sim/up_blocktask.c +++ b/arch/sim/src/sim/up_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/sim/src/sim/up_createstack.c b/arch/sim/src/sim/up_createstack.c index 164d10c8506..ebe36e2ad38 100644 --- a/arch/sim/src/sim/up_createstack.c +++ b/arch/sim/src/sim/up_createstack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/sim/src/sim/up_hcisocket.c b/arch/sim/src/sim/up_hcisocket.c index f1eda8e4b23..6d777ce9036 100644 --- a/arch/sim/src/sim/up_hcisocket.c +++ b/arch/sim/src/sim/up_hcisocket.c @@ -30,6 +30,8 @@ #include #include #include +#include +#include #include #include diff --git a/arch/sim/src/sim/up_hcitty.c b/arch/sim/src/sim/up_hcitty.c deleted file mode 100644 index 75dd5e9b3fe..00000000000 --- a/arch/sim/src/sim/up_hcitty.c +++ /dev/null @@ -1,448 +0,0 @@ -/**************************************************************************** - * arch/sim/src/sim/up_hcitty.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include "up_internal.h" -#include "up_hcisocket_host.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define CONFIG_HCI_RECVBUF_SIZE 1024 -#define CONFIG_HCI_SENDBUF_SIZE 1024 -#define CONFIG_HCI_NPOLLWAITERS 2 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -union bt_hdr_u -{ - struct bt_hci_cmd_hdr_s cmd; - struct bt_hci_acl_hdr_s acl; - struct bt_hci_evt_hdr_s evt; - struct bt_hci_iso_hdr_s iso; -}; - -struct bthcitty_s -{ - sq_entry_t link; - uint8_t recvbuf[CONFIG_HCI_RECVBUF_SIZE]; - size_t recvpos; - size_t recvlen; - sem_t recvsem; - sem_t recvlock; - - uint8_t sendbuf[CONFIG_HCI_SENDBUF_SIZE]; - size_t sendlen; - sem_t sendlock; - - sem_t fdslock; - FAR struct pollfd *fds[CONFIG_HCI_NPOLLWAITERS]; - - unsigned short id; - int fd; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int bthcitty_open (FAR struct file *filep); -static int bthcitty_close (FAR struct file *filep); -static ssize_t bthcitty_read (FAR struct file *filep, - FAR char *buffer, size_t buflen); -static ssize_t bthcitty_write (FAR struct file *filep, - FAR const char *buffer, size_t buflen); -static int bthcitty_ioctl (FAR struct file *filep, - int cmd, unsigned long arg); -static int bthcitty_poll (FAR struct file *filep, - FAR struct pollfd *fds, bool setup); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct file_operations g_hcitty_ops = -{ - .open = bthcitty_open, - .close = bthcitty_close, - .read = bthcitty_read, - .write = bthcitty_write, - .ioctl = bthcitty_ioctl, - .poll = bthcitty_poll -}; - -static sq_queue_t g_hcitty_list; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void bthcitty_post(FAR sem_t *sem) -{ - int semcount; - - nxsem_get_value(sem, &semcount); - if (semcount < 1) - { - nxsem_post(sem); - } -} - -static void bthcitty_pollnotify(FAR struct bthcitty_s *dev, - pollevent_t eventset) -{ - int i; - - for (i = 0; i < CONFIG_HCI_NPOLLWAITERS; i++) - { - FAR struct pollfd *fds = dev->fds[i]; - - if (fds) - { - fds->revents |= (fds->events & eventset); - - if (fds->revents != 0) - { - bthcitty_post(fds->sem); - } - } - } - - bthcitty_post(&dev->recvsem); -} - -static int bthcitty_open(FAR struct file *filep) -{ - FAR struct inode *inode = filep->f_inode; - FAR struct bthcitty_s *dev = inode->i_private; - int ret; - int fd; - - fd = bthcisock_host_open(dev->id); - if (fd < 0) - { - return fd; - } - - dev->sendlen = 0; - dev->recvpos = 0; - dev->recvlen = 0; - dev->fd = fd; - - return OK; -} - -static int bthcitty_close(FAR struct file *filep) -{ - FAR struct inode *inode = filep->f_inode; - FAR struct bthcitty_s *dev = inode->i_private; - - bthcisock_host_close(dev->fd); - - dev->fd = -1; - - bthcitty_pollnotify(dev, POLLIN | POLLOUT); - - return 0; -} - -static ssize_t bthcitty_read(FAR struct file *filep, - FAR char *buffer, size_t buflen) -{ - FAR struct inode *inode = filep->f_inode; - FAR struct bthcitty_s *dev = inode->i_private; - size_t len = dev->recvlen; - int ret; - - ret = nxsem_wait_uninterruptible(&dev->recvlock); - if (ret < 0) - { - return ret; - } - - if (dev->recvpos >= dev->recvlen) - { - while (!bthcisock_host_avail(dev->fd)) - { - nxsem_wait_uninterruptible(&dev->recvsem); - } - - len = bthcisock_host_read(dev->fd, dev->recvbuf, - CONFIG_HCI_RECVBUF_SIZE); - if (len <= 0) - { - nxsem_post(&dev->recvlock); - return len; - } - - dev->recvpos = 0; - dev->recvlen = len; - } - - if (buflen > dev->recvlen - dev->recvpos) - { - buflen = dev->recvlen - dev->recvpos; - } - - memcpy(buffer, dev->recvbuf + dev->recvpos, buflen); - dev->recvpos += buflen; - - nxsem_post(&dev->recvlock); - - return buflen; -} - -static ssize_t bthcitty_write(FAR struct file *filep, - FAR const char *buffer, size_t buflen) -{ - FAR struct inode *inode = filep->f_inode; - FAR struct bthcitty_s *dev = inode->i_private; - FAR union bt_hdr_u *hdr; - size_t pktlen; - size_t hdrlen; - int ret; - - ret = nxsem_wait_uninterruptible(&dev->sendlock); - if (ret < 0) - { - return ret; - } - - if (dev->sendlen + buflen > CONFIG_HCI_SENDBUF_SIZE) - { - ret = -EINVAL; - goto err; - } - - memcpy(dev->sendbuf + dev->sendlen, buffer, buflen); - dev->sendlen += buflen; - - hdr = (FAR union bt_hdr_u *)(dev->sendbuf + 1); - - while (1) - { - switch (dev->sendbuf[0]) - { - case H4_CMD: - hdrlen = sizeof(struct bt_hci_cmd_hdr_s); - pktlen = hdr->cmd.param_len; - break; - case H4_ACL: - hdrlen = sizeof(struct bt_hci_acl_hdr_s); - pktlen = hdr->acl.len; - break; - case H4_ISO: - hdrlen = sizeof(struct bt_hci_iso_hdr_s); - pktlen = hdr->iso.len; - break; - default: - ret = -EINVAL; - goto err; - } - - /* Reassembly is incomplete ? */ - - hdrlen += H4_HEADER_SIZE; - - if (dev->sendlen < hdrlen) - { - goto out; - } - - pktlen += hdrlen; - if (dev->sendlen < pktlen) - { - goto out; - } - - /* Got the full packet, send out */ - - ret = bthcisock_host_send(dev->fd, dev->sendbuf, pktlen); - if (ret < 0) - { - goto err; - } - - dev->sendlen -= pktlen; - if (dev->sendlen == 0) - { - goto out; - } - - memmove(dev->sendbuf, dev->sendbuf + pktlen, dev->sendlen); - } - -err: - dev->sendlen = 0; -out: - nxsem_post(&dev->sendlock); - return ret < 0 ? ret : buflen; -} - -static int bthcitty_ioctl(FAR struct file *filep, - int cmd, unsigned long arg) -{ - return OK; -} - -static int bthcitty_poll(FAR struct file *filep, - FAR struct pollfd *fds, bool setup) -{ - FAR struct inode *inode = filep->f_inode; - FAR struct bthcitty_s *dev = inode->i_private; - pollevent_t eventset; - int ret; - int i; - - ret = nxsem_wait_uninterruptible(&dev->fdslock); - if (ret < 0) - { - return ret; - } - - if (setup) - { - for (i = 0; i < CONFIG_HCI_NPOLLWAITERS; i++) - { - /* Find an available slot */ - - if (!dev->fds[i]) - { - /* Bind the poll structure and this slot */ - - dev->fds[i] = fds; - fds->priv = &dev->fds[i]; - break; - } - } - - if (i >= CONFIG_HCI_NPOLLWAITERS) - { - fds->priv = NULL; - ret = -EBUSY; - } - - if (bthcisock_host_avail(dev->fd)) - { - eventset |= (fds->events & POLLIN); - } - - eventset |= (fds->events & POLLOUT); - - if (eventset) - { - bthcitty_pollnotify(dev, eventset); - } - } - else if (fds->priv != NULL) - { - for (i = 0; i < CONFIG_HCI_NPOLLWAITERS; i++) - { - if (fds == dev->fds[i]) - { - dev->fds[i] = NULL; - fds->priv = NULL; - break; - } - } - } - - nxsem_post(&dev->fdslock); - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void bthcitty_loop(void) -{ - FAR struct bthcitty_s *dev; - FAR sq_entry_t *entry; - - for (entry = sq_peek(&g_hcitty_list); entry; entry = sq_next(entry)) - { - dev = container_of(entry, struct bthcitty_s, link); - if (bthcisock_host_avail(dev->fd)) - { - bthcitty_pollnotify(dev, POLLIN); - } - } -} - -int bthcitty_register(int dev_id) -{ - FAR struct bthcitty_s *dev; - unsigned char name[16]; - int ret; - - snprintf(name, sizeof(name), "/dev/ttyHCI%d", dev_id); - - dev = (FAR struct bthcitty_s *)kmm_zalloc(sizeof(struct bthcitty_s)); - if (dev == NULL) - { - return -ENOMEM; - } - - dev->fd = -1; - dev->id = dev_id; - - nxsem_init(&dev->recvlock, 0, 1); - nxsem_init(&dev->sendlock, 0, 1); - nxsem_init(&dev->recvsem, 0, 0); - nxsem_init(&dev->fdslock, 0, 1); - - nxsem_set_protocol(&dev->recvsem, SEM_PRIO_NONE); - - ret = register_driver(name, &g_hcitty_ops, 0666, dev); - if (ret < 0) - { - nxsem_destroy(&dev->recvlock); - nxsem_destroy(&dev->sendlock); - nxsem_destroy(&dev->recvsem); - nxsem_destroy(&dev->fdslock); - kmm_free(dev); - return ret; - } - - sq_addlast(&dev->link, &g_hcitty_list); - - return 0; -} diff --git a/arch/sim/src/sim/up_heap.c b/arch/sim/src/sim/up_heap.c index 6cb0a9d7c22..84b881c01d9 100644 --- a/arch/sim/src/sim/up_heap.c +++ b/arch/sim/src/sim/up_heap.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -444,7 +445,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* We make the entire heap executable here to keep * the sim simpler. If it turns out to be a problem, the - * ARCH_HAVE_MODULE_TEXT mechanism can be an alternative. + * ARCH_HAVE_TEXT_HEAP mechanism can be an alternative. */ uint8_t *sim_heap = host_alloc_heap(SIM_HEAP_SIZE); diff --git a/arch/sim/src/sim/up_hostmemory.c b/arch/sim/src/sim/up_hostmemory.c index 6d69cedb150..07cad25f53e 100644 --- a/arch/sim/src/sim/up_hostmemory.c +++ b/arch/sim/src/sim/up_hostmemory.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/arch/sim/src/sim/up_hosttime.c b/arch/sim/src/sim/up_hosttime.c index 28142fe9cc0..9d1fb5e8f5b 100644 --- a/arch/sim/src/sim/up_hosttime.c +++ b/arch/sim/src/sim/up_hosttime.c @@ -66,7 +66,7 @@ uint64_t host_gettime(bool rtc) void host_sleep(uint64_t nsec) { - usleep((nsec + 999)/ 1000); + usleep((nsec + 999) / 1000); } /**************************************************************************** diff --git a/arch/sim/src/sim/up_idle.c b/arch/sim/src/sim/up_idle.c index 7b52b34e0f3..6de19e9c9e8 100644 --- a/arch/sim/src/sim/up_idle.c +++ b/arch/sim/src/sim/up_idle.c @@ -54,7 +54,6 @@ * ****************************************************************************/ -#ifndef CONFIG_SMP void up_idle(void) { #ifdef CONFIG_PM @@ -115,30 +114,3 @@ void up_idle(void) sim_foc_update(); #endif } -#endif /* !CONFIG_SMP */ - -#ifdef CONFIG_SMP -void up_idle(void) -{ - host_sleep(100 * 1000); -} -#endif - -/**************************************************************************** - * Name: sim_timer_handler - ****************************************************************************/ - -#ifdef CONFIG_SMP -void sim_timer_handler(void) -{ - /* Handle UART data availability */ - - up_uartloop(); - -#ifdef CONFIG_ONESHOT - /* Driver the simulated interval timer */ - - up_timer_update(); -#endif -} -#endif /* CONFIG_SMP */ diff --git a/arch/sim/src/sim/up_internal.h b/arch/sim/src/sim/up_internal.h index 1fc0743818e..307d7aa5711 100644 --- a/arch/sim/src/sim/up_internal.h +++ b/arch/sim/src/sim/up_internal.h @@ -175,7 +175,6 @@ int up_cpu_paused(int cpu); struct tcb_s *up_this_task(void); int up_cpu_set_pause_handler(int irq); void sim_send_ipi(int cpu); -void sim_timer_handler(void); #endif /* up_oneshot.c *************************************************************/ diff --git a/arch/sim/src/sim/up_lcd.c b/arch/sim/src/sim/up_lcd.c index 170deb06d5b..3ec52042e47 100644 --- a/arch/sim/src/sim/up_lcd.c +++ b/arch/sim/src/sim/up_lcd.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/sim/src/sim/up_qspiflash.c b/arch/sim/src/sim/up_qspiflash.c index 3648cf374db..43d40dee511 100644 --- a/arch/sim/src/sim/up_qspiflash.c +++ b/arch/sim/src/sim/up_qspiflash.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/sim/src/sim/up_releasepending.c b/arch/sim/src/sim/up_releasepending.c index 7194853f928..3f0ca8ec648 100644 --- a/arch/sim/src/sim/up_releasepending.c +++ b/arch/sim/src/sim/up_releasepending.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/sim/src/sim/up_reprioritizertr.c b/arch/sim/src/sim/up_reprioritizertr.c index 87cfa7a2cb1..08aadfd1019 100644 --- a/arch/sim/src/sim/up_reprioritizertr.c +++ b/arch/sim/src/sim/up_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/sim/src/sim/up_sigdeliver.c b/arch/sim/src/sim/up_sigdeliver.c index 02df98f2e9f..ac8544fa9c8 100644 --- a/arch/sim/src/sim/up_sigdeliver.c +++ b/arch/sim/src/sim/up_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/sim/src/sim/up_smpsignal.c b/arch/sim/src/sim/up_smpsignal.c index d1961894e20..cad6cca8e75 100644 --- a/arch/sim/src/sim/up_smpsignal.c +++ b/arch/sim/src/sim/up_smpsignal.c @@ -24,6 +24,8 @@ #include +#include + #include #include #include @@ -96,14 +98,6 @@ static int sim_cpupause_handler(int irq, FAR void *context, FAR void *arg) leave_critical_section(flags); } - else - { - /* NOTE: sim specific logic - * In the case of no pause request, call sim_timer_handler() - */ - - sim_timer_handler(); - } return OK; } diff --git a/arch/sim/src/sim/up_unblocktask.c b/arch/sim/src/sim/up_unblocktask.c index c6d4ed2ee74..1c903b957ad 100644 --- a/arch/sim/src/sim/up_unblocktask.c +++ b/arch/sim/src/sim/up_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/sim/src/sim/up_usestack.c b/arch/sim/src/sim/up_usestack.c index 41952a0c17c..55a833a5b10 100644 --- a/arch/sim/src/sim/up_usestack.c +++ b/arch/sim/src/sim/up_usestack.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/x86/src/common/up_blocktask.c b/arch/x86/src/common/up_blocktask.c index b3504bde94f..e51dfae5401 100644 --- a/arch/x86/src/common/up_blocktask.c +++ b/arch/x86/src/common/up_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/x86/src/common/up_reprioritizertr.c b/arch/x86/src/common/up_reprioritizertr.c index 0ed044bfe95..0a2c2134187 100644 --- a/arch/x86/src/common/up_reprioritizertr.c +++ b/arch/x86/src/common/up_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/src/common/up_unblocktask.c b/arch/x86/src/common/up_unblocktask.c index bf3f3670e0e..4eaf4e529df 100644 --- a/arch/x86/src/common/up_unblocktask.c +++ b/arch/x86/src/common/up_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/x86/src/i486/up_createstack.c b/arch/x86/src/i486/up_createstack.c index 05600bf0add..c4f724f8670 100644 --- a/arch/x86/src/i486/up_createstack.c +++ b/arch/x86/src/i486/up_createstack.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/x86/src/i486/up_savestate.c b/arch/x86/src/i486/up_savestate.c index abc60908e98..3984bb8fa26 100644 --- a/arch/x86/src/i486/up_savestate.c +++ b/arch/x86/src/i486/up_savestate.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/arch/x86/src/i486/up_sigdeliver.c b/arch/x86/src/i486/up_sigdeliver.c index 52e3b5d386c..05a74327e83 100644 --- a/arch/x86/src/i486/up_sigdeliver.c +++ b/arch/x86/src/i486/up_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/x86/src/i486/up_usestack.c b/arch/x86/src/i486/up_usestack.c index 815a8bfe2fd..221c5e2c5a6 100644 --- a/arch/x86/src/i486/up_usestack.c +++ b/arch/x86/src/i486/up_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/x86/src/qemu/qemu.h b/arch/x86/src/qemu/qemu.h index 21f074a5c12..1e607482876 100644 --- a/arch/x86/src/qemu/qemu.h +++ b/arch/x86/src/qemu/qemu.h @@ -284,9 +284,9 @@ void i486_dmainitilaize(void); * gives the caller exclusive access to the DMA channel. * * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. * ****************************************************************************/ diff --git a/arch/x86/src/qemu/qemu_handlers.c b/arch/x86/src/qemu/qemu_handlers.c index 32030013f54..aea36667124 100644 --- a/arch/x86/src/qemu/qemu_handlers.c +++ b/arch/x86/src/qemu/qemu_handlers.c @@ -25,6 +25,8 @@ #include #include +#include + #include #include #include diff --git a/arch/x86/src/qemu/qemu_timerisr.c b/arch/x86/src/qemu/qemu_timerisr.c index 04dfed3a8c8..244b76546fc 100644 --- a/arch/x86/src/qemu/qemu_timerisr.c +++ b/arch/x86/src/qemu/qemu_timerisr.c @@ -30,6 +30,7 @@ #include #include +#include #include #include diff --git a/arch/x86_64/include/intel64/irq.h b/arch/x86_64/include/intel64/irq.h index e820f48b23e..903654e1ebe 100644 --- a/arch/x86_64/include/intel64/irq.h +++ b/arch/x86_64/include/intel64/irq.h @@ -172,7 +172,6 @@ struct xcptcontext * to be processed. */ -#ifndef CONFIG_DISABLE_SIGNALS void *sigdeliver; /* Actual type is sig_deliver_t */ /* These are saved copies of instruction pointer and EFLAGS used during @@ -182,7 +181,6 @@ struct xcptcontext uint64_t saved_rip; uint64_t saved_rflags; uint64_t saved_rsp; -#endif /* Register save area */ diff --git a/arch/x86_64/src/common/up_assert.c b/arch/x86_64/src/common/up_assert.c index 482949d2b36..c1650aa3d4f 100644 --- a/arch/x86_64/src/common/up_assert.c +++ b/arch/x86_64/src/common/up_assert.c @@ -205,6 +205,10 @@ static void up_dumpstate(void) static void _up_assert(void) { + /* Flush any buffered SYSLOG data */ + + syslog_flush(); + /* Are we in an interrupt handler or the idle task? */ if (g_current_regs || (running_task())->flink == NULL) @@ -249,6 +253,10 @@ void up_assert(const char *filename, int lineno) board_autoled_on(LED_ASSERTION); + /* Flush any buffered SYSLOG data (from prior to the assertion) */ + + syslog_flush(); + #if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); @@ -259,6 +267,10 @@ void up_assert(const char *filename, int lineno) up_dumpstate(); + /* Flush any buffered SYSLOG data (from the above) */ + + syslog_flush(); + #ifdef CONFIG_BOARD_CRASHDUMP board_crashdump(up_getsp(), this_task(), filename, lineno); #endif diff --git a/arch/x86_64/src/common/up_blocktask.c b/arch/x86_64/src/common/up_blocktask.c index 7a9143b7633..b7ae8813f1f 100644 --- a/arch/x86_64/src/common/up_blocktask.c +++ b/arch/x86_64/src/common/up_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/x86_64/src/common/up_reprioritizertr.c b/arch/x86_64/src/common/up_reprioritizertr.c index 530d223e11f..426a184ab25 100644 --- a/arch/x86_64/src/common/up_reprioritizertr.c +++ b/arch/x86_64/src/common/up_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86_64/src/common/up_unblocktask.c b/arch/x86_64/src/common/up_unblocktask.c index 5ed575fcb59..519bdd7e482 100644 --- a/arch/x86_64/src/common/up_unblocktask.c +++ b/arch/x86_64/src/common/up_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/arch/x86_64/src/intel64/intel64_handlers.c b/arch/x86_64/src/intel64/intel64_handlers.c index 3fc63352364..5f54a3addcf 100644 --- a/arch/x86_64/src/intel64/intel64_handlers.c +++ b/arch/x86_64/src/intel64/intel64_handlers.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86_64/src/intel64/up_createstack.c b/arch/x86_64/src/intel64/up_createstack.c index fea234c3941..de1c663c12f 100644 --- a/arch/x86_64/src/intel64/up_createstack.c +++ b/arch/x86_64/src/intel64/up_createstack.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/x86_64/src/intel64/up_schedulesigaction.c b/arch/x86_64/src/intel64/up_schedulesigaction.c index dce91a6477c..c072b21f438 100644 --- a/arch/x86_64/src/intel64/up_schedulesigaction.c +++ b/arch/x86_64/src/intel64/up_schedulesigaction.c @@ -35,20 +35,6 @@ #include "up_internal.h" #include "up_arch.h" -#ifndef CONFIG_DISABLE_SIGNALS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -179,5 +165,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) } } } - -#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/x86_64/src/intel64/up_sigdeliver.c b/arch/x86_64/src/intel64/up_sigdeliver.c index 4275ce31f06..fa3d6c39290 100644 --- a/arch/x86_64/src/intel64/up_sigdeliver.c +++ b/arch/x86_64/src/intel64/up_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -37,20 +38,6 @@ #include "up_internal.h" #include "up_arch.h" -#ifndef CONFIG_DISABLE_SIGNALS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -72,7 +59,7 @@ void up_sigdeliver(void) uint64_t regs_area[XCPTCONTEXT_REGS + 2]; uint64_t *regs; - /* align regs to 16byte boundary for SSE instrucitons */ + /* Align regs to 16 byte boundary for SSE instructions. */ regs = (uint64_t *)(((uint64_t)(regs_area) + 15) & (~(uint64_t)15)); @@ -144,6 +131,3 @@ void up_sigdeliver(void) board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } - -#endif /* !CONFIG_DISABLE_SIGNALS */ - diff --git a/arch/x86_64/src/intel64/up_usestack.c b/arch/x86_64/src/intel64/up_usestack.c index d1c8f1385a1..0f1bb4daebc 100644 --- a/arch/x86_64/src/intel64/up_usestack.c +++ b/arch/x86_64/src/intel64/up_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index d6267035a14..5ba21496a54 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -14,7 +14,7 @@ config ARCH_CHIP_ESP32 select ARCH_FAMILY_LX6 select XTENSA_HAVE_INTERRUPTS select ARCH_HAVE_MULTICPU - select ARCH_HAVE_MODULE_TEXT + select ARCH_HAVE_TEXT_HEAP select ARCH_HAVE_SDRAM select ARCH_HAVE_RESET select ARCH_TOOLCHAIN_GNU @@ -37,6 +37,32 @@ config ARCH_CHIP_ESP32 "application"), however for most purposes the two CPUs are interchangeable. +config ARCH_CHIP_ESP32S2 + bool "Espressif ESP32-S2" + select ARCH_FAMILY_LX7 + select XTENSA_HAVE_INTERRUPTS + select ARCH_HAVE_TEXT_HEAP + select ARCH_HAVE_SDRAM + select ARCH_HAVE_RESET + select ARCH_TOOLCHAIN_GNU + select ARCH_VECNOTIRQ + select LIBC_ARCH_MEMCPY + select LIBC_ARCH_MEMCHR + select LIBC_ARCH_MEMCMP + select LIBC_ARCH_MEMCCMP + select LIBC_ARCH_MEMMOVE + select LIBC_ARCH_MEMSET + select LIBC_ARCH_STRCHR + select LIBC_ARCH_STRCMP + select LIBC_ARCH_STRCPY + select LIBC_ARCH_STRLCPY + select LIBC_ARCH_STRNCPY + select LIBC_ARCH_STRLEN + select LIBC_ARCH_STRNLEN + ---help--- + The ESP32-S2 is a dual-core system from Espressif with a + Harvard architecture Xtensa LX7 CPU. + config ARCH_CHIP_XTENSA_CUSTOM bool "Custom XTENSA chip" select ARCH_CHIP_CUSTOM @@ -53,9 +79,17 @@ config ARCH_FAMILY_LX6 Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). The LX6 is a configurable and extensible processor core. +config ARCH_FAMILY_LX7 + bool + default n + ---help--- + Cadence® Tensilica® Xtensa® LX7 data plane processing unit (DPU). + The LX7 is a configurable and extensible processor core. + config ARCH_CHIP string default "esp32" if ARCH_CHIP_ESP32 + default "esp32s2" if ARCH_CHIP_ESP32S2 config XTENSA_CP_LAZY bool "Lazy co-processor state restoration" @@ -143,4 +177,9 @@ if ARCH_CHIP_ESP32 source arch/xtensa/src/esp32/Kconfig endif +source arch/xtensa/src/lx7/Kconfig +if ARCH_CHIP_ESP32S2 +source arch/xtensa/src/esp32s2/Kconfig +endif + endif # ARCH_XTENSA diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 7d7eee0cf30..a610a636872 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -355,7 +355,7 @@ #define ESP32_CPUINT_LEVELPERIPH_20 31 #define ESP32_CPUINT_NLEVELPERIPHS 21 -#define EPS32_CPUINT_LEVELSET 0x8fbe333f +#define ESP32_CPUINT_LEVELSET 0x8fbe333f #define ESP32_CPUINT_EDGEPERIPH_0 10 #define ESP32_CPUINT_EDGEPERIPH_1 22 @@ -363,10 +363,10 @@ #define ESP32_CPUINT_EDGEPERIPH_3 30 #define ESP32_CPUINT_NEDGEPERIPHS 4 -#define EPS32_CPUINT_EDGESET 0x50400400 +#define ESP32_CPUINT_EDGESET 0x50400400 #define ESP32_CPUINT_NNMIPERIPHS 1 -#define EPS32_CPUINT_NMISET 0x00004000 +#define ESP32_CPUINT_NMISET 0x00004000 #define ESP32_CPUINT_MAC 0 #define ESP32_CPUINT_TIMER0 6 @@ -380,8 +380,8 @@ #define ESP32_NCPUINTS 32 #define ESP32_CPUINT_MAX (ESP32_NCPUINTS - 1) -#define EPS32_CPUINT_PERIPHSET 0xdffe773f -#define EPS32_CPUINT_INTERNALSET 0x200188c0 +#define ESP32_CPUINT_PERIPHSET 0xdffe773f +#define ESP32_CPUINT_INTERNALSET 0x200188c0 /* Priority 1: 0-10, 12-13, 17-18 (15) * Priority 2: 19-21 (3) diff --git a/arch/xtensa/include/esp32s2/chip.h b/arch/xtensa/include/esp32s2/chip.h new file mode 100644 index 00000000000..e03c5cc7e3d --- /dev/null +++ b/arch/xtensa/include/esp32s2/chip.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H +#define __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Characterize each supported ESP32S2 part */ + +#define ESP32S2_NDAC 2 /* DAC0-1 */ +#define ESP32S2_NI2C 1 /* I2C0 */ +#define ESP32S2_NI2S 1 /* I2S0 */ +#define ESP32S2_NLCD 1 /* LCD0 */ +#define ESP32S2_NSPI 4 /* SPI0-3 */ +#define ESP32S2_NUARTS 2 /* UART0-1 */ +#define ESP32S2_NUSBOTG 1 /* USB OTG */ + +#define ESP32S2_NGPIOS 46 /* GPIO0-45 */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H */ diff --git a/arch/xtensa/include/esp32s2/core-isa.h b/arch/xtensa/include/esp32s2/core-isa.h new file mode 100644 index 00000000000..2b33b4956bc --- /dev/null +++ b/arch/xtensa/include/esp32s2/core-isa.h @@ -0,0 +1,738 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/core-isa.h + * Xtensa processor CORE configuration + * + * Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H +#define __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option + * is configured, and a value of 0 otherwise. These macros are always + * defined. + */ + +/**************************************************************************** + * ISA + ****************************************************************************/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ + +/* #define XCHAL_HAVE_POPC 0 */ /* POPC instruction */ + +/* #define XCHAL_HAVE_CRC 0 */ /* CRC instruction */ + +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BB 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_PDX 0 /* PDX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_PDX8 0 /* PDX8 */ +#define XCHAL_HAVE_PDX16 0 /* PDX16 */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +/**************************************************************************** + * MISC + ****************************************************************************/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + * (1 = 5-stage, 2 = 7-stage) + */ + +#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */ + +/* In T1050, applies to selected core load and store instr. (see ISA): */ + +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc. */ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw */ + +#define XCHAL_SW_VERSION 1200008 /* sw version of this header */ + +#define XCHAL_CORE_ID "test_0731_1_TIE_GPIO_f" /* alphanum core name + * (CoreID) set in the Xtensa + * Processor Generator + */ + +#define XCHAL_BUILD_UNIQUE_ID 0x00075F76 /* 22-bit sw build ID */ + +/* These definitions describe the hardware targeted by this software. */ + +#define XCHAL_HW_CONFIGID0 0xC2ECFAFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x22075F76 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.0.8" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 8 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 270008 /* major*100+minor */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_0 1 +#define XCHAL_HW_REL_LX7_0_8 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 + +/* If software targets a range of hardware versions, these are the bounds: */ + +#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 8 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 270008 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 8 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 270008 /* latest targeted hw */ + +/**************************************************************************** + * CACHE + ****************************************************************************/ + +#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + +/**************************************************************************** + * Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/**************************************************************************** + * CACHE + ****************************************************************************/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 0 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ + +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 1 +#define XCHAL_DCACHE_WAYS 1 + +/* Cache features: */ + +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ + +#define XCHAL_ICACHE_ACCESS_SIZE 1 +#define XCHAL_DCACHE_ACCESS_SIZE 1 + +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits (see for decoded bits): */ + +#define XCHAL_CA_BITS 4 + +/**************************************************************************** + * INTERNAL I/D RAM/ROMs and XLMI + ****************************************************************************/ + +#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ + +/* Instruction ROM 0: */ + +#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ +#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ +#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 0: */ + +#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Instruction RAM 1: */ + +#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM1 1 +#define XCHAL_INSTRAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data ROM 0: */ + +#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ +#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ +#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATAROM0_BANKS 1 /* number of banks */ + +/* Data RAM 0: */ + +#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ +#define XCHAL_HAVE_DATARAM1 1 +#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* XLMI Port 0: */ + +#define XCHAL_XLMI0_VADDR 0x3FE00000 /* virtual address */ +#define XCHAL_XLMI0_PADDR 0x3FE00000 /* physical address */ +#define XCHAL_XLMI0_SIZE 1048576 /* size in bytes */ +#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +#define XCHAL_HAVE_IDMA 0 +#define XCHAL_HAVE_IDMA_TRANSPOSE 0 + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM */ + +/**************************************************************************** + * INTERRUPTS and TIMERS + ****************************************************************************/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XCHAL_INT_NLEVELS 6 /* number of interrupt levels + * (not including level zero) + */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + +/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ + +#define XCHAL_INTLEVEL1_MASK 0x000637FF +#define XCHAL_INTLEVEL2_MASK 0x00380000 +#define XCHAL_INTLEVEL3_MASK 0x28C08800 +#define XCHAL_INTLEVEL4_MASK 0x53000000 +#define XCHAL_INTLEVEL5_MASK 0x84010000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ + +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ + +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 3 +#define XCHAL_INT16_LEVEL 5 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 2 +#define XCHAL_INT20_LEVEL 2 +#define XCHAL_INT21_LEVEL 2 +#define XCHAL_INT22_LEVEL 3 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 4 +#define XCHAL_INT25_LEVEL 4 +#define XCHAL_INT26_LEVEL 5 +#define XCHAL_INT27_LEVEL 3 +#define XCHAL_INT28_LEVEL 4 +#define XCHAL_INT29_LEVEL 3 +#define XCHAL_INT30_LEVEL 4 +#define XCHAL_INT31_LEVEL 5 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + * EXCSAVE/EPS/EPC_n, RFI n) + */ + +/* Type of each interrupt: */ + +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ + +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F +#define XCHAL_INTTYPE_MASK_TIMER 0x00018040 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ + +#define XTHAL_TIMER_UNCONFIGURED -1 +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ +#define XCHAL_PROFILING_INTERRUPT 11 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ + +#define XCHAL_INTLEVEL7_NUM 14 + +/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ + +/* External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ + +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ +#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ +#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ +#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ +#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ +#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ +#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ +#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ +#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ + +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ + +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ +#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ +#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ +#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ +#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ +#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ +#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ +#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ +#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ + +/**************************************************************************** + * EXCEPTIONS and VECTORS + ****************************************************************************/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + * number: 1 == XEA1 (old) + * 2 == XEA2 (new) + * 0 == XEAX (extern) or TX + */ + +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000400 +#define XCHAL_RESET_VECTOR_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR_PADDR 0x40000400 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x40000340 +#define XCHAL_USER_VECTOR_PADDR 0x40000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x400002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x400002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + +/**************************************************************************** + * DEBUG MODULE + ****************************************************************************/ + +/* Misc */ + +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ + +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ + +#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ + +/**************************************************************************** + * MMU + ****************************************************************************/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + * [autorefill] and protection) + * usable for an MMU-based OS + */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/**************************************************************************** + * MPU + ****************************************************************************/ + +#define XCHAL_HAVE_MPU 0 +#define XCHAL_MPU_ENTRIES 0 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 0 +#define XCHAL_MPU_ALIGN 0 + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + +#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H */ diff --git a/arch/xtensa/include/esp32s2/irq.h b/arch/xtensa/include/esp32s2/irq.h new file mode 100644 index 00000000000..20c95b420c7 --- /dev/null +++ b/arch/xtensa/include/esp32s2/irq.h @@ -0,0 +1,495 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H +#define __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt Matrix + * + * Features + * - Accepts 95 peripheral interrupt sources as input. + * - Generates 26 peripheral interrupt sources as output. + * - CPU NMI Interrupt Mask. + * - Queries current interrupt status of peripheral interrupt sources. + * + * Peripheral Interrupt Source + * + * ESP32S2 has 95 peripheral interrupt sources in total. 67 of 71 ESP32S2 + * peripheral interrupt sources can be allocated to either CPU. The four + * remaining peripheral interrupt sources are CPU-specific, two per CPU. + * + * - GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to + * PRO_CPU. + * - GPIO_INTERRUPT_APP and GPIO_INTERRUPT_APP_NMI can only be allocated to + * APP_CPU. + * + * As a result, PRO_CPU and APP_CPU each have 69 peripheral interrupt + * sources. + */ + +/* PRO_INTR_STATUS_REG_0 */ + +#define ESP32S2_PERI_MAC 0 /* INTR_STATUS_REG_0, bit 0 */ +#define ESP32S2_PERI_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */ +#define ESP32S2_PERI_PWR 2 /* INTR_STATUS_REG_0, bit 2 */ +#define ESP32S2_PERI_BB 3 /* INTR_STATUS_REG_0, bit 3 */ +#define ESP32S2_PERI_BT_MAC 4 /* INTR_STATUS_REG_0, bit 4 */ +#define ESP32S2_PERI_BT_BB 5 /* INTR_STATUS_REG_0, bit 5 */ +#define ESP32S2_PERI_BT_BB_NMI 6 /* INTR_STATUS_REG_0, bit 6 */ +#define ESP32S2_PERI_RWBT 7 /* INTR_STATUS_REG_0, bit 7 */ +#define ESP32S2_PERI_RWBLE 8 /* INTR_STATUS_REG_0, bit 8 */ +#define ESP32S2_PERI_RWBT_NMI 9 /* INTR_STATUS_REG_0, bit 9 */ + +#define ESP32S2_PERI_RWBLE_NMI 10 /* INTR_STATUS_REG_0, bit 10 */ +#define ESP32S2_PERI_SLC0 11 /* INTR_STATUS_REG_0, bit 11 */ +#define ESP32S2_PERI_SLC1 12 /* INTR_STATUS_REG_0, bit 12 */ +#define ESP32S2_PERI_UHCI0 13 /* INTR_STATUS_REG_0, bit 13 */ +#define ESP32S2_PERI_UHCI1 14 /* INTR_STATUS_REG_0, bit 14 */ +#define ESP32S2_PERI_TG_T0_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */ +#define ESP32S2_PERI_TG_T1_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */ +#define ESP32S2_PERI_TG_WDT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */ +#define ESP32S2_PERI_TG_LACT_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */ +#define ESP32S2_PERI_TG1_T0_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */ + +#define ESP32S2_PERI_TG1_T1_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */ +#define ESP32S2_PERI_TG1_WDT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */ +#define ESP32S2_PERI_TG1_LACT_LEVEL 22 /* INTR_STATUS_REG_0, bit 22 */ +#define ESP32S2_PERI_GPIO_INT_PRO 23 /* INTR_STATUS_REG_0, bit 23 */ +#define ESP32S2_PERI_GPIO_INT_PRO_NMI 24 /* INTR_STATUS_REG_0, bit 24 */ +#define ESP32S2_PERI_GPIO_INT_APP 25 /* INTR_STATUS_REG_0, bit 25 */ +#define ESP32S2_PERI_GPIO_INT_APP_NMI 26 /* INTR_STATUS_REG_0, bit 26 */ +#define ESP32S2_PERI_DEDICATED_GPIO_IN 27 /* INTR_STATUS_REG_0, bit 27 */ +#define ESP32S2_PERI_INT_FROM_CPU0 28 /* INTR_STATUS_REG_0, bit 28 */ +#define ESP32S2_PERI_INT_FROM_CPU1 29 /* INTR_STATUS_REG_0, bit 29 */ + +#define ESP32S2_PERI_INT_FROM_CPU2 30 /* INTR_STATUS_REG_0, bit 30 */ +#define ESP32S2_PERI_INT_FROM_CPU3 31 /* INTR_STATUS_REG_0, bit 31 */ + +/* PRO_INTR_STATUS_REG_1 */ + +#define ESP32S2_PERI_SPI1 32 /* INTR_STATUS_REG_1, bit 0 */ +#define ESP32S2_PERI_SPI2 33 /* INTR_STATUS_REG_1, bit 1 */ +#define ESP32S2_PERI_SPI3 34 /* INTR_STATUS_REG_1, bit 2 */ +#define ESP32S2_PERI_I2S0 35 /* INTR_STATUS_REG_1, bit 3 */ +#define ESP32S2_PERI_I2S1 36 /* INTR_STATUS_REG_1, bit 4 */ +#define ESP32S2_PERI_UART 37 /* INTR_STATUS_REG_1, bit 5 */ +#define ESP32S2_PERI_UART1 38 /* INTR_STATUS_REG_1, bit 6 */ +#define ESP32S2_PERI_UART2 39 /* INTR_STATUS_REG_1, bit 7 */ +#define ESP32S2_PERI_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 8 */ +#define ESP32S2_PERI_PWM0 41 /* INTR_STATUS_REG_1, bit 9 */ + +#define ESP32S2_PERI_PWM1 42 /* INTR_STATUS_REG_1, bit 10 */ +#define ESP32S2_PERI_PWM2 43 /* INTR_STATUS_REG_1, bit 11 */ +#define ESP32S2_PERI_PWM3 44 /* INTR_STATUS_REG_1, bit 12 */ +#define ESP32S2_PERI_LEDC 45 /* INTR_STATUS_REG_1, bit 13 */ +#define ESP32S2_PERI_EFUSE 46 /* INTR_STATUS_REG_1, bit 14 */ +#define ESP32S2_PERI_CAN 47 /* INTR_STATUS_REG_1, bit 15 */ +#define ESP32S2_PERI_USB 48 /* INTR_STATUS_REG_1, bit 16 */ +#define ESP32S2_PERI_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 17 */ +#define ESP32S2_PERI_RMT 50 /* INTR_STATUS_REG_1, bit 18 */ +#define ESP32S2_PERI_PCNT 51 /* INTR_STATUS_REG_1, bit 19 */ + +#define ESP32S2_PERI_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 20 */ +#define ESP32S2_PERI_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 21 */ +#define ESP32S2_PERI_RSA 54 /* INTR_STATUS_REG_1, bit 22 */ +#define ESP32S2_PERI_SHA 55 /* INTR_STATUS_REG_1, bit 23 */ +#define ESP32S2_PERI_AES 56 /* INTR_STATUS_REG_1, bit 24 */ +#define ESP32S2_PERI_SPI2_DMA 57 /* INTR_STATUS_REG_1, bit 25 */ +#define ESP32S2_PERI_SPI3_DMA 58 /* INTR_STATUS_REG_1, bit 26 */ +#define ESP32S2_PERI_WDG 59 /* INTR_STATUS_REG_1, bit 27 */ +#define ESP32S2_PERI_TIMER 60 /* INTR_STATUS_REG_1, bit 28 */ +#define ESP32S2_PERI_TIMER_INT2 61 /* INTR_STATUS_REG_1, bit 29 */ + +#define ESP32S2_PERI_TG_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */ +#define ESP32S2_PERI_TG_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */ + +/* PRO_INTR_STATUS_REG_2 */ + +#define ESP32S2_PERI_TG_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */ +#define ESP32S2_PERI_TG_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */ +#define ESP32S2_PERI_TG1_T0_EDGE 66 /* INTR_STATUS_REG_2, bit 2 */ +#define ESP32S2_PERI_TG1_T1_EDGE 67 /* INTR_STATUS_REG_2, bit 3 */ +#define ESP32S2_PERI_TG1_WDT_EDGE 68 /* INTR_STATUS_REG_2, bit 4 */ +#define ESP32S2_PERI_TG1_LACT_EDGE 69 /* INTR_STATUS_REG_2, bit 5 */ +#define ESP32S2_PERI_CACHE_IA 70 /* INTR_STATUS_REG_2, bit 6 */ +#define ESP32S2_PERI_SYSTIMER_TARGET0 71 /* INTR_STATUS_REG_2, bit 7 */ +#define ESP32S2_PERI_SYSTIMER_TARGET1 72 /* INTR_STATUS_REG_2, bit 8 */ +#define ESP32S2_PERI_SYSTIMER_TARGET2 73 /* INTR_STATUS_REG_2, bit 9 */ + +#define ESP32S2_PERI_ASSIST_DEBUG 74 /* INTR_STATUS_REG_2, bit 10 */ +#define ESP32S2_PERI_PMS_PRO_IRAM0_ILG 75 /* INTR_STATUS_REG_2, bit 11 */ +#define ESP32S2_PERI_PMS_PRO_DRAM0_ILG 76 /* INTR_STATUS_REG_2, bit 12 */ +#define ESP32S2_PERI_PMS_PRO_DPORT_ILG 77 /* INTR_STATUS_REG_2, bit 13 */ +#define ESP32S2_PERI_PMS_PRO_AHB_ILG 78 /* INTR_STATUS_REG_2, bit 14 */ +#define ESP32S2_PERI_PMS_PRO_CACHE_ILG 79 /* INTR_STATUS_REG_2, bit 15 */ +#define ESP32S2_PERI_PMS_DMA_APB_I_ILG 80 /* INTR_STATUS_REG_2, bit 16 */ +#define ESP32S2_PERI_PMS_DMA_RX_I_ILG 81 /* INTR_STATUS_REG_2, bit 17 */ +#define ESP32S2_PERI_PMS_DMA_TX_I_ILG 82 /* INTR_STATUS_REG_2, bit 18 */ +#define ESP32S2_PERI_SPI_MEM_REJECT 83 /* INTR_STATUS_REG_2, bit 19 */ + +#define ESP32S2_PERI_DMA_COPY 84 /* INTR_STATUS_REG_2, bit 20 */ +#define ESP32S2_PERI_SPI4_DMA 85 /* INTR_STATUS_REG_2, bit 21 */ +#define ESP32S2_PERI_SPI4 86 /* INTR_STATUS_REG_2, bit 22 */ +#define ESP32S2_PERI_DCACHE_PRELOAD 87 /* INTR_STATUS_REG_2, bit 23 */ +#define ESP32S2_PERI_ICACHE_PRELOAD 88 /* INTR_STATUS_REG_2, bit 24 */ +#define ESP32S2_PERI_APB_ADC 89 /* INTR_STATUS_REG_2, bit 25 */ +#define ESP32S2_PERI_CRYPTO_DMA 90 /* INTR_STATUS_REG_2, bit 26 */ +#define ESP32S2_PERI_CPU_PERI_ERR 91 /* INTR_STATUS_REG_2, bit 27 */ +#define ESP32S2_PERI_APB_PERI_ERR 92 /* INTR_STATUS_REG_2, bit 28 */ +#define ESP32S2_PERI_DCACHE_SYNC 93 /* INTR_STATUS_REG_2, bit 29 */ +#define ESP32S2_PERI_ICACHE_SYNC 94 /* INTR_STATUS_REG_2, bit 29 */ + +/* Total number of peripherals */ + +#define ESP32S2_NPERIPHERALS 95 + +/* Exceptions + * + * IRAM Offset Description + * 0x0000 Windows + * 0x0180 Level 2 interrupt + * 0x01c0 Level 3 interrupt + * 0x0200 Level 4 interrupt + * 0x0240 Level 5 interrupt + * 0x0280 Debug exception + * 0x02c0 NMI exception + * 0x0300 Kernel exception + * 0x0340 User exception + * 0x03c0 Double exception + * + * REVISIT: In more architectures supported by NuttX, exception errors + * tie into the normal interrupt handling via special IRQ numbers. + * It is still to be determined what will be done for the ESP32S2. + * + */ + +/* IRQ numbers for internal interrupts that are dispatched like peripheral + * interrupts + */ + +#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ +#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ +#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ +#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */ + +#define XTENSA_NIRQ_INTERNAL 4 /* Number of dispatch internal interrupts */ +#define XTENSA_IRQ_FIRSTPERI 4 /* First peripheral IRQ number */ + +/* IRQ numbers for peripheral interrupts coming through the Interrupt + * Matrix. + */ + +#define ESP32S2_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERI) + +/* PRO_INTR_STATUS_REG_0 */ + +#define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_MAC) +#define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_MAC_NMI) +#define ESP32S2_IRQ_PWR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWR) +#define ESP32S2_IRQ_BB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB) +#define ESP32S2_IRQ_BT_MAC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BT_MAC) +#define ESP32S2_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB) +#define ESP32S2_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB_NMI) +#define ESP32S2_IRQ_RWBT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBT) +#define ESP32S2_IRQ_RWBLE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBLE) +#define ESP32S2_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBT_NMI) + +#define ESP32S2_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBLE_NMI) +#define ESP32S2_IRQ_SLC0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SLC0) +#define ESP32S2_IRQ_SLC1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SLC1) +#define ESP32S2_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UHCI0) +#define ESP32S2_IRQ_UHCI1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UHCI1) +#define ESP32S2_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T0_LEVEL) +#define ESP32S2_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T1_LEVEL) +#define ESP32S2_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_WDT_LEVEL) +#define ESP32S2_IRQ_TG_LACT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_LACT_LEVEL) +#define ESP32S2_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T0_LEVEL) + +#define ESP32S2_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T1_LEVEL) +#define ESP32S2_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_WDT_LEVEL) +#define ESP32S2_IRQ_TG1_LACT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_LACT_LEVEL) +#define ESP32S2_IRQ_GPIO_INT_PRO (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_PRO) +#define ESP32S2_IRQ_GPIO_INT_PRO_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_PRO_NMI) +#define ESP32S2_IRQ_GPIO_INT_APP (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_APP) +#define ESP32S2_IRQ_GPIO_INT_APP_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_APP_NMI) +#define ESP32S2_IRQ_DEDICATED_GPIO_IN (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DEDICATED_GPIO_IN) +#define ESP32S2_IRQ_INT_FROM_CPU0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU0 +#define ESP32S2_IRQ_INT_FROM_CPU1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU1) + +#define ESP32S2_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU2) +#define ESP32S2_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU3) + +#define ESP32_IRQ_SREG0 ESP32S2_IRQ_MAC +#define ESP32_NIRQS_SREG0 32 + +/* PRO_INTR_STATUS_REG_1 */ + +#define ESP32S2_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI1) +#define ESP32S2_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI2) +#define ESP32S2_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI3) +#define ESP32S2_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2S0) +#define ESP32S2_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2S1) +#define ESP32S2_IRQ_UART (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART) +#define ESP32S2_IRQ_UART1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART1) +#define ESP32S2_IRQ_UART2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART2) +#define ESP32S2_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SDIO_HOST) +#define ESP32S2_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM0) + +#define ESP32S2_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM1) +#define ESP32S2_IRQ_PWM2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM2) +#define ESP32S2_IRQ_PWM3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM3) +#define ESP32S2_IRQ_LEDC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_LEDC) +#define ESP32S2_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_EFUSE) +#define ESP32S2_IRQ_CAN (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CAN) +#define ESP32S2_IRQ_USB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_USB) +#define ESP32S2_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RTC_CORE) +#define ESP32S2_IRQ_RMT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RMT) +#define ESP32S2_IRQ_PCNT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PCNT) + +#define ESP32S2_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2C_EXT0) +#define ESP32S2_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2C_EXT1) +#define ESP32S2_IRQ_RSA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RSA) +#define ESP32S2_IRQ_SHA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SHA) +#define ESP32S2_IRQ_AES (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_AES) +#define ESP32S2_IRQ_SPI2_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI2_DMA) +#define ESP32S2_IRQ_SPI3_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI3_DMA) +#define ESP32S2_IRQ_WDG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_WDG) +#define ESP32S2_IRQ_TIMER (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TIMER) +#define ESP32S2_IRQ_TIMER_INT2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TIMER_INT2) + +#define ESP32S2_IRQ_TG_T0_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T0_EDGE) +#define ESP32S2_IRQ_TG_T1_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T1_EDGE) + +#define ESP32S2_IRQ_SREG1 ESP32S2_IRQ_SPI1 +#define ESP32S2_NIRQS_SREG1 32 + +/* PRO_INTR_STATUS_REG_2 */ + +#define ESP32S2_IRQ_TG_WDT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_WDT_EDGE) +#define ESP32S2_IRQ_TG_LACT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_LACT_EDGE) +#define ESP32S2_IRQ_TG1_T0_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T0_EDGE) +#define ESP32S2_IRQ_TG1_T1_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T1_EDGE) +#define ESP32S2_IRQ_TG1_WDT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_WDT_EDGE) +#define ESP32S2_IRQ_TG1_LACT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_LACT_EDGE) +#define ESP32S2_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CACHE_IA) +#define ESP32S2_IRQ_SYSTIMER_TARGET0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET0) +#define ESP32S2_IRQ_SYSTIMER_TARGET1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET1) +#define ESP32S2_IRQ_SYSTIMER_TARGET2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET2) + +#define ESP32S2_IRQ_ASSIST_DEBUG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ASSIST_DEBUG) +#define ESP32S2_IRQ_PMS_PRO_IRAM0_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_IRAM0_ILG) +#define ESP32S2_IRQ_PMS_PRO_DRAM0_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_DRAM0_ILG) +#define ESP32S2_IRQ_PMS_PRO_DPORT_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_DPORT_ILG) +#define ESP32S2_IRQ_PMS_PRO_AHB_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_AHB_ILG) +#define ESP32S2_IRQ_PMS_PRO_CACHE_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_CACHE_ILG) +#define ESP32S2_IRQ_PMS_DMA_APB_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_APB_I_ILG) +#define ESP32S2_IRQ_PMS_DMA_RX_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_RX_I_ILG) +#define ESP32S2_IRQ_PMS_DMA_TX_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_TX_I_ILG) +#define ESP32S2_IRQ_SPI_MEM_REJECT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI_MEM_REJECT) + +#define ESP32S2_IRQ_DMA_COPY (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DMA_COPY) +#define ESP32S2_IRQ_SPI4_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI4_DMA) +#define ESP32S2_IRQ_SPI4 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI4) +#define ESP32S2_IRQ_DCACHE_PRELOAD (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_PRELOAD) +#define ESP32S2_IRQ_ICACHE_PRELOAD (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_PRELOAD) +#define ESP32S2_IRQ_APB_ADC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_ADC) +#define ESP32S2_IRQ_CRYPTO_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CRYPTO_DMA) +#define ESP32S2_IRQ_CPU_PERI_ERR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CPU_PERI_ERR) +#define ESP32S2_IRQ_APB_PERI_ERE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_PERI_ERR) +#define ESP32S2_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_SYNC) +#define ESP32S2_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_SYNC) + +#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG_WDT_EDGE +#define ESP32S2_NIRQS_SREG2 32 + +/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ + +#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG1_WDT_EDGE +#define ESP32S2_NIRQS_SREG2 5 + +#define ESP32S2_NIRQ_PERIPH ESP32S2_NPERIPHERALS + +/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched + * as a second level of decoding: The first level dispatches to the GPIO + * interrupt handler. The second to the decoded GPIO interrupt handler. + */ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +# define ESP32S2_NIRQ_GPIO 40 +# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL+ESP32S2_NIRQ_PERIPH) +# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ+ESP32S2_NIRQ_GPIO-1) +# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ) +# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ) +#else +# define ESP32S2_NIRQ_GPIO 0 +#endif + +/* Total number of interrupts */ + +#define NR_IRQS (XTENSA_NIRQ_INTERNAL+ESP32S2_NIRQ_PERIPH+ESP32S2_NIRQ_GPIO) + +/* Xtensa CPU Interrupts. + * + * Each of the two CPUs (PRO and APP) have 32 interrupts each, of which + * 26 can be mapped to peripheral interrupts: + * + * Level triggered peripherals (21 total): + * 0-5, 8-9, 12-13, 17-18 - Priority 1 + * 19-21 - Priority 2 + * 23, 27 - Priority 3 + * 24-25 - Priority 4 + * 26, 31 - Priority 5 + * Edge triggered peripherals (4 total): + * 10 - Priority 1 + * 22 - Priority 3 + * 28, 30 - Priority 4 + * NMI (1 total): + * 14 - NMI + * + * CPU peripheral interrupts can be a assigned to a CPU interrupt using the + * PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for + * each peripheral source. Multiple peripheral interrupt sources can be + * mapped to the same CPU interrupt. + * + * The remaining, six, internal CPU interrupts are: + * + * 6 Timer0 - Priority 1 + * 7 Software - Priority 1 + * 11 Profiling - Priority 3 + * 15 Timer1 - Priority 3 + * 16 Timer2 - Priority 5 + * 29 Software - Priority 3 + * + * A peripheral interrupt can be disabled + */ + +#define ESP32S2_CPUINT_LEVELPERIPH_0 0 +#define ESP32S2_CPUINT_LEVELPERIPH_1 1 +#define ESP32S2_CPUINT_LEVELPERIPH_2 2 +#define ESP32S2_CPUINT_LEVELPERIPH_3 3 +#define ESP32S2_CPUINT_LEVELPERIPH_4 4 +#define ESP32S2_CPUINT_LEVELPERIPH_5 5 +#define ESP32S2_CPUINT_LEVELPERIPH_6 8 +#define ESP32S2_CPUINT_LEVELPERIPH_7 9 +#define ESP32S2_CPUINT_LEVELPERIPH_8 12 +#define ESP32S2_CPUINT_LEVELPERIPH_9 13 +#define ESP32S2_CPUINT_LEVELPERIPH_10 17 +#define ESP32S2_CPUINT_LEVELPERIPH_11 18 +#define ESP32S2_CPUINT_LEVELPERIPH_12 19 +#define ESP32S2_CPUINT_LEVELPERIPH_13 20 +#define ESP32S2_CPUINT_LEVELPERIPH_14 21 +#define ESP32S2_CPUINT_LEVELPERIPH_15 23 +#define ESP32S2_CPUINT_LEVELPERIPH_16 24 +#define ESP32S2_CPUINT_LEVELPERIPH_17 25 +#define ESP32S2_CPUINT_LEVELPERIPH_18 26 +#define ESP32S2_CPUINT_LEVELPERIPH_19 27 +#define ESP32S2_CPUINT_LEVELPERIPH_20 31 + +#define ESP32S2_CPUINT_NLEVELPERIPHS 21 +#define EPS32_CPUINT_LEVELSET 0x8fbe333f + +#define ESP32S2_CPUINT_EDGEPERIPH_0 10 +#define ESP32S2_CPUINT_EDGEPERIPH_1 22 +#define ESP32S2_CPUINT_EDGEPERIPH_2 28 +#define ESP32S2_CPUINT_EDGEPERIPH_3 30 + +#define ESP32S2_CPUINT_NEDGEPERIPHS 4 +#define EPS32_CPUINT_EDGESET 0x50400400 + +#define ESP32S2_CPUINT_NNMIPERIPHS 1 +#define EPS32_CPUINT_NMISET 0x00004000 + +#define ESP32S2_CPUINT_MAC 0 +#define ESP32S2_CPUINT_TIMER0 6 +#define ESP32S2_CPUINT_SOFTWARE0 7 +#define ESP32S2_CPUINT_PROFILING 11 +#define ESP32S2_CPUINT_TIMER1 15 +#define ESP32S2_CPUINT_TIMER2 16 +#define ESP32S2_CPUINT_SOFTWARE1 29 + +#define ESP32S2_CPUINT_NINTERNAL 6 + +#define ESP32S2_NCPUINTS 32 +#define ESP32S2_CPUINT_MAX (ESP32S2_NCPUINTS - 1) +#define ESP32_CPUINT_PERIPHSET 0xdffe773f +#define EPS32_CPUINT_INTERNALSET 0x200188c0 + +/* Priority 1: 0-10, 12-13, 17-18 (15) + * Priority 2: 19-21 (3) + * Priority 3: 11, 15, 22-23, 27, 29 (6) + * Priority 4: 24-25, 28, 30 (4) + * Priority 5: 16, 26, 31 (3) + * Priority NMI: 14 (1) + */ + +#define ESP32S2_INTPRI1_MASK 0x000637ff +#define ESP32S2_INTPRI2_MASK 0x00380000 +#define ESP32S2_INTPRI3_MASK 0x28c08800 +#define ESP32S2_INTPRI4_MASK 0x53000000 +#define ESP32S2_INTPRI5_MASK 0x84010000 +#define ESP32S2_INTNMI_MASK 0x00004000 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H */ diff --git a/arch/xtensa/include/esp32s2/tie-asm.h b/arch/xtensa/include/esp32s2/tie-asm.h new file mode 100644 index 00000000000..bc2ebb565d1 --- /dev/null +++ b/arch/xtensa/include/esp32s2/tie-asm.h @@ -0,0 +1,150 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/tie-asm.h + * Compile-time assembler definitions dependent on CORE & TIE + * + * This header file contains assembly-language definitions (assembly + * macros, etc.) for this specific Xtensa processor's TIE extensions + * and options. It is customized to this Xtensa processor configuration. + * + * Customer ID=11657; Build=0x5fe96; + * Copyright (c) 1999-2016 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H +#define __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Selection parameter values for save-area save/restore macros: */ + +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ + +/* Whether used automatically by compiler: */ + +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ + +/* ABI handling across function calls: */ + +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ + +/* Misc */ + +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + +/* Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first + * XCHAL_NCP_NUM_ATMPS registers are clobbered, the + * remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, + * set to 1 if this is not the first in the sequence. + * Defaults to 0. + * ofs Offset from start of larger sequence (from value of first + * ptr in sequence) at which to store. Defaults to next + * available space (or 0 if is 0). + * select Select what category(ies) of registers to store, as a + * bitmask (see XTHAL_SAS_xxx constants). Defaults to all + * registers. + * alloc Select what category(ies) of registers to allocate; if + * any category is selected here that is not in , + * space for the corresponding registers is skipped without + * doing any load. + */ + +.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + + /* Optional global registers used by default by the compiler: */ + + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.THREADPTR \at1 /* threadptr option */ + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif +.endm /* xchal_ncp_load */ + +#define XCHAL_NCP_NUM_ATMPS 1 + +#define XCHAL_SA_NUM_ATMPS 1 + +#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H */ diff --git a/arch/xtensa/include/esp32s2/tie.h b/arch/xtensa/include/esp32s2/tie.h new file mode 100644 index 00000000000..92208ee5c2f --- /dev/null +++ b/arch/xtensa/include/esp32s2/tie.h @@ -0,0 +1,194 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/tie.h + * Compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + * + * This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * + * Customer ID=11657; Build=0x5fe96; + * Copyright (c) 1999-2016 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H +#define _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ + +#define XCHAL_CP0_NAME "FPU" +#define XCHAL_CP0_IDENT FPU +#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ +#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */ +#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ + +#define XCHAL_CP1_SA_SIZE 0 +#define XCHAL_CP1_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ + +#define XCHAL_NCP_SA_SIZE 48 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ + +#define XCHAL_TOTAL_SA_SIZE 128 /* With 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* Actual minimum alignment */ + +/* Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 12 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 18 +#define XCHAL_CP0_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0) + +#define XCHAL_CP1_SA_NUM 0 +#define XCHAL_CP1_SA_LIST(s) /* empty */ + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ + +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +/* Byte length of instruction from its first byte, per FLIX. */ + +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /* _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H */ diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 5ab20c64e2a..d4622a8ed9a 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -55,6 +55,17 @@ # error Unknown LX6 implementation # endif +#elif CONFIG_ARCH_FAMILY_LX7 +# include + +/* Include implementation-specific IRQ definitions (including IRQ numbers) */ + +# ifdef CONFIG_ARCH_CHIP_ESP32S2 +# include +# else +# error Unknown LX7 implementation +# endif + #else # error Unknown XTENSA architecture #endif @@ -89,7 +100,7 @@ #define _REG_LOOPS_START (21) -#ifdef XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_LOOPS != 0 # define REG_LBEG (_REG_LOOPS_START + 0) # define REG_LEND (_REG_LOOPS_START + 1) # define REG_LCOUNT (_REG_LOOPS_START + 2) @@ -192,7 +203,11 @@ static inline void xtensa_setps(uint32_t ps) { __asm__ __volatile__ ( - "wsr %0, PS" : : "r"(ps) + "wsr %0, PS \n" + "rsync \n" + : + : "r"(ps) + : "memory" ); } @@ -202,7 +217,11 @@ static inline void up_irq_restore(uint32_t ps) { __asm__ __volatile__ ( - "wsr %0, PS" : : "r"(ps) + "wsr %0, PS \n" + "rsync \n" + : + : "r"(ps) + : "memory" ); } diff --git a/arch/xtensa/include/lx7/irq.h b/arch/xtensa/include/lx7/irq.h new file mode 100644 index 00000000000..222aebd46c2 --- /dev/null +++ b/arch/xtensa/include/lx7/irq.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * arch/xtensa/include/lx7/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_LX7_IRQ_H +#define __ARCH_XTENSA_INCLUDE_LX7_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_LX7_IRQ_H */ diff --git a/arch/xtensa/include/xtensa/xtensa_coproc.h b/arch/xtensa/include/xtensa/xtensa_coproc.h index ecce93b2f24..0855b0cb508 100644 --- a/arch/xtensa/include/xtensa/xtensa_coproc.h +++ b/arch/xtensa/include/xtensa/xtensa_coproc.h @@ -38,7 +38,7 @@ * Included Files ****************************************************************************/ -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/Makefile b/arch/xtensa/src/Makefile index aa6cfd18c17..36b4e83c4b4 100644 --- a/arch/xtensa/src/Makefile +++ b/arch/xtensa/src/Makefile @@ -25,6 +25,10 @@ ifeq ($(CONFIG_ARCH_FAMILY_LX6),y) ARCH_SUBDIR = lx6 endif +ifeq ($(CONFIG_ARCH_FAMILY_LX7),y) +ARCH_SUBDIR = lx7 +endif + ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip} diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 70d3ed9fbfc..63eb4f1c9df 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -311,8 +311,8 @@ void xtensa_add_region(void); /* Serial output */ void up_lowputc(char ch); -void xtensa_early_serial_initialize(void); -void xtensa_serial_initialize(void); +void xtensa_earlyserialinit(void); +void xtensa_serialinit(void); void rpmsg_serialinit(void); diff --git a/arch/xtensa/src/common/xtensa_blocktask.c b/arch/xtensa/src/common/xtensa_blocktask.c index 76005c96b51..5a8c128e797 100644 --- a/arch/xtensa/src/common/xtensa_blocktask.c +++ b/arch/xtensa/src/common/xtensa_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index decef96f920..f3e1a8e9eef 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -138,7 +138,7 @@ _xtensa_context_save: rsr a3, SAR s32i a3, a2, (4 * REG_SAR) -#ifdef XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_LOOPS != 0 rsr a3, LBEG s32i a3, a2, (4 * REG_LBEG) rsr a3, LEND @@ -344,7 +344,7 @@ _xtensa_save_hook: rsr a3, SAR s32i a3, a2, (4 * REG_SAR) -#ifdef XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_LOOPS != 0 rsr a3, LBEG s32i a3, a2, (4 * REG_LBEG) rsr a3, LEND @@ -449,7 +449,7 @@ xtensa_context_save: _xtensa_context_restore: -#ifdef XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_LOOPS != 0 l32i a3, a2, (4 * REG_LBEG) l32i a4, a2, (4 * REG_LEND) wsr a3, LBEG diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 3b2b6bfe24a..686f6c281c4 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -128,7 +128,7 @@ _xtensa_coproc_savestate: bbci.l a2, 0, 2f /* CP 0 not enabled */ l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL + xchal_ncp_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif @@ -327,7 +327,7 @@ _xtensa_coproc_restorestate: bbci.l a2, 0, 2f /* CP 0 not enabled */ l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL + xchal_ncp_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif diff --git a/arch/xtensa/src/common/xtensa_counter.h b/arch/xtensa/src/common/xtensa_counter.h new file mode 100644 index 00000000000..3228459cb6d --- /dev/null +++ b/arch/xtensa/src/common/xtensa_counter.h @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_counter.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_COUNTER_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_COUNTER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "xtensa_timer.h" + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_getcount + * + * Description: + * Get the current value of the cycle count register. + * + ****************************************************************************/ + +static inline uint32_t xtensa_getcount(void) +{ + uint32_t count; + + __asm__ __volatile__ + ( + "rsr %0, CCOUNT" : "=r"(count) + ); + + return count; +} + +/**************************************************************************** + * Name: xtensa_setcount + * + * Description: + * Set the value of the cycle count register. + * + ****************************************************************************/ + +static inline void xtensa_setcount(uint32_t ticks) +{ + __asm__ __volatile__ + ( + "wsr %0, ccount\n" + : + : "a"(ticks) + : "memory" + ); +} + +/**************************************************************************** + * Name: xtensa_getcompare + * + * Description: + * Get the old value of the compare register. + * + ****************************************************************************/ + +static inline uint32_t xtensa_getcompare(void) +{ + uint32_t compare; + + __asm__ __volatile__ + ( + "rsr %0, %1" : "=r"(compare) : "I"(XT_CCOMPARE) + ); + + return compare; +} + +/**************************************************************************** + * Name: xtensa_getcompare + * + * Description: + * Set the value of the compare register. + * + ****************************************************************************/ + +static inline void xtensa_setcompare(uint32_t compare) +{ + __asm__ __volatile__ + ( + "wsr %0, %1" : : "r"(compare), "I"(XT_CCOMPARE) + ); +} + +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_COUNTER_H */ diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_cpupause.c index bb98e3741a4..228bc3ecf21 100644 --- a/arch/xtensa/src/common/xtensa_cpupause.c +++ b/arch/xtensa/src/common/xtensa_cpupause.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index ddc6619970b..ef7a5469015 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 17929f099cf..f94fc336c2d 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -140,7 +140,7 @@ static inline void xtensa_registerdump(void) _alert(" SAR: %08lx CAUSE: %08lx VADDR: %08lx\n", (unsigned long)regs[REG_SAR], (unsigned long)regs[REG_EXCCAUSE], (unsigned long)regs[REG_EXCVADDR]); -#ifdef XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_LOOPS != 0 _alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n", (unsigned long)regs[REG_LBEG], (unsigned long)regs[REG_LEND], (unsigned long)regs[REG_LCOUNT]); diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index dd380f5c403..a098d96365f 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -181,7 +181,7 @@ void up_initialize(void) /* Initialize the serial device driver */ #ifdef USE_SERIALDRIVER - xtensa_serial_initialize(); + xtensa_serialinit(); #endif #ifdef CONFIG_RPMSG_UART diff --git a/arch/xtensa/src/common/xtensa_reprioritizertr.c b/arch/xtensa/src/common/xtensa_reprioritizertr.c index 2b9f74c69f1..ba100bd834a 100644 --- a/arch/xtensa/src/common/xtensa_reprioritizertr.c +++ b/arch/xtensa/src/common/xtensa_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c index 4f0fb70c05c..fc5f399424c 100644 --- a/arch/xtensa/src/common/xtensa_schedsigaction.c +++ b/arch/xtensa/src/common/xtensa_schedsigaction.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/xtensa/src/common/xtensa_sigdeliver.c b/arch/xtensa/src/common/xtensa_sigdeliver.c index 94a248455b7..d01d8bbb86e 100644 --- a/arch/xtensa/src/common/xtensa_sigdeliver.c +++ b/arch/xtensa/src/common/xtensa_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/xtensa/src/common/xtensa_testset.c b/arch/xtensa/src/common/xtensa_testset.c index 94780357c52..8853c98375c 100644 --- a/arch/xtensa/src/common/xtensa_testset.c +++ b/arch/xtensa/src/common/xtensa_testset.c @@ -57,7 +57,6 @@ static inline uint32_t xtensa_compareset(FAR volatile uint32_t *addr, __asm__ __volatile__ ( "WSR %2, SCOMPARE1\n" /* Initialize SCOMPARE1 */ - "ISYNC\n" /* Wait sync */ "S32C1I %0, %1, 0\n" /* Store id into the lock, if the lock is the * same as comparel. Otherwise, no write-access */ : "=r"(set) : "r"(addr), "r"(compare), "0"(set) diff --git a/arch/xtensa/src/common/xtensa_unblocktask.c b/arch/xtensa/src/common/xtensa_unblocktask.c index 0a04b06c01c..a1e42a0c1c1 100644 --- a/arch/xtensa/src/common/xtensa_unblocktask.c +++ b/arch/xtensa/src/common/xtensa_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index 25ed1efc4fd..e7b470a5133 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -311,7 +311,7 @@ _xtensa_syscall_handler: /* Save EPC */ -#ifdef XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_LOOPS != 0 /* Save A2 and A3 now to give us some registers to work with. A0, A2 * and A3 are now available. NOTE that A3 will get saved again in * _xtensa_context_save(). diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c index 6371bf5d43c..84657a9b5f3 100644 --- a/arch/xtensa/src/common/xtensa_usestack.c +++ b/arch/xtensa/src/common/xtensa_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index a0a5f396aed..55fc67ee595 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -211,9 +211,48 @@ config ESP32_XTAL_26MHz endchoice # On-board Crystal Frequency +choice ESP32_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32_RTC_CLK_SRC_INT_RC + ---help--- + Choose which clock is used as RTC clock source. + + - "Internal 150kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8.5MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 150kHz oscillator. It does not require external components. + + config ESP32_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + + config ESP32_RTC_CLK_SRC_EXT_XTAL + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + + config ESP32_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + + config ESP32_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" + +endchoice + config ESP32_RT_TIMER bool "Real-time Timer" default n + select ESP32_TIMER0 config ESP32_PARTITION bool "ESP32 Partition" @@ -230,6 +269,16 @@ config ESP32_RUN_IRAM This loads all of NuttX inside IRAM. Used to test somewhat small images that can fit entirely in IRAM. +config ESP32_RTC_HEAP + bool "Use the RTC memory as a separate heap" + select ARCH_HAVE_EXTRA_HEAPS + default n + +config ESP32_IRAM_HEAP + bool "Use the rest of IRAM as a separate heap" + select ARCH_HAVE_EXTRA_HEAPS + default n + menu "ESP32 Peripheral Selection" config ESP32_UART @@ -521,18 +570,23 @@ config ESP32_UART0_RXPIN default 3 range 0 39 -if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL config ESP32_UART0_RTSPIN int "UART0 RTS Pin" + depends on SERIAL_IFLOWCONTROL default 22 range 0 39 config ESP32_UART0_CTSPIN int "UART0 CTS Pin" - default 19 + depends on SERIAL_OFLOWCONTROL + default 23 range 0 39 -endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32_UART0_TXDMA + bool "Enable UART0 TX DMA" + select ARCH_DMA + select UART0_TXDMA + endif # ESP32_UART0 if ESP32_UART1 @@ -547,19 +601,22 @@ config ESP32_UART1_RXPIN default 9 range 0 39 -if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL - config ESP32_UART1_RTSPIN int "UART1 RTS Pin" + depends on SERIAL_IFLOWCONTROL default 11 range 0 39 config ESP32_UART1_CTSPIN int "UART1 CTS Pin" + depends on SERIAL_OFLOWCONTROL default 6 range 0 39 -endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32_UART1_TXDMA + bool "Enable UART1 TX DMA" + select ARCH_DMA + select UART1_TXDMA endif # ESP32_UART1 @@ -567,30 +624,58 @@ if ESP32_UART2 config ESP32_UART2_TXPIN int "UART2 Tx Pin" - default 17 + default 19 range 0 39 config ESP32_UART2_RXPIN int "UART2 Rx Pin" - default 16 + default 18 range 0 39 -if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL - config ESP32_UART2_RTSPIN int "UART2 RTS Pin" + depends on SERIAL_IFLOWCONTROL default 7 range 0 39 config ESP32_UART2_CTSPIN int "UART2 CTS Pin" + depends on SERIAL_OFLOWCONTROL default 8 range 0 39 -endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32_UART2_TXDMA + bool "Enable UART2 TX DMA" + select ARCH_DMA + select UART2_TXDMA endif # ESP32_UART2 +choice + prompt "UART with exclusive DMA" + default ESP32_UART0_EXC + depends on ESP32_UART0_TXDMA && ESP32_UART1_TXDMA && ESP32_UART2_TXDMA + ---help--- + The three UARTs from ESP32 share 2 DMA channels. + Select which UART should have exclusive access to + a DMA channel. + +config ESP32_UART0_EXC + bool "UART 0" + +config ESP32_UART1_EXC + bool "UART 1" + +config ESP32_UART2_EXC + bool "UART 2" + +endchoice + +config UART_DMADESC_NUM + int "UART DMA descriptor list size" + depends on SERIAL_TXDMA + default 2 + endmenu # UART configuration menu "I2C configuration" @@ -971,6 +1056,34 @@ config ESP32_WIFI_STA_DISCONNECT_PM Select this option to enable power management for station when disconnected. Chip will do modem-sleep when RF module is not in use anymore. +config EXAMPLE_WIFI_LISTEN_INTERVAL + int "Wi-Fi listen interval" + default 3 + ---help--- + Interval for station to listen to beacon from AP. The unit of listen interval is one beacon interval. + For example, if beacon interval is 100 ms and listen interval is 3, the interval for station to listen + to beacon is 300 ms. + +choice EXAMPLE_POWER_SAVE_MODE + prompt "Power save mode" + default EXAMPLE_POWER_SAVE_NONE + ---help--- + Power save mode for the esp32 to use. Modem sleep mode includes minimum and maximum power save modes. + In minimum power save mode, station wakes up every DTIM to receive beacon. Broadcast data will not be + lost because it is transmitted after DTIM. However, it can not save much more power if DTIM is short + for DTIM is determined by AP. + In maximum power save mode, station wakes up every listen interval to receive beacon. Broadcast data + may be lost because station may be in sleep state at DTIM time. If listen interval is longer, more power + is saved but broadcast data is more easy to lose. + + config EXAMPLE_POWER_SAVE_NONE + bool "none" + config EXAMPLE_POWER_SAVE_MIN_MODEM + bool "minimum modem" + config EXAMPLE_POWER_SAVE_MAX_MODEM + bool "maximum modem" +endchoice + endmenu # ESP32_WIRELESS menu "Real-Time Timer" @@ -1035,4 +1148,20 @@ config ESP32_AES_ACCELERATOR_TEST endmenu # ESP32_AES_ACCELERATOR +config ESP32_AUTO_SLEEP + bool "Auto-sleep" + default n + select PM + select ESP32_RT_TIMER + select ESP32_TIMER0 + select ESP32_TICKLESS + ---help--- + Enable ESP32 Auto-sleep + +config ESP32_TICKLESS + bool "Enable ESP32 tickless OS" + default n + select ARCH_HAVE_TICKLESS + select SCHED_TICKLESS + endif # ARCH_CHIP_ESP32 diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 6696776ba05..89ac4fa68de 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -75,10 +75,15 @@ endif CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c -CHIP_CSRCS += esp32_timerisr.c CHIP_CSRCS += esp32_user.c CHIP_CSRCS += esp32_dma.c +ifeq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += esp32_tickless.c +else +CHIP_CSRCS += esp32_timerisr.c +endif + ifeq ($(CONFIG_PM),y) ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) CHIP_CSRCS += esp32_pminitialize.c @@ -175,8 +180,20 @@ CHIP_CSRCS += esp32_wdt_lowerhalf.c endif endif -ifeq ($(CONFIG_ARCH_USE_MODULE_TEXT),y) -CHIP_CSRCS += esp32_modtext.c +ifeq ($(CONFIG_ARCH_HAVE_EXTRA_HEAPS),y) +CHIP_CSRCS += esp32_extraheaps.c +endif + +ifeq ($(CONFIG_ESP32_RTC_HEAP),y) +CHIP_CSRCS += esp32_rtcheap.c +endif + +ifeq ($(CONFIG_ESP32_IRAM_HEAP),y) +CHIP_CSRCS += esp32_iramheap.c +endif + +ifeq ($(CONFIG_ARCH_USE_TEXT_HEAP),y) +CHIP_CSRCS += esp32_textheap.c CMN_ASRCS += xtensa_loadstore.S endif @@ -188,6 +205,10 @@ ifeq ($(CONFIG_ESP32_AES_ACCELERATOR),y) CHIP_CSRCS += esp32_aes.c endif +ifeq ($(CONFIG_RTC_DRIVER),y) +CHIP_CSRCS += esp32_rtc_lowerhalf.c +endif + ifeq ($(CONFIG_ESP32_WIRELESS),y) WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty WIRELESS_DRV_ID = 2b53111 diff --git a/arch/xtensa/src/esp32/chip_macros.h b/arch/xtensa/src/esp32/chip_macros.h index c8f2d85b622..a38e3483fd5 100644 --- a/arch/xtensa/src/esp32/chip_macros.h +++ b/arch/xtensa/src/esp32/chip_macros.h @@ -68,19 +68,14 @@ #ifdef __ASSEMBLY__ /* Macro to get the current core ID. Only uses the reg given as an argument. - * Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO - * processor and 0xabab on the APP CPU. We distinguish between the two by - * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor. + * Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0) + * and 0xABAB on the APP CPU (1). We can distinguish between the two by + * checking bit 13: it's 1 on the APP and 0 on the PRO processor. */ - .macro getcoreid reg - rsr.prid \reg - bbci \reg, 1, 1f - movi \reg, 1 - j 2f -1: - movi \reg, 0 -2: + .macro getcoreid reg + rsr.prid \reg + extui \reg,\reg,13,1 .endm /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_aes.c b/arch/xtensa/src/esp32/esp32_aes.c index 8fe0d0b6ab6..a04415fe6cf 100644 --- a/arch/xtensa/src/esp32/esp32_aes.c +++ b/arch/xtensa/src/esp32/esp32_aes.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -652,7 +653,7 @@ int aes_cypher(FAR void *out, FAR const void *in, uint32_t size, * Name: esp32_aes_ecb_test ****************************************************************************/ -static void esp32_aes_ecb_test(void) +static bool esp32_aes_ecb_test(void) { int ret; int i; @@ -702,33 +703,46 @@ static void esp32_aes_ecb_test(void) keybits = i * 64 + 128; ret = esp32_aes_setkey(&aes, key, keybits); - DEBUGASSERT(ret == 0); + if (ret < 0) + { + return false; + } ret = esp32_aes_ecb_cypher(&aes, 1, input, encrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(encrypt_buf, result[i], size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(encrypt_buf, result[i], size); + if (ret) + { + return false; } ret = esp32_aes_ecb_cypher(&aes, 0, encrypt_buf, decrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(decrypt_buf, input, size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; } syslog(LOG_INFO, "ESP32 AES ECB key=%d bits test: PASS\n", keybits); } + + return true; } /**************************************************************************** * Name: esp32_aes_cbc_test ****************************************************************************/ -static void esp32_aes_cbc_test(void) +static bool esp32_aes_cbc_test(void) { int ret; int i; @@ -785,36 +799,49 @@ static void esp32_aes_cbc_test(void) keybits = i * 64 + 128; ret = esp32_aes_setkey(&aes, key, keybits); - DEBUGASSERT(ret == 0); + if (ret < 0) + { + return false; + } memcpy(iv_buf, iv, 16); ret = esp32_aes_cbc_cypher(&aes, 1, iv_buf, input, encrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(encrypt_buf, result[i], size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(encrypt_buf, result[i], size); + if (ret) + { + return false; } memcpy(iv_buf, iv, 16); ret = esp32_aes_cbc_cypher(&aes, 0, iv_buf, encrypt_buf, decrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(decrypt_buf, input, size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; } syslog(LOG_INFO, "ESP32 AES CBC key=%d bits test: PASS\n", keybits); } + + return true; } /**************************************************************************** - * Name: esp32_aes_cbc_test + * Name: esp32_aes_ctr_test ****************************************************************************/ -static void esp32_aes_ctr_test(void) +static bool esp32_aes_ctr_test(void) { int ret; int i; @@ -873,39 +900,52 @@ static void esp32_aes_ctr_test(void) keybits = i * 64 + 128; ret = esp32_aes_setkey(&aes, key, keybits); - DEBUGASSERT(ret == 0); + if (ret < 0) + { + return false; + } nc_off = 0; memcpy(cnt_buf, cnt, 16); ret = esp32_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, input, encrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(encrypt_buf, result[i], size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(encrypt_buf, result[i], size); + if (ret) + { + return false; } nc_off = 0; memcpy(cnt_buf, cnt, 16); ret = esp32_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, encrypt_buf, decrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(decrypt_buf, input, size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; } syslog(LOG_INFO, "ESP32 AES CTR key=%d bits test: PASS\n", keybits); } + + return true; } /**************************************************************************** * Name: esp32_aes_xts_test ****************************************************************************/ -static void esp32_aes_xts_test(void) +static bool esp32_aes_xts_test(void) { int ret; int i; @@ -974,7 +1014,10 @@ static void esp32_aes_xts_test(void) keybits = i * 256 + 256; ret = esp32_aes_xts_setkey(&aes, key, keybits); - DEBUGASSERT(ret == 0); + if (ret < 0) + { + return false; + } /* Encrypt/Decrypt 32 bytes */ @@ -983,21 +1026,29 @@ static void esp32_aes_xts_test(void) memcpy(unit_buf, unit, 16); ret = esp32_aes_xts_cypher(&aes, true, unit_buf, input, encrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(encrypt_buf, result_in32[i], size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(encrypt_buf, result_in32[i], size); + if (ret) + { + return false; } memcpy(unit_buf, unit, 16); ret = esp32_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, decrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(decrypt_buf, input, size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(decrypt_buf, input, size); + if (ret) + { + return false; } /* Encrypt/Decrypt 30 bytes */ @@ -1007,25 +1058,35 @@ static void esp32_aes_xts_test(void) memcpy(unit_buf, unit, 16); ret = esp32_aes_xts_cypher(&aes, true, unit_buf, input, encrypt_buf, size); - DEBUGASSERT(ret == 0); - - if (memcmp(encrypt_buf, result_in30[i], size)) + if (ret < 0) { - DEBUGASSERT(0); + return false; + } + + ret = memcmp(encrypt_buf, result_in30[i], size); + if (ret) + { + return false; } memcpy(unit_buf, unit, 16); ret = esp32_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, decrypt_buf, size); - DEBUGASSERT(ret == 0); + if (ret < 0) + { + return false; + } - if (memcmp(decrypt_buf, input, size)) + ret = memcmp(decrypt_buf, input, size); + if (ret) { DEBUGASSERT(0); } syslog(LOG_INFO, "ESP32 AES XTS key=%d bits test: PASS\n", keybits); } + + return true; } /**************************************************************************** @@ -1034,16 +1095,44 @@ static void esp32_aes_xts_test(void) int esp32_aes_main(int argc, char *argv[]) { + bool success; + + syslog(LOG_INFO, "----- BEGIN TEST -----\n"); + esp32_aes_init(); - esp32_aes_ecb_test(); - esp32_aes_cbc_test(); - esp32_aes_ctr_test(); - esp32_aes_xts_test(); + success = esp32_aes_ecb_test(); + if (!success) + { + goto test_end; + } - syslog(LOG_INFO, "\nESP32 AES hardware accelerate test done.\n"); + success = esp32_aes_cbc_test(); + if (!success) + { + goto test_end; + } + + success = esp32_aes_ctr_test(); + if (!success) + { + goto test_end; + } + + success = esp32_aes_xts_test(); + if (!success) + { + goto test_end; + } + +test_end: + syslog(LOG_INFO, "----- END TEST -----\n"); + + syslog(LOG_INFO, "\n"); + + syslog(LOG_INFO, "----- RESULT: %s -----\n", + success ? "SUCCESS" : "FAILED"); return 0; } - #endif diff --git a/arch/xtensa/src/esp32/esp32_allocateheap.c b/arch/xtensa/src/esp32/esp32_allocateheap.c index a39429ffa2d..c0b806ac679 100644 --- a/arch/xtensa/src/esp32/esp32_allocateheap.c +++ b/arch/xtensa/src/esp32/esp32_allocateheap.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index fefa0a91822..b7c941c7261 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -170,10 +170,10 @@ static uint32_t g_intenable[1]; * devices. */ -static uint32_t g_cpu0_freeints = EPS32_CPUINT_PERIPHSET & +static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET & (~ESP32_WIRELESS_RESERVE_INT); #ifdef CONFIG_SMP -static uint32_t g_cpu1_freeints = EPS32_CPUINT_PERIPHSET & +static uint32_t g_cpu1_freeints = ESP32_CPUINT_PERIPHSET & (~ESP32_WIRELESS_RESERVE_INT); #endif @@ -465,7 +465,7 @@ int esp32_alloc_levelint(int priority) * interrupt priority. */ - intmask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET; + intmask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_LEVELSET; return esp32_alloc_cpuint(intmask); } @@ -497,7 +497,7 @@ int esp32_alloc_edgeint(int priority) * interrupt priority. */ - intmask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET; + intmask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_EDGESET; return esp32_alloc_cpuint(intmask); } diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 9324c345380..acd112e971a 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_emac.c b/arch/xtensa/src/esp32/esp32_emac.c index c9dfcca2ca8..5f055b3ec9e 100644 --- a/arch/xtensa/src/esp32/esp32_emac.c +++ b/arch/xtensa/src/esp32/esp32_emac.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -2113,7 +2114,7 @@ static int emac_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { /* Enable PHY link up/down interrupts */ - ret = phy_enable_interrupt(priv); + ret = phy_enable_interrupt(); } } break; diff --git a/arch/xtensa/src/esp32/esp32_extraheaps.c b/arch/xtensa/src/esp32/esp32_extraheaps.c new file mode 100644 index 00000000000..9b0caac9576 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_extraheaps.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_extraheaps.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "hardware/esp32_soc.h" + +#ifdef CONFIG_ESP32_IRAM_HEAP +#include "esp32_iramheap.h" +#endif + +#ifdef CONFIG_ESP32_RTC_HEAP +#include "esp32_rtcheap.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_extraheaps_init + * + * Description: + * Initialize any extra heap. + * + ****************************************************************************/ + +void up_extraheaps_init(void) +{ +#ifdef CONFIG_ESP32_RTC_HEAP + esp32_rtcheap_initialize(); +#endif + +#ifdef CONFIG_ESP32_IRAM_HEAP + esp32_iramheap_initialize(); +#endif +} + diff --git a/arch/xtensa/src/esp32/esp32_himem.c b/arch/xtensa/src/esp32/esp32_himem.c index 269a2eba13e..2cff1f98e83 100644 --- a/arch/xtensa/src/esp32/esp32_himem.c +++ b/arch/xtensa/src/esp32/esp32_himem.c @@ -23,6 +23,7 @@ ****************************************************************************/ #include +#include #include #include #include diff --git a/arch/xtensa/src/esp32/esp32_i2c.c b/arch/xtensa/src/esp32/esp32_i2c.c index a991c5581a2..28ecac715af 100644 --- a/arch/xtensa/src/esp32/esp32_i2c.c +++ b/arch/xtensa/src/esp32/esp32_i2c.c @@ -31,9 +31,11 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -70,6 +72,12 @@ ((_ack_val) << 10) + \ (_bytes)) +/* Helper */ + +#ifdef CONFIG_I2C_POLLED +#define TIMESPEC_TO_US(sec, nano) ((sec * USEC_PER_SEC) + (nano / NSEC_PER_USEC)) +#endif + /* Default option */ #define I2C_FIFO_SIZE (255) @@ -83,6 +91,8 @@ I2C_ARBITRATION_LOST_INT_ENA | \ I2C_RXFIFO_OVF_INT_ENA) +#define I2C_SCL_CYC_NUM_DEF 9 + /* I2C event trace logic. * NOTE: trace uses the internal, non-standard, low-level debug interface * syslog() but does not require that any other debug is enabled. @@ -106,7 +116,9 @@ enum esp32_i2cstate_e I2CSTATE_IDLE = 0, I2CSTATE_PROC, I2CSTATE_STOP, +#ifndef CONFIG_I2C_POLLED I2CSTATE_FINISH +#endif }; /* I2C hardware command */ @@ -159,9 +171,11 @@ struct esp32_i2c_config_s uint8_t scl_pin; /* GPIO configuration for SCL as SCL */ uint8_t sda_pin; /* GPIO configuration for SDA as SDA */ +#ifndef CONFIG_I2C_POLLED uint8_t cpu; /* CPU ID */ - uint8_t periph; /* peripher ID */ + uint8_t periph; /* Peripheral ID */ uint8_t irq; /* Interrupt ID */ +#endif uint32_t clk_bit; /* Clock enable bit */ uint32_t rst_bit; /* I2C reset bit */ @@ -182,9 +196,12 @@ struct esp32_i2c_priv_s /* Port configuration */ const struct esp32_i2c_config_s *config; - int refs; /* Referernce count */ + int refs; /* Reference count */ sem_t sem_excl; /* Mutual exclusion semaphore */ + +#ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ +#endif /* I2C work state (see enum esp32_i2cstate_e) */ @@ -195,11 +212,13 @@ struct esp32_i2c_priv_s uint8_t msgid; /* Current message ID */ ssize_t bytes; /* Processed data bytes */ +#ifndef CONFIG_I2C_POLLED int cpuint; /* CPU interrupt assigned to this I2C */ +#endif uint32_t error; /* I2C transform error */ - bool ready_read; /* If I2C has can read date */ + bool ready_read; /* If I2C has read data */ uint32_t clk_freq; /* Current I2C Clock frequency */ @@ -226,6 +245,11 @@ static void esp32_i2c_deinit(FAR struct esp32_i2c_priv_s *priv); static int esp32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count); +static inline void esp32_i2c_process(struct esp32_i2c_priv_s *priv, + uint32_t status); +#ifdef CONFIG_I2C_POLLED +static int esp32_i2c_polling_waitdone(FAR struct esp32_i2c_priv_s *priv); +#endif #ifdef CONFIG_I2C_RESET static int esp32_i2c_reset(FAR struct i2c_master_s *dev); #endif @@ -264,9 +288,11 @@ static const struct esp32_i2c_config_s esp32_i2c0_config = .clk_freq = I2C_CLK_FREQ_DEF, .scl_pin = CONFIG_ESP32_I2C0_SCLPIN, .sda_pin = CONFIG_ESP32_I2C0_SDAPIN, +#ifndef CONFIG_I2C_POLLED .cpu = 0, .periph = ESP32_PERIPH_I2C_EXT0, .irq = ESP32_IRQ_I2C_EXT0, +#endif .clk_bit = DPORT_I2C_EXT0_CLK_EN, .rst_bit = DPORT_I2C_EXT0_RST, .scl_insig = I2CEXT0_SCL_IN_IDX, @@ -295,9 +321,11 @@ static const struct esp32_i2c_config_s esp32_i2c1_config = .clk_freq = I2C_CLK_FREQ_DEF, .scl_pin = CONFIG_ESP32_I2C1_SCLPIN, .sda_pin = CONFIG_ESP32_I2C1_SDAPIN, +#ifndef CONFIG_I2C_POLLED .cpu = 0, .periph = ESP32_PERIPH_I2C_EXT1, .irq = ESP32_IRQ_I2C_EXT1, +#endif .clk_bit = DPORT_I2C_EXT1_CLK_EN, .rst_bit = DPORT_I2C_EXT1_RST, .scl_insig = I2CEXT1_SCL_IN_IDX, @@ -414,16 +442,29 @@ static void esp32_i2c_sendstart(FAR struct esp32_i2c_priv_s *priv) { struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; + /* Load a start cmd, write and end in controller. */ + esp32_i2c_set_reg(priv, I2C_COMD0_OFFSET, I2C_BASE_CMD(I2C_CMD_RESTART, 0)); esp32_i2c_set_reg(priv, I2C_COMD1_OFFSET, I2C_SEND_CMD(I2C_CMD_WRITE, 1, 1)); esp32_i2c_set_reg(priv, I2C_COMD2_OFFSET, I2C_BASE_CMD(I2C_CMD_END, 0)); + + /* Load the slave address and the flags to the FIFO. */ + esp32_i2c_set_reg(priv, I2C_DATA_OFFSET, (msg->addr << 1) | (msg->flags & I2C_M_READ)); + + /* Enable interrupts to detect the execution of an end cmd and + * multiple errors. + */ + esp32_i2c_set_reg(priv, I2C_INT_ENA_OFFSET, I2C_END_DETECT_INT_ENA | I2C_INT_ERR_EN_BITS); + + /* Start sending the slave address and hold line. */ + esp32_i2c_set_reg_bits(priv, I2C_CTR_OFFSET, I2C_TRANS_START_M); } @@ -443,11 +484,15 @@ static void esp32_i2c_senddata(FAR struct esp32_i2c_priv_s *priv) n = n < I2C_FIFO_SIZE ? n : I2C_FIFO_SIZE; + /* Load a write operation */ + esp32_i2c_set_reg(priv, I2C_COMD0_OFFSET, I2C_SEND_CMD(I2C_CMD_WRITE, 1, n)); esp32_i2c_set_reg(priv, I2C_COMD1_OFFSET, I2C_BASE_CMD(I2C_CMD_END, 0)); + /* Transfer the data from the msg buffer to the TX FIFO */ + for (i = 0; i < n; i ++) { esp32_i2c_set_reg(priv, I2C_DATA_OFFSET, @@ -456,6 +501,10 @@ static void esp32_i2c_senddata(FAR struct esp32_i2c_priv_s *priv) priv->bytes += n; + /* Enable interrupts to detect the execution of an end cmd and + * multiple errors. + */ + esp32_i2c_set_reg(priv, I2C_INT_ENA_OFFSET, I2C_END_DETECT_INT_ENA | I2C_INT_ERR_EN_BITS); esp32_i2c_set_reg_bits(priv, I2C_CTR_OFFSET, I2C_TRANS_START_M); @@ -465,7 +514,7 @@ static void esp32_i2c_senddata(FAR struct esp32_i2c_priv_s *priv) * Name: esp32_i2c_recvdata * * Description: - * Receive I2C data + * Transfer the received data from the RX FIFO to the message buffer. * ****************************************************************************/ @@ -489,8 +538,9 @@ static void esp32_i2c_recvdata(struct esp32_i2c_priv_s *priv) * Name: esp32_i2c_startrecv * * Description: - * Configure I2C to prepare receiving data and it will create an interrupt - * to receive real data + * Configure I2C to prepare receiving data and it will enable an interrupt + * to detect the end of the receiving operation and to load the content + * into the RX buffer. * ****************************************************************************/ @@ -511,11 +561,17 @@ static void esp32_i2c_startrecv(struct esp32_i2c_priv_s *priv) ack_value = 1; } + /* Load read and end cmds */ + esp32_i2c_set_reg(priv, I2C_COMD0_OFFSET, I2C_RECV_CMD(I2C_CMD_READ, ack_value, n)); esp32_i2c_set_reg(priv, I2C_COMD1_OFFSET, I2C_BASE_CMD(I2C_CMD_END, 0)); + /* Enable interrupts to detect the execution of an end cmd and + * multiple errors. + */ + esp32_i2c_set_reg(priv, I2C_INT_ENA_OFFSET, I2C_END_DETECT_INT_ENA | I2C_INT_ERR_EN_BITS); esp32_i2c_set_reg_bits(priv, I2C_CTR_OFFSET, I2C_TRANS_START_M); @@ -531,6 +587,10 @@ static void esp32_i2c_startrecv(struct esp32_i2c_priv_s *priv) static void esp32_i2c_sendstop(struct esp32_i2c_priv_s *priv) { + /* Load a stop cmd and enable the interrupts that indicate end of a stop + * cmd or error. + */ + esp32_i2c_set_reg(priv, I2C_COMD0_OFFSET, I2C_BASE_CMD(I2C_CMD_STOP, 0)); esp32_i2c_set_reg(priv, I2C_INT_ENA_OFFSET, I2C_TRANS_COMPLETE_INT_ENA | I2C_INT_ERR_EN_BITS); @@ -655,24 +715,146 @@ static void esp32_i2c_reset_fsmc(FAR struct esp32_i2c_priv_s *priv) * Name: esp32_i2c_sem_waitdone * * Description: - * Wait for a transfer to complete + * Wait for a transfer to complete using an interruptible semaphore which + * in unlocked from within the ISR context. This function is only used in + * interrupt driven mode. * + * Parameters: + * priv - Pointer to the internal driver state structure. ****************************************************************************/ - +#ifndef CONFIG_I2C_POLLED static int esp32_i2c_sem_waitdone(FAR struct esp32_i2c_priv_s *priv) { int ret; struct timespec abstime; + /* Get the current absolute time and adds a offset as timeout */ + clock_gettime(CLOCK_REALTIME, &abstime); abstime.tv_sec += 10; abstime.tv_nsec += 0; + /* Wait on ISR semaphore */ + ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime); return ret; } +#endif + +/**************************************************************************** + * Name: esp32_i2c_polling_waitdone + * + * Description: + * Wait for a transfer to complete by polling status interrupt registers, + * which indicates the status of the I2C operations. This function is only + * used in polling driven mode. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + * Returned Values: + * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * in case a transfer didn't finish within the timeout interval. And ERROR + * is returned in case of any I2C error during the transfer has happened. + * + ****************************************************************************/ +#ifdef CONFIG_I2C_POLLED +static int esp32_i2c_polling_waitdone(FAR struct esp32_i2c_priv_s *priv) +{ + int ret; + struct timespec current_time; + struct timespec timeout; + uint64_t current_us; + uint64_t timeout_us; + uint32_t status = 0; + + /* Get the current absolute time and add an offset as timeout. + * Preferable to use monotonic, so in case the time changes, + * the time reference is kept, i.e., current time can't jump + * forward and backwards. + */ + + #ifdef CONFIG_CLOCK_MONOTONIC + clock_gettime(CLOCK_MONOTONIC, ¤t_time); + #else + clock_gettime(CLOCK_REALTIME, ¤t_time); + #endif + + timeout.tv_sec = current_time.tv_sec + 10; + timeout.tv_nsec = current_time.tv_nsec + 0; + + current_us = TIMESPEC_TO_US(current_time.tv_sec, current_time.tv_nsec); + timeout_us = TIMESPEC_TO_US(timeout.tv_sec, timeout.tv_nsec); + + /* Loop while a transfer is in progress + * and an error didn't occur within the timeout + */ + + while ((current_us < timeout_us) && (priv->error == 0)) + { + /* Check if any interrupt triggered, clear them + * process the operation. + */ + + status = esp32_i2c_get_reg(priv, I2C_INT_STATUS_OFFSET); + if (status != 0) + { + /* Check if the stop operation ended. Don't use + * I2CSTATE_FINISH, because it is set before the stop + * signal really ends. This works for interrupts because + * the i2c_state is checked in the next interrupt when + * stop signal has concluded. This is not the case of + * polling. + */ + + if (status & I2C_TRANS_COMPLETE_INT_ST_M) + { + esp32_i2c_set_reg(priv, I2C_INT_CLR_OFFSET, status); + break; + } + + esp32_i2c_set_reg(priv, I2C_INT_CLR_OFFSET, status); + esp32_i2c_process(priv, status); + } + + /* Update current time */ + + #ifdef CONFIG_CLOCK_MONOTONIC + clock_gettime(CLOCK_MONOTONIC, ¤t_time); + #else + clock_gettime(CLOCK_REALTIME, ¤t_time); + #endif + current_us = TIMESPEC_TO_US(current_time.tv_sec, current_time.tv_nsec); + } + + /* Return a negated value in case of timeout, and in the other scenarios + * return a positive value. + * The transfer function will check the status of priv to check the other + * scenarios. + */ + + if (current_us >= timeout_us) + { + ret = -ETIMEDOUT; + } + else if (priv->error) + { + ret = ERROR; + } + else + { + ret = OK; + } + + /* Disable all interrupts */ + + esp32_i2c_set_reg(priv, I2C_INT_ENA_OFFSET, 0); + + return ret; +} +#endif /**************************************************************************** * Name: esp32_i2c_sem_wait @@ -711,7 +893,9 @@ static void esp32_i2c_sem_post(struct esp32_i2c_priv_s *priv) static void esp32_i2c_sem_destroy(FAR struct esp32_i2c_priv_s *priv) { nxsem_destroy(&priv->sem_excl); +#ifndef CONFIG_I2C_POLLED nxsem_destroy(&priv->sem_isr); +#endif } /**************************************************************************** @@ -730,8 +914,10 @@ static inline void esp32_i2c_sem_init(FAR struct esp32_i2c_priv_s *priv) * priority inheritance enabled. */ +#ifndef CONFIG_I2C_POLLED nxsem_init(&priv->sem_isr, 0, 0); nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE); +#endif } /**************************************************************************** @@ -762,16 +948,26 @@ static int esp32_i2c_transfer(FAR struct i2c_master_s *dev, return ret; } + /* If previous state is different than idle, + * reset the fsmc to the idle state. + */ + if (priv->i2cstate != I2CSTATE_IDLE) { esp32_i2c_reset_fsmc(priv); priv->i2cstate = I2CSTATE_IDLE; } + /* Transfer the messages to the internal struct + * and loop count times to make all transfers. + */ + priv->msgv = msgs; for (i = 0; i < count; i++) { + /* Clear TX and RX FIFOs. */ + esp32_i2c_reset_fifo(priv); priv->bytes = 0; @@ -780,6 +976,8 @@ static int esp32_i2c_transfer(FAR struct i2c_master_s *dev, priv->error = 0; priv->i2cstate = I2CSTATE_PROC; + /* Set the SCLK frequency for the current msg. */ + esp32_i2c_init_clock(priv, msgs[i].frequency); /* Reset I2C trace logic */ @@ -789,10 +987,15 @@ static int esp32_i2c_transfer(FAR struct i2c_master_s *dev, esp32_i2c_traceevent(priv, I2CEVENT_SENDADDR, msgs[i].addr, esp32_i2c_get_reg(priv, I2C_SR_OFFSET)); + /* Send the start cmd */ + esp32_i2c_sendstart(priv); +#ifndef CONFIG_I2C_POLLED if (esp32_i2c_sem_waitdone(priv) < 0) { + /* Timed out - transfer was not completed within the timeout */ + ret = -ETIMEDOUT; break; } @@ -800,15 +1003,41 @@ static int esp32_i2c_transfer(FAR struct i2c_master_s *dev, { if (priv->error) { + /* An error occurred */ + ret = -EIO; break; } else { + /* Successful transfer, update the I2C state to idle */ + priv->i2cstate = I2CSTATE_IDLE; ret = OK; } } +#else + ret = esp32_i2c_polling_waitdone(priv); + if (ret < 0) + { + if (ret == -ETIMEDOUT) + { + break; + } + else + { + ret = -EIO; + break; + } + } + else + { + /* Successful transfer, update the I2C state to idle */ + + priv->i2cstate = I2CSTATE_IDLE; + ret = OK; + } +#endif } /* Dump the trace result */ @@ -820,6 +1049,100 @@ static int esp32_i2c_transfer(FAR struct i2c_master_s *dev, return ret; } +/**************************************************************************** + * Name: esp32_i2c_clear_bus + * + * Description: + * Clear I2C bus, when the slave is stuck in a deadlock and keeps pulling + * the bus low, master can control the SCL bus to generate 9 CLKs. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv) +{ + uint32_t clock_count; + uint32_t stretch_count; + int ret; + const struct esp32_i2c_config_s *config = priv->config; + + /* Use GPIO configuration to un-wedge the bus */ + + esp32_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp32_gpio_matrix_out(config->scl_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp32_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp32_gpio_matrix_out(config->sda_pin, SIG_GPIO_OUT_IDX, 0, 0); + + /* Set SDA to high */ + + esp32_gpiowrite(config->sda_pin, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!esp32_gpioread(config->sda_pin)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ >= I2C_SCL_CYC_NUM_DEF) + { + ret = -EIO; + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!esp32_gpioread(config->scl_pin)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + ret = -EIO; + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + esp32_gpiowrite(config->scl_pin, 0); + up_udelay(10); + + /* Drive SCL high again */ + + esp32_gpiowrite(config->scl_pin, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + esp32_gpiowrite(config->sda_pin, 0); + up_udelay(10); + esp32_gpiowrite(config->scl_pin, 0); + up_udelay(10); + esp32_gpiowrite(config->scl_pin, 1); + up_udelay(10); + esp32_gpiowrite(config->sda_pin, 1); + up_udelay(10); + + ret = OK; + +out: + return ret; +} +#endif + /**************************************************************************** * Name: esp32_i2c_reset * @@ -846,7 +1169,11 @@ static int esp32_i2c_reset(FAR struct i2c_master_s *dev) flags = enter_critical_section(); - esp32_i2c_reset_fsmc(priv); + esp32_i2c_deinit(priv); + + esp32_i2c_clear_bus(priv); + + esp32_i2c_init(priv); priv->i2cstate = I2CSTATE_IDLE; priv->msgid = 0; @@ -1047,28 +1374,71 @@ static void esp32_i2c_tracedump(struct esp32_i2c_priv_s *priv) * ****************************************************************************/ +#ifndef CONFIG_I2C_POLLED static int esp32_i2c_irq(int cpuint, void *context, FAR void *arg) { struct esp32_i2c_priv_s *priv = (struct esp32_i2c_priv_s *)arg; - struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; - uint32_t status = esp32_i2c_get_reg(priv, I2C_INT_STATUS_OFFSET); + /* Get the interrupt status and clear the interrupts that + * triggered. + */ + + uint32_t status = esp32_i2c_get_reg(priv, I2C_INT_STATUS_OFFSET); esp32_i2c_set_reg(priv, I2C_INT_CLR_OFFSET, status); + esp32_i2c_process(priv, status); + return OK; +} +#endif + +/**************************************************************************** + * Name: esp32_i2c_process + * + * Description: + * This routine manages the transfer. It's called after some specific + * commands from the I2C controller are executed or in case of errors. + * It's responsible for writing/reading operations and transferring data + * from/to FIFO. + * It's called in the interrupt and polled driven mode. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * status - The current interrupt status register. + * + ****************************************************************************/ + +static inline void esp32_i2c_process(struct esp32_i2c_priv_s *priv, + uint32_t status) +{ + struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; + + /* Check for any errors */ if (I2C_INT_ERR_EN_BITS & status) { + /* Save the errors, register the error event, disable interrupts + * and release the semaphore to conclude the transfer. + */ + priv->error = status & I2C_INT_ERR_EN_BITS; esp32_i2c_traceevent(priv, I2CEVENT_ERROR, priv->error, esp32_i2c_get_reg(priv, I2C_SR_OFFSET)); esp32_i2c_set_reg(priv, I2C_INT_ENA_OFFSET, 0); +#ifndef CONFIG_I2C_POLLED nxsem_post(&priv->sem_isr); +#endif } - else + else /* If no error */ { + /* If a transfer has just initialized */ + if (priv->i2cstate == I2CSTATE_PROC) { + /* Check the flags to perform a read or write operation */ + if (msg->flags & I2C_M_READ) { + /* RX FIFO has available data */ + if (priv->ready_read) { esp32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->bytes, @@ -1078,15 +1448,20 @@ static int esp32_i2c_irq(int cpuint, void *context, FAR void *arg) priv->ready_read = 0; } + /* Received all data. Finish the transaction + * and update the state I2C state. + */ + if (priv->bytes == msg->length) { esp32_i2c_traceevent(priv, I2CEVENT_STOP, msg->length, esp32_i2c_get_reg(priv, I2C_SR_OFFSET)); esp32_i2c_sendstop(priv); - +#ifndef CONFIG_I2C_POLLED priv->i2cstate = I2CSTATE_FINISH; +#endif } - else + else /* Start a receive operation */ { esp32_i2c_traceevent(priv, I2CEVENT_RCVMODEEN, 0, esp32_i2c_get_reg(priv, I2C_SR_OFFSET)); @@ -1095,12 +1470,16 @@ static int esp32_i2c_irq(int cpuint, void *context, FAR void *arg) priv->ready_read = 1; } } - else + else /* Write operation */ { esp32_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->bytes, esp32_i2c_get_reg(priv, I2C_SR_OFFSET)); esp32_i2c_senddata(priv); + /* Finally sent the entire message. Update the I2C state to + * send a stop signal in the next interrupt. + */ + if (priv->bytes == msg->length) { priv->i2cstate = I2CSTATE_STOP; @@ -1109,19 +1488,27 @@ static int esp32_i2c_irq(int cpuint, void *context, FAR void *arg) } else if (priv->i2cstate == I2CSTATE_STOP) { + /* Transmitted all data. Finish the transaction sending a stop + * and update the state I2C state. + */ + esp32_i2c_traceevent(priv, I2CEVENT_STOP, msg->length, esp32_i2c_get_reg(priv, I2C_SR_OFFSET)); esp32_i2c_sendstop(priv); - +#ifndef CONFIG_I2C_POLLED priv->i2cstate = I2CSTATE_FINISH; +#endif } +#ifndef CONFIG_I2C_POLLED else if (priv->i2cstate == I2CSTATE_FINISH) { + /* Disable all interrupts and release the semaphore */ + + esp32_i2c_set_reg(priv, I2C_INT_ENA_OFFSET, 0); nxsem_post(&priv->sem_isr); } +#endif } - - return 0; } /**************************************************************************** @@ -1138,10 +1525,12 @@ static int esp32_i2c_irq(int cpuint, void *context, FAR void *arg) FAR struct i2c_master_s *esp32_i2cbus_initialize(int port) { - int ret; irqstate_t flags; struct esp32_i2c_priv_s *priv; +#ifndef CONFIG_I2C_POLLED const struct esp32_i2c_config_s *config; + int ret; +#endif switch (port) { @@ -1159,8 +1548,6 @@ FAR struct i2c_master_s *esp32_i2cbus_initialize(int port) return NULL; } - config = priv->config; - flags = enter_critical_section(); if ((volatile int)priv->refs++ != 0) @@ -1170,6 +1557,8 @@ FAR struct i2c_master_s *esp32_i2cbus_initialize(int port) return (struct i2c_master_s *)priv; } +#ifndef CONFIG_I2C_POLLED + config = priv->config; priv->cpuint = esp32_alloc_levelint(1); if (priv->cpuint < 0) { @@ -1195,6 +1584,7 @@ FAR struct i2c_master_s *esp32_i2cbus_initialize(int port) } up_enable_irq(priv->cpuint); +#endif esp32_i2c_sem_init(priv); @@ -1235,11 +1625,13 @@ int esp32_i2cbus_uninitialize(FAR struct i2c_master_s *dev) leave_critical_section(flags); +#ifndef CONFIG_I2C_POLLED up_disable_irq(priv->cpuint); esp32_detach_peripheral(priv->config->cpu, priv->config->periph, priv->cpuint); esp32_free_cpuint(priv->cpuint); +#endif esp32_i2c_deinit(priv); diff --git a/arch/xtensa/src/esp32/esp32_idle.c b/arch/xtensa/src/esp32/esp32_idle.c index 9f95f66ab1c..35db93dcaf0 100644 --- a/arch/xtensa/src/esp32/esp32_idle.c +++ b/arch/xtensa/src/esp32/esp32_idle.c @@ -22,6 +22,9 @@ * Included Files ****************************************************************************/ +#include +#include +#include #include #include #include @@ -30,6 +33,14 @@ #include "esp32_pm.h" #include "xtensa.h" +#ifdef CONFIG_ESP32_RT_TIMER +#include "esp32_rt_timer.h" +#endif + +#ifdef CONFIG_SCHED_TICKLESS +#include "esp32_tickless.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -41,6 +52,7 @@ */ #ifdef CONFIG_PM + #ifndef CONFIG_PM_ALARM_SEC # define CONFIG_PM_ALARM_SEC 15 #endif @@ -58,6 +70,14 @@ #endif #define PM_IDLE_DOMAIN 0 /* Revisit */ + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#define EXPECTED_IDLE_TIME_US (800) +#define EARLY_WAKEUP_US (200) + #endif /**************************************************************************** @@ -75,9 +95,59 @@ #ifdef CONFIG_PM static void up_idlepm(void) { + irqstate_t flags; + +#ifdef CONFIG_ESP32_AUTO_SLEEP + flags = spin_lock_irqsave(NULL); + if (esp32_pm_lockstatus() == 0) + { + uint64_t os_start_us; + uint64_t os_end_us; + uint64_t os_step_us; + uint64_t hw_start_us; + uint64_t hw_end_us; + uint64_t hw_step_us; + uint64_t rtc_diff_us; + struct timespec ts; + uint64_t os_idle_us = up_get_idletime(); + uint64_t hw_idle_us = rt_timer_get_alarm(); + uint64_t sleep_us = MIN(os_idle_us, hw_idle_us); + if (sleep_us > EXPECTED_IDLE_TIME_US) + { + sleep_us -= EARLY_WAKEUP_US; + + esp32_sleep_enable_timer_wakeup(sleep_us); + + up_timer_gettime(&ts); + os_start_us = (ts.tv_sec * USEC_PER_SEC + + ts.tv_nsec / NSEC_PER_USEC); + hw_start_us = rt_timer_time_us(); + + esp32_light_sleep_start(&rtc_diff_us); + + hw_end_us = rt_timer_time_us(); + up_timer_gettime(&ts); + os_end_us = (ts.tv_sec * USEC_PER_SEC + + ts.tv_nsec / NSEC_PER_USEC); + hw_step_us = rtc_diff_us - (hw_end_us - hw_start_us); + os_step_us = rtc_diff_us - (os_end_us - os_start_us); + DEBUGASSERT(hw_step_us > 0); + DEBUGASSERT(os_step_us > 0); + + /* Adjust current RT timer by a certain value. */ + + rt_timer_calibration(hw_step_us); + + /* Adjust system time by a certain value. */ + + up_step_idletime((uint32_t)os_step_us); + } + } + + spin_unlock_irqrestore(NULL, flags); +#else /* CONFIG_ESP32_AUTO_SLEEP */ static enum pm_state_e oldstate = PM_NORMAL; enum pm_state_e newstate; - irqstate_t flags; int ret; /* Decide, which power saving level can be obtained */ @@ -159,6 +229,7 @@ static void up_idlepm(void) pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); #endif } +#endif } #else # define up_idlepm() @@ -191,10 +262,6 @@ void up_idle(void) nxsched_process_timer(); #else - /* Perform IDLE mode power management */ - - up_idlepm(); - /* This would be an appropriate place to put some MCU-specific logic to * sleep in a reduced power mode until an interrupt occurs to save power */ @@ -202,5 +269,10 @@ void up_idle(void) #if XCHAL_HAVE_INTERRUPTS __asm__ __volatile__ ("waiti 0"); #endif + + /* Perform IDLE mode power management */ + + up_idlepm(); + #endif } diff --git a/arch/xtensa/src/esp32/esp32_iramheap.c b/arch/xtensa/src/esp32/esp32_iramheap.c new file mode 100644 index 00000000000..979f2dcfe58 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_iramheap.c @@ -0,0 +1,181 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_iramheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "esp32_iramheap.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct mm_heap_s *g_iramheap; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_iramheap_initialize + * + * Description: + * Initialize the IRAM heap. + * + ****************************************************************************/ + +void esp32_iramheap_initialize(void) +{ + void *start; + size_t size; + + /* These values come from the linker scripts. Check boards/xtensa/esp32. */ + + extern uint8_t *_siramheap; + extern uint8_t *_eiramheap; + + start = (void *)&_siramheap; + size = (size_t)((uintptr_t)&_eiramheap - (uintptr_t)&_siramheap); + g_iramheap = mm_initialize("iramheap", start, size); +} + +/**************************************************************************** + * Name: esp32_iramheap_malloc + * + * Description: + * Allocate memory from the IRAM heap. + * + ****************************************************************************/ + +void *esp32_iramheap_malloc(size_t size) +{ + return mm_malloc(g_iramheap, size); +} + +/**************************************************************************** + * Name: esp32_iramheap_calloc + * + * Description: + * Calculates the size of the allocation and allocate memory from + * the IRAM heap. + * + ****************************************************************************/ + +void *esp32_iramheap_calloc(size_t n, size_t elem_size) +{ + return mm_calloc(g_iramheap, n, elem_size); +} + +/**************************************************************************** + * Name: esp32_iramheap_realloc + * + * Description: + * Reallocate memory from the IRAM heap. + * + ****************************************************************************/ + +void *esp32_iramheap_realloc(void *ptr, size_t size) +{ + return mm_realloc(g_iramheap, ptr, size); +} + +/**************************************************************************** + * Name: esp32_iramheap_zalloc + * + * Description: + * Allocate and zero memory from the IRAM heap. + * + ****************************************************************************/ + +void *esp32_iramheap_zalloc(size_t size) +{ + return mm_zalloc(g_iramheap, size); +} + +/**************************************************************************** + * Name: esp32_iramheap_free + * + * Description: + * Free memory from the IRAM heap. + * + ****************************************************************************/ + +void esp32_iramheap_free(void *mem) +{ + mm_free(g_iramheap, mem); +} + +/**************************************************************************** + * Name: esp32_iramheap_memalign + * + * Description: + * memalign requests more than enough space from malloc, finds a region + * within that chunk that meets the alignment request and then frees any + * leading or trailing space. + * + * The alignment argument must be a power of two (not checked). 8-byte + * alignment is guaranteed by normal malloc calls. + * + ****************************************************************************/ + +void *esp32_iramheap_memalign(size_t alignment, size_t size) +{ + return mm_memalign(g_iramheap, alignment, size); +} + +/**************************************************************************** + * Name: esp32_iramheap_heapmember + * + * Description: + * Check if an address lies in the IRAM heap. + * + * Parameters: + * mem - The address to check + * + * Return Value: + * true if the address is a member of the IRAM heap. false if not + * + ****************************************************************************/ + +bool esp32_iramheap_heapmember(void *mem) +{ + return mm_heapmember(g_iramheap, mem); +} + +/**************************************************************************** + * Name: esp32_iramheap_mallinfo + * + * Description: + * mallinfo returns a copy of updated current heap information for the + * user heap. + * + ****************************************************************************/ + +int esp32_iramheap_mallinfo(struct mallinfo *info) +{ + return mm_mallinfo(g_iramheap, info); +} diff --git a/arch/xtensa/src/esp32/esp32_iramheap.h b/arch/xtensa/src/esp32/esp32_iramheap.h new file mode 100644 index 00000000000..2a846440e8a --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_iramheap.h @@ -0,0 +1,146 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_iramheap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_IRAMHEAP_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_IRAMHEAP_H + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +struct mallinfo; /* Forward reference, see malloc.h */ + +/**************************************************************************** + * Name: esp32_iramheap_initialize + * + * Description: + * Initialize the IRAM heap. + * + ****************************************************************************/ + +void esp32_iramheap_initialize(void); + +/**************************************************************************** + * Name: esp32_iramheap_malloc + * + * Description: + * Allocate memory from the IRAM heap. + * + ****************************************************************************/ + +void *esp32_iramheap_malloc(size_t size); + +/**************************************************************************** + * Name: esp32_iramheap_calloc + * + * Description: + * Calculates the size of the allocation and allocate memory from + * the IRAM heap. + * + ****************************************************************************/ + +void *esp32_iramheap_calloc(size_t n, size_t elem_size); + +/**************************************************************************** + * Name: esp32_iramheap_realloc + * + * Description: + * Reallocate memory from the IRAM heap. + * + ****************************************************************************/ + +void *esp32_iramheap_realloc(void *ptr, size_t size); + +/**************************************************************************** + * Name: esp32_iramheap_zalloc + * + * Description: + * Allocate and zero memory from the IRAM heap. + * + ****************************************************************************/ + +void *esp32_iramheap_zalloc(size_t size); + +/**************************************************************************** + * Name: esp32_iramheap_free + * + * Description: + * Free memory from the IRAM heap. + * + ****************************************************************************/ + +void esp32_iramheap_free(void *mem); + +/**************************************************************************** + * Name: esp32_iramheap_memalign + * + * Description: + * memalign requests more than enough space from malloc, finds a region + * within that chunk that meets the alignment request and then frees any + * leading or trailing space. + * + * The alignment argument must be a power of two (not checked). 8-byte + * alignment is guaranteed by normal malloc calls. + * + ****************************************************************************/ + +void *esp32_iramheap_memalign(size_t alignment, size_t size); + +/**************************************************************************** + * Name: esp32_iramheap_heapmember + * + * Description: + * Check if an address lies in the IRAM heap. + * + * Parameters: + * mem - The address to check + * + * Return Value: + * true if the address is a member of the IRAM heap. false if not + * + ****************************************************************************/ + +bool esp32_iramheap_heapmember(void *mem); + +/**************************************************************************** + * Name: esp32_iramheap_mallinfo + * + * Description: + * mallinfo returns a copy of updated current heap information for the + * user heap. + * + ****************************************************************************/ + +int esp32_iramheap_mallinfo(struct mallinfo *info); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_IRAMHEAP_H */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 349abcf6543..617f7160017 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_oneshot.c b/arch/xtensa/src/esp32/esp32_oneshot.c index a52b885ff7b..705790a223a 100644 --- a/arch/xtensa/src/esp32/esp32_oneshot.c +++ b/arch/xtensa/src/esp32/esp32_oneshot.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_oneshot_lowerhalf.c b/arch/xtensa/src/esp32/esp32_oneshot_lowerhalf.c index 089f63390c2..7e4949c04fc 100644 --- a/arch/xtensa/src/esp32/esp32_oneshot_lowerhalf.c +++ b/arch/xtensa/src/esp32/esp32_oneshot_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/xtensa/src/esp32/esp32_pm.c b/arch/xtensa/src/esp32/esp32_pm.c index 26399dd1671..127302bf019 100644 --- a/arch/xtensa/src/esp32/esp32_pm.c +++ b/arch/xtensa/src/esp32/esp32_pm.c @@ -23,6 +23,7 @@ ****************************************************************************/ #include +#include #ifdef CONFIG_PM @@ -30,6 +31,8 @@ #include #include #include +#include +#include #include #include #include "hardware/esp32_rtccntl.h" @@ -42,6 +45,14 @@ #include "esp32_pm.h" #include "esp32_resetcause.h" +#ifdef CONFIG_ESP32_RT_TIMER +#include "esp32_rt_timer.h" +#endif + +#ifdef CONFIG_SCHED_TICKLESS +#include "esp32_tickless.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -192,6 +203,8 @@ static struct esp32_sleep_config_t s_config = .wakeup_triggers = 0 }; +static _Atomic uint32_t pm_wakelock = 0; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -836,7 +849,7 @@ static void RTC_IRAM_ATTR esp32_wake_deep_sleep(void) * ****************************************************************************/ -void esp32_sleep_enable_timer_wakeup(uint64_t time_in_us) +void IRAM_ATTR esp32_sleep_enable_timer_wakeup(uint64_t time_in_us) { s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN; s_config.sleep_duration = time_in_us; @@ -849,14 +862,14 @@ void esp32_sleep_enable_timer_wakeup(uint64_t time_in_us) * Enter sleep mode * * Input Parameters: - * None + * sleep_time - Actual sleep time * * Returned Value: * 0 is returned on success or a negated errno value is returned * ****************************************************************************/ -int esp32_light_sleep_start(void) +int esp32_light_sleep_start(uint64_t *sleep_time) { irqstate_t flags; uint32_t pd_flags; @@ -905,6 +918,12 @@ int esp32_light_sleep_start(void) ret = esp32_light_sleep_inner(pd_flags, flash_enable_time_us, vddsdio_config); + if (sleep_time != NULL) + { + *sleep_time = esp32_rtc_time_slowclk_to_us(esp32_rtc_time_get() - + s_config.rtc_ticks_at_sleep_start, esp32_clk_slowclk_cal_get()); + } + leave_critical_section(flags); return ret; } @@ -947,11 +966,42 @@ void esp32_pminit(void) void esp32_pmstandby(uint64_t time_in_us) { + uint64_t rtc_diff_us; +#ifdef CONFIG_ESP32_RT_TIMER + uint64_t hw_start_us; + uint64_t hw_end_us; + uint64_t hw_diff_us; +#endif + /* don't power down XTAL — powering it up takes different time on. */ fflush(stdout); esp32_sleep_enable_timer_wakeup(time_in_us); - esp32_light_sleep_start(); + +#ifdef CONFIG_ESP32_RT_TIMER + /* Get rt-timer timestamp before entering sleep */ + + hw_start_us = rt_timer_time_us(); +#endif + + esp32_light_sleep_start(&rtc_diff_us); + +#ifdef CONFIG_ESP32_RT_TIMER + /* Get rt-timer timestamp after waking up from sleep */ + + hw_end_us = rt_timer_time_us(); + hw_diff_us = hw_end_us - hw_start_us; + DEBUGASSERT(rtc_diff_us > hw_diff_us); + + rt_timer_calibration(rtc_diff_us - hw_diff_us); +#endif + +#ifdef CONFIG_SCHED_TICKLESS + up_step_idletime((uint32_t)time_in_us); +#endif + + pwrinfo("Returned from auto-sleep, slept for %" PRIu32 " ms\n", + (uint32_t)(rtc_diff_us) / 1000); } /**************************************************************************** @@ -1083,4 +1133,43 @@ void esp32_pmsleep(uint64_t time_in_us) esp32_deep_sleep_start(); } +/**************************************************************************** + * Name: esp32_pm_lockacquire + * + * Description: + * Take a power management lock + * + ****************************************************************************/ + +void IRAM_ATTR esp32_pm_lockacquire(void) +{ + ++pm_wakelock; +} + +/**************************************************************************** + * Name: esp32_pm_lockrelease + * + * Description: + * Release the lock taken using esp32_pm_lockacquire. + * + ****************************************************************************/ + +void IRAM_ATTR esp32_pm_lockrelease(void) +{ + --pm_wakelock; +} + +/**************************************************************************** + * Name: esp32_pm_lockstatus + * + * Description: + * Return power management lock status. + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32_pm_lockstatus(void) +{ + return pm_wakelock; +} + #endif /* CONFIG_PM */ \ No newline at end of file diff --git a/arch/xtensa/src/esp32/esp32_pm.h b/arch/xtensa/src/esp32/esp32_pm.h index 20558127fb5..979f8d368fd 100644 --- a/arch/xtensa/src/esp32/esp32_pm.h +++ b/arch/xtensa/src/esp32/esp32_pm.h @@ -118,14 +118,14 @@ void esp32_sleep_enable_timer_wakeup(uint64_t time_in_us); * Enter sleep mode * * Input Parameters: - * None + * sleep_time - Actual sleep time * * Returned Value: * 0 is returned on success or a negated errno value is returned * ****************************************************************************/ -int esp32_light_sleep_start(void); +int esp32_light_sleep_start(uint64_t *sleep_time); /**************************************************************************** * Name: esp32_pminit @@ -207,6 +207,36 @@ void esp32_deep_sleep_start(void); void esp32_pmsleep(uint64_t time_in_us); +/**************************************************************************** + * Name: esp32_pm_lockacquire + * + * Description: + * Take a power management lock + * + ****************************************************************************/ + +void esp32_pm_lockacquire(void); + +/**************************************************************************** + * Name: esp32_pm_lockrelease + * + * Description: + * Release the lock taken using esp32_pm_lock. + * + ****************************************************************************/ + +void esp32_pm_lockrelease(void); + +/**************************************************************************** + * Name: esp32_pm_lockstatus + * + * Description: + * Return power management lock status. + * + ****************************************************************************/ + +uint32_t esp32_pm_lockstatus(void); + #endif /* CONFIG_PM */ #ifdef __cplusplus diff --git a/arch/xtensa/src/esp32/esp32_psram.c b/arch/xtensa/src/esp32/esp32_psram.c index 9f2e4f6c097..87672d003ba 100644 --- a/arch/xtensa/src/esp32/esp32_psram.c +++ b/arch/xtensa/src/esp32/esp32_psram.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_rt_timer.c b/arch/xtensa/src/esp32/esp32_rt_timer.c index f539becca85..2d1ae3d1172 100644 --- a/arch/xtensa/src/esp32/esp32_rt_timer.c +++ b/arch/xtensa/src/esp32/esp32_rt_timer.c @@ -80,13 +80,13 @@ static struct esp32_tim_dev_s *s_esp32_tim_dev; * Name: start_rt_timer * * Description: - * Start timer by inserting it into running list and reset hardware timer - * alarm value if this timer in head of list. + * Start the timer by inserting it into the running list and reset the + * hardware timer alarm value if this timer is at the head of the list. * * Input Parameters: * timer - RT timer pointer * timeout - Timeout value - * repeat - If the timer run repeat + * repeat - repeat mode (true: enabled, false: disabled) * * Returned Value: * None. @@ -124,8 +124,8 @@ static void start_rt_timer(FAR struct rt_timer_s *timer, timer->flags &= ~RT_TIMER_REPEAT; } - /** Scan timer list and insert the new timer into previous - * node of timer whose alarm value is larger than new one + /* Scan the timer list and insert the new timer into previous + * node of timer whose alarm value is larger than new one */ list_for_every_entry(&s_runlist, p, struct rt_timer_s, list) @@ -138,7 +138,9 @@ static void start_rt_timer(FAR struct rt_timer_s *timer, } } - /* If not find a larger one, insert new timer into tail of list */ + /* If we didn't find a larger one, insert the new timer at the tail + * of the list. + */ if (!inserted) { @@ -147,11 +149,11 @@ static void start_rt_timer(FAR struct rt_timer_s *timer, timer->state = RT_TIMER_READY; - /* If this timer is in head of list */ + /* If this timer is at the head of the list */ if (timer == container_of(s_runlist.next, struct rt_timer_s, list)) { - /* Reset hardware timer alarm */ + /* Reset the hardware timer alarm */ ESP32_TIM_SETALRVL(tim, timer->alarm); ESP32_TIM_SETALRM(tim, true); @@ -165,8 +167,8 @@ static void start_rt_timer(FAR struct rt_timer_s *timer, * Name: stop_rt_timer * * Description: - * Stop timer by removing it from running list and reset hardware timer - * alarm value if this timer is in head of list. + * Stop the timer by removing it from the running list and reset the + * hardware timer alarm value if this timer is at the head of list. * * Input Parameters: * timer - RT timer pointer @@ -186,18 +188,17 @@ static void stop_rt_timer(FAR struct rt_timer_s *timer) flags = enter_critical_section(); - /** - * Function "start" can set timer to be repeat, and function "stop" - * should remove this feature although it is not in ready state. + /* "start" function can set the timer's repeat flag, and function "stop" + * should remove this flag. */ timer->flags &= ~RT_TIMER_REPEAT; - /* Only ready timer can be stopped */ + /* Only timers in "ready" state can be stopped */ if (timer->state == RT_TIMER_READY) { - /* Check if timer is in head of list */ + /* Check if the timer is at the head of the list */ if (timer == container_of(s_runlist.next, struct rt_timer_s, list)) { @@ -211,15 +212,15 @@ static void stop_rt_timer(FAR struct rt_timer_s *timer) list_delete(&timer->list); timer->state = RT_TIMER_IDLE; - /* If timer is in in head of list */ + /* If the timer is at the head of the list */ if (ishead) { - /* If list is not empty */ - if (!list_is_empty(&s_runlist)) { - /* Reset hardware timer alarm value to be next timer's */ + /* Set the value from the next timer as the new hardware timer + * alarm value + */ next_timer = container_of(s_runlist.next, struct rt_timer_s, @@ -239,9 +240,9 @@ static void stop_rt_timer(FAR struct rt_timer_s *timer) * Name: delete_rt_timer * * Description: - * Delete timer by removing it from list, then set the timer's state - * to be "RT_TIMER_DELETE", inserting into work list to let rt-timer - * thread to delete it and free resource. + * Delete the timer by removing it from the list, then set the timer's + * state to "RT_TIMER_DELETE" and finally insert it into the work list + * to let the rt-timer's thread to delete it and free the resources. * * Input Parameters: * timer - RT timer pointer @@ -281,8 +282,8 @@ exit: * Name: rt_timer_thread * * Description: - * RT timer working thread, it wait for a timeout semaphore, scan - * the timeout list and process all timers in this list. + * RT timer working thread: Waits for a timeout semaphore, scans + * the timeout list and processes all the timers in the list. * * Input Parameters: * argc - Not used @@ -302,7 +303,7 @@ static int rt_timer_thread(int argc, FAR char *argv[]) while (1) { - /* Waiting for timers timeout */ + /* Waiting for all the timers to time out */ ret = nxsem_wait(&s_toutsem); if (ret) @@ -311,15 +312,13 @@ static int rt_timer_thread(int argc, FAR char *argv[]) assert(0); } - /* Enter critical to check global timer timeout list */ - flags = enter_critical_section(); - /* Process all timers in list */ + /* Process all the timers in the list */ while (!list_is_empty(&s_toutlist)) { - /* Get first timer in list */ + /* Get the first timer in the list */ timer = container_of(s_toutlist.next, struct rt_timer_s, list); @@ -327,16 +326,14 @@ static int rt_timer_thread(int argc, FAR char *argv[]) raw_state = timer->state; - /* Delete timer from list */ + /* Delete the timer from list */ list_delete(&timer->list); - /* Set timer's state to be let it to able to restart by user */ + /* Set timer's state to idle so it can be restarted by the user. */ timer->state = RT_TIMER_IDLE; - /* Leave from critical to start to call "callback" function */ - leave_critical_section(flags); if (raw_state == RT_TIMER_TIMEOUT) @@ -348,13 +345,13 @@ static int rt_timer_thread(int argc, FAR char *argv[]) kmm_free(timer); } - /* Enter critical for next scanning list */ + /* Enter critical section for next scanning list */ flags = enter_critical_section(); if (raw_state == RT_TIMER_TIMEOUT) { - /* Check if timer is repeat */ + /* Check if the timer is in "repeat" mode */ if (timer->flags & RT_TIMER_REPEAT) { @@ -373,7 +370,7 @@ static int rt_timer_thread(int argc, FAR char *argv[]) * Name: rt_timer_isr * * Description: - * Hardware timer interrupt service function. + * Hardware timer interrupt service routine. * * Input Parameters: * irq - Not used @@ -397,13 +394,13 @@ static int rt_timer_isr(int irq, void *context, void *arg) ESP32_TIM_ACKINT(tim); - /* Wake up thread to process timeout timers */ + /* Wake up the thread to process timed-out timers */ nxsem_post(&s_toutsem); flags = enter_critical_section(); - /* Check if there is timer running */ + /* Check if there is a timer running */ if (!list_is_empty(&s_runlist)) { @@ -417,19 +414,18 @@ static int rt_timer_isr(int irq, void *context, void *arg) ESP32_TIM_GETCTR(tim, &counter); if (timer->alarm <= counter) { - /** - * Remove first timer in running list and add it into - * timeout list. + /* Remove the first timer in the running list and add it to + * the timeout list. * * Set the timer's state to be RT_TIMER_TIMEOUT to avoid - * other operation. + * other operations. */ list_delete(&timer->list); timer->state = RT_TIMER_TIMEOUT; list_add_after(&s_toutlist, &timer->list); - /* Check if thers is timer running */ + /* Check if there is a timer running */ if (!list_is_empty(&s_runlist)) { @@ -457,7 +453,7 @@ static int rt_timer_isr(int irq, void *context, void *arg) * Name: rt_timer_create * * Description: - * Create RT timer by into timer creation arguments + * Create a RT timer from the provided arguments. * * Input Parameters: * args - Input RT timer creation arguments @@ -495,12 +491,12 @@ int rt_timer_create(FAR const struct rt_timer_args_s *args, * Name: rt_timer_start * * Description: - * Start RT timer. + * Start the RT timer. * * Input Parameters: * timer - RT timer pointer * timeout - Timeout value - * repeat - If the timer run repeat + * repeat - repeat mode (true: enabled, false: disabled) * * Returned Value: * None @@ -520,7 +516,7 @@ void rt_timer_start(FAR struct rt_timer_s *timer, * Name: rt_timer_stop * * Description: - * Stop RT timer. + * Stop the RT timer. * * Input Parameters: * timer - RT timer pointer @@ -539,7 +535,7 @@ void rt_timer_stop(FAR struct rt_timer_s *timer) * Name: rt_timer_delete * * Description: - * Stop and deleta RT timer. + * Stop and delete RT timer. * * Input Parameters: * timer - RT timer pointer @@ -558,17 +554,17 @@ void rt_timer_delete(FAR struct rt_timer_s *timer) * Name: rt_timer_time_us * * Description: - * Get time of RT timer by micro second. + * Get time of the RT timer in microseconds. * * Input Parameters: * None * * Returned Value: - * Time of RT timer by micro second. + * Time of the RT timer in microseconds. * ****************************************************************************/ -uint64_t rt_timer_time_us(void) +uint64_t IRAM_ATTR rt_timer_time_us(void) { uint64_t counter; struct esp32_tim_dev_s *tim = s_esp32_tim_dev; @@ -578,6 +574,74 @@ uint64_t rt_timer_time_us(void) return counter; } +/**************************************************************************** + * Name: rt_timer_get_alarm + * + * Description: + * Get the timestamp when the next timeout is expected to occur. + * + * Input Parameters: + * None + * + * Returned Value: + * Timestamp of the nearest timer event in microseconds. + * + ****************************************************************************/ + +uint64_t IRAM_ATTR rt_timer_get_alarm(void) +{ + irqstate_t flags; + uint64_t counter; + struct esp32_tim_dev_s *tim = s_esp32_tim_dev; + uint64_t alarm_value = 0; + + flags = enter_critical_section(); + + ESP32_TIM_GETCTR(tim, &counter); + ESP32_TIM_GETALRVL(tim, &alarm_value); + + if (alarm_value <= counter) + { + alarm_value = 0; + } + else + { + alarm_value -= counter; + } + + leave_critical_section(flags); + + return alarm_value; +} + +/**************************************************************************** + * Name: rt_timer_calibration + * + * Description: + * Adjust current RT timer by a certain value. + * + * Input Parameters: + * time_us - adjustment to apply to the RT timer in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void IRAM_ATTR rt_timer_calibration(uint64_t time_us) +{ + uint64_t counter; + struct esp32_tim_dev_s *tim = s_esp32_tim_dev; + irqstate_t flags; + + flags = enter_critical_section(); + ESP32_TIM_GETCTR(tim, &counter); + counter += time_us; + ESP32_TIM_SETCTR(tim, counter); + ESP32_TIM_RLD_NOW(tim); + leave_critical_section(flags); +} + /**************************************************************************** * Name: esp32_rt_timer_init * @@ -627,8 +691,7 @@ int esp32_rt_timer_init(void) flags = enter_critical_section(); - /** - * ESP32 hardware timer configuration: + /* ESP32 hardware timer configuration: * - 1 counter = 1us * - Counter increase mode * - Non-reload mode @@ -678,3 +741,4 @@ void esp32_rt_timer_deinit(void) kthread_delete(s_pid); nxsem_destroy(&s_toutsem); } + diff --git a/arch/xtensa/src/esp32/esp32_rt_timer.h b/arch/xtensa/src/esp32/esp32_rt_timer.h index 5addd0436ab..33fcbd7b482 100644 --- a/arch/xtensa/src/esp32/esp32_rt_timer.h +++ b/arch/xtensa/src/esp32/esp32_rt_timer.h @@ -31,8 +31,16 @@ #include #include -#define RT_TIMER_NOFLAGS (0) /* Timer support no feature */ -#define RT_TIMER_REPEAT (1 << 0) /* Timer is repeat */ +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RT_TIMER_NOFLAGS (0) /* Timer supports no feature */ +#define RT_TIMER_REPEAT (1 << 0) /* Timer supports repeat mode */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ /** * RT timer state @@ -42,7 +50,7 @@ enum rt_timer_state_e { RT_TIMER_IDLE, /* Timer is not counting */ RT_TIMER_READY, /* Timer is counting */ - RT_TIMER_TIMEOUT, /* Timer is timeout */ + RT_TIMER_TIMEOUT, /* Timer timed out */ RT_TIMER_DELETE /* Timer is to be delete */ }; @@ -56,8 +64,8 @@ struct rt_timer_s uint64_t alarm; /* Timeout period */ void (*callback)(void *arg); /* Callback function */ void *arg; /* Private data */ - uint16_t flags; /* Support feature */ - enum rt_timer_state_e state; /* Mark if timer is started */ + uint16_t flags; /* Supported features */ + enum rt_timer_state_e state; /* Timer state */ struct list_node list; /* Working list */ }; @@ -80,11 +88,15 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + /**************************************************************************** * Name: rt_timer_create * * Description: - * Create RT timer by into timer creation arguments + * Create a RT timer from the provided arguments. * * Input Parameters: * args - Input RT timer creation arguments @@ -102,12 +114,12 @@ int rt_timer_create(FAR const struct rt_timer_args_s *args, * Name: rt_timer_start * * Description: - * Start RT timer. + * Start the RT timer. * * Input Parameters: * timer - RT timer pointer * timeout - Timeout value - * repeat - If the timer run repeat + * repeat - repeat mode (true: enabled, false: disabled) * * Returned Value: * None @@ -122,7 +134,7 @@ void rt_timer_start(FAR struct rt_timer_s *timer, * Name: rt_timer_stop * * Description: - * Stop RT timer. + * Stop the RT timer. * * Input Parameters: * timer - RT timer pointer @@ -138,7 +150,7 @@ void rt_timer_stop(FAR struct rt_timer_s *timer); * Name: rt_timer_delete * * Description: - * Stop and deleta RT timer. + * Stop and delete the RT timer. * * Input Parameters: * timer - RT timer pointer @@ -154,18 +166,50 @@ void rt_timer_delete(FAR struct rt_timer_s *timer); * Name: rt_timer_time_us * * Description: - * Get time of RT timer by micro second. + * Get time of the RT timer in microseconds. * * Input Parameters: * None * * Returned Value: - * Time of RT timer by micro second. + * Time of the RT timer in microseconds. * ****************************************************************************/ uint64_t rt_timer_time_us(void); +/**************************************************************************** + * Name: rt_timer_get_alarm + * + * Description: + * Get the timestamp when the next timeout is expected to occur. + * + * Input Parameters: + * None + * + * Returned Value: + * Timestamp of the nearest timer event in microseconds. + * + ****************************************************************************/ + +uint64_t rt_timer_get_alarm(void); + +/**************************************************************************** + * Name: rt_timer_calibration + * + * Description: + * Adjust current RT timer by a certain value. + * + * Input Parameters: + * time_us - adjustment to apply to the RT timer in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void rt_timer_calibration(uint64_t time_us); + /**************************************************************************** * Name: esp32_rt_timer_init * diff --git a/arch/xtensa/src/esp32/esp32_rtc.c b/arch/xtensa/src/esp32/esp32_rtc.c index 9e7e1307e1f..b02c6d462ef 100644 --- a/arch/xtensa/src/esp32/esp32_rtc.c +++ b/arch/xtensa/src/esp32/esp32_rtc.c @@ -24,13 +24,19 @@ #include #include +#include + +#include +#include #include "esp32_rtc.h" #include "esp32_clockconfig.h" +#include "esp32_rt_timer.h" + #include "hardware/esp32_rtccntl.h" #include "hardware/esp32_dport.h" #include "hardware/esp32_i2s.h" -#include "esp32_rtc.h" + #include "xtensa.h" #include "xtensa_attr.h" @@ -64,12 +70,36 @@ #define DELAY_FAST_CLK_SWITCH 3 -#define XTAL_32K_DAC_VAL 3 +#define XTAL_32K_DAC_VAL 1 #define XTAL_32K_DRES_VAL 3 #define XTAL_32K_DBIAS_VAL 0 +#define XTAL_32K_EXT_DAC_VAL 2 +#define XTAL_32K_EXT_DRES_VAL 3 +#define XTAL_32K_EXT_DBIAS_VAL 1 + #define DELAY_SLOW_CLK_SWITCH 300 +#define DELAY_8M_ENABLE 50 + +#define RETRY_CAL_EXT 1 + +/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. + * The ideal value (assuming 32768 Hz frequency) + * is 1000000/32768*(2**19) = 16*10^6. + */ + +#define MIN_32K_XTAL_CAL_VAL 15000000L + +/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP + * setting + */ + +#define RTC_FAST_CLK_FREQ_8M 8500000 +#define RTC_SLOW_CLK_FREQ_150K 150000 +#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256) +#define RTC_SLOW_CLK_FREQ_32K 32768 + /* Number of fractional bits in values returned by rtc_clk_cal */ #define RTC_CLK_CAL_FRACT 19 @@ -124,6 +154,25 @@ .fe_pd = (val), \ } +#ifdef CONFIG_RTC_DRIVER +/* The magic data for the struct esp32_rtc_backup_s that is in RTC slow + * memory. + */ + +# define MAGIC_RTC_SAVE (UINT64_C(0x11223344556677)) +#endif + +/* RTC Memory & Store Register usage */ + +#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG /* RTC_SLOW_CLK calibration value */ +#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG /* Boot time, low word */ +#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG /* Boot time, high word */ +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG /* External XTAL frequency */ +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG /* APB bus frequency */ +#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG /* FAST_RTC_MEMORY_ENTRY */ +#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG +#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG /* FAST_RTC_MEMORY_CRC */ + /**************************************************************************** * Private Types ****************************************************************************/ @@ -176,6 +225,28 @@ struct esp32_rtc_sleep_pd_config_s uint32_t fe_pd : 1; /* Set to 1 to power down WiFi in sleep */ }; +#ifdef CONFIG_RTC_DRIVER + +#ifdef CONFIG_RTC_ALARM +struct alm_cbinfo_s +{ + struct rt_timer_s *alarm_hdl; /* Timer id point to here */ + volatile alm_callback_t ac_cb; /* Client callback function */ + volatile FAR void *ac_arg; /* Argument to pass with the callback function */ + uint64_t deadline_us; + uint8_t index; +}; +#endif + +struct esp32_rtc_backup_s +{ + uint64_t magic; + int64_t offset; /* Offset time from RTC HW value */ + int64_t reserved0; +}; + +#endif + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -190,6 +261,13 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( static void IRAM_ATTR esp32_rtc_clk_slow_freq_set( enum esp32_rtc_slow_freq_e slow_freq); static void esp32_select_rtc_slow_clk(enum esp32_slow_clk_sel_e slow_clk); +static void esp32_rtc_clk_32k_enable(int ac, int res, int bias); +static void IRAM_ATTR esp32_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); +static uint32_t IRAM_ATTR esp32_rtc_clk_slow_freq_get_hz(void); + +#ifdef CONFIG_RTC_DRIVER +static void IRAM_ATTR esp32_rt_cb_handler(FAR void *arg); +#endif /**************************************************************************** * Private Data @@ -205,12 +283,35 @@ static struct esp32_rtc_priv_s esp32_rtc_priv = .rtc_dboost_fpd = 1 }; +#ifdef CONFIG_RTC_DRIVER + +/* Callback to use when the alarm expires */ + +#ifdef CONFIG_RTC_ALARM +static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; +#endif + +static RTC_DATA_ATTR struct esp32_rtc_backup_s rtc_saved_data; + +/* Saved data for persistent RTC time */ + +static struct esp32_rtc_backup_s *g_rtc_save; +static bool g_rt_timer_enabled = false; + +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +volatile bool g_rtc_enabled = false; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ -extern void ets_delay_us(uint32_t us); - /**************************************************************************** * Name: esp32_rtc_sleep_pd * @@ -262,7 +363,7 @@ static void IRAM_ATTR esp32_rtc_clk_fast_freq_set( enum esp32_rtc_fast_freq_e fast_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); - ets_delay_us(DELAY_FAST_CLK_SWITCH); + up_udelay(DELAY_FAST_CLK_SWITCH); } /**************************************************************************** @@ -299,7 +400,9 @@ static inline bool esp32_clk_val_is_valid(uint32_t val) * slowclk_cycles - number of slow clock cycles to count. * * Returned Value: - * Number of XTAL clock cycles within the given number of slow clock cycles + * Number of XTAL clock cycles within the given number of slow clock + * cycles. + * In case of error, return 0 cycle. * ****************************************************************************/ @@ -309,21 +412,26 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( uint32_t expected_freq; uint32_t us_time_estimate; uint32_t us_timer_max; + uint32_t clks_state; + uint32_t clks_mask; int timeout_us; enum esp32_rtc_slow_freq_e slow_freq; enum esp32_rtc_xtal_freq_e xtal_freq; + /* Get the current state */ + + clks_mask = (RTC_CNTL_DIG_XTAL32K_EN_M | RTC_CNTL_DIG_CLK8M_D256_EN_M); + clks_state = getreg32(RTC_CNTL_CLK_CONF_REG); + clks_state &= clks_mask; + /* Enable requested clock (150k clock is always on) */ - int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, - RTC_CNTL_DIG_XTAL32K_EN); - - if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) + if (cal_clk == RTC_CAL_32K_XTAL && !(clks_state & RTC_CNTL_DIG_XTAL32K_EN)) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); } - - if (cal_clk == RTC_CAL_8MD256) + else if (cal_clk == RTC_CAL_8MD256 && + !(clks_state & RTC_CNTL_DIG_CLK8M_D256_EN)) { modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_DIG_CLK8M_D256_EN); } @@ -338,13 +446,11 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); - if (cal_clk == RTC_CAL_32K_XTAL || - (cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_32K_XTAL)) + if (cal_clk == RTC_CAL_32K_XTAL || slow_freq == RTC_SLOW_FREQ_32K_XTAL) { expected_freq = 32768; /* standard 32k XTAL */ } - else if (cal_clk == RTC_CAL_8MD256 || - (cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_8MD256)) + else if (cal_clk == RTC_CAL_8MD256 || slow_freq == RTC_SLOW_FREQ_8MD256) { expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256; } @@ -372,6 +478,7 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( if (us_time_estimate >= us_timer_max) { + rtcerr("Estimated time overflows TIMG_RTC_CALI_VALUE\n"); return 0; } @@ -380,12 +487,9 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START, 0); modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); - /* Wait the expected time calibration should take. - * TODO: if running under RTOS, and us_time_estimate > RTOS tick, use the - * RTOS delay function. - */ + /* Wait the expected time calibration should take */ - ets_delay_us(us_time_estimate); + up_udelay(us_time_estimate); /* Wait for calibration to finish up to another us_time_estimate */ @@ -394,21 +498,20 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( TIMG_RTC_CALI_RDY) && (timeout_us > 0)) { timeout_us--; - ets_delay_us(1); + up_udelay(1); } - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - dig_32k_xtal_state); + /* Restore the previous clocks states */ - if (cal_clk == RTC_CAL_8MD256) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN, 0); - } + modifyreg32(RTC_CNTL_CLK_CONF_REG, clks_mask, clks_state); + + /* Verify if this calibration occured within the timeout */ if (timeout_us == 0) { - /* timed out waiting for calibration */ + /* Timed out waiting for calibration */ + rtcerr("Timed out waiting for calibration\n"); return 0; } @@ -437,7 +540,116 @@ static void IRAM_ATTR esp32_rtc_clk_slow_freq_set( REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); - ets_delay_us(DELAY_SLOW_CLK_SWITCH); + up_udelay(DELAY_SLOW_CLK_SWITCH); +} + +/**************************************************************************** + * Name: esp32_rtc_clk_32k_enable + * + * Description: + * Enable 32 kHz XTAL oscillator + * + * Input Parameters: + * ac - The current of XTAL oscillator. + * res - The resistance of XTAL oscillator. + * bias - The bias voltage of XTAL oscillator. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_rtc_clk_32k_enable(int ac, int res, int bias) +{ + modifyreg32(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | + RTC_IO_X32N_RUE | RTC_IO_X32N_RDE | RTC_IO_X32N_FUN_IE | + RTC_IO_X32P_FUN_IE, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL); + + /* Set the parameters of xtal */ + + REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, ac); + REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, res); + REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, bias); + + /* Power up external xtal */ + + modifyreg32(RTC_IO_XTAL_32K_PAD_REG, 0, RTC_IO_XPD_XTAL_32K_M); +} + +/**************************************************************************** + * Name: esp32_rtc_clk_8m_enable + * + * Description: + * Enable or disable 8 MHz internal oscillator + * + * Input Parameters: + * clk_8m_en - true to enable 8MHz generator, false to disable + * d256_en - true to enable /256 divider, false to disable + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) +{ + if (clk_8m_en) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M, 0); + + /* no need to wait once enabled by software */ + + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); + if (d256_en) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV, 0); + } + else + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M_DIV); + } + + up_udelay(DELAY_8M_ENABLE); + } + else + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, + RTC_CNTL_CK8M_WAIT_DEFAULT); + } +} + +/**************************************************************************** + * Name: esp32_rtc_clk_slow_freq_get_hz + * + * Description: + * Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * Input Parameters: + * None + * + * Returned Value: + * slow_clk_freq - RTC_SLOW_CLK frequency, in Hz + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32_rtc_clk_slow_freq_get_hz(void) +{ + enum esp32_rtc_slow_freq_e slow_clk_freq = + REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); + switch (slow_clk_freq) + { + case RTC_SLOW_FREQ_RTC: + return RTC_SLOW_CLK_FREQ_150K; + + case RTC_SLOW_FREQ_32K_XTAL: + return RTC_SLOW_CLK_FREQ_32K; + + case RTC_SLOW_FREQ_8MD256: + return RTC_SLOW_CLK_FREQ_8MD256; + } + + return OK; } /**************************************************************************** @@ -456,25 +668,125 @@ static void IRAM_ATTR esp32_rtc_clk_slow_freq_set( static void esp32_select_rtc_slow_clk(enum esp32_slow_clk_sel_e slow_clk) { + /* Number of times to repeat 32k XTAL calibration before giving up and + * switching to the internal RC. + */ + + int retry_32k_xtal = RETRY_CAL_EXT; uint32_t cal_val = 0; + uint64_t cal_dividend; enum esp32_rtc_slow_freq_e rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; do { + if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) + { + /* 32k XTAL oscillator needs to be enabled and running before + * it can be used. Hardware doesn't have a direct way of checking + * if the oscillator is running. Here we use rtc_clk_cal function + * to count the number of main XTAL cycles in the given number of + * 32k XTAL oscillator cycles. If the 32k XTAL has not started up, + * calibration will time out, returning 0. + */ + + rtcinfo("Waiting for 32k oscillator to start up\n"); + if (slow_clk == SLOW_CLK_32K_XTAL) + { + esp32_rtc_clk_32k_enable(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, + XTAL_32K_DBIAS_VAL); + } + else if (slow_clk == SLOW_CLK_32K_EXT_OSC) + { + esp32_rtc_clk_32k_enable(XTAL_32K_EXT_DAC_VAL, + XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL); + } + + if (SLOW_CLK_CAL_CYCLES > 0) + { + cal_val = esp32_rtc_clk_cal(RTC_CAL_32K_XTAL, + SLOW_CLK_CAL_CYCLES); + if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) + { + if (retry_32k_xtal-- > 0) + { + continue; + } + + rtc_slow_freq = RTC_SLOW_FREQ_RTC; + } + } + } + else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) + { + esp32_rtc_clk_8m_enable(true, true); + } + esp32_rtc_clk_slow_freq_set(rtc_slow_freq); + if (SLOW_CLK_CAL_CYCLES > 0) + { + /* 32k XTAL oscillator has some frequency drift at startup. Improve + * calibration routine to wait until the frequency is stable. + */ - /* TODO: 32k XTAL oscillator has some frequency drift at startup. - * Improve calibration routine to wait until the frequency is stable. - */ - - cal_val = esp32_rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); + cal_val = esp32_rtc_clk_cal(RTC_CAL_RTC_MUX, + SLOW_CLK_CAL_CYCLES); + } + else + { + cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; + cal_val = (uint32_t) (cal_dividend / + esp32_rtc_clk_slow_freq_get_hz()); + } } while (cal_val == 0); - + rtcinfo("RTC_SLOW_CLK calibration value: %d\n", cal_val); putreg32((uint32_t)cal_val, RTC_SLOW_CLK_CAL_REG); } +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Name: esp32_rt_cb_handler + * + * Description: + * RT-Timer service routine + * + * Input Parameters: + * arg - Information about the RT-Timer configuration. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32_rt_cb_handler(FAR void *arg) +{ + FAR struct alm_cbinfo_s *cbinfo = (struct alm_cbinfo_s *)arg; + alm_callback_t cb; + FAR void *cb_arg; + int alminfo_id; + + DEBUGASSERT(cbinfo != NULL); + alminfo_id = cbinfo->index; + DEBUGASSERT((RTC_ALARM0 <= alminfo_id) && + (alminfo_id < RTC_ALARM_LAST)); + + if (cbinfo->ac_cb != NULL) + { + /* Alarm callback */ + + cb = cbinfo->ac_cb; + cb_arg = (FAR void *)cbinfo->ac_arg; + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + cbinfo->deadline_us = 0; + cb(cb_arg, alminfo_id); + } +} + +#endif /* CONFIG_RTC_DRIVER */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -748,7 +1060,7 @@ void IRAM_ATTR esp32_rtc_bbpll_configure( /* Raise the voltage */ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M); - ets_delay_us(DELAY_PLL_DBIAS_RAISE); + up_udelay(DELAY_PLL_DBIAS_RAISE); /* Configure 480M PLL */ @@ -826,10 +1138,19 @@ void IRAM_ATTR esp32_rtc_bbpll_configure( * ****************************************************************************/ -void esp32_rtc_clk_set() +void esp32_rtc_clk_set(void) { enum esp32_rtc_fast_freq_e fast_freq = RTC_FAST_FREQ_8M; - enum esp32_slow_clk_sel_e slow_clk = RTC_SLOW_FREQ_RTC; + enum esp32_slow_clk_sel_e slow_clk = SLOW_CLK_150K; + +#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) + slow_clk = SLOW_CLK_32K_XTAL; +#elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC) + slow_clk = SLOW_CLK_32K_EXT_OSC; +#elif defined(CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256) + slow_clk = SLOW_CLK_8MD256; +#endif + esp32_rtc_clk_fast_freq_set(fast_freq); esp32_select_rtc_slow_clk(slow_clk); } @@ -848,7 +1169,7 @@ void esp32_rtc_clk_set() * ****************************************************************************/ -void IRAM_ATTR esp32_rtc_init() +void IRAM_ATTR esp32_rtc_init(void) { struct esp32_rtc_priv_s *priv = &esp32_rtc_priv; @@ -975,7 +1296,7 @@ uint64_t IRAM_ATTR esp32_rtc_time_get(void) while ((getreg32(RTC_CNTL_TIME_UPDATE_REG) & RTC_CNTL_TIME_VALID) == 0) { - ets_delay_us(1); + up_udelay(1); } modifyreg32(RTC_CNTL_INT_CLR_REG, 0, RTC_CNTL_TIME_VALID_INT_CLR); @@ -993,21 +1314,70 @@ uint64_t IRAM_ATTR esp32_rtc_time_get(void) * * Input Parameters: * time_in_us - Time interval in microseconds - * slow_clk_period - Period of slow clock in microseconds + * slow_clk_period - Period of slow clock in microseconds * * Returned Value: - * number of slow clock cycles + * Number of slow clock cycles * ****************************************************************************/ uint64_t IRAM_ATTR esp32_rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { - /* Overflow will happen in this function if time_in_us >= 2^45, - * which is about 400 days. TODO: fix overflow. - */ + uint64_t slow_clk_cycles = 0; + uint64_t max_time_in_us = (UINT64_C(1) << 45) - 1; - return (time_in_us << RTC_CLK_CAL_FRACT) / period; + /* Handle overflow that would happen if time_in_us >= 2^45 */ + + while (time_in_us > max_time_in_us) + { + time_in_us -= max_time_in_us; + slow_clk_cycles += ((max_time_in_us << RTC_CLK_CAL_FRACT) / period); + } + + slow_clk_cycles += ((time_in_us << RTC_CLK_CAL_FRACT) / period); + + return slow_clk_cycles; +} + +/**************************************************************************** + * Name: esp32_rtc_time_slowclk_to_us + * + * Description: + * Convert time interval from RTC_SLOW_CLK to microseconds + * + * Input Parameters: + * rtc_cycles - Time interval in RTC_SLOW_CLK cycles + * period - Period of slow clock in microseconds + * + * Returned Value: + * Time interval in microseconds + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32_rtc_time_slowclk_to_us(uint64_t rtc_cycles, + uint32_t period) +{ + return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; +} + +/**************************************************************************** + * Name: esp32_clk_slowclk_cal_get + * + * Description: + * Get the calibration value of RTC slow clock. + * + * Input Parameters: + * None + * + * Returned Value: + * the calibration value obtained using rtc_clk_cal + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32_clk_slowclk_cal_get(void) +{ + return getreg32(RTC_SLOW_CLK_CAL_REG); } /**************************************************************************** @@ -1093,11 +1463,11 @@ void IRAM_ATTR esp32_rtc_wait_for_slow_cycle(void) /* RDY needs some time to go low */ - ets_delay_us(1); + up_udelay(1); while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY)) { - ets_delay_us(1); + up_udelay(1); } } @@ -1433,3 +1803,471 @@ int IRAM_ATTR esp32_rtc_sleep_start(uint32_t wakeup_opt, RTC_CNTL_DBG_ATTEN_DEFAULT); return reject; } + +/**************************************************************************** + * Name: esp32_rtc_get_time_us + * + * Description: + * Get current value of RTC counter in microseconds + * + * Input Parameters: + * None + * + * Returned Value: + * Current value of RTC counter in microseconds + * + ****************************************************************************/ + +uint64_t esp32_rtc_get_time_us(void) +{ + const uint32_t cal = getreg32(RTC_SLOW_CLK_CAL_REG); + const uint64_t rtc_this_ticks = esp32_rtc_time_get(); + + /* RTC counter result is up to 2^48, calibration factor is up to 2^24, + * for a 32kHz clock. We need to calculate (assuming no overflow): + * (ticks * cal) >> RTC_CLK_CAL_FRACT. An overflow in the (ticks * cal) + * multiplication would cause time to wrap around after approximately + * 13 days, which is probably not enough for some applications. + * Therefore multiplication is split into two terms, for the lower 32-bit + * and the upper 16-bit parts of "ticks", i.e.: + * ((ticks_low + 2^32 * ticks_high) * cal) >> RTC_CLK_CAL_FRACT + */ + + const uint64_t ticks_low = rtc_this_ticks & UINT32_MAX; + const uint64_t ticks_high = rtc_this_ticks >> 32; + const uint64_t delta_time_us = ((ticks_low * cal) >> RTC_CLK_CAL_FRACT) + + ((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT)); + + return delta_time_us; +} + +/**************************************************************************** + * Name: esp32_rtc_set_boot_time + * + * Description: + * Set time to RTC register to replace the original boot time. + * + * Input Parameters: + * time_us - set time in microseconds. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32_rtc_set_boot_time(uint64_t time_us) +{ + putreg32((uint32_t)(time_us & UINT32_MAX), RTC_BOOT_TIME_LOW_REG); + putreg32((uint32_t)(time_us >> 32), RTC_BOOT_TIME_HIGH_REG); +} + +/**************************************************************************** + * Name: esp32_rtc_get_boot_time + * + * Description: + * Get time of RTC register to indicate the original boot time. + * + * Input Parameters: + * None + * + * Returned Value: + * time_us - get time in microseconds. + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32_rtc_get_boot_time(void) +{ + return ((uint64_t)getreg32(RTC_BOOT_TIME_LOW_REG)) + + (((uint64_t)getreg32(RTC_BOOT_TIME_HIGH_REG)) << 32); +} + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation is selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but CONFIG_RTC_HIRES is not set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +#ifndef CONFIG_RTC_HIRES +time_t up_rtc_time(void) +{ + uint64_t time_us; + irqstate_t flags; + + flags = spin_lock_irqsave(NULL); + + /* NOTE: RT-Timer starts to work after the board is initialized, and the + * RTC controller starts works after up_rtc_initialize is initialized. + * Since the system clock starts to work before the board is initialized, + * if CONFIG_RTC is enabled, the system time must be matched by the time + * of the RTC controller (up_rtc_initialize has already been initialized, + * and RT-Timer cannot work). + */ + + /* Determine if RT-Timer is started */ + + if (g_rt_timer_enabled == true) + { + /* Get the time from RT-Timer, the time interval between RTC + * controller and RT-Timer is stored in g_rtc_save->offset. + */ + + time_us = rt_timer_time_us() + g_rtc_save->offset + + esp32_rtc_get_boot_time(); + } + else + { + /* Get the time from RTC controller. */ + + time_us = esp32_rtc_get_time_us() + + esp32_rtc_get_boot_time(); + } + + spin_unlock_irqrestore(NULL, flags); + + return (time_t)(time_us / USEC_PER_SEC); +} +#endif /* !CONFIG_RTC_HIRES */ + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. + * + * Input Parameters: + * ts - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(FAR const struct timespec *ts) +{ + irqstate_t flags; + uint64_t now_us; + uint64_t rtc_offset_us; + + DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC); + flags = spin_lock_irqsave(NULL); + + now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC + + ts->tv_nsec / NSEC_PER_USEC; + if (g_rt_timer_enabled == true) + { + /* Set based on RT-Timer offset value. */ + + rtc_offset_us = now_us - rt_timer_time_us(); + } + else + { + /* Set based on the offset value of the RT controller. */ + + rtc_offset_us = now_us - esp32_rtc_get_time_us(); + } + + g_rtc_save->offset = 0; + esp32_rtc_set_boot_time(rtc_offset_us); + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ +#ifndef CONFIG_PM + /* Initialize RTC controller parameters */ + + esp32_rtc_init(); + esp32_rtc_clk_set(); +#endif + + g_rtc_save = &rtc_saved_data; + + /* If saved data is invalid, clear offset information */ + + if (g_rtc_save->magic != MAGIC_RTC_SAVE) + { + g_rtc_save->magic = MAGIC_RTC_SAVE; + g_rtc_save->offset = 0; + esp32_rtc_set_boot_time(0); + } + +#ifdef CONFIG_RTC_HIRES + /* Synchronize the base time to the RTC time */ + + up_rtc_gettime(&g_basetime); +#endif + + g_rtc_enabled = true; + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC time or RT-Timer. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the RTC time or RT-Timer value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(FAR struct timespec *tp) +{ + irqstate_t flags; + uint64_t time_us; + + flags = spin_lock_irqsave(NULL); + + if (g_rt_timer_enabled == true) + { + time_us = rt_timer_time_us() + g_rtc_save->offset + + esp32_rtc_get_boot_time(); + } + else + { + time_us = = esp32_rtc_get_time_us() + + esp32_rtc_get_boot_time(); + } + + tp->tv_sec = time_us / USEC_PER_SEC; + tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} +#endif /* CONFIG_RTC_HIRES */ + +#ifdef CONFIG_RTC_ALARM + +/**************************************************************************** + * Name: up_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_setalarm(FAR struct alm_setalarm_s *alminfo) +{ + struct rt_timer_args_s rt_timer_args; + FAR struct alm_cbinfo_s *cbinfo; + irqstate_t flags; + int ret = -EBUSY; + int id; + + DEBUGASSERT(alminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alminfo->as_id) && + (alminfo->as_id < RTC_ALARM_LAST)); + + /* Set the alarm in RT-Timer */ + + id = alminfo->as_id; + cbinfo = &g_alarmcb[id]; + + if (cbinfo->ac_cb == NULL) + { + /* Create the RT-Timer alarm */ + + flags = spin_lock_irqsave(NULL); + + if (cbinfo->alarm_hdl == NULL) + { + cbinfo->index = id; + rt_timer_args.arg = cbinfo; + rt_timer_args.callback = esp32_rt_cb_handler; + ret = rt_timer_create(&rt_timer_args, &cbinfo->alarm_hdl); + if (ret < 0) + { + rtcerr("ERROR: Failed to create rt_timer error=%d\n", ret); + spin_unlock_irqrestore(NULL, flags); + return ret; + } + } + + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + cbinfo->deadline_us = alminfo->as_time.tv_sec * USEC_PER_SEC + + alminfo->as_time.tv_nsec / NSEC_PER_USEC; + + if (cbinfo->alarm_hdl == NULL) + { + rtcerr("ERROR: failed to create alarm timer\n"); + } + else + { + rtcinfo("Start RTC alarm.\n"); + rt_timer_start(cbinfo->alarm_hdl, cbinfo->deadline_us, false); + ret = OK; + } + + spin_unlock_irqrestore(NULL, flags); + } + + return ret; +} + +/**************************************************************************** + * Name: up_rtc_cancelalarm + * + * Description: + * Cancel an alarm. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_cancelalarm(enum alm_id_e alarmid) +{ + FAR struct alm_cbinfo_s *cbinfo; + irqstate_t flags; + int ret = -ENODATA; + + DEBUGASSERT((RTC_ALARM0 <= alarmid) && + (alarmid < RTC_ALARM_LAST)); + + /* Set the alarm in hardware and enable interrupts */ + + cbinfo = &g_alarmcb[alarmid]; + + if (cbinfo->ac_cb != NULL) + { + flags = spin_lock_irqsave(NULL); + + /* Stop and delete the alarm */ + + rtcinfo("Cancel RTC alarm.\n"); + rt_timer_stop(cbinfo->alarm_hdl); + rt_timer_delete(cbinfo->alarm_hdl); + cbinfo->ac_cb = NULL; + cbinfo->deadline_us = 0; + cbinfo->alarm_hdl = NULL; + + spin_unlock_irqrestore(NULL, flags); + + ret = OK; + } + + return ret; +} + +/**************************************************************************** + * Name: up_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * tp - Location to return the timer match register. + * alarmid - Identifies the alarm to get. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_rdalarm(FAR struct timespec *tp, uint32_t alarmid) +{ + irqstate_t flags; + FAR struct alm_cbinfo_s *cbinfo; + DEBUGASSERT(tp != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarmid) && + (alarmid < RTC_ALARM_LAST)); + + flags = spin_lock_irqsave(NULL); + + /* Get the alarm according to the alarmid */ + + cbinfo = &g_alarmcb[alarmid]; + + tp->tv_sec = (rt_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us) / USEC_PER_SEC; + tp->tv_nsec = ((rt_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: up_rtc_timer_init + * + * Description: + * Init RTC timer. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_timer_init(void) +{ + /* RT-Timer enabled */ + + g_rt_timer_enabled = true; + + /* Get the time difference between rt_timer and RTC timer */ + + g_rtc_save->offset = esp32_rtc_get_time_us() - rt_timer_time_us(); + + return OK; +} + +#endif /* CONFIG_RTC_DRIVER */ \ No newline at end of file diff --git a/arch/xtensa/src/esp32/esp32_rtc.h b/arch/xtensa/src/esp32/esp32_rtc.h index 20915158fb8..3ce469b5dfa 100644 --- a/arch/xtensa/src/esp32/esp32_rtc.h +++ b/arch/xtensa/src/esp32/esp32_rtc.h @@ -30,6 +30,9 @@ ****************************************************************************/ #include +#include +#include +#include #include "hardware/esp32_soc.h" #ifndef __ASSEMBLY__ @@ -127,6 +130,31 @@ enum esp32_rtc_cal_sel_e RTC_CAL_32K_XTAL = 2 /* External 32 kHz XTAL */ }; +#ifdef CONFIG_RTC_ALARM + +/* The form of an alarm callback */ + +typedef CODE void (*alm_callback_t)(FAR void *arg, unsigned int alarmid); + +enum alm_id_e +{ + RTC_ALARM0 = 0, /* RTC ALARM 0 */ + RTC_ALARM1 = 1, /* RTC ALARM 1 */ + RTC_ALARM_LAST, +}; + +/* Structure used to pass parameters to set an alarm */ + +struct alm_setalarm_s +{ + int as_id; /* enum alm_id_e */ + struct timespec as_time; /* Alarm expiration time */ + alm_callback_t as_cb; /* Callback (if non-NULL) */ + FAR void *as_arg; /* Argument for callback */ +}; + +#endif /* CONFIG_RTC_ALARM */ + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -301,6 +329,39 @@ uint64_t esp32_rtc_time_get(void); uint64_t esp32_rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); +/**************************************************************************** + * Name: esp32_rtc_time_slowclk_to_us + * + * Description: + * Convert time interval from RTC_SLOW_CLK to microseconds + * + * Input Parameters: + * rtc_cycles - Time interval in RTC_SLOW_CLK cycles + * period - Period of slow clock in microseconds + * + * Returned Value: + * Time interval in microseconds + * + ****************************************************************************/ + +uint64_t esp32_rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/**************************************************************************** + * Name: esp32_clk_slowclk_cal_get + * + * Description: + * Get the calibration value of RTC slow clock. + * + * Input Parameters: + * None + * + * Returned Value: + * the calibration value obtained using rtc_clk_cal + * + ****************************************************************************/ + +uint32_t esp32_clk_slowclk_cal_get(void); + /**************************************************************************** * Name: esp32_rtc_bbpll_disable * @@ -414,6 +475,203 @@ void esp32_rtc_sleep_init(uint32_t flags); int esp32_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); +/**************************************************************************** + * Name: esp32_rtc_get_time_us + * + * Description: + * Get current value of RTC counter in microseconds + * + * Input Parameters: + * None + * + * Returned Value: + * Current value of RTC counter in microseconds + * + ****************************************************************************/ + +uint64_t esp32_rtc_get_time_us(void); + +/**************************************************************************** + * Name: esp32_rtc_set_boot_time + * + * Description: + * Set time to RTC register to replace the original boot time. + * + * Input Parameters: + * time_us - set time in microseconds. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_rtc_set_boot_time(uint64_t time_us); + +/**************************************************************************** + * Name: esp32_rtc_get_boot_time + * + * Description: + * Get time of RTC register to indicate the original boot time. + * + * Input Parameters: + * None + * + * Returned Value: + * time_us - get time in microseconds. + * + ****************************************************************************/ + +uint64_t esp32_rtc_get_boot_time(void); + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +#ifndef CONFIG_RTC_HIRES +time_t up_rtc_time(void); +#endif + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(FAR const struct timespec *ts); + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void); + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC clock/counter. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(FAR struct timespec *tp); +#endif + +#ifdef CONFIG_RTC_ALARM + +/**************************************************************************** + * Name: up_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_setalarm(FAR struct alm_setalarm_s *alminfo); + +/**************************************************************************** + * Name: up_rtc_cancelalarm + * + * Description: + * Cancel an alaram. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_cancelalarm(enum alm_id_e alarmid); + +/**************************************************************************** + * Name: up_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * tp - Location to return the timer match register. + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_rdalarm(FAR struct timespec *tp, uint32_t alarmid); + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: up_rtc_timer_init + * + * Description: + * Init RTC timer. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_timer_init(void); + +#endif /* CONFIG_RTC_DRIVER */ + #ifdef __cplusplus } #endif diff --git a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c b/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c new file mode 100644 index 00000000000..e2ca2edb973 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c @@ -0,0 +1,565 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "esp32_rtc.h" +#include "hardware/esp32_tim.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct esp32_cbinfo_s +{ + volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ + volatile FAR void *priv; /* Private argurment to accompany callback */ +}; +#endif + +/* This is the private type for the RTC state. It must be cast compatible + * with struct rtc_lowerhalf_s. + */ + +struct esp32_lowerhalf_s +{ + /* This is the contained reference to the read-only, lower-half + * operations vtable (which may lie in FLASH or ROM) + */ + + FAR const struct rtc_ops_s *ops; +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct esp32_cbinfo_s cbinfo[RTC_ALARM_LAST]; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Prototypes for static methods in struct rtc_ops_s */ + +static int rtc_lh_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime); +static int rtc_lh_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime); +static bool rtc_lh_havesettime(FAR struct rtc_lowerhalf_s *lower); + +#ifdef CONFIG_RTC_ALARM +static void rtc_lh_alarm_callback(FAR void *arg, unsigned int alarmid); +static int rtc_lh_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo); +static int rtc_lh_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo); +static int rtc_lh_cancelalarm(FAR struct rtc_lowerhalf_s *lower, + int alarmid); +static int rtc_lh_rdalarm(FAR struct rtc_lowerhalf_s *lower, + FAR struct lower_rdalarm_s *alarminfo); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ESP32 RTC driver operations */ + +static const struct rtc_ops_s g_rtc_ops = +{ + .rdtime = rtc_lh_rdtime, + .settime = rtc_lh_settime, + .havesettime = rtc_lh_havesettime, +#ifdef CONFIG_RTC_ALARM + .setalarm = rtc_lh_setalarm, + .setrelative = rtc_lh_setrelative, + .cancelalarm = rtc_lh_cancelalarm, + .rdalarm = rtc_lh_rdalarm, +#endif +#ifdef CONFIG_RTC_PERIODIC + .setperiodic = NULL, + .cancelperiodic = NULL, +#endif +#ifdef CONFIG_RTC_IOCTL + .ioctl = NULL, +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + .destroy = NULL, +#endif +}; + +/* ESP32 RTC device state */ + +static struct esp32_lowerhalf_s g_rtc_lowerhalf = +{ + .ops = &g_rtc_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_lh_alarm_callback + * + * Description: + * This is the function that is called from the RTC driver when the alarm + * goes off. It just invokes the upper half drivers callback. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static void rtc_lh_alarm_callback(FAR void *arg, unsigned int alarmid) +{ + FAR struct esp32_lowerhalf_s *lower; + FAR struct esp32_cbinfo_s *cbinfo; + rtc_alarm_callback_t cb; + FAR void *priv; + + DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); + + lower = (struct esp32_lowerhalf_s *)arg; + cbinfo = &lower->cbinfo[alarmid]; + + /* Sample and clear the callback information to minimize the window in + * time in which race conditions can occur. + */ + + cb = (rtc_alarm_callback_t)cbinfo->cb; + priv = (FAR void *)cbinfo->priv; + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(priv, alarmid); + } +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_rdtime + * + * Description: + * Returns the current RTC time. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The location in which to return the current RTC time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int rtc_lh_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime) +{ +#if defined(CONFIG_RTC_HIRES) + FAR struct timespec ts; + int ret; + + /* Get the higher resolution time */ + + ret = up_rtc_gettime(&ts); + if (ret < 0) + { + goto errout; + } + + /* Convert the one second epoch time to a struct tm. This operation + * depends on the fact that struct rtc_time and struct tm are cast + * compatible. + */ + + if (!gmtime_r(&ts.tv_sec, (FAR struct tm *)rtctime)) + { + ret = -get_errno(); + goto errout; + } + + return OK; + +errout: + rtcerr("ERROR: failed to get RTC time: %d\n", ret); + return ret; + +#else + time_t timer; + + /* The resolution of time is only 1 second */ + + timer = up_rtc_time(); + + /* Convert the one second epoch time to a struct tm */ + + if (gmtime_r(&timer, (FAR struct tm *)rtctime) == 0) + { + int errcode = get_errno(); + DEBUGASSERT(errcode > 0); + + rtcerr("ERROR: gmtime_r failed: %d\n", errcode); + return -errcode; + } + + return OK; +#endif +} + +/**************************************************************************** + * Name: rtc_lh_settime + * + * Description: + * Implements the settime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The new time to set + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int rtc_lh_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime) +{ + struct timespec ts; + + /* Convert the struct rtc_time to a time_t. Here we assume that struct + * rtc_time is cast compatible with struct tm. + */ + + ts.tv_sec = mktime((FAR struct tm *)rtctime); + ts.tv_nsec = 0; + + /* Now set the time (with a accuracy of seconds) */ + + return up_rtc_settime(&ts); +} + +/**************************************************************************** + * Name: rtc_lh_havesettime + * + * Description: + * Implements the havesettime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Returns true if RTC date-time have been previously set. + * + ****************************************************************************/ + +static bool rtc_lh_havesettime(FAR struct rtc_lowerhalf_s *lower) +{ + if (esp32_rtc_get_boot_time() == 0) + { + return false; + } + + return true; +} + +/**************************************************************************** + * Name: rtc_lh_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo) +{ + FAR struct esp32_lowerhalf_s *priv; + FAR struct esp32_cbinfo_s *cbinfo; + struct alm_setalarm_s lowerinfo; + int ret; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + priv = (FAR struct esp32_lowerhalf_s *)lower; + + /* Remember the callback information */ + + cbinfo = &priv->cbinfo[alarminfo->id]; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + + /* Set the alarm */ + + lowerinfo.as_id = alarminfo->id; + lowerinfo.as_cb = rtc_lh_alarm_callback; + lowerinfo.as_arg = priv; + + /* Convert the RTC time to a timespec (1 second accuracy) */ + + lowerinfo.as_time.tv_sec = mktime((FAR struct tm *)&alarminfo->time); + lowerinfo.as_time.tv_nsec = 0; + + /* And set the alarm */ + + ret = up_rtc_setalarm(&lowerinfo); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo) +{ + struct lower_setalarm_s setalarm; + time_t seconds; + int ret = -EINVAL; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + if (alarminfo->reltime > 0) + { + flags = spin_lock_irqsave(NULL); + + seconds = alarminfo->reltime; + gmtime_r(&seconds, (FAR struct tm *)&setalarm.time); + + /* The set the alarm using this absolute time */ + + setalarm.id = alarminfo->id; + setalarm.cb = alarminfo->cb; + setalarm.priv = alarminfo->priv; + ret = rtc_lh_setalarm(lower, &setalarm); + + spin_unlock_irqrestore(NULL, flags); + } + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarmid - the alarm id + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid) +{ + FAR struct esp32_lowerhalf_s *priv; + FAR struct esp32_cbinfo_s *cbinfo; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); + + priv = (FAR struct esp32_lowerhalf_s *)lower; + + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo[alarmid]; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Then cancel the alarm */ + + return up_rtc_cancelalarm((enum alm_id_e)alarmid); +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_rdalarm + * + * Description: + * Query the RTC alarm. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to query the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_rdalarm(FAR struct rtc_lowerhalf_s *lower, + FAR struct lower_rdalarm_s *alarminfo) +{ + struct timespec ts; + int ret; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + flags = spin_lock_irqsave(NULL); + + ret = up_rtc_rdalarm(&ts, alarminfo->id); + localtime_r((FAR const time_t *)&ts.tv_sec, + (FAR struct tm *)alarminfo->time); + + spin_unlock_irqrestore(NULL, flags); + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the ESP32. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +FAR struct rtc_lowerhalf_s *esp32_rtc_lowerhalf(void) +{ + return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; +} + +/**************************************************************************** + * Name: esp32_rtc_driverinit + * + * Description: + * Bind the configuration timer to a timer lower half instance and register + * the timer drivers at 'devpath' + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32_rtc_driverinit(void) +{ + int ret; + FAR struct rtc_lowerhalf_s *lower; + + /* Instantiate the ESP32 lower-half RTC driver */ + + lower = esp32_rtc_lowerhalf(); + if (lower == NULL) + { + return ret; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + } + + /* Init RTC timer */ + + up_rtc_timer_init(); + + return ret; +} diff --git a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h b/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h new file mode 100644 index 00000000000..a5ef77ed98d --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_rtc_driverinit + * + * Description: + * Bind the configuration timer to a timer lower half instance and register + * the timer drivers at 'devpath' + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32_rtc_driverinit(void); + +#endif /* CONFIG_RTC_DRIVER */ + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H */ diff --git a/arch/xtensa/src/esp32/esp32_rtcheap.c b/arch/xtensa/src/esp32/esp32_rtcheap.c new file mode 100644 index 00000000000..17b20ffbbb2 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_rtcheap.c @@ -0,0 +1,191 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_rtcheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "esp32_rtcheap.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct mm_heap_s *g_rtcheap; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_rtcheap_initialize + * + * Description: + * Initialize the RTC heap. + * + ****************************************************************************/ + +void esp32_rtcheap_initialize(void) +{ + void *start; + size_t size; + + /* These values come from the linker scripts. Check boards/xtensa/esp32. */ + + extern uint8_t *_srtcheap; + extern uint8_t *_ertcheap; + + start = (void *)&_srtcheap; + size = (size_t)((uintptr_t)&_ertcheap - (uintptr_t)&_srtcheap); + g_rtcheap = mm_initialize("rtcheap", start, size); +} + +/**************************************************************************** + * Name: esp32_rtcheap_malloc + * + * Description: + * Allocate memory from the RTC heap. + * + * Parameters: + * size - Size (in bytes) of the memory region to be allocated. + * + ****************************************************************************/ + +void *esp32_rtcheap_malloc(size_t size) +{ + return mm_malloc(g_rtcheap, size); +} + +/**************************************************************************** + * Name: esp32_rtcheap_calloc + * + * Description: + * Calculates the size of the allocation and allocate memory from + * the RTC heap. + * + ****************************************************************************/ + +void *esp32_rtcheap_calloc(size_t n, size_t elem_size) +{ + return mm_calloc(g_rtcheap, n, elem_size); +} + +/**************************************************************************** + * Name: esp32_rtcheap_realloc + * + * Description: + * Reallocate memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32_rtcheap_realloc(void *ptr, size_t size) +{ + return mm_realloc(g_rtcheap, ptr, size); +} + +/**************************************************************************** + * Name: esp32_rtcheap_zalloc + * + * Description: + * Allocate and zero memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32_rtcheap_zalloc(size_t size) +{ + return mm_zalloc(g_rtcheap, size); +} + +/**************************************************************************** + * Name: esp32_rtcheap_free + * + * Description: + * Free memory from the RTC heap. + * + ****************************************************************************/ + +void esp32_rtcheap_free(void *mem) +{ + mm_free(g_rtcheap, mem); +} + +/**************************************************************************** + * Name: esp32_rtcheap_memalign + * + * Description: + * memalign requests more than enough space from malloc, finds a region + * within that chunk that meets the alignment request and then frees any + * leading or trailing space. + * + * The alignment argument must be a power of two (not checked). 8-byte + * alignment is guaranteed by normal malloc calls. + * + * Parameters: + * alignment - Requested alignment. + * size - Size (in bytes) of the memory region to be allocated. + * + ****************************************************************************/ + +void *esp32_rtcheap_memalign(size_t alignment, size_t size) +{ + return mm_memalign(g_rtcheap, alignment, size); +} + +/**************************************************************************** + * Name: esp32_rtcheap_heapmember + * + * Description: + * Check if an address lies in the RTC heap. + * + * Parameters: + * mem - The address to check. + * + * Return Value: + * True if the address is a member of the RTC heap. False if not. + * + ****************************************************************************/ + +bool esp32_rtcheap_heapmember(void *mem) +{ + return mm_heapmember(g_rtcheap, mem); +} + +/**************************************************************************** + * Name: esp32_rtcheap_mallinfo + * + * Description: + * mallinfo returns a copy of updated current heap information for the + * user heap. + * + * Parameters: + * info - Where memory information will be copied. + * + ****************************************************************************/ + +int esp32_rtcheap_mallinfo(struct mallinfo *info) +{ + return mm_mallinfo(g_rtcheap, info); +} diff --git a/arch/xtensa/src/esp32/esp32_rtcheap.h b/arch/xtensa/src/esp32/esp32_rtcheap.h new file mode 100644 index 00000000000..e235fdabb0a --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_rtcheap.h @@ -0,0 +1,149 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_rtcheap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RTCHEAP_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_RTCHEAP_H + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +struct mallinfo; /* Forward reference, see malloc.h */ + +/**************************************************************************** + * Name: esp32_rtcheap_initialize + * + * Description: + * Initialize the RTC heap. + * + ****************************************************************************/ + +void esp32_rtcheap_initialize(void); + +/**************************************************************************** + * Name: esp32_rtcheap_malloc + * + * Description: + * Allocate memory from the RTC heap. + * + * Parameters: + * size - Size (in bytes) of the memory region to be allocated. + * + ****************************************************************************/ + +void *esp32_rtcheap_malloc(size_t size); + +/**************************************************************************** + * Name: esp32_rtcheap_calloc + * + * Description: + * Calculates the size of the allocation and allocate memory from + * the RTC heap. + * + ****************************************************************************/ + +void *esp32_rtcheap_calloc(size_t n, size_t elem_size); + +/**************************************************************************** + * Name: esp32_rtcheap_realloc + * + * Description: + * Reallocate memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32_rtcheap_realloc(void *ptr, size_t size); + +/**************************************************************************** + * Name: esp32_rtcheap_zalloc + * + * Description: + * Allocate and zero memory from the RTC heap. + * + ****************************************************************************/ + +void *esp32_rtcheap_zalloc(size_t size); + +/**************************************************************************** + * Name: esp32_rtcheap_free + * + * Description: + * Free memory from the RTC heap. + * + ****************************************************************************/ + +void esp32_rtcheap_free(void *mem); + +/**************************************************************************** + * Name: esp32_rtcheap_memalign + * + * Description: + * memalign requests more than enough space from malloc, finds a region + * within that chunk that meets the alignment request and then frees any + * leading or trailing space. + * + * The alignment argument must be a power of two (not checked). 8-byte + * alignment is guaranteed by normal malloc calls. + * + ****************************************************************************/ + +void *esp32_rtcheap_memalign(size_t alignment, size_t size); + +/**************************************************************************** + * Name: esp32_rtcheap_heapmember + * + * Description: + * Check if an address lies in the RTC heap. + * + * Parameters: + * mem - The address to check + * + * Return Value: + * True if the address is a member of the RTC heap. False if not. + * + ****************************************************************************/ + +bool esp32_rtcheap_heapmember(void *mem); + +/**************************************************************************** + * Name: esp32_rtcheap_mallinfo + * + * Description: + * mallinfo returns a copy of updated current heap information for the + * user heap. + * + ****************************************************************************/ + +int esp32_rtcheap_mallinfo(struct mallinfo *info); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTCHEAP_H */ diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 623c19ab686..452e7571db7 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -48,9 +49,13 @@ #include "hardware/esp32_iomux.h" #include "hardware/esp32_gpio_sigmap.h" #include "hardware/esp32_uart.h" +#include "hardware/esp32_uhci.h" +#include "hardware/esp32_dma.h" #include "esp32_config.h" #include "esp32_gpio.h" #include "esp32_cpuint.h" +#include "esp32_dma.h" +#include "hardware/esp32_dport.h" /**************************************************************************** * Pre-processor Definitions @@ -120,6 +125,97 @@ #define UART_CLK_FREQ APB_CLK_FREQ +/* DMA related */ + +#ifdef CONFIG_SERIAL_RXDMA +# error "SERIAL_RXDMA is not supported in ESP32 due to a hardware issue" +#endif + +#ifdef CONFIG_SERIAL_TXDMA + +#define UART_SELECT_SHIFT UHCI_UART0_CE_S + +/* UART DMA RX/TX number of descriptors */ + +#define UART_DMADESC_NUM (CONFIG_UART_DMADESC_NUM) + +/* In case the three UARTs select TX DMA support, + * let DMA 0 exclusive to one and DMA 1 + * shared with others. + */ + +#if defined(CONFIG_ESP32_UART0_TXDMA) && defined(CONFIG_ESP32_UART1_TXDMA) && defined(CONFIG_ESP32_UART2_TXDMA) + #ifdef CONFIG_ESP32_UART0_EXC + #define UART0_DMA 0 + #define UART1_DMA 1 + #define UART2_DMA 1 + #elif defined(CONFIG_ESP32_UART1_EXC) + #define UART0_DMA 1 + #define UART1_DMA 0 + #define UART2_DMA 1 + #elif defined(CONFIG_ESP32_UART2_EXC) + #define UART0_DMA 1 + #define UART1_DMA 1 + #define UART2_DMA 0 + #endif + #define USE_DMA0 1 + #define USE_DMA1 1 +#else + #ifdef CONFIG_ESP32_UART0_TXDMA + #define UART0_DMA 0 + #define USE_DMA0 1 + #endif + #ifdef CONFIG_ESP32_UART1_TXDMA + #ifndef USE_DMA0 + #define UART1_DMA 0 + #define USE_DMA0 1 + #else + #define UART1_DMA 1 + #define USE_DMA1 1 + #endif + #endif + #ifdef CONFIG_ESP32_UART2_TXDMA + #ifndef USE_DMA0 + #define UART2_DMA 0 + #define USE_DMA0 1 + #else + #define UART2_DMA 1 + #define USE_DMA1 1 + #endif + #endif +#endif + +/* UART DMA controllers */ + +#if defined(USE_DMA0) && defined(USE_DMA1) +#define UART_DMA_CONTROLLERS_NUM 2 +#else +#define UART_DMA_CONTROLLERS_NUM 1 +#endif + +/* Semaphores to control access to each DMA. + * Theses semaphores ensure a new transfer is + * triggered only after the previous one is completed, + * and it also avoids competing issues with multiple UART + * instances requesting to the same DMA. + */ + +#ifdef USE_DMA0 +static sem_t g_dma0_sem; +#endif +#ifdef USE_DMA1 +static sem_t g_dma1_sem; +#endif + +/* UART DMA RX/TX descriptors */ + +struct esp32_dmadesc_s s_dma_rxdesc[UART_DMA_CONTROLLERS_NUM] + [UART_DMADESC_NUM]; +struct esp32_dmadesc_s s_dma_txdesc[UART_DMA_CONTROLLERS_NUM] + [UART_DMADESC_NUM]; + +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -130,19 +226,25 @@ struct esp32_config_s { - const uint32_t uartbase; /* Base address of UART registers */ + const uint8_t id; /* UART id */ uint8_t periph; /* UART peripheral ID */ uint8_t irq; /* IRQ number assigned to the peripheral */ uint8_t txpin; /* Tx pin number (0-39) */ uint8_t rxpin; /* Rx pin number (0-39) */ uint8_t txsig; /* Tx signal */ uint8_t rxsig; /* Rx signal */ -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) +#ifdef CONFIG_SERIAL_IFLOWCONTROL uint8_t rtspin; /* RTS pin number (0-39) */ - uint8_t ctspin; /* CTS pin number (0-39) */ uint8_t rtssig; /* RTS signal */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + uint8_t ctspin; /* CTS pin number (0-39) */ uint8_t ctssig; /* CTS signal */ #endif +#ifdef CONFIG_SERIAL_TXDMA + uint8_t dma_chan; /* DMA instance 0-1 */ + sem_t * dma_sem; /* DMA semaphore */ +#endif }; /* Current state of the UART */ @@ -156,8 +258,14 @@ struct esp32_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (5-9) */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) - bool flowc; /* Input flow control (RTS) enabled */ +#ifdef CONFIG_SERIAL_TXDMA + bool txdma; /* TX DMA enabled for this UART */ +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* Input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* Output flow control (CTS) enabled */ #endif }; @@ -178,11 +286,29 @@ static void esp32_send(struct uart_dev_s *dev, int ch); static void esp32_txint(struct uart_dev_s *dev, bool enable); static bool esp32_txready(struct uart_dev_s *dev); static bool esp32_txempty(struct uart_dev_s *dev); +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool esp32_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif +#ifdef CONFIG_SERIAL_TXDMA +static void esp32_dmasend(struct uart_dev_s *dev); +static void esp32_dmatxavail(struct uart_dev_s *dev); +static void dma_config(uint8_t dma_chan); +static void dma_attach(uint8_t dma_chan); +static inline void dma_enable_int(uint8_t dma_chan); +static inline void dma_disable_int(uint8_t dma_chan); +static int esp32_interrupt_dma(int cpuint, void *context, FAR void *arg); +#endif /**************************************************************************** * Private Data ****************************************************************************/ +#define UART_TX_FIFO_SIZE 128 +#define UART_RX_FIFO_FULL_THRHD 112 +#define UART_RX_TOUT_THRHD_VALUE 0x02 +#define UART_RX_FLOW_THRHD_VALUE 64 /* Almost half RX FIFO size */ + static const struct uart_ops_s g_uart_ops = { .setup = esp32_setup, @@ -193,13 +319,17 @@ static const struct uart_ops_s g_uart_ops = .receive = esp32_receive, .rxint = esp32_rxint, .rxavailable = esp32_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, -#endif .send = esp32_send, .txint = esp32_txint, .txready = esp32_txready, .txempty = esp32_txempty, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = esp32_rxflowcontrol, +#endif +#ifdef CONFIG_SERIAL_TXDMA + .dmasend = esp32_dmasend, + .dmatxavail = esp32_dmatxavail, +#endif }; /* I/O buffers */ @@ -222,19 +352,31 @@ static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; #ifdef CONFIG_ESP32_UART0 static const struct esp32_config_s g_uart0config = { - .uartbase = DR_REG_UART_BASE, + .id = 0, .periph = ESP32_PERIPH_UART, .irq = ESP32_IRQ_UART, .txpin = CONFIG_ESP32_UART0_TXPIN, .rxpin = CONFIG_ESP32_UART0_RXPIN, .txsig = U0TXD_OUT_IDX, .rxsig = U0RXD_IN_IDX, -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) +#ifdef CONFIG_SERIAL_IFLOWCONTROL .rtspin = CONFIG_ESP32_UART0_RTSPIN, - .ctspin = CONFIG_ESP32_UART0_CTSPIN, .rtssig = U0RTS_OUT_IDX, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .ctspin = CONFIG_ESP32_UART0_CTSPIN, .ctssig = U0CTS_IN_IDX, #endif +#ifdef CONFIG_SERIAL_TXDMA +#ifdef CONFIG_ESP32_UART0_TXDMA + .dma_chan = UART0_DMA, +#if UART0_DMA == 0 + .dma_sem = &g_dma0_sem, +#else + .dma_sem = &g_dma1_sem, +#endif +#endif +#endif }; static struct esp32_dev_s g_uart0priv = @@ -244,6 +386,27 @@ static struct esp32_dev_s g_uart0priv = .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, .stopbits2 = CONFIG_UART0_2STOP, +#ifdef CONFIG_SERIAL_TXDMA +#ifdef CONFIG_ESP32_UART0_TXDMA + .txdma = true, /* TX DMA enabled for this UART */ +#else + .txdma = false, /* TX DMA disabled for this UART */ +#endif +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL +#ifdef CONFIG_UART0_IFLOWCONTROL + .iflow = true, /* Input flow control (RTS) enabled */ +#else + .iflow = false, /* Input flow control (RTS) disabled */ +#endif +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL +#ifdef CONFIG_UART0_OFLOWCONTROL + .oflow = true, /* Output flow control (CTS) enabled */ +#else + .oflow = false, /* Output flow control (CTS) disabled */ +#endif +#endif }; static uart_dev_t g_uart0port = @@ -268,19 +431,31 @@ static uart_dev_t g_uart0port = #ifdef CONFIG_ESP32_UART1 static const struct esp32_config_s g_uart1config = { - .uartbase = DR_REG_UART1_BASE, + .id = 1, .periph = ESP32_PERIPH_UART1, .irq = ESP32_IRQ_UART1, .txpin = CONFIG_ESP32_UART1_TXPIN, .rxpin = CONFIG_ESP32_UART1_RXPIN, .txsig = U1TXD_OUT_IDX, .rxsig = U1RXD_IN_IDX, -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) +#ifdef CONFIG_SERIAL_IFLOWCONTROL .rtspin = CONFIG_ESP32_UART1_RTSPIN, - .ctspin = CONFIG_ESP32_UART1_CTSPIN, .rtssig = U1RTS_OUT_IDX, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .ctspin = CONFIG_ESP32_UART1_CTSPIN, .ctssig = U1CTS_IN_IDX, #endif +#ifdef CONFIG_SERIAL_TXDMA +#ifdef CONFIG_ESP32_UART1_TXDMA + .dma_chan = UART1_DMA, +#if UART1_DMA == 0 + .dma_sem = &g_dma0_sem, +#else + .dma_sem = &g_dma1_sem, +#endif +#endif +#endif }; static struct esp32_dev_s g_uart1priv = @@ -290,6 +465,27 @@ static struct esp32_dev_s g_uart1priv = .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, +#ifdef CONFIG_SERIAL_TXDMA +#ifdef CONFIG_ESP32_UART1_TXDMA + .txdma = true, /* TX DMA enabled for this UART */ +#else + .txdma = false, /* TX DMA disabled for this UART */ +#endif +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL +#ifdef CONFIG_UART1_IFLOWCONTROL + .iflow = true, /* input flow control (RTS) enabled */ +#else + .iflow = false, /* input flow control (RTS) disabled */ +#endif +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL +#ifdef CONFIG_UART1_OFLOWCONTROL + .oflow = true, /* output flow control (CTS) enabled */ +#else + .oflow = false, /* output flow control (CTS) disabled */ +#endif +#endif }; static uart_dev_t g_uart1port = @@ -314,19 +510,31 @@ static uart_dev_t g_uart1port = #ifdef CONFIG_ESP32_UART2 static const struct esp32_config_s g_uart2config = { - .uartbase = DR_REG_UART2_BASE, + .id = 2, .periph = ESP32_PERIPH_UART2, .irq = ESP32_IRQ_UART2, .txpin = CONFIG_ESP32_UART2_TXPIN, .rxpin = CONFIG_ESP32_UART2_RXPIN, .txsig = U2TXD_OUT_IDX, .rxsig = U2RXD_IN_IDX, -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) +#ifdef CONFIG_SERIAL_IFLOWCONTROL .rtspin = CONFIG_ESP32_UART2_RTSPIN, - .ctspin = CONFIG_ESP32_UART2_CTSPIN, .rtssig = U2RTS_OUT_IDX, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .ctspin = CONFIG_ESP32_UART2_CTSPIN, .ctssig = U2CTS_IN_IDX, #endif +#ifdef CONFIG_SERIAL_TXDMA +#ifdef CONFIG_ESP32_UART2_TXDMA + .dma_chan = UART2_DMA, +#if UART2_DMA == 0 + .dma_sem = &g_dma0_sem, +#else + .dma_sem = &g_dma1_sem, +#endif +#endif +#endif }; static struct esp32_dev_s g_uart2priv = @@ -336,6 +544,27 @@ static struct esp32_dev_s g_uart2priv = .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, +#ifdef CONFIG_SERIAL_TXDMA +#ifdef CONFIG_ESP32_UART2_TXDMA + .txdma = true, /* TX DMA enabled for this UART */ +#else + .txdma = false, /* TX DMA disabled for this UART */ +#endif +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL +#ifdef CONFIG_UART2_IFLOWCONTROL + .iflow = true, /* input flow control (RTS) enabled */ +#else + .iflow = false, /* input flow control (RTS) disabled */ +#endif +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL +#ifdef CONFIG_UART2_OFLOWCONTROL + .oflow = true, /* output flow control (CTS) enabled */ +#else + .oflow = false, /* output flow control (CTS) disabled */ +#endif +#endif }; static uart_dev_t g_uart2port = @@ -359,23 +588,207 @@ static uart_dev_t g_uart2port = * Private Functions ****************************************************************************/ +#ifdef CONFIG_SERIAL_TXDMA /**************************************************************************** - * Name: esp32_serialin + * Name: esp32_dmasend + * + * Description: + * Prepare the descriptor linked-list and initialize a transfer. + * + * Parameters: + * priv - Pointer to the serial driver struct. + * ****************************************************************************/ -static inline uint32_t esp32_serialin(struct esp32_dev_s *priv, int offset) +static void esp32_dmasend(struct uart_dev_s *dev) { - return getreg32(priv->config->uartbase + offset); + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + + if (priv->txdma) + { + struct esp32_dmadesc_s *dmadesc; + uint8_t *tp; + #ifdef CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP + uint8_t *alloctp = NULL; + #endif + + /* If the buffer comes from PSRAM, allocate a new one from DRAM */ + + #ifdef CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP + if (esp32_ptr_extram(dev->dmatx.buffer)) + { + alloctp = xtensa_imm_malloc(dev->dmatx.length); + DEBUGASSERT(alloctp != NULL); + memcpy(alloctp, dev->dmatx.buffer, dev->dmatx.length); + tp = alloctp; + } + else + #endif + { + tp = (uint8_t *)dev->dmatx.buffer; + } + + /* Initialize descriptor linked-list. + * esp32_dma_init divides the buffer into the list, perform + * the required alignment and fill all descriptor words. + */ + + dmadesc = s_dma_txdesc[priv->config->dma_chan]; + + esp32_dma_init(dmadesc, UART_DMADESC_NUM, tp, + (uint32_t) dev->dmatx.length); + + /* Set the 1st descriptor address */ + + modifyreg32(UHCI_DMA_OUT_LINK_REG(priv->config->dma_chan), + UHCI_OUTLINK_ADDR_M, + (((uintptr_t) dmadesc) & UHCI_OUTLINK_ADDR_M)); + + /* Trigger DMA transfer */ + + modifyreg32(UHCI_DMA_OUT_LINK_REG(priv->config->dma_chan), + UHCI_OUTLINK_STOP_M, UHCI_OUTLINK_START_M); + + #ifdef CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP + if (alloctp != NULL) + { + xtensa_imm_free(alloctp); + } + #endif + } } /**************************************************************************** - * Name: esp32_serialout + * Name: esp32_dmatxavail + * + * Description: + * Verifies if the DMA is available for a transfer. If so, trigger a + * transfer. + * + * Parameters: + * priv - Pointer to the serial driver struct. + * ****************************************************************************/ -static inline void esp32_serialout(struct esp32_dev_s *priv, int offset, - uint32_t value) +static void esp32_dmatxavail(struct uart_dev_s *dev) { - putreg32(value, priv->config->uartbase + offset); + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + + /* Check if this UART instance has DMA TX enabled */ + + if (priv->txdma) + { + /* Try to acquire the semaphore. + * This semaphore is always unlocked at 1st time. + * Then, the next times, it is released when a DMA transfer + * is completed. + */ + + if (nxsem_trywait(priv->config->dma_sem) == OK) + { + if (priv->config->dma_chan == 0) + { + modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, DPORT_UHCI0_CLK_EN); + } + else + { + modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, DPORT_UHCI1_CLK_EN); + } + + modifyreg32(UHCI_CONF0_REG(priv->config->dma_chan), + UHCI_UART0_CE | UHCI_UART1_CE | UHCI_UART2_CE, + 1 << (UART_SELECT_SHIFT + priv->config->id)); + dma_enable_int(priv->config->dma_chan); + uart_xmitchars_dma(dev); + } + } +} +#endif + +#ifndef CONFIG_SUPPRESS_UART_CONFIG +/**************************************************************************** + * Name: esp32_reset_rx_fifo + * + * Description: + * Resets the RX FIFO. + * NOTE: We can not use rxfifo_rst to reset the hardware RX FIFO. + * + * Parameters: + * priv - Pointer to the serial driver struct. + * + ****************************************************************************/ + +static void esp32_reset_rx_fifo(struct esp32_dev_s *priv) +{ + uint32_t rx_status_reg = getreg32(UART_STATUS_REG(priv->config->id)); + uint32_t fifo_cnt = REG_MASK(rx_status_reg, UART_RXFIFO_CNT); + uint32_t mem_rx_status_reg = getreg32(UART_MEM_RX_STATUS_REG + (priv->config->id)); + uint32_t rd_address = REG_MASK(mem_rx_status_reg, UART_RD_ADDRESS); + uint32_t wr_address = REG_MASK(mem_rx_status_reg, UART_WR_ADDRESS); + + while ((fifo_cnt != 0) || (rd_address != wr_address)) + { + getreg32(DR_UART_FIFO_REG(priv->config->id)); + + rx_status_reg = getreg32(UART_STATUS_REG(priv->config->id)); + fifo_cnt = REG_MASK(rx_status_reg, UART_RXFIFO_CNT); + mem_rx_status_reg = getreg32(UART_MEM_RX_STATUS_REG(priv->config->id)); + rd_address = REG_MASK(mem_rx_status_reg, UART_RD_ADDRESS); + wr_address = REG_MASK(mem_rx_status_reg, UART_WR_ADDRESS); + } +} + +#endif + +/**************************************************************************** + * Name: esp32_get_rx_fifo_len + * + * Description: + * Get the real value on rx fixo. + * RX_FIFO_CNT shouldn't be used alone accordingly to: + * https://www.espressif.com/sites/default/files/documentation/eco_ + * and_workarounds_for_bugs_in_esp32_en.pdf. + * So, some arithmetic with the read and write RX FIFO pointers are + * necessary. + * + * Parameters: + * priv - Pointer to the serial driver struct. + * + * Return: + * The number of bytes in RX fifo. + * + ****************************************************************************/ + +static uint32_t esp32_get_rx_fifo_len(struct esp32_dev_s *priv) +{ + uint32_t rd_address; + uint32_t wr_address; + uint32_t fifo_cnt; + uint32_t mem_rx_status_reg; + uint32_t rx_status_reg; + uint32_t len; + + mem_rx_status_reg = getreg32(UART_MEM_RX_STATUS_REG(priv->config->id)); + rd_address = REG_MASK(mem_rx_status_reg, UART_RD_ADDRESS); + wr_address = REG_MASK(mem_rx_status_reg, UART_WR_ADDRESS); + rx_status_reg = getreg32(UART_STATUS_REG(priv->config->id)); + fifo_cnt = REG_MASK(rx_status_reg, UART_RXFIFO_CNT); + + if (wr_address > rd_address) + { + len = wr_address - rd_address; + } + else if (wr_address < rd_address) + { + len = (wr_address + 128) - rd_address; + } + else + { + len = fifo_cnt > 0 ? 128 : 0; + } + + return len; } /**************************************************************************** @@ -389,7 +802,7 @@ static inline void esp32_restoreuartint(struct esp32_dev_s *priv, * (assuming all interrupts disabled) */ - esp32_serialout(priv, UART_INT_ENA_OFFSET, intena); + putreg32(intena, UART_INT_ENA_REG(priv->config->id)); } /**************************************************************************** @@ -408,12 +821,12 @@ static void esp32_disableallints(struct esp32_dev_s *priv, uint32_t *intena) { /* Return the current interrupt mask */ - *intena = esp32_serialin(priv, UART_INT_ENA_OFFSET); + *intena = getreg32(UART_INT_ENA_REG(priv->config->id)); } /* Disable all interrupts */ - esp32_serialout(priv, UART_INT_ENA_OFFSET, 0); + putreg32(0, UART_INT_ENA_REG(priv->config->id)); leave_critical_section(flags); } @@ -446,15 +859,16 @@ static int esp32_setup(struct uart_dev_s *dev) conf0 = UART_TICK_REF_ALWAYS_ON; -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) - /* Check if flow control is enabled */ +#ifdef CONFIG_SERIAL_OFLOWCONTROL + /* Check if output flow control is enabled for this UART controller. */ - if (priv->flowc) + if (priv->oflow) { - /* Enable hardware flow control */ + /* Enable output hardware flow control */ conf0 |= UART_TX_FLOW_EN; } + #endif /* OR in settings for the selected number of bits */ @@ -504,45 +918,43 @@ static int esp32_setup(struct uart_dev_s *dev) regval = (clkdiv >> 4) << UART_CLKDIV_S; regval |= (clkdiv & 15) << UART_CLKDIV_FRAG_S; - esp32_serialout(priv, UART_CLKDIV_OFFSET, regval); - - /* Configure UART pins - * - * Internal signals can be output to multiple GPIO pads. - * But only one GPIO pad can connect with input signal - */ - - esp32_configgpio(priv->config->txpin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->txpin, priv->config->txsig, 0, 0); - - esp32_configgpio(priv->config->rxpin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->rxpin, priv->config->rxsig, 0); - -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) - esp32_configgpio(priv->config->rtspin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->rtspin, priv->config->rtssig, 0, 0); - - esp32_configgpio(priv->config->ctspin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->ctspin, priv->config->ctssig, 0); -#endif + putreg32(regval, UART_CLKDIV_REG(priv->config->id)); /* Enable RX and error interrupts. Clear and pending interrtupt */ regval = UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA | UART_RXFIFO_TOUT_INT_ENA; - esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); + putreg32(regval, UART_INT_ENA_REG(priv->config->id)); - esp32_serialout(priv, UART_INT_CLR_OFFSET, 0xffffffff); + putreg32(UINT32_MAX, UART_INT_CLR_REG(priv->config->id)); + + /* Reset the RX and TX FIFO */ + + esp32_reset_rx_fifo(priv); /* Configure and enable the UART */ - esp32_serialout(priv, UART_CONF0_OFFSET, conf0); - regval = (112 << UART_RXFIFO_FULL_THRHD_S) | - (0x02 << UART_RX_TOUT_THRHD_S) | - UART_RX_TOUT_EN; - esp32_serialout(priv, UART_CONF1_OFFSET, regval); -#endif + putreg32(conf0, UART_CONF0_REG(priv->config->id)); + regval = VALUE_TO_FIELD(UART_RX_FIFO_FULL_THRHD, UART_RXFIFO_FULL_THRHD) | + VALUE_TO_FIELD(UART_RX_TOUT_THRHD_VALUE, UART_RX_TOUT_THRHD) | + UART_RX_TOUT_EN; + putreg32(regval, UART_CONF1_REG(priv->config->id)); +#ifdef CONFIG_SERIAL_IFLOWCONTROL + /* Check if input flow control is enabled for this UART controller */ + + if (priv->iflow) + { + /* Enable input hardware flow control */ + + regval |= VALUE_TO_FIELD(UART_RX_FLOW_THRHD_VALUE, UART_RX_FLOW_THRHD) + | UART_RX_FLOW_EN; + modifyreg32(UART_CONF1_REG(priv->config->id), 0, regval); + } + +#endif + +#endif return OK; } @@ -569,7 +981,7 @@ static void esp32_shutdown(struct uart_dev_s *dev) do { - status = esp32_serialin(priv, UART_STATUS_OFFSET); + status = getreg32(UART_STATUS_REG(priv->config->id)); } while ((status & UART_TXFIFO_CNT_M) != 0); @@ -577,32 +989,13 @@ static void esp32_shutdown(struct uart_dev_s *dev) esp32_disableallints(priv, NULL); - /* Revert pins to inputs and detach UART signals */ - - esp32_configgpio(priv->config->txpin, INPUT); - esp32_gpio_matrix_out(priv->config->txsig, - MATRIX_DETACH_OUT_SIG, true, false); - - esp32_configgpio(priv->config->rxpin, INPUT); - esp32_gpio_matrix_in(priv->config->rxsig, MATRIX_DETACH_IN_LOW_PIN, false); - -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) - esp32_configgpio(priv->config->rtspin, INPUT); - esp32_gpio_matrix_out(priv->config->rtssig, - MATRIX_DETACH_OUT_SIG, true, false); - - esp32_configgpio(priv->config->ctspin, INPUT); - esp32_gpio_matrix_in(priv->config->ctssig, - MATRIX_DETACH_IN_LOW_PIN, false); -#endif - /* Unconfigure and disable the UART */ - esp32_serialout(priv, UART_CONF0_OFFSET, 0); - esp32_serialout(priv, UART_CONF1_OFFSET, 0); + putreg32(0, UART_CONF0_REG(priv->config->id)); + putreg32(0, UART_CONF1_REG(priv->config->id)); - esp32_serialout(priv, UART_INT_ENA_OFFSET, 0); - esp32_serialout(priv, UART_INT_CLR_OFFSET, 0xffffffff); + putreg32(0, UART_INT_ENA_REG(priv->config->id)); + putreg32(UINT32_MAX, UART_INT_CLR_REG(priv->config->id)); } /**************************************************************************** @@ -701,6 +1094,249 @@ static void esp32_detach(struct uart_dev_s *dev) priv->cpuint = -1; } +#ifdef CONFIG_SERIAL_TXDMA + +/**************************************************************************** + * Name: dma_enable_int + * + * Description: + * Enable UHCI interrupt. + * + * Parameters: + * dma_chan - DMA instance. + * + ****************************************************************************/ + +static inline void dma_enable_int(uint8_t dma_chan) +{ + /* Interrupt will be triggered when all descriptors were transferred or + * in case of error with output descriptor. + */ + + uint32_t int_mask = UHCI_OUT_TOTAL_EOF_INT_ENA_M | + UHCI_OUT_DSCR_ERR_INT_ENA_M; + putreg32(int_mask, UHCI_INT_ENA_REG(dma_chan)); +} + +/**************************************************************************** + * Name: dma_disable_int. + * + * Description: + * Disable UHCI interrupt. + * + * Parameters: + * dma_chan - DMA instance. + * + ****************************************************************************/ + +static inline void dma_disable_int(uint8_t dma_chan) +{ + putreg32(0, UHCI_INT_ENA_REG(dma_chan)); +} + +/**************************************************************************** + * Name: dma_attach + * + * Description: + * Configure an DMA interrupt, attach to a CPU interrupt and enable it. + * + * Parameters: + * dma_chan - DMA instance. + * + ****************************************************************************/ + +static void dma_attach(uint8_t dma_chan) +{ + int dma_cpuint; + int cpu; + int ret; + + /* Clear the interrupts */ + + putreg32(UINT32_MAX, UHCI_INT_CLR_REG(dma_chan)); + + /* Allocate a level-sensitive, priority 1 CPU interrupt for the DMA */ + + dma_cpuint = esp32_alloc_levelint(1); + if (dma_cpuint < 0) + { + /* Failed to allocate a CPU interrupt of this type */ + + dmaerr("Failed to allocate a CPU interrupt.\n"); + return; + } + + /* Set up to receive peripheral interrupts on the current CPU */ + +#ifdef CONFIG_SMP + cpu = up_cpu_index(); +#else + cpu = 0; +#endif + + /* Attach the UHCI interrupt to the allocated CPU interrupt + * and attach and enable the IRQ. + */ + + up_disable_irq(dma_cpuint); + + if (dma_chan == 0) + { + esp32_attach_peripheral(cpu, ESP32_PERIPH_UHCI0, dma_cpuint); + ret = irq_attach(ESP32_IRQ_UHCI0, esp32_interrupt_dma, NULL); + } + else + { + esp32_attach_peripheral(cpu, ESP32_PERIPH_UHCI1, dma_cpuint); + ret = irq_attach(ESP32_IRQ_UHCI1, esp32_interrupt_dma, NULL); + } + + if (ret == OK) + { + /* Enable the CPU interrupt */ + + up_enable_irq(dma_cpuint); + } + else + { + dmaerr("Couldn't attach IRQ to handler.\n"); + } +} + +/**************************************************************************** + * Name: esp32_interrupt + * + * Description: + * DMA interrupt. + * + ****************************************************************************/ + +static int esp32_interrupt_dma(int irq, void *context, FAR void *arg) +{ + uint32_t value; + uint32_t status; + uint8_t uhci = irq - ESP32_IRQ_UHCI0; + struct uart_dev_s *dev = NULL; + + /* Disable interrupt, stop UHCI, save interrupt status + * clear interrupts. + */ + + status = getreg32(UHCI_INT_ST_REG(uhci)); + dma_disable_int(uhci); + modifyreg32(UHCI_DMA_OUT_LINK_REG(uhci), + UHCI_OUTLINK_START_M, UHCI_OUTLINK_STOP_M); + putreg32(UINT32_MAX, UHCI_INT_CLR_REG(uhci)); + + /* Check which UART is using DMA now and calls + * uart_xmitchars_done to adjust TX software buffer. + */ + + value = getreg32(UHCI_CONF0_REG(uhci)); + value = value & (UHCI_UART2_CE_M | UHCI_UART1_CE_M | UHCI_UART0_CE_M); + + switch (value) + { +#ifdef CONFIG_ESP32_UART0_TXDMA + case UHCI_UART0_CE_M: + dev = &g_uart0port; + break; +#endif + +#ifdef CONFIG_ESP32_UART1_TXDMA + case UHCI_UART1_CE_M: + dev = &g_uart1port; + break; +#endif + +#ifdef CONFIG_ESP32_UART2_TXDMA + case UHCI_UART2_CE_M: + dev = &g_uart2port; + break; +#endif + + default: + dmaerr("No UART selected\n"); + } + + if (dev != NULL) + { + dev->dmatx.nbytes = dev->dmatx.length; + uart_xmitchars_done(dev); + } + + /* Post on semaphore to allow new transfers and share the resource. + * Disable clk gate for UHCI, so RX can work properly. + */ + + if (status & UHCI_OUT_TOTAL_EOF_INT_ENA_M) + { + if (uhci == 0) + { + nxsem_post(&g_dma0_sem); + modifyreg32(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN, 0); + } + #ifdef USE_DMA1 + else + { + nxsem_post(&g_dma1_sem); + modifyreg32(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN, 0); + } + #endif + } + else + { + dmaerr("Error with the output descriptor in DMA 0\n"); + } + + return OK; +} + +/**************************************************************************** + * Name: dma_config + * + * Description: + * Configure the UHCI peripheral. + * + * Parameters: + * dma_chan - DMA instance. + * + ****************************************************************************/ + +static void dma_config(uint8_t dma_chan) +{ + /* Enable peripheral CLK and RST module */ + + if (dma_chan == 0) + { + modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, DPORT_UHCI0_CLK_EN); + modifyreg32(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST, DPORT_UHCI0_RST); + modifyreg32(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST, 0); + } + else + { + modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, DPORT_UHCI1_CLK_EN); + modifyreg32(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST, DPORT_UHCI1_RST); + modifyreg32(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST, 0); + } + + /* Configure registers */ + + putreg32(UHCI_CLK_EN_M, UHCI_CONF0_REG(dma_chan)); + + putreg32(0, UHCI_CONF1_REG(dma_chan)); + putreg32(UHCI_CHECK_OWNER | (100 << UHCI_DMA_INFIFO_FULL_THRS_S), + UHCI_CONF1_REG(dma_chan)); + + putreg32(0, UHCI_HUNG_CONF_REG(dma_chan)); + + modifyreg32(UHCI_CONF0_REG(dma_chan), UHCI_IN_RST, UHCI_IN_RST); + modifyreg32(UHCI_CONF0_REG(dma_chan), UHCI_IN_RST, 0); + modifyreg32(UHCI_CONF0_REG(dma_chan), UHCI_OUT_RST, UHCI_OUT_RST); + modifyreg32(UHCI_CONF0_REG(dma_chan), UHCI_OUT_RST, 0); +} +#endif + /**************************************************************************** * Name: esp32_interrupt * @@ -734,16 +1370,16 @@ static int esp32_interrupt(int cpuint, void *context, FAR void *arg) for (passes = 0; passes < 256 && handled; passes++) { handled = false; - priv->status = esp32_serialin(priv, UART_INT_RAW_OFFSET); - status = esp32_serialin(priv, UART_STATUS_OFFSET); - enabled = esp32_serialin(priv, UART_INT_ENA_OFFSET); + priv->status = getreg32(UART_INT_RAW_REG(priv->config->id)); + status = getreg32(UART_STATUS_REG(priv->config->id)); + enabled = getreg32(UART_INT_ENA_REG(priv->config->id)); /* Clear pending interrupts */ regval = (UART_RXFIFO_FULL_INT_CLR | UART_FRM_ERR_INT_CLR | UART_RXFIFO_TOUT_INT_CLR | UART_TX_DONE_INT_CLR | UART_TXFIFO_EMPTY_INT_CLR); - esp32_serialout(priv, UART_INT_CLR_OFFSET, regval); + putreg32(regval, UART_INT_CLR_REG(priv->config->id)); /* Are Rx interrupts enabled? The upper layer may hold off Rx input * by disabling the Rx interrupts if there is no place to saved the @@ -755,7 +1391,7 @@ static int esp32_interrupt(int cpuint, void *context, FAR void *arg) { /* Is there any data waiting in the Rx FIFO? */ - nfifo = (status & UART_RXFIFO_CNT_M) >> UART_RXFIFO_CNT_S; + nfifo = esp32_get_rx_fifo_len(priv); if (nfifo > 0) { /* Received data in the RXFIFO! ... Process incoming bytes */ @@ -772,7 +1408,7 @@ static int esp32_interrupt(int cpuint, void *context, FAR void *arg) if ((enabled & (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA)) != 0) { - nfifo = (status & UART_TXFIFO_CNT_M) >> UART_TXFIFO_CNT_S; + nfifo = REG_MASK(status, UART_TXFIFO_CNT); if (nfifo < 0x7f) { /* The TXFIFO is not full ... process outgoing bytes */ @@ -843,8 +1479,11 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg) /* Return flow control */ -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) - termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= (priv->oflow) ? CCTS_OFLOW : 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= (priv->iflow) ? CRTS_IFLOW : 0; #endif /* Return baud */ @@ -887,8 +1526,11 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg) uint8_t parity; uint8_t nbits; bool stop2; -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) - bool flowc; +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; #endif if (!termiosp) @@ -948,8 +1590,11 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg) /* Decode flow control */ -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) - flowc = (termiosp->c_cflag & (CCTS_OFLOW | CRTS_IFLOW)) != 0; +#ifdef CONFIG_SERIAL_IFLOWCONTROL + iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; #endif /* Verify that all settings are valid before committing */ @@ -961,8 +1606,11 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg) priv->parity = parity; priv->bits = nbits; priv->stopbits2 = stop2; -#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) - priv->flowc = flowc; +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = iflow; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = oflow; #endif /* effect the changes immediately - note that we do not * implement TCSADRAIN / TCSAFLUSH @@ -1000,6 +1648,7 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg) static int esp32_receive(struct uart_dev_s *dev, unsigned int *status) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + uint32_t rx_fifo; /* Return the error information in the saved status */ @@ -1008,8 +1657,9 @@ static int esp32_receive(struct uart_dev_s *dev, unsigned int *status) /* Then return the actual received byte */ - return (int)(esp32_serialin(priv, UART_FIFO_OFFSET) & - UART_RXFIFO_RD_BYTE_M); + rx_fifo = getreg32(DR_UART_FIFO_REG(priv->config->id)); + + return (int)REG_MASK(rx_fifo, UART_RXFIFO_RD_BYTE); } /**************************************************************************** @@ -1035,20 +1685,20 @@ static void esp32_rxint(struct uart_dev_s *dev, bool enable) */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS - regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); + regval = getreg32(UART_INT_ENA_REG(priv->config->id)); regval |= (UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); - esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); + putreg32(regval, UART_INT_ENA_REG(priv->config->id)); #endif } else { /* Disable the RX interrupts */ - regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); + regval = getreg32(UART_INT_ENA_REG(priv->config->id)); regval &= ~(UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); - esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); + putreg32(regval, UART_INT_ENA_REG(priv->config->id)); } leave_critical_section(flags); @@ -1065,9 +1715,7 @@ static void esp32_rxint(struct uart_dev_s *dev, bool enable) static bool esp32_rxavailable(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - - return ((esp32_serialin(priv, UART_STATUS_OFFSET) - & UART_RXFIFO_CNT_M) > 0); + return esp32_get_rx_fifo_len(priv) > 0; } /**************************************************************************** @@ -1082,7 +1730,7 @@ static void esp32_send(struct uart_dev_s *dev, int ch) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - esp32_serialout(priv, UART_FIFO_OFFSET, (uint32_t)ch); + putreg32((uint32_t)ch, AHB_UART_FIFO_REG(priv->config->id)); } /**************************************************************************** @@ -1097,38 +1745,41 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; irqstate_t flags; - int regval; - - flags = enter_critical_section(); - - if (enable) +#ifdef CONFIG_SERIAL_TXDMA + if (priv->txdma == false) { - /* Set to receive an interrupt when the TX holding register register - * is empty - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); - regval |= (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA); - esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); - - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ - - uart_xmitchars(dev); #endif - } - else - { - /* Disable the TX interrupt */ + flags = enter_critical_section(); - regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); - regval &= ~(UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA); - esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); - } + if (enable) + { + /* Set to receive an interrupt when the TX holding register + * is empty. + */ - leave_critical_section(flags); + #ifndef CONFIG_SUPPRESS_SERIAL_INTS + modifyreg32(UART_INT_ENA_REG(priv->config->id), + 0, (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA)); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + #endif + } + else + { + /* Disable the TX interrupt */ + + modifyreg32(UART_INT_ENA_REG(priv->config->id), + (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA), 0); + } + + leave_critical_section(flags); +#ifdef CONFIG_SERIAL_TXDMA + } +#endif } /**************************************************************************** @@ -1142,12 +1793,13 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) static bool esp32_txready(struct uart_dev_s *dev) { uint32_t txcnt; + uint32_t reg; struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - txcnt = (esp32_serialin(priv, UART_STATUS_OFFSET) >> UART_TXFIFO_CNT_S) & - UART_TXFIFO_CNT_V; + reg = getreg32(UART_STATUS_REG(priv->config->id)); + txcnt = REG_MASK(reg, UART_TXFIFO_CNT); - return txcnt < 0x7f; + return (txcnt < (UART_TX_FIFO_SIZE - 1)); } /**************************************************************************** @@ -1162,14 +1814,159 @@ static bool esp32_txempty(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - return ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_TXFIFO_CNT_M) - == 0); + return ((getreg32(UART_STATUS_REG(priv->config->id)) + & UART_TXFIFO_CNT_M) == 0); } +#ifndef CONFIG_SUPPRESS_UART_CONFIG +/**************************************************************************** + * Name: esp32_config_pins + * + * Description: + * Performs the pin configuration. + * + * Parameters: + * priv - Pointer to the serial driver struct. + * + ****************************************************************************/ + +static void esp32_config_pins(struct esp32_dev_s *priv) +{ + /* Configure UART pins + * + * Internal signals can be output to multiple GPIO pads. + * But only one GPIO pad can connect with input signal + */ + + esp32_configgpio(priv->config->txpin, OUTPUT_FUNCTION_3); + esp32_gpio_matrix_out(priv->config->txpin, priv->config->txsig, 0, 0); + + esp32_configgpio(priv->config->rxpin, INPUT_FUNCTION_3); + esp32_gpio_matrix_in(priv->config->rxpin, priv->config->rxsig, 0); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + esp32_configgpio(priv->config->rtspin, OUTPUT_FUNCTION_3); + esp32_gpio_matrix_out(priv->config->rtspin, priv->config->rtssig, + 0, 0); + } + +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->oflow) + { + esp32_configgpio(priv->config->ctspin, INPUT_FUNCTION_3); + esp32_gpio_matrix_in(priv->config->ctspin, priv->config->ctssig, 0); + } +#endif +} + +/**************************************************************************** + * Name: esp32_rxflowcontrol + * + * Description: + * Called when upper half RX buffer is full (or exceeds configured + * watermark levels if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if UART activated RX flow control to block more incoming + * data. + * NOTE: ESP32 has a hardware RX FIFO threshold mechanism to control RTS + * line and to stop receiving data. This is very similar to the concept + * behind upper watermark level. The hardware threshold is used here + * to control the RTS line. When setting the threshold to zero, RTS will + * imediately be asserted. If nbuffered = 0 or the lower watermark is + * crossed and the serial driver decides to disable RX flow control, the + * threshold will be changed to UART_RX_FLOW_THRHD_VALUE, which is almost + * half the HW RX FIFO capacity. It keeps some space to keep the data + * received after the RTS is asserted, but before the sender stops. + * + * Input Parameters: + * dev - UART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool esp32_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + bool ret = false; + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + + if (priv->iflow) + { + if (nbuffered == 0 || upper == false) + { + uint32_t regval; + + /* Empty buffer, RTS should be de-asserted and logic in above + * layers should re-enable RX interrupt. + */ + + regval = VALUE_TO_FIELD(UART_RX_FLOW_THRHD_VALUE, + UART_RX_FLOW_THRHD); + modifyreg32(UART_CONF1_REG(priv->config->id), 0, regval); + esp32_rxint(dev, true); + ret = false; + } + else + { + /* If the RX buffer is not zero and watermarks are not enabled, + * then this function is called to announce RX buffer is full. + * The first thing it should do is to imediately assert RTS. + */ + + modifyreg32(UART_CONF1_REG(priv->config->id), UART_RX_FLOW_THRHD_M, + 0); + + /* Software RX FIFO is full, so besides asserting RTS, it's + * necessary to disable RX interrupts to prevent remaining bytes + * (that arrive after asserting RTS) to be pushed to the + * SW RX FIFO. + */ + + esp32_rxint(dev, false); + ret = true; + } + } + + return ret; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp32_lowsetup + * + * Description: + * Performs the pin configuration for all UARTs. + * This functions is intended to be called in the __start function. + * + ****************************************************************************/ + +void esp32_lowsetup(void) +{ + esp32_config_pins(TTYS0_DEV.priv); +#ifdef TTYS1_DEV + esp32_config_pins(TTYS1_DEV.priv); +#endif +#ifdef TTYS2_DEV + esp32_config_pins(TTYS2_DEV.priv); +#endif +} + +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ /**************************************************************************** * Name: xtensa_early_serial_initialize * @@ -1181,7 +1978,7 @@ static bool esp32_txempty(struct uart_dev_s *dev) ****************************************************************************/ #ifdef USE_EARLYSERIALINIT -void xtensa_early_serial_initialize(void) +void xtensa_earlyserialinit(void) { /* NOTE: All GPIO configuration for the UARTs was performed in * esp32_lowsetup @@ -1215,7 +2012,7 @@ void xtensa_early_serial_initialize(void) * ****************************************************************************/ -void xtensa_serial_initialize(void) +void xtensa_serialinit(void) { /* Register the console */ @@ -1231,6 +2028,21 @@ void xtensa_serial_initialize(void) #endif #ifdef TTYS2_DEV uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif + + /* DMA related */ + +#ifdef CONFIG_SERIAL_TXDMA +#ifdef USE_DMA0 + nxsem_init(&g_dma0_sem, 0, 1); + dma_config(0); + dma_attach(0); +#endif +#ifdef USE_DMA1 + nxsem_init(&g_dma1_sem, 0, 1); + dma_config(1); + dma_attach(1); +#endif #endif } diff --git a/arch/xtensa/src/esp32/esp32_spi.c b/arch/xtensa/src/esp32/esp32_spi.c index 623de9c6c33..2be5a3462a0 100644 --- a/arch/xtensa/src/esp32/esp32_spi.c +++ b/arch/xtensa/src/esp32/esp32_spi.c @@ -26,12 +26,14 @@ #ifdef CONFIG_ESP32_SPI +#include #include #include #include #include #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_spi.h b/arch/xtensa/src/esp32/esp32_spi.h index 9c0f716fd76..afd3946b8ce 100644 --- a/arch/xtensa/src/esp32/esp32_spi.h +++ b/arch/xtensa/src/esp32/esp32_spi.h @@ -121,7 +121,7 @@ int esp32_spi3_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); int esp32_spibus_uninitialize(FAR struct spi_dev_s *dev); /**************************************************************************** - * Name: esp32_spislv_sctrlr_initialize + * Name: esp32_spislv_ctrlr_initialize * * Description: * Initialize the selected SPI slave bus @@ -134,23 +134,23 @@ int esp32_spibus_uninitialize(FAR struct spi_dev_s *dev); * ****************************************************************************/ -FAR struct spi_sctrlr_s *esp32_spislv_sctrlr_initialize(int port); +FAR struct spi_slave_ctrlr_s *esp32_spislv_ctrlr_initialize(int port); /**************************************************************************** - * Name: esp32_spislv_sctrlr_uninitialize + * Name: esp32_spislv_ctrlr_uninitialize * * Description: * Uninitialize an SPI slave bus * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI slave controller interface instance * * Returned Value: * OK if success or fail * ****************************************************************************/ -int esp32_spislv_sctrlr_uninitialize(FAR struct spi_sctrlr_s *sctrlr); +int esp32_spislv_ctrlr_uninitialize(FAR struct spi_slave_ctrlr_s *ctrlr); #endif /* CONFIG_ESP32_SPI */ diff --git a/arch/xtensa/src/esp32/esp32_spi_slave.c b/arch/xtensa/src/esp32/esp32_spi_slave.c index 0bab2888a2e..e16b6453ea6 100644 --- a/arch/xtensa/src/esp32/esp32_spi_slave.c +++ b/arch/xtensa/src/esp32/esp32_spi_slave.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -127,9 +128,11 @@ struct esp32_spislv_priv_s { /* Externally visible part of the SPI slave controller interface */ - struct spi_sctrlr_s sctrlr; + struct spi_slave_ctrlr_s ctrlr; - struct spi_sdev_s *sdev; /* Externally visible part of the SPI interface */ + /* Externally visible part of the SPI interface */ + + struct spi_slave_dev_s *dev; const struct esp32_spislv_config_s *config; /* Port configuration */ @@ -166,22 +169,23 @@ struct esp32_spislv_priv_s * Private Function Prototypes ****************************************************************************/ -static void esp32_spislv_setmode(FAR struct spi_sctrlr_s *dev, +static void esp32_spislv_setmode(FAR struct spi_slave_ctrlr_s *ctrlr, enum spi_mode_e mode); -static void esp32_spislv_setbits(FAR struct spi_sctrlr_s *dev, int nbits); +static void esp32_spislv_setbits(FAR struct spi_slave_ctrlr_s *ctrlr, + int nbits); static int esp32_spislv_interrupt(int irq, void *context, FAR void *arg); -static void esp32_spislv_initialize(FAR struct spi_sctrlr_s *dev); -static void esp32_spislv_bind(struct spi_sctrlr_s *sctrlr, - struct spi_sdev_s *sdev, - enum spi_smode_e mode, +static void esp32_spislv_initialize(FAR struct spi_slave_ctrlr_s *ctrlr); +static void esp32_spislv_bind(struct spi_slave_ctrlr_s *ctrlr, + struct spi_slave_dev_s *dev, + enum spi_slave_mode_e mode, int nbits); -static void esp32_spislv_unbind(struct spi_sctrlr_s *sctrlr); -static int esp32_spislv_enqueue(struct spi_sctrlr_s *sctrlr, +static void esp32_spislv_unbind(struct spi_slave_ctrlr_s *ctrlr); +static int esp32_spislv_enqueue(struct spi_slave_ctrlr_s *ctrlr, FAR const void *data, size_t nwords); -static bool esp32_spislv_qfull(struct spi_sctrlr_s *sctrlr); -static void esp32_spislv_qflush(struct spi_sctrlr_s *sctrlr); -static size_t esp32_spislv_qpoll(FAR struct spi_sctrlr_s *sctrlr); +static bool esp32_spislv_qfull(struct spi_slave_ctrlr_s *ctrlr); +static void esp32_spislv_qflush(struct spi_slave_ctrlr_s *ctrlr); +static size_t esp32_spislv_qpoll(FAR struct spi_slave_ctrlr_s *ctrlr); /**************************************************************************** * Private Data @@ -220,7 +224,7 @@ static const struct esp32_spislv_config_s esp32_spi2_config = .clk_outsig = HSPICLK_OUT_IDX }; -static const struct spi_sctrlrops_s esp32_spi2slv_ops = +static const struct spi_slave_ctrlrops_s esp32_spi2slv_ops = { .bind = esp32_spislv_bind, .unbind = esp32_spislv_unbind, @@ -232,7 +236,7 @@ static const struct spi_sctrlrops_s esp32_spi2slv_ops = static struct esp32_spislv_priv_s esp32_spi2slv_priv = { - .sctrlr = + .ctrlr = { .ops = &esp32_spi2slv_ops }, @@ -274,7 +278,7 @@ static const struct esp32_spislv_config_s esp32_spi3_config = .clk_outsig = VSPICLK_OUT_MUX_IDX }; -static const struct spi_sctrlrops_s esp32_spi3slv_ops = +static const struct spi_slave_ctrlrops_s esp32_spi3slv_ops = { .bind = esp32_spislv_bind, .unbind = esp32_spislv_unbind, @@ -286,7 +290,7 @@ static const struct spi_sctrlrops_s esp32_spi3slv_ops = static struct esp32_spislv_priv_s esp32_spi3slv_priv = { - .sctrlr = + .ctrlr = { .ops = &esp32_spi3slv_ops }, @@ -445,18 +449,18 @@ static inline bool esp32_spi_iomux(struct esp32_spislv_priv_s *priv) * Name: esp32_spislv_setmode * * Description: - * Set the SPI mode. + * Set the SPI Slave mode. * * Input Parameters: - * dev - Device-specific state data - * mode - The SPI mode requested + * ctrlr - SPI Slave controller interface instance + * mode - Requested SPI Slave mode * * Returned Value: - * none + * None. * ****************************************************************************/ -static void esp32_spislv_setmode(FAR struct spi_sctrlr_s *dev, +static void esp32_spislv_setmode(FAR struct spi_slave_ctrlr_s *ctrlr, enum spi_mode_e mode) { uint32_t ck_idle_edge; @@ -465,7 +469,7 @@ static void esp32_spislv_setmode(FAR struct spi_sctrlr_s *dev, uint32_t miso_delay_num; uint32_t mosi_delay_mode; uint32_t mosi_delay_num; - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)dev; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; spiinfo("mode=%d\n", mode); @@ -574,20 +578,21 @@ static void esp32_spislv_setmode(FAR struct spi_sctrlr_s *dev, * Name: esp32_spislv_setbits * * Description: - * Set the number if bits per word. + * Set the number of bits per word. * * Input Parameters: - * dev - Device-specific state data - * nbits - The number of bits in an SPI word. + * ctrlr - SPI Slave controller interface instance + * nbits - The number of bits in an SPI word * * Returned Value: - * none + * None. * ****************************************************************************/ -static void esp32_spislv_setbits(FAR struct spi_sctrlr_s *dev, int nbits) +static void esp32_spislv_setbits(FAR struct spi_slave_ctrlr_s *ctrlr, + int nbits) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)dev; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; spiinfo("nbits=%d\n", nbits); @@ -618,7 +623,7 @@ static int esp32_io_interrupt(int irq, void *context, FAR void *arg) if (priv->process == true) { priv->process = false; - SPI_SDEV_SELECT(priv->sdev, false); + SPIS_DEV_SELECT(priv->dev, false); } return 0; @@ -676,7 +681,7 @@ static void esp32_spislv_tx(struct esp32_spislv_priv_s *priv) * * Description: * Process SPI slave RX. Process SPI slave device receive callback by - * calling SPI_SDEV_RECEIVE and prepare for next RX. + * calling SPIS_DEV_RECEIVE and prepare for next RX. * * DMA mode : Initialize register to prepare for RX * @@ -694,7 +699,7 @@ static void esp32_spislv_rx(struct esp32_spislv_priv_s *priv) uint32_t recv_n; uint32_t regval; - tmp = SPI_SDEV_RECEIVE(priv->sdev, priv->rxbuffer, + tmp = SPIS_DEV_RECEIVE(priv->dev, priv->rxbuffer, BYTES2WORDS(priv, priv->rxlen)); recv_n = WORDS2BYTES(priv, tmp); @@ -769,7 +774,7 @@ static int esp32_spislv_interrupt(int irq, void *context, FAR void *arg) if (priv->process == false) { - SPI_SDEV_SELECT(priv->sdev, true); + SPIS_DEV_SELECT(priv->dev, true); priv->process = true; } @@ -823,7 +828,7 @@ static int esp32_spislv_interrupt(int irq, void *context, FAR void *arg) if (priv->process == true && esp32_gpioread(priv->config->cs_pin)) { priv->process = false; - SPI_SDEV_SELECT(priv->sdev, false); + SPIS_DEV_SELECT(priv->dev, false); } return 0; @@ -833,19 +838,19 @@ static int esp32_spislv_interrupt(int irq, void *context, FAR void *arg) * Name: esp32_spislv_initialize * * Description: - * Initialize ESP32 SPI hardware interface + * Initialize ESP32 SPI Slave hardware interface * * Input Parameters: - * dev - Device-specific state data + * ctrlr - SPI Slave controller interface instance * * Returned Value: * None * ****************************************************************************/ -static void esp32_spislv_initialize(FAR struct spi_sctrlr_s *dev) +static void esp32_spislv_initialize(FAR struct spi_slave_ctrlr_s *ctrlr) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)dev; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; const struct esp32_spislv_config_s *config = priv->config; uint32_t regval; @@ -930,8 +935,8 @@ static void esp32_spislv_initialize(FAR struct spi_sctrlr_s *dev) esp32_spi_set_reg(priv, SPI_SLV_RDBUF_DLEN_OFFSET, 256 - 1); } - esp32_spislv_setmode(dev, config->mode); - esp32_spislv_setbits(dev, 8); + esp32_spislv_setmode(ctrlr, config->mode); + esp32_spislv_setbits(ctrlr, 8); esp32_spi_set_regbits(priv, SPI_SLAVE_OFFSET, SPI_SYNC_RESET_M); esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_SYNC_RESET_M); @@ -945,19 +950,19 @@ static void esp32_spislv_initialize(FAR struct spi_sctrlr_s *dev) * Name: esp32_spislv_deinit * * Description: - * Deinitialize ESP32 SPI hardware interface + * Deinitialize ESP32 SPI Slave hardware interface * * Input Parameters: - * dev - Device-specific state data + * ctrlr - SPI Slave controller interface instance * * Returned Value: * None * ****************************************************************************/ -static void esp32_spislv_deinit(FAR struct spi_sctrlr_s *dev) +static void esp32_spislv_deinit(FAR struct spi_slave_ctrlr_s *ctrlr) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)dev; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; esp32_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin)); esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_INT_EN_M); @@ -984,45 +989,45 @@ static void esp32_spislv_deinit(FAR struct spi_sctrlr_s *dev) * transfers. * * Input Parameters: - * sctrlr - SPI slave controller interface instance - * sdev - SPI slave device interface instance - * mode - The SPI mode requested - * nbits - The number of bits requests + * ctrlr - SPI slave controller interface instance + * dev - SPI slave device interface instance + * mode - The SPI Slave mode requested + * nbits - The number of bits requested * * Returned Value: * none * ****************************************************************************/ -static void esp32_spislv_bind(struct spi_sctrlr_s *sctrlr, - struct spi_sdev_s *sdev, - enum spi_smode_e mode, +static void esp32_spislv_bind(struct spi_slave_ctrlr_s *ctrlr, + struct spi_slave_dev_s *dev, + enum spi_slave_mode_e mode, int nbits) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; irqstate_t flags; - spiinfo("sdev=%p mode=%d nbits=%d\n", sdev, mode, nbits); + spiinfo("dev=%p mode=%d nbits=%d\n", dev, mode, nbits); - DEBUGASSERT(priv != NULL && priv->sdev == NULL && sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev == NULL && dev != NULL); flags = enter_critical_section(); - priv->sdev = sdev; + priv->dev = dev; - SPI_SDEV_SELECT(sdev, false); + SPIS_DEV_SELECT(dev, false); - SPI_SDEV_CMDDATA(sdev, false); + SPIS_DEV_CMDDATA(dev, false); priv->rxlen = 0; priv->txlen = 0; priv->txen = false; - esp32_spislv_initialize(sctrlr); + esp32_spislv_initialize(ctrlr); - esp32_spislv_setmode(sctrlr, mode); - esp32_spislv_setbits(sctrlr, nbits); + esp32_spislv_setmode(ctrlr, mode); + esp32_spislv_setbits(ctrlr, nbits); up_enable_irq(priv->cpuint); @@ -1040,23 +1045,23 @@ static void esp32_spislv_bind(struct spi_sctrlr_s *sctrlr, * controller driver to its initial state, * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI slave controller interface instance * * Returned Value: * none * ****************************************************************************/ -static void esp32_spislv_unbind(struct spi_sctrlr_s *sctrlr) +static void esp32_spislv_unbind(struct spi_slave_ctrlr_s *ctrlr) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; irqstate_t flags; DEBUGASSERT(priv != NULL); - spiinfo("Unbinding %p\n", priv->sdev); + spiinfo("Unbinding %p\n", priv->dev); - DEBUGASSERT(priv->sdev != NULL); + DEBUGASSERT(priv->dev != NULL); flags = enter_critical_section(); @@ -1071,7 +1076,7 @@ static void esp32_spislv_unbind(struct spi_sctrlr_s *sctrlr) modifyreg32(DPORT_PERIP_CLK_EN_REG, priv->config->clk_bit, 0); - priv->sdev = NULL; + priv->dev = NULL; leave_critical_section(flags); } @@ -1085,7 +1090,7 @@ static void esp32_spislv_unbind(struct spi_sctrlr_s *sctrlr) * effect on anyin-process or currently "committed" transfers * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI slave controller interface instance * data - Command/data mode data value to be shifted out. The width of * the data must be the same as the nbits parameter previously * provided to the bind() methods. @@ -1097,19 +1102,19 @@ static void esp32_spislv_unbind(struct spi_sctrlr_s *sctrlr) * ****************************************************************************/ -static int esp32_spislv_enqueue(struct spi_sctrlr_s *sctrlr, +static int esp32_spislv_enqueue(struct spi_slave_ctrlr_s *ctrlr, FAR const void *data, size_t nwords) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; size_t n = WORDS2BYTES(priv, nwords); size_t bufsize; irqstate_t flags; int ret; - spiinfo("spi_enqueue(sctrlr=%p, data=%p, nwords=%d)\n", - sctrlr, data, nwords); - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + spiinfo("spi_enqueue(ctrlr=%p, data=%p, nwords=%d)\n", + ctrlr, data, nwords); + DEBUGASSERT(priv != NULL && priv->dev != NULL); flags = enter_critical_section(); @@ -1145,22 +1150,22 @@ static int esp32_spislv_enqueue(struct spi_sctrlr_s *sctrlr, * additional word to the queue. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI slave controller interface instance * * Returned Value: * true if the output wueue is full * ****************************************************************************/ -static bool esp32_spislv_qfull(struct spi_sctrlr_s *sctrlr) +static bool esp32_spislv_qfull(struct spi_slave_ctrlr_s *ctrlr) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; irqstate_t flags; bool ret = 0; - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev != NULL); - spiinfo("spi_qfull(sctrlr=%p)\n", sctrlr); + spiinfo("spi_qfull(ctrlr=%p)\n", ctrlr); flags = enter_critical_section(); ret = priv->txlen == SPI_SLAVE_BUFSIZE; @@ -1178,19 +1183,19 @@ static bool esp32_spislv_qfull(struct spi_sctrlr_s *sctrlr) * "committed" output values may not be flushed. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI slave controller interface instance * * Returned Value: * None * ****************************************************************************/ -static void esp32_spislv_qflush(struct spi_sctrlr_s *sctrlr) +static void esp32_spislv_qflush(struct spi_slave_ctrlr_s *ctrlr) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; irqstate_t flags; - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev != NULL); flags = enter_critical_section(); priv->rxlen = 0; @@ -1206,7 +1211,7 @@ static void esp32_spislv_qflush(struct spi_sctrlr_s *sctrlr) * Tell the controller to output all the receive queue data. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI slave controller interface instance * * Returned Value: * Number of units of width "nbits" left in the rx queue. If the device @@ -1214,13 +1219,13 @@ static void esp32_spislv_qflush(struct spi_sctrlr_s *sctrlr) * ****************************************************************************/ -static size_t esp32_spislv_qpoll(FAR struct spi_sctrlr_s *sctrlr) +static size_t esp32_spislv_qpoll(FAR struct spi_slave_ctrlr_s *ctrlr) { - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; irqstate_t flags; uint32_t n; - DEBUGASSERT(priv != NULL && priv->sdev != NULL); + DEBUGASSERT(priv != NULL && priv->dev != NULL); flags = enter_critical_section(); @@ -1233,7 +1238,7 @@ static size_t esp32_spislv_qpoll(FAR struct spi_sctrlr_s *sctrlr) } /**************************************************************************** - * Name: esp32_spislv_sctrlr_initialize + * Name: esp32_spislv_ctrlr_initialize * * Description: * Initialize the selected SPI slave bus @@ -1246,10 +1251,10 @@ static size_t esp32_spislv_qpoll(FAR struct spi_sctrlr_s *sctrlr) * ****************************************************************************/ -FAR struct spi_sctrlr_s *esp32_spislv_sctrlr_initialize(int port) +FAR struct spi_slave_ctrlr_s *esp32_spislv_ctrlr_initialize(int port) { int ret; - FAR struct spi_sctrlr_s *spislv_dev; + FAR struct spi_slave_ctrlr_s *spislv_dev; FAR struct esp32_spislv_priv_s *priv; irqstate_t flags; @@ -1269,7 +1274,7 @@ FAR struct spi_sctrlr_s *esp32_spislv_sctrlr_initialize(int port) return NULL; } - spislv_dev = (FAR struct spi_sctrlr_s *)priv; + spislv_dev = (FAR struct spi_slave_ctrlr_s *)priv; flags = enter_critical_section(); @@ -1327,25 +1332,25 @@ FAR struct spi_sctrlr_s *esp32_spislv_sctrlr_initialize(int port) } /**************************************************************************** - * Name: esp32_spislv_sctrlr_uninitialize + * Name: esp32_spislv_ctrlr_uninitialize * * Description: * Uninitialize an SPI slave bus * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI slave controller interface instance * * Returned Value: * OK if success or fail * ****************************************************************************/ -int esp32_spislv_sctrlr_uninitialize(FAR struct spi_sctrlr_s *sctrlr) +int esp32_spislv_ctrlr_uninitialize(FAR struct spi_slave_ctrlr_s *ctrlr) { irqstate_t flags; - struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; - DEBUGASSERT(sctrlr); + DEBUGASSERT(ctrlr); if (priv->refs == 0) { @@ -1366,7 +1371,7 @@ int esp32_spislv_sctrlr_uninitialize(FAR struct spi_sctrlr_s *sctrlr) priv->cpuint); esp32_free_cpuint(priv->cpuint); - esp32_spislv_deinit(sctrlr); + esp32_spislv_deinit(ctrlr); leave_critical_section(flags); diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c index 489be180660..571e06741af 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.c +++ b/arch/xtensa/src/esp32/esp32_spiflash.c @@ -27,6 +27,7 @@ #ifdef CONFIG_ESP32_SPIFLASH #include +#include #include #include #include diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c index 685387ab4c0..4276219cbd3 100644 --- a/arch/xtensa/src/esp32/esp32_spiram.c +++ b/arch/xtensa/src/esp32/esp32_spiram.c @@ -67,9 +67,9 @@ /* Let's to assume SPIFLASH SPEED == SPIRAM SPEED for now */ -#if CONFIG_ESP32_SPIRAM_SPEED_40M +#if defined(CONFIG_ESP32_SPIRAM_SPEED_40M) # define PSRAM_SPEED PSRAM_CACHE_F40M_S40M -#elif CONFIG_ESP32_SPIRAM_SPEED_80M +#elif defined(CONFIG_ESP32_SPIRAM_SPEED_80M) # define PSRAM_SPEED PSRAM_CACHE_F80M_S80M #else # error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!" diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index bc472bbdf12..6d97e54db16 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -40,6 +41,16 @@ #include "esp32_start.h" #include "esp32_spiram.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) up_puts(c) +#else +# define showprogress(c) +#endif + /**************************************************************************** * Public Data ****************************************************************************/ @@ -53,6 +64,10 @@ uint32_t g_idlestack[IDLETHREAD_STACKWORDS] * Public Functions ****************************************************************************/ +#ifndef CONFIG_SUPPRESS_UART_CONFIG +extern void esp32_lowsetup(void); +#endif + /**************************************************************************** * Name: __start * @@ -71,16 +86,6 @@ void IRAM_ATTR __start(void) uint32_t regval; uint32_t sp; - /* Kill the watchdog timer */ - - regval = getreg32(RTC_CNTL_WDTCONFIG0_REG); - regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN; - putreg32(regval, RTC_CNTL_WDTCONFIG0_REG); - - regval = getreg32(0x6001f048); /* DR_REG_BB_BASE+48 */ - regval &= ~(1 << 14); - putreg32(regval, 0x6001f048); - /* Make sure that normal interrupts are disabled. This is really only an * issue when we are started in un-usual ways (such as from IRAM). In this * case, we can at least defer some unexpected interrupts left over from @@ -89,22 +94,6 @@ void IRAM_ATTR __start(void) up_irq_disable(); -#ifdef CONFIG_STACK_COLORATION - { - register uint32_t *ptr; - register int i; - - /* If stack debug is enabled, then fill the stack with a recognizable - * value that we can use later to test for high water marks. - */ - - for (i = 0, ptr = g_idlestack; i < IDLETHREAD_STACKWORDS; i++) - { - *ptr++ = STACK_COLOR; - } - } -#endif - /* Move the stack to a known location. Although we were given a stack * pointer at start-up, we don't know where that stack pointer is * positioned with respect to our memory map. The only safe option is to @@ -132,16 +121,35 @@ void IRAM_ATTR __start(void) regval &= ~DPORT_APPCPU_CLKGATE_EN; putreg32(regval, DPORT_APPCPU_CTRL_B_REG); + /* The 2nd stage bootloader enables RTC WDT to check on startup sequence + * related issues in application. Hence disable that as we are about to + * start the NuttX environment. + */ + + putreg32(RTC_CNTL_WDT_WKEY_VALUE, RTC_CNTL_WDTWPROTECT_REG); + regval = getreg32(RTC_CNTL_WDTCONFIG0_REG); + regval &= ~RTC_CNTL_WDT_EN; + putreg32(regval, RTC_CNTL_WDTCONFIG0_REG); + putreg32(0, RTC_CNTL_WDTWPROTECT_REG); + /* Set CPU frequency configured in board.h */ esp32_clockconfig(); +#ifndef CONFIG_SUPPRESS_UART_CONFIG + /* Configure the UART so we can get debug output */ + + esp32_lowsetup(); +#endif + #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization */ - xtensa_early_serial_initialize(); + xtensa_earlyserialinit(); #endif + showprogress("A"); + #if defined(CONFIG_ESP32_SPIRAM_BOOT_INIT) esp_spiram_init_cache(); if (esp_spiram_init() != OK) @@ -166,6 +174,8 @@ void IRAM_ATTR __start(void) esp32_board_initialize(); + showprogress("B"); + /* Bring up NuttX */ nx_start(); diff --git a/arch/xtensa/src/esp32/esp32_textheap.c b/arch/xtensa/src/esp32/esp32_textheap.c new file mode 100644 index 00000000000..7e29c2f3617 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_textheap.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_textheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include + +#include "hardware/esp32_soc.h" + +#ifdef CONFIG_ESP32_IRAM_HEAP +#include "esp32_iramheap.h" +#endif + +#ifdef CONFIG_ESP32_RTC_HEAP +#include "esp32_rtcheap.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_ESP32_IRAM_HEAP) && !defined(CONFIG_ESP32_RTC_HEAP) +#error "No suitable heap available. Enable ESP32_IRAM_HEAP or ESP32_RTC_HEAP" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_textheap_memalign + * + * Description: + * Allocate memory from the text heap with the specified alignment. + * + ****************************************************************************/ + +FAR void *up_textheap_memalign(size_t align, size_t size) +{ + FAR void *ret = NULL; + + /* Prioritise allocating from RTC. If that fails, allocate from the + * main heap. + */ + +#ifdef CONFIG_ESP32_RTC_HEAP + ret = esp32_rtcheap_memalign(align, size); +#endif + + if (ret == NULL) + { + ret = esp32_iramheap_memalign(align, size); + } + + return ret; +} + +/**************************************************************************** + * Name: up_textheap_free + * + * Description: + * Free memory from the text heap. + * + ****************************************************************************/ + +void up_textheap_free(FAR void *p) +{ + if (p) + { +#ifdef CONFIG_ESP32_RTC_HEAP + if (esp32_ptr_rtcslow(p)) + { + esp32_rtcheap_free(p); + } + else +#endif + { + esp32_iramheap_free(p); + } + } +} diff --git a/arch/xtensa/src/esp32/esp32_tickless.c b/arch/xtensa/src/esp32/esp32_tickless.c new file mode 100644 index 00000000000..382c82c0d59 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_tickless.c @@ -0,0 +1,589 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_tickless.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Tickless OS Support. + * + * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts + * is suppressed and the platform specific code is expected to provide the + * following custom functions. + * + * void up_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_initialize()). + * int up_timer_gettime(FAR struct timespec *ts): Returns the current + * time from the platform specific time source. + * int up_timer_cancel(void): Cancels the interval timer. + * int up_timer_start(FAR const struct timespec *ts): Start (or re-starts) + * the interval timer. + * + * The RTOS will provide the following interfaces for use by the platform- + * specific interval timer implementation: + * + * void sched_timer_expiration(void): Called by the platform-specific + * logic when the interval timer expires. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "xtensa_timer.h" +#include "xtensa.h" +#include "xtensa_attr.h" +#include "xtensa_counter.h" + +#ifdef CONFIG_SCHED_TICKLESS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CTICK_PER_SEC (BOARD_CLOCK_FREQUENCY) +#define CTICK_PER_USEC (CTICK_PER_SEC / USEC_PER_SEC) + +#define SEC_2_CTICK(s) ((s) * CTICK_PER_SEC) +#define USEC_2_CTICK(us) ((us) * CTICK_PER_USEC) +#define NSEC_2_CTICK(nsec) (((nsec) * CTICK_PER_USEC) / NSEC_PER_USEC) + +#define CTICK_2_SEC(tick) ((tick) / CTICK_PER_SEC) +#define CTICK_2_USEC(tick) ((tick) / CTICK_PER_USEC) +#define CTICK_2_NSEC(tick) ((tick) * 1000 / CTICK_PER_USEC) + +#define CPU_TICKS_MAX (UINT32_MAX / 4 * 3) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint64_t up_tmr_total_count(void); +static inline uint64_t up_tmr_getcount(void); +static void IRAM_ATTR up_tmr_setcompare(uint32_t ticks); +static void IRAM_ATTR up_tmr_setcount(uint64_t ticks); +static int up_timer_expire(int irq, void *regs, FAR void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_timer_started; /* Whether an interval timer is being started */ +static uint64_t g_cticks; /* Total ticks of system since power-on */ +static uint32_t g_loop_cnt; /* System Cycle counter cycle times */ + +/* Redundant ticks of an interval timer on the cycle counter */ + +static uint32_t g_last_cticks; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_tmr_total_count + * + * Description: + * Return the total ticks of system since power-on. + * + * Input Parameters: + * None + * + * Returned Value: + * Total system ticks + * + ****************************************************************************/ + +static inline uint64_t up_tmr_total_count(void) +{ + return g_cticks + xtensa_getcount(); +} + +/**************************************************************************** + * Name: up_tmr_getcount + * + * Description: + * Return the remaining ticks in the currently running timer. + * + * Input Parameters: + * None + * + * Returned Value: + * Remaining ticks + * + ****************************************************************************/ + +static inline uint64_t up_tmr_getcount(void) +{ + return (uint64_t)g_loop_cnt * CPU_TICKS_MAX + + g_last_cticks; +} + +/**************************************************************************** + * Name: up_tmr_setcompare + * + * Description: + * Set the value of the compare register, save the currently running + * system tick and clear cycle count register. + * + * Input Parameters: + * ticks - Set the new value of the compare register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR up_tmr_setcompare(uint32_t ticks) +{ + xtensa_setcompare(ticks); + g_cticks += xtensa_getcount(); + xtensa_setcount(0); +} + +/**************************************************************************** + * Name: up_tmr_setcount + * + * Description: + * Set the value of the compare register + * + * Input Parameters: + * ticks - ticks for a timer operation + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR up_tmr_setcount(uint64_t ticks) +{ + irqstate_t flags; + uint32_t loop_cnt; + uint32_t last_ticks; + + if (ticks == 0) + { + ticks = 1; + } + + loop_cnt = ticks / CPU_TICKS_MAX; + last_ticks = ticks % CPU_TICKS_MAX; + + if (loop_cnt != 0) + { + xtensa_setcompare(CPU_TICKS_MAX); + } + else + { + xtensa_setcompare(last_ticks); + } + + flags = enter_critical_section(); + + g_loop_cnt = loop_cnt; + g_last_cticks = last_ticks; + g_timer_started = true; + + leave_critical_section(flags); + + g_cticks += xtensa_getcount(); + xtensa_setcount(0); +} + +/**************************************************************************** + * Name: up_timer_expire + * + * Description: + * Called as the IRQ handler for timer expiration. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int up_timer_expire(int irq, void *regs, FAR void *arg) +{ + irqstate_t flags; + bool do_sched = false; + + flags = enter_critical_section(); + + if (g_timer_started) + { + if (g_loop_cnt != 0) + { + --g_loop_cnt; + if (g_loop_cnt == 0) + { + if (g_last_cticks != 0) + { + up_tmr_setcompare(g_last_cticks); + } + else + { + do_sched = true; + up_tmr_setcompare(CPU_TICKS_MAX); + } + } + else + { + up_tmr_setcompare(CPU_TICKS_MAX); + } + } + else + { + do_sched = true; + } + + if (do_sched) + { + up_timer_cancel(NULL); + nxsched_timer_expiration(); + } + } + else + { + up_tmr_setcompare(CPU_TICKS_MAX); + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * up_timer_initialize() was called). This function is functionally + * equivalent to: + * + * int clock_gettime(clockid_t clockid, FAR struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int IRAM_ATTR up_timer_gettime(FAR struct timespec *ts) +{ + uint64_t ticks; + irqstate_t flags; + + flags = enter_critical_section(); + + ticks = up_tmr_total_count(); + ts->tv_sec = CTICK_2_SEC(ticks); + ts->tv_nsec = CTICK_2_NSEC(ticks % CTICK_PER_SEC); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: up_timer_cancel + * + * Description: + * Cancel the interval timer and return the time remaining on the timer. + * These two steps need to be as nearly atomic as possible. + * nxsched_timer_expiration() will not be called unless the timer is + * restarted with up_timer_start(). + * + * If, as a race condition, the timer has already expired when this + * function is called, then that pending interrupt must be cleared so + * that up_timer_start() and the remaining time of zero should be + * returned. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Location to return the remaining time. Zero should be returned + * if the timer is not active. ts may be zero in which case the + * time remaining is not returned. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int IRAM_ATTR up_timer_cancel(FAR struct timespec *ts) +{ + uint64_t rst_ticks; + uint64_t cur_ticks; + uint64_t ticks; + irqstate_t flags; + + flags = enter_critical_section(); + + if (ts != NULL) + { + if (!g_timer_started) + { + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + else + { + rst_ticks = up_tmr_getcount(); + cur_ticks = xtensa_getcount(); + if (rst_ticks <= cur_ticks) + { + ticks = 0; + } + else + { + ticks = rst_ticks - cur_ticks; + } + + ts->tv_sec = CTICK_2_SEC(ticks); + ts->tv_nsec = CTICK_2_NSEC(ticks % CTICK_PER_SEC); + } + } + + g_timer_started = false; + up_tmr_setcompare(CPU_TICKS_MAX); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: up_timer_start + * + * Description: + * Start the interval timer. nxsched_timer_expiration() will be + * called at the completion of the timeout (unless up_timer_cancel + * is called to stop the timing. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the time interval until nxsched_timer_expiration() is + * called. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int IRAM_ATTR up_timer_start(FAR const struct timespec *ts) +{ + uint64_t cpu_ticks; + irqstate_t flags; + + flags = enter_critical_section(); + + if (g_timer_started) + { + up_timer_cancel(NULL); + } + + cpu_ticks = SEC_2_CTICK((uint64_t)ts->tv_sec) + + NSEC_2_CTICK((uint64_t)ts->tv_nsec); + + up_tmr_setcount(cpu_ticks); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * Initializes all platform-specific timer facilities. This function is + * called early in the initialization sequence by up_initialize(). + * On return, the current up-time should be available from + * up_timer_gettime() and the interval timer is ready for use (but not + * actively timing. + * + * Provided by platform-specific code and called from the architecture- + * specific logic. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * Called early in the initialization sequence before any special + * concurrency protections are required. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + /* Set up periodic timer */ + + up_tmr_setcompare(CPU_TICKS_MAX); + + /* NOTE: Timer 0 is an internal interrupt source so we do not need to + * attach any peripheral ID to the dedicated CPU interrupt. + */ + + /* Attach the timer interrupt */ + + irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)up_timer_expire, NULL); + + /* Enable the timer 0 CPU interrupt. */ + + up_enable_irq(ESP32_CPUINT_TIMER0); + + return; +} + +/**************************************************************************** + * Name: up_get_idletime + * + * Description: + * This function returns the idle time. + * + * Input Parameters: + * None + * + * Returned Value: + * The time in system ticks remaining for idle. + * Zero means system is busy. + * + ****************************************************************************/ + +uint32_t IRAM_ATTR up_get_idletime(void) +{ + uint32_t us; + uint64_t ticks; + uint64_t rst_ticks; + irqstate_t flags; + + flags = enter_critical_section(); + + if (!g_timer_started) + { + us = 0; + } + else + { + ticks = xtensa_getcount(); + rst_ticks = up_tmr_getcount(); + if (rst_ticks > ticks) + { + us = CTICK_2_USEC(rst_ticks - ticks); + } + else + { + us = 0; + } + } + + leave_critical_section(flags); + + return us; +} + +/**************************************************************************** + * Name: up_step_idletime + * + * Description: + * Add system time by idletime_us. + * + * Input Parameters: + * us - Idle time(us) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR up_step_idletime(uint32_t us) +{ + uint64_t ticks; + uint64_t timer_ticks; + irqstate_t flags; + + DEBUGASSERT(g_timer_started); + + flags = enter_critical_section(); + + ticks = USEC_2_CTICK((uint64_t)us); + timer_ticks = up_tmr_getcount(); + + DEBUGASSERT(ticks < timer_ticks); + + g_cticks += ticks; + up_tmr_setcount(timer_ticks - ticks); + + leave_critical_section(flags); +} + +#endif /* CONFIG_SCHED_TICKLESS */ \ No newline at end of file diff --git a/arch/xtensa/src/esp32/esp32_tickless.h b/arch/xtensa/src/esp32/esp32_tickless.h new file mode 100644 index 00000000000..156761a1d94 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_tickless.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_tickless.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_TICKLESS_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_TICKLESS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_get_idletime + * + * Description: + * This function returns the idle time. + * + * Input Parameters: + * None + * + * Returned Value: + * The time in system ticks remaining for idle. + * Zero means system is busy. + * + ****************************************************************************/ + +uint32_t up_get_idletime(void); + +/**************************************************************************** + * Name: up_step_idletime + * + * Description: + * Add system time by idletime_us. + * + * Input Parameters: + * idletime_us - Idle time(us) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_step_idletime(uint32_t idletime_us); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_TICKLESS_H */ diff --git a/arch/xtensa/src/esp32/esp32_tim.c b/arch/xtensa/src/esp32/esp32_tim.c index 70fe03ccd0c..e62973d10b7 100644 --- a/arch/xtensa/src/esp32/esp32_tim.c +++ b/arch/xtensa/src/esp32/esp32_tim.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "xtensa.h" diff --git a/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c index 0f4a59e5d14..7483f66d0c1 100644 --- a/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c +++ b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index cb7b928e352..01e3fee7379 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -33,7 +33,7 @@ #include #include "clock/clock.h" -#include "xtensa_timer.h" +#include "xtensa_counter.h" #include "xtensa.h" /**************************************************************************** @@ -46,52 +46,6 @@ static uint32_t g_tick_divisor; * Private Functions ****************************************************************************/ -/**************************************************************************** - * Function: xtensa_getcount, xtensa_getcompare, and xtensa_setcompare - * - * Description: - * Lower level operations on Xtensa special registers. - * - ****************************************************************************/ - -/* Return the current value of the cycle count register */ - -static inline uint32_t xtensa_getcount(void) -{ - uint32_t count; - - __asm__ __volatile__ - ( - "rsr %0, CCOUNT" : "=r"(count) - ); - - return count; -} - -/* Return the old value of the compare register */ - -static inline uint32_t xtensa_getcompare(void) -{ - uint32_t compare; - - __asm__ __volatile__ - ( - "rsr %0, %1" : "=r"(compare) : "I"(XT_CCOMPARE) - ); - - return compare; -} - -/* Set the value of the compare register */ - -static inline void xtensa_setcompare(uint32_t compare) -{ - __asm__ __volatile__ - ( - "wsr %0, %1" : : "r"(compare), "I"(XT_CCOMPARE) - ); -} - /**************************************************************************** * Function: esp32_timerisr * diff --git a/arch/xtensa/src/esp32/esp32_user.c b/arch/xtensa/src/esp32/esp32_user.c index 8b683611167..95620a26d79 100644 --- a/arch/xtensa/src/esp32/esp32_user.c +++ b/arch/xtensa/src/esp32/esp32_user.c @@ -29,6 +29,7 @@ #include #include +#include #include #include "xtensa.h" @@ -37,9 +38,9 @@ * Public Data ****************************************************************************/ -#ifdef CONFIG_ARCH_USE_MODULE_TEXT -extern uint32_t _smodtext; -extern uint32_t _emodtext; +#ifdef CONFIG_ARCH_USE_TEXT_HEAP +extern uint32_t _siramheap; +extern uint32_t _eiramheap; #endif /**************************************************************************** @@ -50,7 +51,7 @@ extern uint32_t _emodtext; * Private Functions ****************************************************************************/ -#ifdef CONFIG_ARCH_USE_MODULE_TEXT +#ifdef CONFIG_ARCH_USE_TEXT_HEAP #ifdef CONFIG_ENDIAN_BIG #error not implemented #endif @@ -293,7 +294,7 @@ static void advance_pc(uint32_t *regs, int diff) /* Advance to the next instruction. */ nextpc = regs[REG_PC] + diff; -#ifdef XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_LOOPS != 0 /* See Xtensa ISA 4.3.2.4 Loopback Semantics */ if (regs[REG_LCOUNT] != 0 && nextpc == regs[REG_LEND]) @@ -322,7 +323,7 @@ static void advance_pc(uint32_t *regs, int diff) uint32_t *xtensa_user(int exccause, uint32_t *regs) { -#ifdef CONFIG_ARCH_USE_MODULE_TEXT +#ifdef CONFIG_ARCH_USE_TEXT_HEAP /* Emulate byte access for module text. * * ESP32 only allows word-aligned accesses to the instruction memory @@ -337,8 +338,8 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs) */ if (exccause == XCHAL_EXCCAUSE_LOAD_STORE_ERROR && - (uintptr_t)&_smodtext <= regs[REG_EXCVADDR] && - (uintptr_t)&_emodtext > regs[REG_EXCVADDR]) + (uintptr_t)&_siramheap <= regs[REG_EXCVADDR] && + (uintptr_t)&_eiramheap > regs[REG_EXCVADDR]) { uint8_t *pc = (uint8_t *)regs[REG_PC]; uint8_t imm8; diff --git a/arch/xtensa/src/esp32/esp32_wdt.c b/arch/xtensa/src/esp32/esp32_wdt.c index 8942cc28671..1fff28787f5 100644 --- a/arch/xtensa/src/esp32/esp32_wdt.c +++ b/arch/xtensa/src/esp32/esp32_wdt.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include "xtensa.h" #include "hardware/esp32_tim.h" #include "hardware/esp32_rtccntl.h" @@ -503,8 +505,8 @@ static int esp32_wdt_pre(FAR struct esp32_wdt_dev_s *dev, uint16_t pre) * Name: esp32_rtc_clk * * Description: - * Check the RTC clock source and return the necessary cycles to complete - * 1 ms. NOTE: TODO. + * Check the RTC clock source and return the necessary cycles to complete + * 1 ms. * ****************************************************************************/ @@ -526,6 +528,10 @@ static uint16_t esp32_rtc_clk(FAR struct esp32_wdt_dev_s *dev) period_13q19 = esp32_rtc_clk_cal(slow_clk_rtc, SLOW_CLK_CAL_CYCLES); + /* Assert no error happened during the calibration */ + + DEBUGASSERT(period_13q19 != 0); + /* Convert from Q13.19 format to float */ period = Q_TO_FLOAT(period_13q19); diff --git a/arch/xtensa/src/esp32/esp32_wdt_lowerhalf.c b/arch/xtensa/src/esp32/esp32_wdt_lowerhalf.c index c8027d4d24b..c92abe6fe39 100644 --- a/arch/xtensa/src/esp32/esp32_wdt_lowerhalf.c +++ b/arch/xtensa/src/esp32/esp32_wdt_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_wifi_adapter.c b/arch/xtensa/src/esp32/esp32_wifi_adapter.c index 7e1ccc87972..056afab9db0 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_adapter.c +++ b/arch/xtensa/src/esp32/esp32_wifi_adapter.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -60,6 +61,10 @@ #include "esp32_rt_timer.h" #include "esp32_wifi_utils.h" +#ifdef CONFIG_PM +#include "esp32_pm.h" +#endif + #include "espidf_wifi.h" /**************************************************************************** @@ -90,6 +95,24 @@ #define SSID_MAX_LEN (32) #define PWD_MAX_LEN (64) +#ifndef CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL +#define CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL 3 +#endif + +#define DEFAULT_LISTEN_INTERVAL CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL + +/* CONFIG_POWER_SAVE_MODEM */ + +#if defined(CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM) +# define DEFAULT_PS_MODE WIFI_PS_MIN_MODEM +#elif defined(CONFIG_EXAMPLE_POWER_SAVE_MAX_MODEM) +# define DEFAULT_PS_MODE WIFI_PS_MAX_MODEM +#elif defined(CONFIG_EXAMPLE_POWER_SAVE_NONE) +# define DEFAULT_PS_MODE WIFI_PS_NONE +#else +# define DEFAULT_PS_MODE WIFI_PS_NONE +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -2100,7 +2123,7 @@ static void esp_evt_work_cb(FAR void *arg) case WIFI_ADPT_EVT_STA_START: wlinfo("WiFi sta start\n"); g_sta_connected = false; - ret = esp_wifi_set_ps(WIFI_PS_NONE); + ret = esp_wifi_set_ps(DEFAULT_PS_MODE); if (ret) { wlerr("Failed to close PS\n"); @@ -2327,24 +2350,30 @@ static void esp_dport_access_stall_other_cpu_end(void) * Name: wifi_apb80m_request * * Description: - * Don't support + * Take Wi-Fi lock in auto-sleep * ****************************************************************************/ static void wifi_apb80m_request(void) { +#ifdef CONFIG_ESP32_AUTO_SLEEP + esp32_pm_lockacquire(); +#endif } /**************************************************************************** * Name: wifi_apb80m_release * * Description: - * Don't support + * Release Wi-Fi lock in auto-sleep * ****************************************************************************/ static void wifi_apb80m_release(void) { +#ifdef CONFIG_ESP32_AUTO_SLEEP + esp32_pm_lockrelease(); +#endif } /**************************************************************************** @@ -2584,12 +2613,12 @@ int32_t esp_read_mac(uint8_t *mac, esp_mac_type_t type) regval[1] = getreg32(MAC_ADDR1_REG); crc = data[6]; - for (i = 0; i < 6; i++) + for (i = 0; i < MAC_LEN; i++) { mac[i] = data[5 - i]; } - if (crc != esp_crc8(mac, 6)) + if (crc != esp_crc8(mac, MAC_LEN)) { wlerr("Failed to check MAC address CRC\n"); return -1; @@ -4863,13 +4892,6 @@ int esp_wifi_adapter_init(void) return OK; } - ret = esp32_rt_timer_init(); - if (ret < 0) - { - wlerr("Failed to initialize RT timer error=%d\n", ret); - goto errout_init_timer; - } - sq_init(&g_wifi_evt_queue); #ifdef CONFIG_ESP32_WIFI_SAVE_PARAM @@ -4928,9 +4950,8 @@ int esp_wifi_adapter_init(void) errout_init_txdone: esp_wifi_deinit(); errout_init_wifi: - esp32_rt_timer_deinit(); -errout_init_timer: esp_wifi_lock(false); + return ret; } @@ -5203,9 +5224,11 @@ int esp_wifi_sta_password(struct iwreq *iwr, bool set) if (set) { + memset(wifi_cfg.sta.password, 0x0, PWD_MAX_LEN); memcpy(wifi_cfg.sta.password, pdata, len); wifi_cfg.sta.pmf_cfg.capable = true; + wifi_cfg.sta.listen_interval = DEFAULT_LISTEN_INTERVAL; ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); if (ret) @@ -5326,6 +5349,7 @@ int esp_wifi_sta_essid(struct iwreq *iwr, bool set) if (set) { + memset(wifi_cfg.sta.ssid, 0x0, SSID_MAX_LEN); memcpy(wifi_cfg.sta.ssid, pdata, len); ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); @@ -5403,7 +5427,7 @@ int esp_wifi_sta_bssid(struct iwreq *iwr, bool set) if (set) { wifi_cfg.sta.bssid_set = true; - memcpy(wifi_cfg.sta.bssid, pdata, 6); + memcpy(wifi_cfg.sta.bssid, pdata, MAC_LEN); ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); if (ret) @@ -5414,7 +5438,7 @@ int esp_wifi_sta_bssid(struct iwreq *iwr, bool set) } else { - memcpy(pdata, wifi_cfg.sta.bssid, 6); + memcpy(pdata, wifi_cfg.sta.bssid, MAC_LEN); } return OK; @@ -5576,7 +5600,7 @@ int esp_wifi_sta_auth(struct iwreq *iwr, bool set) if (set) { - return -ENOSYS; + return OK; } else { @@ -6273,6 +6297,7 @@ int esp_wifi_softap_password(struct iwreq *iwr, bool set) if (set) { + memset(wifi_cfg.ap.password, 0x0, PWD_MAX_LEN); memcpy(wifi_cfg.ap.password, pdata, len); ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); @@ -6352,6 +6377,7 @@ int esp_wifi_softap_essid(struct iwreq *iwr, bool set) if (set) { + memset(wifi_cfg.ap.ssid, 0x0, SSID_MAX_LEN); memcpy(wifi_cfg.ap.ssid, pdata, len); ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); diff --git a/arch/xtensa/src/esp32/esp32_wifi_adapter.h b/arch/xtensa/src/esp32/esp32_wifi_adapter.h index ac298d2cde0..f25ad053a81 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_adapter.h +++ b/arch/xtensa/src/esp32/esp32_wifi_adapter.h @@ -60,6 +60,8 @@ extern "C" # define ESP32_WLAN_DEVS 2 #endif +#define MAC_LEN (6) + /* WiFi event ID */ enum wifi_adpt_evt_e diff --git a/arch/xtensa/src/esp32/esp32_wifi_utils.c b/arch/xtensa/src/esp32/esp32_wifi_utils.c index 62ce65b90f8..15ad8083206 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_utils.c +++ b/arch/xtensa/src/esp32/esp32_wifi_utils.c @@ -24,6 +24,9 @@ #include +#include +#include + #include #include #include @@ -54,6 +57,10 @@ # define MIN(a,b) ((a) < (b) ? (a) : (b)) #endif +/* Maximum number of channels for Wi-Fi 2.4Ghz */ + +#define CHANNEL_MAX_NUM (14) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -80,6 +87,8 @@ struct wifi_scan_result ****************************************************************************/ static struct wifi_scan_result g_scan_priv; +static uint8_t g_channel_num = 0; +static uint8_t g_channel_list[CHANNEL_MAX_NUM]; /**************************************************************************** * Public Functions @@ -107,6 +116,8 @@ int esp_wifi_start_scan(struct iwreq *iwr) uint8_t target_ssid[SSID_LEN]; struct iw_scan_req *req; int ret = 0; + int i; + uint8_t target_mac[MAC_LEN]; memset(target_ssid, 0x0, sizeof(SSID_LEN)); if (iwr == NULL) @@ -127,6 +138,8 @@ int esp_wifi_start_scan(struct iwreq *iwr) return -ENOMEM; } + g_channel_num = 0; + memset(g_channel_list, 0x0, CHANNEL_MAX_NUM); memset(config, 0x0, sizeof(wifi_scan_config_t)); if (iwr->u.data.pointer && iwr->u.data.length >= sizeof(struct iw_scan_req)) @@ -143,6 +156,35 @@ int esp_wifi_start_scan(struct iwreq *iwr) config->ssid = &target_ssid[0]; config->ssid[req->essid_len] = '\0'; } + + if (iwr->u.data.flags & IW_SCAN_THIS_FREQ && + req->num_channels > 0) + { + /* Scan specific channels */ + + DEBUGASSERT(req->num_channels <= CHANNEL_MAX_NUM); + g_channel_num = req->num_channels; + if (req->num_channels == 1) + { + config->channel = req->channel_list[0].m; + } + else + { + for (i = 0; i < req->num_channels; i++) + { + g_channel_list[i] = req->channel_list[i].m; + } + } + } + + memset(target_mac, 0xff, MAC_LEN); + if (memcmp(req->bssid.sa_data, target_mac, MAC_LEN) != 0) + { + /* Scan specific bssid */ + + memcpy(target_mac, req->bssid.sa_data, MAC_LEN); + config->bssid = &target_mac[0]; + } } else { @@ -315,6 +357,7 @@ void esp_wifi_scan_event_parse(void) esp_wifi_scan_get_ap_num(&bss_total); if (bss_total == 0) { + priv->scan_status = ESP_SCAN_DONE; wlinfo("INFO: None AP is scanned\n"); return; } @@ -322,6 +365,7 @@ void esp_wifi_scan_event_parse(void) ap_list_buffer = kmm_malloc(bss_total * sizeof(wifi_ap_record_t)); if (ap_list_buffer == NULL) { + priv->scan_status = ESP_SCAN_DONE; wlerr("ERROR: Failed to malloc buffer to print scan results"); return; } @@ -334,123 +378,148 @@ void esp_wifi_scan_event_parse(void) unsigned int result_size; size_t essid_len; size_t essid_len_aligned; + bool is_target_channel = true; + int i; for (bss_count = 0; bss_count < bss_total; bss_count++) { - result_size = WIFI_SCAN_RESULT_SIZE - priv->scan_result_size; - - /* Copy BSSID */ - - if (result_size < ESP_IW_EVENT_SIZE(ap_addr)) + if (g_channel_num > 1) { - goto scan_result_full; + is_target_channel = false; + for (i = 0; i < g_channel_num; i++) + { + if (g_channel_list[i] == ap_list_buffer[bss_count].primary) + { + is_target_channel = true; + break; + } + } + } + else + { + is_target_channel = true; } - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(ap_addr); - iwe->cmd = SIOCGIWAP; - memcpy(&iwe->u.ap_addr.sa_data, ap_list_buffer[bss_count].bssid, - sizeof(ap_list_buffer[bss_count].bssid)); - iwe->u.ap_addr.sa_family = ARPHRD_ETHER; - priv->scan_result_size += ESP_IW_EVENT_SIZE(ap_addr); - result_size -= ESP_IW_EVENT_SIZE(ap_addr); - - /* Copy ESSID */ - - essid_len = MIN(strlen((const char *) - ap_list_buffer[bss_count].ssid), 32); - essid_len_aligned = (essid_len + 3) & -4; - if (result_size < ESP_IW_EVENT_SIZE(essid)+essid_len_aligned) + if (is_target_channel == true) { - goto scan_result_full; + result_size = WIFI_SCAN_RESULT_SIZE - priv->scan_result_size; + + /* Copy BSSID */ + + if (result_size < ESP_IW_EVENT_SIZE(ap_addr)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(ap_addr); + iwe->cmd = SIOCGIWAP; + memcpy(&iwe->u.ap_addr.sa_data, + ap_list_buffer[bss_count].bssid, + sizeof(ap_list_buffer[bss_count].bssid)); + iwe->u.ap_addr.sa_family = ARPHRD_ETHER; + priv->scan_result_size += ESP_IW_EVENT_SIZE(ap_addr); + result_size -= ESP_IW_EVENT_SIZE(ap_addr); + + /* Copy ESSID */ + + essid_len = MIN(strlen((const char *) + ap_list_buffer[bss_count].ssid), 32); + essid_len_aligned = (essid_len + 3) & -4; + if (result_size < ESP_IW_EVENT_SIZE(essid)+essid_len_aligned) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; + iwe->cmd = SIOCGIWESSID; + iwe->u.essid.flags = 0; + iwe->u.essid.length = essid_len; + + /* Special processing for iw_point, set offset + * in pointer field. + */ + + iwe->u.essid.pointer = (FAR void *)sizeof(iwe->u.essid); + memcpy(&iwe->u.essid + 1, + ap_list_buffer[bss_count].ssid, essid_len); + wlinfo("INFO: ssid %s\n", ap_list_buffer[bss_count].ssid); + priv->scan_result_size += + ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; + result_size -= ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; + + /* Copy link quality info */ + + if (result_size < ESP_IW_EVENT_SIZE(qual)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(qual); + iwe->cmd = IWEVQUAL; + iwe->u.qual.qual = 0x00; + wlinfo("INFO: signal %d\n", ap_list_buffer[bss_count].rssi); + iwe->u.qual.level = ap_list_buffer[bss_count].rssi; + iwe->u.qual.noise = 0x00; + iwe->u.qual.updated = IW_QUAL_DBM | IW_QUAL_ALL_UPDATED; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(qual); + result_size -= ESP_IW_EVENT_SIZE(qual); + + /* Copy AP mode */ + + if (result_size < ESP_IW_EVENT_SIZE(mode)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(mode); + iwe->cmd = SIOCGIWMODE; + iwe->u.mode = IW_MODE_MASTER; + priv->scan_result_size += ESP_IW_EVENT_SIZE(mode); + result_size -= ESP_IW_EVENT_SIZE(mode); + + /* Copy AP encryption mode */ + + if (result_size < ESP_IW_EVENT_SIZE(data)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(data); + iwe->cmd = SIOCGIWENCODE; + iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + iwe->u.data.length = 0; + iwe->u.essid.pointer = NULL; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(data); + result_size -= ESP_IW_EVENT_SIZE(data); + + /* Copy AP channel */ + + if (result_size < ESP_IW_EVENT_SIZE(freq)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(freq); + iwe->cmd = SIOCGIWFREQ; + iwe->u.freq.e = 0; + iwe->u.freq.m = ap_list_buffer[bss_count].primary; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(freq); + result_size -= ESP_IW_EVENT_SIZE(freq); } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; - iwe->cmd = SIOCGIWESSID; - iwe->u.essid.flags = 0; - iwe->u.essid.length = essid_len; - - /* Special processing for iw_point, set offset in pointer field */ - - iwe->u.essid.pointer = (FAR void *)sizeof(iwe->u.essid); - memcpy(&iwe->u.essid + 1, - ap_list_buffer[bss_count].ssid, essid_len); - wlinfo("INFO: ssid %s\n", ap_list_buffer[bss_count].ssid); - priv->scan_result_size += - ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; - result_size -= ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; - - /* Copy link quality info */ - - if (result_size < ESP_IW_EVENT_SIZE(qual)) - { - goto scan_result_full; - } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(qual); - iwe->cmd = IWEVQUAL; - iwe->u.qual.qual = 0x00; - wlinfo("INFO: signal %d\n", ap_list_buffer[bss_count].rssi); - iwe->u.qual.level = ap_list_buffer[bss_count].rssi; - iwe->u.qual.noise = 0x00; - iwe->u.qual.updated = IW_QUAL_DBM | IW_QUAL_ALL_UPDATED; - - priv->scan_result_size += ESP_IW_EVENT_SIZE(qual); - result_size -= ESP_IW_EVENT_SIZE(qual); - - /* Copy AP mode */ - - if (result_size < ESP_IW_EVENT_SIZE(mode)) - { - goto scan_result_full; - } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(mode); - iwe->cmd = SIOCGIWMODE; - iwe->u.mode = IW_MODE_MASTER; - priv->scan_result_size += ESP_IW_EVENT_SIZE(mode); - result_size -= ESP_IW_EVENT_SIZE(mode); - - /* Copy AP encryption mode */ - - if (result_size < ESP_IW_EVENT_SIZE(data)) - { - goto scan_result_full; - } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(data); - iwe->cmd = SIOCGIWENCODE; - iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; - iwe->u.data.length = 0; - iwe->u.essid.pointer = NULL; - - priv->scan_result_size += ESP_IW_EVENT_SIZE(data); - result_size -= ESP_IW_EVENT_SIZE(data); - - /* Copy AP channel */ - - if (result_size < ESP_IW_EVENT_SIZE(freq)) - { - goto scan_result_full; - } - - iwe = (struct iw_event *) - &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(freq); - iwe->cmd = SIOCGIWFREQ; - iwe->u.freq.e = 0; - iwe->u.freq.m = ap_list_buffer[bss_count].primary; - - priv->scan_result_size += ESP_IW_EVENT_SIZE(freq); - result_size -= ESP_IW_EVENT_SIZE(freq); } parse_done = true; @@ -471,7 +540,7 @@ scan_result_full: ap_list_buffer = NULL; } - g_scan_priv.scan_status = ESP_SCAN_DONE; + priv->scan_status = ESP_SCAN_DONE; nxsem_post(&priv->scan_signal); } diff --git a/arch/xtensa/src/esp32/esp32_wlan.c b/arch/xtensa/src/esp32/esp32_wlan.c index 705edf9cdff..8f00a81fd56 100644 --- a/arch/xtensa/src/esp32/esp32_wlan.c +++ b/arch/xtensa/src/esp32/esp32_wlan.c @@ -27,6 +27,7 @@ #ifdef CONFIG_ESP32_WIRELESS #include +#include #include #include #include diff --git a/arch/xtensa/src/esp32/hardware/esp32_dport.h b/arch/xtensa/src/esp32/hardware/esp32_dport.h index 16fbb0445fe..de9e1609afd 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_dport.h +++ b/arch/xtensa/src/esp32/hardware/esp32_dport.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32_soc.h" +#include "esp32_soc.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32/hardware/esp32_gpio.h b/arch/xtensa/src/esp32/hardware/esp32_gpio.h index bbb65a3eaa8..f86e4c150cf 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_gpio.h +++ b/arch/xtensa/src/esp32/hardware/esp32_gpio.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32_soc.h" +#include "esp32_soc.h" /**************************************************************************** * Pre-preprocessor Definitions diff --git a/arch/xtensa/src/esp32/hardware/esp32_iomux.h b/arch/xtensa/src/esp32/hardware/esp32_iomux.h index 6587514efb8..faffffa13bd 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_iomux.h +++ b/arch/xtensa/src/esp32/hardware/esp32_iomux.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32_soc.h" +#include "esp32_soc.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h index c5368d4ec1e..e661726e12a 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h +++ b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32_soc.h" +#include "esp32_soc.h" /**************************************************************************** * Pre-processor Definitions @@ -47,6 +47,12 @@ #define RWDT_INT_ENA_REG_OFFSET 0x003c #define RWDT_INT_CLR_REG_OFFSET 0x0048 +/* The value that needs to be written to RTC_CNTL_WDT_WKEY to + * write-enable the wdt registers + */ + +#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1 + /* CLK */ #define CK_XTAL_32K_MASK (BIT(30)) #define CK8M_D256_OUT_MASK (BIT(31)) diff --git a/arch/xtensa/src/esp32/hardware/esp32_soc.h b/arch/xtensa/src/esp32/hardware/esp32_soc.h index f208741b619..68e5c6229a7 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_soc.h +++ b/arch/xtensa/src/esp32/hardware/esp32_soc.h @@ -183,6 +183,14 @@ #define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) +/* Extract the field from the register and shift it to avoid wrong reading */ + +#define REG_MASK(_reg, _field) (((_reg) & (_field##_M)) >> (_field##_S)) + +/* Helper to place a value in a field */ + +#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M)) + /* Periheral Clock */ #define APB_CLK_FREQ_ROM 26 * 1000000 @@ -244,6 +252,15 @@ #define DR_REG_PWM3_BASE 0x3ff70000 #define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE +/* Some AHB addresses can be used instead of DPORT addresses + * as a workaround for some HW bugs. + * This workaround is detailed at + * https://www.espressif.com/sites/default/files/documentation/ + * eco_and_workarounds_for_bugs_in_esp32_en.pdf + */ + +#define AHB_REG_UART_BASE 0x60000000 + /* Overall memory map */ #define SOC_DROM_LOW 0x3f400000 @@ -264,8 +281,8 @@ #define SOC_RTC_IRAM_HIGH 0x400c2000 #define SOC_RTC_DRAM_LOW 0x3ff80000 #define SOC_RTC_DRAM_HIGH 0x3ff82000 -#define SOC_RTC_DATA_LOW 0x50000000 -#define SOC_RTC_DATA_HIGH 0x50002000 +#define SOC_RTC_SLOW_LOW 0x50000000 +#define SOC_RTC_SLOW_HIGH 0x50002000 #define SOC_EXTRAM_DATA_LOW 0x3f800000 #define SOC_EXTRAM_DATA_HIGH 0x3fc00000 @@ -838,4 +855,21 @@ static inline bool IRAM_ATTR esp32_ptr_exec(const void *p) || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH); } +/**************************************************************************** + * Name: esp32_ptr_rtcslow + * + * Description: + * Check if the buffer comes from the RTC Slow RAM. + * + * Parameters: + * p - Pointer to the buffer. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32_ptr_rtcslow(const void *p) +{ + return ((intptr_t)p >= SOC_RTC_SLOW_LOW && + (intptr_t)p < SOC_RTC_SLOW_HIGH); +} + #endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_tim.h b/arch/xtensa/src/esp32/hardware/esp32_tim.h index 4f8b0fc75cf..dca6de9c02c 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_tim.h +++ b/arch/xtensa/src/esp32/hardware/esp32_tim.h @@ -25,8 +25,7 @@ * Included Files ************************************************************************************/ -#include -#include "hardware/esp32_soc.h" +#include "esp32_soc.h" /* Offsets relative to each timer instance memory base */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_uart.h b/arch/xtensa/src/esp32/hardware/esp32_uart.h index ba14d1bcf92..cba15cb71be 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_uart.h +++ b/arch/xtensa/src/esp32/hardware/esp32_uart.h @@ -25,16 +25,18 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32_soc.h" +#include "esp32_soc.h" /**************************************************************************** * Pre-processor Macros ****************************************************************************/ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 + (i > 1 ? 0xe000 : 0)) +#define AHB_FIFO_BASE(i) (AHB_REG_UART_BASE + (i) * 0x10000 + (i > 1 ? 0xe000 : 0)) #define UART_FIFO_OFFSET 0x00 -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + UART_FIFO_OFFSET) +#define AHB_UART_FIFO_REG(i) (AHB_FIFO_BASE(i) + UART_FIFO_OFFSET) +#define DR_UART_FIFO_REG(i) (REG_UART_BASE(i) + UART_FIFO_OFFSET) /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ @@ -1798,6 +1800,24 @@ #define UART_MEM_RX_STATUS_V 0xFFFFFF #define UART_MEM_RX_STATUS_S 0 +/* UART_RD_ADDRESS : bitpos:[12:2] */ + +/* Description: Read address of the UART RX FIFO. (a pointer) */ + +#define UART_RD_ADDRESS 0x000007FF +#define UART_RD_ADDRESS_M ((UART_RD_ADDRESS_V) << (UART_RD_ADDRESS_S)) +#define UART_RD_ADDRESS_V 0x7FF +#define UART_RD_ADDRESS_S 2 + +/* UART_WR_ADDRESS : bitpos:[23:13] */ + +/* Description: Write address of the UART RX FIFO. (a pointer) */ + +#define UART_WR_ADDRESS 0x000007FF +#define UART_WR_ADDRESS_M ((UART_WR_ADDRESS_V) << (UART_WR_ADDRESS_S)) +#define UART_WR_ADDRESS_V 0x7FF +#define UART_WR_ADDRESS_S 13 + #define UART_MEM_CNT_STATUS_OFFSET 0x64 #define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + UART_MEM_CNT_STATUS_OFFSET) diff --git a/arch/xtensa/src/esp32/hardware/esp32_uhci.h b/arch/xtensa/src/esp32/hardware/esp32_uhci.h new file mode 100644 index 00000000000..d187f473271 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_uhci.h @@ -0,0 +1,1825 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/hardware/esp32_uhci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_UHCI_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_UHCI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) + +/* UHCI_CONF0_REG register */ + +#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) + +/* UHCI_UART_RX_BRK_EOF_EN : RW; bitpos: [23]; default: 0; + * Set this bit to enable to use brk char as the end of a data frame. + */ + +#define UHCI_UART_RX_BRK_EOF_EN (BIT(23)) +#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001 +#define UHCI_UART_RX_BRK_EOF_EN_S 23 + +/* UHCI_CLK_EN : RW; bitpos: [22]; default: 0; + * Set this bit to enable clock-gating for read or write registers. + */ + +#define UHCI_CLK_EN (BIT(22)) +#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S) +#define UHCI_CLK_EN_V 0x00000001 +#define UHCI_CLK_EN_S 22 + +/* UHCI_ENCODE_CRC_EN : RW; bitpos: [21]; default: 1; + * Set this bit to enable crc calculation for data frame when bit6 in the + * head packet is 1. + */ + +#define UHCI_ENCODE_CRC_EN (BIT(21)) +#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S) +#define UHCI_ENCODE_CRC_EN_V 0x00000001 +#define UHCI_ENCODE_CRC_EN_S 21 + +/* UHCI_LEN_EOF_EN : RW; bitpos: [20]; default: 1; + * Set this bit to enable to use packet_len in packet head when the + * received data is equal to packet_len this means the end of a data frame. + */ + +#define UHCI_LEN_EOF_EN (BIT(20)) +#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S) +#define UHCI_LEN_EOF_EN_V 0x00000001 +#define UHCI_LEN_EOF_EN_S 20 + +/* UHCI_UART_IDLE_EOF_EN : RW; bitpos: [19]; default: 0; + * Set this bit to enable to use idle time when the idle time after data + * frame is satisfied this means the end of a data frame. + */ + +#define UHCI_UART_IDLE_EOF_EN (BIT(19)) +#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S) +#define UHCI_UART_IDLE_EOF_EN_V 0x00000001 +#define UHCI_UART_IDLE_EOF_EN_S 19 + +/* UHCI_CRC_REC_EN : RW; bitpos: [18]; default: 1; + * Set this bit to enable receiver''s ability of crc calculation when + * crc_en bit in head packet is 1 then there will be crc bytes after + * data_frame + */ + +#define UHCI_CRC_REC_EN (BIT(18)) +#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S) +#define UHCI_CRC_REC_EN_V 0x00000001 +#define UHCI_CRC_REC_EN_S 18 + +/* UHCI_HEAD_EN : RW; bitpos: [17]; default: 1; + * Set this bit to enable to use head packet before the data frame. + */ + +#define UHCI_HEAD_EN (BIT(17)) +#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S) +#define UHCI_HEAD_EN_V 0x00000001 +#define UHCI_HEAD_EN_S 17 + +/* UHCI_SEPER_EN : RW; bitpos: [16]; default: 1; + * Set this bit to use special char to separate the data frame. + */ + +#define UHCI_SEPER_EN (BIT(16)) +#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S) +#define UHCI_SEPER_EN_V 0x00000001 +#define UHCI_SEPER_EN_S 16 + +/* UHCI_MEM_TRANS_EN : RW; bitpos: [15]; default: 0; */ + +#define UHCI_MEM_TRANS_EN (BIT(15)) +#define UHCI_MEM_TRANS_EN_M (UHCI_MEM_TRANS_EN_V << UHCI_MEM_TRANS_EN_S) +#define UHCI_MEM_TRANS_EN_V 0x00000001 +#define UHCI_MEM_TRANS_EN_S 15 + +/* UHCI_OUT_DATA_BURST_EN : RW; bitpos: [14]; default: 0; + * Set this bit to enable DMA burst MODE + */ + +#define UHCI_OUT_DATA_BURST_EN (BIT(14)) +#define UHCI_OUT_DATA_BURST_EN_M (UHCI_OUT_DATA_BURST_EN_V << UHCI_OUT_DATA_BURST_EN_S) +#define UHCI_OUT_DATA_BURST_EN_V 0x00000001 +#define UHCI_OUT_DATA_BURST_EN_S 14 + +/* UHCI_INDSCR_BURST_EN : RW; bitpos: [13]; default: 0; + * Set this bit to enable DMA out links to use burst mode. + */ + +#define UHCI_INDSCR_BURST_EN (BIT(13)) +#define UHCI_INDSCR_BURST_EN_M (UHCI_INDSCR_BURST_EN_V << UHCI_INDSCR_BURST_EN_S) +#define UHCI_INDSCR_BURST_EN_V 0x00000001 +#define UHCI_INDSCR_BURST_EN_S 13 + +/* UHCI_OUTDSCR_BURST_EN : RW; bitpos: [12]; default: 0; + * Set this bit to enable DMA in links to use burst mode. + */ + +#define UHCI_OUTDSCR_BURST_EN (BIT(12)) +#define UHCI_OUTDSCR_BURST_EN_M (UHCI_OUTDSCR_BURST_EN_V << UHCI_OUTDSCR_BURST_EN_S) +#define UHCI_OUTDSCR_BURST_EN_V 0x00000001 +#define UHCI_OUTDSCR_BURST_EN_S 12 + +/* UHCI_UART2_CE : RW; bitpos: [11]; default: 0; + * Set this bit to use UART2 to transmit or receive data. + */ + +#define UHCI_UART2_CE (BIT(11)) +#define UHCI_UART2_CE_M (UHCI_UART2_CE_V << UHCI_UART2_CE_S) +#define UHCI_UART2_CE_V 0x00000001 +#define UHCI_UART2_CE_S 11 + +/* UHCI_UART1_CE : RW; bitpos: [10]; default: 0; + * Set this bit to use UART1 to transmit or receive data. + */ + +#define UHCI_UART1_CE (BIT(10)) +#define UHCI_UART1_CE_M (UHCI_UART1_CE_V << UHCI_UART1_CE_S) +#define UHCI_UART1_CE_V 0x00000001 +#define UHCI_UART1_CE_S 10 + +/* UHCI_UART0_CE : RW; bitpos: [9]; default: 0; + * Set this bit to use UART to transmit or receive data. + */ + +#define UHCI_UART0_CE (BIT(9)) +#define UHCI_UART0_CE_M (UHCI_UART0_CE_V << UHCI_UART0_CE_S) +#define UHCI_UART0_CE_V 0x00000001 +#define UHCI_UART0_CE_S 9 + +/* UHCI_OUT_EOF_MODE : RW; bitpos: [8]; default: 1; + * Set this bit to produce eof after DMA pops all data clear this bit to + * produce eof after DMA pushes all data + */ + +#define UHCI_OUT_EOF_MODE (BIT(8)) +#define UHCI_OUT_EOF_MODE_M (UHCI_OUT_EOF_MODE_V << UHCI_OUT_EOF_MODE_S) +#define UHCI_OUT_EOF_MODE_V 0x00000001 +#define UHCI_OUT_EOF_MODE_S 8 + +/* UHCI_OUT_NO_RESTART_CLR : RW; bitpos: [7]; default: 0; + * don't use + */ + +#define UHCI_OUT_NO_RESTART_CLR (BIT(7)) +#define UHCI_OUT_NO_RESTART_CLR_M (UHCI_OUT_NO_RESTART_CLR_V << UHCI_OUT_NO_RESTART_CLR_S) +#define UHCI_OUT_NO_RESTART_CLR_V 0x00000001 +#define UHCI_OUT_NO_RESTART_CLR_S 7 + +/* UHCI_OUT_AUTO_WRBACK : RW; bitpos: [6]; default: 0; + * when in link's length is 0 go on to use the next in link automatically. + */ + +#define UHCI_OUT_AUTO_WRBACK (BIT(6)) +#define UHCI_OUT_AUTO_WRBACK_M (UHCI_OUT_AUTO_WRBACK_V << UHCI_OUT_AUTO_WRBACK_S) +#define UHCI_OUT_AUTO_WRBACK_V 0x00000001 +#define UHCI_OUT_AUTO_WRBACK_S 6 + +/* UHCI_OUT_LOOP_TEST : RW; bitpos: [5]; default: 0; + * Set this bit to enable loop test for out links. + */ + +#define UHCI_OUT_LOOP_TEST (BIT(5)) +#define UHCI_OUT_LOOP_TEST_M (UHCI_OUT_LOOP_TEST_V << UHCI_OUT_LOOP_TEST_S) +#define UHCI_OUT_LOOP_TEST_V 0x00000001 +#define UHCI_OUT_LOOP_TEST_S 5 + +/* UHCI_IN_LOOP_TEST : RW; bitpos: [4]; default: 0; + * Set this bit to enable loop test for in links. + */ + +#define UHCI_IN_LOOP_TEST (BIT(4)) +#define UHCI_IN_LOOP_TEST_M (UHCI_IN_LOOP_TEST_V << UHCI_IN_LOOP_TEST_S) +#define UHCI_IN_LOOP_TEST_V 0x00000001 +#define UHCI_IN_LOOP_TEST_S 4 + +/* UHCI_AHBM_RST : RW; bitpos: [3]; default: 0; + * Set this bit to reset dma ahb interface. + */ + +#define UHCI_AHBM_RST (BIT(3)) +#define UHCI_AHBM_RST_M (UHCI_AHBM_RST_V << UHCI_AHBM_RST_S) +#define UHCI_AHBM_RST_V 0x00000001 +#define UHCI_AHBM_RST_S 3 + +/* UHCI_AHBM_FIFO_RST : RW; bitpos: [2]; default: 0; + * Set this bit to reset dma ahb fifo. + */ + +#define UHCI_AHBM_FIFO_RST (BIT(2)) +#define UHCI_AHBM_FIFO_RST_M (UHCI_AHBM_FIFO_RST_V << UHCI_AHBM_FIFO_RST_S) +#define UHCI_AHBM_FIFO_RST_V 0x00000001 +#define UHCI_AHBM_FIFO_RST_S 2 + +/* UHCI_OUT_RST : RW; bitpos: [1]; default: 0; + * Set this bit to reset out link operations. + */ + +#define UHCI_OUT_RST (BIT(1)) +#define UHCI_OUT_RST_M (UHCI_OUT_RST_V << UHCI_OUT_RST_S) +#define UHCI_OUT_RST_V 0x00000001 +#define UHCI_OUT_RST_S 1 + +/* UHCI_IN_RST : RW; bitpos: [0]; default: 0; + * Set this bit to reset in link operations. + */ + +#define UHCI_IN_RST (BIT(0)) +#define UHCI_IN_RST_M (UHCI_IN_RST_V << UHCI_IN_RST_S) +#define UHCI_IN_RST_V 0x00000001 +#define UHCI_IN_RST_S 0 + +/* UHCI_INT_RAW_REG register */ + +#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) + +/* UHCI_DMA_INFIFO_FULL_WM_INT_RAW : R; bitpos: [16]; default: 0; */ + +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_M (UHCI_DMA_INFIFO_FULL_WM_INT_RAW_V << UHCI_DMA_INFIFO_FULL_WM_INT_RAW_S) +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_V 0x00000001 +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_S 16 + +/* UHCI_SEND_A_Q_INT_RAW : R; bitpos: [15]; default: 0; + * When use always_send registers to send a series of short packets it will + * produce this interrupt when dma has send the short packet. + */ + +#define UHCI_SEND_A_Q_INT_RAW (BIT(15)) +#define UHCI_SEND_A_Q_INT_RAW_M (UHCI_SEND_A_Q_INT_RAW_V << UHCI_SEND_A_Q_INT_RAW_S) +#define UHCI_SEND_A_Q_INT_RAW_V 0x00000001 +#define UHCI_SEND_A_Q_INT_RAW_S 15 + +/* UHCI_SEND_S_Q_INT_RAW : R; bitpos: [14]; default: 0; + * When use single send registers to send a short packets it will produce + * this interrupt when dma has send the short packet. + */ + +#define UHCI_SEND_S_Q_INT_RAW (BIT(14)) +#define UHCI_SEND_S_Q_INT_RAW_M (UHCI_SEND_S_Q_INT_RAW_V << UHCI_SEND_S_Q_INT_RAW_S) +#define UHCI_SEND_S_Q_INT_RAW_V 0x00000001 +#define UHCI_SEND_S_Q_INT_RAW_S 14 + +/* UHCI_OUT_TOTAL_EOF_INT_RAW : R; bitpos: [13]; default: 0; + * When all data have been send it will produce uhci_out_total_eof_int + * interrupt. + */ + +#define UHCI_OUT_TOTAL_EOF_INT_RAW (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_RAW_M (UHCI_OUT_TOTAL_EOF_INT_RAW_V << UHCI_OUT_TOTAL_EOF_INT_RAW_S) +#define UHCI_OUT_TOTAL_EOF_INT_RAW_V 0x00000001 +#define UHCI_OUT_TOTAL_EOF_INT_RAW_S 13 + +/* UHCI_OUTLINK_EOF_ERR_INT_RAW : R; bitpos: [12]; default: 0; + * when there are some errors about eof in outlink descriptor it will + * produce uhci_outlink_eof_err_int interrupt. + */ + +#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (UHCI_OUTLINK_EOF_ERR_INT_RAW_V << UHCI_OUTLINK_EOF_ERR_INT_RAW_S) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x00000001 +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 12 + +/* UHCI_IN_DSCR_EMPTY_INT_RAW : R; bitpos: [11]; default: 0; + * when there are not enough in links for DMA it will produce + * uhci_in_dscr_err_int interrupt. + */ + +#define UHCI_IN_DSCR_EMPTY_INT_RAW (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_RAW_M (UHCI_IN_DSCR_EMPTY_INT_RAW_V << UHCI_IN_DSCR_EMPTY_INT_RAW_S) +#define UHCI_IN_DSCR_EMPTY_INT_RAW_V 0x00000001 +#define UHCI_IN_DSCR_EMPTY_INT_RAW_S 11 + +/* UHCI_OUT_DSCR_ERR_INT_RAW : R; bitpos: [10]; default: 0; + * when there are some errors about the in link descriptor it will produce + * uhci_out_dscr_err_int interrupt. + */ + +#define UHCI_OUT_DSCR_ERR_INT_RAW (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_RAW_M (UHCI_OUT_DSCR_ERR_INT_RAW_V << UHCI_OUT_DSCR_ERR_INT_RAW_S) +#define UHCI_OUT_DSCR_ERR_INT_RAW_V 0x00000001 +#define UHCI_OUT_DSCR_ERR_INT_RAW_S 10 + +/* UHCI_IN_DSCR_ERR_INT_RAW : R; bitpos: [9]; default: 0; + * when there are some errors about the out link descriptor it will produce + * uhci_in_dscr_err_int interrupt. + */ + +#define UHCI_IN_DSCR_ERR_INT_RAW (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_RAW_M (UHCI_IN_DSCR_ERR_INT_RAW_V << UHCI_IN_DSCR_ERR_INT_RAW_S) +#define UHCI_IN_DSCR_ERR_INT_RAW_V 0x00000001 +#define UHCI_IN_DSCR_ERR_INT_RAW_S 9 + +/* UHCI_OUT_EOF_INT_RAW : R; bitpos: [8]; default: 0; + * when the current descriptor's eof bit is 1 it will produce + * uhci_out_eof_int interrupt. + */ + +#define UHCI_OUT_EOF_INT_RAW (BIT(8)) +#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S) +#define UHCI_OUT_EOF_INT_RAW_V 0x00000001 +#define UHCI_OUT_EOF_INT_RAW_S 8 + +/* UHCI_OUT_DONE_INT_RAW : R; bitpos: [7]; default: 0; + * when a out link descriptor is completed it will produce + * uhci_out_done_int interrupt. + */ + +#define UHCI_OUT_DONE_INT_RAW (BIT(7)) +#define UHCI_OUT_DONE_INT_RAW_M (UHCI_OUT_DONE_INT_RAW_V << UHCI_OUT_DONE_INT_RAW_S) +#define UHCI_OUT_DONE_INT_RAW_V 0x00000001 +#define UHCI_OUT_DONE_INT_RAW_S 7 + +/* UHCI_IN_ERR_EOF_INT_RAW : R; bitpos: [6]; default: 0; + * when there are some errors about eof in in link descriptor it will + * produce uhci_in_err_eof_int interrupt. + */ + +#define UHCI_IN_ERR_EOF_INT_RAW (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_RAW_M (UHCI_IN_ERR_EOF_INT_RAW_V << UHCI_IN_ERR_EOF_INT_RAW_S) +#define UHCI_IN_ERR_EOF_INT_RAW_V 0x00000001 +#define UHCI_IN_ERR_EOF_INT_RAW_S 6 + +/* UHCI_IN_SUC_EOF_INT_RAW : R; bitpos: [5]; default: 0; + * when a data packet has been received it will produce uhci_in_suc_eof_int + * interrupt. + */ + +#define UHCI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_RAW_M (UHCI_IN_SUC_EOF_INT_RAW_V << UHCI_IN_SUC_EOF_INT_RAW_S) +#define UHCI_IN_SUC_EOF_INT_RAW_V 0x00000001 +#define UHCI_IN_SUC_EOF_INT_RAW_S 5 + +/* UHCI_IN_DONE_INT_RAW : R; bitpos: [4]; default: 0; + * when a in link descriptor has been completed it will produce + * uhci_in_done_int interrupt. + */ + +#define UHCI_IN_DONE_INT_RAW (BIT(4)) +#define UHCI_IN_DONE_INT_RAW_M (UHCI_IN_DONE_INT_RAW_V << UHCI_IN_DONE_INT_RAW_S) +#define UHCI_IN_DONE_INT_RAW_V 0x00000001 +#define UHCI_IN_DONE_INT_RAW_S 4 + +/* UHCI_TX_HUNG_INT_RAW : R; bitpos: [3]; default: 0; + * when DMA takes a lot of time to read a data from RAM it will produce + * uhci_tx_hung_int interrupt. + */ + +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S) +#define UHCI_TX_HUNG_INT_RAW_V 0x00000001 +#define UHCI_TX_HUNG_INT_RAW_S 3 + +/* UHCI_RX_HUNG_INT_RAW : R; bitpos: [2]; default: 0; + * when DMA takes a lot of time to receive a data it will produce + * uhci_rx_hung_int interrupt. + */ + +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S) +#define UHCI_RX_HUNG_INT_RAW_V 0x00000001 +#define UHCI_RX_HUNG_INT_RAW_S 2 + +/* UHCI_TX_START_INT_RAW : R; bitpos: [1]; default: 0; + * when DMA detects a separator char it will produce uhci_tx_start_int + * interrupt. + */ + +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S) +#define UHCI_TX_START_INT_RAW_V 0x00000001 +#define UHCI_TX_START_INT_RAW_S 1 + +/* UHCI_RX_START_INT_RAW : R; bitpos: [0]; default: 0; + * when a separator char has been send it will produce uhci_rx_start_int + * interrupt. + */ + +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S) +#define UHCI_RX_START_INT_RAW_V 0x00000001 +#define UHCI_RX_START_INT_RAW_S 0 + +/* UHCI_INT_ST_REG register */ + +#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) + +/* UHCI_DMA_INFIFO_FULL_WM_INT_ST : R; bitpos: [16]; default: 0; */ + +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_M (UHCI_DMA_INFIFO_FULL_WM_INT_ST_V << UHCI_DMA_INFIFO_FULL_WM_INT_ST_S) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_V 0x00000001 +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_S 16 + +/* UHCI_SEND_A_Q_INT_ST : R; bitpos: [15]; default: 0; */ + +#define UHCI_SEND_A_Q_INT_ST (BIT(15)) +#define UHCI_SEND_A_Q_INT_ST_M (UHCI_SEND_A_Q_INT_ST_V << UHCI_SEND_A_Q_INT_ST_S) +#define UHCI_SEND_A_Q_INT_ST_V 0x00000001 +#define UHCI_SEND_A_Q_INT_ST_S 15 + +/* UHCI_SEND_S_Q_INT_ST : R; bitpos: [14]; default: 0; */ + +#define UHCI_SEND_S_Q_INT_ST (BIT(14)) +#define UHCI_SEND_S_Q_INT_ST_M (UHCI_SEND_S_Q_INT_ST_V << UHCI_SEND_S_Q_INT_ST_S) +#define UHCI_SEND_S_Q_INT_ST_V 0x00000001 +#define UHCI_SEND_S_Q_INT_ST_S 14 + +/* UHCI_OUT_TOTAL_EOF_INT_ST : R; bitpos: [13]; default: 0; */ + +#define UHCI_OUT_TOTAL_EOF_INT_ST (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ST_M (UHCI_OUT_TOTAL_EOF_INT_ST_V << UHCI_OUT_TOTAL_EOF_INT_ST_S) +#define UHCI_OUT_TOTAL_EOF_INT_ST_V 0x00000001 +#define UHCI_OUT_TOTAL_EOF_INT_ST_S 13 + +/* UHCI_OUTLINK_EOF_ERR_INT_ST : R; bitpos: [12]; default: 0; */ + +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001 +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 12 + +/* UHCI_IN_DSCR_EMPTY_INT_ST : R; bitpos: [11]; default: 0; */ + +#define UHCI_IN_DSCR_EMPTY_INT_ST (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ST_M (UHCI_IN_DSCR_EMPTY_INT_ST_V << UHCI_IN_DSCR_EMPTY_INT_ST_S) +#define UHCI_IN_DSCR_EMPTY_INT_ST_V 0x00000001 +#define UHCI_IN_DSCR_EMPTY_INT_ST_S 11 + +/* UHCI_OUT_DSCR_ERR_INT_ST : R; bitpos: [10]; default: 0; */ + +#define UHCI_OUT_DSCR_ERR_INT_ST (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ST_M (UHCI_OUT_DSCR_ERR_INT_ST_V << UHCI_OUT_DSCR_ERR_INT_ST_S) +#define UHCI_OUT_DSCR_ERR_INT_ST_V 0x00000001 +#define UHCI_OUT_DSCR_ERR_INT_ST_S 10 + +/* UHCI_IN_DSCR_ERR_INT_ST : R; bitpos: [9]; default: 0; */ + +#define UHCI_IN_DSCR_ERR_INT_ST (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ST_M (UHCI_IN_DSCR_ERR_INT_ST_V << UHCI_IN_DSCR_ERR_INT_ST_S) +#define UHCI_IN_DSCR_ERR_INT_ST_V 0x00000001 +#define UHCI_IN_DSCR_ERR_INT_ST_S 9 + +/* UHCI_OUT_EOF_INT_ST : R; bitpos: [8]; default: 0; */ + +#define UHCI_OUT_EOF_INT_ST (BIT(8)) +#define UHCI_OUT_EOF_INT_ST_M (UHCI_OUT_EOF_INT_ST_V << UHCI_OUT_EOF_INT_ST_S) +#define UHCI_OUT_EOF_INT_ST_V 0x00000001 +#define UHCI_OUT_EOF_INT_ST_S 8 + +/* UHCI_OUT_DONE_INT_ST : R; bitpos: [7]; default: 0; */ + +#define UHCI_OUT_DONE_INT_ST (BIT(7)) +#define UHCI_OUT_DONE_INT_ST_M (UHCI_OUT_DONE_INT_ST_V << UHCI_OUT_DONE_INT_ST_S) +#define UHCI_OUT_DONE_INT_ST_V 0x00000001 +#define UHCI_OUT_DONE_INT_ST_S 7 + +/* UHCI_IN_ERR_EOF_INT_ST : R; bitpos: [6]; default: 0; */ + +#define UHCI_IN_ERR_EOF_INT_ST (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ST_M (UHCI_IN_ERR_EOF_INT_ST_V << UHCI_IN_ERR_EOF_INT_ST_S) +#define UHCI_IN_ERR_EOF_INT_ST_V 0x00000001 +#define UHCI_IN_ERR_EOF_INT_ST_S 6 + +/* UHCI_IN_SUC_EOF_INT_ST : R; bitpos: [5]; default: 0; */ + +#define UHCI_IN_SUC_EOF_INT_ST (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ST_M (UHCI_IN_SUC_EOF_INT_ST_V << UHCI_IN_SUC_EOF_INT_ST_S) +#define UHCI_IN_SUC_EOF_INT_ST_V 0x00000001 +#define UHCI_IN_SUC_EOF_INT_ST_S 5 + +/* UHCI_IN_DONE_INT_ST : R; bitpos: [4]; default: 0; */ + +#define UHCI_IN_DONE_INT_ST (BIT(4)) +#define UHCI_IN_DONE_INT_ST_M (UHCI_IN_DONE_INT_ST_V << UHCI_IN_DONE_INT_ST_S) +#define UHCI_IN_DONE_INT_ST_V 0x00000001 +#define UHCI_IN_DONE_INT_ST_S 4 + +/* UHCI_TX_HUNG_INT_ST : R; bitpos: [3]; default: 0; */ + +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S) +#define UHCI_TX_HUNG_INT_ST_V 0x00000001 +#define UHCI_TX_HUNG_INT_ST_S 3 + +/* UHCI_RX_HUNG_INT_ST : R; bitpos: [2]; default: 0; */ + +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S) +#define UHCI_RX_HUNG_INT_ST_V 0x00000001 +#define UHCI_RX_HUNG_INT_ST_S 2 + +/* UHCI_TX_START_INT_ST : R; bitpos: [1]; default: 0; */ + +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S) +#define UHCI_TX_START_INT_ST_V 0x00000001 +#define UHCI_TX_START_INT_ST_S 1 + +/* UHCI_RX_START_INT_ST : R; bitpos: [0]; default: 0; */ + +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S) +#define UHCI_RX_START_INT_ST_V 0x00000001 +#define UHCI_RX_START_INT_ST_S 0 + +/* UHCI_INT_ENA_REG register */ + +#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xc) + +/* UHCI_DMA_INFIFO_FULL_WM_INT_ENA : RW; bitpos: [16]; default: 0; */ + +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_M (UHCI_DMA_INFIFO_FULL_WM_INT_ENA_V << UHCI_DMA_INFIFO_FULL_WM_INT_ENA_S) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_V 0x00000001 +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_S 16 + +/* UHCI_SEND_A_Q_INT_ENA : RW; bitpos: [15]; default: 0; */ + +#define UHCI_SEND_A_Q_INT_ENA (BIT(15)) +#define UHCI_SEND_A_Q_INT_ENA_M (UHCI_SEND_A_Q_INT_ENA_V << UHCI_SEND_A_Q_INT_ENA_S) +#define UHCI_SEND_A_Q_INT_ENA_V 0x00000001 +#define UHCI_SEND_A_Q_INT_ENA_S 15 + +/* UHCI_SEND_S_Q_INT_ENA : RW; bitpos: [14]; default: 0; */ + +#define UHCI_SEND_S_Q_INT_ENA (BIT(14)) +#define UHCI_SEND_S_Q_INT_ENA_M (UHCI_SEND_S_Q_INT_ENA_V << UHCI_SEND_S_Q_INT_ENA_S) +#define UHCI_SEND_S_Q_INT_ENA_V 0x00000001 +#define UHCI_SEND_S_Q_INT_ENA_S 14 + +/* UHCI_OUT_TOTAL_EOF_INT_ENA : RW; bitpos: [13]; default: 0; */ + +#define UHCI_OUT_TOTAL_EOF_INT_ENA (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ENA_M (UHCI_OUT_TOTAL_EOF_INT_ENA_V << UHCI_OUT_TOTAL_EOF_INT_ENA_S) +#define UHCI_OUT_TOTAL_EOF_INT_ENA_V 0x00000001 +#define UHCI_OUT_TOTAL_EOF_INT_ENA_S 13 + +/* UHCI_OUTLINK_EOF_ERR_INT_ENA : RW; bitpos: [12]; default: 0; */ + +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001 +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 12 + +/* UHCI_IN_DSCR_EMPTY_INT_ENA : RW; bitpos: [11]; default: 0; */ + +#define UHCI_IN_DSCR_EMPTY_INT_ENA (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ENA_M (UHCI_IN_DSCR_EMPTY_INT_ENA_V << UHCI_IN_DSCR_EMPTY_INT_ENA_S) +#define UHCI_IN_DSCR_EMPTY_INT_ENA_V 0x00000001 +#define UHCI_IN_DSCR_EMPTY_INT_ENA_S 11 + +/* UHCI_OUT_DSCR_ERR_INT_ENA : RW; bitpos: [10]; default: 0; */ + +#define UHCI_OUT_DSCR_ERR_INT_ENA (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ENA_M (UHCI_OUT_DSCR_ERR_INT_ENA_V << UHCI_OUT_DSCR_ERR_INT_ENA_S) +#define UHCI_OUT_DSCR_ERR_INT_ENA_V 0x00000001 +#define UHCI_OUT_DSCR_ERR_INT_ENA_S 10 + +/* UHCI_IN_DSCR_ERR_INT_ENA : RW; bitpos: [9]; default: 0; */ + +#define UHCI_IN_DSCR_ERR_INT_ENA (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ENA_M (UHCI_IN_DSCR_ERR_INT_ENA_V << UHCI_IN_DSCR_ERR_INT_ENA_S) +#define UHCI_IN_DSCR_ERR_INT_ENA_V 0x00000001 +#define UHCI_IN_DSCR_ERR_INT_ENA_S 9 + +/* UHCI_OUT_EOF_INT_ENA : RW; bitpos: [8]; default: 0; */ + +#define UHCI_OUT_EOF_INT_ENA (BIT(8)) +#define UHCI_OUT_EOF_INT_ENA_M (UHCI_OUT_EOF_INT_ENA_V << UHCI_OUT_EOF_INT_ENA_S) +#define UHCI_OUT_EOF_INT_ENA_V 0x00000001 +#define UHCI_OUT_EOF_INT_ENA_S 8 + +/* UHCI_OUT_DONE_INT_ENA : RW; bitpos: [7]; default: 0; */ + +#define UHCI_OUT_DONE_INT_ENA (BIT(7)) +#define UHCI_OUT_DONE_INT_ENA_M (UHCI_OUT_DONE_INT_ENA_V << UHCI_OUT_DONE_INT_ENA_S) +#define UHCI_OUT_DONE_INT_ENA_V 0x00000001 +#define UHCI_OUT_DONE_INT_ENA_S 7 + +/* UHCI_IN_ERR_EOF_INT_ENA : RW; bitpos: [6]; default: 0; */ + +#define UHCI_IN_ERR_EOF_INT_ENA (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ENA_M (UHCI_IN_ERR_EOF_INT_ENA_V << UHCI_IN_ERR_EOF_INT_ENA_S) +#define UHCI_IN_ERR_EOF_INT_ENA_V 0x00000001 +#define UHCI_IN_ERR_EOF_INT_ENA_S 6 + +/* UHCI_IN_SUC_EOF_INT_ENA : RW; bitpos: [5]; default: 0; */ + +#define UHCI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ENA_M (UHCI_IN_SUC_EOF_INT_ENA_V << UHCI_IN_SUC_EOF_INT_ENA_S) +#define UHCI_IN_SUC_EOF_INT_ENA_V 0x00000001 +#define UHCI_IN_SUC_EOF_INT_ENA_S 5 + +/* UHCI_IN_DONE_INT_ENA : RW; bitpos: [4]; default: 0; */ + +#define UHCI_IN_DONE_INT_ENA (BIT(4)) +#define UHCI_IN_DONE_INT_ENA_M (UHCI_IN_DONE_INT_ENA_V << UHCI_IN_DONE_INT_ENA_S) +#define UHCI_IN_DONE_INT_ENA_V 0x00000001 +#define UHCI_IN_DONE_INT_ENA_S 4 + +/* UHCI_TX_HUNG_INT_ENA : RW; bitpos: [3]; default: 0; */ + +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S) +#define UHCI_TX_HUNG_INT_ENA_V 0x00000001 +#define UHCI_TX_HUNG_INT_ENA_S 3 + +/* UHCI_RX_HUNG_INT_ENA : RW; bitpos: [2]; default: 0; */ + +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S) +#define UHCI_RX_HUNG_INT_ENA_V 0x00000001 +#define UHCI_RX_HUNG_INT_ENA_S 2 + +/* UHCI_TX_START_INT_ENA : RW; bitpos: [1]; default: 0; */ + +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S) +#define UHCI_TX_START_INT_ENA_V 0x00000001 +#define UHCI_TX_START_INT_ENA_S 1 + +/* UHCI_RX_START_INT_ENA : RW; bitpos: [0]; default: 0; */ + +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S) +#define UHCI_RX_START_INT_ENA_V 0x00000001 +#define UHCI_RX_START_INT_ENA_S 0 + +/* UHCI_INT_CLR_REG register */ + +#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) + +/* UHCI_DMA_INFIFO_FULL_WM_INT_CLR : W; bitpos: [16]; default: 0; */ + +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_M (UHCI_DMA_INFIFO_FULL_WM_INT_CLR_V << UHCI_DMA_INFIFO_FULL_WM_INT_CLR_S) +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_V 0x00000001 +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_S 16 + +/* UHCI_SEND_A_Q_INT_CLR : W; bitpos: [15]; default: 0; */ + +#define UHCI_SEND_A_Q_INT_CLR (BIT(15)) +#define UHCI_SEND_A_Q_INT_CLR_M (UHCI_SEND_A_Q_INT_CLR_V << UHCI_SEND_A_Q_INT_CLR_S) +#define UHCI_SEND_A_Q_INT_CLR_V 0x00000001 +#define UHCI_SEND_A_Q_INT_CLR_S 15 + +/* UHCI_SEND_S_Q_INT_CLR : W; bitpos: [14]; default: 0; */ + +#define UHCI_SEND_S_Q_INT_CLR (BIT(14)) +#define UHCI_SEND_S_Q_INT_CLR_M (UHCI_SEND_S_Q_INT_CLR_V << UHCI_SEND_S_Q_INT_CLR_S) +#define UHCI_SEND_S_Q_INT_CLR_V 0x00000001 +#define UHCI_SEND_S_Q_INT_CLR_S 14 + +/* UHCI_OUT_TOTAL_EOF_INT_CLR : W; bitpos: [13]; default: 0; */ + +#define UHCI_OUT_TOTAL_EOF_INT_CLR (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_CLR_M (UHCI_OUT_TOTAL_EOF_INT_CLR_V << UHCI_OUT_TOTAL_EOF_INT_CLR_S) +#define UHCI_OUT_TOTAL_EOF_INT_CLR_V 0x00000001 +#define UHCI_OUT_TOTAL_EOF_INT_CLR_S 13 + +/* UHCI_OUTLINK_EOF_ERR_INT_CLR : W; bitpos: [12]; default: 0; */ + +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001 +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 12 + +/* UHCI_IN_DSCR_EMPTY_INT_CLR : W; bitpos: [11]; default: 0; */ + +#define UHCI_IN_DSCR_EMPTY_INT_CLR (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_CLR_M (UHCI_IN_DSCR_EMPTY_INT_CLR_V << UHCI_IN_DSCR_EMPTY_INT_CLR_S) +#define UHCI_IN_DSCR_EMPTY_INT_CLR_V 0x00000001 +#define UHCI_IN_DSCR_EMPTY_INT_CLR_S 11 + +/* UHCI_OUT_DSCR_ERR_INT_CLR : W; bitpos: [10]; default: 0; */ + +#define UHCI_OUT_DSCR_ERR_INT_CLR (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_CLR_M (UHCI_OUT_DSCR_ERR_INT_CLR_V << UHCI_OUT_DSCR_ERR_INT_CLR_S) +#define UHCI_OUT_DSCR_ERR_INT_CLR_V 0x00000001 +#define UHCI_OUT_DSCR_ERR_INT_CLR_S 10 + +/* UHCI_IN_DSCR_ERR_INT_CLR : W; bitpos: [9]; default: 0; */ + +#define UHCI_IN_DSCR_ERR_INT_CLR (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_CLR_M (UHCI_IN_DSCR_ERR_INT_CLR_V << UHCI_IN_DSCR_ERR_INT_CLR_S) +#define UHCI_IN_DSCR_ERR_INT_CLR_V 0x00000001 +#define UHCI_IN_DSCR_ERR_INT_CLR_S 9 + +/* UHCI_OUT_EOF_INT_CLR : W; bitpos: [8]; default: 0; */ + +#define UHCI_OUT_EOF_INT_CLR (BIT(8)) +#define UHCI_OUT_EOF_INT_CLR_M (UHCI_OUT_EOF_INT_CLR_V << UHCI_OUT_EOF_INT_CLR_S) +#define UHCI_OUT_EOF_INT_CLR_V 0x00000001 +#define UHCI_OUT_EOF_INT_CLR_S 8 + +/* UHCI_OUT_DONE_INT_CLR : W; bitpos: [7]; default: 0; */ + +#define UHCI_OUT_DONE_INT_CLR (BIT(7)) +#define UHCI_OUT_DONE_INT_CLR_M (UHCI_OUT_DONE_INT_CLR_V << UHCI_OUT_DONE_INT_CLR_S) +#define UHCI_OUT_DONE_INT_CLR_V 0x00000001 +#define UHCI_OUT_DONE_INT_CLR_S 7 + +/* UHCI_IN_ERR_EOF_INT_CLR : W; bitpos: [6]; default: 0; */ + +#define UHCI_IN_ERR_EOF_INT_CLR (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_CLR_M (UHCI_IN_ERR_EOF_INT_CLR_V << UHCI_IN_ERR_EOF_INT_CLR_S) +#define UHCI_IN_ERR_EOF_INT_CLR_V 0x00000001 +#define UHCI_IN_ERR_EOF_INT_CLR_S 6 + +/* UHCI_IN_SUC_EOF_INT_CLR : W; bitpos: [5]; default: 0; */ + +#define UHCI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_CLR_M (UHCI_IN_SUC_EOF_INT_CLR_V << UHCI_IN_SUC_EOF_INT_CLR_S) +#define UHCI_IN_SUC_EOF_INT_CLR_V 0x00000001 +#define UHCI_IN_SUC_EOF_INT_CLR_S 5 + +/* UHCI_IN_DONE_INT_CLR : W; bitpos: [4]; default: 0; */ + +#define UHCI_IN_DONE_INT_CLR (BIT(4)) +#define UHCI_IN_DONE_INT_CLR_M (UHCI_IN_DONE_INT_CLR_V << UHCI_IN_DONE_INT_CLR_S) +#define UHCI_IN_DONE_INT_CLR_V 0x00000001 +#define UHCI_IN_DONE_INT_CLR_S 4 + +/* UHCI_TX_HUNG_INT_CLR : W; bitpos: [3]; default: 0; */ + +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S) +#define UHCI_TX_HUNG_INT_CLR_V 0x00000001 +#define UHCI_TX_HUNG_INT_CLR_S 3 + +/* UHCI_RX_HUNG_INT_CLR : W; bitpos: [2]; default: 0; */ + +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S) +#define UHCI_RX_HUNG_INT_CLR_V 0x00000001 +#define UHCI_RX_HUNG_INT_CLR_S 2 + +/* UHCI_TX_START_INT_CLR : W; bitpos: [1]; default: 0; */ + +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S) +#define UHCI_TX_START_INT_CLR_V 0x00000001 +#define UHCI_TX_START_INT_CLR_S 1 + +/* UHCI_RX_START_INT_CLR : W; bitpos: [0]; default: 0; */ + +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S) +#define UHCI_RX_START_INT_CLR_V 0x00000001 +#define UHCI_RX_START_INT_CLR_S 0 + +/* UHCI_DMA_OUT_STATUS_REG register */ + +#define UHCI_DMA_OUT_STATUS_REG(i) (REG_UHCI_BASE(i) + 0x14) + +/* UHCI_OUT_EMPTY : R; bitpos: [1]; default: 1; + * 1:DMA in link descriptor's fifo is empty. + */ + +#define UHCI_OUT_EMPTY (BIT(1)) +#define UHCI_OUT_EMPTY_M (UHCI_OUT_EMPTY_V << UHCI_OUT_EMPTY_S) +#define UHCI_OUT_EMPTY_V 0x00000001 +#define UHCI_OUT_EMPTY_S 1 + +/* UHCI_OUT_FULL : R; bitpos: [0]; default: 0; + * 1:DMA out link descriptor's fifo is full. + */ + +#define UHCI_OUT_FULL (BIT(0)) +#define UHCI_OUT_FULL_M (UHCI_OUT_FULL_V << UHCI_OUT_FULL_S) +#define UHCI_OUT_FULL_V 0x00000001 +#define UHCI_OUT_FULL_S 0 + +/* UHCI_DMA_OUT_PUSH_REG register */ + +#define UHCI_DMA_OUT_PUSH_REG(i) (REG_UHCI_BASE(i) + 0x18) + +/* UHCI_OUTFIFO_PUSH : RW; bitpos: [16]; default: 0; + * Set this bit to push data in out link descriptor's fifo. + */ + +#define UHCI_OUTFIFO_PUSH (BIT(16)) +#define UHCI_OUTFIFO_PUSH_M (UHCI_OUTFIFO_PUSH_V << UHCI_OUTFIFO_PUSH_S) +#define UHCI_OUTFIFO_PUSH_V 0x00000001 +#define UHCI_OUTFIFO_PUSH_S 16 + +/* UHCI_OUTFIFO_WDATA : RW; bitpos: [8:0]; default: 0; + * This is the data need to be pushed into out link descriptor's fifo. + */ + +#define UHCI_OUTFIFO_WDATA 0x000001FF +#define UHCI_OUTFIFO_WDATA_M (UHCI_OUTFIFO_WDATA_V << UHCI_OUTFIFO_WDATA_S) +#define UHCI_OUTFIFO_WDATA_V 0x000001FF +#define UHCI_OUTFIFO_WDATA_S 0 + +/* UHCI_DMA_IN_STATUS_REG register */ + +#define UHCI_DMA_IN_STATUS_REG(i) (REG_UHCI_BASE(i) + 0x1c) + +/* UHCI_RX_ERR_CAUSE : R; bitpos: [6:4]; default: 0; + * This register stores the errors caused in out link descriptor's data + * packet. + */ + +#define UHCI_RX_ERR_CAUSE 0x00000007 +#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S) +#define UHCI_RX_ERR_CAUSE_V 0x00000007 +#define UHCI_RX_ERR_CAUSE_S 4 + +/* UHCI_IN_EMPTY : R; bitpos: [1]; default: 1; */ + +#define UHCI_IN_EMPTY (BIT(1)) +#define UHCI_IN_EMPTY_M (UHCI_IN_EMPTY_V << UHCI_IN_EMPTY_S) +#define UHCI_IN_EMPTY_V 0x00000001 +#define UHCI_IN_EMPTY_S 1 + +/* UHCI_IN_FULL : R; bitpos: [0]; default: 0; */ + +#define UHCI_IN_FULL (BIT(0)) +#define UHCI_IN_FULL_M (UHCI_IN_FULL_V << UHCI_IN_FULL_S) +#define UHCI_IN_FULL_V 0x00000001 +#define UHCI_IN_FULL_S 0 + +/* UHCI_DMA_IN_POP_REG register */ + +#define UHCI_DMA_IN_POP_REG(i) (REG_UHCI_BASE(i) + 0x20) + +/* UHCI_INFIFO_POP : RW; bitpos: [16]; default: 0; + * Set this bit to pop data in in link descriptor's fifo. + */ + +#define UHCI_INFIFO_POP (BIT(16)) +#define UHCI_INFIFO_POP_M (UHCI_INFIFO_POP_V << UHCI_INFIFO_POP_S) +#define UHCI_INFIFO_POP_V 0x00000001 +#define UHCI_INFIFO_POP_S 16 + +/* UHCI_INFIFO_RDATA : R; bitpos: [11:0]; default: 0; + * This register stores the data pop from in link descriptor's fifo. + */ + +#define UHCI_INFIFO_RDATA 0x00000FFF +#define UHCI_INFIFO_RDATA_M (UHCI_INFIFO_RDATA_V << UHCI_INFIFO_RDATA_S) +#define UHCI_INFIFO_RDATA_V 0x00000FFF +#define UHCI_INFIFO_RDATA_S 0 + +/* UHCI_DMA_OUT_LINK_REG register */ + +#define UHCI_DMA_OUT_LINK_REG(i) (REG_UHCI_BASE(i) + 0x24) + +/* UHCI_OUTLINK_PARK : R; bitpos: [31]; default: 0; + * 1£º the out link descriptor's fsm is in idle state. 0:the out link + * descriptor's fsm is working. + */ + +#define UHCI_OUTLINK_PARK (BIT(31)) +#define UHCI_OUTLINK_PARK_M (UHCI_OUTLINK_PARK_V << UHCI_OUTLINK_PARK_S) +#define UHCI_OUTLINK_PARK_V 0x00000001 +#define UHCI_OUTLINK_PARK_S 31 + +/* UHCI_OUTLINK_RESTART : RW; bitpos: [30]; default: 0; + * Set this bit to mount on new out link descriptors + */ + +#define UHCI_OUTLINK_RESTART (BIT(30)) +#define UHCI_OUTLINK_RESTART_M (UHCI_OUTLINK_RESTART_V << UHCI_OUTLINK_RESTART_S) +#define UHCI_OUTLINK_RESTART_V 0x00000001 +#define UHCI_OUTLINK_RESTART_S 30 + +/* UHCI_OUTLINK_START : RW; bitpos: [29]; default: 0; + * Set this bit to start dealing with the out link descriptors. + */ + +#define UHCI_OUTLINK_START (BIT(29)) +#define UHCI_OUTLINK_START_M (UHCI_OUTLINK_START_V << UHCI_OUTLINK_START_S) +#define UHCI_OUTLINK_START_V 0x00000001 +#define UHCI_OUTLINK_START_S 29 + +/* UHCI_OUTLINK_STOP : RW; bitpos: [28]; default: 0; + * Set this bit to stop dealing with the out link descriptors. + */ + +#define UHCI_OUTLINK_STOP (BIT(28)) +#define UHCI_OUTLINK_STOP_M (UHCI_OUTLINK_STOP_V << UHCI_OUTLINK_STOP_S) +#define UHCI_OUTLINK_STOP_V 0x00000001 +#define UHCI_OUTLINK_STOP_S 28 + +/* UHCI_OUTLINK_ADDR : RW; bitpos: [19:0]; default: 0; + * This register stores the least 20 bits of the first out link descriptor's + * address. + */ + +#define UHCI_OUTLINK_ADDR 0x000FFFFF +#define UHCI_OUTLINK_ADDR_M (UHCI_OUTLINK_ADDR_V << UHCI_OUTLINK_ADDR_S) +#define UHCI_OUTLINK_ADDR_V 0x000FFFFF +#define UHCI_OUTLINK_ADDR_S 0 + +/* UHCI_DMA_IN_LINK_REG register */ + +#define UHCI_DMA_IN_LINK_REG(i) (REG_UHCI_BASE(i) + 0x28) + +/* UHCI_INLINK_PARK : R; bitpos: [31]; default: 0; + * 1:the in link descriptor's fsm is in idle state. 0:the in link + * descriptor's fsm is working + */ + +#define UHCI_INLINK_PARK (BIT(31)) +#define UHCI_INLINK_PARK_M (UHCI_INLINK_PARK_V << UHCI_INLINK_PARK_S) +#define UHCI_INLINK_PARK_V 0x00000001 +#define UHCI_INLINK_PARK_S 31 + +/* UHCI_INLINK_RESTART : RW; bitpos: [30]; default: 0; + * Set this bit to mount on new in link descriptors + */ + +#define UHCI_INLINK_RESTART (BIT(30)) +#define UHCI_INLINK_RESTART_M (UHCI_INLINK_RESTART_V << UHCI_INLINK_RESTART_S) +#define UHCI_INLINK_RESTART_V 0x00000001 +#define UHCI_INLINK_RESTART_S 30 + +/* UHCI_INLINK_START : RW; bitpos: [29]; default: 0; + * Set this bit to start dealing with the in link descriptors. + */ + +#define UHCI_INLINK_START (BIT(29)) +#define UHCI_INLINK_START_M (UHCI_INLINK_START_V << UHCI_INLINK_START_S) +#define UHCI_INLINK_START_V 0x00000001 +#define UHCI_INLINK_START_S 29 + +/* UHCI_INLINK_STOP : RW; bitpos: [28]; default: 0; + * Set this bit to stop dealing with the in link descriptors. + */ + +#define UHCI_INLINK_STOP (BIT(28)) +#define UHCI_INLINK_STOP_M (UHCI_INLINK_STOP_V << UHCI_INLINK_STOP_S) +#define UHCI_INLINK_STOP_V 0x00000001 +#define UHCI_INLINK_STOP_S 28 + +/* UHCI_INLINK_AUTO_RET : RW; bitpos: [20]; default: 1; + * 1:when a packet is wrong in link descriptor returns to the descriptor + * which is lately used. + */ + +#define UHCI_INLINK_AUTO_RET (BIT(20)) +#define UHCI_INLINK_AUTO_RET_M (UHCI_INLINK_AUTO_RET_V << UHCI_INLINK_AUTO_RET_S) +#define UHCI_INLINK_AUTO_RET_V 0x00000001 +#define UHCI_INLINK_AUTO_RET_S 20 + +/* UHCI_INLINK_ADDR : RW; bitpos: [19:0]; default: 0; + * This register stores the least 20 bits of the first in link descriptor's + * address. + */ + +#define UHCI_INLINK_ADDR 0x000FFFFF +#define UHCI_INLINK_ADDR_M (UHCI_INLINK_ADDR_V << UHCI_INLINK_ADDR_S) +#define UHCI_INLINK_ADDR_V 0x000FFFFF +#define UHCI_INLINK_ADDR_S 0 + +/* UHCI_CONF1_REG register */ + +#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x2c) + +/* UHCI_DMA_INFIFO_FULL_THRS : RW; bitpos: [20:9]; default: 0; + * when data amount in link descriptor's fifo is more than this register + * value it will produce uhci_dma_infifo_full_wm_int interrupt. + */ + +#define UHCI_DMA_INFIFO_FULL_THRS 0x00000FFF +#define UHCI_DMA_INFIFO_FULL_THRS_M (UHCI_DMA_INFIFO_FULL_THRS_V << UHCI_DMA_INFIFO_FULL_THRS_S) +#define UHCI_DMA_INFIFO_FULL_THRS_V 0x00000FFF +#define UHCI_DMA_INFIFO_FULL_THRS_S 9 + +/* UHCI_SW_START : RW; bitpos: [8]; default: 0; + * Set this bit to start inserting the packet header. + */ + +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S) +#define UHCI_SW_START_V 0x00000001 +#define UHCI_SW_START_S 8 + +/* UHCI_WAIT_SW_START : RW; bitpos: [7]; default: 0; + * Set this bit to enable software way to add packet header. + */ + +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S) +#define UHCI_WAIT_SW_START_V 0x00000001 +#define UHCI_WAIT_SW_START_S 7 + +/* UHCI_CHECK_OWNER : RW; bitpos: [6]; default: 0; + * Set this bit to check the owner bit in link descriptor. + */ + +#define UHCI_CHECK_OWNER (BIT(6)) +#define UHCI_CHECK_OWNER_M (UHCI_CHECK_OWNER_V << UHCI_CHECK_OWNER_S) +#define UHCI_CHECK_OWNER_V 0x00000001 +#define UHCI_CHECK_OWNER_S 6 + +/* UHCI_TX_ACK_NUM_RE : RW; bitpos: [5]; default: 1; + * Set this bit to enable hardware replace ack num in packet header + * automatically. + */ + +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S) +#define UHCI_TX_ACK_NUM_RE_V 0x00000001 +#define UHCI_TX_ACK_NUM_RE_S 5 + +/* UHCI_TX_CHECK_SUM_RE : RW; bitpos: [4]; default: 1; + * Set this bit to enable hardware replace check_sum in packet header + * automatically. + */ + +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S) +#define UHCI_TX_CHECK_SUM_RE_V 0x00000001 +#define UHCI_TX_CHECK_SUM_RE_S 4 + +/* UHCI_SAVE_HEAD : RW; bitpos: [3]; default: 0; + * Set this bit to save packet header . + */ + +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S) +#define UHCI_SAVE_HEAD_V 0x00000001 +#define UHCI_SAVE_HEAD_S 3 + +/* UHCI_CRC_DISABLE : RW; bitpos: [2]; default: 0; + * Set this bit to disable crc calculation. + */ + +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S) +#define UHCI_CRC_DISABLE_V 0x00000001 +#define UHCI_CRC_DISABLE_S 2 + +/* UHCI_CHECK_SEQ_EN : RW; bitpos: [1]; default: 1; + * Set this bit to enable decoder to check seq num in packet header. + */ + +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S) +#define UHCI_CHECK_SEQ_EN_V 0x00000001 +#define UHCI_CHECK_SEQ_EN_S 1 + +/* UHCI_CHECK_SUM_EN : RW; bitpos: [0]; default: 1; + * Set this bit to enable decoder to check check_sum in packet header. + */ + +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S) +#define UHCI_CHECK_SUM_EN_V 0x00000001 +#define UHCI_CHECK_SUM_EN_S 0 + +/* UHCI_STATE0_REG register */ + +#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x30) + +/* UHCI_STATE0 : R; bitpos: [31:0]; default: 0; */ + +#define UHCI_STATE0 0xFFFFFFFF +#define UHCI_STATE0_M (UHCI_STATE0_V << UHCI_STATE0_S) +#define UHCI_STATE0_V 0xFFFFFFFF +#define UHCI_STATE0_S 0 + +/* UHCI_STATE1_REG register */ + +#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x34) + +/* UHCI_STATE1 : R; bitpos: [31:0]; default: 0; */ + +#define UHCI_STATE1 0xFFFFFFFF +#define UHCI_STATE1_M (UHCI_STATE1_V << UHCI_STATE1_S) +#define UHCI_STATE1_V 0xFFFFFFFF +#define UHCI_STATE1_S 0 + +/* UHCI_DMA_OUT_EOF_DES_ADDR_REG register */ + +#define UHCI_DMA_OUT_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x38) + +/* UHCI_OUT_EOF_DES_ADDR : R; bitpos: [31:0]; default: 0; + * This register stores the address of out link descriptoir when eof bit in + * this descriptor is 1. + */ + +#define UHCI_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_OUT_EOF_DES_ADDR_M (UHCI_OUT_EOF_DES_ADDR_V << UHCI_OUT_EOF_DES_ADDR_S) +#define UHCI_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_OUT_EOF_DES_ADDR_S 0 + +/* UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG register */ + +#define UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x3c) + +/* UHCI_IN_SUC_EOF_DES_ADDR : R; bitpos: [31:0]; default: 0; + * This register stores the address of in link descriptor when eof bit in + * this descriptor is 1. + */ + +#define UHCI_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_IN_SUC_EOF_DES_ADDR_M (UHCI_IN_SUC_EOF_DES_ADDR_V << UHCI_IN_SUC_EOF_DES_ADDR_S) +#define UHCI_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_IN_SUC_EOF_DES_ADDR_S 0 + +/* UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG register */ + +#define UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x40) + +/* UHCI_IN_ERR_EOF_DES_ADDR : R; bitpos: [31:0]; default: 0; + * This register stores the address of in link descriptor when there are + * some errors in this descriptor. + */ + +#define UHCI_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_IN_ERR_EOF_DES_ADDR_M (UHCI_IN_ERR_EOF_DES_ADDR_V << UHCI_IN_ERR_EOF_DES_ADDR_S) +#define UHCI_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_IN_ERR_EOF_DES_ADDR_S 0 + +/* UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG register */ + +#define UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x44) + +/* UHCI_OUT_EOF_BFR_DES_ADDR : R; bitpos: [31:0]; default: 0; + * This register stores the address of out link descriptor when there are + * some errors in this descriptor. + */ + +#define UHCI_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define UHCI_OUT_EOF_BFR_DES_ADDR_M (UHCI_OUT_EOF_BFR_DES_ADDR_V << UHCI_OUT_EOF_BFR_DES_ADDR_S) +#define UHCI_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define UHCI_OUT_EOF_BFR_DES_ADDR_S 0 + +/* UHCI_AHB_TEST_REG register */ + +#define UHCI_AHB_TEST_REG(i) (REG_UHCI_BASE(i) + 0x48) + +/* UHCI_AHB_TESTADDR : RW; bitpos: [5:4]; default: 0; + * The two bits represent ahb bus address bit[20:19] + */ + +#define UHCI_AHB_TESTADDR 0x00000003 +#define UHCI_AHB_TESTADDR_M (UHCI_AHB_TESTADDR_V << UHCI_AHB_TESTADDR_S) +#define UHCI_AHB_TESTADDR_V 0x00000003 +#define UHCI_AHB_TESTADDR_S 4 + +/* UHCI_AHB_TESTMODE : RW; bitpos: [2:0]; default: 0; + * bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) + * mode. bit0 is used to choose test only once(1) or continue(0) + */ + +#define UHCI_AHB_TESTMODE 0x00000007 +#define UHCI_AHB_TESTMODE_M (UHCI_AHB_TESTMODE_V << UHCI_AHB_TESTMODE_S) +#define UHCI_AHB_TESTMODE_V 0x00000007 +#define UHCI_AHB_TESTMODE_S 0 + +/* UHCI_DMA_IN_DSCR_REG register */ + +#define UHCI_DMA_IN_DSCR_REG(i) (REG_UHCI_BASE(i) + 0x4c) + +/* UHCI_INLINK_DSCR : R; bitpos: [31:0]; default: 0; + * The content of current in link descriptor's third dword + */ + +#define UHCI_INLINK_DSCR 0xFFFFFFFF +#define UHCI_INLINK_DSCR_M (UHCI_INLINK_DSCR_V << UHCI_INLINK_DSCR_S) +#define UHCI_INLINK_DSCR_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_S 0 + +/* UHCI_DMA_IN_DSCR_BF0_REG register */ + +#define UHCI_DMA_IN_DSCR_BF0_REG(i) (REG_UHCI_BASE(i) + 0x50) + +/* UHCI_INLINK_DSCR_BF0 : R; bitpos: [31:0]; default: 0; + * The content of current in link descriptor's first dword + */ + +#define UHCI_INLINK_DSCR_BF0 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF0_M (UHCI_INLINK_DSCR_BF0_V << UHCI_INLINK_DSCR_BF0_S) +#define UHCI_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF0_S 0 + +/* UHCI_DMA_IN_DSCR_BF1_REG register */ + +#define UHCI_DMA_IN_DSCR_BF1_REG(i) (REG_UHCI_BASE(i) + 0x54) + +/* UHCI_INLINK_DSCR_BF1 : R; bitpos: [31:0]; default: 0; + * The content of current in link descriptor's second dword + */ + +#define UHCI_INLINK_DSCR_BF1 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF1_M (UHCI_INLINK_DSCR_BF1_V << UHCI_INLINK_DSCR_BF1_S) +#define UHCI_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF1_S 0 + +/* UHCI_DMA_OUT_DSCR_REG register */ + +#define UHCI_DMA_OUT_DSCR_REG(i) (REG_UHCI_BASE(i) + 0x58) + +/* UHCI_OUTLINK_DSCR : R; bitpos: [31:0]; default: 0; + * The content of current out link descriptor's third dword + */ + +#define UHCI_OUTLINK_DSCR 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_M (UHCI_OUTLINK_DSCR_V << UHCI_OUTLINK_DSCR_S) +#define UHCI_OUTLINK_DSCR_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_S 0 + +/* UHCI_DMA_OUT_DSCR_BF0_REG register */ + +#define UHCI_DMA_OUT_DSCR_BF0_REG(i) (REG_UHCI_BASE(i) + 0x5c) + +/* UHCI_OUTLINK_DSCR_BF0 : R; bitpos: [31:0]; default: 0; + * The content of current out link descriptor's first dword + */ + +#define UHCI_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF0_M (UHCI_OUTLINK_DSCR_BF0_V << UHCI_OUTLINK_DSCR_BF0_S) +#define UHCI_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF0_S 0 + +/* UHCI_DMA_OUT_DSCR_BF1_REG register */ + +#define UHCI_DMA_OUT_DSCR_BF1_REG(i) (REG_UHCI_BASE(i) + 0x60) + +/* UHCI_OUTLINK_DSCR_BF1 : R; bitpos: [31:0]; default: 0; + * The content of current out link descriptor's second dword + */ + +#define UHCI_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF1_M (UHCI_OUTLINK_DSCR_BF1_V << UHCI_OUTLINK_DSCR_BF1_S) +#define UHCI_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF1_S 0 + +/* UHCI_ESCAPE_CONF_REG register */ + +#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x64) + +/* UHCI_RX_13_ESC_EN : RW; bitpos: [7]; default: 0; + * Set this bit to enable flow control char 0x13 replace when DMA sends + * data. + */ + +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S) +#define UHCI_RX_13_ESC_EN_V 0x00000001 +#define UHCI_RX_13_ESC_EN_S 7 + +/* UHCI_RX_11_ESC_EN : RW; bitpos: [6]; default: 0; + * Set this bit to enable flow control char 0x11 replace when DMA sends + * data. + */ + +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S) +#define UHCI_RX_11_ESC_EN_V 0x00000001 +#define UHCI_RX_11_ESC_EN_S 6 + +/* UHCI_RX_DB_ESC_EN : RW; bitpos: [5]; default: 1; + * Set this bit to enable 0xdb char replace when DMA sends data. + */ + +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S) +#define UHCI_RX_DB_ESC_EN_V 0x00000001 +#define UHCI_RX_DB_ESC_EN_S 5 + +/* UHCI_RX_C0_ESC_EN : RW; bitpos: [4]; default: 1; + * Set this bit to enable 0xc0 char replace when DMA sends data. + */ + +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S) +#define UHCI_RX_C0_ESC_EN_V 0x00000001 +#define UHCI_RX_C0_ESC_EN_S 4 + +/* UHCI_TX_13_ESC_EN : RW; bitpos: [3]; default: 0; + * Set this bit to enable flow control char 0x13 decode when DMA receives + * data. + */ + +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S) +#define UHCI_TX_13_ESC_EN_V 0x00000001 +#define UHCI_TX_13_ESC_EN_S 3 + +/* UHCI_TX_11_ESC_EN : RW; bitpos: [2]; default: 0; + * Set this bit to enable flow control char 0x11 decode when DMA receives + * data. + */ + +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S) +#define UHCI_TX_11_ESC_EN_V 0x00000001 +#define UHCI_TX_11_ESC_EN_S 2 + +/* UHCI_TX_DB_ESC_EN : RW; bitpos: [1]; default: 1; + * Set this bit to enable 0xdb char decode when DMA receives data. + */ + +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S) +#define UHCI_TX_DB_ESC_EN_V 0x00000001 +#define UHCI_TX_DB_ESC_EN_S 1 + +/* UHCI_TX_C0_ESC_EN : RW; bitpos: [0]; default: 1; + * Set this bit to enable 0xc0 char decode when DMA receives data. + */ + +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S) +#define UHCI_TX_C0_ESC_EN_V 0x00000001 +#define UHCI_TX_C0_ESC_EN_S 0 + +/* UHCI_HUNG_CONF_REG register */ + +#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x68) + +/* UHCI_RXFIFO_TIMEOUT_ENA : RW; bitpos: [23]; default: 1; + * This is the enable bit for DMA send data timeout + */ + +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001 +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 + +/* UHCI_RXFIFO_TIMEOUT_SHIFT : RW; bitpos: [22:20]; default: 0; + * The tick count is cleared when its value + * >=(17'd8000>>reg_rxfifo_timeout_shift) + */ + +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 + +/* UHCI_RXFIFO_TIMEOUT : RW; bitpos: [19:12]; default: 16; + * This register stores the timeout value.when DMA takes more time than this + * register value to read a data from RAM it will produce uhci_rx_hung_int + * interrupt. + */ + +#define UHCI_RXFIFO_TIMEOUT 0x000000FF +#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S) +#define UHCI_RXFIFO_TIMEOUT_V 0x000000FF +#define UHCI_RXFIFO_TIMEOUT_S 12 + +/* UHCI_TXFIFO_TIMEOUT_ENA : RW; bitpos: [11]; default: 1; + * The enable bit for txfifo receive data timeout + */ + +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001 +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 + +/* UHCI_TXFIFO_TIMEOUT_SHIFT : RW; bitpos: [10:8]; default: 0; + * The tick count is cleared when its value + * >=(17'd8000>>reg_txfifo_timeout_shift) + */ + +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 + +/* UHCI_TXFIFO_TIMEOUT : RW; bitpos: [7:0]; default: 16; + * This register stores the timeout value.when DMA takes more time than this + * register value to receive a data it will produce uhci_tx_hung_int + * interrupt. + */ + +#define UHCI_TXFIFO_TIMEOUT 0x000000FF +#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S) +#define UHCI_TXFIFO_TIMEOUT_V 0x000000FF +#define UHCI_TXFIFO_TIMEOUT_S 0 + +/* UHCI_ACK_NUM_REG register */ + +#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x6c) + +/* UHCI_RX_HEAD_REG register */ + +#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x70) + +/* UHCI_RX_HEAD : R; bitpos: [31:0]; default: 0; + * This register stores the packet header received by DMA + */ + +#define UHCI_RX_HEAD 0xFFFFFFFF +#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S) +#define UHCI_RX_HEAD_V 0xFFFFFFFF +#define UHCI_RX_HEAD_S 0 + +/* UHCI_QUICK_SENT_REG register */ + +#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x74) + +/* UHCI_ALWAYS_SEND_EN : RW; bitpos: [7]; default: 0; + * Set this bit to enable continuously send the same short packet + */ + +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S) +#define UHCI_ALWAYS_SEND_EN_V 0x00000001 +#define UHCI_ALWAYS_SEND_EN_S 7 + +/* UHCI_ALWAYS_SEND_NUM : RW; bitpos: [6:4]; default: 0; + * The bits are used to choose which short packet + */ + +#define UHCI_ALWAYS_SEND_NUM 0x00000007 +#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S) +#define UHCI_ALWAYS_SEND_NUM_V 0x00000007 +#define UHCI_ALWAYS_SEND_NUM_S 4 + +/* UHCI_SINGLE_SEND_EN : RW; bitpos: [3]; default: 0; + * Set this bit to enable send a short packet + */ + +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S) +#define UHCI_SINGLE_SEND_EN_V 0x00000001 +#define UHCI_SINGLE_SEND_EN_S 3 + +/* UHCI_SINGLE_SEND_NUM : RW; bitpos: [2:0]; default: 0; + * The bits are used to choose which short packet + */ + +#define UHCI_SINGLE_SEND_NUM 0x00000007 +#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S) +#define UHCI_SINGLE_SEND_NUM_V 0x00000007 +#define UHCI_SINGLE_SEND_NUM_S 0 + +/* UHCI_Q0_WORD0_REG register */ + +#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x78) + +/* UHCI_SEND_Q0_WORD0 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's first dword + */ + +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_S 0 + +/* UHCI_Q0_WORD1_REG register */ + +#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x7c) + +/* UHCI_SEND_Q0_WORD1 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's second dword + */ + +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_S 0 + +/* UHCI_Q1_WORD0_REG register */ + +#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x80) + +/* UHCI_SEND_Q1_WORD0 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's first dword + */ + +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_S 0 + +/* UHCI_Q1_WORD1_REG register */ + +#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x84) + +/* UHCI_SEND_Q1_WORD1 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's second dword + */ + +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_S 0 + +/* UHCI_Q2_WORD0_REG register */ + +#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x88) + +/* UHCI_SEND_Q2_WORD0 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's first dword + */ + +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_S 0 + +/* UHCI_Q2_WORD1_REG register */ + +#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x8c) + +/* UHCI_SEND_Q2_WORD1 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's second dword + */ + +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_S 0 + +/* UHCI_Q3_WORD0_REG register */ + +#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x90) + +/* UHCI_SEND_Q3_WORD0 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's first dword + */ + +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_S 0 + +/* UHCI_Q3_WORD1_REG register */ + +#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x94) + +/* UHCI_SEND_Q3_WORD1 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's second dword + */ + +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_S 0 + +/* UHCI_Q4_WORD0_REG register */ + +#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x98) + +/* UHCI_SEND_Q4_WORD0 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's first dword + */ + +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_S 0 + +/* UHCI_Q4_WORD1_REG register */ + +#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x9c) + +/* UHCI_SEND_Q4_WORD1 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's second dword + */ + +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_S 0 + +/* UHCI_Q5_WORD0_REG register */ + +#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0xa0) + +/* UHCI_SEND_Q5_WORD0 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's first dword + */ + +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_S 0 + +/* UHCI_Q5_WORD1_REG register */ + +#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0xa4) + +/* UHCI_SEND_Q5_WORD1 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's second dword + */ + +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_S 0 + +/* UHCI_Q6_WORD0_REG register */ + +#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0xa8) + +/* UHCI_SEND_Q6_WORD0 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's first dword + */ + +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_S 0 + +/* UHCI_Q6_WORD1_REG register */ + +#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0xac) + +/* UHCI_SEND_Q6_WORD1 : RW; bitpos: [31:0]; default: 0; + * This register stores the content of short packet's second dword + */ + +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_S 0 + +/* UHCI_ESC_CONF0_REG register */ + +#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0xb0) + +/* UHCI_SEPER_ESC_CHAR1 : RW; bitpos: [23:16]; default: 220; + * This register stores the second char used to replace seperator char in + * data . 0xdc 0xdb replace 0xc0 by default. + */ + +#define UHCI_SEPER_ESC_CHAR1 0x000000FF +#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S) +#define UHCI_SEPER_ESC_CHAR1_V 0x000000FF +#define UHCI_SEPER_ESC_CHAR1_S 16 + +/* UHCI_SEPER_ESC_CHAR0 : RW; bitpos: [15:8]; default: 219; + * This register stores thee first char used to replace seperator char in + * data. + */ + +#define UHCI_SEPER_ESC_CHAR0 0x000000FF +#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S) +#define UHCI_SEPER_ESC_CHAR0_V 0x000000FF +#define UHCI_SEPER_ESC_CHAR0_S 8 + +/* UHCI_SEPER_CHAR : RW; bitpos: [7:0]; default: 192; + * This register stores the seperator char seperator char is used to + * seperate the data frame. + */ + +#define UHCI_SEPER_CHAR 0x000000FF +#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S) +#define UHCI_SEPER_CHAR_V 0x000000FF +#define UHCI_SEPER_CHAR_S 0 + +/* UHCI_ESC_CONF1_REG register */ + +#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0xb4) + +/* UHCI_ESC_SEQ0_CHAR1 : RW; bitpos: [23:16]; default: 221; + * This register stores the second char used to replace the reg_esc_seq0 in + * data + */ + +#define UHCI_ESC_SEQ0_CHAR1 0x000000FF +#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S) +#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FF +#define UHCI_ESC_SEQ0_CHAR1_S 16 + +/* UHCI_ESC_SEQ0_CHAR0 : RW; bitpos: [15:8]; default: 219; + * This register stores the first char used to replace reg_esc_seq0 in data. + */ + +#define UHCI_ESC_SEQ0_CHAR0 0x000000FF +#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S) +#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FF +#define UHCI_ESC_SEQ0_CHAR0_S 8 + +/* UHCI_ESC_SEQ0 : RW; bitpos: [7:0]; default: 219; + * This register stores the first substitute char used to replace the + * seperator char. + */ + +#define UHCI_ESC_SEQ0 0x000000FF +#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S) +#define UHCI_ESC_SEQ0_V 0x000000FF +#define UHCI_ESC_SEQ0_S 0 + +/* UHCI_ESC_CONF2_REG register */ + +#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0xb8) + +/* UHCI_ESC_SEQ1_CHAR1 : RW; bitpos: [23:16]; default: 222; + * This register stores the second char used to replace the reg_esc_seq1 in + * data. + */ + +#define UHCI_ESC_SEQ1_CHAR1 0x000000FF +#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S) +#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FF +#define UHCI_ESC_SEQ1_CHAR1_S 16 + +/* UHCI_ESC_SEQ1_CHAR0 : RW; bitpos: [15:8]; default: 219; + * This register stores the first char used to replace the reg_esc_seq1 in + * data. + */ + +#define UHCI_ESC_SEQ1_CHAR0 0x000000FF +#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S) +#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FF +#define UHCI_ESC_SEQ1_CHAR0_S 8 + +/* UHCI_ESC_SEQ1 : RW; bitpos: [7:0]; default: 17; + * This register stores the flow control char to turn on the flow_control + */ + +#define UHCI_ESC_SEQ1 0x000000FF +#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S) +#define UHCI_ESC_SEQ1_V 0x000000FF +#define UHCI_ESC_SEQ1_S 0 + +/* UHCI_ESC_CONF3_REG register */ + +#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0xbc) + +/* UHCI_ESC_SEQ2_CHAR1 : RW; bitpos: [23:16]; default: 223; + * This register stores the second char used to replace the reg_esc_seq2 in + * data. + */ + +#define UHCI_ESC_SEQ2_CHAR1 0x000000FF +#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S) +#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FF +#define UHCI_ESC_SEQ2_CHAR1_S 16 + +/* UHCI_ESC_SEQ2_CHAR0 : RW; bitpos: [15:8]; default: 219; + * This register stores the first char used to replace the reg_esc_seq2 in + * data. + */ + +#define UHCI_ESC_SEQ2_CHAR0 0x000000FF +#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S) +#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FF +#define UHCI_ESC_SEQ2_CHAR0_S 8 + +/* UHCI_ESC_SEQ2 : RW; bitpos: [7:0]; default: 19; + * This register stores the flow_control char to turn off the flow_control + */ + +#define UHCI_ESC_SEQ2 0x000000FF +#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S) +#define UHCI_ESC_SEQ2_V 0x000000FF +#define UHCI_ESC_SEQ2_S 0 + +/* UHCI_PKT_THRES_REG register */ + +#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0xc0) + +/* UHCI_PKT_THRS : RW; bitpos: [12:0]; default: 128; + * when the amount of packet payload is greater than this value the process + * of receiving data is done. + */ + +#define UHCI_PKT_THRS 0x00001FFF +#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S) +#define UHCI_PKT_THRS_V 0x00001FFF +#define UHCI_PKT_THRS_S 0 + +/* UHCI_DATE_REG register */ + +#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0xfc) + +/* UHCI_DATE : RW; bitpos: [31:0]; default: 369364993; + * version information + */ + +#define UHCI_DATE 0xFFFFFFFF +#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S) +#define UHCI_DATE_V 0xFFFFFFFF +#define UHCI_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_UHCI_H */ diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig new file mode 100644 index 00000000000..e4ccd9a151b --- /dev/null +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -0,0 +1,883 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_ESP32S2 + +comment "ESP32-S2 Configuration Options" + +choice + prompt "ESP32-S2 Chip Selection" + default ARCH_CHIP_ESP32S2WROVER + depends on ARCH_CHIP_ESP32S2 + +config ARCH_CHIP_ESP32S2WROVER + bool "ESP32-S2-WROVER" + select ESP32S2_ESP32S2DXWDXX + select ESP32S2_FLASH_4M + select ESP32S2_PSRAM_8M + ---help--- + Generic module with an embedded ESP32-S2 + +endchoice # ESP32S2 Chip Selection + +choice + prompt "Instruction CACHE Size" + default ESP32S2_INSTRUCTION_CACHE_8KB + depends on ARCH_CHIP_ESP32S2 + +config ESP32S2_INSTRUCTION_CACHE_8KB + bool "8KB" + ---help--- + Use 8KB of SRAM as Instruction Cache + +config ESP32S2_INSTRUCTION_CACHE_16KB + bool "16KB" + ---help--- + Use 16KB of SRAM as Instruction Cache + +endchoice # ESP32S2 Instruction CACHE size + +choice + prompt "Instruction CACHE Size" + default ESP32S2_INSTRUCTION_CACHE_8KB + depends on ARCH_CHIP_ESP32S2 + +config ESP32S2_DATA_CACHE_0KB + bool "No DATA CACHE" + ---help--- + Use 8KB of SRAM as Data Cache + +config ESP32S2_DATA_CACHE_8KB + bool "8KB" + ---help--- + Use 8KB of SRAM as Data Cache + +config ESP32S2_DATA_CACHE_16KB + bool "16KB" + ---help--- + Use 16KB of SRAM as Data Cache + +endchoice # ESP32S2 Data CACHE size + +config ESP32S2_SINGLE_CPU + bool + default y + +config ESP32S2_FLASH_2M + bool + default n + +config ESP32S2_FLASH_4M + bool + default n + +config ESP32S2_FLASH_8M + bool + default n + +config ESP32S2_FLASH_16M + bool + default n + +config ESP32S2_FLASH_DETECT + bool "Auto-detect FLASH size" + default y + ---help--- + Auto detect flash size when flashing. + +config ESP32S2_PSRAM_8M + bool + default n + +config ESP32S2_ESP32S2SXWDXX + bool + default n + select ESP32S2_SINGLE_CPU + select ARCH_HAVE_I2CRESET + +choice ESP32S2_FLASH_MODE + prompt "SPI FLASH mode" + default ESP32S2_FLASH_MODE_DIO + ---help--- + These options control how many I/O pins are used for communication + with the attached SPI flash chip. + The option selected here is then used by esptool when flashing. + + config ESP32S2_FLASH_MODE_DIO + bool "Dual IO (DIO)" + + config ESP32S2_FLASH_MODE_DOUT + bool "Dual Output (DOUT)" + + config ESP32S2_FLASH_MODE_QIO + bool "Quad IO (QIO)" + + config ESP32S2_FLASH_MODE_QOUT + bool "Quad Output (QOUT)" + +endchoice # ESP32S2_FLASH_MODE + +choice ESP32S2_FLASH_FREQ + prompt "SPI FLASH frequency" + default ESP32S2_FLASH_FREQ_40M + ---help--- + SPI FLASH frequency + + config ESP32S2_FLASH_FREQ_80M + bool "80 MHz" + + config ESP32S2_FLASH_FREQ_40M + bool "40 MHz" + + config ESP32S2_FLASH_FREQ_26M + bool "26 MHz" + + config ESP32S2_FLASH_FREQ_20M + bool "20 MHz" + +endchoice # ESP32S2_FLASH_FREQ + +choice ESP32S2_DEFAULT_CPU_FREQ + prompt "CPU frequency" + default ESP32S2_DEFAULT_CPU_FREQ_240 + ---help--- + CPU frequency to be set on application startup. + + config ESP32S2_DEFAULT_CPU_FREQ_80 + bool "80 MHz" + config ESP32S2_DEFAULT_CPU_FREQ_160 + bool "160 MHz" + config ESP32S2_DEFAULT_CPU_FREQ_240 + bool "240 MHz" +endchoice # CPU frequency + +config ESP32S2_DEFAULT_CPU_FREQ_MHZ + int + default 80 if ESP32S2_DEFAULT_CPU_FREQ_80 + default 160 if ESP32S2_DEFAULT_CPU_FREQ_160 + default 240 if ESP32S2_DEFAULT_CPU_FREQ_240 + +choice + prompt "On-board Crystal Frequency" + default ESP32S2_XTAL_40MZ + +config ESP32S2_XTAL_40MZ + bool "40MHz" + +config ESP32S2_XTAL_26MHz + bool "26MHz" + +endchoice # On-board Crystal Frequency + +config ESP32S2_RT_TIMER + bool "Real-time Timer" + default n + +config ESP32S2_PARTITION + bool "ESP32S2 Partition" + default n + select ESP32S2_SPIFLASH + ---help--- + Decode esp-idf's partition file and initialize + partition by nuttx MTD. + +config ESP32S2_RUN_IRAM + bool "Run from IRAM" + default n + ---help--- + This loads all of NuttX inside IRAM. Used to test somewhat small + images that can fit entirely in IRAM. + +menu "ESP32-S2 Peripheral Selection" + +config ESP32S2_UART + bool + default n + +config ESP32S2_UART + bool + default n + +config ESP32S2_TIMER + bool + default n + +config ESP32S2_WDT + bool + default n + +config ESP32S2_BT + bool "Bluetooth" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_EFUSE + bool "EFUSE support" + default n + ---help--- + Enable ESP32S2 efuse support. + +config ESP32S2_I2C + bool + default n + +config ESP32S2_I2S0 + bool "I2S 0" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_LEDC + bool "LED PWM (LEDC)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_PCNT + bool "Pulse Count Module (PCNT)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_RMT + bool "Remote Control Module (RMT)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_RNG + bool "Random Number Generator (RNG)" + default n + select ARCH_HAVE_RNG + ---help--- + ESP32S2 supports a RNG that passed on Dieharder test suite. + +config ESP32S2_SPI + bool + default n + +config ESP32S2_SPIFLASH + bool "SPI Flash" + default n + select MTD + select MTD_BYTE_WRITE + select MTD_PARTITION + +config ESP32S2_SPI2 + bool "SPI 2" + default n + select ESP32S2_SPI + select ESP32S2_GPIO_IRQ + select SPI + +config ESP32S2_SPI3 + bool "SPI 3" + default n + select ESP32S2_SPI + select ESP32S2_GPIO_IRQ + select SPI + +config ESP32S2_SPIRAM + bool "SPI RAM Support" + default n + select ARCH_HAVE_HEAP2 + select XTENSA_IMEM_USE_SEPARATE_HEAP + +if ESP32S2_SPIRAM && SMP + +choice + prompt "How does SPIRAM share cache?" + default ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD + ---help--- + Selects the cache mode to CPU access the external memory. + + config ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD + bool "Pro CPU uses even 32 byte ranges, App uses odd ones" + config ESP32S2_MEMMAP_SPIRAM_CACHE_LOWHIGH + bool "Pro CPU uses low 2MB ranges, App uses high ones" +endchoice # CPU frequency + +endif + +config XTENSA_TIMER1 + bool "Xtensa Timer 1" + default n + +config XTENSA_TIMER2 + bool "Xtensa Timer 2" + default n + +config ESP32S2_TIMER0 + bool "64-bit Timer 0 (Group 0 Timer 0)" + default n + select ESP32S2_TIMER + ---help--- + Enables Timer + +config ESP32S2_TIMER1 + bool "64-bit Timer 1 (Group 0 Timer 1)" + default n + select ESP32S2_TIMER + ---help--- + Enables Timer + +config ESP32S2_TIMER2 + bool "64-bit Timer 2 (Group 1 Timer 0)" + default n + select ESP32S2_TIMER + ---help--- + Enables Timer + +config ESP32S2_TIMER3 + bool "64-bit Timer 3 (Group 1 Timer 1)" + default n + select ESP32S2_TIMER + ---help--- + Enables Timer + +config ESP32S2_MWDT0 + bool "Main System Watchdog Timer (Group 0)" + default n + select ESP32S2_WDT + ---help--- + Includes MWDT0. This watchdog timer is part of the Group 0 + timer submodule. + +config ESP32S2_MWDT1 + bool "Main System Watchdog Timer (Group 1)" + default n + select ESP32S2_WDT + ---help--- + Includes MWDT1. This watchdog timer is part of the Group 0 + timer submodule. + +config ESP32S2_RWDT + bool "RTC Watchdog Timer" + default n + select ESP32S2_WDT + ---help--- + Includes RWDT. This watchdog timer is from the RTC module. + When it is selected, if the developer sets it to reset on expiration + it will reset Main System and the RTC module. If you don't want + to have the RTC module reset, please, use the Timers' Module WDTs. + They will only reset Main System. + +config ESP32S2_UART0 + bool "UART 0" + default n + select ESP32S2_UART + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESP32S2_UART1 + bool "UART 1" + default n + select ESP32S2_UART + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + + +config ESP32S2_WIRELESS + bool "Wireless" + default n + select NET + select ARCH_PHY_INTERRUPT + select ESP32S2_RNG + select ESP32S2_RT_TIMER + select ESP32S2_TIMER0 + ---help--- + Enable Wireless support + +config ESP32S2_I2C0 + bool "I2C 0" + default n + select ESP32S2_I2C + +config ESP32S2_I2C1 + bool "I2C 1" + default n + select ESP32S2_I2C + +config ESP32S2_AES_ACCELERATOR + bool "AES Accelerator" + default n + +endmenu # ESP32S2 Peripheral Selection + +menu "Memory Configuration" + +config ESP32S2_BT_RESERVE_DRAM + int "Reserved BT DRAM" + default 0 + +config ESP32S2_TRACEMEM_RESERVE_DRAM + int "Reserved trace memory DRAM" + default 0 + +config ESP32S2_ULP_COPROC_RESERVE_MEM + int "Reserved ULP co-processor DRAM" + default 0 + +endmenu # Memory Configuration + +config ESP32S2_GPIO_IRQ + bool "GPIO pin interrupts" + ---help--- + Enable support for interrupting GPIO pins + +menu "UART configuration" + depends on ESP32S2_UART + +if ESP32S2_UART0 + +config ESP32S2_UART0_TXPIN + int "UART0 Tx Pin" + default 43 + range 0 46 + +config ESP32S2_UART0_RXPIN + int "UART0 Rx Pin" + default 44 + range 0 46 + +config ESP32S2_UART0_RTSPIN + int "UART0 RTS Pin" + depends on SERIAL_IFLOWCONTROL + default 16 + range 0 46 + +config ESP32S2_UART0_CTSPIN + int "UART0 CTS Pin" + depends on SERIAL_OFLOWCONTROL + default 15 + range 0 46 + +endif # ESP32S2_UART0 + +if ESP32S2_UART1 + +config ESP32S2_UART1_TXPIN + int "UART1 Tx Pin" + default 37 + range 0 46 + +config ESP32S2_UART1_RXPIN + int "UART1 Rx Pin" + default 38 + range 0 46 + +config ESP32S2_UART1_RTSPIN + int "UART1 RTS Pin" + depends on SERIAL_IFLOWCONTROL + default 35 + range 0 46 + +config ESP32S2_UART1_CTSPIN + int "UART1 CTS Pin" + depends on SERIAL_OFLOWCONTROL + default 36 + range 0 46 + +endif # ESP32S2_UART1 + +endmenu # UART configuration + +menu "I2C configuration" + depends on ESP32S2_I2C + +if ESP32S2_I2C0 + +config ESP32S2_I2C0_SCLPIN + int "I2C0 SCL Pin" + default 22 + range 0 39 + +config ESP32S2_I2C0_SDAPIN + int "I2C0 SDA Pin" + default 23 + range 0 39 + +endif # ESP32S2_I2C0 + +if ESP32S2_I2C1 + +config ESP32S2_I2C1_SCLPIN + int "I2C1 SCL Pin" + default 26 + range 0 39 + +config ESP32S2_I2C1_SDAPIN + int "I2C1 SDA Pin" + default 25 + range 0 39 + +endif # ESP32S2_I2C1 + +endmenu # I2C configuration + +menu "SPI configuration" + depends on ESP32S2_SPI + +config ESP32S2_SPI_SWCS + bool "SPI software CS" + default y + ---help--- + Use SPI software CS. + +config ESP32S2_SPI_UDCS + bool "User defined CS" + default n + depends on ESP32S2_SPI_SWCS + ---help--- + Use user defined CS. + +config ESP32S2_SPI2_DMA + bool "SPI2 use DMA" + default y + depends on ESP32S2_SPI2 + +config ESP32S2_SPI3_DMA + bool "SPI3 use DMA" + default y + depends on ESP32S2_SPI3 + +config SPI_DMADESC_NUM + int "SPI master DMA description number" + default 2 + +config SPI_SLAVE_BUFSIZE + int "SPI slave buffer size" + default 2048 + depends on SPI_SLAVE + +config ESP32S2_SPI_DMATHRESHOLD + int "SPI DMA threshold" + default 64 + depends on ESP32S2_SPI2_DMA || ESP32S2_SPI3_DMA + ---help--- + When SPI DMA is enabled, DMA transfers whose size are below the + defined threshold will be performed by polling logic. + +if ESP32S2_SPI2 + +config ESP32S2_SPI2_CSPIN + int "SPI2 CS Pin" + default 15 + range 0 39 + +config ESP32S2_SPI2_CLKPIN + int "SPI2 CLK Pin" + default 14 + range 0 39 + +config ESP32S2_SPI2_MOSIPIN + int "SPI2 MOSI Pin" + default 13 + range 0 39 + +config ESP32S2_SPI2_MISOPIN + int "SPI2 MISO Pin" + default 12 + range 0 39 + +endif # ESP32S2_SPI2 + +if ESP32S2_SPI3 + +config ESP32S2_SPI3_CSPIN + int "SPI3 CS Pin" + default 5 + range 0 39 + +config ESP32S2_SPI3_CLKPIN + int "SPI3 CLK Pin" + default 18 + range 0 39 + +config ESP32S2_SPI3_MOSIPIN + int "SPI3 MOSI Pin" + default 23 + range 0 39 + +config ESP32S2_SPI3_MISOPIN + int "SPI3 MISO Pin" + default 19 + range 0 39 + +endif # ESP32S2_SPI3 + +endmenu # ESP32S2_SPI + +menu "SPI Flash configuration" + depends on ESP32S2_SPIFLASH + +config ESP32S2_MTD_OFFSET + hex "MTD base address in SPI Flash" + default 0x180000 + ---help--- + MTD base address in SPI Flash. + +config ESP32S2_MTD_SIZE + hex "MTD size in SPI Flash" + default 0x100000 + ---help--- + MTD size in SPI Flash. + +config ESP32S2_SPIFLASH_DEBUG + bool "Debug SPI Flash" + default n + depends on DEBUG_FS_INFO + ---help--- + Enable this option, read and write of SPI Flash + will show input arguments and result. + +endmenu # ESP32S2_SPIFLASH + +menu "SPI RAM Config" + depends on ESP32S2_SPIRAM + +choice ESP32S2_SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + default ESP32S2_SPIRAM_TYPE_AUTO + +config ESP32S2_SPIRAM_TYPE_AUTO + bool "Auto-detect" + +config ESP32S2_SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + +config ESP32S2_SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64 or LY68L6400" +endchoice #ESP32S2_SPIRAM_TYPE + +config ESP32S2_SPIRAM_SIZE + int + default -1 if ESP32S2_SPIRAM_TYPE_AUTO + default 4194304 if ESP32S2_SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if ESP32S2_SPIRAM_TYPE_ESPPSRAM64 + default 0 + +choice ESP32S2_SPIRAM_SPEED + prompt "Set RAM clock speed" + default ESP32S2_SPIRAM_SPEED_40M + ---help--- + Select the speed for the SPI RAM chip. + +config ESP32S2_SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config ESP32S2_SPIRAM_SPEED_80M + bool "80MHz clock speed" + +endchoice # ESP32S2_SPIRAM_SPEED + +config ESP32S2_SPIRAM_BOOT_INIT + bool "Initialize SPI RAM during startup" + depends on ESP32S2_SPIRAM + default "y" + ---help--- + If this is enabled, the SPI RAM will be enabled during initial + boot. Unless you have specific requirements, you'll want to leave + this enabled so memory allocated during boot-up can also be + placed in SPI RAM. + +config ESP32S2_SPIRAM_IGNORE_NOTFOUND + bool "Ignore PSRAM when not found" + default "n" + depends on ESP32S2_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA + ---help--- + Normally, if psram initialization is enabled during compile time + but not found at runtime, it is seen as an error making the CPU + panic. If this is enabled, booting will complete but no PSRAM + will be available. + +config ESP32S2_SPIRAM_2T_MODE + bool "Enable SPI PSRAM 2T mode" + depends on ESP32S2_SPIRAM + default "n" + ---help--- + Enable this option to fix single bit errors inside 64Mbit PSRAM. + Some 64Mbit PSRAM chips have a hardware issue in the RAM which + causes bit errors at multiple fixed bit positions. + Note: If this option is enabled, the 64Mbit PSRAM chip will appear + to be 32Mbit in size. + Applications will not be affected unless the use the esp_himem + APIs, which are not supported in 2T mode. + +config ESP32S2_SPIRAM_BANKSWITCH_ENABLE + bool "Enable bank switching for >4MiB external RAM" + default y + ---help--- + The ESP32S2 only supports 4MiB of external RAM in its address + space. The hardware does support larger memories, but these + have to be bank-switched in and out of this address space. + Enabling this allows you to reserve some MMU pages for this, + which allows the use of the esp_himem api to manage these + banks. + #Note that this is limited to 62 banks, as + #esp_spiram_writeback_cache needs some kind of mapping of + #some banks below that mark to work. We cannot at this + #moment guarantee this to exist when himem is enabled. + If spiram 2T mode is enabled, the size of 64Mbit psram will + be changed as 32Mbit, so himem will be unusable. + +config SPIRAM_BANKSWITCH_RESERVE + int "Amount of 32K pages to reserve for bank switching" + depends on ESP32S2_SPIRAM_BANKSWITCH_ENABLE + default 8 + range 1 62 + ---help--- + Select the amount of banks reserved for bank switching. Note + that the amount of RAM allocatable with malloc will decrease + by 32K for each page reserved here. + Note that this reservation is only actually done if your + program actually uses the himem API. Without any himem + calls, the reservation is not done and the original amount + of memory will be available. + +endmenu #SPI RAM Config + +menu "WiFi configuration" + depends on ESP32S2_WIRELESS + +choice + prompt "ESP32-S2 WiFi mode" + default ESP32S2_WIFI_STATION + +config ESP32S2_WIFI_STATION + bool "Station mode" + +config ESP32S2_WIFI_SOFTAP + bool "SoftAP mode" + +config ESP32S2_WIFI_STATION_SOFTAP_COEXISTENCE + bool "Station + SoftAP coexistence" + +endchoice # ESP32S2 WiFi mode + +config ESP32S2_WIFI_STATIC_RXBUF_NUM + int "WiFi static RX buffer number" + default 10 + +config ESP32S2_WIFI_DYNAMIC_RXBUF_NUM + int "WiFi dynamic RX buffer number" + default 32 + +config ESP32S2_WIFI_DYNAMIC_TXBUF_NUM + int "WiFi dynamic TX buffer number" + default 32 + +config ESP32S2_WIFI_TX_AMPDU + bool "WiFi TX AMPDU" + default y + +config ESP32S2_WIFI_RX_AMPDU + bool "WiFi RX AMPDU" + default y + +config ESP32S2_WIFI_RXBA_AMPDU_WZ + int "WiFi RX BA AMPDU windown size" + default 6 + +config ESP32S2_WLAN_PKTBUF_NUM + int "WLAN netcard packet buffer number per netcard" + default 16 + +config ESP32S2_WIFI_CONNECT_TIMEOUT + int "Connect timeout by second" + default 10 + ---help--- + Max waiting time of connecting to AP. + +config ESP32S2_WIFI_SCAN_RESULT_SIZE + int "Scan result buffer" + default 4096 + ---help--- + Maximum scan result buffer size. + +config ESP32S2_WIFI_SAVE_PARAM + bool "Save WiFi Parameters" + default n + ---help--- + If you enable this option, WiFi adapter parameters will be saved + into the file system instead of computing them each time. + + These parameters mainly contains: + - SSID + - Password + - BSSID + - PMK(compute when connecting) + - Author mode + - MAC address + - WiFi hardware configuration parameters + +config ESP32S2_WIFI_FS_MOUNTPT + string "Save WiFi Parameters" + default "/mnt/esp/wifi" + depends on ESP32S2_WIFI_SAVE_PARAM + ---help--- + Mount point of WiFi storage file system. + +endmenu # ESP32S2_WIRELESS + +menu "Real-Time Timer" + depends on ESP32S2_RT_TIMER + +config ESP32S2_RT_TIMER_TASK_NAME + string "Timer task name" + default "rt_timer" + +config ESP32S2_RT_TIMER_TASK_PRIORITY + int "Timer task priority" + default 223 # Lower than high priority workqueue + +config ESP32S2_RT_TIMER_TASK_STACK_SIZE + int "Timer task stack size" + default 2048 + +endmenu # Real-Time Timer + +if ESP32S2_TIMER +menu "Timer/counter Configuration" + +config ESP32S2_ONESHOT + bool "One-shot wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +endmenu # Timer/counter Configuration +endif # ESP32S2_TIMER + +menu "Partition Configuration" + depends on ESP32S2_PARTITION + +config ESP32S2_PARTITION_OFFSET + hex "Partition offset" + default "0x8000" + +config ESP32S2_PARTITION_MOUNT + string "Partition mount point" + default "/dev/esp/partition/" + +endmenu # ESP32S2_PARTITION + +menu "AES accelerate" + depends on ESP32S2_AES_ACCELERATOR + +config ESP32S2_AES_ACCELERATOR_TEST + bool "AES driver test" + default n + +endmenu # ESP32S2_AES_ACCELERATOR + +endif # ARCH_CHIP_ESP32S2 diff --git a/arch/xtensa/src/esp32s2/Make.defs b/arch/xtensa/src/esp32s2/Make.defs new file mode 100644 index 00000000000..7074f98d367 --- /dev/null +++ b/arch/xtensa/src/esp32s2/Make.defs @@ -0,0 +1,81 @@ +############################################################################ +# arch/xtensa/src/esp32s2/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# The start-up, "head", file. May be either a .S or a .c file. + +HEAD_ASRC = xtensa_vectors.S xtensa_window_vector.S xtensa_windowspill.S +HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S +HEAD_CSRC = esp32s2_start.c + +# Common XTENSA files (arch/xtensa/src/common) + +CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S xtensa_panic.S +CMN_ASRCS += xtensa_sigtramp.S + +CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c +CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c +CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c +CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c +CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c +CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c +CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c +CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c +CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c +CMN_CSRCS += esp32s2_systemreset.c + +# Configuration-dependent common XTENSA files + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) + CMN_CSRCS += esp32s2_idle.c +endif + +ifeq ($(CONFIG_DEBUG_ALERT),y) + CMN_CSRCS += xtensa_dumpstate.c +endif + +ifeq ($(CONFIG_XTENSA_DUMPBT_ON_ASSERT),y) + CMN_ASRCS += xtensa_backtrace.S +endif + +ifeq ($(CONFIG_SPINLOCK),y) + CMN_CSRCS += xtensa_testset.c +endif + +ifeq ($(CONFIG_STACK_COLORATION),y) + CMN_CSRCS += xtensa_checkstack.c +endif + +ifeq ($(CONFIG_FS_HOSTFS),y) + CMN_ASRCS += xtensa_simcall.S + CMN_CSRCS += xtensa_hostfs.c +endif + +# Required ESP32S2 files (arch/xtensa/src/lx7) + +CHIP_CSRCS = esp32s2_allocateheap.c esp32s2_clockconfig.c esp32s2_cpuint.c +CHIP_CSRCS += esp32s2_gpio.c esp32s2_intdecode.c esp32s2_irq.c esp32s2_region.c +CHIP_CSRCS += esp32s2_timerisr.c esp32s2_user.c esp32s2_lowputc.c + +# Configuration-dependent ESP32S2 files + +ifeq ($(CONFIG_ESP32S2_UART),y) +CMN_CSRCS += esp32s2_serial.c +endif + diff --git a/arch/xtensa/src/esp32s2/chip_macros.h b/arch/xtensa/src/esp32s2/chip_macros.h new file mode 100644 index 00000000000..5684e7a5a74 --- /dev/null +++ b/arch/xtensa/src/esp32s2/chip_macros.h @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/chip_macros.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H +#define __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is the name of the section containing the Xtensa low level handlers + * that is used by the board linker scripts. + */ + +#define HANDLER_SECTION .iram1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +/* Macro to get the current core ID. Only uses the reg given as an argument. + * Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO + * processor and 0xabab on the APP CPU. We distinguish between the two by + * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor. + */ + + .macro getcoreid reg + rsr.prid \reg + bbci \reg, 1, 1f + movi \reg, 1 + j 2f +1: + movi \reg, 0 +2: + .endm + +#endif /* __ASSEMBLY */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H */ diff --git a/arch/xtensa/src/esp32s2/chip_memory.h b/arch/xtensa/src/esp32s2/chip_memory.h new file mode 100644 index 00000000000..f418427b7ee --- /dev/null +++ b/arch/xtensa/src/esp32s2/chip_memory.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/chip_memory.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H +#define __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/esp32s2_soc.h" + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: xtensa_sp_sane + ****************************************************************************/ + +static inline bool xtensa_sp_sane(uint32_t sp) +{ + return (esp32s2_sp_dram(sp) && ((sp & 0x0f) == 0)); +} + +/**************************************************************************** + * Name: xtensa_ptr_extram + ****************************************************************************/ + +static inline bool xtensa_ptr_exec(const void *p) +{ + return esp32s2_ptr_exec(p); +} + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H */ + diff --git a/arch/xtensa/src/esp32s2/esp32s2_allocateheap.c b/arch/xtensa/src/esp32s2/esp32s2_allocateheap.c new file mode 100644 index 00000000000..471bd93363a --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_allocateheap.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + extern uint32_t *_dram0_rtos_reserved_start; + + board_autoled_on(LED_HEAPALLOCATE); + + *heap_start = (FAR void *)&_sheap; + *heap_size = (size_t)((uintptr_t)&_dram0_rtos_reserved_start - + (uintptr_t)&_sheap); +} + +/**************************************************************************** + * Name: xtensa_add_region + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void xtensa_add_region(void) +{ +} +#endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c new file mode 100644 index 00000000000..a8a4a7cb3e3 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c @@ -0,0 +1,324 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "xtensa.h" +#include "xtensa_attr.h" +#include "hardware/esp32s2_soc.h" +#include "hardware/esp32s2_uart.h" +#include "hardware/esp32s2_rtccntl.h" +#include "hardware/esp32s2_system.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef CONFIG_ESP_CONSOLE_UART_NUM +#define CONFIG_ESP_CONSOLE_UART_NUM 0 +#endif + +#define DEFAULT_CPU_FREQ 80 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum cpu_freq_e +{ + CPU_80M = 0, + CPU_160M = 1, + CPU_240M = 2, +}; + +enum cpu_clksrc_e +{ + XTAL_CLK, + PLL_CLK, + RTC8M_CLK, + APLL_CLK +}; + +enum pll_freq_e +{ + PLL_320, + PLL_480 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_cpuclksrc + * + * Description: + * Select a clock source for CPU clock. + * + * Input Parameters: + * src - Any source from cpu_clksrc_e. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32s2_cpuclksrc(enum cpu_clksrc_e src) +{ + uint32_t value; + value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL); + modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value); +} + +/**************************************************************************** + * Name: esp32s2_cpudiv + * + * Description: + * Select a divider for the CPU clk. + * NOTE: The divider is not necessarily the real divisor. See TRM for the + * equivalences. + * + * Input Parameters: + * divider - A value between 0 to 2. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32s2_cpudiv(uint8_t divider) +{ + uint32_t value; + value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL); + modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value); +} + +/**************************************************************************** + * Name: esp32s2_pllfreqsel + * + * Description: + * Select the PLL frequency. + * + * Input Parameters: + * freq - Any clock from enum pll_freq_e + * + * Returned Value: + * None + ****************************************************************************/ + +static inline void esp32s2_pllfreqsel(enum pll_freq_e freq) +{ + uint32_t value; + value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL); + modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value); +} + +/**************************************************************************** + * Name: esp32s2_uart_tx_wait_idle + * + * Description: + * Wait until uart tx full empty and the last char send ok. + * + * Input Parameters: + * uart_no - 0 for UART0, 1 for UART1, 2 for UART2 + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32s2_uart_tx_wait_idle(uint8_t uart_no) +{ + uint32_t status; + do + { + status = getreg32(UART_STATUS_REG(uart_no)); + + /* tx count is non-zero */ + } + while ((status & UART_TXFIFO_CNT_M) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +extern uint32_t g_ticks_per_us; + +/**************************************************************************** + * Name: esp32s2_update_cpu_freq + * + * Description: + * Set the real CPU ticks per us to the ets, so that ets_delay_us + * will be accurate. Call this function when CPU frequency is changed. + * + * Input Parameters: + * ticks_per_us - CPU ticks per us + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_update_cpu_freq(uint32_t ticks_per_us) +{ + /* Update scale factors used by esp_rom_delay_us */ + + g_ticks_per_us = ticks_per_us; +} + +/**************************************************************************** + * Name: esp32s2_set_cpu_freq + * + * Description: + * Switch to one of PLL-based frequencies. + * + * Input Parameters: + * cpu_freq_mhz - Target CPU frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_set_cpu_freq(int cpu_freq_mhz) +{ + uint32_t dbias; + uint32_t value; + switch (cpu_freq_mhz) + { + case 80: + /* 80 MHz is obtained from the 480 MHz PLL. + * In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz + * with a 6 divider and set the source clock as PLL_CLK. + */ + + dbias = DIG_DBIAS_80M_160M; + esp32s2_cpudiv(0); + break; + + case 160: + /* 160 MHz is obtained from the 480 MHz PLL. + * In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz + * with a 3 divider and set the source clock as PLL_CLK. + */ + + dbias = DIG_DBIAS_80M_160M; + esp32s2_cpudiv(1); + break; + + case 240: + /* 160 MHz is obtained from the 480 MHz PLL. + * In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz + * with a 2 divider and set the source clock as PLL_CLK. + */ + + dbias = DIG_DBIAS_240M; + esp32s2_cpudiv(2); + break; + + default: + + /* Unsupported clock config. */ + + return; + } + + value = (((80 * MHZ) >> 12) & UINT16_MAX) | + ((((80 * MHZ) >> 12) & UINT16_MAX) << 16); + esp32s2_pllfreqsel(PLL_480); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); + esp32s2_cpuclksrc(PLL_CLK); + putreg32(value, RTC_APB_FREQ_REG); + esp32s2_update_cpu_freq(cpu_freq_mhz); +} + +/**************************************************************************** + * Name: esp32s2_clockconfig + * + * Description: + * Called to initialize the ESP32S2. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void esp32s2_clockconfig(void) +{ + /* Wait for the TX FIFO to unload data */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) + esp32s2_uart_tx_wait_idle(0); +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) + esp32s2_uart_tx_wait_idle(1); +#endif + + /* Configure the CPU frequency */ + + esp32s2_set_cpu_freq(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ); +} + +/**************************************************************************** + * Name: esp_clk_cpu_freq + * + * Description: + * Get CPU frequency + * + * Input Parameters: + * None + * + * Returned Value: + * CPU frequency + * + ****************************************************************************/ + +int IRAM_ATTR esp_clk_cpu_freq(void) +{ + return g_ticks_per_us * MHZ; +} + +/**************************************************************************** + * Name: esp_clk_apb_freq + * + * Description: + * Return current APB clock frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * APB clock frequency, in Hz + * + ****************************************************************************/ + +int IRAM_ATTR esp_clk_apb_freq(void) +{ + return MIN(g_ticks_per_us, 80) * MHZ; +} + diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h new file mode 100644 index 00000000000..a0f05b109ba --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_update_cpu_freq + * + * Description: + * Set the real CPU ticks per us to the ets, so that ets_delay_us + * will be accurate. Call this function when CPU frequency is changed. + * + * Input Parameters: + * ticks_per_us - CPU ticks per us + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_update_cpu_freq(uint32_t ticks_per_us); + +/**************************************************************************** + * Name: esp32s2_set_cpu_freq + * + * Description: + * Switch to one of PLL-based frequencies. + * Current frequency can be XTAL or PLL. + * + * Input Parameters: + * cpu_freq_mhz - new CPU frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_set_cpu_freq(int cpu_freq_mhz); + +/**************************************************************************** + * Name: esp32s2_clockconfig + * + * Description: + * Called to initialize the ESP32S2. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void esp32s2_clockconfig(void); + +/**************************************************************************** + * Name: esp_clk_cpu_freq + * + * Description: + * Get CPU frequency + * + * Input Parameters: + * None + * + * Returned Value: + * CPU frequency + * + ****************************************************************************/ + +int esp_clk_cpu_freq(void); + +/**************************************************************************** + * Name: esp_clk_apb_freq + * + * Description: + * Return current APB clock frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * APB clock frequency, in Hz + * + ****************************************************************************/ + +int esp_clk_apb_freq(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_config.h b/arch/xtensa/src/esp32s2/esp32s2_config.h new file mode 100644 index 00000000000..c8097017b58 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_config.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_config.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UARTs ********************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#ifdef CONFIG_ESP32S2_UART +# define HAVE_UART_DEVICE 1 +#endif + +/* Serial Console ***********************************************************/ + +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn. n E {0,1} + */ + +#undef HAVE_SERIAL_CONSOLE +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32S2_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32S2_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +/* SPI **********************************************************************/ + +/* Don't enable SPI peripherals not supported by the chip. */ + +#if ESP32S2_NSPI < 1 +# undef CONFIG_ESP32S2_SPI0 +# undef CONFIG_ESP32S2_SPI1 +# undef CONFIG_ESP32S2_SPI2 +# undef CONFIG_ESP32S2_SPI3 +#elif ESP32S2_NSPI < 2 +# undef CONFIG_ESP32S2_SPI1 +# undef CONFIG_ESP32S2_SPI2 +# undef CONFIG_ESP32S2_SPI3 +#elif ESP32S2_NSPI < 3 +# undef CONFIG_ESP32S2_SPI2 +# undef CONFIG_ESP32S2_SPI3 +#elif ESP32S2_NSPI < 4 +# undef CONFIG_ESP32S2_SPI3 +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_cpuint.c b/arch/xtensa/src/esp32s2/esp32s2_cpuint.c new file mode 100644 index 00000000000..ce1c3447b35 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_cpuint.c @@ -0,0 +1,587 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_cpuint.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "esp32s2_cpuint.h" +#include "hardware/esp32s2_interrupt.h" +#include "xtensa.h" + +#include "sched/sched.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Mapping Peripheral IDs to map register addresses + * + * PERIPHERAL ID INTERRUPT_PRO_X_MAP + * MNEMONIC REGISTER OFFSET + * ESP32S2_PERIPH_MAC_INTR 0x0000 + * ESP32S2_PERIPH_MAC_NMI 0x0004 + * ESP32S2_PERIPH_PWR_INTR 0x0008 + * ESP32S2_PERIPH_BB_INT 0x000C + * ESP32S2_PERIPH_BT_MAC_INT 0x0010 + * ESP32S2_PERIPH_BT_BB_INT 0x0014 + * ESP32S2_PERIPH_BT_BB_NMI 0x0018 + * ESP32S2_PERIPH_RWBT_IRQ 0x001C + * ESP32S2_PERIPH_RWBLE_IRQ 0x0020 + * ESP32S2_PERIPH_RWBT_NMI 0x0024 + * ESP32S2_PERIPH_RWBLE_NMI 0x0028 + * ESP32S2_PERIPH_SLC0_INTR 0x002C + * ESP32S2_PERIPH_SLC1_INTR 0x0030 + * ESP32S2_PERIPH_UHCI0_INTR 0x0034 + * ESP32S2_PERIPH_UHCI1_INTR 0x0038 + * ESP32S2_PERIPH_TG_T0_LEVEL_INT 0x003C + * ESP32S2_PERIPH_TG_T1_LEVEL_INT 0x0040 + * ESP32S2_PERIPH_TG_WDT_LEVEL_INT 0x0044 + * ESP32S2_PERIPH_TG_LACT_LEVEL_INT 0x0048 + * ESP32S2_PERIPH_TG1_T0_LEVEL_INT 0x004C + * ESP32S2_PERIPH_TG1_T1_LEVEL_INT 0x0050 + * ESP32S2_PERIPH_TG1_WDT_LEVEL_INT 0x0054 + * ESP32S2_PERIPH_TG1_LACT_LEVEL_INT 0x0058 + * ESP32S2_PERIPH_GPIO_INTERRUPT_PRO 0x005C + * ESP32S2_PERIPH_GPIO_INTERRUPT_PRO_NMI 0x0060 + * ESP32S2_PERIPH_GPIO_INTERRUPT_APP 0x0064 + * ESP32S2_PERIPH_GPIO_INTERRUPT_APP_NMI 0x0068 + * ESP32S2_PERIPH_DEDICATED_GPIO_IN_INTR 0x006C + * ESP32S2_PERIPH_CPU_INTR_FROM_CPU_0 0x0070 + * ESP32S2_PERIPH_CPU_INTR_FROM_CPU_1 0x0074 + * ESP32S2_PERIPH_CPU_INTR_FROM_CPU_2 0x0078 + * ESP32S2_PERIPH_CPU_INTR_FROM_CPU_3 0x007C + * ESP32S2_PERIPH_SPI_INTR_1 0x0080 + * ESP32S2_PERIPH_SPI_INTR_2 0x0084 + * ESP32S2_PERIPH_SPI_INTR_3 0x0088 + * ESP32S2_PERIPH_I2S0_INT 0x008C + * ESP32S2_PERIPH_I2S1_INT 0x0090 + * ESP32S2_PERIPH_UART_INT 0x0094 + * ESP32S2_PERIPH_UART1_INT 0x0098 + * ESP32S2_PERIPH_UART2_INT 0x009C + * ESP32S2_PERIPH_SDIO_HOST_INTERRUPT 0x00A0 + * ESP32S2_PERIPH_PWM0_INTR 0x00A4 + * ESP32S2_PERIPH_PWM1_INTR 0x00A8 + * ESP32S2_PERIPH_PWM2_INTR 0x00AC + * ESP32S2_PERIPH_PWM3_INTR 0x00B0 + * ESP32S2_PERIPH_LEDC_INTR 0x00B4 + * ESP32S2_PERIPH_EFUSE_INT 0x00B8 + * ESP32S2_PERIPH_CAN_INT 0x00BC + * ESP32S2_PERIPH_USB_INT 0x00C0 + * ESP32S2_PERIPH_RTC_CORE_INTR 0x00C4 + * ESP32S2_PERIPH_RMT_INTR 0x00C8 + * ESP32S2_PERIPH_PCNT_INTR 0x00CC + * ESP32S2_PERIPH_I2C_EXT0_INTR 0x00D0 + * ESP32S2_PERIPH_I2C_EXT1_INTR 0x00D4 + * ESP32S2_PERIPH_RSA_INTR 0x00D8 + * ESP32S2_PERIPH_SHA_INTR 0x00DC + * ESP32S2_PERIPH_AES_INTR 0x00E0 + * ESP32S2_PERIPH_SPI2_DMA_INT 0x00E4 + * ESP32S2_PERIPH_SPI3_DMA_INT 0x00E8 + * ESP32S2_PERIPH_WDG_INT 0x00EC + * ESP32S2_PERIPH_TIMER_INT1 0x00F0 + * ESP32S2_PERIPH_TIMER_INT2 0x00F4 + * ESP32S2_PERIPH_TG_T0_EDGE_INT 0x00F8 + * ESP32S2_PERIPH_TG_T1_EDGE_INT 0x00FC + * ESP32S2_PERIPH_TG_WDT_EDGE_INT 0x0100 + * ESP32S2_PERIPH_TG_LACT_EDGE_INT 0x0104 + * ESP32S2_PERIPH_TG1_T0_EDGE_INT 0x0108 + * ESP32S2_PERIPH_TG1_T1_EDGE_INT 0x010C + * ESP32S2_PERIPH_TG1_WDT_EDGE_INT 0x0110 + * ESP32S2_PERIPH_TG1_LACT_EDGE_INT 0x0114 + * ESP32S2_PERIPH_CACHE_IA_INT 0x0118 + * ESP32S2_PERIPH_SYSTIMER_TARGET0_INT 0x011C + * ESP32S2_PERIPH_SYSTIMER_TARGET1_INT 0x0120 + * ESP32S2_PERIPH_SYSTIMER_TARGET2 0x0124 + * ESP32S2_PERIPH_ASSIST_DEBUG_INTR 0x0128 + * ESP32S2_PERIPH_PMS_PRO_IRAM0_ILG 0x012C + * ESP32S2_PERIPH_PMS_PRO_DRAM0_ILG 0x0130 + * ESP32S2_PERIPH_PMS_PRO_DPORT_ILG 0x0134 + * ESP32S2_PERIPH_PMS_PRO_AHB_ILG 0x0138 + * ESP32S2_PERIPH_PMS_PRO_CACHE_ILG 0x013C + * ESP32S2_PERIPH_PMS_DMA_APB_I_ILG 0x0140 + * ESP32S2_PERIPH_PMS_DMA_RX_I_ILG 0x0144 + * ESP32S2_PERIPH_PMS_DMA_TX_I_ILG 0x0148 + * ESP32S2_PERIPH_SPI_MEM_REJECT_INTR 0x014C + * ESP32S2_PERIPH_DMA_COPY_INTR 0x0150 + * ESP32S2_PERIPH_SPI4_DMA_INT 0x0154 + * ESP32S2_PERIPH_SPI_INTR_4 0x0158 + * ESP32S2_PERIPH_DCACHE_PRELOAD_INT 0x015C + * ESP32S2_PERIPH_ICACHE_PRELOAD_INT 0x0160 + * ESP32S2_PERIPH_APB_ADC_INT 0x0164 + * ESP32S2_PERIPH_CRYPTO_DMA_INT 0x0168 + * ESP32S2_PERIPH_CPU_PERI_ERROR_INT 0x016C + * ESP32S2_PERIPH_APB_PERI_ERROR_INT 0x0170 + * ESP32S2_PERIPH_DCACHE_SYNC_INT 0x0174 + * ESP32S2_PERIPH_ICACHE_SYNC_INT 0x0178 + * ESP32S2_PERIPH_NMI 0x0188 + */ + +#define INTERRUPT_PRO_X_MAP_REG(n) (DR_REG_INTERRUPT_BASE + ((n) << 2)) + +/* CPU interrupts can be detached from any peripheral source by setting the + * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). + */ + +#define NO_CPUINT ESP32S2_CPUINT_TIMER0 + +/* Priority range is 1-5 */ + +#define ESP32S2_MIN_PRIORITY 1 +#define ESP32S2_MAX_PRIORITY 5 +#define ESP32S2_PRIO_INDEX(p) ((p) - ESP32S2_MIN_PRIORITY) + +#ifdef CONFIG_ESP32S2_WIRELESS +# define ESP32S2_WIRELESS_RESERVE_INT (1 << ESP32S2_CPUINT_MAC) +#else +# define ESP32S2_WIRELESS_RESERVE_INT 0 +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ + +uint8_t g_cpu0_intmap[ESP32S2_NCPUINTS]; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* g_intenable[] is a shadow copy of the CPU INTENABLE register + * content. + */ + +static uint32_t g_intenable[1]; + +/* Bitsets for free, unallocated CPU interrupts available to peripheral + * devices. + */ + +static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET & + (~ESP32S2_WIRELESS_RESERVE_INT); + +/* Bitsets for each interrupt priority 1-5 */ + +static const uint32_t g_priority[5] = +{ + ESP32S2_INTPRI1_MASK, + ESP32S2_INTPRI2_MASK, + ESP32S2_INTPRI3_MASK, + ESP32S2_INTPRI4_MASK, + ESP32S2_INTPRI5_MASK +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_disable_all + * + * Description: + * Disable all CPU interrupts. + ****************************************************************************/ + +static inline void xtensa_disable_all(void) +{ + __asm__ __volatile__ + ( + "movi a2, 0\n" + "xsr a2, INTENABLE\n" + : : : "a2" + ); +} + +/**************************************************************************** + * Name: esp32s2_alloc_cpuint + * + * Description: + * Allocate a CPU interrupt for a peripheral device. This function will + * not allocate any of the pre-allocated CPU interrupts for internal + * devices. This current implementation is not supporting multiple + * peripheral interrupts maped to a single CPU interrupt. + * + * Input Parameters: + * intmask - Mask of candidate CPU interrupts. The CPU interrupt will be + * be allocated from free interrupts within this set. + * + * Returned Value: + * On success, the first available CPU interrupt accordingly to the passed + * intmask. If no one is available return -ENOMEM. + * + ****************************************************************************/ + +static int esp32s2_alloc_cpuint(uint32_t intmask) +{ + irqstate_t flags; + uint32_t *freeints; + uint32_t bitmask; + uint32_t intset; + int cpuint; + int ret = -ENOMEM; + + /* Check if there are CPU interrupts with the requested properties + * available. + */ + + flags = enter_critical_section(); + + freeints = &g_cpu0_freeints; + + intset = *freeints & intmask; + if (intset != 0) + { + /* Skip over initial unavailable CPU interrupts quickly in groups + * of 8 interrupt until find the first slot with the required + * CPU interrupt set. + */ + + for (cpuint = 0, bitmask = 0xff; + cpuint <= ESP32S2_CPUINT_MAX && (intset & bitmask) == 0; + cpuint += 8, bitmask <<= 8); + + /* Search for an unallocated CPU interrupt number in the remaining + * intset. + */ + + for (; cpuint <= ESP32S2_CPUINT_MAX; cpuint++) + { + /* If the bit corresponding to the CPU interrupt is '1', then + * that CPU interrupt is available. + */ + + bitmask = (1ul << cpuint); + if ((intset & bitmask) != 0) + { + /* Got it! + * Update the available CPU interrupts mask + * and return the cpuint. + */ + + *freeints &= ~bitmask; + ret = cpuint; + break; + } + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_cpuint_initialize + * + * Description: + * Initialize CPU interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp32s2_cpuint_initialize(void) +{ + uintptr_t regaddr; + uint8_t *intmap; + int i; + + /* Disable all CPU interrupts on this CPU */ + + xtensa_disable_all(); + + /* Detach all peripheral sources PRO CPU interrupts */ + + for (i = 0; i < ESP32S2_NPERIPHERALS; i++) + { + regaddr = INTERRUPT_PRO_X_MAP_REG(i); + + putreg32(NO_CPUINT, regaddr); + } + + /* Initialize CPU interrupt-to-IRQ mapping table */ + + intmap = g_cpu0_intmap; + + /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ + + memset(intmap, CPUINT_UNASSIGNED, ESP32S2_NCPUINTS); + + /* Special case the 6 internal interrupts. + * + * CPU interrupt bit IRQ number + * --------------------------- --------------------- + * ESP32S2_CPUINT_MAC 0 ESP32S2_IRQ_MAC 4 + * ESP32S2_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0 + * ESP32S2_CPUINT_SOFTWARE0 7 Not yet defined + * ESP32S2_CPUINT_PROFILING 11 Not yet defined + * ESP32S2_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1 + * ESP32S2_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2 + * ESP32S2_CPUINT_SOFTWARE1 29 Not yet defined + */ + + intmap[ESP32S2_CPUINT_TIMER0] = XTENSA_IRQ_TIMER0; + intmap[ESP32S2_CPUINT_TIMER1] = XTENSA_IRQ_TIMER1; + intmap[ESP32S2_CPUINT_TIMER2] = XTENSA_IRQ_TIMER2; + + /* Reserve CPU interrupt for some special drivers */ + +#ifdef CONFIG_ESP32S2_WIRELESS + intmap[ESP32S2_CPUINT_MAC] = ESP32S2_IRQ_MAC; +#endif + + return OK; +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the CPU interrupt specified by 'cpuint'. + * + * Input Parameters: + * cpuint - The CPU interrupt to disable. + * + ****************************************************************************/ + +void up_disable_irq(int cpuint) +{ + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); + + xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint)); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the CPU interrupt specified by 'cpuint'. + * + * Input Parameters: + * cpuint - The CPU interrupt to disable. + * + ****************************************************************************/ + +void up_enable_irq(int cpuint) +{ + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); + + xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint)); +} + +/**************************************************************************** + * Name: esp32s2_alloc_levelint + * + * Description: + * Allocate a level CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * + * Returned Value: + * On success, the allocated level-sensitive, CPU interrupt number is + * returned. A negated errno is returned on failure. The only possible + * failure is that all level-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32s2_alloc_levelint(int priority) +{ + uint32_t intmask; + + DEBUGASSERT(priority >= ESP32S2_MIN_PRIORITY && + priority <= ESP32S2_MAX_PRIORITY); + + /* Check if there are any level CPU interrupts available at the requested + * interrupt priority. + */ + + intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET; + return esp32s2_alloc_cpuint(intmask); +} + +/**************************************************************************** + * Name: esp32s2_alloc_edgeint + * + * Description: + * Allocate an edge CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * + * Returned Value: + * On success, the allocated edge-sensitive, CPU interrupt number is + * returned. A negated errno is returned on failure. The only possible + * failure is that all edge-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32s2_alloc_edgeint(int priority) +{ + uint32_t intmask; + + DEBUGASSERT(priority >= ESP32S2_MIN_PRIORITY && + priority <= ESP32S2_MAX_PRIORITY); + + /* Check if there are any edge CPU interrupts available at the requested + * interrupt priority. + */ + + intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET; + return esp32s2_alloc_cpuint(intmask); +} + +/**************************************************************************** + * Name: esp32s2_free_cpuint + * + * Description: + * Free a previously allocated CPU interrupt by making it available in the + * g_cpu0_freeints. + * + * Input Parameters: + * cpuint - The CPU interrupt number to be freed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_free_cpuint(int cpuint) +{ + irqstate_t flags; + uint32_t *freeints; + uint32_t bitmask; + + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); + + /* Mark the CPU interrupt as available */ + + bitmask = (1ul << cpuint); + flags = enter_critical_section(); + + freeints = &g_cpu0_freeints; + + DEBUGASSERT((*freeints & bitmask) == 0); + *freeints |= bitmask; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32s2_attach_peripheral + * + * Description: + * Attach a peripheral interrupt to a CPU interrupt. + * This function may be called after esp32s2_alloc_edgeint or + * esp32s2_alloc_levelint + * + * Input Parameters: + * periphid - The peripheral number from irq.h to be assigned to + * a CPU interrupt. + * cpuint - The CPU interrupt to receive the peripheral interrupt + * assignment. This value is returned by + * esp32s2_alloc_edgeint or esp32s2_alloc_levelint. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_attach_peripheral(int periphid, int cpuint) +{ + uintptr_t regaddr; + + /* Get the map for CPU interrupts and IRQs */ + + uint8_t *intmap = g_cpu0_intmap; + + DEBUGASSERT(periphid >= 0 && periphid < ESP32S2_NPERIPHERALS); + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); + DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED); + + /* Get the INTERRUPT_PRO_X_MAP_REG for that specific peripheral. + * X stands for the peripheral source. + * Fill the interruption map with the IRQ for the new CPU interrupt. + * Allocate one peripheral interrupt to the CPU interrupt. + */ + + regaddr = INTERRUPT_PRO_X_MAP_REG(periphid); + intmap[cpuint] = periphid + XTENSA_IRQ_FIRSTPERI; + putreg32(cpuint, regaddr); +} + +/**************************************************************************** + * Name: esp32s2_detach_peripheral + * + * Description: + * Detach a peripheral interrupt from a CPU interrupt. + * + * Input Parameters: + * periphid - The peripheral number from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the peripheral interrupt will + * be detached. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_detach_peripheral(int periphid, int cpuint) +{ + uintptr_t regaddr; + uint8_t *intmap = g_cpu0_intmap; + + DEBUGASSERT(periphid >= 0 && periphid < ESP32S2_NPERIPHERALS); + DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED); + + /* Get the INTERRUPT_PRO_X_MAP_REG for that specific peripheral. + * X stands for the peripheral source. + * Unassign the IRQ from the CPU interrupt. + * Deallocate the peripheral interrupt from the CPU interrupt. + */ + + regaddr = INTERRUPT_PRO_X_MAP_REG(periphid); + intmap[cpuint] = CPUINT_UNASSIGNED; + putreg32(NO_CPUINT, regaddr); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_cpuint.h b/arch/xtensa/src/esp32s2/esp32s2_cpuint.h new file mode 100644 index 00000000000..4f6dd2e1c7c --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_cpuint.h @@ -0,0 +1,169 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_cpuint.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* No peripheral assigned to this CPU interrupt */ + +#define CPUINT_UNASSIGNED 0xff + +/* A low priority definition to be used by drivers */ + +#define ESP32S2_INT_PRIO_DEF 1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ + +extern uint8_t g_cpu0_intmap[ESP32S2_NCPUINTS]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_cpuint_initialize + * + * Description: + * Initialize CPU interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp32s2_cpuint_initialize(void); + +/**************************************************************************** + * Name: esp32s2_alloc_levelint + * + * Description: + * Allocate a level CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * + * Returned Value: + * On success, the allocated level-sensitive, CPU interrupt number is + * returned. A negated errno is returned on failure. The only possible + * failure is that all level-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32s2_alloc_levelint(int priority); + +/**************************************************************************** + * Name: esp32s2_alloc_edgeint + * + * Description: + * Allocate an edge CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * + * Returned Value: + * On success, the allocated edge-sensitive, CPU interrupt number is + * returned. A negated errno is returned on failure. The only possible + * failure is that all edge-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32s2_alloc_edgeint(int priority); + +/**************************************************************************** + * Name: esp32s2_free_cpuint + * + * Description: + * Free a previously allocated CPU interrupt by making it available in the + * g_cpu0_freeints. + * + * Input Parameters: + * cpuint - The CPU interrupt number to be freed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_free_cpuint(int cpuint); + +/**************************************************************************** + * Name: esp32s2_attach_peripheral + * + * Description: + * Attach a peripheral interrupt to a CPU interrupt. + * This function may be called after esp32s2_alloc_edgeint or + * esp32s2_alloc_levelint + * + * Input Parameters: + * periphid - The peripheral number from irq.h to be assigned to + * a CPU interrupt. + * cpuint - The CPU interrupt to receive the peripheral interrupt + * assignment. This value is returned by + * esp32s2_alloc_edgeint or esp32s2_alloc_levelint. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_attach_peripheral(int periphid, int cpuint); + +/**************************************************************************** + * Name: esp32s2_detach_peripheral + * + * Description: + * Detach a peripheral interrupt from a CPU interrupt. + * + * Input Parameters: + * periphid - The peripheral number from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the peripheral interrupt will + * be detached. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_detach_peripheral(int periphid, int cpuint); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.c b/arch/xtensa/src/esp32s2/esp32s2_gpio.c new file mode 100644 index 00000000000..265160c74ce --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_gpio.c @@ -0,0 +1,474 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "xtensa.h" +#include "hardware/esp32s2_iomux.h" +#include "hardware/esp32s2_gpio.h" +#include "esp32s2_cpuint.h" +#include "esp32s2_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NGPIO_HPINS (ESP32S2_NIRQ_GPIO - 32) +#define NGPIO_HMASK ((1ul << NGPIO_HPINS) - 1) +#define _NA_ 0xff + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +static int g_gpio_cpuint; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_dispatch + * + * Description: + * Second level dispatch for GPIO interrupt handling. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) +{ + uint32_t mask; + int i; + + /* Check each bit in the status register */ + + for (i = 0; i < 32 && status != 0; i++) + { + /* Check if there is an interrupt pending for this pin */ + + mask = (1ul << i); + if ((status & mask) != 0) + { + /* Yes... perform the second level dispatch */ + + irq_dispatch(irq + i, regs); + + /* Clear the bit in the status so that we might execute this loop + * sooner. + */ + + status &= ~mask; + } + } +} +#endif + +/**************************************************************************** + * Name: gpio_interrupt + * + * Description: + * GPIO interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +static int gpio_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + + /* Read and clear the lower GPIO interrupt status */ + + status = getreg32(GPIO_STATUS_REG); + putreg32(status, GPIO_STATUS_W1TC_REG); + + /* Dispatch pending interrupts in the lower GPIO status register */ + + gpio_dispatch(ESP32S2_FIRST_GPIOIRQ, status, (uint32_t *)context); + + /* Read and clear the upper GPIO interrupt status */ + + status = getreg32(GPIO_STATUS1_REG) & NGPIO_HMASK; + putreg32(status, GPIO_STATUS1_W1TC_REG); + + /* Dispatch pending interrupts in the lower GPIO status register */ + + gpio_dispatch(ESP32S2_FIRST_GPIOIRQ + 32, status, (uint32_t *)context); + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + ****************************************************************************/ + +int esp32s2_configgpio(int pin, gpio_pinattr_t attr) +{ + uintptr_t regaddr; + uint32_t func; + uint32_t cntrl; + uint32_t pin2func; + + DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS); + + /* Handle input pins */ + + func = 0; + cntrl = 0; + + if ((attr & INPUT) != 0) + { + if (pin < 32) + { + putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG); + } + else + { + putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TC_REG); + } + + /* Input enable */ + + func |= FUN_IE; + + if ((attr & PULLUP) != 0) + { + func |= FUN_PU; + } + else if (attr & PULLDOWN) + { + func |= FUN_PD; + } + } + + /* Handle output pins */ + + if ((attr & OUTPUT) != 0) + { + if (pin < 32) + { + putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG); + } + else + { + putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TS_REG); + } + } + + /* Add drivers */ + + func |= (uint32_t)(2ul << FUN_DRV_S); + + /* Select the pad's function. If no function was given, consider it a + * normal input or output (i.e. function3). + */ + + if ((attr & FUNCTION_MASK) != 0) + { + func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S); + } + else + { + func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S); + } + + if ((attr & OPEN_DRAIN) != 0) + { + cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S); + } + + pin2func = (pin + 1) * 4; + regaddr = DR_REG_IO_MUX_BASE + pin2func; + putreg32(func, regaddr); + + regaddr = GPIO_REG(pin); + putreg32(cntrl, regaddr); + return OK; +} + +/**************************************************************************** + * Name: esp32s2_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void esp32s2_gpiowrite(int pin, bool value) +{ + DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS); + + if (value) + { + if (pin < 32) + { + putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TS_REG); + } + else + { + putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TS_REG); + } + } + else + { + if (pin < 32) + { + putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TC_REG); + } + else + { + putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TC_REG); + } + } +} + +/**************************************************************************** + * Name: esp32s2_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool esp32s2_gpioread(int pin) +{ + uint32_t regval; + + DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS); + + if (pin < 32) + { + regval = getreg32(GPIO_IN_REG); + return ((regval >> pin) & 1) != 0; + } + else + { + regval = getreg32(GPIO_IN1_REG); + return ((regval >> (pin - 32)) & 1) != 0; + } +} + +/**************************************************************************** + * Name: esp32s2_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqinitialize(void) +{ + /* Allocate a level-sensitive, priority 1 CPU interrupt */ + + g_gpio_cpuint = esp32s2_alloc_levelint(1); + DEBUGASSERT(g_gpio_cpuint >= 0); + + /* Attach the GPIO peripheral to the allocated CPU interrupt */ + + up_disable_irq(g_gpio_cpuint); + esp32s2_attach_peripheral(ESP32S2_PERI_GPIO_INT_PRO, g_gpio_cpuint); + + /* Attach and enable the interrupt handler */ + + DEBUGVERIFY(irq_attach(ESP32S2_PERI_GPIO_INT_PRO, gpio_interrupt, NULL)); + up_enable_irq(g_gpio_cpuint); +} +#endif + +/**************************************************************************** + * Name: esp32s2_gpioirqenable + * + * Description: + * Enable the COPY interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype) +{ + uintptr_t regaddr; + uint32_t regval; + int pin; + + DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ); + + /* Convert the IRQ number to a pin number */ + + pin = ESP32S2_IRQ2PIN(irq); + + /* Get the address of the GPIO PIN register for this pin */ + + up_disable_irq(g_gpio_cpuint); + + regaddr = GPIO_REG(pin); + regval = getreg32(regaddr); + regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); + + /* Set the pin ENA field: + * + * Bit 0: APP CPU interrupt enable + * Bit 1: APP CPU non-maskable interrupt enable + * Bit 3: PRO CPU interrupt enable + * Bit 4: PRO CPU non-maskable interrupt enable + * Bit 5: SDIO's extent interrupt enable. + */ + + /* PRO_CPU */ + + regval |= ((1 << 2) << GPIO_PIN_INT_ENA_S); + + regval |= (intrtype << GPIO_PIN_INT_TYPE_S); + putreg32(regval, regaddr); + + up_enable_irq(g_gpio_cpuint); +} +#endif + +/**************************************************************************** + * Name: esp32s2_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqdisable(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + int pin; + + DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ); + + /* Convert the IRQ number to a pin number */ + + pin = ESP32S2_IRQ2PIN(irq); + + /* Get the address of the GPIO PIN register for this pin */ + + up_disable_irq(g_gpio_cpuint); + + regaddr = GPIO_REG(pin); + regval = getreg32(regaddr); + regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); + putreg32(regval, regaddr); + + up_enable_irq(g_gpio_cpuint); +} +#endif + +/**************************************************************************** + * Name: esp32s2_gpio_matrix_in + * + * Description: + * Set gpio input to a signal + * NOTE: one gpio can input to several signals + * If gpio == 0x30, cancel input to the signal, input 0 to signal + * If gpio == 0x38, cancel input to the signal, input 1 to signal, + * for I2C pad + * + ****************************************************************************/ + +void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv) +{ + uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4); + uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S); + + if (inv) + { + regval |= GPIO_FUNC0_IN_INV_SEL; + } + + if (gpio != 0x34) + { + regval |= GPIO_SIG0_IN_SEL; + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: esp32s2_gpio_matrix_out + * + * Description: + * Set signal output to gpio + * NOTE: one signal can output to several gpios + * If signal_idx == 0x100, cancel output put to the gpio + * + ****************************************************************************/ + +void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, + bool out_inv, bool oen_inv) +{ + uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4); + uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S; + + if (gpio >= GPIO_PIN_COUNT) + { + return; + } + + if (gpio < 32) + { + putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG); + } + else + { + putreg32((1ul << (gpio - 32)), GPIO_ENABLE1_W1TS_REG); + } + + if (out_inv) + { + regval |= GPIO_FUNC0_OUT_INV_SEL; + } + + if (oen_inv) + { + regval |= GPIO_FUNC0_OEN_INV_SEL; + } + + putreg32(regval, regaddr); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.h b/arch/xtensa/src/esp32s2/esp32s2_gpio.h new file mode 100644 index 00000000000..b83f0214a01 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_gpio.h @@ -0,0 +1,235 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ +#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT sig */ +#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ + +/* Bit-encoded input to esp32s2_configgpio() ********************************/ + +/* Encoded pin attributes used with esp32s2_configgpio() + * + * 8 7 6 5 4 3 2 1 0 + * -- -- -- -- -- -- -- -- -- + * FN FN FN OD PD PU F O I + */ + +#define PINMODE_SHIFT 0 +#define PINMODE_MASK (7 << PINMODE_SHIFT) +# define INPUT (1 << 0) +# define OUTPUT (1 << 1) +# define FUNCTION (1 << 2) + +#define PULLUP (1 << 3) +#define PULLDOWN (1 << 4) +#define OPEN_DRAIN (1 << 5) +#define FUNCTION_SHIFT 6 +#define FUNCTION_MASK (7 << FUNCTION_SHIFT) +# define FUNCTION_1 (1 << FUNCTION_SHIFT) +# define FUNCTION_2 (2 << FUNCTION_SHIFT) +# define FUNCTION_3 (3 << FUNCTION_SHIFT) +# define FUNCTION_4 (4 << FUNCTION_SHIFT) +# define FUNCTION_5 (5 << FUNCTION_SHIFT) +# define FUNCTION_6 (6 << FUNCTION_SHIFT) + +#define INPUT_PULLUP (INPUT | PULLUP) +#define INPUT_PULLDOWN (INPUT | PULLDOWN) +#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) +#define INPUT_FUNCTION (INPUT | FUNCTION) +# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1) +# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2) +# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3) +# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4) +# define INPUT_FUNCTION_5 (INPUT_FUNCTION | FUNCTION_5) +# define INPUT_FUNCTION_6 (INPUT_FUNCTION | FUNCTION_6) +#define OUTPUT_FUNCTION (OUTPUT | FUNCTION) +# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1) +# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2) +# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3) +# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4) +# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5) +# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6) + +/* Interrupt type used with esp32s2_gpioirqenable() */ + +#define DISABLED 0x00 +#define RISING 0x01 +#define FALLING 0x02 +#define CHANGE 0x03 +#define ONLOW 0x04 +#define ONHIGH 0x05 +#define ONLOW_WE 0x0c +#define ONHIGH_WE 0x0d + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Must be big enough to hold the above encodings */ + +typedef uint16_t gpio_pinattr_t; +typedef uint8_t gpio_intrtype_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqinitialize(void); +#else +# define esp32s2_gpioirqinitialize() +#endif + +/**************************************************************************** + * Name: esp32s2_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + ****************************************************************************/ + +int esp32s2_configgpio(int pin, gpio_pinattr_t attr); + +/**************************************************************************** + * Name: esp32s2_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void esp32s2_gpiowrite(int pin, bool value); + +/**************************************************************************** + * Name: esp32s2_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool esp32s2_gpioread(int pin); + +/**************************************************************************** + * Name: esp32s2_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype); +#else +# define esp32s2_gpioirqenable(irq,intrtype) +#endif + +/**************************************************************************** + * Name: esp32s2_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqdisable(int irq); +#else +# define esp32s2_gpioirqdisable(irq) +#endif + +/**************************************************************************** + * Name: esp32s2_gpio_matrix_in + * + * Description: + * Set gpio input to a signal + * NOTE: one gpio can input to several signals + * If gpio == 0x30, cancel input to the signal, input 0 to signal + * If gpio == 0x38, cancel input to the signal, input 1 to signal, + * for I2C pad + * + ****************************************************************************/ + +void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/**************************************************************************** + * Name: esp32s2_gpio_matrix_out + * + * Description: + * Set signal output to gpio + * NOTE: one signal can output to several gpios + * If signal_idx == 0x100, cancel output put to the gpio + * + ****************************************************************************/ + +void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, + bool out_inv, bool oen_inv); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_idle.c b/arch/xtensa/src/esp32s2/esp32s2_idle.c new file mode 100644 index 00000000000..e44ebc145db --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_idle.c @@ -0,0 +1,205 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode + * (which corresponds to ESP32S2 stop mode). If this alarm expires, + * the logic in this file will wakeup from PM_STANDBY mode and + * transition to PM_SLEEP mode (ESP32S2 standby mode). + */ + +#ifdef CONFIG_PM +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 15 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +#ifndef CONFIG_PM_SLEEP_WAKEUP_SEC +# define CONFIG_PM_SLEEP_WAKEUP_SEC 20 +#endif + +#ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC +# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0 +#endif + +#define PM_IDLE_DOMAIN 0 /* Revisit */ +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = spin_lock_irqsave(NULL); + + /* Perform board-specific, state-dependent logic here */ + + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + spin_unlock_irqrestore(NULL, flags); + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + { + /* Enter Force-sleep mode */ + + esp32s2_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 + + CONFIG_PM_ALARM_NSEC / 1000); + } + break; + + case PM_SLEEP: + { + /* Enter Deep-sleep mode */ + + esp32s2_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 + + CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000); + } + break; + + default: + break; + } + } + else + { + if (oldstate == PM_NORMAL) + { + /* Relax normal operation */ + + pm_relax(PM_IDLE_DOMAIN, PM_NORMAL); + } + +#ifdef CONFIG_WATCHDOG + /* Announce the power management state change to feed watchdog */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); +#endif + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + up_idlepm(); + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + +#if XCHAL_HAVE_INTERRUPTS + __asm__ __volatile__ ("waiti 0"); +#endif +#endif +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_intdecode.c b/arch/xtensa/src/esp32s2/esp32s2_intdecode.c new file mode 100644 index 00000000000..5f6ac7e05b6 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_intdecode.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_intdecode.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "xtensa.h" +#include "esp32s2_cpuint.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_intclear + ****************************************************************************/ + +static inline void xtensa_intclear(uint32_t mask) +{ + __asm__ __volatile__ + ( + "wsr %0, INTCLEAR\n" + : "=r"(mask) : : + ); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_int_decode + * + * Description: + * Determine the peripheral that generated the interrupt and dispatch + * handling to the registered interrupt handler via xtensa_irq_dispatch(). + * + * Input Parameters: + * cpuints - Set of pending interrupts valid for this level + * regs - Saves processor state on the stack + * + * Returned Value: + * Normally the same value as regs is returned. But, in the event of an + * interrupt level context switch, the returned value will, instead point + * to the saved processor state in the TCB of the newly started task. + * + ****************************************************************************/ + +uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs) +{ + uint8_t *intmap; + uint32_t mask; + int bit; + + intmap = g_cpu0_intmap; + + /* Skip over zero bits, eight at a time */ + + for (bit = 0, mask = 0xff; + bit < ESP32S2_NCPUINTS && (cpuints & mask) == 0; + bit += 8, mask <<= 8); + + /* Process each pending CPU interrupt */ + + for (; bit < ESP32S2_NCPUINTS && cpuints != 0; bit++) + { + mask = (1 << bit); + if ((cpuints & mask) != 0) + { + /* Extract the IRQ number from the mapping table */ + + uint8_t irq = intmap[bit]; + DEBUGASSERT(irq != CPUINT_UNASSIGNED); + + /* Clear software or edge-triggered interrupt */ + + xtensa_intclear(mask); + + /* Dispatch the CPU interrupt. + * + * NOTE that regs may be altered in the case of an interrupt + * level context switch. + */ + + regs = xtensa_irq_dispatch((int)irq, regs); + + /* Clear the bit in the pending interrupt so that perhaps + * we can exit the look early. + */ + + cpuints &= ~mask; + } + } + + return regs; +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_irq.c b/arch/xtensa/src/esp32s2/esp32s2_irq.c new file mode 100644 index 00000000000..c470dba7e49 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_irq.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "xtensa.h" +#include "esp32s2_cpuint.h" +#include "esp32s2_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a reference to the current interrupt level + * register storage structure. It is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_irq_dump + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void esp32s2_irq_dump(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); +#warning Missing logic + leave_critical_section(flags); +} +#else +# define esp32s2_irq_dump(msg, irq) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Initialize CPU interrupts */ + + esp32s2_cpuint_initialize(); + + /* Attach and enable internal interrupts */ + + esp32s2_irq_dump("initial", NR_IRQS); + +#ifdef CONFIG_ESP32S2_GPIO_IRQ + /* Initialize GPIO interrupt support */ + + esp32s2_gpioirqinitialize(); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts. Also clears PS.EXCM */ + + up_irq_enable(); +#endif +} + diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c new file mode 100644 index 00000000000..b1e2aa34957 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c @@ -0,0 +1,782 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "xtensa.h" + +#include "hardware/esp32s2_system.h" +#include "hardware/esp32s2_uart.h" +#include "hardware/esp32s2_soc.h" + +#include "esp32s2_clockconfig.h" +#include "esp32s2_config.h" +#include "esp32s2_gpio.h" + +#include "esp32s2_lowputc.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE + +#ifdef CONFIG_ESP32S2_UART0 + +struct esp32s2_uart_s g_uart0_config = +{ + .periph = ESP32S2_PERI_UART, + .id = 0, + .cpuint = -ENOMEM, + .irq = ESP32S2_IRQ_UART, + .baud = CONFIG_UART0_BAUD, + .bits = CONFIG_UART0_BITS, + .parity = CONFIG_UART0_PARITY, + .stop_b2 = CONFIG_UART0_2STOP, + .int_pri = ESP32S2_INT_PRIO_DEF, + .txpin = CONFIG_ESP32S2_UART0_TXPIN, + .txsig = U0TXD_OUT_IDX, + .rxpin = CONFIG_ESP32S2_UART0_RXPIN, + .rxsig = U0RXD_IN_IDX, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rtspin = CONFIG_ESP32S2_UART0_RTSPIN, + .rtssig = U0RTS_OUT_IDX, +#ifdef CONFIG_UART0_IFLOWCONTROL + .iflow = true, /* input flow control (RTS) enabled */ +#else + .iflow = false, /* input flow control (RTS) disabled */ +#endif +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .ctspin = CONFIG_ESP32S2_UART0_CTSPIN, + .ctssig = U0CTS_IN_IDX, +#ifdef CONFIG_UART0_OFLOWCONTROL + .oflow = true, /* output flow control (CTS) enabled */ +#else + .oflow = false, /* output flow control (CTS) disabled */ +#endif +#endif +}; + +#endif /* CONFIG_ESP32S2_UART0 */ + +#ifdef CONFIG_ESP32S2_UART1 + +struct esp32s2_uart_s g_uart1_config = +{ + .periph = ESP32S2_PERI_UART1, + .id = 1, + .cpuint = -ENOMEM, + .irq = ESP32S2_IRQ_UART1, + .baud = CONFIG_UART1_BAUD, + .bits = CONFIG_UART1_BITS, + .parity = CONFIG_UART1_PARITY, + .stop_b2 = CONFIG_UART1_2STOP, + .int_pri = ESP32S2_INT_PRIO_DEF, + .txpin = CONFIG_ESP32S2_UART1_TXPIN, + .txsig = U1TXD_OUT_IDX, + .rxpin = CONFIG_ESP32S2_UART1_RXPIN, + .rxsig = U1RXD_IN_IDX, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rtspin = CONFIG_ESP32S2_UART1_RTSPIN, + .rtssig = U1RTS_OUT_IDX, +#ifdef CONFIG_UART1_IFLOWCONTROL + .iflow = true, /* input flow control (RTS) enabled */ +#else + .iflow = false, /* input flow control (RTS) disabled */ +#endif +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .ctspin = CONFIG_ESP32S2_UART1_CTSPIN, + .ctssig = U1CTS_IN_IDX, +#ifdef CONFIG_UART1_OFLOWCONTROL + .oflow = true, /* output flow control (CTS) enabled */ +#else + .oflow = false, /* output flow control (CTS) disabled */ +#endif +#endif +}; + +#endif /* CONFIG_ESP32S2_UART1 */ +#endif /* HAVE_UART_DEVICE */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_lowputc_set_iflow + * + * Description: + * Configure the input hardware flow control. + * + * Parameters: + * priv - Pointer to the private driver struct. + * threshold - RX FIFO value from which RST will automatically be + * asserted. + * enable - true = enable, false = disable + * + ****************************************************************************/ + +void esp32s2_lowputc_set_iflow(const struct esp32s2_uart_s *priv, + uint8_t threshold, bool enable) +{ + uint32_t mask; + if (enable) + { + /* Enable RX flow control */ + + modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN); + + /* Configure the threshold */ + + mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD); + modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask); + } + else + { + /* Disable RX flow control */ + + modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_set_oflow + * + * Description: + * Configure the output hardware flow control. + * + * Parameters: + * priv - Pointer to the private driver struct. + * enable - true = enable, false = disable + * + ****************************************************************************/ + +void esp32s2_lowputc_set_oflow(const struct esp32s2_uart_s *priv, + bool enable) +{ + if (enable) + { + /* Enable TX flow control */ + + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN); + } + else + { + /* Disable TX flow control */ + + modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_enable_sysclk + * + * Description: + * Enable clock for the UART using the System register. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_enable_sysclk(const struct esp32s2_uart_s *priv) +{ + if (priv->id == 0) + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, + SYSTEM_UART_CLK_EN_M); + } + else + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, + SYSTEM_UART1_CLK_EN_M); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_enable_memclk + * + * Description: + * Enable memory clock gate enable signal. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_enable_memclk(const struct esp32s2_uart_s *priv) +{ + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_MEM_CLK_EN_M); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_sysclk + * + * Description: + * Disable clock for the UART using the System register. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_sysclk(const struct esp32s2_uart_s *priv) +{ + if (priv->id == 0) + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART_CLK_EN_M, 0); + } + else + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART1_CLK_EN_M, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_memclk + * + * Description: + * Disable memory clock gate enable signal. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_memclk(const struct esp32s2_uart_s *priv) +{ + modifyreg32(UART_CONF0_REG(priv->id), UART_MEM_CLK_EN_M, 0); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_set_sclk + * + * Description: + * Set a source clock for UART. + * + * Parameters: + * priv - Pointer to the private driver struct. + * source - REF_TICK = 0 + * APB_CLK = 1 80 MHz + * + ****************************************************************************/ + +void esp32s2_lowputc_set_sclk(const struct esp32s2_uart_s *priv, + enum uart_sclk source) +{ + modifyreg32(UART_CONF0_REG(priv->id), UART_TICK_REF_ALWAYS_ON_M, source); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_get_sclk + * + * Description: + * Get the source clock for UART. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + * Returned Value: + * The frequency of the clock in Hz. + * + ****************************************************************************/ + +uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s * priv) +{ + uint32_t clk_conf_reg; + uint32_t ret = -ENODATA; + uint32_t clk; + clk_conf_reg = getreg32(UART_CONF0_REG(priv->id)); + clk = REG_MASK(clk_conf_reg, UART_TICK_REF_ALWAYS_ON); + if (clk == 1) + { + ret = esp_clk_apb_freq(); + } + else + { + /* TODO in esp32s2_clockconfig.c + * ret = esp32s2_clk_ref_freq(); + */ + + _warn("esp32s2_clockconfig.c still doesn't support " + "esp32s2_clk_ref_freq() "); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_lowputc_baud + * + * Description: + * Set the baud rate according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_baud(const struct esp32s2_uart_s * priv) +{ + uint32_t sclk_freq; + uint32_t clk_div; + uint32_t int_part; + uint32_t frag_part; + + /* Get serial clock */ + + sclk_freq = esp32s2_lowputc_get_sclk(priv); + + /* Calculate the clock divisor to achieve the baud rate. + * baud = sclk/clk_div + * clk_div = int_part + (frag_part/16) + * 16*clk_div = 16*int_part + frag + * 16*clk_div = (sclk*16)/baud + */ + + clk_div = ((sclk_freq << 4) / (priv->baud)); + + /* Get the integer part of it. */ + + int_part = clk_div >> 4; + + /* Get the frag part of it. */ + + frag_part = clk_div & 0xf; + + /* Set integer part of the clock divisor for baud rate. */ + + int_part = VALUE_TO_FIELD(int_part, UART_CLKDIV); + modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part); + + /* Set decimal part of the clock divisor for baud rate. */ + + frag_part = VALUE_TO_FIELD(frag_part, UART_CLKDIV_FRAG); + modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M, frag_part); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_normal_mode + * + * Description: + * Set the UART to operate in normal mode, i.e., disable the RS485 mode and + * IRDA mode. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_normal_mode(const struct esp32s2_uart_s * priv) +{ + /* Disable RS485 mode */ + + modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0); + modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0); + modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0); + + /* Disable IRDA mode */ + + modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_parity + * + * Description: + * Set the parity, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_parity(const struct esp32s2_uart_s * priv) +{ + if (priv->parity == UART_PARITY_DISABLE) + { + modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0); + } + else + { + modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M, + ((priv->parity & BIT(0)) << UART_PARITY_S)); + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_PARITY_EN_M); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_data_length + * + * Description: + * Set the data bits length, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +int esp32s2_lowputc_data_length(const struct esp32s2_uart_s * priv) +{ + int ret = OK; + uint32_t length = (priv->bits - 5); + + /* If it is the allowed range */ + + if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS) + { + modifyreg32(UART_CONF0_REG(priv->id), UART_BIT_NUM_M, + length << UART_BIT_NUM_S); + } + else + { + ret = -EINVAL; + } + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_lowputc_stop_length + * + * Description: + * Set the stop bits length, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_stop_length(const struct esp32s2_uart_s *priv) +{ + if (priv->stop_b2 == 0) + { + modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M, + UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S); + } + else + { + modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M, + UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_send_byte + * + * Description: + * Send one byte. + * + * Parameters: + * priv - Pointer to the private driver struct. + * byte - Byte to be sent. + * + ****************************************************************************/ + +void esp32s2_lowputc_send_byte(const struct esp32s2_uart_s * priv, + char byte) +{ + putreg32((uint32_t) byte, UART_FIFO_REG(priv->id)); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_is_tx_fifo_full + * + * Description: + * Verify if TX FIFO is full. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + * Returned Value: + * True if it is full, otherwise false. + * + ****************************************************************************/ + +bool esp32s2_lowputc_is_tx_fifo_full(const struct esp32s2_uart_s *priv) +{ + uint32_t reg; + uint32_t val; + reg = getreg32(UART_STATUS_REG(priv->id)); + val = REG_MASK(reg, UART_TXFIFO_CNT); + if (val < (UART_TX_FIFO_SIZE -1)) + { + return false; + } + else + { + return true; + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_peripheral + * + * Description: + * Reset the UART peripheral by using System reg. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_peripheral(const struct esp32s2_uart_s *priv) +{ + if (priv->id == 0) + { + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, SYSTEM_UART_RST_M); + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST_M, 0); + } + else + { + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, SYSTEM_UART1_RST_M); + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST_M, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_txfifo + * + * Description: + * Reset TX FIFO. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_txfifo(const struct esp32s2_uart_s *priv) +{ + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TXFIFO_RST_M); + modifyreg32(UART_CONF0_REG(priv->id), UART_TXFIFO_RST_M, 0); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_rxfifo + * + * Description: + * Reset RX FIFO. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_rxfifo(const struct esp32s2_uart_s *priv) +{ + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_RXFIFO_RST_M); + modifyreg32(UART_CONF0_REG(priv->id), UART_RXFIFO_RST_M, 0); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_all_uart_int + * + * Description: + * Disable all UART interrupts. + * + * Parameters: + * priv - Pointer to the private driver struct. + * current_status - Pointer to a variable to store the current status of + * the interrupt enable register before disabling + * UART interrupts. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv, + uint32_t *current_status) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (current_status != NULL) + { + /* Save current status */ + + *current_status = getreg32(UART_INT_ENA_REG(priv->id)); + } + + /* Disable all UART int */ + + putreg32(0, UART_INT_ENA_REG(priv->id)); + + /* Clear all ints */ + + putreg32(UINT32_MAX, UART_INT_CLR_REG(priv->id)); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_restore_all_uart_int + * + * Description: + * Restore all UART interrupts. + * + * Parameters: + * priv - Pointer to the private driver struct. + * last_status - Pointer to a variable that stored the last state of the + * interrupt enable register. + * + ****************************************************************************/ + +void esp32s2_lowputc_restore_all_uart_int(const struct esp32s2_uart_s *priv, + uint32_t *last_status) +{ + /* Restore the previous behaviour */ + + putreg32(*last_status, UART_INT_ENA_REG(priv->id)); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_config_pins + * + * Description: + * Configure TX and RX UART pins. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv) +{ + /* Configure the pins */ + + /* Route UART TX signal to the selected TX pin */ + + esp32s2_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0); + + /* Select the GPIO function to the TX pin and + * configure as output. + */ + + esp32s2_configgpio(priv->txpin, OUTPUT_FUNCTION_1); + + /* Select the GPIO function to the RX pin and + * configure as input. + */ + + esp32s2_configgpio(priv->rxpin, INPUT_FUNCTION_1); + + /* Route UART RX signal to the selected RX pin */ + + esp32s2_gpio_matrix_in(priv->rxpin, priv->rxsig, 0); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + esp32s2_configgpio(priv->rtspin, OUTPUT_FUNCTION_1); + esp32s2_gpio_matrix_out(priv->rtspin, priv->rtssig, + 0, 0); + } + +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->oflow) + { + esp32s2_configgpio(priv->ctspin, INPUT_FUNCTION_1); + esp32s2_gpio_matrix_in(priv->ctspin, priv->ctssig, 0); + } +#endif +} + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console. + * + * Parameters: + * ch - Byte to be sent. + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) + struct esp32s2_uart_s *priv = &g_uart0_config; +#elif defined (CONFIG_UART1_SERIAL_CONSOLE) + struct esp32s2_uart_s *priv = &g_uart1_config; +# endif + + /* Wait until the TX FIFO has space to insert new char */ + + while (esp32s2_lowputc_is_tx_fifo_full(priv)); + + /* Then send the character */ + + esp32s2_lowputc_send_byte(priv, ch); + +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: esp32s2_lowsetup + * + * Description: + * This performs only the basic configuration for UART pins. + * + ****************************************************************************/ + +void esp32s2_lowsetup(void) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + +#ifdef CONFIG_ESP32S2_UART0 + + esp32s2_lowputc_config_pins(&g_uart0_config); + +#endif + +#ifdef CONFIG_ESP32S2_UART1 + + esp32s2_lowputc_config_pins(&g_uart1_config); + +#endif + +#endif /* !CONFIG_SUPPRESS_UART_CONFIG */ +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.h b/arch/xtensa/src/esp32s2/esp32s2_lowputc.h new file mode 100644 index 00000000000..bdf49195534 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.h @@ -0,0 +1,433 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "hardware/esp32s2_uart.h" +#include "hardware/esp32s2_gpio_sigmap.h" + +#include "esp32s2_cpuint.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum uart_sclk +{ + REF_TICK, + APB_CLK = 1, /* 80 MHz */ +}; + +enum uart_parity +{ + UART_PARITY_DISABLE, + UART_PARITY_ODD, + UART_PARITY_EVEN +}; + +enum uart_data_length +{ + UART_DATA_5_BITS, + UART_DATA_6_BITS, + UART_DATA_7_BITS, + UART_DATA_8_BITS +}; + +enum uart_stop_length +{ + UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */ + UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */ +}; + +/* Default FIFOs size */ + +#define UART_TX_FIFO_SIZE 128 +#define UART_RX_FIFO_SIZE 128 + +/* Struct used to store uart driver information and to + * manipulate uart driver + */ + +struct esp32s2_uart_s +{ + uint8_t periph; /* UART peripheral ID */ + int cpuint; /* CPU interrupt assigned to this UART */ + uint8_t id; /* UART ID */ + uint8_t irq; /* IRQ associated with this UART */ + uint32_t baud; /* Configured baud rate */ + uint8_t bits; /* Data length (5 to 8 bits). */ + uint8_t parity; /* 0=no parity, 1=odd parity, 2=even parity */ + uint8_t stop_b2; /* Use 2 stop bits? 0 = no (use 1) 1 = yes (use 2) */ + uint8_t int_pri; /* UART Interrupt Priority */ + uint8_t txpin; /* TX pin */ + uint8_t txsig; /* TX signal */ + uint8_t rxpin; /* RX pin */ + uint8_t rxsig; /* RX signal */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + uint8_t rtspin; /* RTS pin number */ + uint8_t rtssig; /* RTS signal */ + bool iflow; /* Input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + uint8_t ctspin; /* CTS pin number */ + uint8_t ctssig; /* CTS signal */ + bool oflow; /* Output flow control (CTS) enabled */ +#endif +}; + +extern struct esp32s2_uart_s g_uart0_config; +extern struct esp32s2_uart_s g_uart1_config; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_lowputc_set_iflow + * + * Description: + * Configure the input hardware flow control. + * + * Parameters: + * priv - Pointer to the private driver struct. + * threshold - RX FIFO value from which RST will automatically be + * asserted. + * enable - true = enable, false = disable + * + ****************************************************************************/ + +void esp32s2_lowputc_set_iflow(const struct esp32s2_uart_s *priv, + uint8_t threshold, bool enable); + +/**************************************************************************** + * Name: esp32s2_lowputc_set_oflow + * + * Description: + * Configure the output hardware flow control. + * + * Parameters: + * priv - Pointer to the private driver struct. + * enable - true = enable, false = disable + * + ****************************************************************************/ + +void esp32s2_lowputc_set_oflow(const struct esp32s2_uart_s *priv, + bool enable); + +/**************************************************************************** + * Name: esp32s2_lowputc_enable_sysclk + * + * Description: + * Enable clock for the UART using the System register. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_enable_sysclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_enable_memclk + * + * Description: + * Enable memory clock gate enable signal. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_enable_memclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_sysclk + * + * Description: + * Disable clock for the UART using the System register. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_sysclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_memclk + * + * Description: + * Disable memory clock gate enable signal. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_memclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_set_sclk + * + * Description: + * Set a source clock for UART. + * + * Parameters: + * priv - Pointer to the private driver struct. + * source - REF_TICK = 0 + * APB_CLK = 1 80 MHz + * + ****************************************************************************/ + +void esp32s2_lowputc_set_sclk(const struct esp32s2_uart_s *priv, + enum uart_sclk source); + +/**************************************************************************** + * Name: esp32s2_lowputc_get_sclk + * + * Description: + * Get the source clock for UART. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + * Returned Value: + * The frequency of the clock in Hz. + * + ****************************************************************************/ + +uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_baud + * + * Description: + * Set the baud rate according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_baud(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_normal_mode + * + * Description: + * Set the UART to operate in normal mode, i.e., disable the RS485 mode and + * IRDA mode. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_normal_mode(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_parity + * + * Description: + * Set the parity, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_parity(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_data_length + * + * Description: + * Set the data bits length, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +int esp32s2_lowputc_data_length(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_stop_length + * + * Description: + * Set the stop bits length, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_stop_length(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_send_byte + * + * Description: + * Send one byte. + * + * Parameters: + * priv - Pointer to the private driver struct. + * byte - Byte to be sent. + * + ****************************************************************************/ + +void esp32s2_lowputc_send_byte(const struct esp32s2_uart_s *priv, + char byte); + +/**************************************************************************** + * Name: esp32s2_lowputc_is_tx_fifo_full + * + * Description: + * Verify if TX FIFO is full. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + * Returned Value: + * True if it is full, otherwise false. + * + ****************************************************************************/ + +bool esp32s2_lowputc_is_tx_fifo_full(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_peripheral + * + * Description: + * Reset the UART peripheral by using System reg. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_peripheral(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_txfifo + * + * Description: + * Reset TX FIFO. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_txfifo(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_rxfifo + * + * Description: + * Reset RX FIFO. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_rxfifo(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_all_uart_int + * + * Description: + * Disable all UART interrupts. + * + * Parameters: + * priv - Pointer to the private driver struct. + * current_status - Pointer to a variable to store the current status of + * the interrupt enable register before disabling + * UART interrupts. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv, + uint32_t *current_status); + +/**************************************************************************** + * Name: esp32s2_lowputc_restore_all_uart_int + * + * Description: + * Restore all UART interrupts. + * + * Parameters: + * priv - Pointer to the private driver struct. + * last_status - Pointer to a variable that stored the last state of the + * interrupt enable register. + * + ****************************************************************************/ + +void esp32s2_lowputc_restore_all_uart_int(const struct esp32s2_uart_s *priv, + uint32_t * last_status); + +/**************************************************************************** + * Name: esp32s2_lowputc_config_pins + * + * Description: + * Configure TX and RX UART pins. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void esp32s2_lowsetup(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_region.c b/arch/xtensa/src/esp32s2/esp32s2_region.c new file mode 100644 index 00000000000..a9d7595591a --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_region.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_region.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_protected_pages[] = +{ + 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000 +}; + +#define NPROTECTED_PAGES (sizeof(g_protected_pages)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_write_dtlb and xtensa_write_itlb + * + * Description: + * Functions to set page attributes for Region Protection option in the + * CPU. See Xtensa ISA Reference manual for explanation of arguments + * (section 4.6.3.2). + * + ****************************************************************************/ + +static inline void xtensa_write_dtlb(uint32_t vpn, unsigned int attr) +{ + __asm__ __volatile__ + ( + "wdtlb %1, %0\n" + "dsync\n" + : : "r" (vpn), "r" (attr) + ); +} + +static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr) +{ + __asm__ __volatile__ + ( + "witlb %1, %0\n" + "isync\n" + : : "r" (vpn), "r" (attr) + ); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_region_protection + * + * Description: + * Make page 0 access raise an exception. Also protect some other unused + * pages so we can catch weirdness. + * + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + * + ****************************************************************************/ + +void esp32s2_region_protection(void) +{ + int i; + + for (i = 0; i < NPROTECTED_PAGES; ++i) + { + xtensa_write_dtlb(g_protected_pages[i], 0xf); + xtensa_write_itlb(g_protected_pages[i], 0xf); + } + + xtensa_write_dtlb(0x20000000, 0); + xtensa_write_itlb(0x20000000, 0); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_region.h b/arch/xtensa/src/esp32s2/esp32s2_region.h new file mode 100644 index 00000000000..67d20cf2793 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_region.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_region.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_region_protection + * + * Description: + * Make page 0 access raise an exception. Also protect some other unused + * pages so we can catch weirdness. + * + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + * + ****************************************************************************/ + +void esp32s2_region_protection(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_serial.c b/arch/xtensa/src/esp32s2/esp32s2_serial.c new file mode 100644 index 00000000000..76aa0252505 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_serial.c @@ -0,0 +1,1169 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include "xtensa.h" + +#include "hardware/esp32s2_uart.h" +#include "hardware/esp32s2_system.h" + +#include "esp32s2_config.h" +#include "esp32s2_cpuint.h" +#include "esp32s2_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef USE_SERIALDRIVER + +/* Which UART will be tty0/console and which tty1? */ + +/* First pick the console and ttys0. + * Console can be UART0 or UART1, but will always be ttys0. + */ + +/* In case a UART was assigned to be + * the console and the corresponding peripheral was also selected. + */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0_dev /* UART0 is console */ +# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1_dev /* UART1 is console */ +# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# endif /* CONFIG_UART0_SERIAL_CONSOLE */ +#else /* No console */ +# undef CONSOLE_DEV +# if defined(CONFIG_ESP32S2_UART0) +# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_ESP32S2_UART1) +# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# endif +#endif /* HAVE_SERIAL_CONSOLE */ + +/* Pick ttys1 */ + +#if defined(CONFIG_ESP32S2_UART0) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_ESP32S2_UART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#endif + +#ifdef HAVE_UART_DEVICE + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Serial driver methods */ + +static int esp32s2_setup(struct uart_dev_s *dev); +static void esp32s2_shutdown(struct uart_dev_s *dev); +static int esp32s2_attach(struct uart_dev_s *dev); +static void esp32s2_detach(struct uart_dev_s *dev); +static void esp32s2_txint(struct uart_dev_s *dev, bool enable); +static void esp32s2_rxint(struct uart_dev_s *dev, bool enable); +static bool esp32s2_rxavailable(struct uart_dev_s *dev); +static bool esp32s2_txready(struct uart_dev_s *dev); +static bool esp32s2_txempty(struct uart_dev_s *dev); +static void esp32s2_send(struct uart_dev_s *dev, int ch); +static int esp32s2_receive(struct uart_dev_s *dev, unsigned int *status); +static int esp32s2_ioctl(struct file *filep, int cmd, unsigned long arg); +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool esp32s2_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Operations */ + +static struct uart_ops_s g_uart_ops = +{ + .setup = esp32s2_setup, + .shutdown = esp32s2_shutdown, + .attach = esp32s2_attach, + .detach = esp32s2_detach, + .txint = esp32s2_txint, + .rxint = esp32s2_rxint, + .rxavailable = esp32s2_rxavailable, + .txready = esp32s2_txready, + .txempty = esp32s2_txempty, + .send = esp32s2_send, + .receive = esp32s2_receive, + .ioctl = esp32s2_ioctl, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = esp32s2_rxflowcontrol, +#endif +}; + +/* UART 0 */ + +#ifdef CONFIG_ESP32S2_UART0 + +static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE]; + +/* Fill only the requested fields */ + +static uart_dev_t g_uart0_dev = +{ +#ifdef CONFIG_UART0_SERIAL_CONSOLE + .isconsole = true, +#else + .isconsole = false, +#endif + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0_txbuffer, + }, + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0_rxbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart0_config +}; + +#endif + +/* UART 1 */ + +#ifdef CONFIG_ESP32S2_UART1 + +static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; + +/* Fill only the requested fields */ + +static uart_dev_t g_uart1_dev = +{ +#ifdef CONFIG_UART1_SERIAL_CONSOLE + .isconsole = true, +#else + .isconsole = false, +#endif + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1_txbuffer, + }, + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1_rxbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart1_config +}; + +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: uart_handler + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq' It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int uart_handler(int irq, FAR void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct esp32s2_uart_s *priv = dev->priv; + uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M; + uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M; + uint32_t int_status; + + int_status = getreg32(UART_INT_ST_REG(priv->id)); + + /* TX FIFO empty interrupt or UART TX done int */ + + if (int_status & tx_mask) + { + /* Unload the SW TX FIFO into the HW TX FIFO and clear interrupts */ + + uart_xmitchars(dev); + modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask); + } + + /* Rx fifo timeout interrupt or rx fifo full interrupt */ + + if (int_status & rx_mask) + { + /* Load the SW RX FIFO with the HW RX FIFO content and clear + * interrupts. + */ + + uart_recvchars(dev); + modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32s2_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This method is + * called the first time that the serial port is opened. + * For the serial console, this will occur very early in initialization, + * for other serial ports this will occur when the port is first opened. + * This setup does not include attaching or enabling interrupts. + * That portion of the UART setup is performed when the attach() method + * is called. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Zero (OK) is returned. + * + ****************************************************************************/ + +static int esp32s2_setup(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + + /* Initialize UART module */ + + /* Discard corrupt RX data */ + + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_ERR_WR_MASK_M); + + /* Define 0 as the threshold that means TX FIFO buffer is empty. */ + + modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0); + + /* Define a threshold to trigger an RX FIFO FULL interrupt. + * Define just one byte to read data immediately. + */ + + modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M, + 1 << UART_RXFIFO_FULL_THRHD_S); + + /* Define the maximum FIFO size for RX and TX FIFO. + * 1 block = 128 bytes. + * As a consequence, software serial FIFO can unload the bytes and + * not wait too much on polling activity. + */ + + modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M, + (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S)); + + /* Configure the UART Baud Rate */ + + esp32s2_lowputc_baud(priv); + + /* Set a mode */ + + esp32s2_lowputc_normal_mode(priv); + + /* Parity */ + + esp32s2_lowputc_parity(priv); + + /* Data Frame size */ + + esp32s2_lowputc_data_length(priv); + + /* Stop bit */ + + esp32s2_lowputc_stop_length(priv); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + /* Configure the input flow control */ + + if (priv->iflow) + { + /* Enable input flow control and set the RX FIFO threshold + * to assert the RTS line to half the RX FIFO buffer. + * It will then save some space on the hardware fifo to + * remaining bytes that may arrive after RTS be asserted + * and before the transmitter stops sending data. + */ + + esp32s2_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2), + true); + } + else + { + /* Just disable input flow control, threshold parameter + * will be discarded. + */ + + esp32s2_lowputc_set_iflow(priv, 0 , false); + } + +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + /* Configure the ouput flow control */ + + if (priv->oflow) + { + esp32s2_lowputc_set_oflow(priv, true); + } + else + { + esp32s2_lowputc_set_oflow(priv, false); + } +#endif + + /* Reset FIFOs */ + + esp32s2_lowputc_rst_txfifo(priv); + esp32s2_lowputc_rst_rxfifo(priv); + + return OK; +} + +/**************************************************************************** + * Name: esp32s2_shutdown + * + * Description: + * Disable the UART. This method is called when the serial port is closed. + * This method reverses the operation the setup method. NOTE that the serial + * console is never shutdown. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + ****************************************************************************/ + +static void esp32s2_shutdown(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + + /* Disable ints */ + + esp32s2_lowputc_disable_all_uart_int(priv, NULL); + + /* Disable clk */ + + esp32s2_lowputc_disable_sysclk(priv); + + /* Disable memory clock */ + + esp32s2_lowputc_disable_memclk(priv); +} + +/**************************************************************************** + * Name: esp32s2_attach + * + * Description: + * Configure the UART to operate in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the the setup() method is called, however, the serial console may + * operate in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int esp32s2_attach(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + int ret; + + DEBUGASSERT(priv->cpuint == -ENOMEM); + + /* Alloc a level CPU interrupt */ + + priv->cpuint = esp32s2_alloc_levelint(priv->int_pri); + if (priv->cpuint < 0) + { + return priv->cpuint; + } + else + { + /* Disable the allocated CPU interrupt */ + + up_disable_irq(priv->cpuint); + + /* Attach a peripheral interrupt to a CPU interrupt */ + + esp32s2_attach_peripheral(priv->periph, priv->cpuint); + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, uart_handler, dev); + if (ret == OK) + { + up_enable_irq(priv->cpuint); + } + } + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + ****************************************************************************/ + +static void esp32s2_detach(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + + DEBUGASSERT(priv->cpuint != -ENOMEM); + + /* Disable the CPU interrupt and detach the IRQ */ + + up_disable_irq(priv->cpuint); + irq_detach(priv->irq); + + /* Disassociate the peripheral interrupt from the CPU interrupt */ + + esp32s2_detach_peripheral(priv->periph, priv->cpuint); + + /* Release the CPU interrupt */ + + esp32s2_free_cpuint(priv->periph); + + /* Reset cpuint */ + + priv->cpuint = -ENOMEM; +} + +/**************************************************************************** + * Name: esp32s2_txint + * + * Description: + * Enable or disable TX interrupts. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * enable - If true enables the TX interrupt, if false disables it. + * + ****************************************************************************/ + +static void esp32s2_txint(struct uart_dev_s *dev, bool enable) +{ + struct esp32s2_uart_s *priv = dev->priv; + uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M; + + if (enable) + { + /* Set to receive an interrupt when the TX holding FIFO is empty or + * a transmission is done. + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + modifyreg32(UART_INT_ENA_REG(priv->id), 0, ints_mask); +#endif + } + else + { + /* Disable the TX interrupts */ + + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_rxint + * + * Description: + * Enable or disable RX interrupts. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * enable - If true enables the RX interrupt, if false disables it. + * + ****************************************************************************/ + +static void esp32s2_rxint(struct uart_dev_s *dev, bool enable) +{ + struct esp32s2_uart_s *priv = dev->priv; + uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M | + UART_RXFIFO_FULL_INT_ENA_M; + + if (enable) + { + /* Receive an interrupt when there is anything in the RX FIFO + * (or when a RX timeout occurs). + * NOTE: RX timeout feature needs to be enabled. + */ +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_TOUT_EN_M); + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask); +#endif + } + else + { + modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0); + + /* Disable the RX interrupts */ + + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_rxavailable + * + * Description: + * Check if there is any data available to be read. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Return true if the RX FIFO is not empty and false if RX FIFO is empty. + * + ****************************************************************************/ + +static bool esp32s2_rxavailable(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + uint32_t status_reg; + uint32_t bytes; + + status_reg = getreg32(UART_STATUS_REG(priv->id)); + + bytes = REG_MASK(status_reg, UART_RXFIFO_CNT); + + return (bytes > 0) ? true : false; +} + +/**************************************************************************** + * Name: esp32s2_txready + * + * Description: + * Check if the transmit hardware is ready to send another byte. + * This is used to determine if send() method can be called. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Return true if the transmit hardware is ready to send another byte, + * false otherwise. + * + ****************************************************************************/ + +static bool esp32s2_txready(struct uart_dev_s *dev) +{ + return (esp32s2_lowputc_is_tx_fifo_full(dev->priv)) ? false : true; +} + +/**************************************************************************** + * Name: esp32s2_txempty + * + * Description: + * Verify if all characters have been sent. If for example, the UART + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Return true if the TX FIFO is empty, false if it is not. + * + ****************************************************************************/ + +static bool esp32s2_txempty(struct uart_dev_s *dev) +{ + uint32_t reg; + struct esp32s2_uart_s *priv = dev->priv; + + reg = getreg32(UART_INT_RAW_REG(priv->id)); + + reg = REG_MASK(reg, UART_TXFIFO_EMPTY_INT_RAW); + + return (reg > 0) ? true : false; +} + +/**************************************************************************** + * Name: esp32s2_send + * + * Description: + * Send a unique character + * + * Parameters: + * dev - Pointer to the serial driver struct. + * ch - Byte to be sent. + * + ****************************************************************************/ + +static void esp32s2_send(struct uart_dev_s *dev, int ch) +{ + esp32s2_lowputc_send_byte(dev->priv, ch); +} + +/**************************************************************************** + * Name: esp32s2_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * status - Pointer to a variable to store eventual error bits. + * + * Returned Values: + * Return the byte read from the RX FIFO. + * + ****************************************************************************/ + +static int esp32s2_receive(struct uart_dev_s *dev, unsigned int *status) +{ + uint32_t rx_fifo; + struct esp32s2_uart_s *priv = dev->priv; + + rx_fifo = getreg32(UART_FIFO_REG(priv->id)); + rx_fifo = REG_MASK(rx_fifo, UART_RXFIFO_RD_BYTE); + + /* Since we don't have error bits associated with receipt, we set zero */ + + *status = 0; + + return (int)rx_fifo; +} + +/**************************************************************************** + * Name: esp32s2_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT. + * + * Parameters: + * filep Pointer to a file structure instance. + * cmd The ioctl command. + * arg The argument of the ioctl cmd. + * + * Returned Value: + * Returns a non-negative number on success; A negated errno value is + * returned on any failure (see comments ioctl() for a list of appropriate + * errno values). + * + ****************************************************************************/ + +static int esp32s2_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + /* Get access to the internal instance of the driver through the file + * pointer. + */ + +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif + int ret = OK; + + /* Run the requested ioctl command. */ + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + + /* Get the internal driver data structure for debug purposes. */ + + case TIOCSERGSTRUCT: + { + struct esp32s2_uart_s *user = (struct esp32s2_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev->priv, sizeof(struct esp32s2_uart_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + + /* Fill a termios structure with the required information. */ + + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct esp32s2_uart_s *priv = (struct esp32s2_uart_s *)dev->priv; + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0; + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= (priv->oflow) ? CCTS_OFLOW : 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= (priv->iflow) ? CRTS_IFLOW : 0; +#endif + + /* Set the baud rate in the termiosp using the + * cfsetispeed interface. + */ + + cfsetispeed(termiosp, priv->baud); + + /* Return number of bits. */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct esp32s2_uart_s *priv = (struct esp32s2_uart_s *)dev->priv; + uint32_t baud; + uint32_t current_int_sts; + uint8_t parity; + uint8_t bits; + uint8_t stop2; +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; +#endif + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Get the target baud rate to change. */ + + baud = cfgetispeed(termiosp); + + /* Decode number of bits. */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + bits = 5; + break; + + case CS6: + bits = 6; + break; + + case CS7: + bits = 7; + break; + + case CS8: + bits = 8; + break; + + default: + ret = -EINVAL; + break; + } + + /* Decode parity. */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits. */ + + stop2 = (termiosp->c_cflag & CSTOPB) ? 1 : 0; + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif + + /* Verify that all settings are valid before + * performing the changes. + */ + + if (ret == OK) + { + /* Fill the private struct fields. */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = bits; + priv->stop_b2 = stop2; + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = iflow; +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = oflow; +#endif + + /* Effect the changes immediately - note that we do not + * implement TCSADRAIN or TCSAFLUSH, only TCSANOW option. + * See nuttx/libs/libc/termios/lib_tcsetattr.c + */ + + esp32s2_lowputc_disable_all_uart_int(priv, ¤t_int_sts); + ret = esp32s2_setup(dev); + + /* Restore the interrupt state */ + + esp32s2_lowputc_restore_all_uart_int(priv, ¤t_int_sts); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_rxflowcontrol + * + * Description: + * Called when upper half RX buffer is full (or exceeds configured + * watermark levels if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if UART activated RX flow control to block more incoming + * data. + * NOTE: ESP32-S2 has a hardware RX FIFO threshold mechanism to control + * RTS line and to stop receiving data. This is very similar to the concept + * behind upper watermark level. The hardware threshold is used here + * to control the RTS line. When setting the threshold to zero, RTS will + * immediately be asserted. If nbuffered = 0 or the lower watermark is + * crossed and the serial driver decides to disable RX flow control, the + * threshold will be changed to UART_RX_FLOW_THRHD_VALUE, which is almost + * half the HW RX FIFO capacity. It keeps some space to keep the data + * received between the RTS assertion and the stop by the sender. + * + * Input Parameters: + * dev - UART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool esp32s2_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + bool ret = false; + struct esp32s2_uart_s *priv = dev->priv; + if (priv->iflow) + { + if (nbuffered == 0 || upper == false) + { + /* Empty buffer, RTS should be de-asserted and logic in above + * layers should re-enable RX interrupt. + */ + + esp32s2_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2), + true); + esp32s2_rxint(dev, true); + ret = false; + } + else + { + /* If the RX buffer is not zero and watermarks are not enabled, + * then this function is called to announce RX buffer is full. + * The first thing it should do is to immediately assert RTS. + * Software RX FIFO is full, so besides asserting RTS, it's + * necessary to disable RX interrupts to prevent remaining bytes + * (that arrive after asserting RTS) to be pushed to the + * SW RX FIFO. + */ + + esp32s2_lowputc_set_iflow(priv, 0 , true); + esp32s2_rxint(dev, false); + ret = true; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT + +/**************************************************************************** + * Name: xtensa_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before xtensa_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in esp32s2_lowsetup. + * + ****************************************************************************/ + +void xtensa_earlyserialinit(void) +{ + /* NOTE: All GPIO configuration for the UARTs was performed in + * esp32s2_lowsetup + */ + + /* Disable all UARTS interrupts */ + + esp32s2_lowputc_disable_all_uart_int(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + esp32s2_lowputc_disable_all_uart_int(TTYS1_DEV.priv, NULL); +#endif + + /* Configure console in early step. + * Setup for other serials will be perfomed when the serial driver is + * open. + */ + +#ifdef HAVE_SERIAL_CONSOLE + esp32s2_setup(&CONSOLE_DEV); +#endif +} + +#endif /* USE_EARLYSERIALINIT */ + +/**************************************************************************** + * Name: xtensa_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that xtensa_earlyserialinit was called previously. + * + ****************************************************************************/ + +void xtensa_serialinit(void) +{ +#ifdef HAVE_SERIAL_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* At least one UART char driver will logically be registered */ + + uart_register("/dev/ttyS0", &TTYS0_DEV); + +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + uint32_t int_status; + + esp32s2_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + esp32s2_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status); +#endif + return ch; +} + +#else /* HAVE_UART_DEVICE */ + +/**************************************************************************** + * Name: xtensa_earlyserialinit, xtensa_serialinit, and up_putc + * + * Description: + * Stubs that may be needed. These stubs will be used if all UARTs are + * disabled. In that case, the logic in common/up_initialize() is not + * smart enough to know that there are not UARTs and will still expect + * these interfaces to be provided. + * This may be a special case where the upper and lower half serial layers + * are added but other device is used as console. + * For more details, take a look at: nuttx/arch/xtensa/src/common/xtensa.h + * + ****************************************************************************/ + +void xtensa_earlyserialinit(void) +{ +} + +void xtensa_serialinit(void) +{ +} + +int up_putc(int ch) +{ + return ch; +} + +#endif /* HAVE_UART_DEVICE */ +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * This up_putc is a utility when the serial driver is not ready yet but + * UART is selected and we have a basic lowsetup. + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + uint32_t int_status; + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + xtensa_lowputc('\r'); + } + + xtensa_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.c b/arch/xtensa/src/esp32s2/esp32s2_start.c new file mode 100644 index 00000000000..76f73d8cd81 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_start.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "xtensa.h" +#include "xtensa_attr.h" + +#include "hardware/esp32s2_rtccntl.h" +#include "esp32s2_clockconfig.h" +#include "esp32s2_region.h" +#include "esp32s2_start.h" +#include "esp32s2_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Address of the CPU0 IDLE thread */ + +uint32_t g_idlestack[IDLETHREAD_STACKWORDS] + __attribute__((aligned(16), section(".noinit"))); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * We arrive here after the bootloader finished loading the program from + * flash. The hardware is mostly uninitialized, and the app CPU is in + * reset. We do have a stack, so we can do the initialization in C. + * + ****************************************************************************/ + +void IRAM_ATTR __start(void) +{ + uint32_t *dest; + uint32_t regval; + uint32_t sp; + + /* Kill the watchdog timer */ + + regval = getreg32(RTC_CNTL_WDTCONFIG0_REG); + regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN; + putreg32(regval, RTC_CNTL_WDTCONFIG0_REG); + + regval = getreg32(DR_REG_BB_BASE + 0x48); /* DR_REG_BB_BASE+48 */ + regval &= ~(1 << 14); + putreg32(regval, DR_REG_BB_BASE + 0x48); + + /* Make sure that normal interrupts are disabled. This is really only an + * issue when we are started in un-usual ways (such as from IRAM). In this + * case, we can at least defer some unexpected interrupts left over from + * the last program execution. + */ + + up_irq_disable(); + + /* Set CPU frequency configured in board.h */ + + esp32s2_clockconfig(); + + esp32s2_lowsetup(); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization */ + + xtensa_earlyserialinit(); +#endif + + /* Move the stack to a known location. Although we were given a stack + * pointer at start-up, we don't know where that stack pointer is + * positioned with respect to our memory map. The only safe option is to + * switch to a well-known IDLE thread stack. + */ + + sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE; + __asm__ __volatile__("mov sp, %0\n" : : "r"(sp)); + + /* Make page 0 access raise an exception */ + + esp32s2_region_protection(); + + /* Move CPU0 exception vectors to IRAM */ + + __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (&_init_start)); + + showprogress('A'); + + /* Set .bss to zero */ + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; dest++) + { + *dest = 0; + } + + showprogress('B'); + + /* Initialize onboard resources */ + + esp32s2_board_initialize(); + + showprogress('C'); + + /* Bring up NuttX */ + + nx_start(); + for (; ; ); /* Should not return */ +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.h b/arch/xtensa/src/esp32s2/esp32s2_start.h new file mode 100644 index 00000000000..42628243da1 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_start.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_start.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_board_initialize + * + * Description: + * Board-specific logic is initialized by calling this function. This + * entry point is called early in the initialization -- after all memory + * has been configured but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_board_initialize(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_systemreset.c b/arch/xtensa/src/esp32s2/esp32s2_systemreset.c new file mode 100644 index 00000000000..9b26e597d70 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_systemreset.c @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_systemreset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "xtensa.h" +#include "hardware/esp32s2_rtccntl.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_systemreset + * + * Description: + * Internal reset logic. + * + ****************************************************************************/ + +void up_systemreset(void) +{ + putreg32(RTC_CNTL_SW_SYS_RST, RTC_CNTL_OPTIONS0_REG); + + /* Wait for the reset */ + + for (; ; ); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_timerisr.c b/arch/xtensa/src/esp32s2/esp32s2_timerisr.c new file mode 100644 index 00000000000..fd61e42595d --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_timerisr.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "clock/clock.h" +#include "xtensa_timer.h" +#include "xtensa.h" + +/**************************************************************************** + * Private data + ****************************************************************************/ + +static uint32_t g_tick_divisor; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: xtensa_getcount, xtensa_getcompare, and xtensa_setcompare + * + * Description: + * Lower level operations on Xtensa special registers. + * + ****************************************************************************/ + +/* Return the current value of the cycle count register */ + +static inline uint32_t xtensa_getcount(void) +{ + uint32_t count; + + __asm__ __volatile__ + ( + "rsr %0, CCOUNT" : "=r"(count) + ); + + return count; +} + +/* Return the old value of the compare register */ + +static inline uint32_t xtensa_getcompare(void) +{ + uint32_t compare; + + __asm__ __volatile__ + ( + "rsr %0, %1" : "=r"(compare) : "I"(XT_CCOMPARE) + ); + + return compare; +} + +/* Set the value of the compare register */ + +static inline void xtensa_setcompare(uint32_t compare) +{ + __asm__ __volatile__ + ( + "wsr %0, %1" : : "r"(compare), "I"(XT_CCOMPARE) + ); +} + +/**************************************************************************** + * Function: esp32s2_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + * Xtensa timers work by comparing a cycle counter with a preset value. + * Once the match occurs an interrupt is generated, and the handler has to + * set a new cycle count into the comparator. To avoid clock drift due to + * interrupt latency, the new cycle count is computed from the old, not the + * time the interrupt was serviced. However if a timer interrupt is ever + * serviced more than one tick late, it is necessary to process multiple + * ticks until the new cycle count is in the future, otherwise the next + * timer interrupt would not occur until after the cycle counter had + * wrapped (2^32 cycles later). + * + ****************************************************************************/ + +static int esp32s2_timerisr(int irq, uint32_t *regs, FAR void *arg) +{ + uint32_t divisor; + uint32_t compare; + uint32_t diff; + + divisor = g_tick_divisor; + do + { + /* Increment the compare register for the next tick */ + + compare = xtensa_getcompare(); + xtensa_setcompare(compare + divisor); + + /* Process one timer tick */ + + nxsched_process_timer(); + + /* Check if we are falling behind and need to process multiple timer + * interrupts. + */ + + diff = xtensa_getcount() - compare; + } + while (diff >= divisor); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t divisor; + uint32_t count; + + /* Configured the timer0 as the system timer. + * + * divisor = BOARD_CLOCK_FREQUENCY / ticks_per_sec + */ + + divisor = BOARD_CLOCK_FREQUENCY / CLOCKS_PER_SEC; + g_tick_divisor = divisor; + + /* Set up periodic timer */ + + count = xtensa_getcount(); + xtensa_setcompare(count + divisor); + + /* NOTE: Timer 0 is an internal interrupt source so we do not need to + * attach any peripheral ID to the dedicated CPU interrupt. + */ + + /* Attach the timer interrupt */ + + irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32s2_timerisr, NULL); + + /* Enable the timer 0 CPU interrupt. */ + + up_enable_irq(ESP32S2_CPUINT_TIMER0); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_user.c b/arch/xtensa/src/esp32s2/esp32s2_user.c new file mode 100644 index 00000000000..d0540b61678 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_user.c @@ -0,0 +1,396 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_user.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USE_TEXT_HEAP +extern uint32_t _stextheap; +extern uint32_t _etextheap; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USE_TEXT_HEAP +#ifdef CONFIG_ENDIAN_BIG +#error not implemented +#endif +#ifndef CONFIG_BUILD_FLAT +#error permission check not implemented +#endif + +/**************************************************************************** + * Name: load_uint8 + * + * Description: + * Fetch a byte using 32-bit aligned access. + * + ****************************************************************************/ + +static uint8_t load_uint8(const uint8_t *p) +{ + const uint32_t *aligned; + uint32_t value; + unsigned int offset; + + aligned = (const uint32_t *)(((uintptr_t)p) & ~3); + value = l32i(aligned); + offset = ((uintptr_t)p) & 3; + switch (offset) + { + case 0: + return value & 0xff; + case 1: + return (value >> 8) & 0xff; + case 2: + return (value >> 16) & 0xff; + case 3: + return (value >> 24) & 0xff; + } + + /* not reached */ + + PANIC(); +} + +/**************************************************************************** + * Name: store_uint8 + * + * Description: + * Store a byte using 32-bit aligned access. + * + ****************************************************************************/ + +static void store_uint8(uint8_t *p, uint8_t v) +{ + uint32_t *aligned; + uint32_t value; + unsigned int offset; + + aligned = (uint32_t *)(((uintptr_t)p) & ~3); + value = l32i(aligned); + offset = ((uintptr_t)p) & 3; + switch (offset) + { + case 0: + value = (value & 0xffffff00) | v; + break; + case 1: + value = (value & 0xffff00ff) | (v << 8); + break; + case 2: + value = (value & 0xff00ffff) | (v << 16); + break; + case 3: + value = (value & 0x00ffffff) | (v << 24); + break; + } + + s32i(aligned, value); +} + +/**************************************************************************** + * Name: decode_s8i + * + * Description: + * Decode S8I instruction using 32-bit aligned access. + * Return non-zero on successful decoding. + * + ****************************************************************************/ + +static int decode_s8i(const uint8_t *p, uint8_t *imm8, uint8_t *s, + uint8_t *t) +{ + /* 23 16 15 12 11 8 7 4 3 0 + * | imm8 |0 1 0 0| s | t |0 0 1 0| + */ + + uint8_t b0 = load_uint8(p); + uint8_t b1 = load_uint8(p + 1); + + if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x40) + { + *t = b0 >> 4; + *s = b1 & 0xf; + *imm8 = load_uint8(p + 2); + return 1; + } + + return 0; +} + +/**************************************************************************** + * Name: decode_s16i + * + * Description: + * Decode S16I instruction using 32-bit aligned access. + * Return non-zero on successful decoding. + * + ****************************************************************************/ + +static int decode_s16i(const uint8_t *p, uint8_t *imm8, uint8_t *s, + uint8_t *t) +{ + /* 23 16 15 12 11 8 7 4 3 0 + * | imm8 |0 1 0 1| s | t |0 0 1 0| + */ + + uint8_t b0 = load_uint8(p); + uint8_t b1 = load_uint8(p + 1); + + if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x50) + { + *t = b0 >> 4; + *s = b1 & 0xf; + *imm8 = load_uint8(p + 2); + return 1; + } + + return 0; +} + +/**************************************************************************** + * Name: decode_l8ui + * + * Description: + * Decode L8UI instruction using 32-bit aligned access. + * Return non-zero on successful decoding. + * + ****************************************************************************/ + +static int decode_l8ui(const uint8_t *p, uint8_t *imm8, uint8_t *s, + uint8_t *t) +{ + /* 23 16 15 12 11 8 7 4 3 0 + * | imm8 |0 0 0 0| s | t |0 0 1 0| + */ + + uint8_t b0 = load_uint8(p); + uint8_t b1 = load_uint8(p + 1); + + if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0) + { + *t = b0 >> 4; + *s = b1 & 0xf; + *imm8 = load_uint8(p + 2); + return 1; + } + + return 0; +} + +/**************************************************************************** + * Name: decode_l16ui + * + * Description: + * Decode L16UI instruction using 32-bit aligned access. + * Return non-zero on successful decoding. + * + ****************************************************************************/ + +static int decode_l16ui(const uint8_t *p, uint8_t *imm8, uint8_t *s, + uint8_t *t) +{ + /* 23 16 15 12 11 8 7 4 3 0 + * | imm8 |0 0 0 1| s | t |0 0 1 0| + */ + + uint8_t b0 = load_uint8(p); + uint8_t b1 = load_uint8(p + 1); + + if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x10) + { + *t = b0 >> 4; + *s = b1 & 0xf; + *imm8 = load_uint8(p + 2); + return 1; + } + + return 0; +} + +/**************************************************************************** + * Name: advance_pc + * + * Description: + * Advance PC register by the given value. + * + ****************************************************************************/ + +static void advance_pc(uint32_t *regs, int diff) +{ + uint32_t nextpc; + + /* Advance to the next instruction. */ + + nextpc = regs[REG_PC] + diff; +#if XCHAL_HAVE_LOOPS + /* See Xtensa ISA 4.3.2.4 Loopback Semantics */ + + if (regs[REG_LCOUNT] != 0 && nextpc == regs[REG_LEND]) + { + regs[REG_LCOUNT]--; + nextpc = regs[REG_LBEG]; + } + +#endif + regs[REG_PC] = nextpc; +} + +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_user + * + * Description: + * ESP32S2-specific user exception handler. + * + ****************************************************************************/ + +uint32_t *xtensa_user(int exccause, uint32_t *regs) +{ +#ifdef CONFIG_ARCH_USE_TEXT_HEAP + /* Emulate byte access for module text. + * + * ESP32S2 only allows word-aligned accesses to the instruction memory + * regions. A non-aligned access raises a LoadStoreErrorCause exception. + * We catch those exception and emulate byte access here because it's + * necessary in a few places during dynamic code loading: + * + * - memcpy as a part of read(2) when loading code from a file system. + * - relocation needs to inspect and modify text. + * + * (thus binfo() is used below) + */ + + if (exccause == XCHAL_EXCCAUSE_LOAD_STORE_ERROR && + (uintptr_t)&_stextheap <= regs[REG_EXCVADDR] && + (uintptr_t)&_etextheap > regs[REG_EXCVADDR]) + { + uint8_t *pc = (uint8_t *)regs[REG_PC]; + uint8_t imm8; + uint8_t s; + uint8_t t; + + binfo("XCHAL_EXCCAUSE_LOAD_STORE_ERROR at %p, pc=%p\n", + (FAR void *)regs[REG_EXCVADDR], + pc); + + if (decode_s8i(pc, &imm8, &s, &t)) + { + binfo("Emulating S8I imm8=%u, s=%u (%p), t=%u (%p)\n", + (unsigned int)imm8, + (unsigned int)s, + (void *)regs[REG_A0 + s], + (unsigned int)t, + (void *)regs[REG_A0 + t]); + + DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]); + store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8, + regs[REG_A0 + t]); + advance_pc(regs, 3); + return regs; + } + else if (decode_s16i(pc, &imm8, &s, &t)) + { + binfo("Emulating S16I imm8=%u, s=%u (%p), t=%u (%p)\n", + (unsigned int)imm8, + (unsigned int)s, + (void *)regs[REG_A0 + s], + (unsigned int)t, + (void *)regs[REG_A0 + t]); + + DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]); + store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8, + regs[REG_A0 + t]); + store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8 + 1, + regs[REG_A0 + t] >> 8); + advance_pc(regs, 3); + return regs; + } + else if (decode_l8ui(pc, &imm8, &s, &t)) + { + binfo("Emulating L8UI imm8=%u, s=%u (%p), t=%u (%p)\n", + (unsigned int)imm8, + (unsigned int)s, + (void *)regs[REG_A0 + s], + (unsigned int)t, + (void *)regs[REG_A0 + t]); + + DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]); + regs[REG_A0 + t] = load_uint8(((uint8_t *)regs[REG_A0 + s]) + + imm8); + advance_pc(regs, 3); + return regs; + } + else if (decode_l16ui(pc, &imm8, &s, &t)) + { + binfo("Emulating L16UI imm8=%u, s=%u (%p), t=%u (%p)\n", + (unsigned int)imm8, + (unsigned int)s, + (void *)regs[REG_A0 + s], + (unsigned int)t, + (void *)regs[REG_A0 + t]); + + DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]); + uint8_t lo = load_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8); + uint8_t hi = load_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8 + 1); + regs[REG_A0 + t] = (hi << 8) | lo; + advance_pc(regs, 3); + return regs; + } + } + +#endif + /* xtensa_user_panic never returns. */ + + xtensa_user_panic(exccause, regs); + + while (1) + { + } +} diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h new file mode 100644 index 00000000000..68dd21450c4 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h @@ -0,0 +1,780 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AES_KEY_0_REG register + * AES key register 0 + */ + +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) + +/* AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_0 0xFFFFFFFF +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFF +#define AES_KEY_0_S 0 + +/* AES_KEY_1_REG register + * AES key register 1 + */ + +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) + +/* AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_1 0xFFFFFFFF +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFF +#define AES_KEY_1_S 0 + +/* AES_KEY_2_REG register + * AES key register 2 + */ + +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) + +/* AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_2 0xFFFFFFFF +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFF +#define AES_KEY_2_S 0 + +/* AES_KEY_3_REG register + * AES key register 3 + */ + +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) + +/* AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_3 0xFFFFFFFF +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFF +#define AES_KEY_3_S 0 + +/* AES_KEY_4_REG register + * AES key register 4 + */ + +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) + +/* AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_4 0xFFFFFFFF +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFF +#define AES_KEY_4_S 0 + +/* AES_KEY_5_REG register + * AES key register 5 + */ + +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) + +/* AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_5 0xFFFFFFFF +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFF +#define AES_KEY_5_S 0 + +/* AES_KEY_6_REG register + * AES key register 6 + */ + +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) + +/* AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_6 0xFFFFFFFF +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFF +#define AES_KEY_6_S 0 + +/* AES_KEY_7_REG register + * AES key register 7 + */ + +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) + +/* AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_7 0xFFFFFFFF +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFF +#define AES_KEY_7_S 0 + +/* AES_TEXT_IN_0_REG register + * Source data register 0 + */ + +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) + +/* AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_0 0xFFFFFFFF +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFF +#define AES_TEXT_IN_0_S 0 + +/* AES_TEXT_IN_1_REG register + * Source data register 1 + */ + +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) + +/* AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_1 0xFFFFFFFF +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFF +#define AES_TEXT_IN_1_S 0 + +/* AES_TEXT_IN_2_REG register + * Source data register 2 + */ + +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) + +/* AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_2 0xFFFFFFFF +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFF +#define AES_TEXT_IN_2_S 0 + +/* AES_TEXT_IN_3_REG register + * Source data register 3 + */ + +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) + +/* AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_3 0xFFFFFFFF +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFF +#define AES_TEXT_IN_3_S 0 + +/* AES_TEXT_OUT_0_REG register + * Result data register 0 + */ + +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) + +/* AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_0 0xFFFFFFFF +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFF +#define AES_TEXT_OUT_0_S 0 + +/* AES_TEXT_OUT_1_REG register + * Result data register 1 + */ + +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) + +/* AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_1 0xFFFFFFFF +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFF +#define AES_TEXT_OUT_1_S 0 + +/* AES_TEXT_OUT_2_REG register + * Result data register 2 + */ + +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) + +/* AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_2 0xFFFFFFFF +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFF +#define AES_TEXT_OUT_2_S 0 + +/* AES_TEXT_OUT_3_REG register + * Result data register 3 + */ + +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) + +/* AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_3 0xFFFFFFFF +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFF +#define AES_TEXT_OUT_3_S 0 + +/* AES_MODE_REG register + * AES working mode configuration register + */ + +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) + +/* AES_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * Typical AES working mode. + * & + * 0x0(AES_EN_128): AES-EN-128 # + * 0x1(AES_EN_192): AES-EN-192 # + * 0x2(AES_EN_256): AES-EN-256 # + * 0x4(AES_DE_128): AES-DE-128 # + * 0x5(AES_DE_192): AES-DE-192 # + * 0x6(AES_DE_256): AES-DE-256 + * & + */ + +#define AES_MODE 0x00000007 +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007 +#define AES_MODE_S 0 + +/* AES_ENDIAN_REG register + * Endian configuration register + */ + +#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) + +/* AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; + * Defines the endianness of input and output texts. + * & + * [1:0] key endian # + * [3:2] text_in endian or in_stream endian # + * [5:4] text_out endian or out_stream endian # + * & + */ + +#define AES_ENDIAN 0x0000003F +#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) +#define AES_ENDIAN_V 0x0000003F +#define AES_ENDIAN_S 0 + +/* AES_TRIGGER_REG register + * Operation start controlling register + */ + +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) + +/* AES_TRIGGER : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start AES operation. + */ + +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001 +#define AES_TRIGGER_S 0 + +/* AES_STATE_REG register + * Operation status register + */ + +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) + +/* AES_STATE : RO; bitpos: [1:0]; default: 0; + * Stores the working status of the AES Accelerator. For details, see Table + * 3 for Typical AES working mode and Table 9 for DMA AES working mode. + * For typical AES; 0 = idle; 1 = busy. + * For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. + */ + +#define AES_STATE 0x00000003 +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003 +#define AES_STATE_S 0 + +/* AES_IV_0_REG register + * initialization vector + */ + +#define AES_IV_0_REG (DR_REG_AES_BASE + 0x50) + +/* AES_IV_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_0 0xFFFFFFFF +#define AES_IV_0_M (AES_IV_0_V << AES_IV_0_S) +#define AES_IV_0_V 0xFFFFFFFF +#define AES_IV_0_S 0 + +/* AES_IV_1_REG register + * initialization vector + */ + +#define AES_IV_1_REG (DR_REG_AES_BASE + 0x54) + +/* AES_IV_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_1 0xFFFFFFFF +#define AES_IV_1_M (AES_IV_1_V << AES_IV_1_S) +#define AES_IV_1_V 0xFFFFFFFF +#define AES_IV_1_S 0 + +/* AES_IV_2_REG register + * initialization vector + */ + +#define AES_IV_2_REG (DR_REG_AES_BASE + 0x58) + +/* AES_IV_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_2 0xFFFFFFFF +#define AES_IV_2_M (AES_IV_2_V << AES_IV_2_S) +#define AES_IV_2_V 0xFFFFFFFF +#define AES_IV_2_S 0 + +/* AES_IV_3_REG register + * initialization vector + */ + +#define AES_IV_3_REG (DR_REG_AES_BASE + 0x5c) + +/* AES_IV_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_3 0xFFFFFFFF +#define AES_IV_3_M (AES_IV_3_V << AES_IV_3_S) +#define AES_IV_3_V 0xFFFFFFFF +#define AES_IV_3_S 0 + +/* AES_H_0_REG register + * GCM hash subkey + */ + +#define AES_H_0_REG (DR_REG_AES_BASE + 0x60) + +/* AES_H_0 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_0 0xFFFFFFFF +#define AES_H_0_M (AES_H_0_V << AES_H_0_S) +#define AES_H_0_V 0xFFFFFFFF +#define AES_H_0_S 0 + +/* AES_H_1_REG register + * GCM hash subkey + */ + +#define AES_H_1_REG (DR_REG_AES_BASE + 0x64) + +/* AES_H_1 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_1 0xFFFFFFFF +#define AES_H_1_M (AES_H_1_V << AES_H_1_S) +#define AES_H_1_V 0xFFFFFFFF +#define AES_H_1_S 0 + +/* AES_H_2_REG register + * GCM hash subkey + */ + +#define AES_H_2_REG (DR_REG_AES_BASE + 0x68) + +/* AES_H_2 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_2 0xFFFFFFFF +#define AES_H_2_M (AES_H_2_V << AES_H_2_S) +#define AES_H_2_V 0xFFFFFFFF +#define AES_H_2_S 0 + +/* AES_H_3_REG register + * GCM hash subkey + */ + +#define AES_H_3_REG (DR_REG_AES_BASE + 0x6c) + +/* AES_H_3 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_3 0xFFFFFFFF +#define AES_H_3_M (AES_H_3_V << AES_H_3_S) +#define AES_H_3_V 0xFFFFFFFF +#define AES_H_3_S 0 + +/* AES_J0_0_REG register + * J0 + */ + +#define AES_J0_0_REG (DR_REG_AES_BASE + 0x70) + +/* AES_J0_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_0 0xFFFFFFFF +#define AES_J0_0_M (AES_J0_0_V << AES_J0_0_S) +#define AES_J0_0_V 0xFFFFFFFF +#define AES_J0_0_S 0 + +/* AES_J0_1_REG register + * J0 + */ + +#define AES_J0_1_REG (DR_REG_AES_BASE + 0x74) + +/* AES_J0_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_1 0xFFFFFFFF +#define AES_J0_1_M (AES_J0_1_V << AES_J0_1_S) +#define AES_J0_1_V 0xFFFFFFFF +#define AES_J0_1_S 0 + +/* AES_J0_2_REG register + * J0 + */ + +#define AES_J0_2_REG (DR_REG_AES_BASE + 0x78) + +/* AES_J0_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_2 0xFFFFFFFF +#define AES_J0_2_M (AES_J0_2_V << AES_J0_2_S) +#define AES_J0_2_V 0xFFFFFFFF +#define AES_J0_2_S 0 + +/* AES_J0_3_REG register + * J0 + */ + +#define AES_J0_3_REG (DR_REG_AES_BASE + 0x7c) + +/* AES_J0_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_3 0xFFFFFFFF +#define AES_J0_3_M (AES_J0_3_V << AES_J0_3_S) +#define AES_J0_3_V 0xFFFFFFFF +#define AES_J0_3_S 0 + +/* AES_T0_0_REG register + * T0 + */ + +#define AES_T0_0_REG (DR_REG_AES_BASE + 0x80) + +/* AES_T0_0 : RO; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_0 0xFFFFFFFF +#define AES_T0_0_M (AES_T0_0_V << AES_T0_0_S) +#define AES_T0_0_V 0xFFFFFFFF +#define AES_T0_0_S 0 + +/* AES_T0_1_REG register + * T0 + */ + +#define AES_T0_1_REG (DR_REG_AES_BASE + 0x84) + +/* AES_T0_1 : RO; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_1 0xFFFFFFFF +#define AES_T0_1_M (AES_T0_1_V << AES_T0_1_S) +#define AES_T0_1_V 0xFFFFFFFF +#define AES_T0_1_S 0 + +/* AES_T0_2_REG register + * T0 + */ + +#define AES_T0_2_REG (DR_REG_AES_BASE + 0x88) + +/* AES_T0_2 : RO; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_2 0xFFFFFFFF +#define AES_T0_2_M (AES_T0_2_V << AES_T0_2_S) +#define AES_T0_2_V 0xFFFFFFFF +#define AES_T0_2_S 0 + +/* AES_T0_3_REG register + * T0 + */ + +#define AES_T0_3_REG (DR_REG_AES_BASE + 0x8c) + +/* AES_T0_3 : RO; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_3 0xFFFFFFFF +#define AES_T0_3_M (AES_T0_3_V << AES_T0_3_S) +#define AES_T0_3_V 0xFFFFFFFF +#define AES_T0_3_S 0 + +/* AES_DMA_ENABLE_REG register + * DMA enable register + */ + +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) + +/* AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * Defines the working mode of the AES Accelerator. For details, see Table 1. + * 1'h0: typical AES operation + * 1'h1: DMA-AES operation + */ + +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001 +#define AES_DMA_ENABLE_S 0 + +/* AES_BLOCK_MODE_REG register + * Block operation type register + */ + +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) + +/* AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * DMA-AES working mode. For details, see Table 8. + * & + * 3'h0(BLOCK_MODE_ECB): ECB # + * 3'h1(BLOCK_MODE_CBC): CBC # + * 3'h2(BLOCK_MODE_OFB): OFB # + * 3'h3(BLOCK_MODE_CTR): CTR # + * 3'h4(BLOCK_MODE_CFB8): CFB-8 # + * 3'h5(BLOCK_MODE_CFB128): CFB-128 # + * 3'h6(BLOCK_MODE_GCM): GCM + * & + */ + +#define AES_BLOCK_MODE 0x00000007 +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007 +#define AES_BLOCK_MODE_S 0 + +/* AES_BLOCK_NUM_REG register + * Block number configuration register + */ + +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) + +/* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the Block Number of plaintext or cipertext when the AES + * Accelerator operates under the DMA-AES working mode. For details, see + * Section 1.5.4. + */ + +#define AES_BLOCK_NUM 0xFFFFFFFF +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFF +#define AES_BLOCK_NUM_S 0 + +/* AES_INC_SEL_REG register + * Standard incrementing function register + */ + +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) + +/* AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * Defines the Standard Incrementing Function for CTR block operation. Set + * this bit to 0 or 1 to choose INC 32 or INC 128 . + */ + +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001 +#define AES_INC_SEL_S 0 + +/* AES_AAD_BLOCK_NUM_REG register + * AAD block number configuration register + */ + +#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) + +/* AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the ADD Block Number for the GCM operation. + */ + +#define AES_AAD_BLOCK_NUM 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) +#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_S 0 + +/* AES_REMAINDER_BIT_NUM_REG register + * Remainder bit number of plaintext/ciphertext + */ + +#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) + +/* AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; + * Stores the Remainder Bit Number for the GCM operation. + */ + +#define AES_REMAINDER_BIT_NUM 0x0000007F +#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) +#define AES_REMAINDER_BIT_NUM_V 0x0000007F +#define AES_REMAINDER_BIT_NUM_S 0 + +/* AES_CONTINUE_REG register + * Operation continue controlling register + */ + +#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) + +/* AES_CONTINUE : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to continue AES operation. + */ + +#define AES_CONTINUE (BIT(0)) +#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) +#define AES_CONTINUE_V 0x00000001 +#define AES_CONTINUE_S 0 + +/* AES_INT_CLR_REG register + * DMA-AES interrupt clear register + */ + +#define AES_INT_CLR_REG (DR_REG_AES_BASE + 0xac) + +/* AES_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear AES interrupt. + */ + +#define AES_INT_CLR (BIT(0)) +#define AES_INT_CLR_M (AES_INT_CLR_V << AES_INT_CLR_S) +#define AES_INT_CLR_V 0x00000001 +#define AES_INT_CLR_S 0 + +/* AES_INT_ENA_REG register + * DMA-AES interrupt enable register + */ + +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) + +/* AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. + */ + +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001 +#define AES_INT_ENA_S 0 + +/* AES_DATE_REG register + * Version control register + */ + +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) + +/* AES_DATE : R/W; bitpos: [29:0]; default: 538510612; + * Version control register + */ + +#define AES_DATE 0x3FFFFFFF +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFF +#define AES_DATE_S 0 + +/* AES_DMA_EXIT_REG register + * Operation exit controlling register + */ + +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) + +/* AES_DMA_EXIT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to exit AES operation. This register is only effective + * for DMA-AES operation. + */ + +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001 +#define AES_DMA_EXIT_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h new file mode 100644 index 00000000000..0cc076b5d2c --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h @@ -0,0 +1,3282 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) + +/* EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_S 0 + +/* EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) + +/* EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_S 0 + +/* EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) + +/* EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_S 0 + +/* EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) + +/* EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_3 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_S 0 + +/* EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) + +/* EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_4 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_S 0 + +/* EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) + +/* EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_5 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_S 0 + +/* EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) + +/* EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_6 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_S 0 + +/* EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) + +/* EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_7 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_S 0 + +/* EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) + +/* EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_S 0 + +/* EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) + +/* EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_S 0 + +/* EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) + +/* EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_S 0 + +/* EFUSE_RD_WR_DIS_REG register + * Register 0 of BLOCK0. + */ + +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) + +/* EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disables programming of individual eFuses. + */ + +#define EFUSE_WR_DIS 0xFFFFFFFF +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFF +#define EFUSE_WR_DIS_S 0 + +/* EFUSE_RD_REPEAT_DATA0_REG register + * Register 1 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) + +/* EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFH 0x00000003 +#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) +#define EFUSE_VDD_SPI_DREFH_V 0x00000003 +#define EFUSE_VDD_SPI_DREFH_S 30 + +/* EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001 +#define EFUSE_VDD_SPI_MODECURLIM_S 29 + +/* EFUSE_RPT4_RESERVED0 : RO; bitpos: [28:27]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED0 0x00000003 +#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) +#define EFUSE_RPT4_RESERVED0_V 0x00000003 +#define EFUSE_RPT4_RESERVED0_S 27 + +/* EFUSE_USB_FORCE_NOPERSIST : RO; bitpos: [26]; default: 0; + * If set, forces USB BVALID to 1. + */ + +#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_M (EFUSE_USB_FORCE_NOPERSIST_V << EFUSE_USB_FORCE_NOPERSIST_S) +#define EFUSE_USB_FORCE_NOPERSIST_V 0x00000001 +#define EFUSE_USB_FORCE_NOPERSIST_S 26 + +/* EFUSE_EXT_PHY_ENABLE : RO; bitpos: [25]; default: 0; + * Set this bit to enable external USB PHY. + */ + +#define EFUSE_EXT_PHY_ENABLE (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_M (EFUSE_EXT_PHY_ENABLE_V << EFUSE_EXT_PHY_ENABLE_S) +#define EFUSE_EXT_PHY_ENABLE_V 0x00000001 +#define EFUSE_EXT_PHY_ENABLE_S 25 + +/* EFUSE_USB_EXCHG_PINS : RO; bitpos: [24]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + +#define EFUSE_USB_EXCHG_PINS (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001 +#define EFUSE_USB_EXCHG_PINS_S 24 + +/* EFUSE_USB_DREFL : RO; bitpos: [23:22]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of + * 80 mV, stored in eFuse. + */ + +#define EFUSE_USB_DREFL 0x00000003 +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003 +#define EFUSE_USB_DREFL_S 22 + +/* EFUSE_USB_DREFH : RO; bitpos: [21:20]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 + * mV, stored in eFuse. + */ + +#define EFUSE_USB_DREFH 0x00000003 +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003 +#define EFUSE_USB_DREFH_S 20 + +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [19]; default: 0; + * Disables flash encryption when in download boot modes. + */ + +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 + +/* EFUSE_HARD_DIS_JTAG : RO; bitpos: [18]; default: 0; + * Hardware disables JTAG permanently. + */ + +#define EFUSE_HARD_DIS_JTAG (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_M (EFUSE_HARD_DIS_JTAG_V << EFUSE_HARD_DIS_JTAG_S) +#define EFUSE_HARD_DIS_JTAG_V 0x00000001 +#define EFUSE_HARD_DIS_JTAG_S 18 + +/* EFUSE_SOFT_DIS_JTAG : RO; bitpos: [17]; default: 0; + * Software disables JTAG. When software disabled, JTAG can be activated + * temporarily by HMAC peripheral. + */ + +#define EFUSE_SOFT_DIS_JTAG (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000001 +#define EFUSE_SOFT_DIS_JTAG_S 17 + +/* EFUSE_DIS_EFUSE_ATE_WR : RO; bitpos: [16]; default: 0; */ + +#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_M (EFUSE_DIS_EFUSE_ATE_WR_V << EFUSE_DIS_EFUSE_ATE_WR_S) +#define EFUSE_DIS_EFUSE_ATE_WR_V 0x00000001 +#define EFUSE_DIS_EFUSE_ATE_WR_S 16 + +/* EFUSE_DIS_BOOT_REMAP : RO; bitpos: [15]; default: 0; + * Disables capability to Remap RAM to ROM address space. + */ + +#define EFUSE_DIS_BOOT_REMAP (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_M (EFUSE_DIS_BOOT_REMAP_V << EFUSE_DIS_BOOT_REMAP_S) +#define EFUSE_DIS_BOOT_REMAP_V 0x00000001 +#define EFUSE_DIS_BOOT_REMAP_S 15 + +/* EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + +#define EFUSE_DIS_CAN (BIT(14)) +#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) +#define EFUSE_DIS_CAN_V 0x00000001 +#define EFUSE_DIS_CAN_S 14 + +/* EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ + +#define EFUSE_DIS_USB (BIT(13)) +#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) +#define EFUSE_DIS_USB_V 0x00000001 +#define EFUSE_DIS_USB_S 13 + +/* EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001 +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 + +/* EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; + * Disables Dcache when SoC is in Download mode. + */ + +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 + +/* EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Disables Icache when SoC is in Download mode. + */ + +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 + +/* EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + +#define EFUSE_DIS_DCACHE (BIT(9)) +#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) +#define EFUSE_DIS_DCACHE_V 0x00000001 +#define EFUSE_DIS_DCACHE_S 9 + +/* EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001 +#define EFUSE_DIS_ICACHE_S 8 + +/* EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001 +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 + +/* EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Disables software reading from individual eFuse blocks (BLOCK4-10). + */ + +#define EFUSE_RD_DIS 0x0000007F +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007F +#define EFUSE_RD_DIS_S 0 + +/* EFUSE_RD_REPEAT_DATA1_REG register + * Register 2 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) + +/* EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of KEY1. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_1 0x0000000F +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000F +#define EFUSE_KEY_PURPOSE_1_S 28 + +/* EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of KEY0. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_0 0x0000000F +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000F +#define EFUSE_KEY_PURPOSE_0_S 24 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * If set, revokes use of secure boot key digest 2. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * If set, revokes use of secure boot key digest 1. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * If set, revokes use of secure boot key digest 0. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 + +/* EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Enables encryption and decryption, when an SPI boot mode is set. Feature + * is enabled 1 or 3 bits are set in the eFuse, disabled otherwise. + */ + +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 + +/* EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock + * cycles; 1: 80,000 slow clock cycles; 2: 160,000 slow clock cycles; 3: + * 320,000 slow clock cycles. + */ + +#define EFUSE_WDT_DELAY_SEL 0x00000003 +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003 +#define EFUSE_WDT_DELAY_SEL_S 16 + +/* EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + +#define EFUSE_VDD_SPI_DCAP 0x00000003 +#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) +#define EFUSE_VDD_SPI_DCAP_V 0x00000003 +#define EFUSE_VDD_SPI_DCAP_S 14 + +/* EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance; 1: 6 K; 2: 4 + * K; 3: 2 K. + */ + +#define EFUSE_VDD_SPI_INIT 0x00000003 +#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) +#define EFUSE_VDD_SPI_INIT_V 0x00000003 +#define EFUSE_VDD_SPI_INIT_S 12 + +/* EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 + * mA/(8+d). + */ + +#define EFUSE_VDD_SPI_DCURLIM 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) +#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_S 9 + +/* EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001 +#define EFUSE_VDD_SPI_ENCURLIM_S 8 + +/* EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) +#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001 +#define EFUSE_VDD_SPI_EN_INIT_S 7 + +/* EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; + * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI + * LDO. + */ + +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) +#define EFUSE_VDD_SPI_FORCE_V 0x00000001 +#define EFUSE_VDD_SPI_FORCE_S 6 + +/* EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; + * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to + * 1.8 V LDO; 1: VDD_SPI connects to VDD_RTC_IO. + */ + +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) +#define EFUSE_VDD_SPI_TIEH_V 0x00000001 +#define EFUSE_VDD_SPI_TIEH_S 5 + +/* EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; + * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is + * powered on. + */ + +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) +#define EFUSE_VDD_SPI_XPD_V 0x00000001 +#define EFUSE_VDD_SPI_XPD_S 4 + +/* EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFL 0x00000003 +#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) +#define EFUSE_VDD_SPI_DREFL_V 0x00000003 +#define EFUSE_VDD_SPI_DREFL_S 2 + +/* EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFM 0x00000003 +#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) +#define EFUSE_VDD_SPI_DREFM_V 0x00000003 +#define EFUSE_VDD_SPI_DREFM_S 0 + +/* EFUSE_RD_REPEAT_DATA2_REG register + * Register 3 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) + +/* EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash startup delay after SoC power-up, in unit of (ms/2). + * When the value is 15, delay is 7.5 ms. + */ + +#define EFUSE_FLASH_TPUW 0x0000000F +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000F +#define EFUSE_FLASH_TPUW_S 28 + +/* EFUSE_RPT4_RESERVED1 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED1 0x0000003F +#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) +#define EFUSE_RPT4_RESERVED1_V 0x0000003F +#define EFUSE_RPT4_RESERVED1_S 22 + +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable aggressive secure boot key revocation mode. + */ + +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 + +/* EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001 +#define EFUSE_SECURE_BOOT_EN_S 20 + +/* EFUSE_KEY_PURPOSE_6 : RO; bitpos: [19:16]; default: 0; + * Purpose of KEY6. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_6 0x0000000F +#define EFUSE_KEY_PURPOSE_6_M (EFUSE_KEY_PURPOSE_6_V << EFUSE_KEY_PURPOSE_6_S) +#define EFUSE_KEY_PURPOSE_6_V 0x0000000F +#define EFUSE_KEY_PURPOSE_6_S 16 + +/* EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of KEY5. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_5 0x0000000F +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000F +#define EFUSE_KEY_PURPOSE_5_S 12 + +/* EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of KEY4. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_4 0x0000000F +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000F +#define EFUSE_KEY_PURPOSE_4_S 8 + +/* EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of KEY3. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_3 0x0000000F +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000F +#define EFUSE_KEY_PURPOSE_3_S 4 + +/* EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of KEY2. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_2 0x0000000F +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000F +#define EFUSE_KEY_PURPOSE_2_S 0 + +/* EFUSE_RD_REPEAT_DATA3_REG register + * Register 4 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) + +/* EFUSE_RPT4_RESERVED2 : RO; bitpos: [31:27]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED2 0x0000001F +#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) +#define EFUSE_RPT4_RESERVED2_V 0x0000001F +#define EFUSE_RPT4_RESERVED2_S 27 + +/* EFUSE_SECURE_VERSION : RO; bitpos: [26:11]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + +#define EFUSE_SECURE_VERSION 0x0000FFFF +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFF +#define EFUSE_SECURE_VERSION_S 11 + +/* EFUSE_FORCE_SEND_RESUME : RO; bitpos: [10]; default: 0; + * If set, forces ROM code to send an SPI flash resume command during SPI + * boot. + */ + +#define EFUSE_FORCE_SEND_RESUME (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001 +#define EFUSE_FORCE_SEND_RESUME_S 10 + +/* EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * SPI flash type. 0: maximum four data lines, 1: eight data lines. + */ + +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001 +#define EFUSE_FLASH_TYPE_S 9 + +/* EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * Set default power supply for GPIO33-GPIO37, set when SPI flash is + * initialized. 0: VDD3P3_CPU; 1: VDD_SPI. + */ + +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001 +#define EFUSE_PIN_POWER_SELECTION_S 8 + +/* EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UART boot message output mode. + * & + * 00: Enabled.# + * 01: Enable when GPIO46 is low at reset.# + * 10: Enable when GPIO46 is high at reset.# + * 11: Disabled. + * & + */ + +#define EFUSE_UART_PRINT_CONTROL 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_S 6 + +/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode (read/write flash only). + */ + +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 + +/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Set this bit to disable use of USB in UART download boot mode. + */ + +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 + +/* EFUSE_RPT4_RESERVED3 : RO; bitpos: [3]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED3 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) +#define EFUSE_RPT4_RESERVED3_V 0x00000001 +#define EFUSE_RPT4_RESERVED3_S 3 + +/* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; + * Selects the default UART for printing boot messages. 0: UART0; 1: UART1. + */ + +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) +#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001 +#define EFUSE_UART_PRINT_CHANNEL_S 2 + +/* EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; + * Set this bit to disable Legacy SPI boot mode. + */ + +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001 +#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 + +/* EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable all download boot modes. + */ + +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 + +/* EFUSE_RD_REPEAT_DATA4_REG register + * Register 5 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) + +/* EFUSE_RPT4_RESERVED4 : RO; bitpos: [23:0]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED4 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_M (EFUSE_RPT4_RESERVED4_V << EFUSE_RPT4_RESERVED4_S) +#define EFUSE_RPT4_RESERVED4_V 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_0_REG register + * Register 0 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) + +/* EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + +#define EFUSE_MAC_0 0xFFFFFFFF +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFF +#define EFUSE_MAC_0_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_1_REG register + * Register 1 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) + +/* EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0; + * Stores the zeroth part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S) +#define EFUSE_SPI_PAD_CONF_0_V 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_S 16 + +/* EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + +#define EFUSE_MAC_1 0x0000FFFF +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFF +#define EFUSE_MAC_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_2_REG register + * Register 2 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) + +/* EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) +#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_3_REG register + * Register 3 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) + +/* EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the zeroth part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_0 0x00003FFF +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFF +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/* EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; + * Stores the second part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) +#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_4_REG register + * Register 4 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) + +/* EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the fist part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_5_REG register + * Register 5 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) + +/* EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_0_REG register + * Register 0 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_0_REG (DR_REG_EFUSE_BASE + 0x5c) + +/* EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_1_REG register + * Register 1 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_1_REG (DR_REG_EFUSE_BASE + 0x60) + +/* EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_2_REG register + * Register 2 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_2_REG (DR_REG_EFUSE_BASE + 0x64) + +/* EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_3_REG register + * Register 3 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_3_REG (DR_REG_EFUSE_BASE + 0x68) + +/* EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_4_REG register + * Register 4 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_4_REG (DR_REG_EFUSE_BASE + 0x6c) + +/* EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_5_REG register + * Register 5 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_5_REG (DR_REG_EFUSE_BASE + 0x70) + +/* EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_6_REG register + * Register 6 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_6_REG (DR_REG_EFUSE_BASE + 0x74) + +/* EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_7_REG register + * Register 7 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_7_REG (DR_REG_EFUSE_BASE + 0x78) + +/* EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/* EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) + +/* EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA0 0xFFFFFFFF +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFF +#define EFUSE_USR_DATA0_S 0 + +/* EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) + +/* EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA1 0xFFFFFFFF +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFF +#define EFUSE_USR_DATA1_S 0 + +/* EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) + +/* EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA2 0xFFFFFFFF +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFF +#define EFUSE_USR_DATA2_S 0 + +/* EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) + +/* EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA3 0xFFFFFFFF +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFF +#define EFUSE_USR_DATA3_S 0 + +/* EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) + +/* EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA4 0xFFFFFFFF +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFF +#define EFUSE_USR_DATA4_S 0 + +/* EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) + +/* EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA5 0xFFFFFFFF +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFF +#define EFUSE_USR_DATA5_S 0 + +/* EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) + +/* EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA6 0xFFFFFFFF +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFF +#define EFUSE_USR_DATA6_S 0 + +/* EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) + +/* EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA7 0xFFFFFFFF +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFF +#define EFUSE_USR_DATA7_S 0 + +/* EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) + +/* EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA0 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_S 0 + +/* EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) + +/* EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA1 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_S 0 + +/* EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) + +/* EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA2 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_S 0 + +/* EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) + +/* EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA3 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_S 0 + +/* EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) + +/* EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA4 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_S 0 + +/* EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) + +/* EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA5 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_S 0 + +/* EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) + +/* EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA6 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_S 0 + +/* EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) + +/* EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA7 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_S 0 + +/* EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) + +/* EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA0 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_S 0 + +/* EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) + +/* EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA1 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_S 0 + +/* EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) + +/* EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA2 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_S 0 + +/* EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) + +/* EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA3 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_S 0 + +/* EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) + +/* EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA4 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_S 0 + +/* EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) + +/* EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA5 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_S 0 + +/* EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) + +/* EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA6 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_S 0 + +/* EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) + +/* EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA7 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_S 0 + +/* EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) + +/* EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA0 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_S 0 + +/* EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) + +/* EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA1 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_S 0 + +/* EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) + +/* EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA2 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_S 0 + +/* EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) + +/* EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA3 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_S 0 + +/* EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) + +/* EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA4 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_S 0 + +/* EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) + +/* EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA5 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_S 0 + +/* EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) + +/* EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA6 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_S 0 + +/* EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) + +/* EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA7 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_S 0 + +/* EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) + +/* EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA0 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_S 0 + +/* EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) + +/* EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA1 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_S 0 + +/* EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) + +/* EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA2 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_S 0 + +/* EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) + +/* EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA3 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_S 0 + +/* EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) + +/* EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA4 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_S 0 + +/* EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) + +/* EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA5 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_S 0 + +/* EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) + +/* EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA6 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_S 0 + +/* EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) + +/* EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA7 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_S 0 + +/* EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) + +/* EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA0 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_S 0 + +/* EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) + +/* EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA1 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_S 0 + +/* EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) + +/* EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA2 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_S 0 + +/* EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) + +/* EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA3 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_S 0 + +/* EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) + +/* EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA4 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_S 0 + +/* EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) + +/* EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA5 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_S 0 + +/* EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) + +/* EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA6 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_S 0 + +/* EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) + +/* EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA7 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_S 0 + +/* EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) + +/* EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA0 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_S 0 + +/* EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) + +/* EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA1 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_S 0 + +/* EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) + +/* EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA2 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_S 0 + +/* EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) + +/* EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA3 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_S 0 + +/* EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) + +/* EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA4 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_S 0 + +/* EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) + +/* EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA5 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_S 0 + +/* EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) + +/* EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA6 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_S 0 + +/* EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) + +/* EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA7 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_0_REG register + * Register 0 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_0_REG (DR_REG_EFUSE_BASE + 0x15c) + +/* EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_1_REG register + * Register 1 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_1_REG (DR_REG_EFUSE_BASE + 0x160) + +/* EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_2_REG register + * Register 2 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_2_REG (DR_REG_EFUSE_BASE + 0x164) + +/* EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_3_REG register + * Register 3 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_3_REG (DR_REG_EFUSE_BASE + 0x168) + +/* EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_4_REG register + * Register 4 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_4_REG (DR_REG_EFUSE_BASE + 0x16c) + +/* EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_5_REG register + * Register 5 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_5_REG (DR_REG_EFUSE_BASE + 0x170) + +/* EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_6_REG register + * Register 6 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_6_REG (DR_REG_EFUSE_BASE + 0x174) + +/* EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_7_REG register + * Register 7 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_7_REG (DR_REG_EFUSE_BASE + 0x178) + +/* EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/* EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) + +/* EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFH. + */ + +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 + +/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_MODECURLIM. + */ + +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 + +/* EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [28:27]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED0. + */ + +#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_S 27 + +/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO; bitpos: [26]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_FORCE_NOPERSIST. + */ + +#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (EFUSE_USB_FORCE_NOPERSIST_ERR_V << EFUSE_USB_FORCE_NOPERSIST_ERR_S) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x00000001 +#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 + +/* EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [25]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_EXT_PHY_ENABLE. + */ + +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001 +#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 + +/* EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [24]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_EXCHG_PINS. + */ + +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001 +#define EFUSE_USB_EXCHG_PINS_ERR_S 24 + +/* EFUSE_USB_DREFL_ERR : RO; bitpos: [23:22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_DREFL. + */ + +#define EFUSE_USB_DREFL_ERR 0x00000003 +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003 +#define EFUSE_USB_DREFL_ERR_S 22 + +/* EFUSE_USB_DREFH_ERR : RO; bitpos: [21:20]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_DREFH. + */ + +#define EFUSE_USB_DREFH_ERR 0x00000003 +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003 +#define EFUSE_USB_DREFH_ERR_S 20 + +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [19]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 + +/* EFUSE_HARD_DIS_JTAG_ERR : RO; bitpos: [18]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_HARD_DIS_JTAG. + */ + +#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_ERR_M (EFUSE_HARD_DIS_JTAG_ERR_V << EFUSE_HARD_DIS_JTAG_ERR_S) +#define EFUSE_HARD_DIS_JTAG_ERR_V 0x00000001 +#define EFUSE_HARD_DIS_JTAG_ERR_S 18 + +/* EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [17]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SOFT_DIS_JTAG. + */ + +#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000001 +#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 + +/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO; bitpos: [16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_EFUSE_ATE_WR. + */ + +#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (EFUSE_DIS_EFUSE_ATE_WR_ERR_V << EFUSE_DIS_EFUSE_ATE_WR_ERR_S) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x00000001 +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 + +/* EFUSE_DIS_BOOT_REMAP_ERR : RO; bitpos: [15]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_BOOT_REMAP. + */ + +#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_ERR_M (EFUSE_DIS_BOOT_REMAP_ERR_V << EFUSE_DIS_BOOT_REMAP_ERR_S) +#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x00000001 +#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 + +/* EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_CAN. + */ + +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001 +#define EFUSE_DIS_CAN_ERR_S 14 + +/* EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_USB. + */ + +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) +#define EFUSE_DIS_USB_ERR_V 0x00000001 +#define EFUSE_DIS_USB_ERR_S 13 + +/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_FORCE_DOWNLOAD. + */ + +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001 +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 + +/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_DCACHE. + */ + +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 + +/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_ICACHE. + */ + +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 + +/* EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DCACHE. + */ + +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) +#define EFUSE_DIS_DCACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DCACHE_ERR_S 9 + +/* EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_ICACHE. + */ + +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001 +#define EFUSE_DIS_ICACHE_ERR_S 8 + +/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_RTC_RAM_BOOT. + */ + +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001 +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 + +/* EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RD_DIS. + */ + +#define EFUSE_RD_DIS_ERR 0x0000007F +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007F +#define EFUSE_RD_DIS_ERR_S 0 + +/* EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) + +/* EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_1. + */ + +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 + +/* EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_0. + */ + +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE2. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE1. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE0. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 + +/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SPI_BOOT_CRYPT_CNT. + */ + +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 + +/* EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_WDT_DELAY_SEL. + */ + +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 + +/* EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DCAP. + */ + +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 + +/* EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_INIT. + */ + +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_S 12 + +/* EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DCURLIM. + */ + +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 + +/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_ENCURLIM. + */ + +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 + +/* EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_EN_INIT. + */ + +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 + +/* EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_FORCE. + */ + +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 + +/* EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_TIEH. + */ + +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 + +/* EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_XPD. + */ + +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_XPD_ERR_S 4 + +/* EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFL. + */ + +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 + +/* EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFM. + */ + +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_S 0 + +/* EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) + +/* EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FLASH_TPUW. + */ + +#define EFUSE_FLASH_TPUW_ERR 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/* EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [27:22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED1. + */ + +#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_S 22 + +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 + +/* EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_EN. + */ + +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 + +/* EFUSE_KEY_PURPOSE_6_ERR : RO; bitpos: [19:16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_6. + */ + +#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_M (EFUSE_KEY_PURPOSE_6_ERR_V << EFUSE_KEY_PURPOSE_6_ERR_S) +#define EFUSE_KEY_PURPOSE_6_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_S 16 + +/* EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_5. + */ + +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 + +/* EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_4. + */ + +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 + +/* EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_3. + */ + +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 + +/* EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_2. + */ + +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 + +/* EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) + +/* EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [31:27]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED2. + */ + +#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_S 27 + +/* EFUSE_SECURE_VERSION_ERR : RO; bitpos: [26:11]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_VERSION. + */ + +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_S 11 + +/* EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [10]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FORCE_SEND_RESUME. + */ + +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001 +#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 + +/* EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FLASH_TYPE. + */ + +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001 +#define EFUSE_FLASH_TYPE_ERR_S 9 + +/* EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_PIN_POWER_SELECTION. + */ + +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001 +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 + +/* EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_UART_PRINT_CONTROL. + */ + +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 + +/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_ENABLE_SECURITY_DOWNLOAD. + */ + +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 + +/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_USB_DOWNLOAD_MODE. + */ + +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 + +/* EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [3]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED3. + */ + +#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x00000001 +#define EFUSE_RPT4_RESERVED3_ERR_S 3 + +/* EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_UART_PRINT_CHANNEL. + */ + +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001 +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 + +/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_LEGACY_SPI_BOOT. + */ + +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001 +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 + +/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_MODE. + */ + +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 + +/* EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) + +/* EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED4. + */ + +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) +#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_S 0 + +/* EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ + +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) + +/* EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of KEY4 is reliable; 1: Means that + * programming KEY4 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001 +#define EFUSE_KEY4_FAIL_S 31 + +/* EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes in KEY4. + */ + +#define EFUSE_KEY4_ERR_NUM 0x00000007 +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007 +#define EFUSE_KEY4_ERR_NUM_S 28 + +/* EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of KEY3 is reliable; 1: Means that + * programming KEY3 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001 +#define EFUSE_KEY3_FAIL_S 27 + +/* EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes in KEY3. + */ + +#define EFUSE_KEY3_ERR_NUM 0x00000007 +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007 +#define EFUSE_KEY3_ERR_NUM_S 24 + +/* EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of KEY2 is reliable; 1: Means that + * programming KEY2 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001 +#define EFUSE_KEY2_FAIL_S 23 + +/* EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes in KEY2. + */ + +#define EFUSE_KEY2_ERR_NUM 0x00000007 +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007 +#define EFUSE_KEY2_ERR_NUM_S 20 + +/* EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of KEY1 is reliable; 1: Means that + * programming KEY1 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001 +#define EFUSE_KEY1_FAIL_S 19 + +/* EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes in KEY1. + */ + +#define EFUSE_KEY1_ERR_NUM 0x00000007 +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007 +#define EFUSE_KEY1_ERR_NUM_S 16 + +/* EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of KEY0 is reliable; 1: Means that + * programming KEY0 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001 +#define EFUSE_KEY0_FAIL_S 15 + +/* EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes in KEY0. + */ + +#define EFUSE_KEY0_ERR_NUM 0x00000007 +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007 +#define EFUSE_KEY0_ERR_NUM_S 12 + +/* EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the data of BLOCK3 is reliable; 1: Means + * that programming BLOCK3 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001 +#define EFUSE_USR_DATA_FAIL_S 11 + +/* EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in BLOCK3. + */ + +#define EFUSE_USR_DATA_ERR_NUM 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_S 8 + +/* EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK2 is reliable; 1: Means + * that programming BLOCK2 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001 +#define EFUSE_SYS_PART1_FAIL_S 7 + +/* EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK2. + */ + +#define EFUSE_SYS_PART1_NUM 0x00000007 +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007 +#define EFUSE_SYS_PART1_NUM_S 4 + +/* EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of BLOCK1 is reliable; 1: Means + * that programming BLOCK1 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001 +#define EFUSE_MAC_SPI_8M_FAIL_S 3 + +/* EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in BLOCK1. + */ + +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 + +/* EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ + +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) + +/* EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK10 is reliable; 1: Means + * that programming BLOCK10 data failed and the number of error bytes is + * over 5. + */ + +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001 +#define EFUSE_SYS_PART2_FAIL_S 7 + +/* EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK10. + */ + +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_S 4 + +/* EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable; 1: Means that + * programming user data failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001 +#define EFUSE_KEY5_FAIL_S 3 + +/* EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in KEY5. + */ + +#define EFUSE_KEY5_ERR_NUM 0x00000007 +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007 +#define EFUSE_KEY5_ERR_NUM_S 0 + +/* EFUSE_CLK_REG register + * eFuse clock configuration register. + */ + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) + +/* EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * If set, forces to enable clock signal of eFuse memory. + */ + +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001 +#define EFUSE_CLK_EN_S 16 + +/* EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * If set, forces eFuse SRAM into working mode. + */ + +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001 +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 + +/* EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * If set, forces to activate clock signal of eFuse SRAM. + */ + +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001 +#define EFUSE_MEM_CLK_FORCE_ON_S 1 + +/* EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * If set, forces eFuse SRAM into power-saving mode. + */ + +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001 +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 + +/* EFUSE_CONF_REG register + * eFuse operation mode configuration register. + */ + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) + +/* EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command; 0x5AA5: Operate read command. + */ + +#define EFUSE_OP_CODE 0x0000FFFF +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFF +#define EFUSE_OP_CODE_S 0 + +/* EFUSE_STATUS_REG register + * eFuse status register. + */ + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) + +/* EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + +#define EFUSE_REPEAT_ERR_CNT 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_S 10 + +/* EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001 +#define EFUSE_OTP_VDDQ_IS_SW_S 9 + +/* EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001 +#define EFUSE_OTP_PGENB_SW_S 8 + +/* EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001 +#define EFUSE_OTP_CSB_SW_S 7 + +/* EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001 +#define EFUSE_OTP_STROBE_SW_S 6 + +/* EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001 +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 + +/* EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001 +#define EFUSE_OTP_LOAD_SW_S 4 + +/* EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + +#define EFUSE_STATE 0x0000000F +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000F +#define EFUSE_STATE_S 0 + +/* EFUSE_CMD_REG register + * eFuse command register. + */ + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) + +/* EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. + */ + +#define EFUSE_BLK_NUM 0x0000000F +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000F +#define EFUSE_BLK_NUM_S 2 + +/* EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001 +#define EFUSE_PGM_CMD_S 1 + +/* EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001 +#define EFUSE_READ_CMD_S 0 + +/* EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) + +/* EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/* EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +/* EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) + +/* EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/* EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001 +#define EFUSE_READ_DONE_INT_ST_S 0 + +/* EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) + +/* EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/* EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +/* EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) + +/* EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/* EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +/* EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) + +/* EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001 +#define EFUSE_OE_CLR_S 17 + +/* EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + +#define EFUSE_DAC_NUM 0x000000FF +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FF +#define EFUSE_DAC_NUM_S 9 + +/* EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 + +/* EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming + * voltage. + */ + +#define EFUSE_DAC_CLK_DIV 0x000000FF +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FF +#define EFUSE_DAC_CLK_DIV_S 0 + +/* EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ + +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) + +/* EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + +#define EFUSE_READ_INIT_NUM 0x000000FF +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FF +#define EFUSE_READ_INIT_NUM_S 24 + +/* EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the setup time of read operation. + */ + +#define EFUSE_TSUR_A 0x000000FF +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FF +#define EFUSE_TSUR_A_S 16 + +/* EFUSE_TRD : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse of read operation. + */ + +#define EFUSE_TRD 0x000000FF +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FF +#define EFUSE_TRD_S 8 + +/* EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of read operation. + */ + +#define EFUSE_THR_A 0x000000FF +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FF +#define EFUSE_THR_A_S 0 + +/* EFUSE_WR_TIM_CONF0_REG register + * Configuration register 0 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) + +/* EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures the length of pulse during programming 1 to eFuse. + */ + +#define EFUSE_TPGM 0x0000FFFF +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFF +#define EFUSE_TPGM_S 16 + +/* EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse during programming 0 to eFuse. + */ + +#define EFUSE_TPGM_INACTIVE 0x000000FF +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FF +#define EFUSE_TPGM_INACTIVE_S 8 + +/* EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of programming operation. + */ + +#define EFUSE_THP_A 0x000000FF +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FF +#define EFUSE_THP_A_S 0 + +/* EFUSE_WR_TIM_CONF1_REG register + * Configuration register 1 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) + +/* EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + +#define EFUSE_PWR_ON_NUM 0x0000FFFF +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFF +#define EFUSE_PWR_ON_NUM_S 8 + +/* EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the setup time of programming operation. + */ + +#define EFUSE_TSUP_A 0x000000FF +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FF +#define EFUSE_TSUP_A_S 0 + +/* EFUSE_WR_TIM_CONF2_REG register + * Configuration register 2 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) + +/* EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + +#define EFUSE_PWR_OFF_NUM 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_S 0 + +/* EFUSE_DATE_REG register + * eFuse version register. + */ + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) + +/* EFUSE_EFUSE_DATE : R/W; bitpos: [31:0]; default: 419959040; + * Stores eFuse version. + */ + +#define EFUSE_EFUSE_DATE 0xFFFFFFFF +#define EFUSE_EFUSE_DATE_M (EFUSE_EFUSE_DATE_V << EFUSE_EFUSE_DATE_S) +#define EFUSE_EFUSE_DATE_V 0xFFFFFFFF +#define EFUSE_EFUSE_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h new file mode 100644 index 00000000000..0c36a00fe15 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h @@ -0,0 +1,16494 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIO_PIN_COUNT 53 + +/* GPIO_BT_SELECT_REG register + * GPIO bit select register + */ + +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) + +/* GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) +#define GPIO_BT_SEL_V 0xFFFFFFFF +#define GPIO_BT_SEL_S 0 + +/* GPIO_OUT_REG register + * GPIO0 ~ 31 output register + */ + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) + +/* GPIO_OUT_DATA_ORIG : R/W; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output value in simple GPIO output mode. The values of bit0 ~ + * bit31 correspond to the output value of GPIO0 ~ GPIO31 respectively. + * Bit22 ~ bit25 are invalid. + */ + +#define GPIO_OUT_DATA_ORIG 0xFFFFFFFF +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFF +#define GPIO_OUT_DATA_ORIG_S 0 + +/* GPIO_OUT_W1TS_REG register + * GPIO0 ~ 31 output bit set register + */ + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) + +/* GPIO_OUT_W1TS : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output set register. If the value 1 is written to a bit here, + * the corre- sponding bit in GPIO_OUT_REG will be set to 1. Recommended + * operation: use this register to set GPIO_OUT_REG. + */ + +#define GPIO_OUT_W1TS 0xFFFFFFFF +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0xFFFFFFFF +#define GPIO_OUT_W1TS_S 0 + +/* GPIO_OUT_W1TC_REG register + * GPIO0 ~ 31 output bit clear register + */ + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) + +/* GPIO_OUT_W1TC : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output clear register. If the value 1 is written to a bit + * here, the cor- responding bit in GPIO_OUT_REG will be cleared. + * Recommended operation: use this register to clear GPIO_OUT_REG. + */ + +#define GPIO_OUT_W1TC 0xFFFFFFFF +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0xFFFFFFFF +#define GPIO_OUT_W1TC_S 0 + +/* GPIO_OUT1_REG register + * GPIO32 ~ 53 output register + */ + +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) + +/* GPIO_OUT1_DATA_ORIG : R/W; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output value in simple GPIO output mode. The values of bit0 ~ + * bit13 correspond to GPIO32 ~ GPIO45. Bit14 ~ bit21 are invalid. + */ + +#define GPIO_OUT1_DATA_ORIG 0x003FFFFF +#define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) +#define GPIO_OUT1_DATA_ORIG_V 0x003FFFFF +#define GPIO_OUT1_DATA_ORIG_S 0 + +/* GPIO_OUT1_W1TS_REG register + * GPIO32 ~ 53 output bit set register + */ + +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) + +/* GPIO_OUT1_W1TS : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output value set register. If the value 1 is written to a bit + * here, the corresponding bit in GPIO_OUT1_REG will be set to 1. + * Recommended operation: use this register to set GPIO_OUT1_REG. + */ + +#define GPIO_OUT1_W1TS 0x003FFFFF +#define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) +#define GPIO_OUT1_W1TS_V 0x003FFFFF +#define GPIO_OUT1_W1TS_S 0 + +/* GPIO_OUT1_W1TC_REG register + * GPIO32 ~ 53 output bit clear register + */ + +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) + +/* GPIO_OUT1_W1TC : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output value clear register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_OUT1_REG will be cleared. + * Recommended operation: use this register to clear GPIO_OUT1_REG. + */ + +#define GPIO_OUT1_W1TC 0x003FFFFF +#define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) +#define GPIO_OUT1_W1TC_V 0x003FFFFF +#define GPIO_OUT1_W1TC_S 0 + +/* GPIO_SDIO_SELECT_REG register + * GPIO SDIO selection register + */ + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) + +/* GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; + * Reserved + */ + +#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) +#define GPIO_SDIO_SEL_V 0x000000FF +#define GPIO_SDIO_SEL_S 0 + +/* GPIO_ENABLE_REG register + * GPIO0 ~ 31 output enable register + */ + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) + +/* GPIO_ENABLE_DATA : R/W; bitpos: [31:0]; default: 0; + * GPIO0~31 output enable register. + */ + +#define GPIO_ENABLE_DATA 0xFFFFFFFF +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_S 0 + +/* GPIO_ENABLE_W1TS_REG register + * GPIO0 ~ 31 output enable bit set register + */ + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) + +/* GPIO_ENABLE_W1TS : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output enable set register. If the value 1 is written to a bit + * here, the corresponding bit in GPIO_ENABLE_REG will be set to 1. + * Recommended operation: use this register to set GPIO_ENABLE_REG. + */ + +#define GPIO_ENABLE_W1TS 0xFFFFFFFF +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFF +#define GPIO_ENABLE_W1TS_S 0 + +/* GPIO_ENABLE_W1TC_REG register + * GPIO0 ~ 31 output enable bit clear register + */ + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) + +/* GPIO_ENABLE_W1TC : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output enable clear register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_ENABLE_REG will be cleared. + * Recommended operation: use this register to clear GPIO_ENABLE_REG. + */ + +#define GPIO_ENABLE_W1TC 0xFFFFFFFF +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFF +#define GPIO_ENABLE_W1TC_S 0 + +/* GPIO_ENABLE1_REG register + * GPIO32 ~ 53 output enable register + */ + +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c) + +/* GPIO_ENABLE1_DATA : R/W; bitpos: [21:0]; default: 0; + * GPIO32~53 output enable register. + */ + +#define GPIO_ENABLE1_DATA 0x003FFFFF +#define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) +#define GPIO_ENABLE1_DATA_V 0x003FFFFF +#define GPIO_ENABLE1_DATA_S 0 + +/* GPIO_ENABLE1_W1TS_REG register + * GPIO32 ~ 53 output enable bit set register + */ + +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) + +/* GPIO_ENABLE1_W1TS : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output enable set register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_ENABLE1_REG will be set to 1. + * Recommended operation: use this register to set GPIO_ENABLE1_REG. + */ + +#define GPIO_ENABLE1_W1TS 0x003FFFFF +#define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) +#define GPIO_ENABLE1_W1TS_V 0x003FFFFF +#define GPIO_ENABLE1_W1TS_S 0 + +/* GPIO_ENABLE1_W1TC_REG register + * GPIO32 ~ 53 output enable bit clear register + */ + +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) + +/* GPIO_ENABLE1_W1TC : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output enable clear register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_ENABLE1_REG will be cleared. + * Recommended operation: use this register to clear GPIO_ENABLE1_REG. + */ + +#define GPIO_ENABLE1_W1TC 0x003FFFFF +#define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) +#define GPIO_ENABLE1_W1TC_V 0x003FFFFF +#define GPIO_ENABLE1_W1TC_S 0 + +/* GPIO_STRAP_REG register + * Bootstrap pin value register + */ + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) + +/* GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * GPIO strapping values: bit4 ~ bit2 correspond to stripping pins GPIO45, + * GPIO0, and GPIO46 respectively. + */ + +#define GPIO_STRAPPING 0x0000FFFF +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFF +#define GPIO_STRAPPING_S 0 + +/* GPIO_IN_REG register + * GPIO0 ~ 31 input register + */ + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) + +/* GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 input value. Each bit represents a pad input value, 1 for high + * level and 0 for low level. + */ + +#define GPIO_IN_DATA_NEXT 0xFFFFFFFF +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0xFFFFFFFF +#define GPIO_IN_DATA_NEXT_S 0 + +/* GPIO_IN1_REG register + * GPIO32 ~ 53 input register + */ + +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) + +/* GPIO_IN_DATA1_NEXT : RO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 input value. Each bit represents a pad input value. + */ + +#define GPIO_IN_DATA1_NEXT 0x003FFFFF +#define GPIO_IN_DATA1_NEXT_M (GPIO_IN_DATA1_NEXT_V << GPIO_IN_DATA1_NEXT_S) +#define GPIO_IN_DATA1_NEXT_V 0x003FFFFF +#define GPIO_IN_DATA1_NEXT_S 0 + +/* GPIO_STATUS_REG register + * GPIO0 ~ 31 interrupt status register + */ + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) + +/* GPIO_STATUS_INTERRUPT : R/W; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 interrupt status register. + */ + +#define GPIO_STATUS_INTERRUPT 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_S 0 + +/* GPIO_STATUS_W1TS_REG register + * GPIO0 ~ 31 interrupt status bit set register + */ + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) + +/* GPIO_STATUS_W1TS : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 interrupt status set register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set to + * 1. Recommended operation: use this register to set GPIO_STATUS_INTERRUPT. + */ + +#define GPIO_STATUS_W1TS 0xFFFFFFFF +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0xFFFFFFFF +#define GPIO_STATUS_W1TS_S 0 + +/* GPIO_STATUS_W1TC_REG register + * GPIO0 ~ 31 interrupt status bit clear register + */ + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) + +/* GPIO_STATUS_W1TC : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 interrupt status clear register. If the value 1 is written to + * a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be + * cleared. Recommended operation: use this register to clear + * GPIO_STATUS_INTERRUPT. + */ + +#define GPIO_STATUS_W1TC 0xFFFFFFFF +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0xFFFFFFFF +#define GPIO_STATUS_W1TC_S 0 + +/* GPIO_STATUS1_REG register + * GPIO32 ~ 53 interrupt status register + */ + +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) + +/* GPIO_STATUS1_INTERRUPT : R/W; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 interrupt status register. + */ + +#define GPIO_STATUS1_INTERRUPT 0x003FFFFF +#define GPIO_STATUS1_INTERRUPT_M (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S) +#define GPIO_STATUS1_INTERRUPT_V 0x003FFFFF +#define GPIO_STATUS1_INTERRUPT_S 0 + +/* GPIO_STATUS1_W1TS_REG register + * GPIO32 ~ 53 interrupt status bit set register + */ + +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) + +/* GPIO_STATUS1_W1TS : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 interrupt status set register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_STATUS1_REG will be set to 1. + * Recommended operation: use this register to set GPIO_STATUS1_REG. + */ + +#define GPIO_STATUS1_W1TS 0x003FFFFF +#define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) +#define GPIO_STATUS1_W1TS_V 0x003FFFFF +#define GPIO_STATUS1_W1TS_S 0 + +/* GPIO_STATUS1_W1TC_REG register + * GPIO32 ~ 53 interrupt status bit clear register + */ + +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) + +/* GPIO_STATUS1_W1TC : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 interrupt status clear register. If the value 1 is written to + * a bit here, the corresponding bit in GPIO_STATUS1_REG will be cleared. + * Recommended operation: use this register to clear GPIO_STATUS1_REG. + */ + +#define GPIO_STATUS1_W1TC 0x003FFFFF +#define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) +#define GPIO_STATUS1_W1TC_V 0x003FFFFF +#define GPIO_STATUS1_W1TC_S 0 + +/* GPIO_PCPU_INT_REG register + * GPIO0 ~ 31 PRO_CPU interrupt status register + */ + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) + +/* GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 PRO_CPU interrupt status. This interrupt status is + * corresponding to the bit in GPIO_STATUS_REG when assert (high) enable + * signal (bit13 of GPIO_PINn_REG). + */ + +#define GPIO_PROCPU_INT 0xFFFFFFFF +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_INT_S 0 + +/* GPIO_PCPU_NMI_INT_REG register + * GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register + */ + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) + +/* GPIO_PROCPU_NMI_INT : RO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 PRO_CPU non-maskable interrupt status. This interrupt sta- tus + * is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable + * signal (bit 14 of GPIO_PINn_REG). + */ + +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_S 0 + +/* GPIO_CPUSDIO_INT_REG register + * GPIO0 ~ 31 CPU SDIO interrupt status register + */ + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) + +/* GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; + * GPIO0~31 CPU SDIO interrupt status. + */ + +#define GPIO_SDIO_INT 0xFFFFFFFF +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0xFFFFFFFF +#define GPIO_SDIO_INT_S 0 + +/* GPIO_PCPU_INT1_REG register + * GPIO32 ~ 53 PRO_CPU interrupt status register + */ + +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) + +/* GPIO_PROCPU1_INT : RO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 PRO_CPU interrupt status. This interrupt status is + * corresponding to the bit in GPIO_STATUS1_REG when assert (high) enable + * signal (bit 13 of GPIO_PINn_REG). + */ + +#define GPIO_PROCPU1_INT 0x003FFFFF +#define GPIO_PROCPU1_INT_M (GPIO_PROCPU1_INT_V << GPIO_PROCPU1_INT_S) +#define GPIO_PROCPU1_INT_V 0x003FFFFF +#define GPIO_PROCPU1_INT_S 0 + +/* GPIO_PCPU_NMI_INT1_REG register + * GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register + */ + +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6c) + +/* GPIO_PROCPU_NMI1_INT : RO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 PRO_CPU non-maskable interrupt status. This interrupt status + * is corresponding to bit in GPIO_STATUS1_REG when assert (high) enable + * signal (bit 14 of GPIO_PINn_REG). + */ + +#define GPIO_PROCPU_NMI1_INT 0x003FFFFF +#define GPIO_PROCPU_NMI1_INT_M (GPIO_PROCPU_NMI1_INT_V << GPIO_PROCPU_NMI1_INT_S) +#define GPIO_PROCPU_NMI1_INT_V 0x003FFFFF +#define GPIO_PROCPU_NMI1_INT_S 0 + +/* GPIO_CPUSDIO_INT1_REG register + * GPIO32 ~ 53 CPU SDIO interrupt status register + */ + +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) + +/* GPIO_SDIO1_INT : RO; bitpos: [21:0]; default: 0; + * GPIO32~53 CPU SDIO interrupt status. + */ + +#define GPIO_SDIO1_INT 0x003FFFFF +#define GPIO_SDIO1_INT_M (GPIO_SDIO1_INT_V << GPIO_SDIO1_INT_S) +#define GPIO_SDIO1_INT_V 0x003FFFFF +#define GPIO_SDIO1_INT_S 0 + +/* GPIO_PIN0_REG register + * Configuration for GPIO pin 0 + */ + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4) +#define GPIO_PIN_PAD_DRIVER_S 2 + +/* GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001F +#define GPIO_PIN0_INT_ENA_S 13 + +/* GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) +#define GPIO_PIN0_CONFIG_V 0x00000003 +#define GPIO_PIN0_CONFIG_S 11 + +/* GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 + +#define GPIO_PIN_INT_TYPE 0x00000007 +#define GPIO_PIN_INT_TYPE_M (GPIO_PIN_INT_TYPE_V << GPIO_PIN_INT_TYPE_S) +#define GPIO_PIN_INT_TYPE_V 0x00000007 +#define GPIO_PIN_INT_TYPE_S 7 + +#define GPIO_PIN_INT_ENA 0x0000001F +#define GPIO_PIN_INT_ENA_M (GPIO_PIN_INT_ENA_V << GPIO_PIN_INT_ENA_S) +#define GPIO_PIN_INT_ENA_V 0x0000001F +#define GPIO_PIN_INT_ENA_S 13 + +/* GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007 +#define GPIO_PIN0_INT_TYPE_S 7 + +/* GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN0_SYNC1_BYPASS_S 3 + +/* GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN0_PAD_DRIVER_S 2 + +/* GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN0_SYNC2_BYPASS_S 0 + +/* GPIO_PIN1_REG register + * Configuration for GPIO pin 1 + */ + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) + +/* GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001F +#define GPIO_PIN1_INT_ENA_S 13 + +/* GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) +#define GPIO_PIN1_CONFIG_V 0x00000003 +#define GPIO_PIN1_CONFIG_S 11 + +/* GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007 +#define GPIO_PIN1_INT_TYPE_S 7 + +/* GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN1_SYNC1_BYPASS_S 3 + +/* GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN1_PAD_DRIVER_S 2 + +/* GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN1_SYNC2_BYPASS_S 0 + +/* GPIO_PIN2_REG register + * Configuration for GPIO pin 2 + */ + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) + +/* GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001F +#define GPIO_PIN2_INT_ENA_S 13 + +/* GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) +#define GPIO_PIN2_CONFIG_V 0x00000003 +#define GPIO_PIN2_CONFIG_S 11 + +/* GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007 +#define GPIO_PIN2_INT_TYPE_S 7 + +/* GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN2_SYNC1_BYPASS_S 3 + +/* GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN2_PAD_DRIVER_S 2 + +/* GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN2_SYNC2_BYPASS_S 0 + +/* GPIO_PIN3_REG register + * Configuration for GPIO pin 3 + */ + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) + +/* GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001F +#define GPIO_PIN3_INT_ENA_S 13 + +/* GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) +#define GPIO_PIN3_CONFIG_V 0x00000003 +#define GPIO_PIN3_CONFIG_S 11 + +/* GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007 +#define GPIO_PIN3_INT_TYPE_S 7 + +/* GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN3_SYNC1_BYPASS_S 3 + +/* GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN3_PAD_DRIVER_S 2 + +/* GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN3_SYNC2_BYPASS_S 0 + +/* GPIO_PIN4_REG register + * Configuration for GPIO pin 4 + */ + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) + +/* GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001F +#define GPIO_PIN4_INT_ENA_S 13 + +/* GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) +#define GPIO_PIN4_CONFIG_V 0x00000003 +#define GPIO_PIN4_CONFIG_S 11 + +/* GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007 +#define GPIO_PIN4_INT_TYPE_S 7 + +/* GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN4_SYNC1_BYPASS_S 3 + +/* GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN4_PAD_DRIVER_S 2 + +/* GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN4_SYNC2_BYPASS_S 0 + +/* GPIO_PIN5_REG register + * Configuration for GPIO pin 5 + */ + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) + +/* GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001F +#define GPIO_PIN5_INT_ENA_S 13 + +/* GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) +#define GPIO_PIN5_CONFIG_V 0x00000003 +#define GPIO_PIN5_CONFIG_S 11 + +/* GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007 +#define GPIO_PIN5_INT_TYPE_S 7 + +/* GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN5_SYNC1_BYPASS_S 3 + +/* GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN5_PAD_DRIVER_S 2 + +/* GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN5_SYNC2_BYPASS_S 0 + +/* GPIO_PIN6_REG register + * Configuration for GPIO pin 6 + */ + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) + +/* GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001F +#define GPIO_PIN6_INT_ENA_S 13 + +/* GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) +#define GPIO_PIN6_CONFIG_V 0x00000003 +#define GPIO_PIN6_CONFIG_S 11 + +/* GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007 +#define GPIO_PIN6_INT_TYPE_S 7 + +/* GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN6_SYNC1_BYPASS_S 3 + +/* GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN6_PAD_DRIVER_S 2 + +/* GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN6_SYNC2_BYPASS_S 0 + +/* GPIO_PIN7_REG register + * Configuration for GPIO pin 7 + */ + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) + +/* GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001F +#define GPIO_PIN7_INT_ENA_S 13 + +/* GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) +#define GPIO_PIN7_CONFIG_V 0x00000003 +#define GPIO_PIN7_CONFIG_S 11 + +/* GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007 +#define GPIO_PIN7_INT_TYPE_S 7 + +/* GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN7_SYNC1_BYPASS_S 3 + +/* GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN7_PAD_DRIVER_S 2 + +/* GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN7_SYNC2_BYPASS_S 0 + +/* GPIO_PIN8_REG register + * Configuration for GPIO pin 8 + */ + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) + +/* GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001F +#define GPIO_PIN8_INT_ENA_S 13 + +/* GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) +#define GPIO_PIN8_CONFIG_V 0x00000003 +#define GPIO_PIN8_CONFIG_S 11 + +/* GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007 +#define GPIO_PIN8_INT_TYPE_S 7 + +/* GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN8_SYNC1_BYPASS_S 3 + +/* GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN8_PAD_DRIVER_S 2 + +/* GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN8_SYNC2_BYPASS_S 0 + +/* GPIO_PIN9_REG register + * Configuration for GPIO pin 9 + */ + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) + +/* GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001F +#define GPIO_PIN9_INT_ENA_S 13 + +/* GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) +#define GPIO_PIN9_CONFIG_V 0x00000003 +#define GPIO_PIN9_CONFIG_S 11 + +/* GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007 +#define GPIO_PIN9_INT_TYPE_S 7 + +/* GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN9_SYNC1_BYPASS_S 3 + +/* GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN9_PAD_DRIVER_S 2 + +/* GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN9_SYNC2_BYPASS_S 0 + +/* GPIO_PIN10_REG register + * Configuration for GPIO pin 10 + */ + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) + +/* GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001F +#define GPIO_PIN10_INT_ENA_S 13 + +/* GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) +#define GPIO_PIN10_CONFIG_V 0x00000003 +#define GPIO_PIN10_CONFIG_S 11 + +/* GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007 +#define GPIO_PIN10_INT_TYPE_S 7 + +/* GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN10_SYNC1_BYPASS_S 3 + +/* GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN10_PAD_DRIVER_S 2 + +/* GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN10_SYNC2_BYPASS_S 0 + +/* GPIO_PIN11_REG register + * Configuration for GPIO pin 11 + */ + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) + +/* GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001F +#define GPIO_PIN11_INT_ENA_S 13 + +/* GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) +#define GPIO_PIN11_CONFIG_V 0x00000003 +#define GPIO_PIN11_CONFIG_S 11 + +/* GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007 +#define GPIO_PIN11_INT_TYPE_S 7 + +/* GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN11_SYNC1_BYPASS_S 3 + +/* GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN11_PAD_DRIVER_S 2 + +/* GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN11_SYNC2_BYPASS_S 0 + +/* GPIO_PIN12_REG register + * Configuration for GPIO pin 12 + */ + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) + +/* GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001F +#define GPIO_PIN12_INT_ENA_S 13 + +/* GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) +#define GPIO_PIN12_CONFIG_V 0x00000003 +#define GPIO_PIN12_CONFIG_S 11 + +/* GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007 +#define GPIO_PIN12_INT_TYPE_S 7 + +/* GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN12_SYNC1_BYPASS_S 3 + +/* GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN12_PAD_DRIVER_S 2 + +/* GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN12_SYNC2_BYPASS_S 0 + +/* GPIO_PIN13_REG register + * Configuration for GPIO pin 13 + */ + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) + +/* GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001F +#define GPIO_PIN13_INT_ENA_S 13 + +/* GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) +#define GPIO_PIN13_CONFIG_V 0x00000003 +#define GPIO_PIN13_CONFIG_S 11 + +/* GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007 +#define GPIO_PIN13_INT_TYPE_S 7 + +/* GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN13_SYNC1_BYPASS_S 3 + +/* GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN13_PAD_DRIVER_S 2 + +/* GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN13_SYNC2_BYPASS_S 0 + +/* GPIO_PIN14_REG register + * Configuration for GPIO pin 14 + */ + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) + +/* GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001F +#define GPIO_PIN14_INT_ENA_S 13 + +/* GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) +#define GPIO_PIN14_CONFIG_V 0x00000003 +#define GPIO_PIN14_CONFIG_S 11 + +/* GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007 +#define GPIO_PIN14_INT_TYPE_S 7 + +/* GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN14_SYNC1_BYPASS_S 3 + +/* GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN14_PAD_DRIVER_S 2 + +/* GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN14_SYNC2_BYPASS_S 0 + +/* GPIO_PIN15_REG register + * Configuration for GPIO pin 15 + */ + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) + +/* GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001F +#define GPIO_PIN15_INT_ENA_S 13 + +/* GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) +#define GPIO_PIN15_CONFIG_V 0x00000003 +#define GPIO_PIN15_CONFIG_S 11 + +/* GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007 +#define GPIO_PIN15_INT_TYPE_S 7 + +/* GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN15_SYNC1_BYPASS_S 3 + +/* GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN15_PAD_DRIVER_S 2 + +/* GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN15_SYNC2_BYPASS_S 0 + +/* GPIO_PIN16_REG register + * Configuration for GPIO pin 16 + */ + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) + +/* GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001F +#define GPIO_PIN16_INT_ENA_S 13 + +/* GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) +#define GPIO_PIN16_CONFIG_V 0x00000003 +#define GPIO_PIN16_CONFIG_S 11 + +/* GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007 +#define GPIO_PIN16_INT_TYPE_S 7 + +/* GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN16_SYNC1_BYPASS_S 3 + +/* GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN16_PAD_DRIVER_S 2 + +/* GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN16_SYNC2_BYPASS_S 0 + +/* GPIO_PIN17_REG register + * Configuration for GPIO pin 17 + */ + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) + +/* GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001F +#define GPIO_PIN17_INT_ENA_S 13 + +/* GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) +#define GPIO_PIN17_CONFIG_V 0x00000003 +#define GPIO_PIN17_CONFIG_S 11 + +/* GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007 +#define GPIO_PIN17_INT_TYPE_S 7 + +/* GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN17_SYNC1_BYPASS_S 3 + +/* GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN17_PAD_DRIVER_S 2 + +/* GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN17_SYNC2_BYPASS_S 0 + +/* GPIO_PIN18_REG register + * Configuration for GPIO pin 18 + */ + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) + +/* GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001F +#define GPIO_PIN18_INT_ENA_S 13 + +/* GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) +#define GPIO_PIN18_CONFIG_V 0x00000003 +#define GPIO_PIN18_CONFIG_S 11 + +/* GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007 +#define GPIO_PIN18_INT_TYPE_S 7 + +/* GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN18_SYNC1_BYPASS_S 3 + +/* GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN18_PAD_DRIVER_S 2 + +/* GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN18_SYNC2_BYPASS_S 0 + +/* GPIO_PIN19_REG register + * Configuration for GPIO pin 19 + */ + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) + +/* GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001F +#define GPIO_PIN19_INT_ENA_S 13 + +/* GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) +#define GPIO_PIN19_CONFIG_V 0x00000003 +#define GPIO_PIN19_CONFIG_S 11 + +/* GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007 +#define GPIO_PIN19_INT_TYPE_S 7 + +/* GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN19_SYNC1_BYPASS_S 3 + +/* GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN19_PAD_DRIVER_S 2 + +/* GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN19_SYNC2_BYPASS_S 0 + +/* GPIO_PIN20_REG register + * Configuration for GPIO pin 20 + */ + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) + +/* GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001F +#define GPIO_PIN20_INT_ENA_S 13 + +/* GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) +#define GPIO_PIN20_CONFIG_V 0x00000003 +#define GPIO_PIN20_CONFIG_S 11 + +/* GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007 +#define GPIO_PIN20_INT_TYPE_S 7 + +/* GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN20_SYNC1_BYPASS_S 3 + +/* GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN20_PAD_DRIVER_S 2 + +/* GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN20_SYNC2_BYPASS_S 0 + +/* GPIO_PIN21_REG register + * Configuration for GPIO pin 21 + */ + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) + +/* GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001F +#define GPIO_PIN21_INT_ENA_S 13 + +/* GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) +#define GPIO_PIN21_CONFIG_V 0x00000003 +#define GPIO_PIN21_CONFIG_S 11 + +/* GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007 +#define GPIO_PIN21_INT_TYPE_S 7 + +/* GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN21_SYNC1_BYPASS_S 3 + +/* GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN21_PAD_DRIVER_S 2 + +/* GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN21_SYNC2_BYPASS_S 0 + +/* GPIO_PIN22_REG register + * Configuration for GPIO pin 22 + */ + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) + +/* GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001F +#define GPIO_PIN22_INT_ENA_S 13 + +/* GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) +#define GPIO_PIN22_CONFIG_V 0x00000003 +#define GPIO_PIN22_CONFIG_S 11 + +/* GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007 +#define GPIO_PIN22_INT_TYPE_S 7 + +/* GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN22_SYNC1_BYPASS_S 3 + +/* GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN22_PAD_DRIVER_S 2 + +/* GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN22_SYNC2_BYPASS_S 0 + +/* GPIO_PIN23_REG register + * Configuration for GPIO pin 23 + */ + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) + +/* GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001F +#define GPIO_PIN23_INT_ENA_S 13 + +/* GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) +#define GPIO_PIN23_CONFIG_V 0x00000003 +#define GPIO_PIN23_CONFIG_S 11 + +/* GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007 +#define GPIO_PIN23_INT_TYPE_S 7 + +/* GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN23_SYNC1_BYPASS_S 3 + +/* GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN23_PAD_DRIVER_S 2 + +/* GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN23_SYNC2_BYPASS_S 0 + +/* GPIO_PIN24_REG register + * Configuration for GPIO pin 24 + */ + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) + +/* GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001F +#define GPIO_PIN24_INT_ENA_S 13 + +/* GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) +#define GPIO_PIN24_CONFIG_V 0x00000003 +#define GPIO_PIN24_CONFIG_S 11 + +/* GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007 +#define GPIO_PIN24_INT_TYPE_S 7 + +/* GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN24_SYNC1_BYPASS_S 3 + +/* GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN24_PAD_DRIVER_S 2 + +/* GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN24_SYNC2_BYPASS_S 0 + +/* GPIO_PIN25_REG register + * Configuration for GPIO pin 25 + */ + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) + +/* GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001F +#define GPIO_PIN25_INT_ENA_S 13 + +/* GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) +#define GPIO_PIN25_CONFIG_V 0x00000003 +#define GPIO_PIN25_CONFIG_S 11 + +/* GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007 +#define GPIO_PIN25_INT_TYPE_S 7 + +/* GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN25_SYNC1_BYPASS_S 3 + +/* GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN25_PAD_DRIVER_S 2 + +/* GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN25_SYNC2_BYPASS_S 0 + +/* GPIO_PIN26_REG register + * Configuration for GPIO pin 26 + */ + +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) + +/* GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001F +#define GPIO_PIN26_INT_ENA_S 13 + +/* GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) +#define GPIO_PIN26_CONFIG_V 0x00000003 +#define GPIO_PIN26_CONFIG_S 11 + +/* GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007 +#define GPIO_PIN26_INT_TYPE_S 7 + +/* GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN26_SYNC1_BYPASS_S 3 + +/* GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN26_PAD_DRIVER_S 2 + +/* GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN26_SYNC2_BYPASS_S 0 + +/* GPIO_PIN27_REG register + * Configuration for GPIO pin 27 + */ + +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) + +/* GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001F +#define GPIO_PIN27_INT_ENA_S 13 + +/* GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) +#define GPIO_PIN27_CONFIG_V 0x00000003 +#define GPIO_PIN27_CONFIG_S 11 + +/* GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007 +#define GPIO_PIN27_INT_TYPE_S 7 + +/* GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN27_SYNC1_BYPASS_S 3 + +/* GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN27_PAD_DRIVER_S 2 + +/* GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN27_SYNC2_BYPASS_S 0 + +/* GPIO_PIN28_REG register + * Configuration for GPIO pin 28 + */ + +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) + +/* GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001F +#define GPIO_PIN28_INT_ENA_S 13 + +/* GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) +#define GPIO_PIN28_CONFIG_V 0x00000003 +#define GPIO_PIN28_CONFIG_S 11 + +/* GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007 +#define GPIO_PIN28_INT_TYPE_S 7 + +/* GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN28_SYNC1_BYPASS_S 3 + +/* GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN28_PAD_DRIVER_S 2 + +/* GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN28_SYNC2_BYPASS_S 0 + +/* GPIO_PIN29_REG register + * Configuration for GPIO pin 29 + */ + +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) + +/* GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001F +#define GPIO_PIN29_INT_ENA_S 13 + +/* GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) +#define GPIO_PIN29_CONFIG_V 0x00000003 +#define GPIO_PIN29_CONFIG_S 11 + +/* GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007 +#define GPIO_PIN29_INT_TYPE_S 7 + +/* GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN29_SYNC1_BYPASS_S 3 + +/* GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN29_PAD_DRIVER_S 2 + +/* GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN29_SYNC2_BYPASS_S 0 + +/* GPIO_PIN30_REG register + * Configuration for GPIO pin 30 + */ + +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) + +/* GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN30_INT_ENA 0x0000001F +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001F +#define GPIO_PIN30_INT_ENA_S 13 + +/* GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN30_CONFIG 0x00000003 +#define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) +#define GPIO_PIN30_CONFIG_V 0x00000003 +#define GPIO_PIN30_CONFIG_S 11 + +/* GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN30_INT_TYPE 0x00000007 +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007 +#define GPIO_PIN30_INT_TYPE_S 7 + +/* GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN30_SYNC1_BYPASS_S 3 + +/* GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN30_PAD_DRIVER_S 2 + +/* GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN30_SYNC2_BYPASS_S 0 + +/* GPIO_PIN31_REG register + * Configuration for GPIO pin 31 + */ + +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0) + +/* GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN31_INT_ENA 0x0000001F +#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) +#define GPIO_PIN31_INT_ENA_V 0x0000001F +#define GPIO_PIN31_INT_ENA_S 13 + +/* GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN31_CONFIG 0x00000003 +#define GPIO_PIN31_CONFIG_M (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S) +#define GPIO_PIN31_CONFIG_V 0x00000003 +#define GPIO_PIN31_CONFIG_S 11 + +/* GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN31_INT_TYPE 0x00000007 +#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) +#define GPIO_PIN31_INT_TYPE_V 0x00000007 +#define GPIO_PIN31_INT_TYPE_S 7 + +/* GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN31_SYNC1_BYPASS_S 3 + +/* GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) +#define GPIO_PIN31_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN31_PAD_DRIVER_S 2 + +/* GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN31_SYNC2_BYPASS_S 0 + +/* GPIO_PIN32_REG register + * Configuration for GPIO pin 32 + */ + +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4) + +/* GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN32_INT_ENA 0x0000001F +#define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) +#define GPIO_PIN32_INT_ENA_V 0x0000001F +#define GPIO_PIN32_INT_ENA_S 13 + +/* GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN32_CONFIG 0x00000003 +#define GPIO_PIN32_CONFIG_M (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S) +#define GPIO_PIN32_CONFIG_V 0x00000003 +#define GPIO_PIN32_CONFIG_S 11 + +/* GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN32_INT_TYPE 0x00000007 +#define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) +#define GPIO_PIN32_INT_TYPE_V 0x00000007 +#define GPIO_PIN32_INT_TYPE_S 7 + +/* GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN32_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) +#define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN32_SYNC1_BYPASS_S 3 + +/* GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) +#define GPIO_PIN32_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN32_PAD_DRIVER_S 2 + +/* GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN32_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) +#define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN32_SYNC2_BYPASS_S 0 + +/* GPIO_PIN33_REG register + * Configuration for GPIO pin 33 + */ + +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8) + +/* GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN33_INT_ENA 0x0000001F +#define GPIO_PIN33_INT_ENA_M (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S) +#define GPIO_PIN33_INT_ENA_V 0x0000001F +#define GPIO_PIN33_INT_ENA_S 13 + +/* GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN33_CONFIG 0x00000003 +#define GPIO_PIN33_CONFIG_M (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S) +#define GPIO_PIN33_CONFIG_V 0x00000003 +#define GPIO_PIN33_CONFIG_S 11 + +/* GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN33_INT_TYPE 0x00000007 +#define GPIO_PIN33_INT_TYPE_M (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S) +#define GPIO_PIN33_INT_TYPE_V 0x00000007 +#define GPIO_PIN33_INT_TYPE_S 7 + +/* GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN33_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN33_SYNC1_BYPASS_M (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S) +#define GPIO_PIN33_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN33_SYNC1_BYPASS_S 3 + +/* GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S) +#define GPIO_PIN33_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN33_PAD_DRIVER_S 2 + +/* GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN33_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN33_SYNC2_BYPASS_M (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S) +#define GPIO_PIN33_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN33_SYNC2_BYPASS_S 0 + +/* GPIO_PIN34_REG register + * Configuration for GPIO pin 34 + */ + +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc) + +/* GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN34_INT_ENA 0x0000001F +#define GPIO_PIN34_INT_ENA_M (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S) +#define GPIO_PIN34_INT_ENA_V 0x0000001F +#define GPIO_PIN34_INT_ENA_S 13 + +/* GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN34_CONFIG 0x00000003 +#define GPIO_PIN34_CONFIG_M (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S) +#define GPIO_PIN34_CONFIG_V 0x00000003 +#define GPIO_PIN34_CONFIG_S 11 + +/* GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN34_INT_TYPE 0x00000007 +#define GPIO_PIN34_INT_TYPE_M (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S) +#define GPIO_PIN34_INT_TYPE_V 0x00000007 +#define GPIO_PIN34_INT_TYPE_S 7 + +/* GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN34_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN34_SYNC1_BYPASS_M (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S) +#define GPIO_PIN34_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN34_SYNC1_BYPASS_S 3 + +/* GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S) +#define GPIO_PIN34_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN34_PAD_DRIVER_S 2 + +/* GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN34_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN34_SYNC2_BYPASS_M (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S) +#define GPIO_PIN34_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN34_SYNC2_BYPASS_S 0 + +/* GPIO_PIN35_REG register + * Configuration for GPIO pin 35 + */ + +#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100) + +/* GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN35_INT_ENA 0x0000001F +#define GPIO_PIN35_INT_ENA_M (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S) +#define GPIO_PIN35_INT_ENA_V 0x0000001F +#define GPIO_PIN35_INT_ENA_S 13 + +/* GPIO_PIN35_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN35_CONFIG 0x00000003 +#define GPIO_PIN35_CONFIG_M (GPIO_PIN35_CONFIG_V << GPIO_PIN35_CONFIG_S) +#define GPIO_PIN35_CONFIG_V 0x00000003 +#define GPIO_PIN35_CONFIG_S 11 + +/* GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_M (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S) +#define GPIO_PIN35_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN35_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN35_INT_TYPE 0x00000007 +#define GPIO_PIN35_INT_TYPE_M (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S) +#define GPIO_PIN35_INT_TYPE_V 0x00000007 +#define GPIO_PIN35_INT_TYPE_S 7 + +/* GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN35_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN35_SYNC1_BYPASS_M (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S) +#define GPIO_PIN35_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN35_SYNC1_BYPASS_S 3 + +/* GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_M (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S) +#define GPIO_PIN35_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN35_PAD_DRIVER_S 2 + +/* GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN35_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN35_SYNC2_BYPASS_M (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S) +#define GPIO_PIN35_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN35_SYNC2_BYPASS_S 0 + +/* GPIO_PIN36_REG register + * Configuration for GPIO pin 36 + */ + +#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104) + +/* GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN36_INT_ENA 0x0000001F +#define GPIO_PIN36_INT_ENA_M (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S) +#define GPIO_PIN36_INT_ENA_V 0x0000001F +#define GPIO_PIN36_INT_ENA_S 13 + +/* GPIO_PIN36_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN36_CONFIG 0x00000003 +#define GPIO_PIN36_CONFIG_M (GPIO_PIN36_CONFIG_V << GPIO_PIN36_CONFIG_S) +#define GPIO_PIN36_CONFIG_V 0x00000003 +#define GPIO_PIN36_CONFIG_S 11 + +/* GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_M (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S) +#define GPIO_PIN36_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN36_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN36_INT_TYPE 0x00000007 +#define GPIO_PIN36_INT_TYPE_M (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S) +#define GPIO_PIN36_INT_TYPE_V 0x00000007 +#define GPIO_PIN36_INT_TYPE_S 7 + +/* GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN36_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN36_SYNC1_BYPASS_M (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S) +#define GPIO_PIN36_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN36_SYNC1_BYPASS_S 3 + +/* GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_M (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S) +#define GPIO_PIN36_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN36_PAD_DRIVER_S 2 + +/* GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN36_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN36_SYNC2_BYPASS_M (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S) +#define GPIO_PIN36_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN36_SYNC2_BYPASS_S 0 + +/* GPIO_PIN37_REG register + * Configuration for GPIO pin 37 + */ + +#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108) + +/* GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN37_INT_ENA 0x0000001F +#define GPIO_PIN37_INT_ENA_M (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S) +#define GPIO_PIN37_INT_ENA_V 0x0000001F +#define GPIO_PIN37_INT_ENA_S 13 + +/* GPIO_PIN37_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN37_CONFIG 0x00000003 +#define GPIO_PIN37_CONFIG_M (GPIO_PIN37_CONFIG_V << GPIO_PIN37_CONFIG_S) +#define GPIO_PIN37_CONFIG_V 0x00000003 +#define GPIO_PIN37_CONFIG_S 11 + +/* GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_M (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S) +#define GPIO_PIN37_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN37_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN37_INT_TYPE 0x00000007 +#define GPIO_PIN37_INT_TYPE_M (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S) +#define GPIO_PIN37_INT_TYPE_V 0x00000007 +#define GPIO_PIN37_INT_TYPE_S 7 + +/* GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN37_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN37_SYNC1_BYPASS_M (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S) +#define GPIO_PIN37_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN37_SYNC1_BYPASS_S 3 + +/* GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_M (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S) +#define GPIO_PIN37_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN37_PAD_DRIVER_S 2 + +/* GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN37_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN37_SYNC2_BYPASS_M (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S) +#define GPIO_PIN37_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN37_SYNC2_BYPASS_S 0 + +/* GPIO_PIN38_REG register + * Configuration for GPIO pin 38 + */ + +#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10c) + +/* GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN38_INT_ENA 0x0000001F +#define GPIO_PIN38_INT_ENA_M (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S) +#define GPIO_PIN38_INT_ENA_V 0x0000001F +#define GPIO_PIN38_INT_ENA_S 13 + +/* GPIO_PIN38_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN38_CONFIG 0x00000003 +#define GPIO_PIN38_CONFIG_M (GPIO_PIN38_CONFIG_V << GPIO_PIN38_CONFIG_S) +#define GPIO_PIN38_CONFIG_V 0x00000003 +#define GPIO_PIN38_CONFIG_S 11 + +/* GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_M (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S) +#define GPIO_PIN38_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN38_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN38_INT_TYPE 0x00000007 +#define GPIO_PIN38_INT_TYPE_M (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S) +#define GPIO_PIN38_INT_TYPE_V 0x00000007 +#define GPIO_PIN38_INT_TYPE_S 7 + +/* GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN38_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN38_SYNC1_BYPASS_M (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S) +#define GPIO_PIN38_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN38_SYNC1_BYPASS_S 3 + +/* GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_M (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S) +#define GPIO_PIN38_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN38_PAD_DRIVER_S 2 + +/* GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN38_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN38_SYNC2_BYPASS_M (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S) +#define GPIO_PIN38_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN38_SYNC2_BYPASS_S 0 + +/* GPIO_PIN39_REG register + * Configuration for GPIO pin 39 + */ + +#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110) + +/* GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN39_INT_ENA 0x0000001F +#define GPIO_PIN39_INT_ENA_M (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S) +#define GPIO_PIN39_INT_ENA_V 0x0000001F +#define GPIO_PIN39_INT_ENA_S 13 + +/* GPIO_PIN39_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN39_CONFIG 0x00000003 +#define GPIO_PIN39_CONFIG_M (GPIO_PIN39_CONFIG_V << GPIO_PIN39_CONFIG_S) +#define GPIO_PIN39_CONFIG_V 0x00000003 +#define GPIO_PIN39_CONFIG_S 11 + +/* GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_M (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S) +#define GPIO_PIN39_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN39_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN39_INT_TYPE 0x00000007 +#define GPIO_PIN39_INT_TYPE_M (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S) +#define GPIO_PIN39_INT_TYPE_V 0x00000007 +#define GPIO_PIN39_INT_TYPE_S 7 + +/* GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN39_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN39_SYNC1_BYPASS_M (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S) +#define GPIO_PIN39_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN39_SYNC1_BYPASS_S 3 + +/* GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_M (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S) +#define GPIO_PIN39_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN39_PAD_DRIVER_S 2 + +/* GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN39_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN39_SYNC2_BYPASS_M (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S) +#define GPIO_PIN39_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN39_SYNC2_BYPASS_S 0 + +/* GPIO_PIN40_REG register + * Configuration for GPIO pin 40 + */ + +#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114) + +/* GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN40_INT_ENA 0x0000001F +#define GPIO_PIN40_INT_ENA_M (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S) +#define GPIO_PIN40_INT_ENA_V 0x0000001F +#define GPIO_PIN40_INT_ENA_S 13 + +/* GPIO_PIN40_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN40_CONFIG 0x00000003 +#define GPIO_PIN40_CONFIG_M (GPIO_PIN40_CONFIG_V << GPIO_PIN40_CONFIG_S) +#define GPIO_PIN40_CONFIG_V 0x00000003 +#define GPIO_PIN40_CONFIG_S 11 + +/* GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN40_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN40_WAKEUP_ENABLE_M (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S) +#define GPIO_PIN40_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN40_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN40_INT_TYPE 0x00000007 +#define GPIO_PIN40_INT_TYPE_M (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S) +#define GPIO_PIN40_INT_TYPE_V 0x00000007 +#define GPIO_PIN40_INT_TYPE_S 7 + +/* GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN40_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN40_SYNC1_BYPASS_M (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S) +#define GPIO_PIN40_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN40_SYNC1_BYPASS_S 3 + +/* GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN40_PAD_DRIVER (BIT(2)) +#define GPIO_PIN40_PAD_DRIVER_M (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S) +#define GPIO_PIN40_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN40_PAD_DRIVER_S 2 + +/* GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN40_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN40_SYNC2_BYPASS_M (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S) +#define GPIO_PIN40_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN40_SYNC2_BYPASS_S 0 + +/* GPIO_PIN41_REG register + * Configuration for GPIO pin 41 + */ + +#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118) + +/* GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN41_INT_ENA 0x0000001F +#define GPIO_PIN41_INT_ENA_M (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S) +#define GPIO_PIN41_INT_ENA_V 0x0000001F +#define GPIO_PIN41_INT_ENA_S 13 + +/* GPIO_PIN41_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN41_CONFIG 0x00000003 +#define GPIO_PIN41_CONFIG_M (GPIO_PIN41_CONFIG_V << GPIO_PIN41_CONFIG_S) +#define GPIO_PIN41_CONFIG_V 0x00000003 +#define GPIO_PIN41_CONFIG_S 11 + +/* GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN41_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN41_WAKEUP_ENABLE_M (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S) +#define GPIO_PIN41_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN41_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN41_INT_TYPE 0x00000007 +#define GPIO_PIN41_INT_TYPE_M (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S) +#define GPIO_PIN41_INT_TYPE_V 0x00000007 +#define GPIO_PIN41_INT_TYPE_S 7 + +/* GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN41_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN41_SYNC1_BYPASS_M (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S) +#define GPIO_PIN41_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN41_SYNC1_BYPASS_S 3 + +/* GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN41_PAD_DRIVER (BIT(2)) +#define GPIO_PIN41_PAD_DRIVER_M (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S) +#define GPIO_PIN41_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN41_PAD_DRIVER_S 2 + +/* GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN41_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN41_SYNC2_BYPASS_M (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S) +#define GPIO_PIN41_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN41_SYNC2_BYPASS_S 0 + +/* GPIO_PIN42_REG register + * Configuration for GPIO pin 42 + */ + +#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11c) + +/* GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN42_INT_ENA 0x0000001F +#define GPIO_PIN42_INT_ENA_M (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S) +#define GPIO_PIN42_INT_ENA_V 0x0000001F +#define GPIO_PIN42_INT_ENA_S 13 + +/* GPIO_PIN42_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN42_CONFIG 0x00000003 +#define GPIO_PIN42_CONFIG_M (GPIO_PIN42_CONFIG_V << GPIO_PIN42_CONFIG_S) +#define GPIO_PIN42_CONFIG_V 0x00000003 +#define GPIO_PIN42_CONFIG_S 11 + +/* GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN42_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN42_WAKEUP_ENABLE_M (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S) +#define GPIO_PIN42_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN42_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN42_INT_TYPE 0x00000007 +#define GPIO_PIN42_INT_TYPE_M (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S) +#define GPIO_PIN42_INT_TYPE_V 0x00000007 +#define GPIO_PIN42_INT_TYPE_S 7 + +/* GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN42_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN42_SYNC1_BYPASS_M (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S) +#define GPIO_PIN42_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN42_SYNC1_BYPASS_S 3 + +/* GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN42_PAD_DRIVER (BIT(2)) +#define GPIO_PIN42_PAD_DRIVER_M (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S) +#define GPIO_PIN42_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN42_PAD_DRIVER_S 2 + +/* GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN42_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN42_SYNC2_BYPASS_M (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S) +#define GPIO_PIN42_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN42_SYNC2_BYPASS_S 0 + +/* GPIO_PIN43_REG register + * Configuration for GPIO pin 43 + */ + +#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120) + +/* GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN43_INT_ENA 0x0000001F +#define GPIO_PIN43_INT_ENA_M (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S) +#define GPIO_PIN43_INT_ENA_V 0x0000001F +#define GPIO_PIN43_INT_ENA_S 13 + +/* GPIO_PIN43_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN43_CONFIG 0x00000003 +#define GPIO_PIN43_CONFIG_M (GPIO_PIN43_CONFIG_V << GPIO_PIN43_CONFIG_S) +#define GPIO_PIN43_CONFIG_V 0x00000003 +#define GPIO_PIN43_CONFIG_S 11 + +/* GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN43_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN43_WAKEUP_ENABLE_M (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S) +#define GPIO_PIN43_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN43_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN43_INT_TYPE 0x00000007 +#define GPIO_PIN43_INT_TYPE_M (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S) +#define GPIO_PIN43_INT_TYPE_V 0x00000007 +#define GPIO_PIN43_INT_TYPE_S 7 + +/* GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN43_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN43_SYNC1_BYPASS_M (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S) +#define GPIO_PIN43_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN43_SYNC1_BYPASS_S 3 + +/* GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN43_PAD_DRIVER (BIT(2)) +#define GPIO_PIN43_PAD_DRIVER_M (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S) +#define GPIO_PIN43_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN43_PAD_DRIVER_S 2 + +/* GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN43_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN43_SYNC2_BYPASS_M (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S) +#define GPIO_PIN43_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN43_SYNC2_BYPASS_S 0 + +/* GPIO_PIN44_REG register + * Configuration for GPIO pin 44 + */ + +#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124) + +/* GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN44_INT_ENA 0x0000001F +#define GPIO_PIN44_INT_ENA_M (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S) +#define GPIO_PIN44_INT_ENA_V 0x0000001F +#define GPIO_PIN44_INT_ENA_S 13 + +/* GPIO_PIN44_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN44_CONFIG 0x00000003 +#define GPIO_PIN44_CONFIG_M (GPIO_PIN44_CONFIG_V << GPIO_PIN44_CONFIG_S) +#define GPIO_PIN44_CONFIG_V 0x00000003 +#define GPIO_PIN44_CONFIG_S 11 + +/* GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN44_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN44_WAKEUP_ENABLE_M (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S) +#define GPIO_PIN44_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN44_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN44_INT_TYPE 0x00000007 +#define GPIO_PIN44_INT_TYPE_M (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S) +#define GPIO_PIN44_INT_TYPE_V 0x00000007 +#define GPIO_PIN44_INT_TYPE_S 7 + +/* GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN44_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN44_SYNC1_BYPASS_M (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S) +#define GPIO_PIN44_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN44_SYNC1_BYPASS_S 3 + +/* GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN44_PAD_DRIVER (BIT(2)) +#define GPIO_PIN44_PAD_DRIVER_M (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S) +#define GPIO_PIN44_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN44_PAD_DRIVER_S 2 + +/* GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN44_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN44_SYNC2_BYPASS_M (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S) +#define GPIO_PIN44_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN44_SYNC2_BYPASS_S 0 + +/* GPIO_PIN45_REG register + * Configuration for GPIO pin 45 + */ + +#define GPIO_PIN45_REG (DR_REG_GPIO_BASE + 0x128) + +/* GPIO_PIN45_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN45_INT_ENA 0x0000001F +#define GPIO_PIN45_INT_ENA_M (GPIO_PIN45_INT_ENA_V << GPIO_PIN45_INT_ENA_S) +#define GPIO_PIN45_INT_ENA_V 0x0000001F +#define GPIO_PIN45_INT_ENA_S 13 + +/* GPIO_PIN45_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN45_CONFIG 0x00000003 +#define GPIO_PIN45_CONFIG_M (GPIO_PIN45_CONFIG_V << GPIO_PIN45_CONFIG_S) +#define GPIO_PIN45_CONFIG_V 0x00000003 +#define GPIO_PIN45_CONFIG_S 11 + +/* GPIO_PIN45_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN45_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN45_WAKEUP_ENABLE_M (GPIO_PIN45_WAKEUP_ENABLE_V << GPIO_PIN45_WAKEUP_ENABLE_S) +#define GPIO_PIN45_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN45_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN45_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN45_INT_TYPE 0x00000007 +#define GPIO_PIN45_INT_TYPE_M (GPIO_PIN45_INT_TYPE_V << GPIO_PIN45_INT_TYPE_S) +#define GPIO_PIN45_INT_TYPE_V 0x00000007 +#define GPIO_PIN45_INT_TYPE_S 7 + +/* GPIO_PIN45_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN45_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN45_SYNC1_BYPASS_M (GPIO_PIN45_SYNC1_BYPASS_V << GPIO_PIN45_SYNC1_BYPASS_S) +#define GPIO_PIN45_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN45_SYNC1_BYPASS_S 3 + +/* GPIO_PIN45_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN45_PAD_DRIVER (BIT(2)) +#define GPIO_PIN45_PAD_DRIVER_M (GPIO_PIN45_PAD_DRIVER_V << GPIO_PIN45_PAD_DRIVER_S) +#define GPIO_PIN45_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN45_PAD_DRIVER_S 2 + +/* GPIO_PIN45_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN45_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN45_SYNC2_BYPASS_M (GPIO_PIN45_SYNC2_BYPASS_V << GPIO_PIN45_SYNC2_BYPASS_S) +#define GPIO_PIN45_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN45_SYNC2_BYPASS_S 0 + +/* GPIO_PIN46_REG register + * Configuration for GPIO pin 46 + */ + +#define GPIO_PIN46_REG (DR_REG_GPIO_BASE + 0x12c) + +/* GPIO_PIN46_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN46_INT_ENA 0x0000001F +#define GPIO_PIN46_INT_ENA_M (GPIO_PIN46_INT_ENA_V << GPIO_PIN46_INT_ENA_S) +#define GPIO_PIN46_INT_ENA_V 0x0000001F +#define GPIO_PIN46_INT_ENA_S 13 + +/* GPIO_PIN46_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN46_CONFIG 0x00000003 +#define GPIO_PIN46_CONFIG_M (GPIO_PIN46_CONFIG_V << GPIO_PIN46_CONFIG_S) +#define GPIO_PIN46_CONFIG_V 0x00000003 +#define GPIO_PIN46_CONFIG_S 11 + +/* GPIO_PIN46_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN46_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN46_WAKEUP_ENABLE_M (GPIO_PIN46_WAKEUP_ENABLE_V << GPIO_PIN46_WAKEUP_ENABLE_S) +#define GPIO_PIN46_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN46_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN46_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN46_INT_TYPE 0x00000007 +#define GPIO_PIN46_INT_TYPE_M (GPIO_PIN46_INT_TYPE_V << GPIO_PIN46_INT_TYPE_S) +#define GPIO_PIN46_INT_TYPE_V 0x00000007 +#define GPIO_PIN46_INT_TYPE_S 7 + +/* GPIO_PIN46_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN46_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN46_SYNC1_BYPASS_M (GPIO_PIN46_SYNC1_BYPASS_V << GPIO_PIN46_SYNC1_BYPASS_S) +#define GPIO_PIN46_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN46_SYNC1_BYPASS_S 3 + +/* GPIO_PIN46_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN46_PAD_DRIVER (BIT(2)) +#define GPIO_PIN46_PAD_DRIVER_M (GPIO_PIN46_PAD_DRIVER_V << GPIO_PIN46_PAD_DRIVER_S) +#define GPIO_PIN46_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN46_PAD_DRIVER_S 2 + +/* GPIO_PIN46_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN46_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN46_SYNC2_BYPASS_M (GPIO_PIN46_SYNC2_BYPASS_V << GPIO_PIN46_SYNC2_BYPASS_S) +#define GPIO_PIN46_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN46_SYNC2_BYPASS_S 0 + +/* GPIO_PIN47_REG register + * Configuration for GPIO pin 47 + */ + +#define GPIO_PIN47_REG (DR_REG_GPIO_BASE + 0x130) + +/* GPIO_PIN47_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN47_INT_ENA 0x0000001F +#define GPIO_PIN47_INT_ENA_M (GPIO_PIN47_INT_ENA_V << GPIO_PIN47_INT_ENA_S) +#define GPIO_PIN47_INT_ENA_V 0x0000001F +#define GPIO_PIN47_INT_ENA_S 13 + +/* GPIO_PIN47_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN47_CONFIG 0x00000003 +#define GPIO_PIN47_CONFIG_M (GPIO_PIN47_CONFIG_V << GPIO_PIN47_CONFIG_S) +#define GPIO_PIN47_CONFIG_V 0x00000003 +#define GPIO_PIN47_CONFIG_S 11 + +/* GPIO_PIN47_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN47_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN47_WAKEUP_ENABLE_M (GPIO_PIN47_WAKEUP_ENABLE_V << GPIO_PIN47_WAKEUP_ENABLE_S) +#define GPIO_PIN47_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN47_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN47_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN47_INT_TYPE 0x00000007 +#define GPIO_PIN47_INT_TYPE_M (GPIO_PIN47_INT_TYPE_V << GPIO_PIN47_INT_TYPE_S) +#define GPIO_PIN47_INT_TYPE_V 0x00000007 +#define GPIO_PIN47_INT_TYPE_S 7 + +/* GPIO_PIN47_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN47_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN47_SYNC1_BYPASS_M (GPIO_PIN47_SYNC1_BYPASS_V << GPIO_PIN47_SYNC1_BYPASS_S) +#define GPIO_PIN47_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN47_SYNC1_BYPASS_S 3 + +/* GPIO_PIN47_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN47_PAD_DRIVER (BIT(2)) +#define GPIO_PIN47_PAD_DRIVER_M (GPIO_PIN47_PAD_DRIVER_V << GPIO_PIN47_PAD_DRIVER_S) +#define GPIO_PIN47_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN47_PAD_DRIVER_S 2 + +/* GPIO_PIN47_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN47_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN47_SYNC2_BYPASS_M (GPIO_PIN47_SYNC2_BYPASS_V << GPIO_PIN47_SYNC2_BYPASS_S) +#define GPIO_PIN47_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN47_SYNC2_BYPASS_S 0 + +/* GPIO_PIN48_REG register + * Configuration for GPIO pin 48 + */ + +#define GPIO_PIN48_REG (DR_REG_GPIO_BASE + 0x134) + +/* GPIO_PIN48_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN48_INT_ENA 0x0000001F +#define GPIO_PIN48_INT_ENA_M (GPIO_PIN48_INT_ENA_V << GPIO_PIN48_INT_ENA_S) +#define GPIO_PIN48_INT_ENA_V 0x0000001F +#define GPIO_PIN48_INT_ENA_S 13 + +/* GPIO_PIN48_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN48_CONFIG 0x00000003 +#define GPIO_PIN48_CONFIG_M (GPIO_PIN48_CONFIG_V << GPIO_PIN48_CONFIG_S) +#define GPIO_PIN48_CONFIG_V 0x00000003 +#define GPIO_PIN48_CONFIG_S 11 + +/* GPIO_PIN48_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN48_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN48_WAKEUP_ENABLE_M (GPIO_PIN48_WAKEUP_ENABLE_V << GPIO_PIN48_WAKEUP_ENABLE_S) +#define GPIO_PIN48_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN48_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN48_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN48_INT_TYPE 0x00000007 +#define GPIO_PIN48_INT_TYPE_M (GPIO_PIN48_INT_TYPE_V << GPIO_PIN48_INT_TYPE_S) +#define GPIO_PIN48_INT_TYPE_V 0x00000007 +#define GPIO_PIN48_INT_TYPE_S 7 + +/* GPIO_PIN48_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN48_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN48_SYNC1_BYPASS_M (GPIO_PIN48_SYNC1_BYPASS_V << GPIO_PIN48_SYNC1_BYPASS_S) +#define GPIO_PIN48_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN48_SYNC1_BYPASS_S 3 + +/* GPIO_PIN48_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN48_PAD_DRIVER (BIT(2)) +#define GPIO_PIN48_PAD_DRIVER_M (GPIO_PIN48_PAD_DRIVER_V << GPIO_PIN48_PAD_DRIVER_S) +#define GPIO_PIN48_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN48_PAD_DRIVER_S 2 + +/* GPIO_PIN48_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN48_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN48_SYNC2_BYPASS_M (GPIO_PIN48_SYNC2_BYPASS_V << GPIO_PIN48_SYNC2_BYPASS_S) +#define GPIO_PIN48_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN48_SYNC2_BYPASS_S 0 + +/* GPIO_PIN49_REG register + * Configuration for GPIO pin 49 + */ + +#define GPIO_PIN49_REG (DR_REG_GPIO_BASE + 0x138) + +/* GPIO_PIN49_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN49_INT_ENA 0x0000001F +#define GPIO_PIN49_INT_ENA_M (GPIO_PIN49_INT_ENA_V << GPIO_PIN49_INT_ENA_S) +#define GPIO_PIN49_INT_ENA_V 0x0000001F +#define GPIO_PIN49_INT_ENA_S 13 + +/* GPIO_PIN49_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN49_CONFIG 0x00000003 +#define GPIO_PIN49_CONFIG_M (GPIO_PIN49_CONFIG_V << GPIO_PIN49_CONFIG_S) +#define GPIO_PIN49_CONFIG_V 0x00000003 +#define GPIO_PIN49_CONFIG_S 11 + +/* GPIO_PIN49_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN49_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN49_WAKEUP_ENABLE_M (GPIO_PIN49_WAKEUP_ENABLE_V << GPIO_PIN49_WAKEUP_ENABLE_S) +#define GPIO_PIN49_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN49_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN49_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN49_INT_TYPE 0x00000007 +#define GPIO_PIN49_INT_TYPE_M (GPIO_PIN49_INT_TYPE_V << GPIO_PIN49_INT_TYPE_S) +#define GPIO_PIN49_INT_TYPE_V 0x00000007 +#define GPIO_PIN49_INT_TYPE_S 7 + +/* GPIO_PIN49_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN49_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN49_SYNC1_BYPASS_M (GPIO_PIN49_SYNC1_BYPASS_V << GPIO_PIN49_SYNC1_BYPASS_S) +#define GPIO_PIN49_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN49_SYNC1_BYPASS_S 3 + +/* GPIO_PIN49_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN49_PAD_DRIVER (BIT(2)) +#define GPIO_PIN49_PAD_DRIVER_M (GPIO_PIN49_PAD_DRIVER_V << GPIO_PIN49_PAD_DRIVER_S) +#define GPIO_PIN49_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN49_PAD_DRIVER_S 2 + +/* GPIO_PIN49_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN49_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN49_SYNC2_BYPASS_M (GPIO_PIN49_SYNC2_BYPASS_V << GPIO_PIN49_SYNC2_BYPASS_S) +#define GPIO_PIN49_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN49_SYNC2_BYPASS_S 0 + +/* GPIO_PIN50_REG register + * Configuration for GPIO pin 50 + */ + +#define GPIO_PIN50_REG (DR_REG_GPIO_BASE + 0x13c) + +/* GPIO_PIN50_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN50_INT_ENA 0x0000001F +#define GPIO_PIN50_INT_ENA_M (GPIO_PIN50_INT_ENA_V << GPIO_PIN50_INT_ENA_S) +#define GPIO_PIN50_INT_ENA_V 0x0000001F +#define GPIO_PIN50_INT_ENA_S 13 + +/* GPIO_PIN50_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN50_CONFIG 0x00000003 +#define GPIO_PIN50_CONFIG_M (GPIO_PIN50_CONFIG_V << GPIO_PIN50_CONFIG_S) +#define GPIO_PIN50_CONFIG_V 0x00000003 +#define GPIO_PIN50_CONFIG_S 11 + +/* GPIO_PIN50_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN50_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN50_WAKEUP_ENABLE_M (GPIO_PIN50_WAKEUP_ENABLE_V << GPIO_PIN50_WAKEUP_ENABLE_S) +#define GPIO_PIN50_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN50_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN50_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN50_INT_TYPE 0x00000007 +#define GPIO_PIN50_INT_TYPE_M (GPIO_PIN50_INT_TYPE_V << GPIO_PIN50_INT_TYPE_S) +#define GPIO_PIN50_INT_TYPE_V 0x00000007 +#define GPIO_PIN50_INT_TYPE_S 7 + +/* GPIO_PIN50_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN50_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN50_SYNC1_BYPASS_M (GPIO_PIN50_SYNC1_BYPASS_V << GPIO_PIN50_SYNC1_BYPASS_S) +#define GPIO_PIN50_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN50_SYNC1_BYPASS_S 3 + +/* GPIO_PIN50_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN50_PAD_DRIVER (BIT(2)) +#define GPIO_PIN50_PAD_DRIVER_M (GPIO_PIN50_PAD_DRIVER_V << GPIO_PIN50_PAD_DRIVER_S) +#define GPIO_PIN50_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN50_PAD_DRIVER_S 2 + +/* GPIO_PIN50_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN50_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN50_SYNC2_BYPASS_M (GPIO_PIN50_SYNC2_BYPASS_V << GPIO_PIN50_SYNC2_BYPASS_S) +#define GPIO_PIN50_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN50_SYNC2_BYPASS_S 0 + +/* GPIO_PIN51_REG register + * Configuration for GPIO pin 51 + */ + +#define GPIO_PIN51_REG (DR_REG_GPIO_BASE + 0x140) + +/* GPIO_PIN51_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN51_INT_ENA 0x0000001F +#define GPIO_PIN51_INT_ENA_M (GPIO_PIN51_INT_ENA_V << GPIO_PIN51_INT_ENA_S) +#define GPIO_PIN51_INT_ENA_V 0x0000001F +#define GPIO_PIN51_INT_ENA_S 13 + +/* GPIO_PIN51_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN51_CONFIG 0x00000003 +#define GPIO_PIN51_CONFIG_M (GPIO_PIN51_CONFIG_V << GPIO_PIN51_CONFIG_S) +#define GPIO_PIN51_CONFIG_V 0x00000003 +#define GPIO_PIN51_CONFIG_S 11 + +/* GPIO_PIN51_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN51_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN51_WAKEUP_ENABLE_M (GPIO_PIN51_WAKEUP_ENABLE_V << GPIO_PIN51_WAKEUP_ENABLE_S) +#define GPIO_PIN51_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN51_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN51_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN51_INT_TYPE 0x00000007 +#define GPIO_PIN51_INT_TYPE_M (GPIO_PIN51_INT_TYPE_V << GPIO_PIN51_INT_TYPE_S) +#define GPIO_PIN51_INT_TYPE_V 0x00000007 +#define GPIO_PIN51_INT_TYPE_S 7 + +/* GPIO_PIN51_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN51_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN51_SYNC1_BYPASS_M (GPIO_PIN51_SYNC1_BYPASS_V << GPIO_PIN51_SYNC1_BYPASS_S) +#define GPIO_PIN51_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN51_SYNC1_BYPASS_S 3 + +/* GPIO_PIN51_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN51_PAD_DRIVER (BIT(2)) +#define GPIO_PIN51_PAD_DRIVER_M (GPIO_PIN51_PAD_DRIVER_V << GPIO_PIN51_PAD_DRIVER_S) +#define GPIO_PIN51_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN51_PAD_DRIVER_S 2 + +/* GPIO_PIN51_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN51_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN51_SYNC2_BYPASS_M (GPIO_PIN51_SYNC2_BYPASS_V << GPIO_PIN51_SYNC2_BYPASS_S) +#define GPIO_PIN51_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN51_SYNC2_BYPASS_S 0 + +/* GPIO_PIN52_REG register + * Configuration for GPIO pin 52 + */ + +#define GPIO_PIN52_REG (DR_REG_GPIO_BASE + 0x144) + +/* GPIO_PIN52_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN52_INT_ENA 0x0000001F +#define GPIO_PIN52_INT_ENA_M (GPIO_PIN52_INT_ENA_V << GPIO_PIN52_INT_ENA_S) +#define GPIO_PIN52_INT_ENA_V 0x0000001F +#define GPIO_PIN52_INT_ENA_S 13 + +/* GPIO_PIN52_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN52_CONFIG 0x00000003 +#define GPIO_PIN52_CONFIG_M (GPIO_PIN52_CONFIG_V << GPIO_PIN52_CONFIG_S) +#define GPIO_PIN52_CONFIG_V 0x00000003 +#define GPIO_PIN52_CONFIG_S 11 + +/* GPIO_PIN52_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN52_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN52_WAKEUP_ENABLE_M (GPIO_PIN52_WAKEUP_ENABLE_V << GPIO_PIN52_WAKEUP_ENABLE_S) +#define GPIO_PIN52_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN52_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN52_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN52_INT_TYPE 0x00000007 +#define GPIO_PIN52_INT_TYPE_M (GPIO_PIN52_INT_TYPE_V << GPIO_PIN52_INT_TYPE_S) +#define GPIO_PIN52_INT_TYPE_V 0x00000007 +#define GPIO_PIN52_INT_TYPE_S 7 + +/* GPIO_PIN52_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN52_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN52_SYNC1_BYPASS_M (GPIO_PIN52_SYNC1_BYPASS_V << GPIO_PIN52_SYNC1_BYPASS_S) +#define GPIO_PIN52_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN52_SYNC1_BYPASS_S 3 + +/* GPIO_PIN52_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN52_PAD_DRIVER (BIT(2)) +#define GPIO_PIN52_PAD_DRIVER_M (GPIO_PIN52_PAD_DRIVER_V << GPIO_PIN52_PAD_DRIVER_S) +#define GPIO_PIN52_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN52_PAD_DRIVER_S 2 + +/* GPIO_PIN52_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN52_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN52_SYNC2_BYPASS_M (GPIO_PIN52_SYNC2_BYPASS_V << GPIO_PIN52_SYNC2_BYPASS_S) +#define GPIO_PIN52_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN52_SYNC2_BYPASS_S 0 + +/* GPIO_PIN53_REG register + * Configuration for GPIO pin 53 + */ + +#define GPIO_PIN53_REG (DR_REG_GPIO_BASE + 0x148) + +/* GPIO_PIN53_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN53_INT_ENA 0x0000001F +#define GPIO_PIN53_INT_ENA_M (GPIO_PIN53_INT_ENA_V << GPIO_PIN53_INT_ENA_S) +#define GPIO_PIN53_INT_ENA_V 0x0000001F +#define GPIO_PIN53_INT_ENA_S 13 + +/* GPIO_PIN53_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN53_CONFIG 0x00000003 +#define GPIO_PIN53_CONFIG_M (GPIO_PIN53_CONFIG_V << GPIO_PIN53_CONFIG_S) +#define GPIO_PIN53_CONFIG_V 0x00000003 +#define GPIO_PIN53_CONFIG_S 11 + +/* GPIO_PIN53_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN53_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN53_WAKEUP_ENABLE_M (GPIO_PIN53_WAKEUP_ENABLE_V << GPIO_PIN53_WAKEUP_ENABLE_S) +#define GPIO_PIN53_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN53_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN53_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN53_INT_TYPE 0x00000007 +#define GPIO_PIN53_INT_TYPE_M (GPIO_PIN53_INT_TYPE_V << GPIO_PIN53_INT_TYPE_S) +#define GPIO_PIN53_INT_TYPE_V 0x00000007 +#define GPIO_PIN53_INT_TYPE_S 7 + +/* GPIO_PIN53_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN53_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN53_SYNC1_BYPASS_M (GPIO_PIN53_SYNC1_BYPASS_V << GPIO_PIN53_SYNC1_BYPASS_S) +#define GPIO_PIN53_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN53_SYNC1_BYPASS_S 3 + +/* GPIO_PIN53_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN53_PAD_DRIVER (BIT(2)) +#define GPIO_PIN53_PAD_DRIVER_M (GPIO_PIN53_PAD_DRIVER_V << GPIO_PIN53_PAD_DRIVER_S) +#define GPIO_PIN53_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN53_PAD_DRIVER_S 2 + +/* GPIO_PIN53_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN53_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN53_SYNC2_BYPASS_M (GPIO_PIN53_SYNC2_BYPASS_V << GPIO_PIN53_SYNC2_BYPASS_S) +#define GPIO_PIN53_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN53_SYNC2_BYPASS_S 0 + +/* GPIO_STATUS_NEXT_REG register + * GPIO0 ~ 31 interrupt source register + */ + +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) + +/* GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; + * Interrupt source signal of GPIO0 ~ 31, could be rising edge interrupt, + * falling edge interrupt, level sensitive interrupt and any edge interrupt. + */ + +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/* GPIO_STATUS_NEXT1_REG register + * GPIO32 ~ 53 interrupt source register + */ + +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) + +/* GPIO_STATUS1_INTERRUPT_NEXT : RO; bitpos: [21:0]; default: 0; + * Interrupt source signal of GPIO32 ~ 53. + */ + +#define GPIO_STATUS1_INTERRUPT_NEXT 0x003FFFFF +#define GPIO_STATUS1_INTERRUPT_NEXT_M (GPIO_STATUS1_INTERRUPT_NEXT_V << GPIO_STATUS1_INTERRUPT_NEXT_S) +#define GPIO_STATUS1_INTERRUPT_NEXT_V 0x003FFFFF +#define GPIO_STATUS1_INTERRUPT_NEXT_S 0 + +/* GPIO_FUNC0_IN_SEL_CFG_REG register + * Peripheral function 0 input selection register + */ + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) + +/* GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001 +#define GPIO_SIG0_IN_SEL_S 7 + +/* GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC0_IN_INV_SEL_S 6 + +/* GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC0_IN_SEL 0x0000003F +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000003F +#define GPIO_FUNC0_IN_SEL_S 0 + +/* GPIO_FUNC1_IN_SEL_CFG_REG register + * Peripheral function 1 input selection register + */ + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) + +/* GPIO_SIG1_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL_M (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S) +#define GPIO_SIG1_IN_SEL_V 0x00000001 +#define GPIO_SIG1_IN_SEL_S 7 + +/* GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_M (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S) +#define GPIO_FUNC1_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC1_IN_INV_SEL_S 6 + +/* GPIO_FUNC1_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC1_IN_SEL 0x0000003F +#define GPIO_FUNC1_IN_SEL_M (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S) +#define GPIO_FUNC1_IN_SEL_V 0x0000003F +#define GPIO_FUNC1_IN_SEL_S 0 + +/* GPIO_FUNC2_IN_SEL_CFG_REG register + * Peripheral function 2 input selection register + */ + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) + +/* GPIO_SIG2_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL_M (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S) +#define GPIO_SIG2_IN_SEL_V 0x00000001 +#define GPIO_SIG2_IN_SEL_S 7 + +/* GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_M (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S) +#define GPIO_FUNC2_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC2_IN_INV_SEL_S 6 + +/* GPIO_FUNC2_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC2_IN_SEL 0x0000003F +#define GPIO_FUNC2_IN_SEL_M (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S) +#define GPIO_FUNC2_IN_SEL_V 0x0000003F +#define GPIO_FUNC2_IN_SEL_S 0 + +/* GPIO_FUNC3_IN_SEL_CFG_REG register + * Peripheral function 3 input selection register + */ + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) + +/* GPIO_SIG3_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL_M (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S) +#define GPIO_SIG3_IN_SEL_V 0x00000001 +#define GPIO_SIG3_IN_SEL_S 7 + +/* GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_M (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S) +#define GPIO_FUNC3_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC3_IN_INV_SEL_S 6 + +/* GPIO_FUNC3_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC3_IN_SEL 0x0000003F +#define GPIO_FUNC3_IN_SEL_M (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S) +#define GPIO_FUNC3_IN_SEL_V 0x0000003F +#define GPIO_FUNC3_IN_SEL_S 0 + +/* GPIO_FUNC4_IN_SEL_CFG_REG register + * Peripheral function 4 input selection register + */ + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) + +/* GPIO_SIG4_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL_M (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S) +#define GPIO_SIG4_IN_SEL_V 0x00000001 +#define GPIO_SIG4_IN_SEL_S 7 + +/* GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_M (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S) +#define GPIO_FUNC4_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC4_IN_INV_SEL_S 6 + +/* GPIO_FUNC4_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC4_IN_SEL 0x0000003F +#define GPIO_FUNC4_IN_SEL_M (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S) +#define GPIO_FUNC4_IN_SEL_V 0x0000003F +#define GPIO_FUNC4_IN_SEL_S 0 + +/* GPIO_FUNC5_IN_SEL_CFG_REG register + * Peripheral function 5 input selection register + */ + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) + +/* GPIO_SIG5_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL_M (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S) +#define GPIO_SIG5_IN_SEL_V 0x00000001 +#define GPIO_SIG5_IN_SEL_S 7 + +/* GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_M (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S) +#define GPIO_FUNC5_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC5_IN_INV_SEL_S 6 + +/* GPIO_FUNC5_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC5_IN_SEL 0x0000003F +#define GPIO_FUNC5_IN_SEL_M (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S) +#define GPIO_FUNC5_IN_SEL_V 0x0000003F +#define GPIO_FUNC5_IN_SEL_S 0 + +/* GPIO_FUNC6_IN_SEL_CFG_REG register + * Peripheral function 6 input selection register + */ + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) + +/* GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001 +#define GPIO_SIG6_IN_SEL_S 7 + +/* GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC6_IN_INV_SEL_S 6 + +/* GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC6_IN_SEL 0x0000003F +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000003F +#define GPIO_FUNC6_IN_SEL_S 0 + +/* GPIO_FUNC7_IN_SEL_CFG_REG register + * Peripheral function 7 input selection register + */ + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) + +/* GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001 +#define GPIO_SIG7_IN_SEL_S 7 + +/* GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC7_IN_INV_SEL_S 6 + +/* GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC7_IN_SEL 0x0000003F +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000003F +#define GPIO_FUNC7_IN_SEL_S 0 + +/* GPIO_FUNC8_IN_SEL_CFG_REG register + * Peripheral function 8 input selection register + */ + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) + +/* GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001 +#define GPIO_SIG8_IN_SEL_S 7 + +/* GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC8_IN_INV_SEL_S 6 + +/* GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC8_IN_SEL 0x0000003F +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000003F +#define GPIO_FUNC8_IN_SEL_S 0 + +/* GPIO_FUNC9_IN_SEL_CFG_REG register + * Peripheral function 9 input selection register + */ + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) + +/* GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001 +#define GPIO_SIG9_IN_SEL_S 7 + +/* GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC9_IN_INV_SEL_S 6 + +/* GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC9_IN_SEL 0x0000003F +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000003F +#define GPIO_FUNC9_IN_SEL_S 0 + +/* GPIO_FUNC10_IN_SEL_CFG_REG register + * Peripheral function 10 input selection register + */ + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) + +/* GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001 +#define GPIO_SIG10_IN_SEL_S 7 + +/* GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC10_IN_INV_SEL_S 6 + +/* GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC10_IN_SEL 0x0000003F +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000003F +#define GPIO_FUNC10_IN_SEL_S 0 + +/* GPIO_FUNC11_IN_SEL_CFG_REG register + * Peripheral function 11 input selection register + */ + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) + +/* GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001 +#define GPIO_SIG11_IN_SEL_S 7 + +/* GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC11_IN_INV_SEL_S 6 + +/* GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC11_IN_SEL 0x0000003F +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000003F +#define GPIO_FUNC11_IN_SEL_S 0 + +/* GPIO_FUNC12_IN_SEL_CFG_REG register + * Peripheral function 12 input selection register + */ + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) + +/* GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001 +#define GPIO_SIG12_IN_SEL_S 7 + +/* GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC12_IN_INV_SEL_S 6 + +/* GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC12_IN_SEL 0x0000003F +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000003F +#define GPIO_FUNC12_IN_SEL_S 0 + +/* GPIO_FUNC13_IN_SEL_CFG_REG register + * Peripheral function 13 input selection register + */ + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) + +/* GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001 +#define GPIO_SIG13_IN_SEL_S 7 + +/* GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC13_IN_INV_SEL_S 6 + +/* GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC13_IN_SEL 0x0000003F +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000003F +#define GPIO_FUNC13_IN_SEL_S 0 + +/* GPIO_FUNC14_IN_SEL_CFG_REG register + * Peripheral function 14 input selection register + */ + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) + +/* GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001 +#define GPIO_SIG14_IN_SEL_S 7 + +/* GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC14_IN_INV_SEL_S 6 + +/* GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC14_IN_SEL 0x0000003F +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000003F +#define GPIO_FUNC14_IN_SEL_S 0 + +/* GPIO_FUNC15_IN_SEL_CFG_REG register + * Peripheral function 15 input selection register + */ + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) + +/* GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001 +#define GPIO_SIG15_IN_SEL_S 7 + +/* GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC15_IN_INV_SEL_S 6 + +/* GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC15_IN_SEL 0x0000003F +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000003F +#define GPIO_FUNC15_IN_SEL_S 0 + +/* GPIO_FUNC16_IN_SEL_CFG_REG register + * Peripheral function 16 input selection register + */ + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) + +/* GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001 +#define GPIO_SIG16_IN_SEL_S 7 + +/* GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC16_IN_INV_SEL_S 6 + +/* GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC16_IN_SEL 0x0000003F +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000003F +#define GPIO_FUNC16_IN_SEL_S 0 + +/* GPIO_FUNC17_IN_SEL_CFG_REG register + * Peripheral function 17 input selection register + */ + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) + +/* GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001 +#define GPIO_SIG17_IN_SEL_S 7 + +/* GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC17_IN_INV_SEL_S 6 + +/* GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC17_IN_SEL 0x0000003F +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000003F +#define GPIO_FUNC17_IN_SEL_S 0 + +/* GPIO_FUNC18_IN_SEL_CFG_REG register + * Peripheral function 18 input selection register + */ + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c) + +/* GPIO_SIG18_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL_M (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S) +#define GPIO_SIG18_IN_SEL_V 0x00000001 +#define GPIO_SIG18_IN_SEL_S 7 + +/* GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_M (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S) +#define GPIO_FUNC18_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC18_IN_INV_SEL_S 6 + +/* GPIO_FUNC18_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC18_IN_SEL 0x0000003F +#define GPIO_FUNC18_IN_SEL_M (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S) +#define GPIO_FUNC18_IN_SEL_V 0x0000003F +#define GPIO_FUNC18_IN_SEL_S 0 + +/* GPIO_FUNC19_IN_SEL_CFG_REG register + * Peripheral function 19 input selection register + */ + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) + +/* GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) +#define GPIO_SIG19_IN_SEL_V 0x00000001 +#define GPIO_SIG19_IN_SEL_S 7 + +/* GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) +#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC19_IN_INV_SEL_S 6 + +/* GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC19_IN_SEL 0x0000003F +#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) +#define GPIO_FUNC19_IN_SEL_V 0x0000003F +#define GPIO_FUNC19_IN_SEL_S 0 + +/* GPIO_FUNC20_IN_SEL_CFG_REG register + * Peripheral function 20 input selection register + */ + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4) + +/* GPIO_SIG20_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL_M (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S) +#define GPIO_SIG20_IN_SEL_V 0x00000001 +#define GPIO_SIG20_IN_SEL_S 7 + +/* GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_M (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S) +#define GPIO_FUNC20_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC20_IN_INV_SEL_S 6 + +/* GPIO_FUNC20_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC20_IN_SEL 0x0000003F +#define GPIO_FUNC20_IN_SEL_M (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S) +#define GPIO_FUNC20_IN_SEL_V 0x0000003F +#define GPIO_FUNC20_IN_SEL_S 0 + +/* GPIO_FUNC21_IN_SEL_CFG_REG register + * Peripheral function 21 input selection register + */ + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) + +/* GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S) +#define GPIO_SIG21_IN_SEL_V 0x00000001 +#define GPIO_SIG21_IN_SEL_S 7 + +/* GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S) +#define GPIO_FUNC21_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC21_IN_INV_SEL_S 6 + +/* GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC21_IN_SEL 0x0000003F +#define GPIO_FUNC21_IN_SEL_M (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S) +#define GPIO_FUNC21_IN_SEL_V 0x0000003F +#define GPIO_FUNC21_IN_SEL_S 0 + +/* GPIO_FUNC22_IN_SEL_CFG_REG register + * Peripheral function 22 input selection register + */ + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) + +/* GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S) +#define GPIO_SIG22_IN_SEL_V 0x00000001 +#define GPIO_SIG22_IN_SEL_S 7 + +/* GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S) +#define GPIO_FUNC22_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC22_IN_INV_SEL_S 6 + +/* GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC22_IN_SEL 0x0000003F +#define GPIO_FUNC22_IN_SEL_M (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S) +#define GPIO_FUNC22_IN_SEL_V 0x0000003F +#define GPIO_FUNC22_IN_SEL_S 0 + +/* GPIO_FUNC23_IN_SEL_CFG_REG register + * Peripheral function 23 input selection register + */ + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) + +/* GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S) +#define GPIO_SIG23_IN_SEL_V 0x00000001 +#define GPIO_SIG23_IN_SEL_S 7 + +/* GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S) +#define GPIO_FUNC23_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC23_IN_INV_SEL_S 6 + +/* GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC23_IN_SEL 0x0000003F +#define GPIO_FUNC23_IN_SEL_M (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S) +#define GPIO_FUNC23_IN_SEL_V 0x0000003F +#define GPIO_FUNC23_IN_SEL_S 0 + +/* GPIO_FUNC24_IN_SEL_CFG_REG register + * Peripheral function 24 input selection register + */ + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) + +/* GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S) +#define GPIO_SIG24_IN_SEL_V 0x00000001 +#define GPIO_SIG24_IN_SEL_S 7 + +/* GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S) +#define GPIO_FUNC24_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC24_IN_INV_SEL_S 6 + +/* GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC24_IN_SEL 0x0000003F +#define GPIO_FUNC24_IN_SEL_M (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S) +#define GPIO_FUNC24_IN_SEL_V 0x0000003F +#define GPIO_FUNC24_IN_SEL_S 0 + +/* GPIO_FUNC25_IN_SEL_CFG_REG register + * Peripheral function 25 input selection register + */ + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8) + +/* GPIO_SIG25_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL_M (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S) +#define GPIO_SIG25_IN_SEL_V 0x00000001 +#define GPIO_SIG25_IN_SEL_S 7 + +/* GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_M (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S) +#define GPIO_FUNC25_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC25_IN_INV_SEL_S 6 + +/* GPIO_FUNC25_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC25_IN_SEL 0x0000003F +#define GPIO_FUNC25_IN_SEL_M (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S) +#define GPIO_FUNC25_IN_SEL_V 0x0000003F +#define GPIO_FUNC25_IN_SEL_S 0 + +/* GPIO_FUNC26_IN_SEL_CFG_REG register + * Peripheral function 26 input selection register + */ + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc) + +/* GPIO_SIG26_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL_M (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S) +#define GPIO_SIG26_IN_SEL_V 0x00000001 +#define GPIO_SIG26_IN_SEL_S 7 + +/* GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_M (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S) +#define GPIO_FUNC26_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC26_IN_INV_SEL_S 6 + +/* GPIO_FUNC26_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC26_IN_SEL 0x0000003F +#define GPIO_FUNC26_IN_SEL_M (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S) +#define GPIO_FUNC26_IN_SEL_V 0x0000003F +#define GPIO_FUNC26_IN_SEL_S 0 + +/* GPIO_FUNC27_IN_SEL_CFG_REG register + * Peripheral function 27 input selection register + */ + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0) + +/* GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) +#define GPIO_SIG27_IN_SEL_V 0x00000001 +#define GPIO_SIG27_IN_SEL_S 7 + +/* GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) +#define GPIO_FUNC27_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC27_IN_INV_SEL_S 6 + +/* GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC27_IN_SEL 0x0000003F +#define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) +#define GPIO_FUNC27_IN_SEL_V 0x0000003F +#define GPIO_FUNC27_IN_SEL_S 0 + +/* GPIO_FUNC28_IN_SEL_CFG_REG register + * Peripheral function 28 input selection register + */ + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) + +/* GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001 +#define GPIO_SIG28_IN_SEL_S 7 + +/* GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC28_IN_INV_SEL_S 6 + +/* GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC28_IN_SEL 0x0000003F +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000003F +#define GPIO_FUNC28_IN_SEL_S 0 + +/* GPIO_FUNC29_IN_SEL_CFG_REG register + * Peripheral function 29 input selection register + */ + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) + +/* GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001 +#define GPIO_SIG29_IN_SEL_S 7 + +/* GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC29_IN_INV_SEL_S 6 + +/* GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC29_IN_SEL 0x0000003F +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000003F +#define GPIO_FUNC29_IN_SEL_S 0 + +/* GPIO_FUNC30_IN_SEL_CFG_REG register + * Peripheral function 30 input selection register + */ + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) + +/* GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001 +#define GPIO_SIG30_IN_SEL_S 7 + +/* GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC30_IN_INV_SEL_S 6 + +/* GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC30_IN_SEL 0x0000003F +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000003F +#define GPIO_FUNC30_IN_SEL_S 0 + +/* GPIO_FUNC31_IN_SEL_CFG_REG register + * Peripheral function 31 input selection register + */ + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) + +/* GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001 +#define GPIO_SIG31_IN_SEL_S 7 + +/* GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC31_IN_INV_SEL_S 6 + +/* GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC31_IN_SEL 0x0000003F +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000003F +#define GPIO_FUNC31_IN_SEL_S 0 + +/* GPIO_FUNC32_IN_SEL_CFG_REG register + * Peripheral function 32 input selection register + */ + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) + +/* GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001 +#define GPIO_SIG32_IN_SEL_S 7 + +/* GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC32_IN_INV_SEL_S 6 + +/* GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC32_IN_SEL 0x0000003F +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000003F +#define GPIO_FUNC32_IN_SEL_S 0 + +/* GPIO_FUNC33_IN_SEL_CFG_REG register + * Peripheral function 33 input selection register + */ + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) + +/* GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001 +#define GPIO_SIG33_IN_SEL_S 7 + +/* GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC33_IN_INV_SEL_S 6 + +/* GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC33_IN_SEL 0x0000003F +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000003F +#define GPIO_FUNC33_IN_SEL_S 0 + +/* GPIO_FUNC34_IN_SEL_CFG_REG register + * Peripheral function 34 input selection register + */ + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) + +/* GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001 +#define GPIO_SIG34_IN_SEL_S 7 + +/* GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC34_IN_INV_SEL_S 6 + +/* GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC34_IN_SEL 0x0000003F +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000003F +#define GPIO_FUNC34_IN_SEL_S 0 + +/* GPIO_FUNC35_IN_SEL_CFG_REG register + * Peripheral function 35 input selection register + */ + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) + +/* GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001 +#define GPIO_SIG35_IN_SEL_S 7 + +/* GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC35_IN_INV_SEL_S 6 + +/* GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC35_IN_SEL 0x0000003F +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000003F +#define GPIO_FUNC35_IN_SEL_S 0 + +/* GPIO_FUNC36_IN_SEL_CFG_REG register + * Peripheral function 36 input selection register + */ + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4) + +/* GPIO_SIG36_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL_M (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S) +#define GPIO_SIG36_IN_SEL_V 0x00000001 +#define GPIO_SIG36_IN_SEL_S 7 + +/* GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_M (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S) +#define GPIO_FUNC36_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC36_IN_INV_SEL_S 6 + +/* GPIO_FUNC36_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC36_IN_SEL 0x0000003F +#define GPIO_FUNC36_IN_SEL_M (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S) +#define GPIO_FUNC36_IN_SEL_V 0x0000003F +#define GPIO_FUNC36_IN_SEL_S 0 + +/* GPIO_FUNC37_IN_SEL_CFG_REG register + * Peripheral function 37 input selection register + */ + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8) + +/* GPIO_SIG37_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL_M (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S) +#define GPIO_SIG37_IN_SEL_V 0x00000001 +#define GPIO_SIG37_IN_SEL_S 7 + +/* GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_M (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S) +#define GPIO_FUNC37_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC37_IN_INV_SEL_S 6 + +/* GPIO_FUNC37_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC37_IN_SEL 0x0000003F +#define GPIO_FUNC37_IN_SEL_M (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S) +#define GPIO_FUNC37_IN_SEL_V 0x0000003F +#define GPIO_FUNC37_IN_SEL_S 0 + +/* GPIO_FUNC38_IN_SEL_CFG_REG register + * Peripheral function 38 input selection register + */ + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec) + +/* GPIO_SIG38_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL_M (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S) +#define GPIO_SIG38_IN_SEL_V 0x00000001 +#define GPIO_SIG38_IN_SEL_S 7 + +/* GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_M (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S) +#define GPIO_FUNC38_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC38_IN_INV_SEL_S 6 + +/* GPIO_FUNC38_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC38_IN_SEL 0x0000003F +#define GPIO_FUNC38_IN_SEL_M (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S) +#define GPIO_FUNC38_IN_SEL_V 0x0000003F +#define GPIO_FUNC38_IN_SEL_S 0 + +/* GPIO_FUNC39_IN_SEL_CFG_REG register + * Peripheral function 39 input selection register + */ + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0) + +/* GPIO_SIG39_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL_M (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S) +#define GPIO_SIG39_IN_SEL_V 0x00000001 +#define GPIO_SIG39_IN_SEL_S 7 + +/* GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_M (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S) +#define GPIO_FUNC39_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC39_IN_INV_SEL_S 6 + +/* GPIO_FUNC39_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC39_IN_SEL 0x0000003F +#define GPIO_FUNC39_IN_SEL_M (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S) +#define GPIO_FUNC39_IN_SEL_V 0x0000003F +#define GPIO_FUNC39_IN_SEL_S 0 + +/* GPIO_FUNC40_IN_SEL_CFG_REG register + * Peripheral function 40 input selection register + */ + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) + +/* GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) +#define GPIO_SIG40_IN_SEL_V 0x00000001 +#define GPIO_SIG40_IN_SEL_S 7 + +/* GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) +#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC40_IN_INV_SEL_S 6 + +/* GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC40_IN_SEL 0x0000003F +#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) +#define GPIO_FUNC40_IN_SEL_V 0x0000003F +#define GPIO_FUNC40_IN_SEL_S 0 + +/* GPIO_FUNC41_IN_SEL_CFG_REG register + * Peripheral function 41 input selection register + */ + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) + +/* GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001 +#define GPIO_SIG41_IN_SEL_S 7 + +/* GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC41_IN_INV_SEL_S 6 + +/* GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC41_IN_SEL 0x0000003F +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000003F +#define GPIO_FUNC41_IN_SEL_S 0 + +/* GPIO_FUNC42_IN_SEL_CFG_REG register + * Peripheral function 42 input selection register + */ + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) + +/* GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001 +#define GPIO_SIG42_IN_SEL_S 7 + +/* GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC42_IN_INV_SEL_S 6 + +/* GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC42_IN_SEL 0x0000003F +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000003F +#define GPIO_FUNC42_IN_SEL_S 0 + +/* GPIO_FUNC43_IN_SEL_CFG_REG register + * Peripheral function 43 input selection register + */ + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) + +/* GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) +#define GPIO_SIG43_IN_SEL_V 0x00000001 +#define GPIO_SIG43_IN_SEL_S 7 + +/* GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) +#define GPIO_FUNC43_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC43_IN_INV_SEL_S 6 + +/* GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC43_IN_SEL 0x0000003F +#define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) +#define GPIO_FUNC43_IN_SEL_V 0x0000003F +#define GPIO_FUNC43_IN_SEL_S 0 + +/* GPIO_FUNC44_IN_SEL_CFG_REG register + * Peripheral function 44 input selection register + */ + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) + +/* GPIO_SIG44_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL_M (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S) +#define GPIO_SIG44_IN_SEL_V 0x00000001 +#define GPIO_SIG44_IN_SEL_S 7 + +/* GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_M (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S) +#define GPIO_FUNC44_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC44_IN_INV_SEL_S 6 + +/* GPIO_FUNC44_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC44_IN_SEL 0x0000003F +#define GPIO_FUNC44_IN_SEL_M (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S) +#define GPIO_FUNC44_IN_SEL_V 0x0000003F +#define GPIO_FUNC44_IN_SEL_S 0 + +/* GPIO_FUNC45_IN_SEL_CFG_REG register + * Peripheral function 45 input selection register + */ + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) + +/* GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) +#define GPIO_SIG45_IN_SEL_V 0x00000001 +#define GPIO_SIG45_IN_SEL_S 7 + +/* GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) +#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC45_IN_INV_SEL_S 6 + +/* GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC45_IN_SEL 0x0000003F +#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) +#define GPIO_FUNC45_IN_SEL_V 0x0000003F +#define GPIO_FUNC45_IN_SEL_S 0 + +/* GPIO_FUNC46_IN_SEL_CFG_REG register + * Peripheral function 46 input selection register + */ + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) + +/* GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001 +#define GPIO_SIG46_IN_SEL_S 7 + +/* GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC46_IN_INV_SEL_S 6 + +/* GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC46_IN_SEL 0x0000003F +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000003F +#define GPIO_FUNC46_IN_SEL_S 0 + +/* GPIO_FUNC47_IN_SEL_CFG_REG register + * Peripheral function 47 input selection register + */ + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) + +/* GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001 +#define GPIO_SIG47_IN_SEL_S 7 + +/* GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC47_IN_INV_SEL_S 6 + +/* GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC47_IN_SEL 0x0000003F +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000003F +#define GPIO_FUNC47_IN_SEL_S 0 + +/* GPIO_FUNC48_IN_SEL_CFG_REG register + * Peripheral function 48 input selection register + */ + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) + +/* GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) +#define GPIO_SIG48_IN_SEL_V 0x00000001 +#define GPIO_SIG48_IN_SEL_S 7 + +/* GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) +#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC48_IN_INV_SEL_S 6 + +/* GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC48_IN_SEL 0x0000003F +#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) +#define GPIO_FUNC48_IN_SEL_V 0x0000003F +#define GPIO_FUNC48_IN_SEL_S 0 + +/* GPIO_FUNC49_IN_SEL_CFG_REG register + * Peripheral function 49 input selection register + */ + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) + +/* GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) +#define GPIO_SIG49_IN_SEL_V 0x00000001 +#define GPIO_SIG49_IN_SEL_S 7 + +/* GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) +#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC49_IN_INV_SEL_S 6 + +/* GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC49_IN_SEL 0x0000003F +#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) +#define GPIO_FUNC49_IN_SEL_V 0x0000003F +#define GPIO_FUNC49_IN_SEL_S 0 + +/* GPIO_FUNC50_IN_SEL_CFG_REG register + * Peripheral function 50 input selection register + */ + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) + +/* GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) +#define GPIO_SIG50_IN_SEL_V 0x00000001 +#define GPIO_SIG50_IN_SEL_S 7 + +/* GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) +#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC50_IN_INV_SEL_S 6 + +/* GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC50_IN_SEL 0x0000003F +#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) +#define GPIO_FUNC50_IN_SEL_V 0x0000003F +#define GPIO_FUNC50_IN_SEL_S 0 + +/* GPIO_FUNC51_IN_SEL_CFG_REG register + * Peripheral function 51 input selection register + */ + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) + +/* GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) +#define GPIO_SIG51_IN_SEL_V 0x00000001 +#define GPIO_SIG51_IN_SEL_S 7 + +/* GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) +#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC51_IN_INV_SEL_S 6 + +/* GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC51_IN_SEL 0x0000003F +#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) +#define GPIO_FUNC51_IN_SEL_V 0x0000003F +#define GPIO_FUNC51_IN_SEL_S 0 + +/* GPIO_FUNC52_IN_SEL_CFG_REG register + * Peripheral function 52 input selection register + */ + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) + +/* GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) +#define GPIO_SIG52_IN_SEL_V 0x00000001 +#define GPIO_SIG52_IN_SEL_S 7 + +/* GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) +#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC52_IN_INV_SEL_S 6 + +/* GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC52_IN_SEL 0x0000003F +#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) +#define GPIO_FUNC52_IN_SEL_V 0x0000003F +#define GPIO_FUNC52_IN_SEL_S 0 + +/* GPIO_FUNC53_IN_SEL_CFG_REG register + * Peripheral function 53 input selection register + */ + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) + +/* GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) +#define GPIO_SIG53_IN_SEL_V 0x00000001 +#define GPIO_SIG53_IN_SEL_S 7 + +/* GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) +#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC53_IN_INV_SEL_S 6 + +/* GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC53_IN_SEL 0x0000003F +#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) +#define GPIO_FUNC53_IN_SEL_V 0x0000003F +#define GPIO_FUNC53_IN_SEL_S 0 + +/* GPIO_FUNC54_IN_SEL_CFG_REG register + * Peripheral function 54 input selection register + */ + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) + +/* GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) +#define GPIO_SIG54_IN_SEL_V 0x00000001 +#define GPIO_SIG54_IN_SEL_S 7 + +/* GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) +#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC54_IN_INV_SEL_S 6 + +/* GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC54_IN_SEL 0x0000003F +#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) +#define GPIO_FUNC54_IN_SEL_V 0x0000003F +#define GPIO_FUNC54_IN_SEL_S 0 + +/* GPIO_FUNC55_IN_SEL_CFG_REG register + * Peripheral function 55 input selection register + */ + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) + +/* GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) +#define GPIO_SIG55_IN_SEL_V 0x00000001 +#define GPIO_SIG55_IN_SEL_S 7 + +/* GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) +#define GPIO_FUNC55_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC55_IN_INV_SEL_S 6 + +/* GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC55_IN_SEL 0x0000003F +#define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) +#define GPIO_FUNC55_IN_SEL_V 0x0000003F +#define GPIO_FUNC55_IN_SEL_S 0 + +/* GPIO_FUNC56_IN_SEL_CFG_REG register + * Peripheral function 56 input selection register + */ + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) + +/* GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) +#define GPIO_SIG56_IN_SEL_V 0x00000001 +#define GPIO_SIG56_IN_SEL_S 7 + +/* GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) +#define GPIO_FUNC56_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC56_IN_INV_SEL_S 6 + +/* GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC56_IN_SEL 0x0000003F +#define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) +#define GPIO_FUNC56_IN_SEL_V 0x0000003F +#define GPIO_FUNC56_IN_SEL_S 0 + +/* GPIO_FUNC57_IN_SEL_CFG_REG register + * Peripheral function 57 input selection register + */ + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) + +/* GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) +#define GPIO_SIG57_IN_SEL_V 0x00000001 +#define GPIO_SIG57_IN_SEL_S 7 + +/* GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) +#define GPIO_FUNC57_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC57_IN_INV_SEL_S 6 + +/* GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC57_IN_SEL 0x0000003F +#define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) +#define GPIO_FUNC57_IN_SEL_V 0x0000003F +#define GPIO_FUNC57_IN_SEL_S 0 + +/* GPIO_FUNC58_IN_SEL_CFG_REG register + * Peripheral function 58 input selection register + */ + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) + +/* GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) +#define GPIO_SIG58_IN_SEL_V 0x00000001 +#define GPIO_SIG58_IN_SEL_S 7 + +/* GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) +#define GPIO_FUNC58_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC58_IN_INV_SEL_S 6 + +/* GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC58_IN_SEL 0x0000003F +#define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) +#define GPIO_FUNC58_IN_SEL_V 0x0000003F +#define GPIO_FUNC58_IN_SEL_S 0 + +/* GPIO_FUNC59_IN_SEL_CFG_REG register + * Peripheral function 59 input selection register + */ + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) + +/* GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) +#define GPIO_SIG59_IN_SEL_V 0x00000001 +#define GPIO_SIG59_IN_SEL_S 7 + +/* GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) +#define GPIO_FUNC59_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC59_IN_INV_SEL_S 6 + +/* GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC59_IN_SEL 0x0000003F +#define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) +#define GPIO_FUNC59_IN_SEL_V 0x0000003F +#define GPIO_FUNC59_IN_SEL_S 0 + +/* GPIO_FUNC60_IN_SEL_CFG_REG register + * Peripheral function 60 input selection register + */ + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) + +/* GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) +#define GPIO_SIG60_IN_SEL_V 0x00000001 +#define GPIO_SIG60_IN_SEL_S 7 + +/* GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) +#define GPIO_FUNC60_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC60_IN_INV_SEL_S 6 + +/* GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC60_IN_SEL 0x0000003F +#define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) +#define GPIO_FUNC60_IN_SEL_V 0x0000003F +#define GPIO_FUNC60_IN_SEL_S 0 + +/* GPIO_FUNC61_IN_SEL_CFG_REG register + * Peripheral function 61 input selection register + */ + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) + +/* GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) +#define GPIO_SIG61_IN_SEL_V 0x00000001 +#define GPIO_SIG61_IN_SEL_S 7 + +/* GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) +#define GPIO_FUNC61_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC61_IN_INV_SEL_S 6 + +/* GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC61_IN_SEL 0x0000003F +#define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) +#define GPIO_FUNC61_IN_SEL_V 0x0000003F +#define GPIO_FUNC61_IN_SEL_S 0 + +/* GPIO_FUNC62_IN_SEL_CFG_REG register + * Peripheral function 62 input selection register + */ + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) + +/* GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) +#define GPIO_SIG62_IN_SEL_V 0x00000001 +#define GPIO_SIG62_IN_SEL_S 7 + +/* GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) +#define GPIO_FUNC62_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC62_IN_INV_SEL_S 6 + +/* GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC62_IN_SEL 0x0000003F +#define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) +#define GPIO_FUNC62_IN_SEL_V 0x0000003F +#define GPIO_FUNC62_IN_SEL_S 0 + +/* GPIO_FUNC63_IN_SEL_CFG_REG register + * Peripheral function 63 input selection register + */ + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) + +/* GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) +#define GPIO_SIG63_IN_SEL_V 0x00000001 +#define GPIO_SIG63_IN_SEL_S 7 + +/* GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) +#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC63_IN_INV_SEL_S 6 + +/* GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC63_IN_SEL 0x0000003F +#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) +#define GPIO_FUNC63_IN_SEL_V 0x0000003F +#define GPIO_FUNC63_IN_SEL_S 0 + +/* GPIO_FUNC64_IN_SEL_CFG_REG register + * Peripheral function 64 input selection register + */ + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) + +/* GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001 +#define GPIO_SIG64_IN_SEL_S 7 + +/* GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC64_IN_INV_SEL_S 6 + +/* GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC64_IN_SEL 0x0000003F +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000003F +#define GPIO_FUNC64_IN_SEL_S 0 + +/* GPIO_FUNC65_IN_SEL_CFG_REG register + * Peripheral function 65 input selection register + */ + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) + +/* GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001 +#define GPIO_SIG65_IN_SEL_S 7 + +/* GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC65_IN_INV_SEL_S 6 + +/* GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC65_IN_SEL 0x0000003F +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000003F +#define GPIO_FUNC65_IN_SEL_S 0 + +/* GPIO_FUNC66_IN_SEL_CFG_REG register + * Peripheral function 66 input selection register + */ + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) + +/* GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001 +#define GPIO_SIG66_IN_SEL_S 7 + +/* GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC66_IN_INV_SEL_S 6 + +/* GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC66_IN_SEL 0x0000003F +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000003F +#define GPIO_FUNC66_IN_SEL_S 0 + +/* GPIO_FUNC67_IN_SEL_CFG_REG register + * Peripheral function 67 input selection register + */ + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) + +/* GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001 +#define GPIO_SIG67_IN_SEL_S 7 + +/* GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC67_IN_INV_SEL_S 6 + +/* GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC67_IN_SEL 0x0000003F +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000003F +#define GPIO_FUNC67_IN_SEL_S 0 + +/* GPIO_FUNC68_IN_SEL_CFG_REG register + * Peripheral function 68 input selection register + */ + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) + +/* GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001 +#define GPIO_SIG68_IN_SEL_S 7 + +/* GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC68_IN_INV_SEL_S 6 + +/* GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC68_IN_SEL 0x0000003F +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000003F +#define GPIO_FUNC68_IN_SEL_S 0 + +/* GPIO_FUNC69_IN_SEL_CFG_REG register + * Peripheral function 69 input selection register + */ + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) + +/* GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001 +#define GPIO_SIG69_IN_SEL_S 7 + +/* GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC69_IN_INV_SEL_S 6 + +/* GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC69_IN_SEL 0x0000003F +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000003F +#define GPIO_FUNC69_IN_SEL_S 0 + +/* GPIO_FUNC70_IN_SEL_CFG_REG register + * Peripheral function 70 input selection register + */ + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) + +/* GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) +#define GPIO_SIG70_IN_SEL_V 0x00000001 +#define GPIO_SIG70_IN_SEL_S 7 + +/* GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) +#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC70_IN_INV_SEL_S 6 + +/* GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC70_IN_SEL 0x0000003F +#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) +#define GPIO_FUNC70_IN_SEL_V 0x0000003F +#define GPIO_FUNC70_IN_SEL_S 0 + +/* GPIO_FUNC71_IN_SEL_CFG_REG register + * Peripheral function 71 input selection register + */ + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) + +/* GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) +#define GPIO_SIG71_IN_SEL_V 0x00000001 +#define GPIO_SIG71_IN_SEL_S 7 + +/* GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) +#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC71_IN_INV_SEL_S 6 + +/* GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC71_IN_SEL 0x0000003F +#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) +#define GPIO_FUNC71_IN_SEL_V 0x0000003F +#define GPIO_FUNC71_IN_SEL_S 0 + +/* GPIO_FUNC72_IN_SEL_CFG_REG register + * Peripheral function 72 input selection register + */ + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) + +/* GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001 +#define GPIO_SIG72_IN_SEL_S 7 + +/* GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC72_IN_INV_SEL_S 6 + +/* GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC72_IN_SEL 0x0000003F +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000003F +#define GPIO_FUNC72_IN_SEL_S 0 + +/* GPIO_FUNC73_IN_SEL_CFG_REG register + * Peripheral function 73 input selection register + */ + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) + +/* GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001 +#define GPIO_SIG73_IN_SEL_S 7 + +/* GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC73_IN_INV_SEL_S 6 + +/* GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC73_IN_SEL 0x0000003F +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000003F +#define GPIO_FUNC73_IN_SEL_S 0 + +/* GPIO_FUNC74_IN_SEL_CFG_REG register + * Peripheral function 74 input selection register + */ + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c) + +/* GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) +#define GPIO_SIG74_IN_SEL_V 0x00000001 +#define GPIO_SIG74_IN_SEL_S 7 + +/* GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) +#define GPIO_FUNC74_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC74_IN_INV_SEL_S 6 + +/* GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC74_IN_SEL 0x0000003F +#define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) +#define GPIO_FUNC74_IN_SEL_V 0x0000003F +#define GPIO_FUNC74_IN_SEL_S 0 + +/* GPIO_FUNC75_IN_SEL_CFG_REG register + * Peripheral function 75 input selection register + */ + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) + +/* GPIO_SIG75_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL_M (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S) +#define GPIO_SIG75_IN_SEL_V 0x00000001 +#define GPIO_SIG75_IN_SEL_S 7 + +/* GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_M (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S) +#define GPIO_FUNC75_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC75_IN_INV_SEL_S 6 + +/* GPIO_FUNC75_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC75_IN_SEL 0x0000003F +#define GPIO_FUNC75_IN_SEL_M (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S) +#define GPIO_FUNC75_IN_SEL_V 0x0000003F +#define GPIO_FUNC75_IN_SEL_S 0 + +/* GPIO_FUNC76_IN_SEL_CFG_REG register + * Peripheral function 76 input selection register + */ + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) + +/* GPIO_SIG76_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL_M (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S) +#define GPIO_SIG76_IN_SEL_V 0x00000001 +#define GPIO_SIG76_IN_SEL_S 7 + +/* GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_M (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S) +#define GPIO_FUNC76_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC76_IN_INV_SEL_S 6 + +/* GPIO_FUNC76_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC76_IN_SEL 0x0000003F +#define GPIO_FUNC76_IN_SEL_M (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S) +#define GPIO_FUNC76_IN_SEL_V 0x0000003F +#define GPIO_FUNC76_IN_SEL_S 0 + +/* GPIO_FUNC77_IN_SEL_CFG_REG register + * Peripheral function 77 input selection register + */ + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) + +/* GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) +#define GPIO_SIG77_IN_SEL_V 0x00000001 +#define GPIO_SIG77_IN_SEL_S 7 + +/* GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) +#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC77_IN_INV_SEL_S 6 + +/* GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC77_IN_SEL 0x0000003F +#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) +#define GPIO_FUNC77_IN_SEL_V 0x0000003F +#define GPIO_FUNC77_IN_SEL_S 0 + +/* GPIO_FUNC78_IN_SEL_CFG_REG register + * Peripheral function 78 input selection register + */ + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c) + +/* GPIO_SIG78_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL_M (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S) +#define GPIO_SIG78_IN_SEL_V 0x00000001 +#define GPIO_SIG78_IN_SEL_S 7 + +/* GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_M (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S) +#define GPIO_FUNC78_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC78_IN_INV_SEL_S 6 + +/* GPIO_FUNC78_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC78_IN_SEL 0x0000003F +#define GPIO_FUNC78_IN_SEL_M (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S) +#define GPIO_FUNC78_IN_SEL_V 0x0000003F +#define GPIO_FUNC78_IN_SEL_S 0 + +/* GPIO_FUNC79_IN_SEL_CFG_REG register + * Peripheral function 79 input selection register + */ + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) + +/* GPIO_SIG79_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL_M (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S) +#define GPIO_SIG79_IN_SEL_V 0x00000001 +#define GPIO_SIG79_IN_SEL_S 7 + +/* GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_M (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S) +#define GPIO_FUNC79_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC79_IN_INV_SEL_S 6 + +/* GPIO_FUNC79_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC79_IN_SEL 0x0000003F +#define GPIO_FUNC79_IN_SEL_M (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S) +#define GPIO_FUNC79_IN_SEL_V 0x0000003F +#define GPIO_FUNC79_IN_SEL_S 0 + +/* GPIO_FUNC80_IN_SEL_CFG_REG register + * Peripheral function 80 input selection register + */ + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) + +/* GPIO_SIG80_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL_M (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S) +#define GPIO_SIG80_IN_SEL_V 0x00000001 +#define GPIO_SIG80_IN_SEL_S 7 + +/* GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_M (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S) +#define GPIO_FUNC80_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC80_IN_INV_SEL_S 6 + +/* GPIO_FUNC80_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC80_IN_SEL 0x0000003F +#define GPIO_FUNC80_IN_SEL_M (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S) +#define GPIO_FUNC80_IN_SEL_V 0x0000003F +#define GPIO_FUNC80_IN_SEL_S 0 + +/* GPIO_FUNC81_IN_SEL_CFG_REG register + * Peripheral function 81 input selection register + */ + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) + +/* GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) +#define GPIO_SIG81_IN_SEL_V 0x00000001 +#define GPIO_SIG81_IN_SEL_S 7 + +/* GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) +#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC81_IN_INV_SEL_S 6 + +/* GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC81_IN_SEL 0x0000003F +#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) +#define GPIO_FUNC81_IN_SEL_V 0x0000003F +#define GPIO_FUNC81_IN_SEL_S 0 + +/* GPIO_FUNC82_IN_SEL_CFG_REG register + * Peripheral function 82 input selection register + */ + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) + +/* GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001 +#define GPIO_SIG82_IN_SEL_S 7 + +/* GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC82_IN_INV_SEL_S 6 + +/* GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC82_IN_SEL 0x0000003F +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000003F +#define GPIO_FUNC82_IN_SEL_S 0 + +/* GPIO_FUNC83_IN_SEL_CFG_REG register + * Peripheral function 83 input selection register + */ + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) + +/* GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) +#define GPIO_SIG83_IN_SEL_V 0x00000001 +#define GPIO_SIG83_IN_SEL_S 7 + +/* GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) +#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC83_IN_INV_SEL_S 6 + +/* GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC83_IN_SEL 0x0000003F +#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) +#define GPIO_FUNC83_IN_SEL_V 0x0000003F +#define GPIO_FUNC83_IN_SEL_S 0 + +/* GPIO_FUNC84_IN_SEL_CFG_REG register + * Peripheral function 84 input selection register + */ + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) + +/* GPIO_SIG84_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) +#define GPIO_SIG84_IN_SEL_V 0x00000001 +#define GPIO_SIG84_IN_SEL_S 7 + +/* GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) +#define GPIO_FUNC84_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC84_IN_INV_SEL_S 6 + +/* GPIO_FUNC84_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC84_IN_SEL 0x0000003F +#define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) +#define GPIO_FUNC84_IN_SEL_V 0x0000003F +#define GPIO_FUNC84_IN_SEL_S 0 + +/* GPIO_FUNC85_IN_SEL_CFG_REG register + * Peripheral function 85 input selection register + */ + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) + +/* GPIO_SIG85_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) +#define GPIO_SIG85_IN_SEL_V 0x00000001 +#define GPIO_SIG85_IN_SEL_S 7 + +/* GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) +#define GPIO_FUNC85_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC85_IN_INV_SEL_S 6 + +/* GPIO_FUNC85_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC85_IN_SEL 0x0000003F +#define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) +#define GPIO_FUNC85_IN_SEL_V 0x0000003F +#define GPIO_FUNC85_IN_SEL_S 0 + +/* GPIO_FUNC86_IN_SEL_CFG_REG register + * Peripheral function 86 input selection register + */ + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) + +/* GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) +#define GPIO_SIG86_IN_SEL_V 0x00000001 +#define GPIO_SIG86_IN_SEL_S 7 + +/* GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) +#define GPIO_FUNC86_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC86_IN_INV_SEL_S 6 + +/* GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC86_IN_SEL 0x0000003F +#define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) +#define GPIO_FUNC86_IN_SEL_V 0x0000003F +#define GPIO_FUNC86_IN_SEL_S 0 + +/* GPIO_FUNC87_IN_SEL_CFG_REG register + * Peripheral function 87 input selection register + */ + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) + +/* GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) +#define GPIO_SIG87_IN_SEL_V 0x00000001 +#define GPIO_SIG87_IN_SEL_S 7 + +/* GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) +#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC87_IN_INV_SEL_S 6 + +/* GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC87_IN_SEL 0x0000003F +#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) +#define GPIO_FUNC87_IN_SEL_V 0x0000003F +#define GPIO_FUNC87_IN_SEL_S 0 + +/* GPIO_FUNC88_IN_SEL_CFG_REG register + * Peripheral function 88 input selection register + */ + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) + +/* GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) +#define GPIO_SIG88_IN_SEL_V 0x00000001 +#define GPIO_SIG88_IN_SEL_S 7 + +/* GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) +#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC88_IN_INV_SEL_S 6 + +/* GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC88_IN_SEL 0x0000003F +#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) +#define GPIO_FUNC88_IN_SEL_V 0x0000003F +#define GPIO_FUNC88_IN_SEL_S 0 + +/* GPIO_FUNC89_IN_SEL_CFG_REG register + * Peripheral function 89 input selection register + */ + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) + +/* GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) +#define GPIO_SIG89_IN_SEL_V 0x00000001 +#define GPIO_SIG89_IN_SEL_S 7 + +/* GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) +#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC89_IN_INV_SEL_S 6 + +/* GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC89_IN_SEL 0x0000003F +#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) +#define GPIO_FUNC89_IN_SEL_V 0x0000003F +#define GPIO_FUNC89_IN_SEL_S 0 + +/* GPIO_FUNC90_IN_SEL_CFG_REG register + * Peripheral function 90 input selection register + */ + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) + +/* GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) +#define GPIO_SIG90_IN_SEL_V 0x00000001 +#define GPIO_SIG90_IN_SEL_S 7 + +/* GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) +#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC90_IN_INV_SEL_S 6 + +/* GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC90_IN_SEL 0x0000003F +#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) +#define GPIO_FUNC90_IN_SEL_V 0x0000003F +#define GPIO_FUNC90_IN_SEL_S 0 + +/* GPIO_FUNC91_IN_SEL_CFG_REG register + * Peripheral function 91 input selection register + */ + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) + +/* GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) +#define GPIO_SIG91_IN_SEL_V 0x00000001 +#define GPIO_SIG91_IN_SEL_S 7 + +/* GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) +#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC91_IN_INV_SEL_S 6 + +/* GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC91_IN_SEL 0x0000003F +#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) +#define GPIO_FUNC91_IN_SEL_V 0x0000003F +#define GPIO_FUNC91_IN_SEL_S 0 + +/* GPIO_FUNC92_IN_SEL_CFG_REG register + * Peripheral function 92 input selection register + */ + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) + +/* GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) +#define GPIO_SIG92_IN_SEL_V 0x00000001 +#define GPIO_SIG92_IN_SEL_S 7 + +/* GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) +#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC92_IN_INV_SEL_S 6 + +/* GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC92_IN_SEL 0x0000003F +#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) +#define GPIO_FUNC92_IN_SEL_V 0x0000003F +#define GPIO_FUNC92_IN_SEL_S 0 + +/* GPIO_FUNC93_IN_SEL_CFG_REG register + * Peripheral function 93 input selection register + */ + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) + +/* GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) +#define GPIO_SIG93_IN_SEL_V 0x00000001 +#define GPIO_SIG93_IN_SEL_S 7 + +/* GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) +#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC93_IN_INV_SEL_S 6 + +/* GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC93_IN_SEL 0x0000003F +#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) +#define GPIO_FUNC93_IN_SEL_V 0x0000003F +#define GPIO_FUNC93_IN_SEL_S 0 + +/* GPIO_FUNC94_IN_SEL_CFG_REG register + * Peripheral function 94 input selection register + */ + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) + +/* GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) +#define GPIO_SIG94_IN_SEL_V 0x00000001 +#define GPIO_SIG94_IN_SEL_S 7 + +/* GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) +#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC94_IN_INV_SEL_S 6 + +/* GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC94_IN_SEL 0x0000003F +#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) +#define GPIO_FUNC94_IN_SEL_V 0x0000003F +#define GPIO_FUNC94_IN_SEL_S 0 + +/* GPIO_FUNC95_IN_SEL_CFG_REG register + * Peripheral function 95 input selection register + */ + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) + +/* GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) +#define GPIO_SIG95_IN_SEL_V 0x00000001 +#define GPIO_SIG95_IN_SEL_S 7 + +/* GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) +#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC95_IN_INV_SEL_S 6 + +/* GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC95_IN_SEL 0x0000003F +#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) +#define GPIO_FUNC95_IN_SEL_V 0x0000003F +#define GPIO_FUNC95_IN_SEL_S 0 + +/* GPIO_FUNC96_IN_SEL_CFG_REG register + * Peripheral function 96 input selection register + */ + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) + +/* GPIO_SIG96_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL_M (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S) +#define GPIO_SIG96_IN_SEL_V 0x00000001 +#define GPIO_SIG96_IN_SEL_S 7 + +/* GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_M (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S) +#define GPIO_FUNC96_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC96_IN_INV_SEL_S 6 + +/* GPIO_FUNC96_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC96_IN_SEL 0x0000003F +#define GPIO_FUNC96_IN_SEL_M (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S) +#define GPIO_FUNC96_IN_SEL_V 0x0000003F +#define GPIO_FUNC96_IN_SEL_S 0 + +/* GPIO_FUNC97_IN_SEL_CFG_REG register + * Peripheral function 97 input selection register + */ + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) + +/* GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001 +#define GPIO_SIG97_IN_SEL_S 7 + +/* GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC97_IN_INV_SEL_S 6 + +/* GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC97_IN_SEL 0x0000003F +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000003F +#define GPIO_FUNC97_IN_SEL_S 0 + +/* GPIO_FUNC98_IN_SEL_CFG_REG register + * Peripheral function 98 input selection register + */ + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) + +/* GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001 +#define GPIO_SIG98_IN_SEL_S 7 + +/* GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC98_IN_INV_SEL_S 6 + +/* GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC98_IN_SEL 0x0000003F +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000003F +#define GPIO_FUNC98_IN_SEL_S 0 + +/* GPIO_FUNC99_IN_SEL_CFG_REG register + * Peripheral function 99 input selection register + */ + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) + +/* GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001 +#define GPIO_SIG99_IN_SEL_S 7 + +/* GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC99_IN_INV_SEL_S 6 + +/* GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC99_IN_SEL 0x0000003F +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000003F +#define GPIO_FUNC99_IN_SEL_S 0 + +/* GPIO_FUNC100_IN_SEL_CFG_REG register + * Peripheral function 100 input selection register + */ + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) + +/* GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001 +#define GPIO_SIG100_IN_SEL_S 7 + +/* GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC100_IN_INV_SEL_S 6 + +/* GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC100_IN_SEL 0x0000003F +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000003F +#define GPIO_FUNC100_IN_SEL_S 0 + +/* GPIO_FUNC101_IN_SEL_CFG_REG register + * Peripheral function 101 input selection register + */ + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) + +/* GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) +#define GPIO_SIG101_IN_SEL_V 0x00000001 +#define GPIO_SIG101_IN_SEL_S 7 + +/* GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) +#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC101_IN_INV_SEL_S 6 + +/* GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC101_IN_SEL 0x0000003F +#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) +#define GPIO_FUNC101_IN_SEL_V 0x0000003F +#define GPIO_FUNC101_IN_SEL_S 0 + +/* GPIO_FUNC102_IN_SEL_CFG_REG register + * Peripheral function 102 input selection register + */ + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) + +/* GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) +#define GPIO_SIG102_IN_SEL_V 0x00000001 +#define GPIO_SIG102_IN_SEL_S 7 + +/* GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) +#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC102_IN_INV_SEL_S 6 + +/* GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC102_IN_SEL 0x0000003F +#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) +#define GPIO_FUNC102_IN_SEL_V 0x0000003F +#define GPIO_FUNC102_IN_SEL_S 0 + +/* GPIO_FUNC103_IN_SEL_CFG_REG register + * Peripheral function 103 input selection register + */ + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) + +/* GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) +#define GPIO_SIG103_IN_SEL_V 0x00000001 +#define GPIO_SIG103_IN_SEL_S 7 + +/* GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) +#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC103_IN_INV_SEL_S 6 + +/* GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC103_IN_SEL 0x0000003F +#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) +#define GPIO_FUNC103_IN_SEL_V 0x0000003F +#define GPIO_FUNC103_IN_SEL_S 0 + +/* GPIO_FUNC104_IN_SEL_CFG_REG register + * Peripheral function 104 input selection register + */ + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) + +/* GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) +#define GPIO_SIG104_IN_SEL_V 0x00000001 +#define GPIO_SIG104_IN_SEL_S 7 + +/* GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) +#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC104_IN_INV_SEL_S 6 + +/* GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC104_IN_SEL 0x0000003F +#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) +#define GPIO_FUNC104_IN_SEL_V 0x0000003F +#define GPIO_FUNC104_IN_SEL_S 0 + +/* GPIO_FUNC105_IN_SEL_CFG_REG register + * Peripheral function 105 input selection register + */ + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) + +/* GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) +#define GPIO_SIG105_IN_SEL_V 0x00000001 +#define GPIO_SIG105_IN_SEL_S 7 + +/* GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) +#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC105_IN_INV_SEL_S 6 + +/* GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC105_IN_SEL 0x0000003F +#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) +#define GPIO_FUNC105_IN_SEL_V 0x0000003F +#define GPIO_FUNC105_IN_SEL_S 0 + +/* GPIO_FUNC106_IN_SEL_CFG_REG register + * Peripheral function 106 input selection register + */ + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) + +/* GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) +#define GPIO_SIG106_IN_SEL_V 0x00000001 +#define GPIO_SIG106_IN_SEL_S 7 + +/* GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) +#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC106_IN_INV_SEL_S 6 + +/* GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC106_IN_SEL 0x0000003F +#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) +#define GPIO_FUNC106_IN_SEL_V 0x0000003F +#define GPIO_FUNC106_IN_SEL_S 0 + +/* GPIO_FUNC107_IN_SEL_CFG_REG register + * Peripheral function 107 input selection register + */ + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) + +/* GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) +#define GPIO_SIG107_IN_SEL_V 0x00000001 +#define GPIO_SIG107_IN_SEL_S 7 + +/* GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) +#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC107_IN_INV_SEL_S 6 + +/* GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC107_IN_SEL 0x0000003F +#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) +#define GPIO_FUNC107_IN_SEL_V 0x0000003F +#define GPIO_FUNC107_IN_SEL_S 0 + +/* GPIO_FUNC108_IN_SEL_CFG_REG register + * Peripheral function 108 input selection register + */ + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) + +/* GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) +#define GPIO_SIG108_IN_SEL_V 0x00000001 +#define GPIO_SIG108_IN_SEL_S 7 + +/* GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) +#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC108_IN_INV_SEL_S 6 + +/* GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC108_IN_SEL 0x0000003F +#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) +#define GPIO_FUNC108_IN_SEL_V 0x0000003F +#define GPIO_FUNC108_IN_SEL_S 0 + +/* GPIO_FUNC109_IN_SEL_CFG_REG register + * Peripheral function 109 input selection register + */ + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) + +/* GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) +#define GPIO_SIG109_IN_SEL_V 0x00000001 +#define GPIO_SIG109_IN_SEL_S 7 + +/* GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) +#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC109_IN_INV_SEL_S 6 + +/* GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC109_IN_SEL 0x0000003F +#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) +#define GPIO_FUNC109_IN_SEL_V 0x0000003F +#define GPIO_FUNC109_IN_SEL_S 0 + +/* GPIO_FUNC110_IN_SEL_CFG_REG register + * Peripheral function 110 input selection register + */ + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) + +/* GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) +#define GPIO_SIG110_IN_SEL_V 0x00000001 +#define GPIO_SIG110_IN_SEL_S 7 + +/* GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) +#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC110_IN_INV_SEL_S 6 + +/* GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC110_IN_SEL 0x0000003F +#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) +#define GPIO_FUNC110_IN_SEL_V 0x0000003F +#define GPIO_FUNC110_IN_SEL_S 0 + +/* GPIO_FUNC111_IN_SEL_CFG_REG register + * Peripheral function 111 input selection register + */ + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) + +/* GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) +#define GPIO_SIG111_IN_SEL_V 0x00000001 +#define GPIO_SIG111_IN_SEL_S 7 + +/* GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) +#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC111_IN_INV_SEL_S 6 + +/* GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC111_IN_SEL 0x0000003F +#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) +#define GPIO_FUNC111_IN_SEL_V 0x0000003F +#define GPIO_FUNC111_IN_SEL_S 0 + +/* GPIO_FUNC112_IN_SEL_CFG_REG register + * Peripheral function 112 input selection register + */ + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) + +/* GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) +#define GPIO_SIG112_IN_SEL_V 0x00000001 +#define GPIO_SIG112_IN_SEL_S 7 + +/* GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) +#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC112_IN_INV_SEL_S 6 + +/* GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC112_IN_SEL 0x0000003F +#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) +#define GPIO_FUNC112_IN_SEL_V 0x0000003F +#define GPIO_FUNC112_IN_SEL_S 0 + +/* GPIO_FUNC113_IN_SEL_CFG_REG register + * Peripheral function 113 input selection register + */ + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) + +/* GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) +#define GPIO_SIG113_IN_SEL_V 0x00000001 +#define GPIO_SIG113_IN_SEL_S 7 + +/* GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) +#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC113_IN_INV_SEL_S 6 + +/* GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC113_IN_SEL 0x0000003F +#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) +#define GPIO_FUNC113_IN_SEL_V 0x0000003F +#define GPIO_FUNC113_IN_SEL_S 0 + +/* GPIO_FUNC114_IN_SEL_CFG_REG register + * Peripheral function 114 input selection register + */ + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) + +/* GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) +#define GPIO_SIG114_IN_SEL_V 0x00000001 +#define GPIO_SIG114_IN_SEL_S 7 + +/* GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) +#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC114_IN_INV_SEL_S 6 + +/* GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC114_IN_SEL 0x0000003F +#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) +#define GPIO_FUNC114_IN_SEL_V 0x0000003F +#define GPIO_FUNC114_IN_SEL_S 0 + +/* GPIO_FUNC115_IN_SEL_CFG_REG register + * Peripheral function 115 input selection register + */ + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) + +/* GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) +#define GPIO_SIG115_IN_SEL_V 0x00000001 +#define GPIO_SIG115_IN_SEL_S 7 + +/* GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) +#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC115_IN_INV_SEL_S 6 + +/* GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC115_IN_SEL 0x0000003F +#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) +#define GPIO_FUNC115_IN_SEL_V 0x0000003F +#define GPIO_FUNC115_IN_SEL_S 0 + +/* GPIO_FUNC116_IN_SEL_CFG_REG register + * Peripheral function 116 input selection register + */ + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) + +/* GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) +#define GPIO_SIG116_IN_SEL_V 0x00000001 +#define GPIO_SIG116_IN_SEL_S 7 + +/* GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) +#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC116_IN_INV_SEL_S 6 + +/* GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC116_IN_SEL 0x0000003F +#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) +#define GPIO_FUNC116_IN_SEL_V 0x0000003F +#define GPIO_FUNC116_IN_SEL_S 0 + +/* GPIO_FUNC117_IN_SEL_CFG_REG register + * Peripheral function 117 input selection register + */ + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) + +/* GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) +#define GPIO_SIG117_IN_SEL_V 0x00000001 +#define GPIO_SIG117_IN_SEL_S 7 + +/* GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) +#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC117_IN_INV_SEL_S 6 + +/* GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC117_IN_SEL 0x0000003F +#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) +#define GPIO_FUNC117_IN_SEL_V 0x0000003F +#define GPIO_FUNC117_IN_SEL_S 0 + +/* GPIO_FUNC118_IN_SEL_CFG_REG register + * Peripheral function 118 input selection register + */ + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) + +/* GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001 +#define GPIO_SIG118_IN_SEL_S 7 + +/* GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC118_IN_INV_SEL_S 6 + +/* GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC118_IN_SEL 0x0000003F +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000003F +#define GPIO_FUNC118_IN_SEL_S 0 + +/* GPIO_FUNC119_IN_SEL_CFG_REG register + * Peripheral function 119 input selection register + */ + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) + +/* GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001 +#define GPIO_SIG119_IN_SEL_S 7 + +/* GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC119_IN_INV_SEL_S 6 + +/* GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC119_IN_SEL 0x0000003F +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000003F +#define GPIO_FUNC119_IN_SEL_S 0 + +/* GPIO_FUNC120_IN_SEL_CFG_REG register + * Peripheral function 120 input selection register + */ + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) + +/* GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001 +#define GPIO_SIG120_IN_SEL_S 7 + +/* GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC120_IN_INV_SEL_S 6 + +/* GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC120_IN_SEL 0x0000003F +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000003F +#define GPIO_FUNC120_IN_SEL_S 0 + +/* GPIO_FUNC121_IN_SEL_CFG_REG register + * Peripheral function 121 input selection register + */ + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) + +/* GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001 +#define GPIO_SIG121_IN_SEL_S 7 + +/* GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC121_IN_INV_SEL_S 6 + +/* GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC121_IN_SEL 0x0000003F +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000003F +#define GPIO_FUNC121_IN_SEL_S 0 + +/* GPIO_FUNC122_IN_SEL_CFG_REG register + * Peripheral function 122 input selection register + */ + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) + +/* GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) +#define GPIO_SIG122_IN_SEL_V 0x00000001 +#define GPIO_SIG122_IN_SEL_S 7 + +/* GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) +#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC122_IN_INV_SEL_S 6 + +/* GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC122_IN_SEL 0x0000003F +#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) +#define GPIO_FUNC122_IN_SEL_V 0x0000003F +#define GPIO_FUNC122_IN_SEL_S 0 + +/* GPIO_FUNC123_IN_SEL_CFG_REG register + * Peripheral function 123 input selection register + */ + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) + +/* GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) +#define GPIO_SIG123_IN_SEL_V 0x00000001 +#define GPIO_SIG123_IN_SEL_S 7 + +/* GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) +#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC123_IN_INV_SEL_S 6 + +/* GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC123_IN_SEL 0x0000003F +#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) +#define GPIO_FUNC123_IN_SEL_V 0x0000003F +#define GPIO_FUNC123_IN_SEL_S 0 + +/* GPIO_FUNC124_IN_SEL_CFG_REG register + * Peripheral function 124 input selection register + */ + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) + +/* GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) +#define GPIO_SIG124_IN_SEL_V 0x00000001 +#define GPIO_SIG124_IN_SEL_S 7 + +/* GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) +#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC124_IN_INV_SEL_S 6 + +/* GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC124_IN_SEL 0x0000003F +#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) +#define GPIO_FUNC124_IN_SEL_V 0x0000003F +#define GPIO_FUNC124_IN_SEL_S 0 + +/* GPIO_FUNC125_IN_SEL_CFG_REG register + * Peripheral function 125 input selection register + */ + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) + +/* GPIO_SIG125_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL_M (GPIO_SIG125_IN_SEL_V << GPIO_SIG125_IN_SEL_S) +#define GPIO_SIG125_IN_SEL_V 0x00000001 +#define GPIO_SIG125_IN_SEL_S 7 + +/* GPIO_FUNC125_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_M (GPIO_FUNC125_IN_INV_SEL_V << GPIO_FUNC125_IN_INV_SEL_S) +#define GPIO_FUNC125_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC125_IN_INV_SEL_S 6 + +/* GPIO_FUNC125_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC125_IN_SEL 0x0000003F +#define GPIO_FUNC125_IN_SEL_M (GPIO_FUNC125_IN_SEL_V << GPIO_FUNC125_IN_SEL_S) +#define GPIO_FUNC125_IN_SEL_V 0x0000003F +#define GPIO_FUNC125_IN_SEL_S 0 + +/* GPIO_FUNC126_IN_SEL_CFG_REG register + * Peripheral function 126 input selection register + */ + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) + +/* GPIO_SIG126_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL_M (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S) +#define GPIO_SIG126_IN_SEL_V 0x00000001 +#define GPIO_SIG126_IN_SEL_S 7 + +/* GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_M (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S) +#define GPIO_FUNC126_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC126_IN_INV_SEL_S 6 + +/* GPIO_FUNC126_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC126_IN_SEL 0x0000003F +#define GPIO_FUNC126_IN_SEL_M (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S) +#define GPIO_FUNC126_IN_SEL_V 0x0000003F +#define GPIO_FUNC126_IN_SEL_S 0 + +/* GPIO_FUNC127_IN_SEL_CFG_REG register + * Peripheral function 127 input selection register + */ + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) + +/* GPIO_SIG127_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL_M (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S) +#define GPIO_SIG127_IN_SEL_V 0x00000001 +#define GPIO_SIG127_IN_SEL_S 7 + +/* GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_M (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S) +#define GPIO_FUNC127_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC127_IN_INV_SEL_S 6 + +/* GPIO_FUNC127_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC127_IN_SEL 0x0000003F +#define GPIO_FUNC127_IN_SEL_M (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S) +#define GPIO_FUNC127_IN_SEL_V 0x0000003F +#define GPIO_FUNC127_IN_SEL_S 0 + +/* GPIO_FUNC128_IN_SEL_CFG_REG register + * Peripheral function 128 input selection register + */ + +#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354) + +/* GPIO_SIG128_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG128_IN_SEL (BIT(7)) +#define GPIO_SIG128_IN_SEL_M (GPIO_SIG128_IN_SEL_V << GPIO_SIG128_IN_SEL_S) +#define GPIO_SIG128_IN_SEL_V 0x00000001 +#define GPIO_SIG128_IN_SEL_S 7 + +/* GPIO_FUNC128_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC128_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_M (GPIO_FUNC128_IN_INV_SEL_V << GPIO_FUNC128_IN_INV_SEL_S) +#define GPIO_FUNC128_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC128_IN_INV_SEL_S 6 + +/* GPIO_FUNC128_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC128_IN_SEL 0x0000003F +#define GPIO_FUNC128_IN_SEL_M (GPIO_FUNC128_IN_SEL_V << GPIO_FUNC128_IN_SEL_S) +#define GPIO_FUNC128_IN_SEL_V 0x0000003F +#define GPIO_FUNC128_IN_SEL_S 0 + +/* GPIO_FUNC129_IN_SEL_CFG_REG register + * Peripheral function 129 input selection register + */ + +#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358) + +/* GPIO_SIG129_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG129_IN_SEL (BIT(7)) +#define GPIO_SIG129_IN_SEL_M (GPIO_SIG129_IN_SEL_V << GPIO_SIG129_IN_SEL_S) +#define GPIO_SIG129_IN_SEL_V 0x00000001 +#define GPIO_SIG129_IN_SEL_S 7 + +/* GPIO_FUNC129_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC129_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_M (GPIO_FUNC129_IN_INV_SEL_V << GPIO_FUNC129_IN_INV_SEL_S) +#define GPIO_FUNC129_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC129_IN_INV_SEL_S 6 + +/* GPIO_FUNC129_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC129_IN_SEL 0x0000003F +#define GPIO_FUNC129_IN_SEL_M (GPIO_FUNC129_IN_SEL_V << GPIO_FUNC129_IN_SEL_S) +#define GPIO_FUNC129_IN_SEL_V 0x0000003F +#define GPIO_FUNC129_IN_SEL_S 0 + +/* GPIO_FUNC130_IN_SEL_CFG_REG register + * Peripheral function 130 input selection register + */ + +#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c) + +/* GPIO_SIG130_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG130_IN_SEL (BIT(7)) +#define GPIO_SIG130_IN_SEL_M (GPIO_SIG130_IN_SEL_V << GPIO_SIG130_IN_SEL_S) +#define GPIO_SIG130_IN_SEL_V 0x00000001 +#define GPIO_SIG130_IN_SEL_S 7 + +/* GPIO_FUNC130_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC130_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_M (GPIO_FUNC130_IN_INV_SEL_V << GPIO_FUNC130_IN_INV_SEL_S) +#define GPIO_FUNC130_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC130_IN_INV_SEL_S 6 + +/* GPIO_FUNC130_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC130_IN_SEL 0x0000003F +#define GPIO_FUNC130_IN_SEL_M (GPIO_FUNC130_IN_SEL_V << GPIO_FUNC130_IN_SEL_S) +#define GPIO_FUNC130_IN_SEL_V 0x0000003F +#define GPIO_FUNC130_IN_SEL_S 0 + +/* GPIO_FUNC131_IN_SEL_CFG_REG register + * Peripheral function 131 input selection register + */ + +#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360) + +/* GPIO_SIG131_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG131_IN_SEL (BIT(7)) +#define GPIO_SIG131_IN_SEL_M (GPIO_SIG131_IN_SEL_V << GPIO_SIG131_IN_SEL_S) +#define GPIO_SIG131_IN_SEL_V 0x00000001 +#define GPIO_SIG131_IN_SEL_S 7 + +/* GPIO_FUNC131_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC131_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_M (GPIO_FUNC131_IN_INV_SEL_V << GPIO_FUNC131_IN_INV_SEL_S) +#define GPIO_FUNC131_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC131_IN_INV_SEL_S 6 + +/* GPIO_FUNC131_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC131_IN_SEL 0x0000003F +#define GPIO_FUNC131_IN_SEL_M (GPIO_FUNC131_IN_SEL_V << GPIO_FUNC131_IN_SEL_S) +#define GPIO_FUNC131_IN_SEL_V 0x0000003F +#define GPIO_FUNC131_IN_SEL_S 0 + +/* GPIO_FUNC132_IN_SEL_CFG_REG register + * Peripheral function 132 input selection register + */ + +#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x364) + +/* GPIO_SIG132_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG132_IN_SEL (BIT(7)) +#define GPIO_SIG132_IN_SEL_M (GPIO_SIG132_IN_SEL_V << GPIO_SIG132_IN_SEL_S) +#define GPIO_SIG132_IN_SEL_V 0x00000001 +#define GPIO_SIG132_IN_SEL_S 7 + +/* GPIO_FUNC132_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC132_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_M (GPIO_FUNC132_IN_INV_SEL_V << GPIO_FUNC132_IN_INV_SEL_S) +#define GPIO_FUNC132_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC132_IN_INV_SEL_S 6 + +/* GPIO_FUNC132_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC132_IN_SEL 0x0000003F +#define GPIO_FUNC132_IN_SEL_M (GPIO_FUNC132_IN_SEL_V << GPIO_FUNC132_IN_SEL_S) +#define GPIO_FUNC132_IN_SEL_V 0x0000003F +#define GPIO_FUNC132_IN_SEL_S 0 + +/* GPIO_FUNC133_IN_SEL_CFG_REG register + * Peripheral function 133 input selection register + */ + +#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368) + +/* GPIO_SIG133_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG133_IN_SEL (BIT(7)) +#define GPIO_SIG133_IN_SEL_M (GPIO_SIG133_IN_SEL_V << GPIO_SIG133_IN_SEL_S) +#define GPIO_SIG133_IN_SEL_V 0x00000001 +#define GPIO_SIG133_IN_SEL_S 7 + +/* GPIO_FUNC133_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC133_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_M (GPIO_FUNC133_IN_INV_SEL_V << GPIO_FUNC133_IN_INV_SEL_S) +#define GPIO_FUNC133_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC133_IN_INV_SEL_S 6 + +/* GPIO_FUNC133_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC133_IN_SEL 0x0000003F +#define GPIO_FUNC133_IN_SEL_M (GPIO_FUNC133_IN_SEL_V << GPIO_FUNC133_IN_SEL_S) +#define GPIO_FUNC133_IN_SEL_V 0x0000003F +#define GPIO_FUNC133_IN_SEL_S 0 + +/* GPIO_FUNC134_IN_SEL_CFG_REG register + * Peripheral function 134 input selection register + */ + +#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c) + +/* GPIO_SIG134_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG134_IN_SEL (BIT(7)) +#define GPIO_SIG134_IN_SEL_M (GPIO_SIG134_IN_SEL_V << GPIO_SIG134_IN_SEL_S) +#define GPIO_SIG134_IN_SEL_V 0x00000001 +#define GPIO_SIG134_IN_SEL_S 7 + +/* GPIO_FUNC134_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC134_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_M (GPIO_FUNC134_IN_INV_SEL_V << GPIO_FUNC134_IN_INV_SEL_S) +#define GPIO_FUNC134_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC134_IN_INV_SEL_S 6 + +/* GPIO_FUNC134_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC134_IN_SEL 0x0000003F +#define GPIO_FUNC134_IN_SEL_M (GPIO_FUNC134_IN_SEL_V << GPIO_FUNC134_IN_SEL_S) +#define GPIO_FUNC134_IN_SEL_V 0x0000003F +#define GPIO_FUNC134_IN_SEL_S 0 + +/* GPIO_FUNC135_IN_SEL_CFG_REG register + * Peripheral function 135 input selection register + */ + +#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370) + +/* GPIO_SIG135_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG135_IN_SEL (BIT(7)) +#define GPIO_SIG135_IN_SEL_M (GPIO_SIG135_IN_SEL_V << GPIO_SIG135_IN_SEL_S) +#define GPIO_SIG135_IN_SEL_V 0x00000001 +#define GPIO_SIG135_IN_SEL_S 7 + +/* GPIO_FUNC135_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC135_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_M (GPIO_FUNC135_IN_INV_SEL_V << GPIO_FUNC135_IN_INV_SEL_S) +#define GPIO_FUNC135_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC135_IN_INV_SEL_S 6 + +/* GPIO_FUNC135_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC135_IN_SEL 0x0000003F +#define GPIO_FUNC135_IN_SEL_M (GPIO_FUNC135_IN_SEL_V << GPIO_FUNC135_IN_SEL_S) +#define GPIO_FUNC135_IN_SEL_V 0x0000003F +#define GPIO_FUNC135_IN_SEL_S 0 + +/* GPIO_FUNC136_IN_SEL_CFG_REG register + * Peripheral function 136 input selection register + */ + +#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x374) + +/* GPIO_SIG136_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG136_IN_SEL (BIT(7)) +#define GPIO_SIG136_IN_SEL_M (GPIO_SIG136_IN_SEL_V << GPIO_SIG136_IN_SEL_S) +#define GPIO_SIG136_IN_SEL_V 0x00000001 +#define GPIO_SIG136_IN_SEL_S 7 + +/* GPIO_FUNC136_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC136_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_M (GPIO_FUNC136_IN_INV_SEL_V << GPIO_FUNC136_IN_INV_SEL_S) +#define GPIO_FUNC136_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC136_IN_INV_SEL_S 6 + +/* GPIO_FUNC136_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC136_IN_SEL 0x0000003F +#define GPIO_FUNC136_IN_SEL_M (GPIO_FUNC136_IN_SEL_V << GPIO_FUNC136_IN_SEL_S) +#define GPIO_FUNC136_IN_SEL_V 0x0000003F +#define GPIO_FUNC136_IN_SEL_S 0 + +/* GPIO_FUNC137_IN_SEL_CFG_REG register + * Peripheral function 137 input selection register + */ + +#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378) + +/* GPIO_SIG137_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG137_IN_SEL (BIT(7)) +#define GPIO_SIG137_IN_SEL_M (GPIO_SIG137_IN_SEL_V << GPIO_SIG137_IN_SEL_S) +#define GPIO_SIG137_IN_SEL_V 0x00000001 +#define GPIO_SIG137_IN_SEL_S 7 + +/* GPIO_FUNC137_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC137_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_M (GPIO_FUNC137_IN_INV_SEL_V << GPIO_FUNC137_IN_INV_SEL_S) +#define GPIO_FUNC137_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC137_IN_INV_SEL_S 6 + +/* GPIO_FUNC137_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC137_IN_SEL 0x0000003F +#define GPIO_FUNC137_IN_SEL_M (GPIO_FUNC137_IN_SEL_V << GPIO_FUNC137_IN_SEL_S) +#define GPIO_FUNC137_IN_SEL_V 0x0000003F +#define GPIO_FUNC137_IN_SEL_S 0 + +/* GPIO_FUNC138_IN_SEL_CFG_REG register + * Peripheral function 138 input selection register + */ + +#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) + +/* GPIO_SIG138_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG138_IN_SEL (BIT(7)) +#define GPIO_SIG138_IN_SEL_M (GPIO_SIG138_IN_SEL_V << GPIO_SIG138_IN_SEL_S) +#define GPIO_SIG138_IN_SEL_V 0x00000001 +#define GPIO_SIG138_IN_SEL_S 7 + +/* GPIO_FUNC138_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC138_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_M (GPIO_FUNC138_IN_INV_SEL_V << GPIO_FUNC138_IN_INV_SEL_S) +#define GPIO_FUNC138_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC138_IN_INV_SEL_S 6 + +/* GPIO_FUNC138_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC138_IN_SEL 0x0000003F +#define GPIO_FUNC138_IN_SEL_M (GPIO_FUNC138_IN_SEL_V << GPIO_FUNC138_IN_SEL_S) +#define GPIO_FUNC138_IN_SEL_V 0x0000003F +#define GPIO_FUNC138_IN_SEL_S 0 + +/* GPIO_FUNC139_IN_SEL_CFG_REG register + * Peripheral function 139 input selection register + */ + +#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) + +/* GPIO_SIG139_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG139_IN_SEL (BIT(7)) +#define GPIO_SIG139_IN_SEL_M (GPIO_SIG139_IN_SEL_V << GPIO_SIG139_IN_SEL_S) +#define GPIO_SIG139_IN_SEL_V 0x00000001 +#define GPIO_SIG139_IN_SEL_S 7 + +/* GPIO_FUNC139_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC139_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_M (GPIO_FUNC139_IN_INV_SEL_V << GPIO_FUNC139_IN_INV_SEL_S) +#define GPIO_FUNC139_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC139_IN_INV_SEL_S 6 + +/* GPIO_FUNC139_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC139_IN_SEL 0x0000003F +#define GPIO_FUNC139_IN_SEL_M (GPIO_FUNC139_IN_SEL_V << GPIO_FUNC139_IN_SEL_S) +#define GPIO_FUNC139_IN_SEL_V 0x0000003F +#define GPIO_FUNC139_IN_SEL_S 0 + +/* GPIO_FUNC140_IN_SEL_CFG_REG register + * Peripheral function 140 input selection register + */ + +#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x384) + +/* GPIO_SIG140_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG140_IN_SEL (BIT(7)) +#define GPIO_SIG140_IN_SEL_M (GPIO_SIG140_IN_SEL_V << GPIO_SIG140_IN_SEL_S) +#define GPIO_SIG140_IN_SEL_V 0x00000001 +#define GPIO_SIG140_IN_SEL_S 7 + +/* GPIO_FUNC140_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC140_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_M (GPIO_FUNC140_IN_INV_SEL_V << GPIO_FUNC140_IN_INV_SEL_S) +#define GPIO_FUNC140_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC140_IN_INV_SEL_S 6 + +/* GPIO_FUNC140_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC140_IN_SEL 0x0000003F +#define GPIO_FUNC140_IN_SEL_M (GPIO_FUNC140_IN_SEL_V << GPIO_FUNC140_IN_SEL_S) +#define GPIO_FUNC140_IN_SEL_V 0x0000003F +#define GPIO_FUNC140_IN_SEL_S 0 + +/* GPIO_FUNC141_IN_SEL_CFG_REG register + * Peripheral function 141 input selection register + */ + +#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388) + +/* GPIO_SIG141_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG141_IN_SEL (BIT(7)) +#define GPIO_SIG141_IN_SEL_M (GPIO_SIG141_IN_SEL_V << GPIO_SIG141_IN_SEL_S) +#define GPIO_SIG141_IN_SEL_V 0x00000001 +#define GPIO_SIG141_IN_SEL_S 7 + +/* GPIO_FUNC141_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC141_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_M (GPIO_FUNC141_IN_INV_SEL_V << GPIO_FUNC141_IN_INV_SEL_S) +#define GPIO_FUNC141_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC141_IN_INV_SEL_S 6 + +/* GPIO_FUNC141_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC141_IN_SEL 0x0000003F +#define GPIO_FUNC141_IN_SEL_M (GPIO_FUNC141_IN_SEL_V << GPIO_FUNC141_IN_SEL_S) +#define GPIO_FUNC141_IN_SEL_V 0x0000003F +#define GPIO_FUNC141_IN_SEL_S 0 + +/* GPIO_FUNC142_IN_SEL_CFG_REG register + * Peripheral function 142 input selection register + */ + +#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c) + +/* GPIO_SIG142_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG142_IN_SEL (BIT(7)) +#define GPIO_SIG142_IN_SEL_M (GPIO_SIG142_IN_SEL_V << GPIO_SIG142_IN_SEL_S) +#define GPIO_SIG142_IN_SEL_V 0x00000001 +#define GPIO_SIG142_IN_SEL_S 7 + +/* GPIO_FUNC142_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC142_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_M (GPIO_FUNC142_IN_INV_SEL_V << GPIO_FUNC142_IN_INV_SEL_S) +#define GPIO_FUNC142_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC142_IN_INV_SEL_S 6 + +/* GPIO_FUNC142_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC142_IN_SEL 0x0000003F +#define GPIO_FUNC142_IN_SEL_M (GPIO_FUNC142_IN_SEL_V << GPIO_FUNC142_IN_SEL_S) +#define GPIO_FUNC142_IN_SEL_V 0x0000003F +#define GPIO_FUNC142_IN_SEL_S 0 + +/* GPIO_FUNC143_IN_SEL_CFG_REG register + * Peripheral function 143 input selection register + */ + +#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390) + +/* GPIO_SIG143_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG143_IN_SEL (BIT(7)) +#define GPIO_SIG143_IN_SEL_M (GPIO_SIG143_IN_SEL_V << GPIO_SIG143_IN_SEL_S) +#define GPIO_SIG143_IN_SEL_V 0x00000001 +#define GPIO_SIG143_IN_SEL_S 7 + +/* GPIO_FUNC143_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC143_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_M (GPIO_FUNC143_IN_INV_SEL_V << GPIO_FUNC143_IN_INV_SEL_S) +#define GPIO_FUNC143_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC143_IN_INV_SEL_S 6 + +/* GPIO_FUNC143_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC143_IN_SEL 0x0000003F +#define GPIO_FUNC143_IN_SEL_M (GPIO_FUNC143_IN_SEL_V << GPIO_FUNC143_IN_SEL_S) +#define GPIO_FUNC143_IN_SEL_V 0x0000003F +#define GPIO_FUNC143_IN_SEL_S 0 + +/* GPIO_FUNC144_IN_SEL_CFG_REG register + * Peripheral function 144 input selection register + */ + +#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394) + +/* GPIO_SIG144_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG144_IN_SEL (BIT(7)) +#define GPIO_SIG144_IN_SEL_M (GPIO_SIG144_IN_SEL_V << GPIO_SIG144_IN_SEL_S) +#define GPIO_SIG144_IN_SEL_V 0x00000001 +#define GPIO_SIG144_IN_SEL_S 7 + +/* GPIO_FUNC144_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC144_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_M (GPIO_FUNC144_IN_INV_SEL_V << GPIO_FUNC144_IN_INV_SEL_S) +#define GPIO_FUNC144_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC144_IN_INV_SEL_S 6 + +/* GPIO_FUNC144_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC144_IN_SEL 0x0000003F +#define GPIO_FUNC144_IN_SEL_M (GPIO_FUNC144_IN_SEL_V << GPIO_FUNC144_IN_SEL_S) +#define GPIO_FUNC144_IN_SEL_V 0x0000003F +#define GPIO_FUNC144_IN_SEL_S 0 + +/* GPIO_FUNC145_IN_SEL_CFG_REG register + * Peripheral function 145 input selection register + */ + +#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398) + +/* GPIO_SIG145_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG145_IN_SEL (BIT(7)) +#define GPIO_SIG145_IN_SEL_M (GPIO_SIG145_IN_SEL_V << GPIO_SIG145_IN_SEL_S) +#define GPIO_SIG145_IN_SEL_V 0x00000001 +#define GPIO_SIG145_IN_SEL_S 7 + +/* GPIO_FUNC145_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC145_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_M (GPIO_FUNC145_IN_INV_SEL_V << GPIO_FUNC145_IN_INV_SEL_S) +#define GPIO_FUNC145_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC145_IN_INV_SEL_S 6 + +/* GPIO_FUNC145_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC145_IN_SEL 0x0000003F +#define GPIO_FUNC145_IN_SEL_M (GPIO_FUNC145_IN_SEL_V << GPIO_FUNC145_IN_SEL_S) +#define GPIO_FUNC145_IN_SEL_V 0x0000003F +#define GPIO_FUNC145_IN_SEL_S 0 + +/* GPIO_FUNC146_IN_SEL_CFG_REG register + * Peripheral function 146 input selection register + */ + +#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39c) + +/* GPIO_SIG146_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG146_IN_SEL (BIT(7)) +#define GPIO_SIG146_IN_SEL_M (GPIO_SIG146_IN_SEL_V << GPIO_SIG146_IN_SEL_S) +#define GPIO_SIG146_IN_SEL_V 0x00000001 +#define GPIO_SIG146_IN_SEL_S 7 + +/* GPIO_FUNC146_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC146_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_M (GPIO_FUNC146_IN_INV_SEL_V << GPIO_FUNC146_IN_INV_SEL_S) +#define GPIO_FUNC146_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC146_IN_INV_SEL_S 6 + +/* GPIO_FUNC146_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC146_IN_SEL 0x0000003F +#define GPIO_FUNC146_IN_SEL_M (GPIO_FUNC146_IN_SEL_V << GPIO_FUNC146_IN_SEL_S) +#define GPIO_FUNC146_IN_SEL_V 0x0000003F +#define GPIO_FUNC146_IN_SEL_S 0 + +/* GPIO_FUNC147_IN_SEL_CFG_REG register + * Peripheral function 147 input selection register + */ + +#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0) + +/* GPIO_SIG147_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG147_IN_SEL (BIT(7)) +#define GPIO_SIG147_IN_SEL_M (GPIO_SIG147_IN_SEL_V << GPIO_SIG147_IN_SEL_S) +#define GPIO_SIG147_IN_SEL_V 0x00000001 +#define GPIO_SIG147_IN_SEL_S 7 + +/* GPIO_FUNC147_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC147_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_M (GPIO_FUNC147_IN_INV_SEL_V << GPIO_FUNC147_IN_INV_SEL_S) +#define GPIO_FUNC147_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC147_IN_INV_SEL_S 6 + +/* GPIO_FUNC147_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC147_IN_SEL 0x0000003F +#define GPIO_FUNC147_IN_SEL_M (GPIO_FUNC147_IN_SEL_V << GPIO_FUNC147_IN_SEL_S) +#define GPIO_FUNC147_IN_SEL_V 0x0000003F +#define GPIO_FUNC147_IN_SEL_S 0 + +/* GPIO_FUNC148_IN_SEL_CFG_REG register + * Peripheral function 148 input selection register + */ + +#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4) + +/* GPIO_SIG148_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG148_IN_SEL (BIT(7)) +#define GPIO_SIG148_IN_SEL_M (GPIO_SIG148_IN_SEL_V << GPIO_SIG148_IN_SEL_S) +#define GPIO_SIG148_IN_SEL_V 0x00000001 +#define GPIO_SIG148_IN_SEL_S 7 + +/* GPIO_FUNC148_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC148_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_M (GPIO_FUNC148_IN_INV_SEL_V << GPIO_FUNC148_IN_INV_SEL_S) +#define GPIO_FUNC148_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC148_IN_INV_SEL_S 6 + +/* GPIO_FUNC148_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC148_IN_SEL 0x0000003F +#define GPIO_FUNC148_IN_SEL_M (GPIO_FUNC148_IN_SEL_V << GPIO_FUNC148_IN_SEL_S) +#define GPIO_FUNC148_IN_SEL_V 0x0000003F +#define GPIO_FUNC148_IN_SEL_S 0 + +/* GPIO_FUNC149_IN_SEL_CFG_REG register + * Peripheral function 149 input selection register + */ + +#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8) + +/* GPIO_SIG149_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG149_IN_SEL (BIT(7)) +#define GPIO_SIG149_IN_SEL_M (GPIO_SIG149_IN_SEL_V << GPIO_SIG149_IN_SEL_S) +#define GPIO_SIG149_IN_SEL_V 0x00000001 +#define GPIO_SIG149_IN_SEL_S 7 + +/* GPIO_FUNC149_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC149_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_M (GPIO_FUNC149_IN_INV_SEL_V << GPIO_FUNC149_IN_INV_SEL_S) +#define GPIO_FUNC149_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC149_IN_INV_SEL_S 6 + +/* GPIO_FUNC149_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC149_IN_SEL 0x0000003F +#define GPIO_FUNC149_IN_SEL_M (GPIO_FUNC149_IN_SEL_V << GPIO_FUNC149_IN_SEL_S) +#define GPIO_FUNC149_IN_SEL_V 0x0000003F +#define GPIO_FUNC149_IN_SEL_S 0 + +/* GPIO_FUNC150_IN_SEL_CFG_REG register + * Peripheral function 150 input selection register + */ + +#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ac) + +/* GPIO_SIG150_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG150_IN_SEL (BIT(7)) +#define GPIO_SIG150_IN_SEL_M (GPIO_SIG150_IN_SEL_V << GPIO_SIG150_IN_SEL_S) +#define GPIO_SIG150_IN_SEL_V 0x00000001 +#define GPIO_SIG150_IN_SEL_S 7 + +/* GPIO_FUNC150_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC150_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_M (GPIO_FUNC150_IN_INV_SEL_V << GPIO_FUNC150_IN_INV_SEL_S) +#define GPIO_FUNC150_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC150_IN_INV_SEL_S 6 + +/* GPIO_FUNC150_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC150_IN_SEL 0x0000003F +#define GPIO_FUNC150_IN_SEL_M (GPIO_FUNC150_IN_SEL_V << GPIO_FUNC150_IN_SEL_S) +#define GPIO_FUNC150_IN_SEL_V 0x0000003F +#define GPIO_FUNC150_IN_SEL_S 0 + +/* GPIO_FUNC151_IN_SEL_CFG_REG register + * Peripheral function 151 input selection register + */ + +#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0) + +/* GPIO_SIG151_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG151_IN_SEL (BIT(7)) +#define GPIO_SIG151_IN_SEL_M (GPIO_SIG151_IN_SEL_V << GPIO_SIG151_IN_SEL_S) +#define GPIO_SIG151_IN_SEL_V 0x00000001 +#define GPIO_SIG151_IN_SEL_S 7 + +/* GPIO_FUNC151_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC151_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_M (GPIO_FUNC151_IN_INV_SEL_V << GPIO_FUNC151_IN_INV_SEL_S) +#define GPIO_FUNC151_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC151_IN_INV_SEL_S 6 + +/* GPIO_FUNC151_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC151_IN_SEL 0x0000003F +#define GPIO_FUNC151_IN_SEL_M (GPIO_FUNC151_IN_SEL_V << GPIO_FUNC151_IN_SEL_S) +#define GPIO_FUNC151_IN_SEL_V 0x0000003F +#define GPIO_FUNC151_IN_SEL_S 0 + +/* GPIO_FUNC152_IN_SEL_CFG_REG register + * Peripheral function 152 input selection register + */ + +#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4) + +/* GPIO_SIG152_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG152_IN_SEL (BIT(7)) +#define GPIO_SIG152_IN_SEL_M (GPIO_SIG152_IN_SEL_V << GPIO_SIG152_IN_SEL_S) +#define GPIO_SIG152_IN_SEL_V 0x00000001 +#define GPIO_SIG152_IN_SEL_S 7 + +/* GPIO_FUNC152_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC152_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_M (GPIO_FUNC152_IN_INV_SEL_V << GPIO_FUNC152_IN_INV_SEL_S) +#define GPIO_FUNC152_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC152_IN_INV_SEL_S 6 + +/* GPIO_FUNC152_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC152_IN_SEL 0x0000003F +#define GPIO_FUNC152_IN_SEL_M (GPIO_FUNC152_IN_SEL_V << GPIO_FUNC152_IN_SEL_S) +#define GPIO_FUNC152_IN_SEL_V 0x0000003F +#define GPIO_FUNC152_IN_SEL_S 0 + +/* GPIO_FUNC153_IN_SEL_CFG_REG register + * Peripheral function 153 input selection register + */ + +#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8) + +/* GPIO_SIG153_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG153_IN_SEL (BIT(7)) +#define GPIO_SIG153_IN_SEL_M (GPIO_SIG153_IN_SEL_V << GPIO_SIG153_IN_SEL_S) +#define GPIO_SIG153_IN_SEL_V 0x00000001 +#define GPIO_SIG153_IN_SEL_S 7 + +/* GPIO_FUNC153_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC153_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_M (GPIO_FUNC153_IN_INV_SEL_V << GPIO_FUNC153_IN_INV_SEL_S) +#define GPIO_FUNC153_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC153_IN_INV_SEL_S 6 + +/* GPIO_FUNC153_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC153_IN_SEL 0x0000003F +#define GPIO_FUNC153_IN_SEL_M (GPIO_FUNC153_IN_SEL_V << GPIO_FUNC153_IN_SEL_S) +#define GPIO_FUNC153_IN_SEL_V 0x0000003F +#define GPIO_FUNC153_IN_SEL_S 0 + +/* GPIO_FUNC154_IN_SEL_CFG_REG register + * Peripheral function 154 input selection register + */ + +#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc) + +/* GPIO_SIG154_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG154_IN_SEL (BIT(7)) +#define GPIO_SIG154_IN_SEL_M (GPIO_SIG154_IN_SEL_V << GPIO_SIG154_IN_SEL_S) +#define GPIO_SIG154_IN_SEL_V 0x00000001 +#define GPIO_SIG154_IN_SEL_S 7 + +/* GPIO_FUNC154_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC154_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_M (GPIO_FUNC154_IN_INV_SEL_V << GPIO_FUNC154_IN_INV_SEL_S) +#define GPIO_FUNC154_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC154_IN_INV_SEL_S 6 + +/* GPIO_FUNC154_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC154_IN_SEL 0x0000003F +#define GPIO_FUNC154_IN_SEL_M (GPIO_FUNC154_IN_SEL_V << GPIO_FUNC154_IN_SEL_S) +#define GPIO_FUNC154_IN_SEL_V 0x0000003F +#define GPIO_FUNC154_IN_SEL_S 0 + +/* GPIO_FUNC155_IN_SEL_CFG_REG register + * Peripheral function 155 input selection register + */ + +#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0) + +/* GPIO_SIG155_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG155_IN_SEL (BIT(7)) +#define GPIO_SIG155_IN_SEL_M (GPIO_SIG155_IN_SEL_V << GPIO_SIG155_IN_SEL_S) +#define GPIO_SIG155_IN_SEL_V 0x00000001 +#define GPIO_SIG155_IN_SEL_S 7 + +/* GPIO_FUNC155_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC155_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_M (GPIO_FUNC155_IN_INV_SEL_V << GPIO_FUNC155_IN_INV_SEL_S) +#define GPIO_FUNC155_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC155_IN_INV_SEL_S 6 + +/* GPIO_FUNC155_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC155_IN_SEL 0x0000003F +#define GPIO_FUNC155_IN_SEL_M (GPIO_FUNC155_IN_SEL_V << GPIO_FUNC155_IN_SEL_S) +#define GPIO_FUNC155_IN_SEL_V 0x0000003F +#define GPIO_FUNC155_IN_SEL_S 0 + +/* GPIO_FUNC156_IN_SEL_CFG_REG register + * Peripheral function 156 input selection register + */ + +#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4) + +/* GPIO_SIG156_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG156_IN_SEL (BIT(7)) +#define GPIO_SIG156_IN_SEL_M (GPIO_SIG156_IN_SEL_V << GPIO_SIG156_IN_SEL_S) +#define GPIO_SIG156_IN_SEL_V 0x00000001 +#define GPIO_SIG156_IN_SEL_S 7 + +/* GPIO_FUNC156_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC156_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_M (GPIO_FUNC156_IN_INV_SEL_V << GPIO_FUNC156_IN_INV_SEL_S) +#define GPIO_FUNC156_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC156_IN_INV_SEL_S 6 + +/* GPIO_FUNC156_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC156_IN_SEL 0x0000003F +#define GPIO_FUNC156_IN_SEL_M (GPIO_FUNC156_IN_SEL_V << GPIO_FUNC156_IN_SEL_S) +#define GPIO_FUNC156_IN_SEL_V 0x0000003F +#define GPIO_FUNC156_IN_SEL_S 0 + +/* GPIO_FUNC157_IN_SEL_CFG_REG register + * Peripheral function 157 input selection register + */ + +#define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8) + +/* GPIO_SIG157_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG157_IN_SEL (BIT(7)) +#define GPIO_SIG157_IN_SEL_M (GPIO_SIG157_IN_SEL_V << GPIO_SIG157_IN_SEL_S) +#define GPIO_SIG157_IN_SEL_V 0x00000001 +#define GPIO_SIG157_IN_SEL_S 7 + +/* GPIO_FUNC157_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC157_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_M (GPIO_FUNC157_IN_INV_SEL_V << GPIO_FUNC157_IN_INV_SEL_S) +#define GPIO_FUNC157_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC157_IN_INV_SEL_S 6 + +/* GPIO_FUNC157_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC157_IN_SEL 0x0000003F +#define GPIO_FUNC157_IN_SEL_M (GPIO_FUNC157_IN_SEL_V << GPIO_FUNC157_IN_SEL_S) +#define GPIO_FUNC157_IN_SEL_V 0x0000003F +#define GPIO_FUNC157_IN_SEL_S 0 + +/* GPIO_FUNC158_IN_SEL_CFG_REG register + * Peripheral function 158 input selection register + */ + +#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc) + +/* GPIO_SIG158_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG158_IN_SEL (BIT(7)) +#define GPIO_SIG158_IN_SEL_M (GPIO_SIG158_IN_SEL_V << GPIO_SIG158_IN_SEL_S) +#define GPIO_SIG158_IN_SEL_V 0x00000001 +#define GPIO_SIG158_IN_SEL_S 7 + +/* GPIO_FUNC158_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC158_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_M (GPIO_FUNC158_IN_INV_SEL_V << GPIO_FUNC158_IN_INV_SEL_S) +#define GPIO_FUNC158_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC158_IN_INV_SEL_S 6 + +/* GPIO_FUNC158_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC158_IN_SEL 0x0000003F +#define GPIO_FUNC158_IN_SEL_M (GPIO_FUNC158_IN_SEL_V << GPIO_FUNC158_IN_SEL_S) +#define GPIO_FUNC158_IN_SEL_V 0x0000003F +#define GPIO_FUNC158_IN_SEL_S 0 + +/* GPIO_FUNC159_IN_SEL_CFG_REG register + * Peripheral function 159 input selection register + */ + +#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0) + +/* GPIO_SIG159_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG159_IN_SEL (BIT(7)) +#define GPIO_SIG159_IN_SEL_M (GPIO_SIG159_IN_SEL_V << GPIO_SIG159_IN_SEL_S) +#define GPIO_SIG159_IN_SEL_V 0x00000001 +#define GPIO_SIG159_IN_SEL_S 7 + +/* GPIO_FUNC159_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC159_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_M (GPIO_FUNC159_IN_INV_SEL_V << GPIO_FUNC159_IN_INV_SEL_S) +#define GPIO_FUNC159_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC159_IN_INV_SEL_S 6 + +/* GPIO_FUNC159_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC159_IN_SEL 0x0000003F +#define GPIO_FUNC159_IN_SEL_M (GPIO_FUNC159_IN_SEL_V << GPIO_FUNC159_IN_SEL_S) +#define GPIO_FUNC159_IN_SEL_V 0x0000003F +#define GPIO_FUNC159_IN_SEL_S 0 + +/* GPIO_FUNC160_IN_SEL_CFG_REG register + * Peripheral function 160 input selection register + */ + +#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4) + +/* GPIO_SIG160_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG160_IN_SEL (BIT(7)) +#define GPIO_SIG160_IN_SEL_M (GPIO_SIG160_IN_SEL_V << GPIO_SIG160_IN_SEL_S) +#define GPIO_SIG160_IN_SEL_V 0x00000001 +#define GPIO_SIG160_IN_SEL_S 7 + +/* GPIO_FUNC160_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC160_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_M (GPIO_FUNC160_IN_INV_SEL_V << GPIO_FUNC160_IN_INV_SEL_S) +#define GPIO_FUNC160_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC160_IN_INV_SEL_S 6 + +/* GPIO_FUNC160_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC160_IN_SEL 0x0000003F +#define GPIO_FUNC160_IN_SEL_M (GPIO_FUNC160_IN_SEL_V << GPIO_FUNC160_IN_SEL_S) +#define GPIO_FUNC160_IN_SEL_V 0x0000003F +#define GPIO_FUNC160_IN_SEL_S 0 + +/* GPIO_FUNC161_IN_SEL_CFG_REG register + * Peripheral function 161 input selection register + */ + +#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8) + +/* GPIO_SIG161_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG161_IN_SEL (BIT(7)) +#define GPIO_SIG161_IN_SEL_M (GPIO_SIG161_IN_SEL_V << GPIO_SIG161_IN_SEL_S) +#define GPIO_SIG161_IN_SEL_V 0x00000001 +#define GPIO_SIG161_IN_SEL_S 7 + +/* GPIO_FUNC161_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC161_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_M (GPIO_FUNC161_IN_INV_SEL_V << GPIO_FUNC161_IN_INV_SEL_S) +#define GPIO_FUNC161_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC161_IN_INV_SEL_S 6 + +/* GPIO_FUNC161_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC161_IN_SEL 0x0000003F +#define GPIO_FUNC161_IN_SEL_M (GPIO_FUNC161_IN_SEL_V << GPIO_FUNC161_IN_SEL_S) +#define GPIO_FUNC161_IN_SEL_V 0x0000003F +#define GPIO_FUNC161_IN_SEL_S 0 + +/* GPIO_FUNC162_IN_SEL_CFG_REG register + * Peripheral function 162 input selection register + */ + +#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc) + +/* GPIO_SIG162_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG162_IN_SEL (BIT(7)) +#define GPIO_SIG162_IN_SEL_M (GPIO_SIG162_IN_SEL_V << GPIO_SIG162_IN_SEL_S) +#define GPIO_SIG162_IN_SEL_V 0x00000001 +#define GPIO_SIG162_IN_SEL_S 7 + +/* GPIO_FUNC162_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC162_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_M (GPIO_FUNC162_IN_INV_SEL_V << GPIO_FUNC162_IN_INV_SEL_S) +#define GPIO_FUNC162_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC162_IN_INV_SEL_S 6 + +/* GPIO_FUNC162_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC162_IN_SEL 0x0000003F +#define GPIO_FUNC162_IN_SEL_M (GPIO_FUNC162_IN_SEL_V << GPIO_FUNC162_IN_SEL_S) +#define GPIO_FUNC162_IN_SEL_V 0x0000003F +#define GPIO_FUNC162_IN_SEL_S 0 + +/* GPIO_FUNC163_IN_SEL_CFG_REG register + * Peripheral function 163 input selection register + */ + +#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0) + +/* GPIO_SIG163_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG163_IN_SEL (BIT(7)) +#define GPIO_SIG163_IN_SEL_M (GPIO_SIG163_IN_SEL_V << GPIO_SIG163_IN_SEL_S) +#define GPIO_SIG163_IN_SEL_V 0x00000001 +#define GPIO_SIG163_IN_SEL_S 7 + +/* GPIO_FUNC163_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC163_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_M (GPIO_FUNC163_IN_INV_SEL_V << GPIO_FUNC163_IN_INV_SEL_S) +#define GPIO_FUNC163_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC163_IN_INV_SEL_S 6 + +/* GPIO_FUNC163_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC163_IN_SEL 0x0000003F +#define GPIO_FUNC163_IN_SEL_M (GPIO_FUNC163_IN_SEL_V << GPIO_FUNC163_IN_SEL_S) +#define GPIO_FUNC163_IN_SEL_V 0x0000003F +#define GPIO_FUNC163_IN_SEL_S 0 + +/* GPIO_FUNC164_IN_SEL_CFG_REG register + * Peripheral function 164 input selection register + */ + +#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4) + +/* GPIO_SIG164_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG164_IN_SEL (BIT(7)) +#define GPIO_SIG164_IN_SEL_M (GPIO_SIG164_IN_SEL_V << GPIO_SIG164_IN_SEL_S) +#define GPIO_SIG164_IN_SEL_V 0x00000001 +#define GPIO_SIG164_IN_SEL_S 7 + +/* GPIO_FUNC164_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC164_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_M (GPIO_FUNC164_IN_INV_SEL_V << GPIO_FUNC164_IN_INV_SEL_S) +#define GPIO_FUNC164_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC164_IN_INV_SEL_S 6 + +/* GPIO_FUNC164_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC164_IN_SEL 0x0000003F +#define GPIO_FUNC164_IN_SEL_M (GPIO_FUNC164_IN_SEL_V << GPIO_FUNC164_IN_SEL_S) +#define GPIO_FUNC164_IN_SEL_V 0x0000003F +#define GPIO_FUNC164_IN_SEL_S 0 + +/* GPIO_FUNC165_IN_SEL_CFG_REG register + * Peripheral function 165 input selection register + */ + +#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8) + +/* GPIO_SIG165_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG165_IN_SEL (BIT(7)) +#define GPIO_SIG165_IN_SEL_M (GPIO_SIG165_IN_SEL_V << GPIO_SIG165_IN_SEL_S) +#define GPIO_SIG165_IN_SEL_V 0x00000001 +#define GPIO_SIG165_IN_SEL_S 7 + +/* GPIO_FUNC165_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC165_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_M (GPIO_FUNC165_IN_INV_SEL_V << GPIO_FUNC165_IN_INV_SEL_S) +#define GPIO_FUNC165_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC165_IN_INV_SEL_S 6 + +/* GPIO_FUNC165_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC165_IN_SEL 0x0000003F +#define GPIO_FUNC165_IN_SEL_M (GPIO_FUNC165_IN_SEL_V << GPIO_FUNC165_IN_SEL_S) +#define GPIO_FUNC165_IN_SEL_V 0x0000003F +#define GPIO_FUNC165_IN_SEL_S 0 + +/* GPIO_FUNC166_IN_SEL_CFG_REG register + * Peripheral function 166 input selection register + */ + +#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec) + +/* GPIO_SIG166_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG166_IN_SEL (BIT(7)) +#define GPIO_SIG166_IN_SEL_M (GPIO_SIG166_IN_SEL_V << GPIO_SIG166_IN_SEL_S) +#define GPIO_SIG166_IN_SEL_V 0x00000001 +#define GPIO_SIG166_IN_SEL_S 7 + +/* GPIO_FUNC166_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC166_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_M (GPIO_FUNC166_IN_INV_SEL_V << GPIO_FUNC166_IN_INV_SEL_S) +#define GPIO_FUNC166_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC166_IN_INV_SEL_S 6 + +/* GPIO_FUNC166_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC166_IN_SEL 0x0000003F +#define GPIO_FUNC166_IN_SEL_M (GPIO_FUNC166_IN_SEL_V << GPIO_FUNC166_IN_SEL_S) +#define GPIO_FUNC166_IN_SEL_V 0x0000003F +#define GPIO_FUNC166_IN_SEL_S 0 + +/* GPIO_FUNC167_IN_SEL_CFG_REG register + * Peripheral function 167 input selection register + */ + +#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f0) + +/* GPIO_SIG167_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG167_IN_SEL (BIT(7)) +#define GPIO_SIG167_IN_SEL_M (GPIO_SIG167_IN_SEL_V << GPIO_SIG167_IN_SEL_S) +#define GPIO_SIG167_IN_SEL_V 0x00000001 +#define GPIO_SIG167_IN_SEL_S 7 + +/* GPIO_FUNC167_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC167_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_M (GPIO_FUNC167_IN_INV_SEL_V << GPIO_FUNC167_IN_INV_SEL_S) +#define GPIO_FUNC167_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC167_IN_INV_SEL_S 6 + +/* GPIO_FUNC167_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC167_IN_SEL 0x0000003F +#define GPIO_FUNC167_IN_SEL_M (GPIO_FUNC167_IN_SEL_V << GPIO_FUNC167_IN_SEL_S) +#define GPIO_FUNC167_IN_SEL_V 0x0000003F +#define GPIO_FUNC167_IN_SEL_S 0 + +/* GPIO_FUNC168_IN_SEL_CFG_REG register + * Peripheral function 168 input selection register + */ + +#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4) + +/* GPIO_SIG168_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG168_IN_SEL (BIT(7)) +#define GPIO_SIG168_IN_SEL_M (GPIO_SIG168_IN_SEL_V << GPIO_SIG168_IN_SEL_S) +#define GPIO_SIG168_IN_SEL_V 0x00000001 +#define GPIO_SIG168_IN_SEL_S 7 + +/* GPIO_FUNC168_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC168_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_M (GPIO_FUNC168_IN_INV_SEL_V << GPIO_FUNC168_IN_INV_SEL_S) +#define GPIO_FUNC168_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC168_IN_INV_SEL_S 6 + +/* GPIO_FUNC168_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC168_IN_SEL 0x0000003F +#define GPIO_FUNC168_IN_SEL_M (GPIO_FUNC168_IN_SEL_V << GPIO_FUNC168_IN_SEL_S) +#define GPIO_FUNC168_IN_SEL_V 0x0000003F +#define GPIO_FUNC168_IN_SEL_S 0 + +/* GPIO_FUNC169_IN_SEL_CFG_REG register + * Peripheral function 169 input selection register + */ + +#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8) + +/* GPIO_SIG169_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG169_IN_SEL (BIT(7)) +#define GPIO_SIG169_IN_SEL_M (GPIO_SIG169_IN_SEL_V << GPIO_SIG169_IN_SEL_S) +#define GPIO_SIG169_IN_SEL_V 0x00000001 +#define GPIO_SIG169_IN_SEL_S 7 + +/* GPIO_FUNC169_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC169_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_M (GPIO_FUNC169_IN_INV_SEL_V << GPIO_FUNC169_IN_INV_SEL_S) +#define GPIO_FUNC169_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC169_IN_INV_SEL_S 6 + +/* GPIO_FUNC169_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC169_IN_SEL 0x0000003F +#define GPIO_FUNC169_IN_SEL_M (GPIO_FUNC169_IN_SEL_V << GPIO_FUNC169_IN_SEL_S) +#define GPIO_FUNC169_IN_SEL_V 0x0000003F +#define GPIO_FUNC169_IN_SEL_S 0 + +/* GPIO_FUNC170_IN_SEL_CFG_REG register + * Peripheral function 170 input selection register + */ + +#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc) + +/* GPIO_SIG170_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG170_IN_SEL (BIT(7)) +#define GPIO_SIG170_IN_SEL_M (GPIO_SIG170_IN_SEL_V << GPIO_SIG170_IN_SEL_S) +#define GPIO_SIG170_IN_SEL_V 0x00000001 +#define GPIO_SIG170_IN_SEL_S 7 + +/* GPIO_FUNC170_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC170_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_M (GPIO_FUNC170_IN_INV_SEL_V << GPIO_FUNC170_IN_INV_SEL_S) +#define GPIO_FUNC170_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC170_IN_INV_SEL_S 6 + +/* GPIO_FUNC170_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC170_IN_SEL 0x0000003F +#define GPIO_FUNC170_IN_SEL_M (GPIO_FUNC170_IN_SEL_V << GPIO_FUNC170_IN_SEL_S) +#define GPIO_FUNC170_IN_SEL_V 0x0000003F +#define GPIO_FUNC170_IN_SEL_S 0 + +/* GPIO_FUNC171_IN_SEL_CFG_REG register + * Peripheral function 171 input selection register + */ + +#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400) + +/* GPIO_SIG171_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG171_IN_SEL (BIT(7)) +#define GPIO_SIG171_IN_SEL_M (GPIO_SIG171_IN_SEL_V << GPIO_SIG171_IN_SEL_S) +#define GPIO_SIG171_IN_SEL_V 0x00000001 +#define GPIO_SIG171_IN_SEL_S 7 + +/* GPIO_FUNC171_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC171_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_M (GPIO_FUNC171_IN_INV_SEL_V << GPIO_FUNC171_IN_INV_SEL_S) +#define GPIO_FUNC171_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC171_IN_INV_SEL_S 6 + +/* GPIO_FUNC171_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC171_IN_SEL 0x0000003F +#define GPIO_FUNC171_IN_SEL_M (GPIO_FUNC171_IN_SEL_V << GPIO_FUNC171_IN_SEL_S) +#define GPIO_FUNC171_IN_SEL_V 0x0000003F +#define GPIO_FUNC171_IN_SEL_S 0 + +/* GPIO_FUNC172_IN_SEL_CFG_REG register + * Peripheral function 172 input selection register + */ + +#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404) + +/* GPIO_SIG172_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG172_IN_SEL (BIT(7)) +#define GPIO_SIG172_IN_SEL_M (GPIO_SIG172_IN_SEL_V << GPIO_SIG172_IN_SEL_S) +#define GPIO_SIG172_IN_SEL_V 0x00000001 +#define GPIO_SIG172_IN_SEL_S 7 + +/* GPIO_FUNC172_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC172_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_M (GPIO_FUNC172_IN_INV_SEL_V << GPIO_FUNC172_IN_INV_SEL_S) +#define GPIO_FUNC172_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC172_IN_INV_SEL_S 6 + +/* GPIO_FUNC172_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC172_IN_SEL 0x0000003F +#define GPIO_FUNC172_IN_SEL_M (GPIO_FUNC172_IN_SEL_V << GPIO_FUNC172_IN_SEL_S) +#define GPIO_FUNC172_IN_SEL_V 0x0000003F +#define GPIO_FUNC172_IN_SEL_S 0 + +/* GPIO_FUNC173_IN_SEL_CFG_REG register + * Peripheral function 173 input selection register + */ + +#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408) + +/* GPIO_SIG173_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG173_IN_SEL (BIT(7)) +#define GPIO_SIG173_IN_SEL_M (GPIO_SIG173_IN_SEL_V << GPIO_SIG173_IN_SEL_S) +#define GPIO_SIG173_IN_SEL_V 0x00000001 +#define GPIO_SIG173_IN_SEL_S 7 + +/* GPIO_FUNC173_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC173_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_M (GPIO_FUNC173_IN_INV_SEL_V << GPIO_FUNC173_IN_INV_SEL_S) +#define GPIO_FUNC173_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC173_IN_INV_SEL_S 6 + +/* GPIO_FUNC173_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC173_IN_SEL 0x0000003F +#define GPIO_FUNC173_IN_SEL_M (GPIO_FUNC173_IN_SEL_V << GPIO_FUNC173_IN_SEL_S) +#define GPIO_FUNC173_IN_SEL_V 0x0000003F +#define GPIO_FUNC173_IN_SEL_S 0 + +/* GPIO_FUNC174_IN_SEL_CFG_REG register + * Peripheral function 174 input selection register + */ + +#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c) + +/* GPIO_SIG174_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG174_IN_SEL (BIT(7)) +#define GPIO_SIG174_IN_SEL_M (GPIO_SIG174_IN_SEL_V << GPIO_SIG174_IN_SEL_S) +#define GPIO_SIG174_IN_SEL_V 0x00000001 +#define GPIO_SIG174_IN_SEL_S 7 + +/* GPIO_FUNC174_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC174_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_M (GPIO_FUNC174_IN_INV_SEL_V << GPIO_FUNC174_IN_INV_SEL_S) +#define GPIO_FUNC174_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC174_IN_INV_SEL_S 6 + +/* GPIO_FUNC174_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC174_IN_SEL 0x0000003F +#define GPIO_FUNC174_IN_SEL_M (GPIO_FUNC174_IN_SEL_V << GPIO_FUNC174_IN_SEL_S) +#define GPIO_FUNC174_IN_SEL_V 0x0000003F +#define GPIO_FUNC174_IN_SEL_S 0 + +/* GPIO_FUNC175_IN_SEL_CFG_REG register + * Peripheral function 175 input selection register + */ + +#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410) + +/* GPIO_SIG175_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG175_IN_SEL (BIT(7)) +#define GPIO_SIG175_IN_SEL_M (GPIO_SIG175_IN_SEL_V << GPIO_SIG175_IN_SEL_S) +#define GPIO_SIG175_IN_SEL_V 0x00000001 +#define GPIO_SIG175_IN_SEL_S 7 + +/* GPIO_FUNC175_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC175_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_M (GPIO_FUNC175_IN_INV_SEL_V << GPIO_FUNC175_IN_INV_SEL_S) +#define GPIO_FUNC175_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC175_IN_INV_SEL_S 6 + +/* GPIO_FUNC175_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC175_IN_SEL 0x0000003F +#define GPIO_FUNC175_IN_SEL_M (GPIO_FUNC175_IN_SEL_V << GPIO_FUNC175_IN_SEL_S) +#define GPIO_FUNC175_IN_SEL_V 0x0000003F +#define GPIO_FUNC175_IN_SEL_S 0 + +/* GPIO_FUNC176_IN_SEL_CFG_REG register + * Peripheral function 176 input selection register + */ + +#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414) + +/* GPIO_SIG176_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG176_IN_SEL (BIT(7)) +#define GPIO_SIG176_IN_SEL_M (GPIO_SIG176_IN_SEL_V << GPIO_SIG176_IN_SEL_S) +#define GPIO_SIG176_IN_SEL_V 0x00000001 +#define GPIO_SIG176_IN_SEL_S 7 + +/* GPIO_FUNC176_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC176_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_M (GPIO_FUNC176_IN_INV_SEL_V << GPIO_FUNC176_IN_INV_SEL_S) +#define GPIO_FUNC176_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC176_IN_INV_SEL_S 6 + +/* GPIO_FUNC176_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC176_IN_SEL 0x0000003F +#define GPIO_FUNC176_IN_SEL_M (GPIO_FUNC176_IN_SEL_V << GPIO_FUNC176_IN_SEL_S) +#define GPIO_FUNC176_IN_SEL_V 0x0000003F +#define GPIO_FUNC176_IN_SEL_S 0 + +/* GPIO_FUNC177_IN_SEL_CFG_REG register + * Peripheral function 177 input selection register + */ + +#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418) + +/* GPIO_SIG177_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG177_IN_SEL (BIT(7)) +#define GPIO_SIG177_IN_SEL_M (GPIO_SIG177_IN_SEL_V << GPIO_SIG177_IN_SEL_S) +#define GPIO_SIG177_IN_SEL_V 0x00000001 +#define GPIO_SIG177_IN_SEL_S 7 + +/* GPIO_FUNC177_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC177_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_M (GPIO_FUNC177_IN_INV_SEL_V << GPIO_FUNC177_IN_INV_SEL_S) +#define GPIO_FUNC177_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC177_IN_INV_SEL_S 6 + +/* GPIO_FUNC177_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC177_IN_SEL 0x0000003F +#define GPIO_FUNC177_IN_SEL_M (GPIO_FUNC177_IN_SEL_V << GPIO_FUNC177_IN_SEL_S) +#define GPIO_FUNC177_IN_SEL_V 0x0000003F +#define GPIO_FUNC177_IN_SEL_S 0 + +/* GPIO_FUNC178_IN_SEL_CFG_REG register + * Peripheral function 178 input selection register + */ + +#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c) + +/* GPIO_SIG178_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG178_IN_SEL (BIT(7)) +#define GPIO_SIG178_IN_SEL_M (GPIO_SIG178_IN_SEL_V << GPIO_SIG178_IN_SEL_S) +#define GPIO_SIG178_IN_SEL_V 0x00000001 +#define GPIO_SIG178_IN_SEL_S 7 + +/* GPIO_FUNC178_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC178_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_M (GPIO_FUNC178_IN_INV_SEL_V << GPIO_FUNC178_IN_INV_SEL_S) +#define GPIO_FUNC178_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC178_IN_INV_SEL_S 6 + +/* GPIO_FUNC178_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC178_IN_SEL 0x0000003F +#define GPIO_FUNC178_IN_SEL_M (GPIO_FUNC178_IN_SEL_V << GPIO_FUNC178_IN_SEL_S) +#define GPIO_FUNC178_IN_SEL_V 0x0000003F +#define GPIO_FUNC178_IN_SEL_S 0 + +/* GPIO_FUNC179_IN_SEL_CFG_REG register + * Peripheral function 179 input selection register + */ + +#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420) + +/* GPIO_SIG179_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG179_IN_SEL (BIT(7)) +#define GPIO_SIG179_IN_SEL_M (GPIO_SIG179_IN_SEL_V << GPIO_SIG179_IN_SEL_S) +#define GPIO_SIG179_IN_SEL_V 0x00000001 +#define GPIO_SIG179_IN_SEL_S 7 + +/* GPIO_FUNC179_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC179_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_M (GPIO_FUNC179_IN_INV_SEL_V << GPIO_FUNC179_IN_INV_SEL_S) +#define GPIO_FUNC179_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC179_IN_INV_SEL_S 6 + +/* GPIO_FUNC179_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC179_IN_SEL 0x0000003F +#define GPIO_FUNC179_IN_SEL_M (GPIO_FUNC179_IN_SEL_V << GPIO_FUNC179_IN_SEL_S) +#define GPIO_FUNC179_IN_SEL_V 0x0000003F +#define GPIO_FUNC179_IN_SEL_S 0 + +/* GPIO_FUNC180_IN_SEL_CFG_REG register + * Peripheral function 180 input selection register + */ + +#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424) + +/* GPIO_SIG180_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG180_IN_SEL (BIT(7)) +#define GPIO_SIG180_IN_SEL_M (GPIO_SIG180_IN_SEL_V << GPIO_SIG180_IN_SEL_S) +#define GPIO_SIG180_IN_SEL_V 0x00000001 +#define GPIO_SIG180_IN_SEL_S 7 + +/* GPIO_FUNC180_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC180_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_M (GPIO_FUNC180_IN_INV_SEL_V << GPIO_FUNC180_IN_INV_SEL_S) +#define GPIO_FUNC180_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC180_IN_INV_SEL_S 6 + +/* GPIO_FUNC180_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC180_IN_SEL 0x0000003F +#define GPIO_FUNC180_IN_SEL_M (GPIO_FUNC180_IN_SEL_V << GPIO_FUNC180_IN_SEL_S) +#define GPIO_FUNC180_IN_SEL_V 0x0000003F +#define GPIO_FUNC180_IN_SEL_S 0 + +/* GPIO_FUNC181_IN_SEL_CFG_REG register + * Peripheral function 181 input selection register + */ + +#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428) + +/* GPIO_SIG181_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG181_IN_SEL (BIT(7)) +#define GPIO_SIG181_IN_SEL_M (GPIO_SIG181_IN_SEL_V << GPIO_SIG181_IN_SEL_S) +#define GPIO_SIG181_IN_SEL_V 0x00000001 +#define GPIO_SIG181_IN_SEL_S 7 + +/* GPIO_FUNC181_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC181_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_M (GPIO_FUNC181_IN_INV_SEL_V << GPIO_FUNC181_IN_INV_SEL_S) +#define GPIO_FUNC181_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC181_IN_INV_SEL_S 6 + +/* GPIO_FUNC181_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC181_IN_SEL 0x0000003F +#define GPIO_FUNC181_IN_SEL_M (GPIO_FUNC181_IN_SEL_V << GPIO_FUNC181_IN_SEL_S) +#define GPIO_FUNC181_IN_SEL_V 0x0000003F +#define GPIO_FUNC181_IN_SEL_S 0 + +/* GPIO_FUNC182_IN_SEL_CFG_REG register + * Peripheral function 182 input selection register + */ + +#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c) + +/* GPIO_SIG182_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG182_IN_SEL (BIT(7)) +#define GPIO_SIG182_IN_SEL_M (GPIO_SIG182_IN_SEL_V << GPIO_SIG182_IN_SEL_S) +#define GPIO_SIG182_IN_SEL_V 0x00000001 +#define GPIO_SIG182_IN_SEL_S 7 + +/* GPIO_FUNC182_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC182_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_M (GPIO_FUNC182_IN_INV_SEL_V << GPIO_FUNC182_IN_INV_SEL_S) +#define GPIO_FUNC182_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC182_IN_INV_SEL_S 6 + +/* GPIO_FUNC182_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC182_IN_SEL 0x0000003F +#define GPIO_FUNC182_IN_SEL_M (GPIO_FUNC182_IN_SEL_V << GPIO_FUNC182_IN_SEL_S) +#define GPIO_FUNC182_IN_SEL_V 0x0000003F +#define GPIO_FUNC182_IN_SEL_S 0 + +/* GPIO_FUNC183_IN_SEL_CFG_REG register + * Peripheral function 183 input selection register + */ + +#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430) + +/* GPIO_SIG183_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG183_IN_SEL (BIT(7)) +#define GPIO_SIG183_IN_SEL_M (GPIO_SIG183_IN_SEL_V << GPIO_SIG183_IN_SEL_S) +#define GPIO_SIG183_IN_SEL_V 0x00000001 +#define GPIO_SIG183_IN_SEL_S 7 + +/* GPIO_FUNC183_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC183_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_M (GPIO_FUNC183_IN_INV_SEL_V << GPIO_FUNC183_IN_INV_SEL_S) +#define GPIO_FUNC183_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC183_IN_INV_SEL_S 6 + +/* GPIO_FUNC183_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC183_IN_SEL 0x0000003F +#define GPIO_FUNC183_IN_SEL_M (GPIO_FUNC183_IN_SEL_V << GPIO_FUNC183_IN_SEL_S) +#define GPIO_FUNC183_IN_SEL_V 0x0000003F +#define GPIO_FUNC183_IN_SEL_S 0 + +/* GPIO_FUNC184_IN_SEL_CFG_REG register + * Peripheral function 184 input selection register + */ + +#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434) + +/* GPIO_SIG184_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG184_IN_SEL (BIT(7)) +#define GPIO_SIG184_IN_SEL_M (GPIO_SIG184_IN_SEL_V << GPIO_SIG184_IN_SEL_S) +#define GPIO_SIG184_IN_SEL_V 0x00000001 +#define GPIO_SIG184_IN_SEL_S 7 + +/* GPIO_FUNC184_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC184_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_M (GPIO_FUNC184_IN_INV_SEL_V << GPIO_FUNC184_IN_INV_SEL_S) +#define GPIO_FUNC184_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC184_IN_INV_SEL_S 6 + +/* GPIO_FUNC184_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC184_IN_SEL 0x0000003F +#define GPIO_FUNC184_IN_SEL_M (GPIO_FUNC184_IN_SEL_V << GPIO_FUNC184_IN_SEL_S) +#define GPIO_FUNC184_IN_SEL_V 0x0000003F +#define GPIO_FUNC184_IN_SEL_S 0 + +/* GPIO_FUNC185_IN_SEL_CFG_REG register + * Peripheral function 185 input selection register + */ + +#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438) + +/* GPIO_SIG185_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG185_IN_SEL (BIT(7)) +#define GPIO_SIG185_IN_SEL_M (GPIO_SIG185_IN_SEL_V << GPIO_SIG185_IN_SEL_S) +#define GPIO_SIG185_IN_SEL_V 0x00000001 +#define GPIO_SIG185_IN_SEL_S 7 + +/* GPIO_FUNC185_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC185_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_M (GPIO_FUNC185_IN_INV_SEL_V << GPIO_FUNC185_IN_INV_SEL_S) +#define GPIO_FUNC185_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC185_IN_INV_SEL_S 6 + +/* GPIO_FUNC185_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC185_IN_SEL 0x0000003F +#define GPIO_FUNC185_IN_SEL_M (GPIO_FUNC185_IN_SEL_V << GPIO_FUNC185_IN_SEL_S) +#define GPIO_FUNC185_IN_SEL_V 0x0000003F +#define GPIO_FUNC185_IN_SEL_S 0 + +/* GPIO_FUNC186_IN_SEL_CFG_REG register + * Peripheral function 186 input selection register + */ + +#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43c) + +/* GPIO_SIG186_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG186_IN_SEL (BIT(7)) +#define GPIO_SIG186_IN_SEL_M (GPIO_SIG186_IN_SEL_V << GPIO_SIG186_IN_SEL_S) +#define GPIO_SIG186_IN_SEL_V 0x00000001 +#define GPIO_SIG186_IN_SEL_S 7 + +/* GPIO_FUNC186_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC186_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_M (GPIO_FUNC186_IN_INV_SEL_V << GPIO_FUNC186_IN_INV_SEL_S) +#define GPIO_FUNC186_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC186_IN_INV_SEL_S 6 + +/* GPIO_FUNC186_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC186_IN_SEL 0x0000003F +#define GPIO_FUNC186_IN_SEL_M (GPIO_FUNC186_IN_SEL_V << GPIO_FUNC186_IN_SEL_S) +#define GPIO_FUNC186_IN_SEL_V 0x0000003F +#define GPIO_FUNC186_IN_SEL_S 0 + +/* GPIO_FUNC187_IN_SEL_CFG_REG register + * Peripheral function 187 input selection register + */ + +#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440) + +/* GPIO_SIG187_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG187_IN_SEL (BIT(7)) +#define GPIO_SIG187_IN_SEL_M (GPIO_SIG187_IN_SEL_V << GPIO_SIG187_IN_SEL_S) +#define GPIO_SIG187_IN_SEL_V 0x00000001 +#define GPIO_SIG187_IN_SEL_S 7 + +/* GPIO_FUNC187_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC187_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_M (GPIO_FUNC187_IN_INV_SEL_V << GPIO_FUNC187_IN_INV_SEL_S) +#define GPIO_FUNC187_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC187_IN_INV_SEL_S 6 + +/* GPIO_FUNC187_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC187_IN_SEL 0x0000003F +#define GPIO_FUNC187_IN_SEL_M (GPIO_FUNC187_IN_SEL_V << GPIO_FUNC187_IN_SEL_S) +#define GPIO_FUNC187_IN_SEL_V 0x0000003F +#define GPIO_FUNC187_IN_SEL_S 0 + +/* GPIO_FUNC188_IN_SEL_CFG_REG register + * Peripheral function 188 input selection register + */ + +#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444) + +/* GPIO_SIG188_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG188_IN_SEL (BIT(7)) +#define GPIO_SIG188_IN_SEL_M (GPIO_SIG188_IN_SEL_V << GPIO_SIG188_IN_SEL_S) +#define GPIO_SIG188_IN_SEL_V 0x00000001 +#define GPIO_SIG188_IN_SEL_S 7 + +/* GPIO_FUNC188_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC188_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_M (GPIO_FUNC188_IN_INV_SEL_V << GPIO_FUNC188_IN_INV_SEL_S) +#define GPIO_FUNC188_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC188_IN_INV_SEL_S 6 + +/* GPIO_FUNC188_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC188_IN_SEL 0x0000003F +#define GPIO_FUNC188_IN_SEL_M (GPIO_FUNC188_IN_SEL_V << GPIO_FUNC188_IN_SEL_S) +#define GPIO_FUNC188_IN_SEL_V 0x0000003F +#define GPIO_FUNC188_IN_SEL_S 0 + +/* GPIO_FUNC189_IN_SEL_CFG_REG register + * Peripheral function 189 input selection register + */ + +#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448) + +/* GPIO_SIG189_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG189_IN_SEL (BIT(7)) +#define GPIO_SIG189_IN_SEL_M (GPIO_SIG189_IN_SEL_V << GPIO_SIG189_IN_SEL_S) +#define GPIO_SIG189_IN_SEL_V 0x00000001 +#define GPIO_SIG189_IN_SEL_S 7 + +/* GPIO_FUNC189_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC189_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_M (GPIO_FUNC189_IN_INV_SEL_V << GPIO_FUNC189_IN_INV_SEL_S) +#define GPIO_FUNC189_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC189_IN_INV_SEL_S 6 + +/* GPIO_FUNC189_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC189_IN_SEL 0x0000003F +#define GPIO_FUNC189_IN_SEL_M (GPIO_FUNC189_IN_SEL_V << GPIO_FUNC189_IN_SEL_S) +#define GPIO_FUNC189_IN_SEL_V 0x0000003F +#define GPIO_FUNC189_IN_SEL_S 0 + +/* GPIO_FUNC190_IN_SEL_CFG_REG register + * Peripheral function 190 input selection register + */ + +#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c) + +/* GPIO_SIG190_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG190_IN_SEL (BIT(7)) +#define GPIO_SIG190_IN_SEL_M (GPIO_SIG190_IN_SEL_V << GPIO_SIG190_IN_SEL_S) +#define GPIO_SIG190_IN_SEL_V 0x00000001 +#define GPIO_SIG190_IN_SEL_S 7 + +/* GPIO_FUNC190_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC190_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_M (GPIO_FUNC190_IN_INV_SEL_V << GPIO_FUNC190_IN_INV_SEL_S) +#define GPIO_FUNC190_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC190_IN_INV_SEL_S 6 + +/* GPIO_FUNC190_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC190_IN_SEL 0x0000003F +#define GPIO_FUNC190_IN_SEL_M (GPIO_FUNC190_IN_SEL_V << GPIO_FUNC190_IN_SEL_S) +#define GPIO_FUNC190_IN_SEL_V 0x0000003F +#define GPIO_FUNC190_IN_SEL_S 0 + +/* GPIO_FUNC191_IN_SEL_CFG_REG register + * Peripheral function 191 input selection register + */ + +#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450) + +/* GPIO_SIG191_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG191_IN_SEL (BIT(7)) +#define GPIO_SIG191_IN_SEL_M (GPIO_SIG191_IN_SEL_V << GPIO_SIG191_IN_SEL_S) +#define GPIO_SIG191_IN_SEL_V 0x00000001 +#define GPIO_SIG191_IN_SEL_S 7 + +/* GPIO_FUNC191_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC191_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_M (GPIO_FUNC191_IN_INV_SEL_V << GPIO_FUNC191_IN_INV_SEL_S) +#define GPIO_FUNC191_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC191_IN_INV_SEL_S 6 + +/* GPIO_FUNC191_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC191_IN_SEL 0x0000003F +#define GPIO_FUNC191_IN_SEL_M (GPIO_FUNC191_IN_SEL_V << GPIO_FUNC191_IN_SEL_S) +#define GPIO_FUNC191_IN_SEL_V 0x0000003F +#define GPIO_FUNC191_IN_SEL_S 0 + +/* GPIO_FUNC192_IN_SEL_CFG_REG register + * Peripheral function 192 input selection register + */ + +#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454) + +/* GPIO_SIG192_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG192_IN_SEL (BIT(7)) +#define GPIO_SIG192_IN_SEL_M (GPIO_SIG192_IN_SEL_V << GPIO_SIG192_IN_SEL_S) +#define GPIO_SIG192_IN_SEL_V 0x00000001 +#define GPIO_SIG192_IN_SEL_S 7 + +/* GPIO_FUNC192_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC192_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_M (GPIO_FUNC192_IN_INV_SEL_V << GPIO_FUNC192_IN_INV_SEL_S) +#define GPIO_FUNC192_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC192_IN_INV_SEL_S 6 + +/* GPIO_FUNC192_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC192_IN_SEL 0x0000003F +#define GPIO_FUNC192_IN_SEL_M (GPIO_FUNC192_IN_SEL_V << GPIO_FUNC192_IN_SEL_S) +#define GPIO_FUNC192_IN_SEL_V 0x0000003F +#define GPIO_FUNC192_IN_SEL_S 0 + +/* GPIO_FUNC193_IN_SEL_CFG_REG register + * Peripheral function 193 input selection register + */ + +#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458) + +/* GPIO_SIG193_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG193_IN_SEL (BIT(7)) +#define GPIO_SIG193_IN_SEL_M (GPIO_SIG193_IN_SEL_V << GPIO_SIG193_IN_SEL_S) +#define GPIO_SIG193_IN_SEL_V 0x00000001 +#define GPIO_SIG193_IN_SEL_S 7 + +/* GPIO_FUNC193_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC193_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_M (GPIO_FUNC193_IN_INV_SEL_V << GPIO_FUNC193_IN_INV_SEL_S) +#define GPIO_FUNC193_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC193_IN_INV_SEL_S 6 + +/* GPIO_FUNC193_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC193_IN_SEL 0x0000003F +#define GPIO_FUNC193_IN_SEL_M (GPIO_FUNC193_IN_SEL_V << GPIO_FUNC193_IN_SEL_S) +#define GPIO_FUNC193_IN_SEL_V 0x0000003F +#define GPIO_FUNC193_IN_SEL_S 0 + +/* GPIO_FUNC194_IN_SEL_CFG_REG register + * Peripheral function 194 input selection register + */ + +#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c) + +/* GPIO_SIG194_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG194_IN_SEL (BIT(7)) +#define GPIO_SIG194_IN_SEL_M (GPIO_SIG194_IN_SEL_V << GPIO_SIG194_IN_SEL_S) +#define GPIO_SIG194_IN_SEL_V 0x00000001 +#define GPIO_SIG194_IN_SEL_S 7 + +/* GPIO_FUNC194_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC194_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_M (GPIO_FUNC194_IN_INV_SEL_V << GPIO_FUNC194_IN_INV_SEL_S) +#define GPIO_FUNC194_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC194_IN_INV_SEL_S 6 + +/* GPIO_FUNC194_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC194_IN_SEL 0x0000003F +#define GPIO_FUNC194_IN_SEL_M (GPIO_FUNC194_IN_SEL_V << GPIO_FUNC194_IN_SEL_S) +#define GPIO_FUNC194_IN_SEL_V 0x0000003F +#define GPIO_FUNC194_IN_SEL_S 0 + +/* GPIO_FUNC195_IN_SEL_CFG_REG register + * Peripheral function 195 input selection register + */ + +#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460) + +/* GPIO_SIG195_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG195_IN_SEL (BIT(7)) +#define GPIO_SIG195_IN_SEL_M (GPIO_SIG195_IN_SEL_V << GPIO_SIG195_IN_SEL_S) +#define GPIO_SIG195_IN_SEL_V 0x00000001 +#define GPIO_SIG195_IN_SEL_S 7 + +/* GPIO_FUNC195_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC195_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_M (GPIO_FUNC195_IN_INV_SEL_V << GPIO_FUNC195_IN_INV_SEL_S) +#define GPIO_FUNC195_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC195_IN_INV_SEL_S 6 + +/* GPIO_FUNC195_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC195_IN_SEL 0x0000003F +#define GPIO_FUNC195_IN_SEL_M (GPIO_FUNC195_IN_SEL_V << GPIO_FUNC195_IN_SEL_S) +#define GPIO_FUNC195_IN_SEL_V 0x0000003F +#define GPIO_FUNC195_IN_SEL_S 0 + +/* GPIO_FUNC196_IN_SEL_CFG_REG register + * Peripheral function 196 input selection register + */ + +#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464) + +/* GPIO_SIG196_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG196_IN_SEL (BIT(7)) +#define GPIO_SIG196_IN_SEL_M (GPIO_SIG196_IN_SEL_V << GPIO_SIG196_IN_SEL_S) +#define GPIO_SIG196_IN_SEL_V 0x00000001 +#define GPIO_SIG196_IN_SEL_S 7 + +/* GPIO_FUNC196_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC196_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_M (GPIO_FUNC196_IN_INV_SEL_V << GPIO_FUNC196_IN_INV_SEL_S) +#define GPIO_FUNC196_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC196_IN_INV_SEL_S 6 + +/* GPIO_FUNC196_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC196_IN_SEL 0x0000003F +#define GPIO_FUNC196_IN_SEL_M (GPIO_FUNC196_IN_SEL_V << GPIO_FUNC196_IN_SEL_S) +#define GPIO_FUNC196_IN_SEL_V 0x0000003F +#define GPIO_FUNC196_IN_SEL_S 0 + +/* GPIO_FUNC197_IN_SEL_CFG_REG register + * Peripheral function 197 input selection register + */ + +#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468) + +/* GPIO_SIG197_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG197_IN_SEL (BIT(7)) +#define GPIO_SIG197_IN_SEL_M (GPIO_SIG197_IN_SEL_V << GPIO_SIG197_IN_SEL_S) +#define GPIO_SIG197_IN_SEL_V 0x00000001 +#define GPIO_SIG197_IN_SEL_S 7 + +/* GPIO_FUNC197_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC197_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_M (GPIO_FUNC197_IN_INV_SEL_V << GPIO_FUNC197_IN_INV_SEL_S) +#define GPIO_FUNC197_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC197_IN_INV_SEL_S 6 + +/* GPIO_FUNC197_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC197_IN_SEL 0x0000003F +#define GPIO_FUNC197_IN_SEL_M (GPIO_FUNC197_IN_SEL_V << GPIO_FUNC197_IN_SEL_S) +#define GPIO_FUNC197_IN_SEL_V 0x0000003F +#define GPIO_FUNC197_IN_SEL_S 0 + +/* GPIO_FUNC198_IN_SEL_CFG_REG register + * Peripheral function 198 input selection register + */ + +#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c) + +/* GPIO_SIG198_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG198_IN_SEL (BIT(7)) +#define GPIO_SIG198_IN_SEL_M (GPIO_SIG198_IN_SEL_V << GPIO_SIG198_IN_SEL_S) +#define GPIO_SIG198_IN_SEL_V 0x00000001 +#define GPIO_SIG198_IN_SEL_S 7 + +/* GPIO_FUNC198_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC198_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_M (GPIO_FUNC198_IN_INV_SEL_V << GPIO_FUNC198_IN_INV_SEL_S) +#define GPIO_FUNC198_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC198_IN_INV_SEL_S 6 + +/* GPIO_FUNC198_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC198_IN_SEL 0x0000003F +#define GPIO_FUNC198_IN_SEL_M (GPIO_FUNC198_IN_SEL_V << GPIO_FUNC198_IN_SEL_S) +#define GPIO_FUNC198_IN_SEL_V 0x0000003F +#define GPIO_FUNC198_IN_SEL_S 0 + +/* GPIO_FUNC199_IN_SEL_CFG_REG register + * Peripheral function 199 input selection register + */ + +#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470) + +/* GPIO_SIG199_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG199_IN_SEL (BIT(7)) +#define GPIO_SIG199_IN_SEL_M (GPIO_SIG199_IN_SEL_V << GPIO_SIG199_IN_SEL_S) +#define GPIO_SIG199_IN_SEL_V 0x00000001 +#define GPIO_SIG199_IN_SEL_S 7 + +/* GPIO_FUNC199_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC199_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_M (GPIO_FUNC199_IN_INV_SEL_V << GPIO_FUNC199_IN_INV_SEL_S) +#define GPIO_FUNC199_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC199_IN_INV_SEL_S 6 + +/* GPIO_FUNC199_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC199_IN_SEL 0x0000003F +#define GPIO_FUNC199_IN_SEL_M (GPIO_FUNC199_IN_SEL_V << GPIO_FUNC199_IN_SEL_S) +#define GPIO_FUNC199_IN_SEL_V 0x0000003F +#define GPIO_FUNC199_IN_SEL_S 0 + +/* GPIO_FUNC200_IN_SEL_CFG_REG register + * Peripheral function 200 input selection register + */ + +#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474) + +/* GPIO_SIG200_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG200_IN_SEL (BIT(7)) +#define GPIO_SIG200_IN_SEL_M (GPIO_SIG200_IN_SEL_V << GPIO_SIG200_IN_SEL_S) +#define GPIO_SIG200_IN_SEL_V 0x00000001 +#define GPIO_SIG200_IN_SEL_S 7 + +/* GPIO_FUNC200_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC200_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_M (GPIO_FUNC200_IN_INV_SEL_V << GPIO_FUNC200_IN_INV_SEL_S) +#define GPIO_FUNC200_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC200_IN_INV_SEL_S 6 + +/* GPIO_FUNC200_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC200_IN_SEL 0x0000003F +#define GPIO_FUNC200_IN_SEL_M (GPIO_FUNC200_IN_SEL_V << GPIO_FUNC200_IN_SEL_S) +#define GPIO_FUNC200_IN_SEL_V 0x0000003F +#define GPIO_FUNC200_IN_SEL_S 0 + +/* GPIO_FUNC201_IN_SEL_CFG_REG register + * Peripheral function 201 input selection register + */ + +#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478) + +/* GPIO_SIG201_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG201_IN_SEL (BIT(7)) +#define GPIO_SIG201_IN_SEL_M (GPIO_SIG201_IN_SEL_V << GPIO_SIG201_IN_SEL_S) +#define GPIO_SIG201_IN_SEL_V 0x00000001 +#define GPIO_SIG201_IN_SEL_S 7 + +/* GPIO_FUNC201_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC201_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_M (GPIO_FUNC201_IN_INV_SEL_V << GPIO_FUNC201_IN_INV_SEL_S) +#define GPIO_FUNC201_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC201_IN_INV_SEL_S 6 + +/* GPIO_FUNC201_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC201_IN_SEL 0x0000003F +#define GPIO_FUNC201_IN_SEL_M (GPIO_FUNC201_IN_SEL_V << GPIO_FUNC201_IN_SEL_S) +#define GPIO_FUNC201_IN_SEL_V 0x0000003F +#define GPIO_FUNC201_IN_SEL_S 0 + +/* GPIO_FUNC202_IN_SEL_CFG_REG register + * Peripheral function 202 input selection register + */ + +#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c) + +/* GPIO_SIG202_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG202_IN_SEL (BIT(7)) +#define GPIO_SIG202_IN_SEL_M (GPIO_SIG202_IN_SEL_V << GPIO_SIG202_IN_SEL_S) +#define GPIO_SIG202_IN_SEL_V 0x00000001 +#define GPIO_SIG202_IN_SEL_S 7 + +/* GPIO_FUNC202_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC202_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_M (GPIO_FUNC202_IN_INV_SEL_V << GPIO_FUNC202_IN_INV_SEL_S) +#define GPIO_FUNC202_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC202_IN_INV_SEL_S 6 + +/* GPIO_FUNC202_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC202_IN_SEL 0x0000003F +#define GPIO_FUNC202_IN_SEL_M (GPIO_FUNC202_IN_SEL_V << GPIO_FUNC202_IN_SEL_S) +#define GPIO_FUNC202_IN_SEL_V 0x0000003F +#define GPIO_FUNC202_IN_SEL_S 0 + +/* GPIO_FUNC203_IN_SEL_CFG_REG register + * Peripheral function 203 input selection register + */ + +#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480) + +/* GPIO_SIG203_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG203_IN_SEL (BIT(7)) +#define GPIO_SIG203_IN_SEL_M (GPIO_SIG203_IN_SEL_V << GPIO_SIG203_IN_SEL_S) +#define GPIO_SIG203_IN_SEL_V 0x00000001 +#define GPIO_SIG203_IN_SEL_S 7 + +/* GPIO_FUNC203_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC203_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_M (GPIO_FUNC203_IN_INV_SEL_V << GPIO_FUNC203_IN_INV_SEL_S) +#define GPIO_FUNC203_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC203_IN_INV_SEL_S 6 + +/* GPIO_FUNC203_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC203_IN_SEL 0x0000003F +#define GPIO_FUNC203_IN_SEL_M (GPIO_FUNC203_IN_SEL_V << GPIO_FUNC203_IN_SEL_S) +#define GPIO_FUNC203_IN_SEL_V 0x0000003F +#define GPIO_FUNC203_IN_SEL_S 0 + +/* GPIO_FUNC204_IN_SEL_CFG_REG register + * Peripheral function 204 input selection register + */ + +#define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484) + +/* GPIO_SIG204_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG204_IN_SEL (BIT(7)) +#define GPIO_SIG204_IN_SEL_M (GPIO_SIG204_IN_SEL_V << GPIO_SIG204_IN_SEL_S) +#define GPIO_SIG204_IN_SEL_V 0x00000001 +#define GPIO_SIG204_IN_SEL_S 7 + +/* GPIO_FUNC204_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC204_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_M (GPIO_FUNC204_IN_INV_SEL_V << GPIO_FUNC204_IN_INV_SEL_S) +#define GPIO_FUNC204_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC204_IN_INV_SEL_S 6 + +/* GPIO_FUNC204_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC204_IN_SEL 0x0000003F +#define GPIO_FUNC204_IN_SEL_M (GPIO_FUNC204_IN_SEL_V << GPIO_FUNC204_IN_SEL_S) +#define GPIO_FUNC204_IN_SEL_V 0x0000003F +#define GPIO_FUNC204_IN_SEL_S 0 + +/* GPIO_FUNC205_IN_SEL_CFG_REG register + * Peripheral function 205 input selection register + */ + +#define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x488) + +/* GPIO_SIG205_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG205_IN_SEL (BIT(7)) +#define GPIO_SIG205_IN_SEL_M (GPIO_SIG205_IN_SEL_V << GPIO_SIG205_IN_SEL_S) +#define GPIO_SIG205_IN_SEL_V 0x00000001 +#define GPIO_SIG205_IN_SEL_S 7 + +/* GPIO_FUNC205_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC205_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_M (GPIO_FUNC205_IN_INV_SEL_V << GPIO_FUNC205_IN_INV_SEL_S) +#define GPIO_FUNC205_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC205_IN_INV_SEL_S 6 + +/* GPIO_FUNC205_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC205_IN_SEL 0x0000003F +#define GPIO_FUNC205_IN_SEL_M (GPIO_FUNC205_IN_SEL_V << GPIO_FUNC205_IN_SEL_S) +#define GPIO_FUNC205_IN_SEL_V 0x0000003F +#define GPIO_FUNC205_IN_SEL_S 0 + +/* GPIO_FUNC206_IN_SEL_CFG_REG register + * Peripheral function 206 input selection register + */ + +#define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x48c) + +/* GPIO_SIG206_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG206_IN_SEL (BIT(7)) +#define GPIO_SIG206_IN_SEL_M (GPIO_SIG206_IN_SEL_V << GPIO_SIG206_IN_SEL_S) +#define GPIO_SIG206_IN_SEL_V 0x00000001 +#define GPIO_SIG206_IN_SEL_S 7 + +/* GPIO_FUNC206_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC206_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_M (GPIO_FUNC206_IN_INV_SEL_V << GPIO_FUNC206_IN_INV_SEL_S) +#define GPIO_FUNC206_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC206_IN_INV_SEL_S 6 + +/* GPIO_FUNC206_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC206_IN_SEL 0x0000003F +#define GPIO_FUNC206_IN_SEL_M (GPIO_FUNC206_IN_SEL_V << GPIO_FUNC206_IN_SEL_S) +#define GPIO_FUNC206_IN_SEL_V 0x0000003F +#define GPIO_FUNC206_IN_SEL_S 0 + +/* GPIO_FUNC207_IN_SEL_CFG_REG register + * Peripheral function 207 input selection register + */ + +#define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x490) + +/* GPIO_SIG207_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG207_IN_SEL (BIT(7)) +#define GPIO_SIG207_IN_SEL_M (GPIO_SIG207_IN_SEL_V << GPIO_SIG207_IN_SEL_S) +#define GPIO_SIG207_IN_SEL_V 0x00000001 +#define GPIO_SIG207_IN_SEL_S 7 + +/* GPIO_FUNC207_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC207_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_M (GPIO_FUNC207_IN_INV_SEL_V << GPIO_FUNC207_IN_INV_SEL_S) +#define GPIO_FUNC207_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC207_IN_INV_SEL_S 6 + +/* GPIO_FUNC207_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC207_IN_SEL 0x0000003F +#define GPIO_FUNC207_IN_SEL_M (GPIO_FUNC207_IN_SEL_V << GPIO_FUNC207_IN_SEL_S) +#define GPIO_FUNC207_IN_SEL_V 0x0000003F +#define GPIO_FUNC207_IN_SEL_S 0 + +/* GPIO_FUNC208_IN_SEL_CFG_REG register + * Peripheral function 208 input selection register + */ + +#define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x494) + +/* GPIO_SIG208_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG208_IN_SEL (BIT(7)) +#define GPIO_SIG208_IN_SEL_M (GPIO_SIG208_IN_SEL_V << GPIO_SIG208_IN_SEL_S) +#define GPIO_SIG208_IN_SEL_V 0x00000001 +#define GPIO_SIG208_IN_SEL_S 7 + +/* GPIO_FUNC208_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC208_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_M (GPIO_FUNC208_IN_INV_SEL_V << GPIO_FUNC208_IN_INV_SEL_S) +#define GPIO_FUNC208_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC208_IN_INV_SEL_S 6 + +/* GPIO_FUNC208_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC208_IN_SEL 0x0000003F +#define GPIO_FUNC208_IN_SEL_M (GPIO_FUNC208_IN_SEL_V << GPIO_FUNC208_IN_SEL_S) +#define GPIO_FUNC208_IN_SEL_V 0x0000003F +#define GPIO_FUNC208_IN_SEL_S 0 + +/* GPIO_FUNC209_IN_SEL_CFG_REG register + * Peripheral function 209 input selection register + */ + +#define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x498) + +/* GPIO_SIG209_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG209_IN_SEL (BIT(7)) +#define GPIO_SIG209_IN_SEL_M (GPIO_SIG209_IN_SEL_V << GPIO_SIG209_IN_SEL_S) +#define GPIO_SIG209_IN_SEL_V 0x00000001 +#define GPIO_SIG209_IN_SEL_S 7 + +/* GPIO_FUNC209_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC209_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_M (GPIO_FUNC209_IN_INV_SEL_V << GPIO_FUNC209_IN_INV_SEL_S) +#define GPIO_FUNC209_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC209_IN_INV_SEL_S 6 + +/* GPIO_FUNC209_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC209_IN_SEL 0x0000003F +#define GPIO_FUNC209_IN_SEL_M (GPIO_FUNC209_IN_SEL_V << GPIO_FUNC209_IN_SEL_S) +#define GPIO_FUNC209_IN_SEL_V 0x0000003F +#define GPIO_FUNC209_IN_SEL_S 0 + +/* GPIO_FUNC210_IN_SEL_CFG_REG register + * Peripheral function 210 input selection register + */ + +#define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c) + +/* GPIO_SIG210_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG210_IN_SEL (BIT(7)) +#define GPIO_SIG210_IN_SEL_M (GPIO_SIG210_IN_SEL_V << GPIO_SIG210_IN_SEL_S) +#define GPIO_SIG210_IN_SEL_V 0x00000001 +#define GPIO_SIG210_IN_SEL_S 7 + +/* GPIO_FUNC210_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC210_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_M (GPIO_FUNC210_IN_INV_SEL_V << GPIO_FUNC210_IN_INV_SEL_S) +#define GPIO_FUNC210_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC210_IN_INV_SEL_S 6 + +/* GPIO_FUNC210_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC210_IN_SEL 0x0000003F +#define GPIO_FUNC210_IN_SEL_M (GPIO_FUNC210_IN_SEL_V << GPIO_FUNC210_IN_SEL_S) +#define GPIO_FUNC210_IN_SEL_V 0x0000003F +#define GPIO_FUNC210_IN_SEL_S 0 + +/* GPIO_FUNC211_IN_SEL_CFG_REG register + * Peripheral function 211 input selection register + */ + +#define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0) + +/* GPIO_SIG211_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG211_IN_SEL (BIT(7)) +#define GPIO_SIG211_IN_SEL_M (GPIO_SIG211_IN_SEL_V << GPIO_SIG211_IN_SEL_S) +#define GPIO_SIG211_IN_SEL_V 0x00000001 +#define GPIO_SIG211_IN_SEL_S 7 + +/* GPIO_FUNC211_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC211_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_M (GPIO_FUNC211_IN_INV_SEL_V << GPIO_FUNC211_IN_INV_SEL_S) +#define GPIO_FUNC211_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC211_IN_INV_SEL_S 6 + +/* GPIO_FUNC211_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC211_IN_SEL 0x0000003F +#define GPIO_FUNC211_IN_SEL_M (GPIO_FUNC211_IN_SEL_V << GPIO_FUNC211_IN_SEL_S) +#define GPIO_FUNC211_IN_SEL_V 0x0000003F +#define GPIO_FUNC211_IN_SEL_S 0 + +/* GPIO_FUNC212_IN_SEL_CFG_REG register + * Peripheral function 212 input selection register + */ + +#define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4) + +/* GPIO_SIG212_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG212_IN_SEL (BIT(7)) +#define GPIO_SIG212_IN_SEL_M (GPIO_SIG212_IN_SEL_V << GPIO_SIG212_IN_SEL_S) +#define GPIO_SIG212_IN_SEL_V 0x00000001 +#define GPIO_SIG212_IN_SEL_S 7 + +/* GPIO_FUNC212_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC212_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_M (GPIO_FUNC212_IN_INV_SEL_V << GPIO_FUNC212_IN_INV_SEL_S) +#define GPIO_FUNC212_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC212_IN_INV_SEL_S 6 + +/* GPIO_FUNC212_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC212_IN_SEL 0x0000003F +#define GPIO_FUNC212_IN_SEL_M (GPIO_FUNC212_IN_SEL_V << GPIO_FUNC212_IN_SEL_S) +#define GPIO_FUNC212_IN_SEL_V 0x0000003F +#define GPIO_FUNC212_IN_SEL_S 0 + +/* GPIO_FUNC213_IN_SEL_CFG_REG register + * Peripheral function 213 input selection register + */ + +#define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a8) + +/* GPIO_SIG213_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG213_IN_SEL (BIT(7)) +#define GPIO_SIG213_IN_SEL_M (GPIO_SIG213_IN_SEL_V << GPIO_SIG213_IN_SEL_S) +#define GPIO_SIG213_IN_SEL_V 0x00000001 +#define GPIO_SIG213_IN_SEL_S 7 + +/* GPIO_FUNC213_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC213_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_M (GPIO_FUNC213_IN_INV_SEL_V << GPIO_FUNC213_IN_INV_SEL_S) +#define GPIO_FUNC213_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC213_IN_INV_SEL_S 6 + +/* GPIO_FUNC213_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC213_IN_SEL 0x0000003F +#define GPIO_FUNC213_IN_SEL_M (GPIO_FUNC213_IN_SEL_V << GPIO_FUNC213_IN_SEL_S) +#define GPIO_FUNC213_IN_SEL_V 0x0000003F +#define GPIO_FUNC213_IN_SEL_S 0 + +/* GPIO_FUNC214_IN_SEL_CFG_REG register + * Peripheral function 214 input selection register + */ + +#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ac) + +/* GPIO_SIG214_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG214_IN_SEL (BIT(7)) +#define GPIO_SIG214_IN_SEL_M (GPIO_SIG214_IN_SEL_V << GPIO_SIG214_IN_SEL_S) +#define GPIO_SIG214_IN_SEL_V 0x00000001 +#define GPIO_SIG214_IN_SEL_S 7 + +/* GPIO_FUNC214_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC214_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_M (GPIO_FUNC214_IN_INV_SEL_V << GPIO_FUNC214_IN_INV_SEL_S) +#define GPIO_FUNC214_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC214_IN_INV_SEL_S 6 + +/* GPIO_FUNC214_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC214_IN_SEL 0x0000003F +#define GPIO_FUNC214_IN_SEL_M (GPIO_FUNC214_IN_SEL_V << GPIO_FUNC214_IN_SEL_S) +#define GPIO_FUNC214_IN_SEL_V 0x0000003F +#define GPIO_FUNC214_IN_SEL_S 0 + +/* GPIO_FUNC215_IN_SEL_CFG_REG register + * Peripheral function 215 input selection register + */ + +#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0) + +/* GPIO_SIG215_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG215_IN_SEL (BIT(7)) +#define GPIO_SIG215_IN_SEL_M (GPIO_SIG215_IN_SEL_V << GPIO_SIG215_IN_SEL_S) +#define GPIO_SIG215_IN_SEL_V 0x00000001 +#define GPIO_SIG215_IN_SEL_S 7 + +/* GPIO_FUNC215_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC215_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_M (GPIO_FUNC215_IN_INV_SEL_V << GPIO_FUNC215_IN_INV_SEL_S) +#define GPIO_FUNC215_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC215_IN_INV_SEL_S 6 + +/* GPIO_FUNC215_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC215_IN_SEL 0x0000003F +#define GPIO_FUNC215_IN_SEL_M (GPIO_FUNC215_IN_SEL_V << GPIO_FUNC215_IN_SEL_S) +#define GPIO_FUNC215_IN_SEL_V 0x0000003F +#define GPIO_FUNC215_IN_SEL_S 0 + +/* GPIO_FUNC216_IN_SEL_CFG_REG register + * Peripheral function 216 input selection register + */ + +#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4) + +/* GPIO_SIG216_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG216_IN_SEL (BIT(7)) +#define GPIO_SIG216_IN_SEL_M (GPIO_SIG216_IN_SEL_V << GPIO_SIG216_IN_SEL_S) +#define GPIO_SIG216_IN_SEL_V 0x00000001 +#define GPIO_SIG216_IN_SEL_S 7 + +/* GPIO_FUNC216_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC216_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_M (GPIO_FUNC216_IN_INV_SEL_V << GPIO_FUNC216_IN_INV_SEL_S) +#define GPIO_FUNC216_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC216_IN_INV_SEL_S 6 + +/* GPIO_FUNC216_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC216_IN_SEL 0x0000003F +#define GPIO_FUNC216_IN_SEL_M (GPIO_FUNC216_IN_SEL_V << GPIO_FUNC216_IN_SEL_S) +#define GPIO_FUNC216_IN_SEL_V 0x0000003F +#define GPIO_FUNC216_IN_SEL_S 0 + +/* GPIO_FUNC217_IN_SEL_CFG_REG register + * Peripheral function 217 input selection register + */ + +#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8) + +/* GPIO_SIG217_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG217_IN_SEL (BIT(7)) +#define GPIO_SIG217_IN_SEL_M (GPIO_SIG217_IN_SEL_V << GPIO_SIG217_IN_SEL_S) +#define GPIO_SIG217_IN_SEL_V 0x00000001 +#define GPIO_SIG217_IN_SEL_S 7 + +/* GPIO_FUNC217_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC217_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_M (GPIO_FUNC217_IN_INV_SEL_V << GPIO_FUNC217_IN_INV_SEL_S) +#define GPIO_FUNC217_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC217_IN_INV_SEL_S 6 + +/* GPIO_FUNC217_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC217_IN_SEL 0x0000003F +#define GPIO_FUNC217_IN_SEL_M (GPIO_FUNC217_IN_SEL_V << GPIO_FUNC217_IN_SEL_S) +#define GPIO_FUNC217_IN_SEL_V 0x0000003F +#define GPIO_FUNC217_IN_SEL_S 0 + +/* GPIO_FUNC218_IN_SEL_CFG_REG register + * Peripheral function 218 input selection register + */ + +#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4bc) + +/* GPIO_SIG218_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG218_IN_SEL (BIT(7)) +#define GPIO_SIG218_IN_SEL_M (GPIO_SIG218_IN_SEL_V << GPIO_SIG218_IN_SEL_S) +#define GPIO_SIG218_IN_SEL_V 0x00000001 +#define GPIO_SIG218_IN_SEL_S 7 + +/* GPIO_FUNC218_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC218_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_M (GPIO_FUNC218_IN_INV_SEL_V << GPIO_FUNC218_IN_INV_SEL_S) +#define GPIO_FUNC218_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC218_IN_INV_SEL_S 6 + +/* GPIO_FUNC218_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC218_IN_SEL 0x0000003F +#define GPIO_FUNC218_IN_SEL_M (GPIO_FUNC218_IN_SEL_V << GPIO_FUNC218_IN_SEL_S) +#define GPIO_FUNC218_IN_SEL_V 0x0000003F +#define GPIO_FUNC218_IN_SEL_S 0 + +/* GPIO_FUNC219_IN_SEL_CFG_REG register + * Peripheral function 219 input selection register + */ + +#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c0) + +/* GPIO_SIG219_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG219_IN_SEL (BIT(7)) +#define GPIO_SIG219_IN_SEL_M (GPIO_SIG219_IN_SEL_V << GPIO_SIG219_IN_SEL_S) +#define GPIO_SIG219_IN_SEL_V 0x00000001 +#define GPIO_SIG219_IN_SEL_S 7 + +/* GPIO_FUNC219_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC219_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_M (GPIO_FUNC219_IN_INV_SEL_V << GPIO_FUNC219_IN_INV_SEL_S) +#define GPIO_FUNC219_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC219_IN_INV_SEL_S 6 + +/* GPIO_FUNC219_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC219_IN_SEL 0x0000003F +#define GPIO_FUNC219_IN_SEL_M (GPIO_FUNC219_IN_SEL_V << GPIO_FUNC219_IN_SEL_S) +#define GPIO_FUNC219_IN_SEL_V 0x0000003F +#define GPIO_FUNC219_IN_SEL_S 0 + +/* GPIO_FUNC220_IN_SEL_CFG_REG register + * Peripheral function 220 input selection register + */ + +#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c4) + +/* GPIO_SIG220_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG220_IN_SEL (BIT(7)) +#define GPIO_SIG220_IN_SEL_M (GPIO_SIG220_IN_SEL_V << GPIO_SIG220_IN_SEL_S) +#define GPIO_SIG220_IN_SEL_V 0x00000001 +#define GPIO_SIG220_IN_SEL_S 7 + +/* GPIO_FUNC220_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC220_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_M (GPIO_FUNC220_IN_INV_SEL_V << GPIO_FUNC220_IN_INV_SEL_S) +#define GPIO_FUNC220_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC220_IN_INV_SEL_S 6 + +/* GPIO_FUNC220_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC220_IN_SEL 0x0000003F +#define GPIO_FUNC220_IN_SEL_M (GPIO_FUNC220_IN_SEL_V << GPIO_FUNC220_IN_SEL_S) +#define GPIO_FUNC220_IN_SEL_V 0x0000003F +#define GPIO_FUNC220_IN_SEL_S 0 + +/* GPIO_FUNC221_IN_SEL_CFG_REG register + * Peripheral function 221 input selection register + */ + +#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c8) + +/* GPIO_SIG221_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG221_IN_SEL (BIT(7)) +#define GPIO_SIG221_IN_SEL_M (GPIO_SIG221_IN_SEL_V << GPIO_SIG221_IN_SEL_S) +#define GPIO_SIG221_IN_SEL_V 0x00000001 +#define GPIO_SIG221_IN_SEL_S 7 + +/* GPIO_FUNC221_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC221_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_M (GPIO_FUNC221_IN_INV_SEL_V << GPIO_FUNC221_IN_INV_SEL_S) +#define GPIO_FUNC221_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC221_IN_INV_SEL_S 6 + +/* GPIO_FUNC221_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC221_IN_SEL 0x0000003F +#define GPIO_FUNC221_IN_SEL_M (GPIO_FUNC221_IN_SEL_V << GPIO_FUNC221_IN_SEL_S) +#define GPIO_FUNC221_IN_SEL_V 0x0000003F +#define GPIO_FUNC221_IN_SEL_S 0 + +/* GPIO_FUNC222_IN_SEL_CFG_REG register + * Peripheral function 222 input selection register + */ + +#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4cc) + +/* GPIO_SIG222_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG222_IN_SEL (BIT(7)) +#define GPIO_SIG222_IN_SEL_M (GPIO_SIG222_IN_SEL_V << GPIO_SIG222_IN_SEL_S) +#define GPIO_SIG222_IN_SEL_V 0x00000001 +#define GPIO_SIG222_IN_SEL_S 7 + +/* GPIO_FUNC222_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC222_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_M (GPIO_FUNC222_IN_INV_SEL_V << GPIO_FUNC222_IN_INV_SEL_S) +#define GPIO_FUNC222_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC222_IN_INV_SEL_S 6 + +/* GPIO_FUNC222_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC222_IN_SEL 0x0000003F +#define GPIO_FUNC222_IN_SEL_M (GPIO_FUNC222_IN_SEL_V << GPIO_FUNC222_IN_SEL_S) +#define GPIO_FUNC222_IN_SEL_V 0x0000003F +#define GPIO_FUNC222_IN_SEL_S 0 + +/* GPIO_FUNC223_IN_SEL_CFG_REG register + * Peripheral function 223 input selection register + */ + +#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d0) + +/* GPIO_SIG223_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG223_IN_SEL (BIT(7)) +#define GPIO_SIG223_IN_SEL_M (GPIO_SIG223_IN_SEL_V << GPIO_SIG223_IN_SEL_S) +#define GPIO_SIG223_IN_SEL_V 0x00000001 +#define GPIO_SIG223_IN_SEL_S 7 + +/* GPIO_FUNC223_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC223_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_M (GPIO_FUNC223_IN_INV_SEL_V << GPIO_FUNC223_IN_INV_SEL_S) +#define GPIO_FUNC223_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC223_IN_INV_SEL_S 6 + +/* GPIO_FUNC223_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC223_IN_SEL 0x0000003F +#define GPIO_FUNC223_IN_SEL_M (GPIO_FUNC223_IN_SEL_V << GPIO_FUNC223_IN_SEL_S) +#define GPIO_FUNC223_IN_SEL_V 0x0000003F +#define GPIO_FUNC223_IN_SEL_S 0 + +/* GPIO_FUNC224_IN_SEL_CFG_REG register + * Peripheral function 224 input selection register + */ + +#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d4) + +/* GPIO_SIG224_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG224_IN_SEL (BIT(7)) +#define GPIO_SIG224_IN_SEL_M (GPIO_SIG224_IN_SEL_V << GPIO_SIG224_IN_SEL_S) +#define GPIO_SIG224_IN_SEL_V 0x00000001 +#define GPIO_SIG224_IN_SEL_S 7 + +/* GPIO_FUNC224_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC224_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_M (GPIO_FUNC224_IN_INV_SEL_V << GPIO_FUNC224_IN_INV_SEL_S) +#define GPIO_FUNC224_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC224_IN_INV_SEL_S 6 + +/* GPIO_FUNC224_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC224_IN_SEL 0x0000003F +#define GPIO_FUNC224_IN_SEL_M (GPIO_FUNC224_IN_SEL_V << GPIO_FUNC224_IN_SEL_S) +#define GPIO_FUNC224_IN_SEL_V 0x0000003F +#define GPIO_FUNC224_IN_SEL_S 0 + +/* GPIO_FUNC225_IN_SEL_CFG_REG register + * Peripheral function 225 input selection register + */ + +#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d8) + +/* GPIO_SIG225_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG225_IN_SEL (BIT(7)) +#define GPIO_SIG225_IN_SEL_M (GPIO_SIG225_IN_SEL_V << GPIO_SIG225_IN_SEL_S) +#define GPIO_SIG225_IN_SEL_V 0x00000001 +#define GPIO_SIG225_IN_SEL_S 7 + +/* GPIO_FUNC225_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC225_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_M (GPIO_FUNC225_IN_INV_SEL_V << GPIO_FUNC225_IN_INV_SEL_S) +#define GPIO_FUNC225_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC225_IN_INV_SEL_S 6 + +/* GPIO_FUNC225_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC225_IN_SEL 0x0000003F +#define GPIO_FUNC225_IN_SEL_M (GPIO_FUNC225_IN_SEL_V << GPIO_FUNC225_IN_SEL_S) +#define GPIO_FUNC225_IN_SEL_V 0x0000003F +#define GPIO_FUNC225_IN_SEL_S 0 + +/* GPIO_FUNC226_IN_SEL_CFG_REG register + * Peripheral function 226 input selection register + */ + +#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4dc) + +/* GPIO_SIG226_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG226_IN_SEL (BIT(7)) +#define GPIO_SIG226_IN_SEL_M (GPIO_SIG226_IN_SEL_V << GPIO_SIG226_IN_SEL_S) +#define GPIO_SIG226_IN_SEL_V 0x00000001 +#define GPIO_SIG226_IN_SEL_S 7 + +/* GPIO_FUNC226_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC226_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_M (GPIO_FUNC226_IN_INV_SEL_V << GPIO_FUNC226_IN_INV_SEL_S) +#define GPIO_FUNC226_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC226_IN_INV_SEL_S 6 + +/* GPIO_FUNC226_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC226_IN_SEL 0x0000003F +#define GPIO_FUNC226_IN_SEL_M (GPIO_FUNC226_IN_SEL_V << GPIO_FUNC226_IN_SEL_S) +#define GPIO_FUNC226_IN_SEL_V 0x0000003F +#define GPIO_FUNC226_IN_SEL_S 0 + +/* GPIO_FUNC227_IN_SEL_CFG_REG register + * Peripheral function 227 input selection register + */ + +#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e0) + +/* GPIO_SIG227_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG227_IN_SEL (BIT(7)) +#define GPIO_SIG227_IN_SEL_M (GPIO_SIG227_IN_SEL_V << GPIO_SIG227_IN_SEL_S) +#define GPIO_SIG227_IN_SEL_V 0x00000001 +#define GPIO_SIG227_IN_SEL_S 7 + +/* GPIO_FUNC227_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC227_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_M (GPIO_FUNC227_IN_INV_SEL_V << GPIO_FUNC227_IN_INV_SEL_S) +#define GPIO_FUNC227_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC227_IN_INV_SEL_S 6 + +/* GPIO_FUNC227_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC227_IN_SEL 0x0000003F +#define GPIO_FUNC227_IN_SEL_M (GPIO_FUNC227_IN_SEL_V << GPIO_FUNC227_IN_SEL_S) +#define GPIO_FUNC227_IN_SEL_V 0x0000003F +#define GPIO_FUNC227_IN_SEL_S 0 + +/* GPIO_FUNC228_IN_SEL_CFG_REG register + * Peripheral function 228 input selection register + */ + +#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e4) + +/* GPIO_SIG228_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG228_IN_SEL (BIT(7)) +#define GPIO_SIG228_IN_SEL_M (GPIO_SIG228_IN_SEL_V << GPIO_SIG228_IN_SEL_S) +#define GPIO_SIG228_IN_SEL_V 0x00000001 +#define GPIO_SIG228_IN_SEL_S 7 + +/* GPIO_FUNC228_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC228_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_M (GPIO_FUNC228_IN_INV_SEL_V << GPIO_FUNC228_IN_INV_SEL_S) +#define GPIO_FUNC228_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC228_IN_INV_SEL_S 6 + +/* GPIO_FUNC228_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC228_IN_SEL 0x0000003F +#define GPIO_FUNC228_IN_SEL_M (GPIO_FUNC228_IN_SEL_V << GPIO_FUNC228_IN_SEL_S) +#define GPIO_FUNC228_IN_SEL_V 0x0000003F +#define GPIO_FUNC228_IN_SEL_S 0 + +/* GPIO_FUNC229_IN_SEL_CFG_REG register + * Peripheral function 229 input selection register + */ + +#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e8) + +/* GPIO_SIG229_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG229_IN_SEL (BIT(7)) +#define GPIO_SIG229_IN_SEL_M (GPIO_SIG229_IN_SEL_V << GPIO_SIG229_IN_SEL_S) +#define GPIO_SIG229_IN_SEL_V 0x00000001 +#define GPIO_SIG229_IN_SEL_S 7 + +/* GPIO_FUNC229_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC229_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_M (GPIO_FUNC229_IN_INV_SEL_V << GPIO_FUNC229_IN_INV_SEL_S) +#define GPIO_FUNC229_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC229_IN_INV_SEL_S 6 + +/* GPIO_FUNC229_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC229_IN_SEL 0x0000003F +#define GPIO_FUNC229_IN_SEL_M (GPIO_FUNC229_IN_SEL_V << GPIO_FUNC229_IN_SEL_S) +#define GPIO_FUNC229_IN_SEL_V 0x0000003F +#define GPIO_FUNC229_IN_SEL_S 0 + +/* GPIO_FUNC230_IN_SEL_CFG_REG register + * Peripheral function 230 input selection register + */ + +#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ec) + +/* GPIO_SIG230_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG230_IN_SEL (BIT(7)) +#define GPIO_SIG230_IN_SEL_M (GPIO_SIG230_IN_SEL_V << GPIO_SIG230_IN_SEL_S) +#define GPIO_SIG230_IN_SEL_V 0x00000001 +#define GPIO_SIG230_IN_SEL_S 7 + +/* GPIO_FUNC230_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC230_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_M (GPIO_FUNC230_IN_INV_SEL_V << GPIO_FUNC230_IN_INV_SEL_S) +#define GPIO_FUNC230_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC230_IN_INV_SEL_S 6 + +/* GPIO_FUNC230_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC230_IN_SEL 0x0000003F +#define GPIO_FUNC230_IN_SEL_M (GPIO_FUNC230_IN_SEL_V << GPIO_FUNC230_IN_SEL_S) +#define GPIO_FUNC230_IN_SEL_V 0x0000003F +#define GPIO_FUNC230_IN_SEL_S 0 + +/* GPIO_FUNC231_IN_SEL_CFG_REG register + * Peripheral function 231 input selection register + */ + +#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f0) + +/* GPIO_SIG231_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG231_IN_SEL (BIT(7)) +#define GPIO_SIG231_IN_SEL_M (GPIO_SIG231_IN_SEL_V << GPIO_SIG231_IN_SEL_S) +#define GPIO_SIG231_IN_SEL_V 0x00000001 +#define GPIO_SIG231_IN_SEL_S 7 + +/* GPIO_FUNC231_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC231_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_M (GPIO_FUNC231_IN_INV_SEL_V << GPIO_FUNC231_IN_INV_SEL_S) +#define GPIO_FUNC231_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC231_IN_INV_SEL_S 6 + +/* GPIO_FUNC231_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC231_IN_SEL 0x0000003F +#define GPIO_FUNC231_IN_SEL_M (GPIO_FUNC231_IN_SEL_V << GPIO_FUNC231_IN_SEL_S) +#define GPIO_FUNC231_IN_SEL_V 0x0000003F +#define GPIO_FUNC231_IN_SEL_S 0 + +/* GPIO_FUNC232_IN_SEL_CFG_REG register + * Peripheral function 232 input selection register + */ + +#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f4) + +/* GPIO_SIG232_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG232_IN_SEL (BIT(7)) +#define GPIO_SIG232_IN_SEL_M (GPIO_SIG232_IN_SEL_V << GPIO_SIG232_IN_SEL_S) +#define GPIO_SIG232_IN_SEL_V 0x00000001 +#define GPIO_SIG232_IN_SEL_S 7 + +/* GPIO_FUNC232_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC232_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_M (GPIO_FUNC232_IN_INV_SEL_V << GPIO_FUNC232_IN_INV_SEL_S) +#define GPIO_FUNC232_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC232_IN_INV_SEL_S 6 + +/* GPIO_FUNC232_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC232_IN_SEL 0x0000003F +#define GPIO_FUNC232_IN_SEL_M (GPIO_FUNC232_IN_SEL_V << GPIO_FUNC232_IN_SEL_S) +#define GPIO_FUNC232_IN_SEL_V 0x0000003F +#define GPIO_FUNC232_IN_SEL_S 0 + +/* GPIO_FUNC233_IN_SEL_CFG_REG register + * Peripheral function 233 input selection register + */ + +#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f8) + +/* GPIO_SIG233_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG233_IN_SEL (BIT(7)) +#define GPIO_SIG233_IN_SEL_M (GPIO_SIG233_IN_SEL_V << GPIO_SIG233_IN_SEL_S) +#define GPIO_SIG233_IN_SEL_V 0x00000001 +#define GPIO_SIG233_IN_SEL_S 7 + +/* GPIO_FUNC233_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC233_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_M (GPIO_FUNC233_IN_INV_SEL_V << GPIO_FUNC233_IN_INV_SEL_S) +#define GPIO_FUNC233_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC233_IN_INV_SEL_S 6 + +/* GPIO_FUNC233_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC233_IN_SEL 0x0000003F +#define GPIO_FUNC233_IN_SEL_M (GPIO_FUNC233_IN_SEL_V << GPIO_FUNC233_IN_SEL_S) +#define GPIO_FUNC233_IN_SEL_V 0x0000003F +#define GPIO_FUNC233_IN_SEL_S 0 + +/* GPIO_FUNC234_IN_SEL_CFG_REG register + * Peripheral function 234 input selection register + */ + +#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4fc) + +/* GPIO_SIG234_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG234_IN_SEL (BIT(7)) +#define GPIO_SIG234_IN_SEL_M (GPIO_SIG234_IN_SEL_V << GPIO_SIG234_IN_SEL_S) +#define GPIO_SIG234_IN_SEL_V 0x00000001 +#define GPIO_SIG234_IN_SEL_S 7 + +/* GPIO_FUNC234_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC234_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_M (GPIO_FUNC234_IN_INV_SEL_V << GPIO_FUNC234_IN_INV_SEL_S) +#define GPIO_FUNC234_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC234_IN_INV_SEL_S 6 + +/* GPIO_FUNC234_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC234_IN_SEL 0x0000003F +#define GPIO_FUNC234_IN_SEL_M (GPIO_FUNC234_IN_SEL_V << GPIO_FUNC234_IN_SEL_S) +#define GPIO_FUNC234_IN_SEL_V 0x0000003F +#define GPIO_FUNC234_IN_SEL_S 0 + +/* GPIO_FUNC235_IN_SEL_CFG_REG register + * Peripheral function 235 input selection register + */ + +#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x500) + +/* GPIO_SIG235_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG235_IN_SEL (BIT(7)) +#define GPIO_SIG235_IN_SEL_M (GPIO_SIG235_IN_SEL_V << GPIO_SIG235_IN_SEL_S) +#define GPIO_SIG235_IN_SEL_V 0x00000001 +#define GPIO_SIG235_IN_SEL_S 7 + +/* GPIO_FUNC235_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC235_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_M (GPIO_FUNC235_IN_INV_SEL_V << GPIO_FUNC235_IN_INV_SEL_S) +#define GPIO_FUNC235_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC235_IN_INV_SEL_S 6 + +/* GPIO_FUNC235_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC235_IN_SEL 0x0000003F +#define GPIO_FUNC235_IN_SEL_M (GPIO_FUNC235_IN_SEL_V << GPIO_FUNC235_IN_SEL_S) +#define GPIO_FUNC235_IN_SEL_V 0x0000003F +#define GPIO_FUNC235_IN_SEL_S 0 + +/* GPIO_FUNC236_IN_SEL_CFG_REG register + * Peripheral function 236 input selection register + */ + +#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x504) + +/* GPIO_SIG236_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG236_IN_SEL (BIT(7)) +#define GPIO_SIG236_IN_SEL_M (GPIO_SIG236_IN_SEL_V << GPIO_SIG236_IN_SEL_S) +#define GPIO_SIG236_IN_SEL_V 0x00000001 +#define GPIO_SIG236_IN_SEL_S 7 + +/* GPIO_FUNC236_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC236_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_M (GPIO_FUNC236_IN_INV_SEL_V << GPIO_FUNC236_IN_INV_SEL_S) +#define GPIO_FUNC236_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC236_IN_INV_SEL_S 6 + +/* GPIO_FUNC236_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC236_IN_SEL 0x0000003F +#define GPIO_FUNC236_IN_SEL_M (GPIO_FUNC236_IN_SEL_V << GPIO_FUNC236_IN_SEL_S) +#define GPIO_FUNC236_IN_SEL_V 0x0000003F +#define GPIO_FUNC236_IN_SEL_S 0 + +/* GPIO_FUNC237_IN_SEL_CFG_REG register + * Peripheral function 237 input selection register + */ + +#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x508) + +/* GPIO_SIG237_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG237_IN_SEL (BIT(7)) +#define GPIO_SIG237_IN_SEL_M (GPIO_SIG237_IN_SEL_V << GPIO_SIG237_IN_SEL_S) +#define GPIO_SIG237_IN_SEL_V 0x00000001 +#define GPIO_SIG237_IN_SEL_S 7 + +/* GPIO_FUNC237_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC237_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_M (GPIO_FUNC237_IN_INV_SEL_V << GPIO_FUNC237_IN_INV_SEL_S) +#define GPIO_FUNC237_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC237_IN_INV_SEL_S 6 + +/* GPIO_FUNC237_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC237_IN_SEL 0x0000003F +#define GPIO_FUNC237_IN_SEL_M (GPIO_FUNC237_IN_SEL_V << GPIO_FUNC237_IN_SEL_S) +#define GPIO_FUNC237_IN_SEL_V 0x0000003F +#define GPIO_FUNC237_IN_SEL_S 0 + +/* GPIO_FUNC238_IN_SEL_CFG_REG register + * Peripheral function 238 input selection register + */ + +#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x50c) + +/* GPIO_SIG238_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG238_IN_SEL (BIT(7)) +#define GPIO_SIG238_IN_SEL_M (GPIO_SIG238_IN_SEL_V << GPIO_SIG238_IN_SEL_S) +#define GPIO_SIG238_IN_SEL_V 0x00000001 +#define GPIO_SIG238_IN_SEL_S 7 + +/* GPIO_FUNC238_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC238_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_M (GPIO_FUNC238_IN_INV_SEL_V << GPIO_FUNC238_IN_INV_SEL_S) +#define GPIO_FUNC238_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC238_IN_INV_SEL_S 6 + +/* GPIO_FUNC238_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC238_IN_SEL 0x0000003F +#define GPIO_FUNC238_IN_SEL_M (GPIO_FUNC238_IN_SEL_V << GPIO_FUNC238_IN_SEL_S) +#define GPIO_FUNC238_IN_SEL_V 0x0000003F +#define GPIO_FUNC238_IN_SEL_S 0 + +/* GPIO_FUNC239_IN_SEL_CFG_REG register + * Peripheral function 239 input selection register + */ + +#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x510) + +/* GPIO_SIG239_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG239_IN_SEL (BIT(7)) +#define GPIO_SIG239_IN_SEL_M (GPIO_SIG239_IN_SEL_V << GPIO_SIG239_IN_SEL_S) +#define GPIO_SIG239_IN_SEL_V 0x00000001 +#define GPIO_SIG239_IN_SEL_S 7 + +/* GPIO_FUNC239_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC239_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_M (GPIO_FUNC239_IN_INV_SEL_V << GPIO_FUNC239_IN_INV_SEL_S) +#define GPIO_FUNC239_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC239_IN_INV_SEL_S 6 + +/* GPIO_FUNC239_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC239_IN_SEL 0x0000003F +#define GPIO_FUNC239_IN_SEL_M (GPIO_FUNC239_IN_SEL_V << GPIO_FUNC239_IN_SEL_S) +#define GPIO_FUNC239_IN_SEL_V 0x0000003F +#define GPIO_FUNC239_IN_SEL_S 0 + +/* GPIO_FUNC240_IN_SEL_CFG_REG register + * Peripheral function 240 input selection register + */ + +#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x514) + +/* GPIO_SIG240_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG240_IN_SEL (BIT(7)) +#define GPIO_SIG240_IN_SEL_M (GPIO_SIG240_IN_SEL_V << GPIO_SIG240_IN_SEL_S) +#define GPIO_SIG240_IN_SEL_V 0x00000001 +#define GPIO_SIG240_IN_SEL_S 7 + +/* GPIO_FUNC240_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC240_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_M (GPIO_FUNC240_IN_INV_SEL_V << GPIO_FUNC240_IN_INV_SEL_S) +#define GPIO_FUNC240_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC240_IN_INV_SEL_S 6 + +/* GPIO_FUNC240_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC240_IN_SEL 0x0000003F +#define GPIO_FUNC240_IN_SEL_M (GPIO_FUNC240_IN_SEL_V << GPIO_FUNC240_IN_SEL_S) +#define GPIO_FUNC240_IN_SEL_V 0x0000003F +#define GPIO_FUNC240_IN_SEL_S 0 + +/* GPIO_FUNC241_IN_SEL_CFG_REG register + * Peripheral function 241 input selection register + */ + +#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x518) + +/* GPIO_SIG241_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG241_IN_SEL (BIT(7)) +#define GPIO_SIG241_IN_SEL_M (GPIO_SIG241_IN_SEL_V << GPIO_SIG241_IN_SEL_S) +#define GPIO_SIG241_IN_SEL_V 0x00000001 +#define GPIO_SIG241_IN_SEL_S 7 + +/* GPIO_FUNC241_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC241_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_M (GPIO_FUNC241_IN_INV_SEL_V << GPIO_FUNC241_IN_INV_SEL_S) +#define GPIO_FUNC241_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC241_IN_INV_SEL_S 6 + +/* GPIO_FUNC241_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC241_IN_SEL 0x0000003F +#define GPIO_FUNC241_IN_SEL_M (GPIO_FUNC241_IN_SEL_V << GPIO_FUNC241_IN_SEL_S) +#define GPIO_FUNC241_IN_SEL_V 0x0000003F +#define GPIO_FUNC241_IN_SEL_S 0 + +/* GPIO_FUNC242_IN_SEL_CFG_REG register + * Peripheral function 242 input selection register + */ + +#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x51c) + +/* GPIO_SIG242_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG242_IN_SEL (BIT(7)) +#define GPIO_SIG242_IN_SEL_M (GPIO_SIG242_IN_SEL_V << GPIO_SIG242_IN_SEL_S) +#define GPIO_SIG242_IN_SEL_V 0x00000001 +#define GPIO_SIG242_IN_SEL_S 7 + +/* GPIO_FUNC242_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC242_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_M (GPIO_FUNC242_IN_INV_SEL_V << GPIO_FUNC242_IN_INV_SEL_S) +#define GPIO_FUNC242_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC242_IN_INV_SEL_S 6 + +/* GPIO_FUNC242_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC242_IN_SEL 0x0000003F +#define GPIO_FUNC242_IN_SEL_M (GPIO_FUNC242_IN_SEL_V << GPIO_FUNC242_IN_SEL_S) +#define GPIO_FUNC242_IN_SEL_V 0x0000003F +#define GPIO_FUNC242_IN_SEL_S 0 + +/* GPIO_FUNC243_IN_SEL_CFG_REG register + * Peripheral function 243 input selection register + */ + +#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x520) + +/* GPIO_SIG243_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG243_IN_SEL (BIT(7)) +#define GPIO_SIG243_IN_SEL_M (GPIO_SIG243_IN_SEL_V << GPIO_SIG243_IN_SEL_S) +#define GPIO_SIG243_IN_SEL_V 0x00000001 +#define GPIO_SIG243_IN_SEL_S 7 + +/* GPIO_FUNC243_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC243_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_M (GPIO_FUNC243_IN_INV_SEL_V << GPIO_FUNC243_IN_INV_SEL_S) +#define GPIO_FUNC243_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC243_IN_INV_SEL_S 6 + +/* GPIO_FUNC243_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC243_IN_SEL 0x0000003F +#define GPIO_FUNC243_IN_SEL_M (GPIO_FUNC243_IN_SEL_V << GPIO_FUNC243_IN_SEL_S) +#define GPIO_FUNC243_IN_SEL_V 0x0000003F +#define GPIO_FUNC243_IN_SEL_S 0 + +/* GPIO_FUNC244_IN_SEL_CFG_REG register + * Peripheral function 244 input selection register + */ + +#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x524) + +/* GPIO_SIG244_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG244_IN_SEL (BIT(7)) +#define GPIO_SIG244_IN_SEL_M (GPIO_SIG244_IN_SEL_V << GPIO_SIG244_IN_SEL_S) +#define GPIO_SIG244_IN_SEL_V 0x00000001 +#define GPIO_SIG244_IN_SEL_S 7 + +/* GPIO_FUNC244_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC244_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_M (GPIO_FUNC244_IN_INV_SEL_V << GPIO_FUNC244_IN_INV_SEL_S) +#define GPIO_FUNC244_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC244_IN_INV_SEL_S 6 + +/* GPIO_FUNC244_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC244_IN_SEL 0x0000003F +#define GPIO_FUNC244_IN_SEL_M (GPIO_FUNC244_IN_SEL_V << GPIO_FUNC244_IN_SEL_S) +#define GPIO_FUNC244_IN_SEL_V 0x0000003F +#define GPIO_FUNC244_IN_SEL_S 0 + +/* GPIO_FUNC245_IN_SEL_CFG_REG register + * Peripheral function 245 input selection register + */ + +#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x528) + +/* GPIO_SIG245_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG245_IN_SEL (BIT(7)) +#define GPIO_SIG245_IN_SEL_M (GPIO_SIG245_IN_SEL_V << GPIO_SIG245_IN_SEL_S) +#define GPIO_SIG245_IN_SEL_V 0x00000001 +#define GPIO_SIG245_IN_SEL_S 7 + +/* GPIO_FUNC245_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC245_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_M (GPIO_FUNC245_IN_INV_SEL_V << GPIO_FUNC245_IN_INV_SEL_S) +#define GPIO_FUNC245_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC245_IN_INV_SEL_S 6 + +/* GPIO_FUNC245_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC245_IN_SEL 0x0000003F +#define GPIO_FUNC245_IN_SEL_M (GPIO_FUNC245_IN_SEL_V << GPIO_FUNC245_IN_SEL_S) +#define GPIO_FUNC245_IN_SEL_V 0x0000003F +#define GPIO_FUNC245_IN_SEL_S 0 + +/* GPIO_FUNC246_IN_SEL_CFG_REG register + * Peripheral function 246 input selection register + */ + +#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x52c) + +/* GPIO_SIG246_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG246_IN_SEL (BIT(7)) +#define GPIO_SIG246_IN_SEL_M (GPIO_SIG246_IN_SEL_V << GPIO_SIG246_IN_SEL_S) +#define GPIO_SIG246_IN_SEL_V 0x00000001 +#define GPIO_SIG246_IN_SEL_S 7 + +/* GPIO_FUNC246_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC246_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_M (GPIO_FUNC246_IN_INV_SEL_V << GPIO_FUNC246_IN_INV_SEL_S) +#define GPIO_FUNC246_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC246_IN_INV_SEL_S 6 + +/* GPIO_FUNC246_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC246_IN_SEL 0x0000003F +#define GPIO_FUNC246_IN_SEL_M (GPIO_FUNC246_IN_SEL_V << GPIO_FUNC246_IN_SEL_S) +#define GPIO_FUNC246_IN_SEL_V 0x0000003F +#define GPIO_FUNC246_IN_SEL_S 0 + +/* GPIO_FUNC247_IN_SEL_CFG_REG register + * Peripheral function 247 input selection register + */ + +#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x530) + +/* GPIO_SIG247_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG247_IN_SEL (BIT(7)) +#define GPIO_SIG247_IN_SEL_M (GPIO_SIG247_IN_SEL_V << GPIO_SIG247_IN_SEL_S) +#define GPIO_SIG247_IN_SEL_V 0x00000001 +#define GPIO_SIG247_IN_SEL_S 7 + +/* GPIO_FUNC247_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC247_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_M (GPIO_FUNC247_IN_INV_SEL_V << GPIO_FUNC247_IN_INV_SEL_S) +#define GPIO_FUNC247_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC247_IN_INV_SEL_S 6 + +/* GPIO_FUNC247_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC247_IN_SEL 0x0000003F +#define GPIO_FUNC247_IN_SEL_M (GPIO_FUNC247_IN_SEL_V << GPIO_FUNC247_IN_SEL_S) +#define GPIO_FUNC247_IN_SEL_V 0x0000003F +#define GPIO_FUNC247_IN_SEL_S 0 + +/* GPIO_FUNC248_IN_SEL_CFG_REG register + * Peripheral function 248 input selection register + */ + +#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x534) + +/* GPIO_SIG248_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG248_IN_SEL (BIT(7)) +#define GPIO_SIG248_IN_SEL_M (GPIO_SIG248_IN_SEL_V << GPIO_SIG248_IN_SEL_S) +#define GPIO_SIG248_IN_SEL_V 0x00000001 +#define GPIO_SIG248_IN_SEL_S 7 + +/* GPIO_FUNC248_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC248_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_M (GPIO_FUNC248_IN_INV_SEL_V << GPIO_FUNC248_IN_INV_SEL_S) +#define GPIO_FUNC248_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC248_IN_INV_SEL_S 6 + +/* GPIO_FUNC248_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC248_IN_SEL 0x0000003F +#define GPIO_FUNC248_IN_SEL_M (GPIO_FUNC248_IN_SEL_V << GPIO_FUNC248_IN_SEL_S) +#define GPIO_FUNC248_IN_SEL_V 0x0000003F +#define GPIO_FUNC248_IN_SEL_S 0 + +/* GPIO_FUNC249_IN_SEL_CFG_REG register + * Peripheral function 249 input selection register + */ + +#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x538) + +/* GPIO_SIG249_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG249_IN_SEL (BIT(7)) +#define GPIO_SIG249_IN_SEL_M (GPIO_SIG249_IN_SEL_V << GPIO_SIG249_IN_SEL_S) +#define GPIO_SIG249_IN_SEL_V 0x00000001 +#define GPIO_SIG249_IN_SEL_S 7 + +/* GPIO_FUNC249_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC249_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_M (GPIO_FUNC249_IN_INV_SEL_V << GPIO_FUNC249_IN_INV_SEL_S) +#define GPIO_FUNC249_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC249_IN_INV_SEL_S 6 + +/* GPIO_FUNC249_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC249_IN_SEL 0x0000003F +#define GPIO_FUNC249_IN_SEL_M (GPIO_FUNC249_IN_SEL_V << GPIO_FUNC249_IN_SEL_S) +#define GPIO_FUNC249_IN_SEL_V 0x0000003F +#define GPIO_FUNC249_IN_SEL_S 0 + +/* GPIO_FUNC250_IN_SEL_CFG_REG register + * Peripheral function 250 input selection register + */ + +#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x53c) + +/* GPIO_SIG250_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG250_IN_SEL (BIT(7)) +#define GPIO_SIG250_IN_SEL_M (GPIO_SIG250_IN_SEL_V << GPIO_SIG250_IN_SEL_S) +#define GPIO_SIG250_IN_SEL_V 0x00000001 +#define GPIO_SIG250_IN_SEL_S 7 + +/* GPIO_FUNC250_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC250_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_M (GPIO_FUNC250_IN_INV_SEL_V << GPIO_FUNC250_IN_INV_SEL_S) +#define GPIO_FUNC250_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC250_IN_INV_SEL_S 6 + +/* GPIO_FUNC250_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC250_IN_SEL 0x0000003F +#define GPIO_FUNC250_IN_SEL_M (GPIO_FUNC250_IN_SEL_V << GPIO_FUNC250_IN_SEL_S) +#define GPIO_FUNC250_IN_SEL_V 0x0000003F +#define GPIO_FUNC250_IN_SEL_S 0 + +/* GPIO_FUNC251_IN_SEL_CFG_REG register + * Peripheral function 251 input selection register + */ + +#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x540) + +/* GPIO_SIG251_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG251_IN_SEL (BIT(7)) +#define GPIO_SIG251_IN_SEL_M (GPIO_SIG251_IN_SEL_V << GPIO_SIG251_IN_SEL_S) +#define GPIO_SIG251_IN_SEL_V 0x00000001 +#define GPIO_SIG251_IN_SEL_S 7 + +/* GPIO_FUNC251_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC251_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_M (GPIO_FUNC251_IN_INV_SEL_V << GPIO_FUNC251_IN_INV_SEL_S) +#define GPIO_FUNC251_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC251_IN_INV_SEL_S 6 + +/* GPIO_FUNC251_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC251_IN_SEL 0x0000003F +#define GPIO_FUNC251_IN_SEL_M (GPIO_FUNC251_IN_SEL_V << GPIO_FUNC251_IN_SEL_S) +#define GPIO_FUNC251_IN_SEL_V 0x0000003F +#define GPIO_FUNC251_IN_SEL_S 0 + +/* GPIO_FUNC252_IN_SEL_CFG_REG register + * Peripheral function 252 input selection register + */ + +#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x544) + +/* GPIO_SIG252_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG252_IN_SEL (BIT(7)) +#define GPIO_SIG252_IN_SEL_M (GPIO_SIG252_IN_SEL_V << GPIO_SIG252_IN_SEL_S) +#define GPIO_SIG252_IN_SEL_V 0x00000001 +#define GPIO_SIG252_IN_SEL_S 7 + +/* GPIO_FUNC252_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC252_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_M (GPIO_FUNC252_IN_INV_SEL_V << GPIO_FUNC252_IN_INV_SEL_S) +#define GPIO_FUNC252_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC252_IN_INV_SEL_S 6 + +/* GPIO_FUNC252_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC252_IN_SEL 0x0000003F +#define GPIO_FUNC252_IN_SEL_M (GPIO_FUNC252_IN_SEL_V << GPIO_FUNC252_IN_SEL_S) +#define GPIO_FUNC252_IN_SEL_V 0x0000003F +#define GPIO_FUNC252_IN_SEL_S 0 + +/* GPIO_FUNC253_IN_SEL_CFG_REG register + * Peripheral function 253 input selection register + */ + +#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x548) + +/* GPIO_SIG253_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG253_IN_SEL (BIT(7)) +#define GPIO_SIG253_IN_SEL_M (GPIO_SIG253_IN_SEL_V << GPIO_SIG253_IN_SEL_S) +#define GPIO_SIG253_IN_SEL_V 0x00000001 +#define GPIO_SIG253_IN_SEL_S 7 + +/* GPIO_FUNC253_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC253_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_M (GPIO_FUNC253_IN_INV_SEL_V << GPIO_FUNC253_IN_INV_SEL_S) +#define GPIO_FUNC253_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC253_IN_INV_SEL_S 6 + +/* GPIO_FUNC253_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC253_IN_SEL 0x0000003F +#define GPIO_FUNC253_IN_SEL_M (GPIO_FUNC253_IN_SEL_V << GPIO_FUNC253_IN_SEL_S) +#define GPIO_FUNC253_IN_SEL_V 0x0000003F +#define GPIO_FUNC253_IN_SEL_S 0 + +/* GPIO_FUNC254_IN_SEL_CFG_REG register + * Peripheral function 254 input selection register + */ + +#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x54c) + +/* GPIO_SIG254_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG254_IN_SEL (BIT(7)) +#define GPIO_SIG254_IN_SEL_M (GPIO_SIG254_IN_SEL_V << GPIO_SIG254_IN_SEL_S) +#define GPIO_SIG254_IN_SEL_V 0x00000001 +#define GPIO_SIG254_IN_SEL_S 7 + +/* GPIO_FUNC254_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC254_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_M (GPIO_FUNC254_IN_INV_SEL_V << GPIO_FUNC254_IN_INV_SEL_S) +#define GPIO_FUNC254_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC254_IN_INV_SEL_S 6 + +/* GPIO_FUNC254_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC254_IN_SEL 0x0000003F +#define GPIO_FUNC254_IN_SEL_M (GPIO_FUNC254_IN_SEL_V << GPIO_FUNC254_IN_SEL_S) +#define GPIO_FUNC254_IN_SEL_V 0x0000003F +#define GPIO_FUNC254_IN_SEL_S 0 + +/* GPIO_FUNC255_IN_SEL_CFG_REG register + * Peripheral function 255 input selection register + */ + +#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x550) + +/* GPIO_SIG255_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG255_IN_SEL (BIT(7)) +#define GPIO_SIG255_IN_SEL_M (GPIO_SIG255_IN_SEL_V << GPIO_SIG255_IN_SEL_S) +#define GPIO_SIG255_IN_SEL_V 0x00000001 +#define GPIO_SIG255_IN_SEL_S 7 + +/* GPIO_FUNC255_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC255_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_M (GPIO_FUNC255_IN_INV_SEL_V << GPIO_FUNC255_IN_INV_SEL_S) +#define GPIO_FUNC255_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC255_IN_INV_SEL_S 6 + +/* GPIO_FUNC255_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC255_IN_SEL 0x0000003F +#define GPIO_FUNC255_IN_SEL_M (GPIO_FUNC255_IN_SEL_V << GPIO_FUNC255_IN_SEL_S) +#define GPIO_FUNC255_IN_SEL_V 0x0000003F +#define GPIO_FUNC255_IN_SEL_S 0 + +/* GPIO_FUNC0_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 0 + */ + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) + +/* GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC0_OEN_INV_SEL_S 11 + +/* GPIO_FUNC0_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC0_OEN_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) +#define GPIO_FUNC0_OEN_SEL_V 0x00000001 +#define GPIO_FUNC0_OEN_SEL_S 10 + +/* GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC0_OUT_INV_SEL_S 9 + +/* GPIO_FUNC0_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC0_OUT_SEL 0x000001FF +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000001FF +#define GPIO_FUNC0_OUT_SEL_S 0 + +/* GPIO_FUNC1_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 1 + */ + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) + +/* GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC1_OEN_INV_SEL_S 11 + +/* GPIO_FUNC1_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC1_OEN_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) +#define GPIO_FUNC1_OEN_SEL_V 0x00000001 +#define GPIO_FUNC1_OEN_SEL_S 10 + +/* GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC1_OUT_INV_SEL_S 9 + +/* GPIO_FUNC1_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC1_OUT_SEL 0x000001FF +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000001FF +#define GPIO_FUNC1_OUT_SEL_S 0 + +/* GPIO_FUNC2_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 2 + */ + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) + +/* GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC2_OEN_INV_SEL_S 11 + +/* GPIO_FUNC2_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC2_OEN_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) +#define GPIO_FUNC2_OEN_SEL_V 0x00000001 +#define GPIO_FUNC2_OEN_SEL_S 10 + +/* GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC2_OUT_INV_SEL_S 9 + +/* GPIO_FUNC2_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC2_OUT_SEL 0x000001FF +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000001FF +#define GPIO_FUNC2_OUT_SEL_S 0 + +/* GPIO_FUNC3_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 3 + */ + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) + +/* GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC3_OEN_INV_SEL_S 11 + +/* GPIO_FUNC3_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC3_OEN_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) +#define GPIO_FUNC3_OEN_SEL_V 0x00000001 +#define GPIO_FUNC3_OEN_SEL_S 10 + +/* GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC3_OUT_INV_SEL_S 9 + +/* GPIO_FUNC3_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC3_OUT_SEL 0x000001FF +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000001FF +#define GPIO_FUNC3_OUT_SEL_S 0 + +/* GPIO_FUNC4_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 4 + */ + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) + +/* GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC4_OEN_INV_SEL_S 11 + +/* GPIO_FUNC4_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC4_OEN_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) +#define GPIO_FUNC4_OEN_SEL_V 0x00000001 +#define GPIO_FUNC4_OEN_SEL_S 10 + +/* GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC4_OUT_INV_SEL_S 9 + +/* GPIO_FUNC4_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC4_OUT_SEL 0x000001FF +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000001FF +#define GPIO_FUNC4_OUT_SEL_S 0 + +/* GPIO_FUNC5_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 5 + */ + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) + +/* GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC5_OEN_INV_SEL_S 11 + +/* GPIO_FUNC5_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC5_OEN_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) +#define GPIO_FUNC5_OEN_SEL_V 0x00000001 +#define GPIO_FUNC5_OEN_SEL_S 10 + +/* GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC5_OUT_INV_SEL_S 9 + +/* GPIO_FUNC5_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC5_OUT_SEL 0x000001FF +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000001FF +#define GPIO_FUNC5_OUT_SEL_S 0 + +/* GPIO_FUNC6_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 6 + */ + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) + +/* GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC6_OEN_INV_SEL_S 11 + +/* GPIO_FUNC6_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC6_OEN_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) +#define GPIO_FUNC6_OEN_SEL_V 0x00000001 +#define GPIO_FUNC6_OEN_SEL_S 10 + +/* GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC6_OUT_INV_SEL_S 9 + +/* GPIO_FUNC6_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC6_OUT_SEL 0x000001FF +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000001FF +#define GPIO_FUNC6_OUT_SEL_S 0 + +/* GPIO_FUNC7_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 7 + */ + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) + +/* GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC7_OEN_INV_SEL_S 11 + +/* GPIO_FUNC7_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC7_OEN_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) +#define GPIO_FUNC7_OEN_SEL_V 0x00000001 +#define GPIO_FUNC7_OEN_SEL_S 10 + +/* GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC7_OUT_INV_SEL_S 9 + +/* GPIO_FUNC7_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC7_OUT_SEL 0x000001FF +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000001FF +#define GPIO_FUNC7_OUT_SEL_S 0 + +/* GPIO_FUNC8_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 8 + */ + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) + +/* GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC8_OEN_INV_SEL_S 11 + +/* GPIO_FUNC8_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC8_OEN_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) +#define GPIO_FUNC8_OEN_SEL_V 0x00000001 +#define GPIO_FUNC8_OEN_SEL_S 10 + +/* GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC8_OUT_INV_SEL_S 9 + +/* GPIO_FUNC8_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC8_OUT_SEL 0x000001FF +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000001FF +#define GPIO_FUNC8_OUT_SEL_S 0 + +/* GPIO_FUNC9_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 9 + */ + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) + +/* GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC9_OEN_INV_SEL_S 11 + +/* GPIO_FUNC9_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC9_OEN_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) +#define GPIO_FUNC9_OEN_SEL_V 0x00000001 +#define GPIO_FUNC9_OEN_SEL_S 10 + +/* GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC9_OUT_INV_SEL_S 9 + +/* GPIO_FUNC9_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC9_OUT_SEL 0x000001FF +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000001FF +#define GPIO_FUNC9_OUT_SEL_S 0 + +/* GPIO_FUNC10_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 10 + */ + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) + +/* GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC10_OEN_INV_SEL_S 11 + +/* GPIO_FUNC10_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC10_OEN_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) +#define GPIO_FUNC10_OEN_SEL_V 0x00000001 +#define GPIO_FUNC10_OEN_SEL_S 10 + +/* GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC10_OUT_INV_SEL_S 9 + +/* GPIO_FUNC10_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC10_OUT_SEL 0x000001FF +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000001FF +#define GPIO_FUNC10_OUT_SEL_S 0 + +/* GPIO_FUNC11_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 11 + */ + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) + +/* GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC11_OEN_INV_SEL_S 11 + +/* GPIO_FUNC11_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC11_OEN_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) +#define GPIO_FUNC11_OEN_SEL_V 0x00000001 +#define GPIO_FUNC11_OEN_SEL_S 10 + +/* GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC11_OUT_INV_SEL_S 9 + +/* GPIO_FUNC11_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC11_OUT_SEL 0x000001FF +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000001FF +#define GPIO_FUNC11_OUT_SEL_S 0 + +/* GPIO_FUNC12_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 12 + */ + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) + +/* GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC12_OEN_INV_SEL_S 11 + +/* GPIO_FUNC12_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC12_OEN_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) +#define GPIO_FUNC12_OEN_SEL_V 0x00000001 +#define GPIO_FUNC12_OEN_SEL_S 10 + +/* GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC12_OUT_INV_SEL_S 9 + +/* GPIO_FUNC12_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC12_OUT_SEL 0x000001FF +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000001FF +#define GPIO_FUNC12_OUT_SEL_S 0 + +/* GPIO_FUNC13_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 13 + */ + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) + +/* GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC13_OEN_INV_SEL_S 11 + +/* GPIO_FUNC13_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC13_OEN_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) +#define GPIO_FUNC13_OEN_SEL_V 0x00000001 +#define GPIO_FUNC13_OEN_SEL_S 10 + +/* GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC13_OUT_INV_SEL_S 9 + +/* GPIO_FUNC13_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC13_OUT_SEL 0x000001FF +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000001FF +#define GPIO_FUNC13_OUT_SEL_S 0 + +/* GPIO_FUNC14_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 14 + */ + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) + +/* GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC14_OEN_INV_SEL_S 11 + +/* GPIO_FUNC14_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC14_OEN_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) +#define GPIO_FUNC14_OEN_SEL_V 0x00000001 +#define GPIO_FUNC14_OEN_SEL_S 10 + +/* GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC14_OUT_INV_SEL_S 9 + +/* GPIO_FUNC14_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC14_OUT_SEL 0x000001FF +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000001FF +#define GPIO_FUNC14_OUT_SEL_S 0 + +/* GPIO_FUNC15_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 15 + */ + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) + +/* GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC15_OEN_INV_SEL_S 11 + +/* GPIO_FUNC15_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC15_OEN_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) +#define GPIO_FUNC15_OEN_SEL_V 0x00000001 +#define GPIO_FUNC15_OEN_SEL_S 10 + +/* GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC15_OUT_INV_SEL_S 9 + +/* GPIO_FUNC15_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC15_OUT_SEL 0x000001FF +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000001FF +#define GPIO_FUNC15_OUT_SEL_S 0 + +/* GPIO_FUNC16_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 16 + */ + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) + +/* GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC16_OEN_INV_SEL_S 11 + +/* GPIO_FUNC16_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC16_OEN_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) +#define GPIO_FUNC16_OEN_SEL_V 0x00000001 +#define GPIO_FUNC16_OEN_SEL_S 10 + +/* GPIO_FUNC16_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC16_OUT_INV_SEL_S 9 + +/* GPIO_FUNC16_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC16_OUT_SEL 0x000001FF +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000001FF +#define GPIO_FUNC16_OUT_SEL_S 0 + +/* GPIO_FUNC17_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 17 + */ + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) + +/* GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC17_OEN_INV_SEL_S 11 + +/* GPIO_FUNC17_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC17_OEN_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) +#define GPIO_FUNC17_OEN_SEL_V 0x00000001 +#define GPIO_FUNC17_OEN_SEL_S 10 + +/* GPIO_FUNC17_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC17_OUT_INV_SEL_S 9 + +/* GPIO_FUNC17_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC17_OUT_SEL 0x000001FF +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000001FF +#define GPIO_FUNC17_OUT_SEL_S 0 + +/* GPIO_FUNC18_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 18 + */ + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) + +/* GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC18_OEN_INV_SEL_S 11 + +/* GPIO_FUNC18_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC18_OEN_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) +#define GPIO_FUNC18_OEN_SEL_V 0x00000001 +#define GPIO_FUNC18_OEN_SEL_S 10 + +/* GPIO_FUNC18_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC18_OUT_INV_SEL_S 9 + +/* GPIO_FUNC18_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC18_OUT_SEL 0x000001FF +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000001FF +#define GPIO_FUNC18_OUT_SEL_S 0 + +/* GPIO_FUNC19_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 19 + */ + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) + +/* GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC19_OEN_INV_SEL_S 11 + +/* GPIO_FUNC19_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC19_OEN_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) +#define GPIO_FUNC19_OEN_SEL_V 0x00000001 +#define GPIO_FUNC19_OEN_SEL_S 10 + +/* GPIO_FUNC19_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC19_OUT_INV_SEL_S 9 + +/* GPIO_FUNC19_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC19_OUT_SEL 0x000001FF +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000001FF +#define GPIO_FUNC19_OUT_SEL_S 0 + +/* GPIO_FUNC20_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 20 + */ + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) + +/* GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC20_OEN_INV_SEL_S 11 + +/* GPIO_FUNC20_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC20_OEN_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) +#define GPIO_FUNC20_OEN_SEL_V 0x00000001 +#define GPIO_FUNC20_OEN_SEL_S 10 + +/* GPIO_FUNC20_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC20_OUT_INV_SEL_S 9 + +/* GPIO_FUNC20_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC20_OUT_SEL 0x000001FF +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000001FF +#define GPIO_FUNC20_OUT_SEL_S 0 + +/* GPIO_FUNC21_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 21 + */ + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) + +/* GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC21_OEN_INV_SEL_S 11 + +/* GPIO_FUNC21_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC21_OEN_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) +#define GPIO_FUNC21_OEN_SEL_V 0x00000001 +#define GPIO_FUNC21_OEN_SEL_S 10 + +/* GPIO_FUNC21_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC21_OUT_INV_SEL_S 9 + +/* GPIO_FUNC21_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC21_OUT_SEL 0x000001FF +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000001FF +#define GPIO_FUNC21_OUT_SEL_S 0 + +/* GPIO_FUNC22_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 22 + */ + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) + +/* GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC22_OEN_INV_SEL_S 11 + +/* GPIO_FUNC22_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC22_OEN_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) +#define GPIO_FUNC22_OEN_SEL_V 0x00000001 +#define GPIO_FUNC22_OEN_SEL_S 10 + +/* GPIO_FUNC22_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC22_OUT_INV_SEL_S 9 + +/* GPIO_FUNC22_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC22_OUT_SEL 0x000001FF +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000001FF +#define GPIO_FUNC22_OUT_SEL_S 0 + +/* GPIO_FUNC23_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 23 + */ + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) + +/* GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC23_OEN_INV_SEL_S 11 + +/* GPIO_FUNC23_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC23_OEN_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) +#define GPIO_FUNC23_OEN_SEL_V 0x00000001 +#define GPIO_FUNC23_OEN_SEL_S 10 + +/* GPIO_FUNC23_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC23_OUT_INV_SEL_S 9 + +/* GPIO_FUNC23_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC23_OUT_SEL 0x000001FF +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000001FF +#define GPIO_FUNC23_OUT_SEL_S 0 + +/* GPIO_FUNC24_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 24 + */ + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) + +/* GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC24_OEN_INV_SEL_S 11 + +/* GPIO_FUNC24_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC24_OEN_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) +#define GPIO_FUNC24_OEN_SEL_V 0x00000001 +#define GPIO_FUNC24_OEN_SEL_S 10 + +/* GPIO_FUNC24_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC24_OUT_INV_SEL_S 9 + +/* GPIO_FUNC24_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC24_OUT_SEL 0x000001FF +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000001FF +#define GPIO_FUNC24_OUT_SEL_S 0 + +/* GPIO_FUNC25_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 25 + */ + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) + +/* GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC25_OEN_INV_SEL_S 11 + +/* GPIO_FUNC25_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC25_OEN_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) +#define GPIO_FUNC25_OEN_SEL_V 0x00000001 +#define GPIO_FUNC25_OEN_SEL_S 10 + +/* GPIO_FUNC25_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC25_OUT_INV_SEL_S 9 + +/* GPIO_FUNC25_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC25_OUT_SEL 0x000001FF +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000001FF +#define GPIO_FUNC25_OUT_SEL_S 0 + +/* GPIO_FUNC26_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 26 + */ + +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) + +/* GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC26_OEN_INV_SEL_S 11 + +/* GPIO_FUNC26_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC26_OEN_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) +#define GPIO_FUNC26_OEN_SEL_V 0x00000001 +#define GPIO_FUNC26_OEN_SEL_S 10 + +/* GPIO_FUNC26_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC26_OUT_INV_SEL_S 9 + +/* GPIO_FUNC26_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC26_OUT_SEL 0x000001FF +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000001FF +#define GPIO_FUNC26_OUT_SEL_S 0 + +/* GPIO_FUNC27_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 27 + */ + +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) + +/* GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC27_OEN_INV_SEL_S 11 + +/* GPIO_FUNC27_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC27_OEN_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) +#define GPIO_FUNC27_OEN_SEL_V 0x00000001 +#define GPIO_FUNC27_OEN_SEL_S 10 + +/* GPIO_FUNC27_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC27_OUT_INV_SEL_S 9 + +/* GPIO_FUNC27_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC27_OUT_SEL 0x000001FF +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000001FF +#define GPIO_FUNC27_OUT_SEL_S 0 + +/* GPIO_FUNC28_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 28 + */ + +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) + +/* GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC28_OEN_INV_SEL_S 11 + +/* GPIO_FUNC28_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC28_OEN_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) +#define GPIO_FUNC28_OEN_SEL_V 0x00000001 +#define GPIO_FUNC28_OEN_SEL_S 10 + +/* GPIO_FUNC28_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC28_OUT_INV_SEL_S 9 + +/* GPIO_FUNC28_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC28_OUT_SEL 0x000001FF +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000001FF +#define GPIO_FUNC28_OUT_SEL_S 0 + +/* GPIO_FUNC29_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 29 + */ + +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) + +/* GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC29_OEN_INV_SEL_S 11 + +/* GPIO_FUNC29_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC29_OEN_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) +#define GPIO_FUNC29_OEN_SEL_V 0x00000001 +#define GPIO_FUNC29_OEN_SEL_S 10 + +/* GPIO_FUNC29_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC29_OUT_INV_SEL_S 9 + +/* GPIO_FUNC29_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC29_OUT_SEL 0x000001FF +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000001FF +#define GPIO_FUNC29_OUT_SEL_S 0 + +/* GPIO_FUNC30_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 30 + */ + +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) + +/* GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC30_OEN_INV_SEL_S 11 + +/* GPIO_FUNC30_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC30_OEN_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) +#define GPIO_FUNC30_OEN_SEL_V 0x00000001 +#define GPIO_FUNC30_OEN_SEL_S 10 + +/* GPIO_FUNC30_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC30_OUT_INV_SEL_S 9 + +/* GPIO_FUNC30_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC30_OUT_SEL 0x000001FF +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000001FF +#define GPIO_FUNC30_OUT_SEL_S 0 + +/* GPIO_FUNC31_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 31 + */ + +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0) + +/* GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_M (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC31_OEN_INV_SEL_S 11 + +/* GPIO_FUNC31_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC31_OEN_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_M (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S) +#define GPIO_FUNC31_OEN_SEL_V 0x00000001 +#define GPIO_FUNC31_OEN_SEL_S 10 + +/* GPIO_FUNC31_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC31_OUT_INV_SEL_S 9 + +/* GPIO_FUNC31_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC31_OUT_SEL 0x000001FF +#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) +#define GPIO_FUNC31_OUT_SEL_V 0x000001FF +#define GPIO_FUNC31_OUT_SEL_S 0 + +/* GPIO_FUNC32_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 32 + */ + +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4) + +/* GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_M (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC32_OEN_INV_SEL_S 11 + +/* GPIO_FUNC32_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC32_OEN_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_M (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S) +#define GPIO_FUNC32_OEN_SEL_V 0x00000001 +#define GPIO_FUNC32_OEN_SEL_S 10 + +/* GPIO_FUNC32_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC32_OUT_INV_SEL_S 9 + +/* GPIO_FUNC32_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC32_OUT_SEL 0x000001FF +#define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) +#define GPIO_FUNC32_OUT_SEL_V 0x000001FF +#define GPIO_FUNC32_OUT_SEL_S 0 + +/* GPIO_FUNC33_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 33 + */ + +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8) + +/* GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_M (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC33_OEN_INV_SEL_S 11 + +/* GPIO_FUNC33_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC33_OEN_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_M (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S) +#define GPIO_FUNC33_OEN_SEL_V 0x00000001 +#define GPIO_FUNC33_OEN_SEL_S 10 + +/* GPIO_FUNC33_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_M (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC33_OUT_INV_SEL_S 9 + +/* GPIO_FUNC33_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC33_OUT_SEL 0x000001FF +#define GPIO_FUNC33_OUT_SEL_M (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S) +#define GPIO_FUNC33_OUT_SEL_V 0x000001FF +#define GPIO_FUNC33_OUT_SEL_S 0 + +/* GPIO_FUNC34_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 34 + */ + +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc) + +/* GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_M (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC34_OEN_INV_SEL_S 11 + +/* GPIO_FUNC34_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC34_OEN_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_M (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S) +#define GPIO_FUNC34_OEN_SEL_V 0x00000001 +#define GPIO_FUNC34_OEN_SEL_S 10 + +/* GPIO_FUNC34_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_M (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC34_OUT_INV_SEL_S 9 + +/* GPIO_FUNC34_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC34_OUT_SEL 0x000001FF +#define GPIO_FUNC34_OUT_SEL_M (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S) +#define GPIO_FUNC34_OUT_SEL_V 0x000001FF +#define GPIO_FUNC34_OUT_SEL_S 0 + +/* GPIO_FUNC35_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 35 + */ + +#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0) + +/* GPIO_FUNC35_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_M (GPIO_FUNC35_OEN_INV_SEL_V << GPIO_FUNC35_OEN_INV_SEL_S) +#define GPIO_FUNC35_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC35_OEN_INV_SEL_S 11 + +/* GPIO_FUNC35_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC35_OEN_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_M (GPIO_FUNC35_OEN_SEL_V << GPIO_FUNC35_OEN_SEL_S) +#define GPIO_FUNC35_OEN_SEL_V 0x00000001 +#define GPIO_FUNC35_OEN_SEL_S 10 + +/* GPIO_FUNC35_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_M (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S) +#define GPIO_FUNC35_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC35_OUT_INV_SEL_S 9 + +/* GPIO_FUNC35_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC35_OUT_SEL 0x000001FF +#define GPIO_FUNC35_OUT_SEL_M (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S) +#define GPIO_FUNC35_OUT_SEL_V 0x000001FF +#define GPIO_FUNC35_OUT_SEL_S 0 + +/* GPIO_FUNC36_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 36 + */ + +#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4) + +/* GPIO_FUNC36_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_M (GPIO_FUNC36_OEN_INV_SEL_V << GPIO_FUNC36_OEN_INV_SEL_S) +#define GPIO_FUNC36_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC36_OEN_INV_SEL_S 11 + +/* GPIO_FUNC36_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC36_OEN_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_M (GPIO_FUNC36_OEN_SEL_V << GPIO_FUNC36_OEN_SEL_S) +#define GPIO_FUNC36_OEN_SEL_V 0x00000001 +#define GPIO_FUNC36_OEN_SEL_S 10 + +/* GPIO_FUNC36_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_M (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S) +#define GPIO_FUNC36_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC36_OUT_INV_SEL_S 9 + +/* GPIO_FUNC36_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC36_OUT_SEL 0x000001FF +#define GPIO_FUNC36_OUT_SEL_M (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S) +#define GPIO_FUNC36_OUT_SEL_V 0x000001FF +#define GPIO_FUNC36_OUT_SEL_S 0 + +/* GPIO_FUNC37_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 37 + */ + +#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8) + +/* GPIO_FUNC37_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_M (GPIO_FUNC37_OEN_INV_SEL_V << GPIO_FUNC37_OEN_INV_SEL_S) +#define GPIO_FUNC37_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC37_OEN_INV_SEL_S 11 + +/* GPIO_FUNC37_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC37_OEN_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_M (GPIO_FUNC37_OEN_SEL_V << GPIO_FUNC37_OEN_SEL_S) +#define GPIO_FUNC37_OEN_SEL_V 0x00000001 +#define GPIO_FUNC37_OEN_SEL_S 10 + +/* GPIO_FUNC37_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_M (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S) +#define GPIO_FUNC37_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC37_OUT_INV_SEL_S 9 + +/* GPIO_FUNC37_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC37_OUT_SEL 0x000001FF +#define GPIO_FUNC37_OUT_SEL_M (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S) +#define GPIO_FUNC37_OUT_SEL_V 0x000001FF +#define GPIO_FUNC37_OUT_SEL_S 0 + +/* GPIO_FUNC38_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 38 + */ + +#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec) + +/* GPIO_FUNC38_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_M (GPIO_FUNC38_OEN_INV_SEL_V << GPIO_FUNC38_OEN_INV_SEL_S) +#define GPIO_FUNC38_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC38_OEN_INV_SEL_S 11 + +/* GPIO_FUNC38_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC38_OEN_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_M (GPIO_FUNC38_OEN_SEL_V << GPIO_FUNC38_OEN_SEL_S) +#define GPIO_FUNC38_OEN_SEL_V 0x00000001 +#define GPIO_FUNC38_OEN_SEL_S 10 + +/* GPIO_FUNC38_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_M (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S) +#define GPIO_FUNC38_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC38_OUT_INV_SEL_S 9 + +/* GPIO_FUNC38_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC38_OUT_SEL 0x000001FF +#define GPIO_FUNC38_OUT_SEL_M (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S) +#define GPIO_FUNC38_OUT_SEL_V 0x000001FF +#define GPIO_FUNC38_OUT_SEL_S 0 + +/* GPIO_FUNC39_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 39 + */ + +#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0) + +/* GPIO_FUNC39_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_M (GPIO_FUNC39_OEN_INV_SEL_V << GPIO_FUNC39_OEN_INV_SEL_S) +#define GPIO_FUNC39_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC39_OEN_INV_SEL_S 11 + +/* GPIO_FUNC39_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC39_OEN_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_M (GPIO_FUNC39_OEN_SEL_V << GPIO_FUNC39_OEN_SEL_S) +#define GPIO_FUNC39_OEN_SEL_V 0x00000001 +#define GPIO_FUNC39_OEN_SEL_S 10 + +/* GPIO_FUNC39_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_M (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S) +#define GPIO_FUNC39_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC39_OUT_INV_SEL_S 9 + +/* GPIO_FUNC39_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC39_OUT_SEL 0x000001FF +#define GPIO_FUNC39_OUT_SEL_M (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S) +#define GPIO_FUNC39_OUT_SEL_V 0x000001FF +#define GPIO_FUNC39_OUT_SEL_S 0 + +/* GPIO_FUNC40_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 40 + */ + +#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4) + +/* GPIO_FUNC40_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC40_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC40_OEN_INV_SEL_M (GPIO_FUNC40_OEN_INV_SEL_V << GPIO_FUNC40_OEN_INV_SEL_S) +#define GPIO_FUNC40_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC40_OEN_INV_SEL_S 11 + +/* GPIO_FUNC40_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC40_OEN_SEL (BIT(10)) +#define GPIO_FUNC40_OEN_SEL_M (GPIO_FUNC40_OEN_SEL_V << GPIO_FUNC40_OEN_SEL_S) +#define GPIO_FUNC40_OEN_SEL_V 0x00000001 +#define GPIO_FUNC40_OEN_SEL_S 10 + +/* GPIO_FUNC40_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC40_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC40_OUT_INV_SEL_M (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S) +#define GPIO_FUNC40_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC40_OUT_INV_SEL_S 9 + +/* GPIO_FUNC40_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC40_OUT_SEL 0x000001FF +#define GPIO_FUNC40_OUT_SEL_M (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S) +#define GPIO_FUNC40_OUT_SEL_V 0x000001FF +#define GPIO_FUNC40_OUT_SEL_S 0 + +/* GPIO_FUNC41_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 41 + */ + +#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8) + +/* GPIO_FUNC41_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC41_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC41_OEN_INV_SEL_M (GPIO_FUNC41_OEN_INV_SEL_V << GPIO_FUNC41_OEN_INV_SEL_S) +#define GPIO_FUNC41_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC41_OEN_INV_SEL_S 11 + +/* GPIO_FUNC41_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC41_OEN_SEL (BIT(10)) +#define GPIO_FUNC41_OEN_SEL_M (GPIO_FUNC41_OEN_SEL_V << GPIO_FUNC41_OEN_SEL_S) +#define GPIO_FUNC41_OEN_SEL_V 0x00000001 +#define GPIO_FUNC41_OEN_SEL_S 10 + +/* GPIO_FUNC41_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC41_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC41_OUT_INV_SEL_M (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S) +#define GPIO_FUNC41_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC41_OUT_INV_SEL_S 9 + +/* GPIO_FUNC41_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC41_OUT_SEL 0x000001FF +#define GPIO_FUNC41_OUT_SEL_M (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S) +#define GPIO_FUNC41_OUT_SEL_V 0x000001FF +#define GPIO_FUNC41_OUT_SEL_S 0 + +/* GPIO_FUNC42_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 42 + */ + +#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc) + +/* GPIO_FUNC42_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC42_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC42_OEN_INV_SEL_M (GPIO_FUNC42_OEN_INV_SEL_V << GPIO_FUNC42_OEN_INV_SEL_S) +#define GPIO_FUNC42_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC42_OEN_INV_SEL_S 11 + +/* GPIO_FUNC42_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC42_OEN_SEL (BIT(10)) +#define GPIO_FUNC42_OEN_SEL_M (GPIO_FUNC42_OEN_SEL_V << GPIO_FUNC42_OEN_SEL_S) +#define GPIO_FUNC42_OEN_SEL_V 0x00000001 +#define GPIO_FUNC42_OEN_SEL_S 10 + +/* GPIO_FUNC42_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC42_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC42_OUT_INV_SEL_M (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S) +#define GPIO_FUNC42_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC42_OUT_INV_SEL_S 9 + +/* GPIO_FUNC42_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC42_OUT_SEL 0x000001FF +#define GPIO_FUNC42_OUT_SEL_M (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S) +#define GPIO_FUNC42_OUT_SEL_V 0x000001FF +#define GPIO_FUNC42_OUT_SEL_S 0 + +/* GPIO_FUNC43_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 43 + */ + +#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600) + +/* GPIO_FUNC43_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC43_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC43_OEN_INV_SEL_M (GPIO_FUNC43_OEN_INV_SEL_V << GPIO_FUNC43_OEN_INV_SEL_S) +#define GPIO_FUNC43_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC43_OEN_INV_SEL_S 11 + +/* GPIO_FUNC43_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC43_OEN_SEL (BIT(10)) +#define GPIO_FUNC43_OEN_SEL_M (GPIO_FUNC43_OEN_SEL_V << GPIO_FUNC43_OEN_SEL_S) +#define GPIO_FUNC43_OEN_SEL_V 0x00000001 +#define GPIO_FUNC43_OEN_SEL_S 10 + +/* GPIO_FUNC43_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC43_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC43_OUT_INV_SEL_M (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S) +#define GPIO_FUNC43_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC43_OUT_INV_SEL_S 9 + +/* GPIO_FUNC43_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC43_OUT_SEL 0x000001FF +#define GPIO_FUNC43_OUT_SEL_M (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S) +#define GPIO_FUNC43_OUT_SEL_V 0x000001FF +#define GPIO_FUNC43_OUT_SEL_S 0 + +/* GPIO_FUNC44_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 44 + */ + +#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604) + +/* GPIO_FUNC44_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC44_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC44_OEN_INV_SEL_M (GPIO_FUNC44_OEN_INV_SEL_V << GPIO_FUNC44_OEN_INV_SEL_S) +#define GPIO_FUNC44_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC44_OEN_INV_SEL_S 11 + +/* GPIO_FUNC44_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC44_OEN_SEL (BIT(10)) +#define GPIO_FUNC44_OEN_SEL_M (GPIO_FUNC44_OEN_SEL_V << GPIO_FUNC44_OEN_SEL_S) +#define GPIO_FUNC44_OEN_SEL_V 0x00000001 +#define GPIO_FUNC44_OEN_SEL_S 10 + +/* GPIO_FUNC44_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC44_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC44_OUT_INV_SEL_M (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S) +#define GPIO_FUNC44_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC44_OUT_INV_SEL_S 9 + +/* GPIO_FUNC44_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC44_OUT_SEL 0x000001FF +#define GPIO_FUNC44_OUT_SEL_M (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S) +#define GPIO_FUNC44_OUT_SEL_V 0x000001FF +#define GPIO_FUNC44_OUT_SEL_S 0 + +/* GPIO_FUNC45_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 45 + */ + +#define GPIO_FUNC45_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x608) + +/* GPIO_FUNC45_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC45_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC45_OEN_INV_SEL_M (GPIO_FUNC45_OEN_INV_SEL_V << GPIO_FUNC45_OEN_INV_SEL_S) +#define GPIO_FUNC45_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC45_OEN_INV_SEL_S 11 + +/* GPIO_FUNC45_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC45_OEN_SEL (BIT(10)) +#define GPIO_FUNC45_OEN_SEL_M (GPIO_FUNC45_OEN_SEL_V << GPIO_FUNC45_OEN_SEL_S) +#define GPIO_FUNC45_OEN_SEL_V 0x00000001 +#define GPIO_FUNC45_OEN_SEL_S 10 + +/* GPIO_FUNC45_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC45_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC45_OUT_INV_SEL_M (GPIO_FUNC45_OUT_INV_SEL_V << GPIO_FUNC45_OUT_INV_SEL_S) +#define GPIO_FUNC45_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC45_OUT_INV_SEL_S 9 + +/* GPIO_FUNC45_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC45_OUT_SEL 0x000001FF +#define GPIO_FUNC45_OUT_SEL_M (GPIO_FUNC45_OUT_SEL_V << GPIO_FUNC45_OUT_SEL_S) +#define GPIO_FUNC45_OUT_SEL_V 0x000001FF +#define GPIO_FUNC45_OUT_SEL_S 0 + +/* GPIO_FUNC46_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 46 + */ + +#define GPIO_FUNC46_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x60c) + +/* GPIO_FUNC46_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC46_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC46_OEN_INV_SEL_M (GPIO_FUNC46_OEN_INV_SEL_V << GPIO_FUNC46_OEN_INV_SEL_S) +#define GPIO_FUNC46_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC46_OEN_INV_SEL_S 11 + +/* GPIO_FUNC46_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC46_OEN_SEL (BIT(10)) +#define GPIO_FUNC46_OEN_SEL_M (GPIO_FUNC46_OEN_SEL_V << GPIO_FUNC46_OEN_SEL_S) +#define GPIO_FUNC46_OEN_SEL_V 0x00000001 +#define GPIO_FUNC46_OEN_SEL_S 10 + +/* GPIO_FUNC46_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC46_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC46_OUT_INV_SEL_M (GPIO_FUNC46_OUT_INV_SEL_V << GPIO_FUNC46_OUT_INV_SEL_S) +#define GPIO_FUNC46_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC46_OUT_INV_SEL_S 9 + +/* GPIO_FUNC46_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC46_OUT_SEL 0x000001FF +#define GPIO_FUNC46_OUT_SEL_M (GPIO_FUNC46_OUT_SEL_V << GPIO_FUNC46_OUT_SEL_S) +#define GPIO_FUNC46_OUT_SEL_V 0x000001FF +#define GPIO_FUNC46_OUT_SEL_S 0 + +/* GPIO_FUNC47_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 47 + */ + +#define GPIO_FUNC47_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x610) + +/* GPIO_FUNC47_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC47_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC47_OEN_INV_SEL_M (GPIO_FUNC47_OEN_INV_SEL_V << GPIO_FUNC47_OEN_INV_SEL_S) +#define GPIO_FUNC47_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC47_OEN_INV_SEL_S 11 + +/* GPIO_FUNC47_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC47_OEN_SEL (BIT(10)) +#define GPIO_FUNC47_OEN_SEL_M (GPIO_FUNC47_OEN_SEL_V << GPIO_FUNC47_OEN_SEL_S) +#define GPIO_FUNC47_OEN_SEL_V 0x00000001 +#define GPIO_FUNC47_OEN_SEL_S 10 + +/* GPIO_FUNC47_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC47_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC47_OUT_INV_SEL_M (GPIO_FUNC47_OUT_INV_SEL_V << GPIO_FUNC47_OUT_INV_SEL_S) +#define GPIO_FUNC47_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC47_OUT_INV_SEL_S 9 + +/* GPIO_FUNC47_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC47_OUT_SEL 0x000001FF +#define GPIO_FUNC47_OUT_SEL_M (GPIO_FUNC47_OUT_SEL_V << GPIO_FUNC47_OUT_SEL_S) +#define GPIO_FUNC47_OUT_SEL_V 0x000001FF +#define GPIO_FUNC47_OUT_SEL_S 0 + +/* GPIO_FUNC48_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 48 + */ + +#define GPIO_FUNC48_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x614) + +/* GPIO_FUNC48_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC48_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC48_OEN_INV_SEL_M (GPIO_FUNC48_OEN_INV_SEL_V << GPIO_FUNC48_OEN_INV_SEL_S) +#define GPIO_FUNC48_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC48_OEN_INV_SEL_S 11 + +/* GPIO_FUNC48_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC48_OEN_SEL (BIT(10)) +#define GPIO_FUNC48_OEN_SEL_M (GPIO_FUNC48_OEN_SEL_V << GPIO_FUNC48_OEN_SEL_S) +#define GPIO_FUNC48_OEN_SEL_V 0x00000001 +#define GPIO_FUNC48_OEN_SEL_S 10 + +/* GPIO_FUNC48_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC48_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC48_OUT_INV_SEL_M (GPIO_FUNC48_OUT_INV_SEL_V << GPIO_FUNC48_OUT_INV_SEL_S) +#define GPIO_FUNC48_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC48_OUT_INV_SEL_S 9 + +/* GPIO_FUNC48_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC48_OUT_SEL 0x000001FF +#define GPIO_FUNC48_OUT_SEL_M (GPIO_FUNC48_OUT_SEL_V << GPIO_FUNC48_OUT_SEL_S) +#define GPIO_FUNC48_OUT_SEL_V 0x000001FF +#define GPIO_FUNC48_OUT_SEL_S 0 + +/* GPIO_FUNC49_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 49 + */ + +#define GPIO_FUNC49_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x618) + +/* GPIO_FUNC49_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC49_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC49_OEN_INV_SEL_M (GPIO_FUNC49_OEN_INV_SEL_V << GPIO_FUNC49_OEN_INV_SEL_S) +#define GPIO_FUNC49_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC49_OEN_INV_SEL_S 11 + +/* GPIO_FUNC49_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC49_OEN_SEL (BIT(10)) +#define GPIO_FUNC49_OEN_SEL_M (GPIO_FUNC49_OEN_SEL_V << GPIO_FUNC49_OEN_SEL_S) +#define GPIO_FUNC49_OEN_SEL_V 0x00000001 +#define GPIO_FUNC49_OEN_SEL_S 10 + +/* GPIO_FUNC49_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC49_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC49_OUT_INV_SEL_M (GPIO_FUNC49_OUT_INV_SEL_V << GPIO_FUNC49_OUT_INV_SEL_S) +#define GPIO_FUNC49_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC49_OUT_INV_SEL_S 9 + +/* GPIO_FUNC49_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC49_OUT_SEL 0x000001FF +#define GPIO_FUNC49_OUT_SEL_M (GPIO_FUNC49_OUT_SEL_V << GPIO_FUNC49_OUT_SEL_S) +#define GPIO_FUNC49_OUT_SEL_V 0x000001FF +#define GPIO_FUNC49_OUT_SEL_S 0 + +/* GPIO_FUNC50_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 50 + */ + +#define GPIO_FUNC50_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x61c) + +/* GPIO_FUNC50_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC50_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC50_OEN_INV_SEL_M (GPIO_FUNC50_OEN_INV_SEL_V << GPIO_FUNC50_OEN_INV_SEL_S) +#define GPIO_FUNC50_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC50_OEN_INV_SEL_S 11 + +/* GPIO_FUNC50_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC50_OEN_SEL (BIT(10)) +#define GPIO_FUNC50_OEN_SEL_M (GPIO_FUNC50_OEN_SEL_V << GPIO_FUNC50_OEN_SEL_S) +#define GPIO_FUNC50_OEN_SEL_V 0x00000001 +#define GPIO_FUNC50_OEN_SEL_S 10 + +/* GPIO_FUNC50_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC50_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC50_OUT_INV_SEL_M (GPIO_FUNC50_OUT_INV_SEL_V << GPIO_FUNC50_OUT_INV_SEL_S) +#define GPIO_FUNC50_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC50_OUT_INV_SEL_S 9 + +/* GPIO_FUNC50_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC50_OUT_SEL 0x000001FF +#define GPIO_FUNC50_OUT_SEL_M (GPIO_FUNC50_OUT_SEL_V << GPIO_FUNC50_OUT_SEL_S) +#define GPIO_FUNC50_OUT_SEL_V 0x000001FF +#define GPIO_FUNC50_OUT_SEL_S 0 + +/* GPIO_FUNC51_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 51 + */ + +#define GPIO_FUNC51_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x620) + +/* GPIO_FUNC51_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC51_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC51_OEN_INV_SEL_M (GPIO_FUNC51_OEN_INV_SEL_V << GPIO_FUNC51_OEN_INV_SEL_S) +#define GPIO_FUNC51_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC51_OEN_INV_SEL_S 11 + +/* GPIO_FUNC51_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC51_OEN_SEL (BIT(10)) +#define GPIO_FUNC51_OEN_SEL_M (GPIO_FUNC51_OEN_SEL_V << GPIO_FUNC51_OEN_SEL_S) +#define GPIO_FUNC51_OEN_SEL_V 0x00000001 +#define GPIO_FUNC51_OEN_SEL_S 10 + +/* GPIO_FUNC51_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC51_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC51_OUT_INV_SEL_M (GPIO_FUNC51_OUT_INV_SEL_V << GPIO_FUNC51_OUT_INV_SEL_S) +#define GPIO_FUNC51_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC51_OUT_INV_SEL_S 9 + +/* GPIO_FUNC51_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC51_OUT_SEL 0x000001FF +#define GPIO_FUNC51_OUT_SEL_M (GPIO_FUNC51_OUT_SEL_V << GPIO_FUNC51_OUT_SEL_S) +#define GPIO_FUNC51_OUT_SEL_V 0x000001FF +#define GPIO_FUNC51_OUT_SEL_S 0 + +/* GPIO_FUNC52_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 52 + */ + +#define GPIO_FUNC52_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x624) + +/* GPIO_FUNC52_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC52_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC52_OEN_INV_SEL_M (GPIO_FUNC52_OEN_INV_SEL_V << GPIO_FUNC52_OEN_INV_SEL_S) +#define GPIO_FUNC52_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC52_OEN_INV_SEL_S 11 + +/* GPIO_FUNC52_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC52_OEN_SEL (BIT(10)) +#define GPIO_FUNC52_OEN_SEL_M (GPIO_FUNC52_OEN_SEL_V << GPIO_FUNC52_OEN_SEL_S) +#define GPIO_FUNC52_OEN_SEL_V 0x00000001 +#define GPIO_FUNC52_OEN_SEL_S 10 + +/* GPIO_FUNC52_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC52_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC52_OUT_INV_SEL_M (GPIO_FUNC52_OUT_INV_SEL_V << GPIO_FUNC52_OUT_INV_SEL_S) +#define GPIO_FUNC52_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC52_OUT_INV_SEL_S 9 + +/* GPIO_FUNC52_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC52_OUT_SEL 0x000001FF +#define GPIO_FUNC52_OUT_SEL_M (GPIO_FUNC52_OUT_SEL_V << GPIO_FUNC52_OUT_SEL_S) +#define GPIO_FUNC52_OUT_SEL_V 0x000001FF +#define GPIO_FUNC52_OUT_SEL_S 0 + +/* GPIO_FUNC53_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 53 + */ + +#define GPIO_FUNC53_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x628) + +/* GPIO_FUNC53_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC53_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC53_OEN_INV_SEL_M (GPIO_FUNC53_OEN_INV_SEL_V << GPIO_FUNC53_OEN_INV_SEL_S) +#define GPIO_FUNC53_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC53_OEN_INV_SEL_S 11 + +/* GPIO_FUNC53_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC53_OEN_SEL (BIT(10)) +#define GPIO_FUNC53_OEN_SEL_M (GPIO_FUNC53_OEN_SEL_V << GPIO_FUNC53_OEN_SEL_S) +#define GPIO_FUNC53_OEN_SEL_V 0x00000001 +#define GPIO_FUNC53_OEN_SEL_S 10 + +/* GPIO_FUNC53_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC53_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC53_OUT_INV_SEL_M (GPIO_FUNC53_OUT_INV_SEL_V << GPIO_FUNC53_OUT_INV_SEL_S) +#define GPIO_FUNC53_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC53_OUT_INV_SEL_S 9 + +/* GPIO_FUNC53_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC53_OUT_SEL 0x000001FF +#define GPIO_FUNC53_OUT_SEL_M (GPIO_FUNC53_OUT_SEL_V << GPIO_FUNC53_OUT_SEL_S) +#define GPIO_FUNC53_OUT_SEL_V 0x000001FF +#define GPIO_FUNC53_OUT_SEL_S 0 + +/* GPIO_CLOCK_GATE_REG register + * GPIO clock gating register + */ + +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) + +/* GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * Clock gating enable bit. If set to 1, the clock is free running. + */ + +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001 +#define GPIO_CLK_EN_S 0 + +/* GPIO_REG_DATE_REG register + * Version control register + */ + +#define GPIO_REG_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) + +/* GPIO_DATE : R/W; bitpos: [27:0]; default: 26234977; + * Version control register + */ + +#define GPIO_DATE 0x0FFFFFFF +#define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) +#define GPIO_DATE_V 0x0FFFFFFF +#define GPIO_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h new file mode 100644 index 00000000000..95f4e671b3f --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h @@ -0,0 +1,327 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H + +#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX +#define CLK_I2S_IDX CLK_I2S_MUX_IDX +#define FSPICLK_OUT_IDX FSPICLK_OUT_MUX_IDX + +#define SPIQ_IN_IDX 0 +#define SPIQ_OUT_IDX 0 +#define SPID_IN_IDX 1 +#define SPID_OUT_IDX 1 +#define SPIHD_IN_IDX 2 +#define SPIHD_OUT_IDX 2 +#define SPIWP_IN_IDX 3 +#define SPIWP_OUT_IDX 3 +#define SPICLK_OUT_MUX_IDX 4 +#define SPICS0_OUT_IDX 5 +#define SPICS1_OUT_IDX 6 +#define SPID4_IN_IDX 7 +#define SPID4_OUT_IDX 7 +#define SPID5_IN_IDX 8 +#define SPID5_OUT_IDX 8 +#define SPID6_IN_IDX 9 +#define SPID6_OUT_IDX 9 +#define SPID7_IN_IDX 10 +#define SPID7_OUT_IDX 10 +#define SPIDQS_IN_IDX 11 +#define SPIDQS_OUT_IDX 11 +#define U0RXD_IN_IDX 14 +#define U0TXD_OUT_IDX 14 +#define U0CTS_IN_IDX 15 +#define U0RTS_OUT_IDX 15 +#define U0DSR_IN_IDX 16 +#define U0DTR_OUT_IDX 16 +#define U1RXD_IN_IDX 17 +#define U1TXD_OUT_IDX 17 +#define U1CTS_IN_IDX 18 +#define U1RTS_OUT_IDX 18 +#define U1DSR_IN_IDX 21 +#define U1DTR_OUT_IDX 21 +#define I2S0O_BCK_IN_IDX 23 +#define I2S0O_BCK_OUT_IDX 23 +#define I2S0O_WS_IN_IDX 25 +#define I2S0O_WS_OUT_IDX 25 +#define I2S0I_BCK_IN_IDX 27 +#define I2S0I_BCK_OUT_IDX 27 +#define I2S0I_WS_IN_IDX 28 +#define I2S0I_WS_OUT_IDX 28 +#define I2CEXT0_SCL_IN_IDX 29 +#define I2CEXT0_SCL_OUT_IDX 29 +#define I2CEXT0_SDA_IN_IDX 30 +#define I2CEXT0_SDA_OUT_IDX 30 +#define SDIO_TOHOST_INT_OUT_IDX 31 +#define GPIO_BT_ACTIVE_IDX 37 +#define GPIO_BT_PRIORITY_IDX 38 +#define PCNT_SIG_CH0_IN0_IDX 39 +#define GPIO_WLAN_PRIO_IDX 39 +#define PCNT_SIG_CH1_IN0_IDX 40 +#define GPIO_WLAN_ACTIVE_IDX 40 +#define PCNT_CTRL_CH0_IN0_IDX 41 +#define BB_DIAG0_IDX 41 +#define PCNT_CTRL_CH1_IN0_IDX 42 +#define BB_DIAG1_IDX 42 +#define PCNT_SIG_CH0_IN1_IDX 43 +#define BB_DIAG2_IDX 43 +#define PCNT_SIG_CH1_IN1_IDX 44 +#define BB_DIAG3_IDX 44 +#define PCNT_CTRL_CH0_IN1_IDX 45 +#define BB_DIAG4_IDX 45 +#define PCNT_CTRL_CH1_IN1_IDX 46 +#define BB_DIAG5_IDX 46 +#define PCNT_SIG_CH0_IN2_IDX 47 +#define BB_DIAG6_IDX 47 +#define PCNT_SIG_CH1_IN2_IDX 48 +#define BB_DIAG7_IDX 48 +#define PCNT_CTRL_CH0_IN2_IDX 49 +#define BB_DIAG8_IDX 49 +#define PCNT_CTRL_CH1_IN2_IDX 50 +#define BB_DIAG9_IDX 50 +#define PCNT_SIG_CH0_IN3_IDX 51 +#define BB_DIAG10_IDX 51 +#define PCNT_SIG_CH1_IN3_IDX 52 +#define BB_DIAG11_IDX 52 +#define PCNT_CTRL_CH0_IN3_IDX 53 +#define BB_DIAG12_IDX 53 +#define PCNT_CTRL_CH1_IN3_IDX 54 +#define BB_DIAG13_IDX 54 +#define BB_DIAG14_IDX 55 +#define BB_DIAG15_IDX 56 +#define BB_DIAG16_IDX 57 +#define BB_DIAG17_IDX 58 +#define BB_DIAG18_IDX 59 +#define BB_DIAG19_IDX 60 +#define USB_EXTPHY_VP_IDX 61 +#define USB_EXTPHY_OEN_IDX 61 +#define USB_EXTPHY_VM_IDX 62 +#define USB_EXTPHY_SPEED_IDX 62 +#define USB_EXTPHY_RCV_IDX 63 +#define USB_EXTPHY_VPO_IDX 63 +#define USB_OTG_IDDIG_IN_IDX 64 +#define USB_EXTPHY_VMO_IDX 64 +#define USB_OTG_AVALID_IN_IDX 65 +#define USB_EXTPHY_SUSPND_IDX 65 +#define USB_SRP_BVALID_IN_IDX 66 +#define USB_OTG_IDPULLUP_IDX 66 +#define USB_OTG_VBUSVALID_IN_IDX 67 +#define USB_OTG_DPPULLDOWN_IDX 67 +#define USB_SRP_SESSEND_IN_IDX 68 +#define USB_OTG_DMPULLDOWN_IDX 68 +#define USB_OTG_DRVVBUS_IDX 69 +#define USB_SRP_CHRGVBUS_IDX 70 +#define USB_SRP_DISCHRGVBUS_IDX 71 +#define SPI3_CLK_IN_IDX 72 +#define SPI3_CLK_OUT_MUX_IDX 72 +#define SPI3_Q_IN_IDX 73 +#define SPI3_Q_OUT_IDX 73 +#define SPI3_D_IN_IDX 74 +#define SPI3_D_OUT_IDX 74 +#define SPI3_HD_IN_IDX 75 +#define SPI3_HD_OUT_IDX 75 +#define SPI3_CS0_IN_IDX 76 +#define SPI3_CS0_OUT_IDX 76 +#define SPI3_CS1_OUT_IDX 77 +#define SPI3_CS2_OUT_IDX 78 +#define LEDC_LS_SIG_OUT0_IDX 79 +#define LEDC_LS_SIG_OUT1_IDX 80 +#define LEDC_LS_SIG_OUT2_IDX 81 +#define LEDC_LS_SIG_OUT3_IDX 82 +#define RMT_SIG_IN0_IDX 83 +#define LEDC_LS_SIG_OUT4_IDX 83 +#define RMT_SIG_IN1_IDX 84 +#define LEDC_LS_SIG_OUT5_IDX 84 +#define RMT_SIG_IN2_IDX 85 +#define LEDC_LS_SIG_OUT6_IDX 85 +#define RMT_SIG_IN3_IDX 86 +#define LEDC_LS_SIG_OUT7_IDX 86 +#define RMT_SIG_OUT0_IDX 87 +#define RMT_SIG_OUT1_IDX 88 +#define RMT_SIG_OUT2_IDX 89 +#define RMT_SIG_OUT3_IDX 90 +#define EXT_ADC_START_IDX 93 +#define I2CEXT1_SCL_IN_IDX 95 +#define I2CEXT1_SCL_OUT_IDX 95 +#define I2CEXT1_SDA_IN_IDX 96 +#define I2CEXT1_SDA_OUT_IDX 96 +#define GPIO_SD0_OUT_IDX 100 +#define GPIO_SD1_OUT_IDX 101 +#define GPIO_SD2_OUT_IDX 102 +#define GPIO_SD3_OUT_IDX 103 +#define GPIO_SD4_OUT_IDX 104 +#define GPIO_SD5_OUT_IDX 105 +#define GPIO_SD6_OUT_IDX 106 +#define GPIO_SD7_OUT_IDX 107 +#define FSPICLK_IN_IDX 108 +#define FSPICLK_OUT_MUX_IDX 108 +#define FSPIQ_IN_IDX 109 +#define FSPIQ_OUT_IDX 109 +#define FSPID_IN_IDX 110 +#define FSPID_OUT_IDX 110 +#define FSPIHD_IN_IDX 111 +#define FSPIHD_OUT_IDX 111 +#define FSPIWP_IN_IDX 112 +#define FSPIWP_OUT_IDX 112 +#define FSPIIO4_IN_IDX 113 +#define FSPIIO4_OUT_IDX 113 +#define FSPIIO5_IN_IDX 114 +#define FSPIIO5_OUT_IDX 114 +#define FSPIIO6_IN_IDX 115 +#define FSPIIO6_OUT_IDX 115 +#define FSPIIO7_IN_IDX 116 +#define FSPIIO7_OUT_IDX 116 +#define FSPICS0_IN_IDX 117 +#define FSPICS0_OUT_IDX 117 +#define FSPICS1_OUT_IDX 118 +#define FSPICS2_OUT_IDX 119 +#define FSPICS3_OUT_IDX 120 +#define FSPICS4_OUT_IDX 121 +#define FSPICS5_OUT_IDX 122 +#define TWAI_RX_IDX 123 +#define TWAI_TX_IDX 123 +#define TWAI_BUS_OFF_ON_IDX 124 +#define TWAI_CLKOUT_IDX 125 +#define SUBSPICLK_OUT_MUX_IDX 126 +#define SUBSPIQ_IN_IDX 127 +#define SUBSPIQ_OUT_IDX 127 +#define SUBSPID_IN_IDX 128 +#define SUBSPID_OUT_IDX 128 +#define SUBSPIHD_IN_IDX 129 +#define SUBSPIHD_OUT_IDX 129 +#define SUBSPIWP_IN_IDX 130 +#define SUBSPIWP_OUT_IDX 130 +#define SUBSPICS0_OUT_IDX 131 +#define SUBSPICS1_OUT_IDX 132 +#define FSPIDQS_OUT_IDX 133 +#define FSPI_HSYNC_OUT_IDX 134 +#define FSPI_VSYNC_OUT_IDX 135 +#define FSPI_DE_OUT_IDX 136 +#define FSPICD_OUT_IDX 137 +#define SPI3_CD_OUT_IDX 139 +#define SPI3_DQS_OUT_IDX 140 +#define I2S0I_DATA_IN0_IDX 143 +#define I2S0O_DATA_OUT0_IDX 143 +#define I2S0I_DATA_IN1_IDX 144 +#define I2S0O_DATA_OUT1_IDX 144 +#define I2S0I_DATA_IN2_IDX 145 +#define I2S0O_DATA_OUT2_IDX 145 +#define I2S0I_DATA_IN3_IDX 146 +#define I2S0O_DATA_OUT3_IDX 146 +#define I2S0I_DATA_IN4_IDX 147 +#define I2S0O_DATA_OUT4_IDX 147 +#define I2S0I_DATA_IN5_IDX 148 +#define I2S0O_DATA_OUT5_IDX 148 +#define I2S0I_DATA_IN6_IDX 149 +#define I2S0O_DATA_OUT6_IDX 149 +#define I2S0I_DATA_IN7_IDX 150 +#define I2S0O_DATA_OUT7_IDX 150 +#define I2S0I_DATA_IN8_IDX 151 +#define I2S0O_DATA_OUT8_IDX 151 +#define I2S0I_DATA_IN9_IDX 152 +#define I2S0O_DATA_OUT9_IDX 152 +#define I2S0I_DATA_IN10_IDX 153 +#define I2S0O_DATA_OUT10_IDX 153 +#define I2S0I_DATA_IN11_IDX 154 +#define I2S0O_DATA_OUT11_IDX 154 +#define I2S0I_DATA_IN12_IDX 155 +#define I2S0O_DATA_OUT12_IDX 155 +#define I2S0I_DATA_IN13_IDX 156 +#define I2S0O_DATA_OUT13_IDX 156 +#define I2S0I_DATA_IN14_IDX 157 +#define I2S0O_DATA_OUT14_IDX 157 +#define I2S0I_DATA_IN15_IDX 158 +#define I2S0O_DATA_OUT15_IDX 158 +#define I2S0O_DATA_OUT16_IDX 159 +#define I2S0O_DATA_OUT17_IDX 160 +#define I2S0O_DATA_OUT18_IDX 161 +#define I2S0O_DATA_OUT19_IDX 162 +#define I2S0O_DATA_OUT20_IDX 163 +#define I2S0O_DATA_OUT21_IDX 164 +#define I2S0O_DATA_OUT22_IDX 165 +#define I2S0O_DATA_OUT23_IDX 166 +#define SUBSPID4_IN_IDX 167 +#define SUBSPID4_OUT_IDX 167 +#define SUBSPID5_IN_IDX 168 +#define SUBSPID5_OUT_IDX 168 +#define SUBSPID6_IN_IDX 169 +#define SUBSPID6_OUT_IDX 169 +#define SUBSPID7_IN_IDX 170 +#define SUBSPID7_OUT_IDX 170 +#define SUBSPIDQS_IN_IDX 171 +#define SUBSPIDQS_OUT_IDX 171 +#define I2S0I_H_SYNC_IDX 193 +#define I2S0I_V_SYNC_IDX 194 +#define I2S0I_H_ENABLE_IDX 195 +#define PCMFSYNC_IN_IDX 203 +#define BT_AUDIO0_IRQ_IDX 203 +#define PCMCLK_IN_IDX 204 +#define BT_AUDIO1_IRQ_IDX 204 +#define PCMDIN_IDX 205 +#define BT_AUDIO2_IRQ_IDX 205 +#define RW_WAKEUP_REQ_IDX 206 +#define BLE_AUDIO0_IRQ_IDX 206 +#define BLE_AUDIO1_IRQ_IDX 207 +#define BLE_AUDIO2_IRQ_IDX 208 +#define PCMFSYNC_OUT_IDX 209 +#define PCMCLK_OUT_IDX 210 +#define PCMDOUT_IDX 211 +#define BLE_AUDIO_SYNC0_P_IDX 212 +#define BLE_AUDIO_SYNC1_P_IDX 213 +#define BLE_AUDIO_SYNC2_P_IDX 214 +#define ANT_SEL0_IDX 215 +#define ANT_SEL1_IDX 216 +#define ANT_SEL2_IDX 217 +#define ANT_SEL3_IDX 218 +#define ANT_SEL4_IDX 219 +#define ANT_SEL5_IDX 220 +#define ANT_SEL6_IDX 221 +#define ANT_SEL7_IDX 222 +#define SIG_IN_FUNC_223_IDX 223 +#define SIG_IN_FUNC223_IDX 223 +#define SIG_IN_FUNC_224_IDX 224 +#define SIG_IN_FUNC224_IDX 224 +#define SIG_IN_FUNC_225_IDX 225 +#define SIG_IN_FUNC225_IDX 225 +#define SIG_IN_FUNC_226_IDX 226 +#define SIG_IN_FUNC226_IDX 226 +#define SIG_IN_FUNC_227_IDX 227 +#define SIG_IN_FUNC227_IDX 227 +#define PRO_ALONEGPIO_IN0_IDX 235 +#define PRO_ALONEGPIO_OUT0_IDX 235 +#define PRO_ALONEGPIO_IN1_IDX 236 +#define PRO_ALONEGPIO_OUT1_IDX 236 +#define PRO_ALONEGPIO_IN2_IDX 237 +#define PRO_ALONEGPIO_OUT2_IDX 237 +#define PRO_ALONEGPIO_IN3_IDX 238 +#define PRO_ALONEGPIO_OUT3_IDX 238 +#define PRO_ALONEGPIO_IN4_IDX 239 +#define PRO_ALONEGPIO_OUT4_IDX 239 +#define PRO_ALONEGPIO_IN5_IDX 240 +#define PRO_ALONEGPIO_OUT5_IDX 240 +#define PRO_ALONEGPIO_IN6_IDX 241 +#define PRO_ALONEGPIO_OUT6_IDX 241 +#define PRO_ALONEGPIO_IN7_IDX 242 +#define PRO_ALONEGPIO_OUT7_IDX 242 +#define CLK_I2S_MUX_IDX 251 +#define SIG_GPIO_OUT_IDX 256 +#define GPIO_MAP_DATE_IDX 0x1904100 +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h new file mode 100644 index 00000000000..25c87e9a122 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h @@ -0,0 +1,193 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H + +/** + * Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal + * configuration bus. These definitions are used via macros defined in + * regi2c_ctrl.h, by rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 1 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_BBADC_DELAY1 9 +#define I2C_BBPLL_BBADC_DELAY1_MSB 1 +#define I2C_BBPLL_BBADC_DELAY1_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_BBADC_CAL_7_0 12 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 + +#endif diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h new file mode 100644 index 00000000000..74c3732c2ce --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h @@ -0,0 +1,2229 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2S_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2S_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* I2S_CONF_REG register + * I2S Configure register + */ + +#define I2S_CONF_REG (DR_REG_I2S_BASE + 0x8) + +/* I2S_RX_RESET_ST : RO; bitpos: [29]; default: 0; + * I2S RX reset status. 1: I2S_RX_RESET is not finished. 0: I2S_RX_RESET is + * finished. + */ + +#define I2S_RX_RESET_ST (BIT(29)) +#define I2S_RX_RESET_ST_M (I2S_RX_RESET_ST_V << I2S_RX_RESET_ST_S) +#define I2S_RX_RESET_ST_V 0x00000001 +#define I2S_RX_RESET_ST_S 29 + +/* I2S_RX_BIG_ENDIAN : R/W; bitpos: [28]; default: 0; + * I2S RX byte endian. + */ + +#define I2S_RX_BIG_ENDIAN (BIT(28)) +#define I2S_RX_BIG_ENDIAN_M (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S) +#define I2S_RX_BIG_ENDIAN_V 0x00000001 +#define I2S_RX_BIG_ENDIAN_S 28 + +/* I2S_TX_BIG_ENDIAN : R/W; bitpos: [27]; default: 0; + * I2S TX byte endian. + */ + +#define I2S_TX_BIG_ENDIAN (BIT(27)) +#define I2S_TX_BIG_ENDIAN_M (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S) +#define I2S_TX_BIG_ENDIAN_V 0x00000001 +#define I2S_TX_BIG_ENDIAN_S 27 + +/* I2S_PRE_REQ_EN : R/W; bitpos: [26]; default: 0; + * set this bit to enable i2s to prepare data earlier + */ + +#define I2S_PRE_REQ_EN (BIT(26)) +#define I2S_PRE_REQ_EN_M (I2S_PRE_REQ_EN_V << I2S_PRE_REQ_EN_S) +#define I2S_PRE_REQ_EN_V 0x00000001 +#define I2S_PRE_REQ_EN_S 26 + +/* I2S_RX_DMA_EQUAL : R/W; bitpos: [25]; default: 0; + * 1:data in left channel is equal to data in right channel + */ + +#define I2S_RX_DMA_EQUAL (BIT(25)) +#define I2S_RX_DMA_EQUAL_M (I2S_RX_DMA_EQUAL_V << I2S_RX_DMA_EQUAL_S) +#define I2S_RX_DMA_EQUAL_V 0x00000001 +#define I2S_RX_DMA_EQUAL_S 25 + +/* I2S_TX_DMA_EQUAL : R/W; bitpos: [24]; default: 0; + * 1:data in left channel is equal to data in right channel + */ + +#define I2S_TX_DMA_EQUAL (BIT(24)) +#define I2S_TX_DMA_EQUAL_M (I2S_TX_DMA_EQUAL_V << I2S_TX_DMA_EQUAL_S) +#define I2S_TX_DMA_EQUAL_V 0x00000001 +#define I2S_TX_DMA_EQUAL_S 24 + +/* I2S_TX_RESET_ST : RO; bitpos: [23]; default: 0; + * 1: i2s_tx_reset is not ok 0: i2s_tx_reset is ok + */ + +#define I2S_TX_RESET_ST (BIT(23)) +#define I2S_TX_RESET_ST_M (I2S_TX_RESET_ST_V << I2S_TX_RESET_ST_S) +#define I2S_TX_RESET_ST_V 0x00000001 +#define I2S_TX_RESET_ST_S 23 + +/* I2S_RX_FIFO_RESET_ST : RO; bitpos: [22]; default: 0; + * 1:i2s_rx_fifo_reset is not ok 0:i2s_rx_fifo reset is ok + */ + +#define I2S_RX_FIFO_RESET_ST (BIT(22)) +#define I2S_RX_FIFO_RESET_ST_M (I2S_RX_FIFO_RESET_ST_V << I2S_RX_FIFO_RESET_ST_S) +#define I2S_RX_FIFO_RESET_ST_V 0x00000001 +#define I2S_RX_FIFO_RESET_ST_S 22 + +/* I2S_TX_FIFO_RESET_ST : RO; bitpos: [21]; default: 0; + * 1:i2s_tx_fifo reset is not ok 0:i2s_tx_fifo_reset is ok + */ + +#define I2S_TX_FIFO_RESET_ST (BIT(21)) +#define I2S_TX_FIFO_RESET_ST_M (I2S_TX_FIFO_RESET_ST_V << I2S_TX_FIFO_RESET_ST_S) +#define I2S_TX_FIFO_RESET_ST_V 0x00000001 +#define I2S_TX_FIFO_RESET_ST_S 21 + +/* I2S_SIG_LOOPBACK : R/W; bitpos: [20]; default: 0; + * Enable signal loopback mode with transmitter module and receiver module + * sharing the same WS and BCK signals. + */ + +#define I2S_SIG_LOOPBACK (BIT(20)) +#define I2S_SIG_LOOPBACK_M (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S) +#define I2S_SIG_LOOPBACK_V 0x00000001 +#define I2S_SIG_LOOPBACK_S 20 + +/* I2S_RX_LSB_FIRST_DMA : R/W; bitpos: [19]; default: 1; + * 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB + * transform from high bits. + */ + +#define I2S_RX_LSB_FIRST_DMA (BIT(19)) +#define I2S_RX_LSB_FIRST_DMA_M (I2S_RX_LSB_FIRST_DMA_V << I2S_RX_LSB_FIRST_DMA_S) +#define I2S_RX_LSB_FIRST_DMA_V 0x00000001 +#define I2S_RX_LSB_FIRST_DMA_S 19 + +/* I2S_TX_LSB_FIRST_DMA : R/W; bitpos: [18]; default: 1; + * 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB + * transform from high bits. + */ + +#define I2S_TX_LSB_FIRST_DMA (BIT(18)) +#define I2S_TX_LSB_FIRST_DMA_M (I2S_TX_LSB_FIRST_DMA_V << I2S_TX_LSB_FIRST_DMA_S) +#define I2S_TX_LSB_FIRST_DMA_V 0x00000001 +#define I2S_TX_LSB_FIRST_DMA_S 18 + +/* I2S_RX_MSB_RIGHT : R/W; bitpos: [17]; default: 0; + * Set this bit to place right channel data at the MSB in the receive FIFO. + */ + +#define I2S_RX_MSB_RIGHT (BIT(17)) +#define I2S_RX_MSB_RIGHT_M (I2S_RX_MSB_RIGHT_V << I2S_RX_MSB_RIGHT_S) +#define I2S_RX_MSB_RIGHT_V 0x00000001 +#define I2S_RX_MSB_RIGHT_S 17 + +/* I2S_TX_MSB_RIGHT : R/W; bitpos: [16]; default: 0; + * Set this bit to place right channel data at the MSB in the transmit FIFO. + */ + +#define I2S_TX_MSB_RIGHT (BIT(16)) +#define I2S_TX_MSB_RIGHT_M (I2S_TX_MSB_RIGHT_V << I2S_TX_MSB_RIGHT_S) +#define I2S_TX_MSB_RIGHT_V 0x00000001 +#define I2S_TX_MSB_RIGHT_S 16 + +/* I2S_RX_MONO : R/W; bitpos: [15]; default: 0; + * Set this bit to enable receiver in mono mode + */ + +#define I2S_RX_MONO (BIT(15)) +#define I2S_RX_MONO_M (I2S_RX_MONO_V << I2S_RX_MONO_S) +#define I2S_RX_MONO_V 0x00000001 +#define I2S_RX_MONO_S 15 + +/* I2S_TX_MONO : R/W; bitpos: [14]; default: 0; + * Set this bit to enable transmitter in mono mode + */ + +#define I2S_TX_MONO (BIT(14)) +#define I2S_TX_MONO_M (I2S_TX_MONO_V << I2S_TX_MONO_S) +#define I2S_TX_MONO_V 0x00000001 +#define I2S_TX_MONO_S 14 + +/* I2S_RX_SHORT_SYNC : R/W; bitpos: [13]; default: 0; + * Set this bit to enable receiver in PCM standard mode + */ + +#define I2S_RX_SHORT_SYNC (BIT(13)) +#define I2S_RX_SHORT_SYNC_M (I2S_RX_SHORT_SYNC_V << I2S_RX_SHORT_SYNC_S) +#define I2S_RX_SHORT_SYNC_V 0x00000001 +#define I2S_RX_SHORT_SYNC_S 13 + +/* I2S_TX_SHORT_SYNC : R/W; bitpos: [12]; default: 0; + * Set this bit to enable transmitter in PCM standard mode + */ + +#define I2S_TX_SHORT_SYNC (BIT(12)) +#define I2S_TX_SHORT_SYNC_M (I2S_TX_SHORT_SYNC_V << I2S_TX_SHORT_SYNC_S) +#define I2S_TX_SHORT_SYNC_V 0x00000001 +#define I2S_TX_SHORT_SYNC_S 12 + +/* I2S_RX_MSB_SHIFT : R/W; bitpos: [11]; default: 0; + * Set this bit to enable receiver in Phillips standard mode + */ + +#define I2S_RX_MSB_SHIFT (BIT(11)) +#define I2S_RX_MSB_SHIFT_M (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S) +#define I2S_RX_MSB_SHIFT_V 0x00000001 +#define I2S_RX_MSB_SHIFT_S 11 + +/* I2S_TX_MSB_SHIFT : R/W; bitpos: [10]; default: 0; + * Set this bit to enable transmitter in Phillips standard mode + */ + +#define I2S_TX_MSB_SHIFT (BIT(10)) +#define I2S_TX_MSB_SHIFT_M (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S) +#define I2S_TX_MSB_SHIFT_V 0x00000001 +#define I2S_TX_MSB_SHIFT_S 10 + +/* I2S_RX_RIGHT_FIRST : R/W; bitpos: [9]; default: 1; + * Set this bit to receive right channel data first + */ + +#define I2S_RX_RIGHT_FIRST (BIT(9)) +#define I2S_RX_RIGHT_FIRST_M (I2S_RX_RIGHT_FIRST_V << I2S_RX_RIGHT_FIRST_S) +#define I2S_RX_RIGHT_FIRST_V 0x00000001 +#define I2S_RX_RIGHT_FIRST_S 9 + +/* I2S_TX_RIGHT_FIRST : R/W; bitpos: [8]; default: 1; + * Set this bit to transmit right channel data first + */ + +#define I2S_TX_RIGHT_FIRST (BIT(8)) +#define I2S_TX_RIGHT_FIRST_M (I2S_TX_RIGHT_FIRST_V << I2S_TX_RIGHT_FIRST_S) +#define I2S_TX_RIGHT_FIRST_V 0x00000001 +#define I2S_TX_RIGHT_FIRST_S 8 + +/* I2S_RX_SLAVE_MOD : R/W; bitpos: [7]; default: 0; + * Set this bit to enable slave receiver mode + */ + +#define I2S_RX_SLAVE_MOD (BIT(7)) +#define I2S_RX_SLAVE_MOD_M (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S) +#define I2S_RX_SLAVE_MOD_V 0x00000001 +#define I2S_RX_SLAVE_MOD_S 7 + +/* I2S_TX_SLAVE_MOD : R/W; bitpos: [6]; default: 0; + * Set this bit to enable slave transmitter mode + */ + +#define I2S_TX_SLAVE_MOD (BIT(6)) +#define I2S_TX_SLAVE_MOD_M (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S) +#define I2S_TX_SLAVE_MOD_V 0x00000001 +#define I2S_TX_SLAVE_MOD_S 6 + +/* I2S_RX_START : R/W; bitpos: [5]; default: 0; + * Set this bit to start receiving data + */ + +#define I2S_RX_START (BIT(5)) +#define I2S_RX_START_M (I2S_RX_START_V << I2S_RX_START_S) +#define I2S_RX_START_V 0x00000001 +#define I2S_RX_START_S 5 + +/* I2S_TX_START : R/W; bitpos: [4]; default: 0; + * Set this bit to start transmitting data + */ + +#define I2S_TX_START (BIT(4)) +#define I2S_TX_START_M (I2S_TX_START_V << I2S_TX_START_S) +#define I2S_TX_START_V 0x00000001 +#define I2S_TX_START_S 4 + +/* I2S_RX_FIFO_RESET : WO; bitpos: [3]; default: 0; + * Set this bit to reset rxFIFO + */ + +#define I2S_RX_FIFO_RESET (BIT(3)) +#define I2S_RX_FIFO_RESET_M (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S) +#define I2S_RX_FIFO_RESET_V 0x00000001 +#define I2S_RX_FIFO_RESET_S 3 + +/* I2S_TX_FIFO_RESET : WO; bitpos: [2]; default: 0; + * Set this bit to reset txFIFO + */ + +#define I2S_TX_FIFO_RESET (BIT(2)) +#define I2S_TX_FIFO_RESET_M (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S) +#define I2S_TX_FIFO_RESET_V 0x00000001 +#define I2S_TX_FIFO_RESET_S 2 + +/* I2S_RX_RESET : WO; bitpos: [1]; default: 0; + * Set this bit to reset receiver + */ + +#define I2S_RX_RESET (BIT(1)) +#define I2S_RX_RESET_M (I2S_RX_RESET_V << I2S_RX_RESET_S) +#define I2S_RX_RESET_V 0x00000001 +#define I2S_RX_RESET_S 1 + +/* I2S_TX_RESET : WO; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ + +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (I2S_TX_RESET_V << I2S_TX_RESET_S) +#define I2S_TX_RESET_V 0x00000001 +#define I2S_TX_RESET_S 0 + +/* I2S_INT_RAW_REG register + * Raw interrupt status + */ + +#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc) + +/* I2S_V_SYNC_INT_RAW : RO; bitpos: [17]; default: 0; + * The raw interrupt status bit for the i2s_v_sync_int interrupt + */ + +#define I2S_V_SYNC_INT_RAW (BIT(17)) +#define I2S_V_SYNC_INT_RAW_M (I2S_V_SYNC_INT_RAW_V << I2S_V_SYNC_INT_RAW_S) +#define I2S_V_SYNC_INT_RAW_V 0x00000001 +#define I2S_V_SYNC_INT_RAW_S 17 + +/* I2S_OUT_TOTAL_EOF_INT_RAW : RO; bitpos: [16]; default: 0; + * The raw interrupt status bit for the i2s_out_total_eof_int interrupt + */ + +#define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_RAW_M (I2S_OUT_TOTAL_EOF_INT_RAW_V << I2S_OUT_TOTAL_EOF_INT_RAW_S) +#define I2S_OUT_TOTAL_EOF_INT_RAW_V 0x00000001 +#define I2S_OUT_TOTAL_EOF_INT_RAW_S 16 + +/* I2S_IN_DSCR_EMPTY_INT_RAW : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the i2s_in_dscr_empty_int interrupt + */ + +#define I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_RAW_M (I2S_IN_DSCR_EMPTY_INT_RAW_V << I2S_IN_DSCR_EMPTY_INT_RAW_S) +#define I2S_IN_DSCR_EMPTY_INT_RAW_V 0x00000001 +#define I2S_IN_DSCR_EMPTY_INT_RAW_S 15 + +/* I2S_OUT_DSCR_ERR_INT_RAW : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the i2s_out_dscr_err_int interrupt + */ + +#define I2S_OUT_DSCR_ERR_INT_RAW (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_RAW_M (I2S_OUT_DSCR_ERR_INT_RAW_V << I2S_OUT_DSCR_ERR_INT_RAW_S) +#define I2S_OUT_DSCR_ERR_INT_RAW_V 0x00000001 +#define I2S_OUT_DSCR_ERR_INT_RAW_S 14 + +/* I2S_IN_DSCR_ERR_INT_RAW : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the i2s_in_dscr_err_int interrupt + */ + +#define I2S_IN_DSCR_ERR_INT_RAW (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_RAW_M (I2S_IN_DSCR_ERR_INT_RAW_V << I2S_IN_DSCR_ERR_INT_RAW_S) +#define I2S_IN_DSCR_ERR_INT_RAW_V 0x00000001 +#define I2S_IN_DSCR_ERR_INT_RAW_S 13 + +/* I2S_OUT_EOF_INT_RAW : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the i2s_out_eof_int interrupt + */ + +#define I2S_OUT_EOF_INT_RAW (BIT(12)) +#define I2S_OUT_EOF_INT_RAW_M (I2S_OUT_EOF_INT_RAW_V << I2S_OUT_EOF_INT_RAW_S) +#define I2S_OUT_EOF_INT_RAW_V 0x00000001 +#define I2S_OUT_EOF_INT_RAW_S 12 + +/* I2S_OUT_DONE_INT_RAW : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the i2s_out_done_int interrupt + */ + +#define I2S_OUT_DONE_INT_RAW (BIT(11)) +#define I2S_OUT_DONE_INT_RAW_M (I2S_OUT_DONE_INT_RAW_V << I2S_OUT_DONE_INT_RAW_S) +#define I2S_OUT_DONE_INT_RAW_V 0x00000001 +#define I2S_OUT_DONE_INT_RAW_S 11 + +/* I2S_IN_ERR_EOF_INT_RAW : RO; bitpos: [10]; default: 0; + * don't use + */ + +#define I2S_IN_ERR_EOF_INT_RAW (BIT(10)) +#define I2S_IN_ERR_EOF_INT_RAW_M (I2S_IN_ERR_EOF_INT_RAW_V << I2S_IN_ERR_EOF_INT_RAW_S) +#define I2S_IN_ERR_EOF_INT_RAW_V 0x00000001 +#define I2S_IN_ERR_EOF_INT_RAW_S 10 + +/* I2S_IN_SUC_EOF_INT_RAW : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the i2s_in_suc_eof_int interrupt + */ + +#define I2S_IN_SUC_EOF_INT_RAW (BIT(9)) +#define I2S_IN_SUC_EOF_INT_RAW_M (I2S_IN_SUC_EOF_INT_RAW_V << I2S_IN_SUC_EOF_INT_RAW_S) +#define I2S_IN_SUC_EOF_INT_RAW_V 0x00000001 +#define I2S_IN_SUC_EOF_INT_RAW_S 9 + +/* I2S_IN_DONE_INT_RAW : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the i2s_in_done_int interrupt + */ + +#define I2S_IN_DONE_INT_RAW (BIT(8)) +#define I2S_IN_DONE_INT_RAW_M (I2S_IN_DONE_INT_RAW_V << I2S_IN_DONE_INT_RAW_S) +#define I2S_IN_DONE_INT_RAW_V 0x00000001 +#define I2S_IN_DONE_INT_RAW_S 8 + +/* I2S_TX_HUNG_INT_RAW : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ + +#define I2S_TX_HUNG_INT_RAW (BIT(7)) +#define I2S_TX_HUNG_INT_RAW_M (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S) +#define I2S_TX_HUNG_INT_RAW_V 0x00000001 +#define I2S_TX_HUNG_INT_RAW_S 7 + +/* I2S_RX_HUNG_INT_RAW : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ + +#define I2S_RX_HUNG_INT_RAW (BIT(6)) +#define I2S_RX_HUNG_INT_RAW_M (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S) +#define I2S_RX_HUNG_INT_RAW_V 0x00000001 +#define I2S_RX_HUNG_INT_RAW_S 6 + +/* I2S_TX_REMPTY_INT_RAW : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the i2s_tx_rempty_int interrupt + */ + +#define I2S_TX_REMPTY_INT_RAW (BIT(5)) +#define I2S_TX_REMPTY_INT_RAW_M (I2S_TX_REMPTY_INT_RAW_V << I2S_TX_REMPTY_INT_RAW_S) +#define I2S_TX_REMPTY_INT_RAW_V 0x00000001 +#define I2S_TX_REMPTY_INT_RAW_S 5 + +/* I2S_TX_WFULL_INT_RAW : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the i2s_tx_wfull_int interrupt + */ + +#define I2S_TX_WFULL_INT_RAW (BIT(4)) +#define I2S_TX_WFULL_INT_RAW_M (I2S_TX_WFULL_INT_RAW_V << I2S_TX_WFULL_INT_RAW_S) +#define I2S_TX_WFULL_INT_RAW_V 0x00000001 +#define I2S_TX_WFULL_INT_RAW_S 4 + +/* I2S_RX_REMPTY_INT_RAW : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_rx_rempty_int interrupt + */ + +#define I2S_RX_REMPTY_INT_RAW (BIT(3)) +#define I2S_RX_REMPTY_INT_RAW_M (I2S_RX_REMPTY_INT_RAW_V << I2S_RX_REMPTY_INT_RAW_S) +#define I2S_RX_REMPTY_INT_RAW_V 0x00000001 +#define I2S_RX_REMPTY_INT_RAW_S 3 + +/* I2S_RX_WFULL_INT_RAW : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_wfull_int interrupt + */ + +#define I2S_RX_WFULL_INT_RAW (BIT(2)) +#define I2S_RX_WFULL_INT_RAW_M (I2S_RX_WFULL_INT_RAW_V << I2S_RX_WFULL_INT_RAW_S) +#define I2S_RX_WFULL_INT_RAW_V 0x00000001 +#define I2S_RX_WFULL_INT_RAW_S 2 + +/* I2S_TX_PUT_DATA_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_put_data_int interrupt + */ + +#define I2S_TX_PUT_DATA_INT_RAW (BIT(1)) +#define I2S_TX_PUT_DATA_INT_RAW_M (I2S_TX_PUT_DATA_INT_RAW_V << I2S_TX_PUT_DATA_INT_RAW_S) +#define I2S_TX_PUT_DATA_INT_RAW_V 0x00000001 +#define I2S_TX_PUT_DATA_INT_RAW_S 1 + +/* I2S_RX_TAKE_DATA_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_take_data_int interrupt + */ + +#define I2S_RX_TAKE_DATA_INT_RAW (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_RAW_M (I2S_RX_TAKE_DATA_INT_RAW_V << I2S_RX_TAKE_DATA_INT_RAW_S) +#define I2S_RX_TAKE_DATA_INT_RAW_V 0x00000001 +#define I2S_RX_TAKE_DATA_INT_RAW_S 0 + +/* I2S_INT_ST_REG register + * Masked interrupt status + */ + +#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10) + +/* I2S_V_SYNC_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for the i2s_v_sync_int interrupt + */ + +#define I2S_V_SYNC_INT_ST (BIT(17)) +#define I2S_V_SYNC_INT_ST_M (I2S_V_SYNC_INT_ST_V << I2S_V_SYNC_INT_ST_S) +#define I2S_V_SYNC_INT_ST_V 0x00000001 +#define I2S_V_SYNC_INT_ST_S 17 + +/* I2S_OUT_TOTAL_EOF_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for the i2s_out_total_eof_int interrupt + */ + +#define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ST_M (I2S_OUT_TOTAL_EOF_INT_ST_V << I2S_OUT_TOTAL_EOF_INT_ST_S) +#define I2S_OUT_TOTAL_EOF_INT_ST_V 0x00000001 +#define I2S_OUT_TOTAL_EOF_INT_ST_S 16 + +/* I2S_IN_DSCR_EMPTY_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for the i2s_in_dscr_empty_int interrupt + */ + +#define I2S_IN_DSCR_EMPTY_INT_ST (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ST_M (I2S_IN_DSCR_EMPTY_INT_ST_V << I2S_IN_DSCR_EMPTY_INT_ST_S) +#define I2S_IN_DSCR_EMPTY_INT_ST_V 0x00000001 +#define I2S_IN_DSCR_EMPTY_INT_ST_S 15 + +/* I2S_OUT_DSCR_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for the i2s_out_dscr_err_int interrupt + */ + +#define I2S_OUT_DSCR_ERR_INT_ST (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ST_M (I2S_OUT_DSCR_ERR_INT_ST_V << I2S_OUT_DSCR_ERR_INT_ST_S) +#define I2S_OUT_DSCR_ERR_INT_ST_V 0x00000001 +#define I2S_OUT_DSCR_ERR_INT_ST_S 14 + +/* I2S_IN_DSCR_ERR_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for the i2s_in_dscr_err_int interrupt + */ + +#define I2S_IN_DSCR_ERR_INT_ST (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ST_M (I2S_IN_DSCR_ERR_INT_ST_V << I2S_IN_DSCR_ERR_INT_ST_S) +#define I2S_IN_DSCR_ERR_INT_ST_V 0x00000001 +#define I2S_IN_DSCR_ERR_INT_ST_S 13 + +/* I2S_OUT_EOF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for the i2s_out_eof_int interrupt + */ + +#define I2S_OUT_EOF_INT_ST (BIT(12)) +#define I2S_OUT_EOF_INT_ST_M (I2S_OUT_EOF_INT_ST_V << I2S_OUT_EOF_INT_ST_S) +#define I2S_OUT_EOF_INT_ST_V 0x00000001 +#define I2S_OUT_EOF_INT_ST_S 12 + +/* I2S_OUT_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for the i2s_out_done_int interrupt + */ + +#define I2S_OUT_DONE_INT_ST (BIT(11)) +#define I2S_OUT_DONE_INT_ST_M (I2S_OUT_DONE_INT_ST_V << I2S_OUT_DONE_INT_ST_S) +#define I2S_OUT_DONE_INT_ST_V 0x00000001 +#define I2S_OUT_DONE_INT_ST_S 11 + +/* I2S_IN_ERR_EOF_INT_ST : RO; bitpos: [10]; default: 0; + * don't use + */ + +#define I2S_IN_ERR_EOF_INT_ST (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ST_M (I2S_IN_ERR_EOF_INT_ST_V << I2S_IN_ERR_EOF_INT_ST_S) +#define I2S_IN_ERR_EOF_INT_ST_V 0x00000001 +#define I2S_IN_ERR_EOF_INT_ST_S 10 + +/* I2S_IN_SUC_EOF_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the i2s_in_suc_eof_int interrupt + */ + +#define I2S_IN_SUC_EOF_INT_ST (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ST_M (I2S_IN_SUC_EOF_INT_ST_V << I2S_IN_SUC_EOF_INT_ST_S) +#define I2S_IN_SUC_EOF_INT_ST_V 0x00000001 +#define I2S_IN_SUC_EOF_INT_ST_S 9 + +/* I2S_IN_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the i2s_in_done_int interrupt + */ + +#define I2S_IN_DONE_INT_ST (BIT(8)) +#define I2S_IN_DONE_INT_ST_M (I2S_IN_DONE_INT_ST_V << I2S_IN_DONE_INT_ST_S) +#define I2S_IN_DONE_INT_ST_V 0x00000001 +#define I2S_IN_DONE_INT_ST_S 8 + +/* I2S_TX_HUNG_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ + +#define I2S_TX_HUNG_INT_ST (BIT(7)) +#define I2S_TX_HUNG_INT_ST_M (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S) +#define I2S_TX_HUNG_INT_ST_V 0x00000001 +#define I2S_TX_HUNG_INT_ST_S 7 + +/* I2S_RX_HUNG_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ + +#define I2S_RX_HUNG_INT_ST (BIT(6)) +#define I2S_RX_HUNG_INT_ST_M (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S) +#define I2S_RX_HUNG_INT_ST_V 0x00000001 +#define I2S_RX_HUNG_INT_ST_S 6 + +/* I2S_TX_REMPTY_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the i2s_tx_rempty_int interrupt + */ + +#define I2S_TX_REMPTY_INT_ST (BIT(5)) +#define I2S_TX_REMPTY_INT_ST_M (I2S_TX_REMPTY_INT_ST_V << I2S_TX_REMPTY_INT_ST_S) +#define I2S_TX_REMPTY_INT_ST_V 0x00000001 +#define I2S_TX_REMPTY_INT_ST_S 5 + +/* I2S_TX_WFULL_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the i2s_tx_wfull_int interrupt + */ + +#define I2S_TX_WFULL_INT_ST (BIT(4)) +#define I2S_TX_WFULL_INT_ST_M (I2S_TX_WFULL_INT_ST_V << I2S_TX_WFULL_INT_ST_S) +#define I2S_TX_WFULL_INT_ST_V 0x00000001 +#define I2S_TX_WFULL_INT_ST_S 4 + +/* I2S_RX_REMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_rx_rempty_int interrupt + */ + +#define I2S_RX_REMPTY_INT_ST (BIT(3)) +#define I2S_RX_REMPTY_INT_ST_M (I2S_RX_REMPTY_INT_ST_V << I2S_RX_REMPTY_INT_ST_S) +#define I2S_RX_REMPTY_INT_ST_V 0x00000001 +#define I2S_RX_REMPTY_INT_ST_S 3 + +/* I2S_RX_WFULL_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_wfull_int interrupt + */ + +#define I2S_RX_WFULL_INT_ST (BIT(2)) +#define I2S_RX_WFULL_INT_ST_M (I2S_RX_WFULL_INT_ST_V << I2S_RX_WFULL_INT_ST_S) +#define I2S_RX_WFULL_INT_ST_V 0x00000001 +#define I2S_RX_WFULL_INT_ST_S 2 + +/* I2S_TX_PUT_DATA_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_put_data_int interrupt + */ + +#define I2S_TX_PUT_DATA_INT_ST (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ST_M (I2S_TX_PUT_DATA_INT_ST_V << I2S_TX_PUT_DATA_INT_ST_S) +#define I2S_TX_PUT_DATA_INT_ST_V 0x00000001 +#define I2S_TX_PUT_DATA_INT_ST_S 1 + +/* I2S_RX_TAKE_DATA_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_take_data_int interrupt + */ + +#define I2S_RX_TAKE_DATA_INT_ST (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ST_M (I2S_RX_TAKE_DATA_INT_ST_V << I2S_RX_TAKE_DATA_INT_ST_S) +#define I2S_RX_TAKE_DATA_INT_ST_V 0x00000001 +#define I2S_RX_TAKE_DATA_INT_ST_S 0 + +/* I2S_INT_ENA_REG register + * Interrupt enable bits + */ + +#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14) + +/* I2S_V_SYNC_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for the i2s_v_sync_int interrupt + */ + +#define I2S_V_SYNC_INT_ENA (BIT(17)) +#define I2S_V_SYNC_INT_ENA_M (I2S_V_SYNC_INT_ENA_V << I2S_V_SYNC_INT_ENA_S) +#define I2S_V_SYNC_INT_ENA_V 0x00000001 +#define I2S_V_SYNC_INT_ENA_S 17 + +/* I2S_OUT_TOTAL_EOF_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for the i2s_out_total_eof_int interrupt + */ + +#define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ENA_M (I2S_OUT_TOTAL_EOF_INT_ENA_V << I2S_OUT_TOTAL_EOF_INT_ENA_S) +#define I2S_OUT_TOTAL_EOF_INT_ENA_V 0x00000001 +#define I2S_OUT_TOTAL_EOF_INT_ENA_S 16 + +/* I2S_IN_DSCR_EMPTY_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the i2s_in_dscr_empty_int interrupt + */ + +#define I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ENA_M (I2S_IN_DSCR_EMPTY_INT_ENA_V << I2S_IN_DSCR_EMPTY_INT_ENA_S) +#define I2S_IN_DSCR_EMPTY_INT_ENA_V 0x00000001 +#define I2S_IN_DSCR_EMPTY_INT_ENA_S 15 + +/* I2S_OUT_DSCR_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the i2s_out_dscr_err_int interrupt + */ + +#define I2S_OUT_DSCR_ERR_INT_ENA (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ENA_M (I2S_OUT_DSCR_ERR_INT_ENA_V << I2S_OUT_DSCR_ERR_INT_ENA_S) +#define I2S_OUT_DSCR_ERR_INT_ENA_V 0x00000001 +#define I2S_OUT_DSCR_ERR_INT_ENA_S 14 + +/* I2S_IN_DSCR_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the i2s_in_dscr_err_int interrupt + */ + +#define I2S_IN_DSCR_ERR_INT_ENA (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ENA_M (I2S_IN_DSCR_ERR_INT_ENA_V << I2S_IN_DSCR_ERR_INT_ENA_S) +#define I2S_IN_DSCR_ERR_INT_ENA_V 0x00000001 +#define I2S_IN_DSCR_ERR_INT_ENA_S 13 + +/* I2S_OUT_EOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the i2s_out_eof_int interrupt + */ + +#define I2S_OUT_EOF_INT_ENA (BIT(12)) +#define I2S_OUT_EOF_INT_ENA_M (I2S_OUT_EOF_INT_ENA_V << I2S_OUT_EOF_INT_ENA_S) +#define I2S_OUT_EOF_INT_ENA_V 0x00000001 +#define I2S_OUT_EOF_INT_ENA_S 12 + +/* I2S_OUT_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the i2s_out_done_int interrupt + */ + +#define I2S_OUT_DONE_INT_ENA (BIT(11)) +#define I2S_OUT_DONE_INT_ENA_M (I2S_OUT_DONE_INT_ENA_V << I2S_OUT_DONE_INT_ENA_S) +#define I2S_OUT_DONE_INT_ENA_V 0x00000001 +#define I2S_OUT_DONE_INT_ENA_S 11 + +/* I2S_IN_ERR_EOF_INT_ENA : R/W; bitpos: [10]; default: 0; + * don't use + */ + +#define I2S_IN_ERR_EOF_INT_ENA (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ENA_M (I2S_IN_ERR_EOF_INT_ENA_V << I2S_IN_ERR_EOF_INT_ENA_S) +#define I2S_IN_ERR_EOF_INT_ENA_V 0x00000001 +#define I2S_IN_ERR_EOF_INT_ENA_S 10 + +/* I2S_IN_SUC_EOF_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the i2s_in_suc_eof_int interrupt + */ + +#define I2S_IN_SUC_EOF_INT_ENA (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ENA_M (I2S_IN_SUC_EOF_INT_ENA_V << I2S_IN_SUC_EOF_INT_ENA_S) +#define I2S_IN_SUC_EOF_INT_ENA_V 0x00000001 +#define I2S_IN_SUC_EOF_INT_ENA_S 9 + +/* I2S_IN_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the i2s_in_done_int interrupt + */ + +#define I2S_IN_DONE_INT_ENA (BIT(8)) +#define I2S_IN_DONE_INT_ENA_M (I2S_IN_DONE_INT_ENA_V << I2S_IN_DONE_INT_ENA_S) +#define I2S_IN_DONE_INT_ENA_V 0x00000001 +#define I2S_IN_DONE_INT_ENA_S 8 + +/* I2S_TX_HUNG_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ + +#define I2S_TX_HUNG_INT_ENA (BIT(7)) +#define I2S_TX_HUNG_INT_ENA_M (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S) +#define I2S_TX_HUNG_INT_ENA_V 0x00000001 +#define I2S_TX_HUNG_INT_ENA_S 7 + +/* I2S_RX_HUNG_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ + +#define I2S_RX_HUNG_INT_ENA (BIT(6)) +#define I2S_RX_HUNG_INT_ENA_M (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S) +#define I2S_RX_HUNG_INT_ENA_V 0x00000001 +#define I2S_RX_HUNG_INT_ENA_S 6 + +/* I2S_TX_REMPTY_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the i2s_tx_rempty_int interrupt + */ + +#define I2S_TX_REMPTY_INT_ENA (BIT(5)) +#define I2S_TX_REMPTY_INT_ENA_M (I2S_TX_REMPTY_INT_ENA_V << I2S_TX_REMPTY_INT_ENA_S) +#define I2S_TX_REMPTY_INT_ENA_V 0x00000001 +#define I2S_TX_REMPTY_INT_ENA_S 5 + +/* I2S_TX_WFULL_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the i2s_tx_wfull_int interrupt + */ + +#define I2S_TX_WFULL_INT_ENA (BIT(4)) +#define I2S_TX_WFULL_INT_ENA_M (I2S_TX_WFULL_INT_ENA_V << I2S_TX_WFULL_INT_ENA_S) +#define I2S_TX_WFULL_INT_ENA_V 0x00000001 +#define I2S_TX_WFULL_INT_ENA_S 4 + +/* I2S_RX_REMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_rx_rempty_int interrupt + */ + +#define I2S_RX_REMPTY_INT_ENA (BIT(3)) +#define I2S_RX_REMPTY_INT_ENA_M (I2S_RX_REMPTY_INT_ENA_V << I2S_RX_REMPTY_INT_ENA_S) +#define I2S_RX_REMPTY_INT_ENA_V 0x00000001 +#define I2S_RX_REMPTY_INT_ENA_S 3 + +/* I2S_RX_WFULL_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_wfull_int interrupt + */ + +#define I2S_RX_WFULL_INT_ENA (BIT(2)) +#define I2S_RX_WFULL_INT_ENA_M (I2S_RX_WFULL_INT_ENA_V << I2S_RX_WFULL_INT_ENA_S) +#define I2S_RX_WFULL_INT_ENA_V 0x00000001 +#define I2S_RX_WFULL_INT_ENA_S 2 + +/* I2S_TX_PUT_DATA_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_put_data_int interrupt + */ + +#define I2S_TX_PUT_DATA_INT_ENA (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ENA_M (I2S_TX_PUT_DATA_INT_ENA_V << I2S_TX_PUT_DATA_INT_ENA_S) +#define I2S_TX_PUT_DATA_INT_ENA_V 0x00000001 +#define I2S_TX_PUT_DATA_INT_ENA_S 1 + +/* I2S_RX_TAKE_DATA_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_take_data_int interrupt + */ + +#define I2S_RX_TAKE_DATA_INT_ENA (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ENA_M (I2S_RX_TAKE_DATA_INT_ENA_V << I2S_RX_TAKE_DATA_INT_ENA_S) +#define I2S_RX_TAKE_DATA_INT_ENA_V 0x00000001 +#define I2S_RX_TAKE_DATA_INT_ENA_S 0 + +/* I2S_INT_CLR_REG register + * Interrupt clear bits + */ + +#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18) + +/* I2S_V_SYNC_INT_CLR : WO; bitpos: [17]; default: 0; + * Set this bit to clear the i2s_v_sync_int interrupt + */ + +#define I2S_V_SYNC_INT_CLR (BIT(17)) +#define I2S_V_SYNC_INT_CLR_M (I2S_V_SYNC_INT_CLR_V << I2S_V_SYNC_INT_CLR_S) +#define I2S_V_SYNC_INT_CLR_V 0x00000001 +#define I2S_V_SYNC_INT_CLR_S 17 + +/* I2S_OUT_TOTAL_EOF_INT_CLR : WO; bitpos: [16]; default: 0; + * Set this bit to clear the i2s_out_total_eof_int interrupt + */ + +#define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_CLR_M (I2S_OUT_TOTAL_EOF_INT_CLR_V << I2S_OUT_TOTAL_EOF_INT_CLR_S) +#define I2S_OUT_TOTAL_EOF_INT_CLR_V 0x00000001 +#define I2S_OUT_TOTAL_EOF_INT_CLR_S 16 + +/* I2S_IN_DSCR_EMPTY_INT_CLR : WO; bitpos: [15]; default: 0; + * Set this bit to clear the i2s_in_dscr_empty_int interrupt + */ + +#define I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_CLR_M (I2S_IN_DSCR_EMPTY_INT_CLR_V << I2S_IN_DSCR_EMPTY_INT_CLR_S) +#define I2S_IN_DSCR_EMPTY_INT_CLR_V 0x00000001 +#define I2S_IN_DSCR_EMPTY_INT_CLR_S 15 + +/* I2S_OUT_DSCR_ERR_INT_CLR : WO; bitpos: [14]; default: 0; + * Set this bit to clear the i2s_out_dscr_err_int interrupt + */ + +#define I2S_OUT_DSCR_ERR_INT_CLR (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_CLR_M (I2S_OUT_DSCR_ERR_INT_CLR_V << I2S_OUT_DSCR_ERR_INT_CLR_S) +#define I2S_OUT_DSCR_ERR_INT_CLR_V 0x00000001 +#define I2S_OUT_DSCR_ERR_INT_CLR_S 14 + +/* I2S_IN_DSCR_ERR_INT_CLR : WO; bitpos: [13]; default: 0; + * Set this bit to clear the i2s_in_dscr_err_int interrupt + */ + +#define I2S_IN_DSCR_ERR_INT_CLR (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_CLR_M (I2S_IN_DSCR_ERR_INT_CLR_V << I2S_IN_DSCR_ERR_INT_CLR_S) +#define I2S_IN_DSCR_ERR_INT_CLR_V 0x00000001 +#define I2S_IN_DSCR_ERR_INT_CLR_S 13 + +/* I2S_OUT_EOF_INT_CLR : WO; bitpos: [12]; default: 0; + * Set this bit to clear the i2s_out_eof_int interrupt + */ + +#define I2S_OUT_EOF_INT_CLR (BIT(12)) +#define I2S_OUT_EOF_INT_CLR_M (I2S_OUT_EOF_INT_CLR_V << I2S_OUT_EOF_INT_CLR_S) +#define I2S_OUT_EOF_INT_CLR_V 0x00000001 +#define I2S_OUT_EOF_INT_CLR_S 12 + +/* I2S_OUT_DONE_INT_CLR : WO; bitpos: [11]; default: 0; + * Set this bit to clear the i2s_out_done_int interrupt + */ + +#define I2S_OUT_DONE_INT_CLR (BIT(11)) +#define I2S_OUT_DONE_INT_CLR_M (I2S_OUT_DONE_INT_CLR_V << I2S_OUT_DONE_INT_CLR_S) +#define I2S_OUT_DONE_INT_CLR_V 0x00000001 +#define I2S_OUT_DONE_INT_CLR_S 11 + +/* I2S_IN_ERR_EOF_INT_CLR : WO; bitpos: [10]; default: 0; + * don't use + */ + +#define I2S_IN_ERR_EOF_INT_CLR (BIT(10)) +#define I2S_IN_ERR_EOF_INT_CLR_M (I2S_IN_ERR_EOF_INT_CLR_V << I2S_IN_ERR_EOF_INT_CLR_S) +#define I2S_IN_ERR_EOF_INT_CLR_V 0x00000001 +#define I2S_IN_ERR_EOF_INT_CLR_S 10 + +/* I2S_IN_SUC_EOF_INT_CLR : WO; bitpos: [9]; default: 0; + * Set this bit to clear the i2s_in_suc_eof_int interrupt + */ + +#define I2S_IN_SUC_EOF_INT_CLR (BIT(9)) +#define I2S_IN_SUC_EOF_INT_CLR_M (I2S_IN_SUC_EOF_INT_CLR_V << I2S_IN_SUC_EOF_INT_CLR_S) +#define I2S_IN_SUC_EOF_INT_CLR_V 0x00000001 +#define I2S_IN_SUC_EOF_INT_CLR_S 9 + +/* I2S_IN_DONE_INT_CLR : WO; bitpos: [8]; default: 0; + * Set this bit to clear the i2s_in_done_int interrupt + */ + +#define I2S_IN_DONE_INT_CLR (BIT(8)) +#define I2S_IN_DONE_INT_CLR_M (I2S_IN_DONE_INT_CLR_V << I2S_IN_DONE_INT_CLR_S) +#define I2S_IN_DONE_INT_CLR_V 0x00000001 +#define I2S_IN_DONE_INT_CLR_S 8 + +/* I2S_TX_HUNG_INT_CLR : WO; bitpos: [7]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ + +#define I2S_TX_HUNG_INT_CLR (BIT(7)) +#define I2S_TX_HUNG_INT_CLR_M (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S) +#define I2S_TX_HUNG_INT_CLR_V 0x00000001 +#define I2S_TX_HUNG_INT_CLR_S 7 + +/* I2S_RX_HUNG_INT_CLR : WO; bitpos: [6]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ + +#define I2S_RX_HUNG_INT_CLR (BIT(6)) +#define I2S_RX_HUNG_INT_CLR_M (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S) +#define I2S_RX_HUNG_INT_CLR_V 0x00000001 +#define I2S_RX_HUNG_INT_CLR_S 6 + +/* I2S_TX_REMPTY_INT_CLR : WO; bitpos: [5]; default: 0; + * Set this bit to clear the i2s_tx_rempty_int interrupt + */ + +#define I2S_TX_REMPTY_INT_CLR (BIT(5)) +#define I2S_TX_REMPTY_INT_CLR_M (I2S_TX_REMPTY_INT_CLR_V << I2S_TX_REMPTY_INT_CLR_S) +#define I2S_TX_REMPTY_INT_CLR_V 0x00000001 +#define I2S_TX_REMPTY_INT_CLR_S 5 + +/* I2S_TX_WFULL_INT_CLR : WO; bitpos: [4]; default: 0; + * Set this bit to clear the i2s_tx_wfull_int interrupt + */ + +#define I2S_TX_WFULL_INT_CLR (BIT(4)) +#define I2S_TX_WFULL_INT_CLR_M (I2S_TX_WFULL_INT_CLR_V << I2S_TX_WFULL_INT_CLR_S) +#define I2S_TX_WFULL_INT_CLR_V 0x00000001 +#define I2S_TX_WFULL_INT_CLR_S 4 + +/* I2S_RX_REMPTY_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_rx_rempty_int interrupt + */ + +#define I2S_RX_REMPTY_INT_CLR (BIT(3)) +#define I2S_RX_REMPTY_INT_CLR_M (I2S_RX_REMPTY_INT_CLR_V << I2S_RX_REMPTY_INT_CLR_S) +#define I2S_RX_REMPTY_INT_CLR_V 0x00000001 +#define I2S_RX_REMPTY_INT_CLR_S 3 + +/* I2S_RX_WFULL_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_wfull_int interrupt + */ + +#define I2S_RX_WFULL_INT_CLR (BIT(2)) +#define I2S_RX_WFULL_INT_CLR_M (I2S_RX_WFULL_INT_CLR_V << I2S_RX_WFULL_INT_CLR_S) +#define I2S_RX_WFULL_INT_CLR_V 0x00000001 +#define I2S_RX_WFULL_INT_CLR_S 2 + +/* I2S_PUT_DATA_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_put_data_int interrupt + */ + +#define I2S_PUT_DATA_INT_CLR (BIT(1)) +#define I2S_PUT_DATA_INT_CLR_M (I2S_PUT_DATA_INT_CLR_V << I2S_PUT_DATA_INT_CLR_S) +#define I2S_PUT_DATA_INT_CLR_V 0x00000001 +#define I2S_PUT_DATA_INT_CLR_S 1 + +/* I2S_TAKE_DATA_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_take_data_int interrupt + */ + +#define I2S_TAKE_DATA_INT_CLR (BIT(0)) +#define I2S_TAKE_DATA_INT_CLR_M (I2S_TAKE_DATA_INT_CLR_V << I2S_TAKE_DATA_INT_CLR_S) +#define I2S_TAKE_DATA_INT_CLR_V 0x00000001 +#define I2S_TAKE_DATA_INT_CLR_S 0 + +/* I2S_TIMING_REG register + * I2S timing register + */ + +#define I2S_TIMING_REG (DR_REG_I2S_BASE + 0x1c) + +/* I2S_TX_BCK_IN_INV : R/W; bitpos: [24]; default: 0; + * Set this bit to invert BCK signal input to the slave transmitter + */ + +#define I2S_TX_BCK_IN_INV (BIT(24)) +#define I2S_TX_BCK_IN_INV_M (I2S_TX_BCK_IN_INV_V << I2S_TX_BCK_IN_INV_S) +#define I2S_TX_BCK_IN_INV_V 0x00000001 +#define I2S_TX_BCK_IN_INV_S 24 + +/* I2S_DATA_ENABLE_DELAY : R/W; bitpos: [23:22]; default: 0; + * Number of delay cycles for data valid flag. + */ + +#define I2S_DATA_ENABLE_DELAY 0x00000003 +#define I2S_DATA_ENABLE_DELAY_M (I2S_DATA_ENABLE_DELAY_V << I2S_DATA_ENABLE_DELAY_S) +#define I2S_DATA_ENABLE_DELAY_V 0x00000003 +#define I2S_DATA_ENABLE_DELAY_S 22 + +/* I2S_RX_DSYNC_SW : R/W; bitpos: [21]; default: 0; + * Set this bit to synchronize signals with the double sync method into the + * receiver + */ + +#define I2S_RX_DSYNC_SW (BIT(21)) +#define I2S_RX_DSYNC_SW_M (I2S_RX_DSYNC_SW_V << I2S_RX_DSYNC_SW_S) +#define I2S_RX_DSYNC_SW_V 0x00000001 +#define I2S_RX_DSYNC_SW_S 21 + +/* I2S_TX_DSYNC_SW : R/W; bitpos: [20]; default: 0; + * Set this bit to synchronize signals with the double sync method into the + * transmitter + */ + +#define I2S_TX_DSYNC_SW (BIT(20)) +#define I2S_TX_DSYNC_SW_M (I2S_TX_DSYNC_SW_V << I2S_TX_DSYNC_SW_S) +#define I2S_TX_DSYNC_SW_V 0x00000001 +#define I2S_TX_DSYNC_SW_S 20 + +/* I2S_RX_BCK_OUT_DELAY : R/W; bitpos: [19:18]; default: 0; + * Number of delay cycles for BCK out of the receiver + */ + +#define I2S_RX_BCK_OUT_DELAY 0x00000003 +#define I2S_RX_BCK_OUT_DELAY_M (I2S_RX_BCK_OUT_DELAY_V << I2S_RX_BCK_OUT_DELAY_S) +#define I2S_RX_BCK_OUT_DELAY_V 0x00000003 +#define I2S_RX_BCK_OUT_DELAY_S 18 + +/* I2S_RX_WS_OUT_DELAY : R/W; bitpos: [17:16]; default: 0; + * Number of delay cycles for WS out of the receiver + */ + +#define I2S_RX_WS_OUT_DELAY 0x00000003 +#define I2S_RX_WS_OUT_DELAY_M (I2S_RX_WS_OUT_DELAY_V << I2S_RX_WS_OUT_DELAY_S) +#define I2S_RX_WS_OUT_DELAY_V 0x00000003 +#define I2S_RX_WS_OUT_DELAY_S 16 + +/* I2S_TX_SD_OUT_DELAY : R/W; bitpos: [15:14]; default: 0; + * Number of delay cycles for SD out of the transmitter + */ + +#define I2S_TX_SD_OUT_DELAY 0x00000003 +#define I2S_TX_SD_OUT_DELAY_M (I2S_TX_SD_OUT_DELAY_V << I2S_TX_SD_OUT_DELAY_S) +#define I2S_TX_SD_OUT_DELAY_V 0x00000003 +#define I2S_TX_SD_OUT_DELAY_S 14 + +/* I2S_TX_WS_OUT_DELAY : R/W; bitpos: [13:12]; default: 0; + * Number of delay cycles for WS out of the transmitter + */ + +#define I2S_TX_WS_OUT_DELAY 0x00000003 +#define I2S_TX_WS_OUT_DELAY_M (I2S_TX_WS_OUT_DELAY_V << I2S_TX_WS_OUT_DELAY_S) +#define I2S_TX_WS_OUT_DELAY_V 0x00000003 +#define I2S_TX_WS_OUT_DELAY_S 12 + +/* I2S_TX_BCK_OUT_DELAY : R/W; bitpos: [11:10]; default: 0; + * Number of delay cycles for BCK out of the transmitter + */ + +#define I2S_TX_BCK_OUT_DELAY 0x00000003 +#define I2S_TX_BCK_OUT_DELAY_M (I2S_TX_BCK_OUT_DELAY_V << I2S_TX_BCK_OUT_DELAY_S) +#define I2S_TX_BCK_OUT_DELAY_V 0x00000003 +#define I2S_TX_BCK_OUT_DELAY_S 10 + +/* I2S_RX_SD_IN_DELAY : R/W; bitpos: [9:8]; default: 0; + * Number of delay cycles for SD into the receiver + */ + +#define I2S_RX_SD_IN_DELAY 0x00000003 +#define I2S_RX_SD_IN_DELAY_M (I2S_RX_SD_IN_DELAY_V << I2S_RX_SD_IN_DELAY_S) +#define I2S_RX_SD_IN_DELAY_V 0x00000003 +#define I2S_RX_SD_IN_DELAY_S 8 + +/* I2S_RX_WS_IN_DELAY : R/W; bitpos: [7:6]; default: 0; + * Number of delay cycles for WS into the receiver + */ + +#define I2S_RX_WS_IN_DELAY 0x00000003 +#define I2S_RX_WS_IN_DELAY_M (I2S_RX_WS_IN_DELAY_V << I2S_RX_WS_IN_DELAY_S) +#define I2S_RX_WS_IN_DELAY_V 0x00000003 +#define I2S_RX_WS_IN_DELAY_S 6 + +/* I2S_RX_BCK_IN_DELAY : R/W; bitpos: [5:4]; default: 0; + * Number of delay cycles for BCK into the receiver + */ + +#define I2S_RX_BCK_IN_DELAY 0x00000003 +#define I2S_RX_BCK_IN_DELAY_M (I2S_RX_BCK_IN_DELAY_V << I2S_RX_BCK_IN_DELAY_S) +#define I2S_RX_BCK_IN_DELAY_V 0x00000003 +#define I2S_RX_BCK_IN_DELAY_S 4 + +/* I2S_TX_WS_IN_DELAY : R/W; bitpos: [3:2]; default: 0; + * Number of delay cycles for WS into the transmitter + */ + +#define I2S_TX_WS_IN_DELAY 0x00000003 +#define I2S_TX_WS_IN_DELAY_M (I2S_TX_WS_IN_DELAY_V << I2S_TX_WS_IN_DELAY_S) +#define I2S_TX_WS_IN_DELAY_V 0x00000003 +#define I2S_TX_WS_IN_DELAY_S 2 + +/* I2S_TX_BCK_IN_DELAY : R/W; bitpos: [1:0]; default: 0; + * Number of delay cycles for BCK into the transmitter + */ + +#define I2S_TX_BCK_IN_DELAY 0x00000003 +#define I2S_TX_BCK_IN_DELAY_M (I2S_TX_BCK_IN_DELAY_V << I2S_TX_BCK_IN_DELAY_S) +#define I2S_TX_BCK_IN_DELAY_V 0x00000003 +#define I2S_TX_BCK_IN_DELAY_S 0 + +/* I2S_FIFO_CONF_REG register + * I2S FIFO configure register + */ + +#define I2S_FIFO_CONF_REG (DR_REG_I2S_BASE + 0x20) + +/* I2S_TX_24MSB_EN : R/W; bitpos: [23]; default: 0; + * Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s + * fifo 0: the low 24 bits are effective in i2s fifo + */ + +#define I2S_TX_24MSB_EN (BIT(23)) +#define I2S_TX_24MSB_EN_M (I2S_TX_24MSB_EN_V << I2S_TX_24MSB_EN_S) +#define I2S_TX_24MSB_EN_V 0x00000001 +#define I2S_TX_24MSB_EN_S 23 + +/* I2S_RX_24MSB_EN : R/W; bitpos: [22]; default: 0; + * Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s + * fifo 0: the low 24 bits are effective in i2s fifo + */ + +#define I2S_RX_24MSB_EN (BIT(22)) +#define I2S_RX_24MSB_EN_M (I2S_RX_24MSB_EN_V << I2S_RX_24MSB_EN_S) +#define I2S_RX_24MSB_EN_V 0x00000001 +#define I2S_RX_24MSB_EN_S 22 + +/* I2S_RX_FIFO_SYNC : R/W; bitpos: [21]; default: 0; + * force write back rx data to memory + */ + +#define I2S_RX_FIFO_SYNC (BIT(21)) +#define I2S_RX_FIFO_SYNC_M (I2S_RX_FIFO_SYNC_V << I2S_RX_FIFO_SYNC_S) +#define I2S_RX_FIFO_SYNC_V 0x00000001 +#define I2S_RX_FIFO_SYNC_S 21 + +/* I2S_RX_FIFO_MOD_FORCE_EN : R/W; bitpos: [20]; default: 0; + * The bit should always be set to 1 + */ + +#define I2S_RX_FIFO_MOD_FORCE_EN (BIT(20)) +#define I2S_RX_FIFO_MOD_FORCE_EN_M (I2S_RX_FIFO_MOD_FORCE_EN_V << I2S_RX_FIFO_MOD_FORCE_EN_S) +#define I2S_RX_FIFO_MOD_FORCE_EN_V 0x00000001 +#define I2S_RX_FIFO_MOD_FORCE_EN_S 20 + +/* I2S_TX_FIFO_MOD_FORCE_EN : R/W; bitpos: [19]; default: 0; + * The bit should always be set to 1 + */ + +#define I2S_TX_FIFO_MOD_FORCE_EN (BIT(19)) +#define I2S_TX_FIFO_MOD_FORCE_EN_M (I2S_TX_FIFO_MOD_FORCE_EN_V << I2S_TX_FIFO_MOD_FORCE_EN_S) +#define I2S_TX_FIFO_MOD_FORCE_EN_V 0x00000001 +#define I2S_TX_FIFO_MOD_FORCE_EN_S 19 + +/* I2S_RX_FIFO_MOD : R/W; bitpos: [18:16]; default: 0; + * Receiver FIFO mode configuration bits + */ + +#define I2S_RX_FIFO_MOD 0x00000007 +#define I2S_RX_FIFO_MOD_M (I2S_RX_FIFO_MOD_V << I2S_RX_FIFO_MOD_S) +#define I2S_RX_FIFO_MOD_V 0x00000007 +#define I2S_RX_FIFO_MOD_S 16 + +/* I2S_TX_FIFO_MOD : R/W; bitpos: [15:13]; default: 0; + * Transmitter FIFO mode configuration bits + */ + +#define I2S_TX_FIFO_MOD 0x00000007 +#define I2S_TX_FIFO_MOD_M (I2S_TX_FIFO_MOD_V << I2S_TX_FIFO_MOD_S) +#define I2S_TX_FIFO_MOD_V 0x00000007 +#define I2S_TX_FIFO_MOD_S 13 + +/* I2S_DSCR_EN : R/W; bitpos: [12]; default: 1; + * Set this bit to enable I2S DMA mode + */ + +#define I2S_DSCR_EN (BIT(12)) +#define I2S_DSCR_EN_M (I2S_DSCR_EN_V << I2S_DSCR_EN_S) +#define I2S_DSCR_EN_V 0x00000001 +#define I2S_DSCR_EN_S 12 + +/* I2S_TX_DATA_NUM : R/W; bitpos: [11:6]; default: 32; + * Threshold of data length in transmitter FIFO + */ + +#define I2S_TX_DATA_NUM 0x0000003F +#define I2S_TX_DATA_NUM_M (I2S_TX_DATA_NUM_V << I2S_TX_DATA_NUM_S) +#define I2S_TX_DATA_NUM_V 0x0000003F +#define I2S_TX_DATA_NUM_S 6 + +/* I2S_RX_DATA_NUM : R/W; bitpos: [5:0]; default: 32; + * Threshold of data length in receiver FIFO + */ + +#define I2S_RX_DATA_NUM 0x0000003F +#define I2S_RX_DATA_NUM_M (I2S_RX_DATA_NUM_V << I2S_RX_DATA_NUM_S) +#define I2S_RX_DATA_NUM_V 0x0000003F +#define I2S_RX_DATA_NUM_S 0 + +/* I2S_RXEOF_NUM_REG register + * I2S DMA RX EOF data length + */ + +#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x24) + +/* I2S_RX_EOF_NUM : R/W; bitpos: [31:0]; default: 64; + * the length of data to be received. It will trigger i2s_in_suc_eof_int. + */ + +#define I2S_RX_EOF_NUM 0xFFFFFFFF +#define I2S_RX_EOF_NUM_M (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S) +#define I2S_RX_EOF_NUM_V 0xFFFFFFFF +#define I2S_RX_EOF_NUM_S 0 + +/* I2S_CONF_SIGLE_DATA_REG register + * Constant single channel data + */ + +#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x28) + +/* I2S_SIGLE_DATA : R/W; bitpos: [31:0]; default: 0; + * the right channel or left channel put out constant value stored in this + * register according to tx_chan_mod and reg_tx_msb_right + */ + +#define I2S_SIGLE_DATA 0xFFFFFFFF +#define I2S_SIGLE_DATA_M (I2S_SIGLE_DATA_V << I2S_SIGLE_DATA_S) +#define I2S_SIGLE_DATA_V 0xFFFFFFFF +#define I2S_SIGLE_DATA_S 0 + +/* I2S_CONF_CHAN_REG register + * I2S channel configure register + */ + +#define I2S_CONF_CHAN_REG (DR_REG_I2S_BASE + 0x2c) + +/* I2S_RX_CHAN_MOD : R/W; bitpos: [4:3]; default: 0; + * I2S receiver channel mode configuration bits. + */ + +#define I2S_RX_CHAN_MOD 0x00000003 +#define I2S_RX_CHAN_MOD_M (I2S_RX_CHAN_MOD_V << I2S_RX_CHAN_MOD_S) +#define I2S_RX_CHAN_MOD_V 0x00000003 +#define I2S_RX_CHAN_MOD_S 3 + +/* I2S_TX_CHAN_MOD : R/W; bitpos: [2:0]; default: 0; + * I2S transmitter channel mode configuration bits. + */ + +#define I2S_TX_CHAN_MOD 0x00000007 +#define I2S_TX_CHAN_MOD_M (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S) +#define I2S_TX_CHAN_MOD_V 0x00000007 +#define I2S_TX_CHAN_MOD_S 0 + +/* I2S_OUT_LINK_REG register + * I2S DMA TX configure register + */ + +#define I2S_OUT_LINK_REG (DR_REG_I2S_BASE + 0x30) + +/* I2S_OUTLINK_PARK : RO; bitpos: [31]; default: 0; */ + +#define I2S_OUTLINK_PARK (BIT(31)) +#define I2S_OUTLINK_PARK_M (I2S_OUTLINK_PARK_V << I2S_OUTLINK_PARK_S) +#define I2S_OUTLINK_PARK_V 0x00000001 +#define I2S_OUTLINK_PARK_S 31 + +/* I2S_OUTLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set this bit to restart outlink descriptor + */ + +#define I2S_OUTLINK_RESTART (BIT(30)) +#define I2S_OUTLINK_RESTART_M (I2S_OUTLINK_RESTART_V << I2S_OUTLINK_RESTART_S) +#define I2S_OUTLINK_RESTART_V 0x00000001 +#define I2S_OUTLINK_RESTART_S 30 + +/* I2S_OUTLINK_START : R/W; bitpos: [29]; default: 0; + * Set this bit to start outlink descriptor + */ + +#define I2S_OUTLINK_START (BIT(29)) +#define I2S_OUTLINK_START_M (I2S_OUTLINK_START_V << I2S_OUTLINK_START_S) +#define I2S_OUTLINK_START_V 0x00000001 +#define I2S_OUTLINK_START_S 29 + +/* I2S_OUTLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set this bit to stop outlink descriptor + */ + +#define I2S_OUTLINK_STOP (BIT(28)) +#define I2S_OUTLINK_STOP_M (I2S_OUTLINK_STOP_V << I2S_OUTLINK_STOP_S) +#define I2S_OUTLINK_STOP_V 0x00000001 +#define I2S_OUTLINK_STOP_S 28 + +/* I2S_OUTLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * The address of first outlink descriptor + */ + +#define I2S_OUTLINK_ADDR 0x000FFFFF +#define I2S_OUTLINK_ADDR_M (I2S_OUTLINK_ADDR_V << I2S_OUTLINK_ADDR_S) +#define I2S_OUTLINK_ADDR_V 0x000FFFFF +#define I2S_OUTLINK_ADDR_S 0 + +/* I2S_IN_LINK_REG register + * I2S DMA RX configure register + */ + +#define I2S_IN_LINK_REG (DR_REG_I2S_BASE + 0x34) + +/* I2S_INLINK_PARK : RO; bitpos: [31]; default: 0; */ + +#define I2S_INLINK_PARK (BIT(31)) +#define I2S_INLINK_PARK_M (I2S_INLINK_PARK_V << I2S_INLINK_PARK_S) +#define I2S_INLINK_PARK_V 0x00000001 +#define I2S_INLINK_PARK_S 31 + +/* I2S_INLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set this bit to restart inlink descriptor + */ + +#define I2S_INLINK_RESTART (BIT(30)) +#define I2S_INLINK_RESTART_M (I2S_INLINK_RESTART_V << I2S_INLINK_RESTART_S) +#define I2S_INLINK_RESTART_V 0x00000001 +#define I2S_INLINK_RESTART_S 30 + +/* I2S_INLINK_START : R/W; bitpos: [29]; default: 0; + * Set this bit to start inlink descriptor + */ + +#define I2S_INLINK_START (BIT(29)) +#define I2S_INLINK_START_M (I2S_INLINK_START_V << I2S_INLINK_START_S) +#define I2S_INLINK_START_V 0x00000001 +#define I2S_INLINK_START_S 29 + +/* I2S_INLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set this bit to stop inlink descriptor + */ + +#define I2S_INLINK_STOP (BIT(28)) +#define I2S_INLINK_STOP_M (I2S_INLINK_STOP_V << I2S_INLINK_STOP_S) +#define I2S_INLINK_STOP_V 0x00000001 +#define I2S_INLINK_STOP_S 28 + +/* I2S_INLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * The address of first inlink descriptor + */ + +#define I2S_INLINK_ADDR 0x000FFFFF +#define I2S_INLINK_ADDR_M (I2S_INLINK_ADDR_V << I2S_INLINK_ADDR_S) +#define I2S_INLINK_ADDR_V 0x000FFFFF +#define I2S_INLINK_ADDR_S 0 + +/* I2S_OUT_EOF_DES_ADDR_REG register + * The address of outlink descriptor that produces EOF + */ + +#define I2S_OUT_EOF_DES_ADDR_REG (DR_REG_I2S_BASE + 0x38) + +/* I2S_OUT_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The address of outlink descriptor that produces EOF + */ + +#define I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define I2S_OUT_EOF_DES_ADDR_M (I2S_OUT_EOF_DES_ADDR_V << I2S_OUT_EOF_DES_ADDR_S) +#define I2S_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define I2S_OUT_EOF_DES_ADDR_S 0 + +/* I2S_IN_EOF_DES_ADDR_REG register + * The address of inlink descriptor that produces EOF + */ + +#define I2S_IN_EOF_DES_ADDR_REG (DR_REG_I2S_BASE + 0x3c) + +/* I2S_IN_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The address of inlink descriptor that produces EOF + */ + +#define I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define I2S_IN_SUC_EOF_DES_ADDR_M (I2S_IN_SUC_EOF_DES_ADDR_V << I2S_IN_SUC_EOF_DES_ADDR_S) +#define I2S_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define I2S_IN_SUC_EOF_DES_ADDR_S 0 + +/* I2S_OUT_EOF_BFR_DES_ADDR_REG register + * The address of buffer relative to the outlink descriptor that produces EOF + */ + +#define I2S_OUT_EOF_BFR_DES_ADDR_REG (DR_REG_I2S_BASE + 0x40) + +/* I2S_OUT_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The address of buffer relative to the outlink descriptor that produces EOF + */ + +#define I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define I2S_OUT_EOF_BFR_DES_ADDR_M (I2S_OUT_EOF_BFR_DES_ADDR_V << I2S_OUT_EOF_BFR_DES_ADDR_S) +#define I2S_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define I2S_OUT_EOF_BFR_DES_ADDR_S 0 + +/* I2S_INLINK_DSCR_REG register + * The address of current inlink descriptor + */ + +#define I2S_INLINK_DSCR_REG (DR_REG_I2S_BASE + 0x48) + +/* I2S_INLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The address of current inlink descriptor + */ + +#define I2S_INLINK_DSCR 0xFFFFFFFF +#define I2S_INLINK_DSCR_M (I2S_INLINK_DSCR_V << I2S_INLINK_DSCR_S) +#define I2S_INLINK_DSCR_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_S 0 + +/* I2S_INLINK_DSCR_BF0_REG register + * The address of next inlink descriptor + */ + +#define I2S_INLINK_DSCR_BF0_REG (DR_REG_I2S_BASE + 0x4c) + +/* I2S_INLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The address of next inlink descriptor + */ + +#define I2S_INLINK_DSCR_BF0 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF0_M (I2S_INLINK_DSCR_BF0_V << I2S_INLINK_DSCR_BF0_S) +#define I2S_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF0_S 0 + +/* I2S_INLINK_DSCR_BF1_REG register + * The address of next inlink data buffer + */ + +#define I2S_INLINK_DSCR_BF1_REG (DR_REG_I2S_BASE + 0x50) + +/* I2S_INLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The address of next inlink data buffer + */ + +#define I2S_INLINK_DSCR_BF1 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF1_M (I2S_INLINK_DSCR_BF1_V << I2S_INLINK_DSCR_BF1_S) +#define I2S_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF1_S 0 + +/* I2S_OUTLINK_DSCR_REG register + * The address of current outlink descriptor + */ + +#define I2S_OUTLINK_DSCR_REG (DR_REG_I2S_BASE + 0x54) + +/* I2S_OUTLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The address of current outlink descriptor + */ + +#define I2S_OUTLINK_DSCR 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_M (I2S_OUTLINK_DSCR_V << I2S_OUTLINK_DSCR_S) +#define I2S_OUTLINK_DSCR_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_S 0 + +/* I2S_OUTLINK_DSCR_BF0_REG register + * The address of next outlink descriptor + */ + +#define I2S_OUTLINK_DSCR_BF0_REG (DR_REG_I2S_BASE + 0x58) + +/* I2S_OUTLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The address of next outlink descriptor + */ + +#define I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF0_M (I2S_OUTLINK_DSCR_BF0_V << I2S_OUTLINK_DSCR_BF0_S) +#define I2S_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF0_S 0 + +/* I2S_OUTLINK_DSCR_BF1_REG register + * The address of next outlink data buffer + */ + +#define I2S_OUTLINK_DSCR_BF1_REG (DR_REG_I2S_BASE + 0x5c) + +/* I2S_OUTLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The address of next outlink data buffer + */ + +#define I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF1_M (I2S_OUTLINK_DSCR_BF1_V << I2S_OUTLINK_DSCR_BF1_S) +#define I2S_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF1_S 0 + +/* I2S_LC_CONF_REG register + * I2S DMA configuration register + */ + +#define I2S_LC_CONF_REG (DR_REG_I2S_BASE + 0x60) + +/* I2S_EXT_MEM_BK_SIZE : R/W; bitpos: [15:14]; default: 0; + * DMA access external memory block size. 0: 16 bytes 1: 32 bytes + * 2:64 bytes 3:reserved + */ + +#define I2S_EXT_MEM_BK_SIZE 0x00000003 +#define I2S_EXT_MEM_BK_SIZE_M (I2S_EXT_MEM_BK_SIZE_V << I2S_EXT_MEM_BK_SIZE_S) +#define I2S_EXT_MEM_BK_SIZE_V 0x00000003 +#define I2S_EXT_MEM_BK_SIZE_S 14 + +/* I2S_MEM_TRANS_EN : R/W; bitpos: [13]; default: 0; + * don't use + */ + +#define I2S_MEM_TRANS_EN (BIT(13)) +#define I2S_MEM_TRANS_EN_M (I2S_MEM_TRANS_EN_V << I2S_MEM_TRANS_EN_S) +#define I2S_MEM_TRANS_EN_V 0x00000001 +#define I2S_MEM_TRANS_EN_S 13 + +/* I2S_CHECK_OWNER : R/W; bitpos: [12]; default: 0; + * Set this bit to enable check owner bit by hardware + */ + +#define I2S_CHECK_OWNER (BIT(12)) +#define I2S_CHECK_OWNER_M (I2S_CHECK_OWNER_V << I2S_CHECK_OWNER_S) +#define I2S_CHECK_OWNER_V 0x00000001 +#define I2S_CHECK_OWNER_S 12 + +/* I2S_OUT_DATA_BURST_EN : R/W; bitpos: [11]; default: 0; + * Transmitter data transfer mode configuration bit. 1: to prepare out data + * with burst mode 0: to prepare out data with byte mode + */ + +#define I2S_OUT_DATA_BURST_EN (BIT(11)) +#define I2S_OUT_DATA_BURST_EN_M (I2S_OUT_DATA_BURST_EN_V << I2S_OUT_DATA_BURST_EN_S) +#define I2S_OUT_DATA_BURST_EN_V 0x00000001 +#define I2S_OUT_DATA_BURST_EN_S 11 + +/* I2S_INDSCR_BURST_EN : R/W; bitpos: [10]; default: 0; + * DMA inlink descriptor transfer mode configuration bit. 1: to prepare + * inlink descriptor with burst mode 0: to prepare inlink descriptor with + * byte mode + */ + +#define I2S_INDSCR_BURST_EN (BIT(10)) +#define I2S_INDSCR_BURST_EN_M (I2S_INDSCR_BURST_EN_V << I2S_INDSCR_BURST_EN_S) +#define I2S_INDSCR_BURST_EN_V 0x00000001 +#define I2S_INDSCR_BURST_EN_S 10 + +/* I2S_OUTDSCR_BURST_EN : R/W; bitpos: [9]; default: 0; + * DMA outlink descriptor transfer mode configuration bit. 1: to prepare + * outlink descriptor with burst mode 0: to prepare outlink descriptor + * with byte mode + */ + +#define I2S_OUTDSCR_BURST_EN (BIT(9)) +#define I2S_OUTDSCR_BURST_EN_M (I2S_OUTDSCR_BURST_EN_V << I2S_OUTDSCR_BURST_EN_S) +#define I2S_OUTDSCR_BURST_EN_V 0x00000001 +#define I2S_OUTDSCR_BURST_EN_S 9 + +/* I2S_OUT_EOF_MODE : R/W; bitpos: [8]; default: 1; + * DMA out EOF flag generation mode . 1: when dma has popped all data from + * the FIFO 0:when ahb has pushed all data to the FIFO + */ + +#define I2S_OUT_EOF_MODE (BIT(8)) +#define I2S_OUT_EOF_MODE_M (I2S_OUT_EOF_MODE_V << I2S_OUT_EOF_MODE_S) +#define I2S_OUT_EOF_MODE_V 0x00000001 +#define I2S_OUT_EOF_MODE_S 8 + +/* I2S_OUT_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0; + * don't use + */ + +#define I2S_OUT_NO_RESTART_CLR (BIT(7)) +#define I2S_OUT_NO_RESTART_CLR_M (I2S_OUT_NO_RESTART_CLR_V << I2S_OUT_NO_RESTART_CLR_S) +#define I2S_OUT_NO_RESTART_CLR_V 0x00000001 +#define I2S_OUT_NO_RESTART_CLR_S 7 + +/* I2S_OUT_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; + * Set this bit to enable outlink-written-back automatically when out buffer + * is transmitted done. + */ + +#define I2S_OUT_AUTO_WRBACK (BIT(6)) +#define I2S_OUT_AUTO_WRBACK_M (I2S_OUT_AUTO_WRBACK_V << I2S_OUT_AUTO_WRBACK_S) +#define I2S_OUT_AUTO_WRBACK_V 0x00000001 +#define I2S_OUT_AUTO_WRBACK_S 6 + +/* I2S_IN_LOOP_TEST : R/W; bitpos: [5]; default: 0; + * Set this bit to loop test outlink + */ + +#define I2S_IN_LOOP_TEST (BIT(5)) +#define I2S_IN_LOOP_TEST_M (I2S_IN_LOOP_TEST_V << I2S_IN_LOOP_TEST_S) +#define I2S_IN_LOOP_TEST_V 0x00000001 +#define I2S_IN_LOOP_TEST_S 5 + +/* I2S_OUT_LOOP_TEST : R/W; bitpos: [4]; default: 0; + * Set this bit to loop test inlink + */ + +#define I2S_OUT_LOOP_TEST (BIT(4)) +#define I2S_OUT_LOOP_TEST_M (I2S_OUT_LOOP_TEST_V << I2S_OUT_LOOP_TEST_S) +#define I2S_OUT_LOOP_TEST_V 0x00000001 +#define I2S_OUT_LOOP_TEST_S 4 + +/* I2S_AHBM_RST : R/W; bitpos: [3]; default: 0; + * Set this bit to reset ahb interface of DMA + */ + +#define I2S_AHBM_RST (BIT(3)) +#define I2S_AHBM_RST_M (I2S_AHBM_RST_V << I2S_AHBM_RST_S) +#define I2S_AHBM_RST_V 0x00000001 +#define I2S_AHBM_RST_S 3 + +/* I2S_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0; + * Set this bit to reset ahb interface cmdFIFO of DMA + */ + +#define I2S_AHBM_FIFO_RST (BIT(2)) +#define I2S_AHBM_FIFO_RST_M (I2S_AHBM_FIFO_RST_V << I2S_AHBM_FIFO_RST_S) +#define I2S_AHBM_FIFO_RST_V 0x00000001 +#define I2S_AHBM_FIFO_RST_S 2 + +/* I2S_OUT_RST : R/W; bitpos: [1]; default: 0; + * Set this bit to reset out dma FSM + */ + +#define I2S_OUT_RST (BIT(1)) +#define I2S_OUT_RST_M (I2S_OUT_RST_V << I2S_OUT_RST_S) +#define I2S_OUT_RST_V 0x00000001 +#define I2S_OUT_RST_S 1 + +/* I2S_IN_RST : R/W; bitpos: [0]; default: 0; + * Set this bit to reset in dma FSM + */ + +#define I2S_IN_RST (BIT(0)) +#define I2S_IN_RST_M (I2S_IN_RST_V << I2S_IN_RST_S) +#define I2S_IN_RST_V 0x00000001 +#define I2S_IN_RST_S 0 + +/* I2S_OUTFIFO_PUSH_REG register + * APB out FIFO mode register + */ + +#define I2S_OUTFIFO_PUSH_REG (DR_REG_I2S_BASE + 0x64) + +/* I2S_OUTFIFO_PUSH : R/W; bitpos: [16]; default: 0; + * APB out FIFO push. + */ + +#define I2S_OUTFIFO_PUSH (BIT(16)) +#define I2S_OUTFIFO_PUSH_M (I2S_OUTFIFO_PUSH_V << I2S_OUTFIFO_PUSH_S) +#define I2S_OUTFIFO_PUSH_V 0x00000001 +#define I2S_OUTFIFO_PUSH_S 16 + +/* I2S_OUTFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * APB out FIFO write data. + */ + +#define I2S_OUTFIFO_WDATA 0x000001FF +#define I2S_OUTFIFO_WDATA_M (I2S_OUTFIFO_WDATA_V << I2S_OUTFIFO_WDATA_S) +#define I2S_OUTFIFO_WDATA_V 0x000001FF +#define I2S_OUTFIFO_WDATA_S 0 + +/* I2S_INFIFO_POP_REG register + * APB in FIFO mode register + */ + +#define I2S_INFIFO_POP_REG (DR_REG_I2S_BASE + 0x68) + +/* I2S_INFIFO_POP : R/W; bitpos: [16]; default: 0; + * APB in FIFO pop. + */ + +#define I2S_INFIFO_POP (BIT(16)) +#define I2S_INFIFO_POP_M (I2S_INFIFO_POP_V << I2S_INFIFO_POP_S) +#define I2S_INFIFO_POP_V 0x00000001 +#define I2S_INFIFO_POP_S 16 + +/* I2S_INFIFO_RDATA : RO; bitpos: [11:0]; default: 0; + * APB in FIFO read data. + */ + +#define I2S_INFIFO_RDATA 0x00000FFF +#define I2S_INFIFO_RDATA_M (I2S_INFIFO_RDATA_V << I2S_INFIFO_RDATA_S) +#define I2S_INFIFO_RDATA_V 0x00000FFF +#define I2S_INFIFO_RDATA_S 0 + +/* I2S_LC_STATE0_REG register + * I2S DMA TX status + */ + +#define I2S_LC_STATE0_REG (DR_REG_I2S_BASE + 0x6c) + +/* I2S_OUT_EMPTY : RO; bitpos: [31]; default: 0; + * I2S DMA outfifo is empty. + */ + +#define I2S_OUT_EMPTY (BIT(31)) +#define I2S_OUT_EMPTY_M (I2S_OUT_EMPTY_V << I2S_OUT_EMPTY_S) +#define I2S_OUT_EMPTY_V 0x00000001 +#define I2S_OUT_EMPTY_S 31 + +/* I2S_OUT_FULL : RO; bitpos: [30]; default: 0; + * I2S DMA outfifo is full. + */ + +#define I2S_OUT_FULL (BIT(30)) +#define I2S_OUT_FULL_M (I2S_OUT_FULL_V << I2S_OUT_FULL_S) +#define I2S_OUT_FULL_V 0x00000001 +#define I2S_OUT_FULL_S 30 + +/* I2S_OUTFIFO_CNT : RO; bitpos: [29:23]; default: 0; + * The remains of I2S DMA outfifo data. + */ + +#define I2S_OUTFIFO_CNT 0x0000007F +#define I2S_OUTFIFO_CNT_M (I2S_OUTFIFO_CNT_V << I2S_OUTFIFO_CNT_S) +#define I2S_OUTFIFO_CNT_V 0x0000007F +#define I2S_OUTFIFO_CNT_S 23 + +/* I2S_OUT_STATE : RO; bitpos: [22:20]; default: 0; + * I2S DMA out data state. + */ + +#define I2S_OUT_STATE 0x00000007 +#define I2S_OUT_STATE_M (I2S_OUT_STATE_V << I2S_OUT_STATE_S) +#define I2S_OUT_STATE_V 0x00000007 +#define I2S_OUT_STATE_S 20 + +/* I2S_OUT_DSCR_STATE : RO; bitpos: [19:18]; default: 0; + * I2S DMA out descriptor state. + */ + +#define I2S_OUT_DSCR_STATE 0x00000003 +#define I2S_OUT_DSCR_STATE_M (I2S_OUT_DSCR_STATE_V << I2S_OUT_DSCR_STATE_S) +#define I2S_OUT_DSCR_STATE_V 0x00000003 +#define I2S_OUT_DSCR_STATE_S 18 + +/* I2S_OUTLINK_DSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * I2S DMA out descriptor address. + */ + +#define I2S_OUTLINK_DSCR_ADDR 0x0003FFFF +#define I2S_OUTLINK_DSCR_ADDR_M (I2S_OUTLINK_DSCR_ADDR_V << I2S_OUTLINK_DSCR_ADDR_S) +#define I2S_OUTLINK_DSCR_ADDR_V 0x0003FFFF +#define I2S_OUTLINK_DSCR_ADDR_S 0 + +/* I2S_LC_STATE1_REG register + * I2S DMA RX status + */ + +#define I2S_LC_STATE1_REG (DR_REG_I2S_BASE + 0x70) + +/* I2S_IN_EMPTY : RO; bitpos: [31]; default: 0; + * I2S DMA infifo is empty. + */ + +#define I2S_IN_EMPTY (BIT(31)) +#define I2S_IN_EMPTY_M (I2S_IN_EMPTY_V << I2S_IN_EMPTY_S) +#define I2S_IN_EMPTY_V 0x00000001 +#define I2S_IN_EMPTY_S 31 + +/* I2S_IN_FULL : RO; bitpos: [30]; default: 0; + * I2S DMA infifo is full. + */ + +#define I2S_IN_FULL (BIT(30)) +#define I2S_IN_FULL_M (I2S_IN_FULL_V << I2S_IN_FULL_S) +#define I2S_IN_FULL_V 0x00000001 +#define I2S_IN_FULL_S 30 + +/* I2S_INFIFO_CNT_DEBUG : RO; bitpos: [29:23]; default: 0; + * The remains of I2S DMA infifo data. + */ + +#define I2S_INFIFO_CNT_DEBUG 0x0000007F +#define I2S_INFIFO_CNT_DEBUG_M (I2S_INFIFO_CNT_DEBUG_V << I2S_INFIFO_CNT_DEBUG_S) +#define I2S_INFIFO_CNT_DEBUG_V 0x0000007F +#define I2S_INFIFO_CNT_DEBUG_S 23 + +/* I2S_IN_STATE : RO; bitpos: [22:20]; default: 0; + * I2S DMA in data state. + */ + +#define I2S_IN_STATE 0x00000007 +#define I2S_IN_STATE_M (I2S_IN_STATE_V << I2S_IN_STATE_S) +#define I2S_IN_STATE_V 0x00000007 +#define I2S_IN_STATE_S 20 + +/* I2S_IN_DSCR_STATE : RO; bitpos: [19:18]; default: 0; + * I2S DMA in descriptor state. + */ + +#define I2S_IN_DSCR_STATE 0x00000003 +#define I2S_IN_DSCR_STATE_M (I2S_IN_DSCR_STATE_V << I2S_IN_DSCR_STATE_S) +#define I2S_IN_DSCR_STATE_V 0x00000003 +#define I2S_IN_DSCR_STATE_S 18 + +/* I2S_INLINK_DSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * I2S DMA in descriptor address. + */ + +#define I2S_INLINK_DSCR_ADDR 0x0003FFFF +#define I2S_INLINK_DSCR_ADDR_M (I2S_INLINK_DSCR_ADDR_V << I2S_INLINK_DSCR_ADDR_S) +#define I2S_INLINK_DSCR_ADDR_V 0x0003FFFF +#define I2S_INLINK_DSCR_ADDR_S 0 + +/* I2S_LC_HUNG_CONF_REG register + * I2S Hung configure register + */ + +#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x74) + +/* I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ + +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001 +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 + +/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is + * reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ + +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 + +/* I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be + * triggered when fifo hung counter is equal to this value + */ + +#define I2S_LC_FIFO_TIMEOUT 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_M (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S) +#define I2S_LC_FIFO_TIMEOUT_V 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_S 0 + +/* I2S_CONF1 _REG register + * I2S configure1 register + */ + +#define I2S_CONF1 _REG (DR_REG_I2S_BASE + 0xa0) + +/* I2S_TX_ZEROS_RM_EN : R/W; bitpos: [9]; default: 0; + * don't use + */ + +#define I2S_TX_ZEROS_RM_EN (BIT(9)) +#define I2S_TX_ZEROS_RM_EN_M (I2S_TX_ZEROS_RM_EN_V << I2S_TX_ZEROS_RM_EN_S) +#define I2S_TX_ZEROS_RM_EN_V 0x00000001 +#define I2S_TX_ZEROS_RM_EN_S 9 + +/* I2S_TX_STOP_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO + * is emtpy + */ + +#define I2S_TX_STOP_EN (BIT(8)) +#define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) +#define I2S_TX_STOP_EN_V 0x00000001 +#define I2S_TX_STOP_EN_S 8 + +/* I2S_RX_PCM_BYPASS : R/W; bitpos: [7]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ + +#define I2S_RX_PCM_BYPASS (BIT(7)) +#define I2S_RX_PCM_BYPASS_M (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S) +#define I2S_RX_PCM_BYPASS_V 0x00000001 +#define I2S_RX_PCM_BYPASS_S 7 + +/* I2S_RX_PCM_CONF : R/W; bitpos: [6:4]; default: 0; + * Compress/Decompress module configuration bits. 0: decompress received + * data 1:compress received data + */ + +#define I2S_RX_PCM_CONF 0x00000007 +#define I2S_RX_PCM_CONF_M (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S) +#define I2S_RX_PCM_CONF_V 0x00000007 +#define I2S_RX_PCM_CONF_S 4 + +/* I2S_TX_PCM_BYPASS : R/W; bitpos: [3]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ + +#define I2S_TX_PCM_BYPASS (BIT(3)) +#define I2S_TX_PCM_BYPASS_M (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S) +#define I2S_TX_PCM_BYPASS_V 0x00000001 +#define I2S_TX_PCM_BYPASS_S 3 + +/* I2S_TX_PCM_CONF : R/W; bitpos: [2:0]; default: 1; + * Compress/Decompress module configuration bits. 0: decompress transmitted + * data 1:compress transmitted data + */ + +#define I2S_TX_PCM_CONF 0x00000007 +#define I2S_TX_PCM_CONF_M (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S) +#define I2S_TX_PCM_CONF_V 0x00000007 +#define I2S_TX_PCM_CONF_S 0 + +/* I2S_PD_CONF_REG register + * I2S power down configure register + */ + +#define I2S_PD_CONF_REG (DR_REG_I2S_BASE + 0xa4) + +/* I2S_DMA_RAM_CLK_FO : R/W; bitpos: [6]; default: 0; + * Set this bit to force on the DMA ram clock. + */ + +#define I2S_DMA_RAM_CLK_FO (BIT(6)) +#define I2S_DMA_RAM_CLK_FO_M (I2S_DMA_RAM_CLK_FO_V << I2S_DMA_RAM_CLK_FO_S) +#define I2S_DMA_RAM_CLK_FO_V 0x00000001 +#define I2S_DMA_RAM_CLK_FO_S 6 + +/* I2S_DMA_RAM_FORCE_PU : R/W; bitpos: [5]; default: 1; + * Force DMA FIFO power-up + */ + +#define I2S_DMA_RAM_FORCE_PU (BIT(5)) +#define I2S_DMA_RAM_FORCE_PU_M (I2S_DMA_RAM_FORCE_PU_V << I2S_DMA_RAM_FORCE_PU_S) +#define I2S_DMA_RAM_FORCE_PU_V 0x00000001 +#define I2S_DMA_RAM_FORCE_PU_S 5 + +/* I2S_DMA_RAM_FORCE_PD : R/W; bitpos: [4]; default: 0; + * Force DMA FIFO power-down + */ + +#define I2S_DMA_RAM_FORCE_PD (BIT(4)) +#define I2S_DMA_RAM_FORCE_PD_M (I2S_DMA_RAM_FORCE_PD_V << I2S_DMA_RAM_FORCE_PD_S) +#define I2S_DMA_RAM_FORCE_PD_V 0x00000001 +#define I2S_DMA_RAM_FORCE_PD_S 4 + +/* I2S_PLC_MEM_FORCE_PU : R/W; bitpos: [3]; default: 1; + * Force I2S memory power-up + */ + +#define I2S_PLC_MEM_FORCE_PU (BIT(3)) +#define I2S_PLC_MEM_FORCE_PU_M (I2S_PLC_MEM_FORCE_PU_V << I2S_PLC_MEM_FORCE_PU_S) +#define I2S_PLC_MEM_FORCE_PU_V 0x00000001 +#define I2S_PLC_MEM_FORCE_PU_S 3 + +/* I2S_PLC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Force I2S memory power-down + */ + +#define I2S_PLC_MEM_FORCE_PD (BIT(2)) +#define I2S_PLC_MEM_FORCE_PD_M (I2S_PLC_MEM_FORCE_PD_V << I2S_PLC_MEM_FORCE_PD_S) +#define I2S_PLC_MEM_FORCE_PD_V 0x00000001 +#define I2S_PLC_MEM_FORCE_PD_S 2 + +/* I2S_FIFO_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Force FIFO power-up + */ + +#define I2S_FIFO_FORCE_PU (BIT(1)) +#define I2S_FIFO_FORCE_PU_M (I2S_FIFO_FORCE_PU_V << I2S_FIFO_FORCE_PU_S) +#define I2S_FIFO_FORCE_PU_V 0x00000001 +#define I2S_FIFO_FORCE_PU_S 1 + +/* I2S_FIFO_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Force FIFO power-down + */ + +#define I2S_FIFO_FORCE_PD (BIT(0)) +#define I2S_FIFO_FORCE_PD_M (I2S_FIFO_FORCE_PD_V << I2S_FIFO_FORCE_PD_S) +#define I2S_FIFO_FORCE_PD_V 0x00000001 +#define I2S_FIFO_FORCE_PD_S 0 + +/* I2S_CONF2_REG register + * I2S configure2 register + */ + +#define I2S_CONF2_REG (DR_REG_I2S_BASE + 0xa8) + +/* I2S_VSYNC_FILTER_THRES : R/W; bitpos: [13:11]; default: 0; + * Configure the I2S VSYNC filter threshold value + */ + +#define I2S_VSYNC_FILTER_THRES 0x00000007 +#define I2S_VSYNC_FILTER_THRES_M (I2S_VSYNC_FILTER_THRES_V << I2S_VSYNC_FILTER_THRES_S) +#define I2S_VSYNC_FILTER_THRES_V 0x00000007 +#define I2S_VSYNC_FILTER_THRES_S 11 + +/* I2S_VSYNC_FILTER_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable I2S VSYNC filter function. + */ + +#define I2S_VSYNC_FILTER_EN (BIT(10)) +#define I2S_VSYNC_FILTER_EN_M (I2S_VSYNC_FILTER_EN_V << I2S_VSYNC_FILTER_EN_S) +#define I2S_VSYNC_FILTER_EN_V 0x00000001 +#define I2S_VSYNC_FILTER_EN_S 10 + +/* I2S_CAM_CLK_LOOPBACK : R/W; bitpos: [9]; default: 0; + * Set this bit to loopback cam_clk from i2s_rx + */ + +#define I2S_CAM_CLK_LOOPBACK (BIT(9)) +#define I2S_CAM_CLK_LOOPBACK_M (I2S_CAM_CLK_LOOPBACK_V << I2S_CAM_CLK_LOOPBACK_S) +#define I2S_CAM_CLK_LOOPBACK_V 0x00000001 +#define I2S_CAM_CLK_LOOPBACK_S 9 + +/* I2S_CAM_SYNC_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Set this bit to reset cam_sync_fifo + */ + +#define I2S_CAM_SYNC_FIFO_RESET (BIT(8)) +#define I2S_CAM_SYNC_FIFO_RESET_M (I2S_CAM_SYNC_FIFO_RESET_V << I2S_CAM_SYNC_FIFO_RESET_S) +#define I2S_CAM_SYNC_FIFO_RESET_V 0x00000001 +#define I2S_CAM_SYNC_FIFO_RESET_S 8 + +/* I2S_INTER_VALID_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable camera internal valid + */ + +#define I2S_INTER_VALID_EN (BIT(7)) +#define I2S_INTER_VALID_EN_M (I2S_INTER_VALID_EN_V << I2S_INTER_VALID_EN_S) +#define I2S_INTER_VALID_EN_V 0x00000001 +#define I2S_INTER_VALID_EN_S 7 + +/* I2S_EXT_ADC_START_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the function that ADC mode is triggered by + * external signal. + */ + +#define I2S_EXT_ADC_START_EN (BIT(6)) +#define I2S_EXT_ADC_START_EN_M (I2S_EXT_ADC_START_EN_V << I2S_EXT_ADC_START_EN_S) +#define I2S_EXT_ADC_START_EN_V 0x00000001 +#define I2S_EXT_ADC_START_EN_S 6 + +/* I2S_LCD_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable LCD mode + */ + +#define I2S_LCD_EN (BIT(5)) +#define I2S_LCD_EN_M (I2S_LCD_EN_V << I2S_LCD_EN_S) +#define I2S_LCD_EN_V 0x00000001 +#define I2S_LCD_EN_S 5 + +/* I2S_DATA_ENABLE : R/W; bitpos: [4]; default: 0; + * for debug camera mode enable + */ + +#define I2S_DATA_ENABLE (BIT(4)) +#define I2S_DATA_ENABLE_M (I2S_DATA_ENABLE_V << I2S_DATA_ENABLE_S) +#define I2S_DATA_ENABLE_V 0x00000001 +#define I2S_DATA_ENABLE_S 4 + +/* I2S_DATA_ENABLE_TEST_EN : R/W; bitpos: [3]; default: 0; + * for debug camera mode enable + */ + +#define I2S_DATA_ENABLE_TEST_EN (BIT(3)) +#define I2S_DATA_ENABLE_TEST_EN_M (I2S_DATA_ENABLE_TEST_EN_V << I2S_DATA_ENABLE_TEST_EN_S) +#define I2S_DATA_ENABLE_TEST_EN_V 0x00000001 +#define I2S_DATA_ENABLE_TEST_EN_S 3 + +/* I2S_LCD_TX_SDX2_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to duplicate data pairs (Frame Form 2) in LCD mode. + */ + +#define I2S_LCD_TX_SDX2_EN (BIT(2)) +#define I2S_LCD_TX_SDX2_EN_M (I2S_LCD_TX_SDX2_EN_V << I2S_LCD_TX_SDX2_EN_S) +#define I2S_LCD_TX_SDX2_EN_V 0x00000001 +#define I2S_LCD_TX_SDX2_EN_S 2 + +/* I2S_LCD_TX_WRX2_EN : R/W; bitpos: [1]; default: 0; + * LCD WR double for one datum. + */ + +#define I2S_LCD_TX_WRX2_EN (BIT(1)) +#define I2S_LCD_TX_WRX2_EN_M (I2S_LCD_TX_WRX2_EN_V << I2S_LCD_TX_WRX2_EN_S) +#define I2S_LCD_TX_WRX2_EN_V 0x00000001 +#define I2S_LCD_TX_WRX2_EN_S 1 + +/* I2S_CAMERA_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable camera mode + */ + +#define I2S_CAMERA_EN (BIT(0)) +#define I2S_CAMERA_EN_M (I2S_CAMERA_EN_V << I2S_CAMERA_EN_S) +#define I2S_CAMERA_EN_V 0x00000001 +#define I2S_CAMERA_EN_S 0 + +/* I2S_CLKM_CONF_REG register + * I2S module clock configure register + */ + +#define I2S_CLKM_CONF_REG (DR_REG_I2S_BASE + 0xac) + +/* I2S_CLK_SEL : R/W; bitpos: [22:21]; default: 0; + * Set this bit to select I2S module clock source. 0: No clock. 1: APLL_CLK. + * 2: PLL_160M_CLK. 3: No clock. + */ + +#define I2S_CLK_SEL 0x00000003 +#define I2S_CLK_SEL_M (I2S_CLK_SEL_V << I2S_CLK_SEL_S) +#define I2S_CLK_SEL_V 0x00000003 +#define I2S_CLK_SEL_S 21 + +/* I2S_CLK_EN : R/W; bitpos: [20]; default: 0; + * Set this bit to enable clk gate + */ + +#define I2S_CLK_EN (BIT(20)) +#define I2S_CLK_EN_M (I2S_CLK_EN_V << I2S_CLK_EN_S) +#define I2S_CLK_EN_V 0x00000001 +#define I2S_CLK_EN_S 20 + +/* I2S_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ + +#define I2S_CLKM_DIV_A 0x0000003F +#define I2S_CLKM_DIV_A_M (I2S_CLKM_DIV_A_V << I2S_CLKM_DIV_A_S) +#define I2S_CLKM_DIV_A_V 0x0000003F +#define I2S_CLKM_DIV_A_S 14 + +/* I2S_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ + +#define I2S_CLKM_DIV_B 0x0000003F +#define I2S_CLKM_DIV_B_M (I2S_CLKM_DIV_B_V << I2S_CLKM_DIV_B_S) +#define I2S_CLKM_DIV_B_V 0x0000003F +#define I2S_CLKM_DIV_B_S 8 + +/* I2S_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ + +#define I2S_CLKM_DIV_NUM 0x000000FF +#define I2S_CLKM_DIV_NUM_M (I2S_CLKM_DIV_NUM_V << I2S_CLKM_DIV_NUM_S) +#define I2S_CLKM_DIV_NUM_V 0x000000FF +#define I2S_CLKM_DIV_NUM_S 0 + +/* I2S_SAMPLE_RATE_CONF_REG register + * I2S sample rate register + */ + +#define I2S_SAMPLE_RATE_CONF_REG (DR_REG_I2S_BASE + 0xb0) + +/* I2S_RX_BITS_MOD : R/W; bitpos: [23:18]; default: 16; + * Set the bits to configure bit length of I2S receiver channel. + */ + +#define I2S_RX_BITS_MOD 0x0000003F +#define I2S_RX_BITS_MOD_M (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S) +#define I2S_RX_BITS_MOD_V 0x0000003F +#define I2S_RX_BITS_MOD_S 18 + +/* I2S_TX_BITS_MOD : R/W; bitpos: [17:12]; default: 16; + * Set the bits to configure bit length of I2S transmitter channel. + */ + +#define I2S_TX_BITS_MOD 0x0000003F +#define I2S_TX_BITS_MOD_M (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S) +#define I2S_TX_BITS_MOD_V 0x0000003F +#define I2S_TX_BITS_MOD_S 12 + +/* I2S_RX_BCK_DIV_NUM : R/W; bitpos: [11:6]; default: 6; + * Bit clock configuration bits in receiver mode. + */ + +#define I2S_RX_BCK_DIV_NUM 0x0000003F +#define I2S_RX_BCK_DIV_NUM_M (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S) +#define I2S_RX_BCK_DIV_NUM_V 0x0000003F +#define I2S_RX_BCK_DIV_NUM_S 6 + +/* I2S_TX_BCK_DIV_NUM : R/W; bitpos: [5:0]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ + +#define I2S_TX_BCK_DIV_NUM 0x0000003F +#define I2S_TX_BCK_DIV_NUM_M (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S) +#define I2S_TX_BCK_DIV_NUM_V 0x0000003F +#define I2S_TX_BCK_DIV_NUM_S 0 + +/* I2S_STATE_REG register + * I2S TX status register + */ + +#define I2S_STATE_REG (DR_REG_I2S_BASE + 0xbc) + +/* I2S_TX_IDLE : RO; bitpos: [0]; default: 1; + * 1: I2S TX is in idle state. 0: I2S TX is at work. + */ + +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (I2S_TX_IDLE_V << I2S_TX_IDLE_S) +#define I2S_TX_IDLE_V 0x00000001 +#define I2S_TX_IDLE_S 0 + +/* I2S_DATE_REG register + * Version control register + */ + +#define I2S_DATE_REG (DR_REG_I2S_BASE + 0xfc) + +/* I2S_DATE : R/W; bitpos: [31:0]; default: 419767552; + * Version control register + */ + +#define I2S_DATE 0xFFFFFFFF +#define I2S_DATE_M (I2S_DATE_V << I2S_DATE_S) +#define I2S_DATE_V 0xFFFFFFFF +#define I2S_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2S_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h new file mode 100644 index 00000000000..da3f1b2097d --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h @@ -0,0 +1,1647 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_INTERRUPT_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_INTERRUPT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* INTERRUPT_PRO_MAC_INTR_MAP_REG register + * MAC_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0) + +/* INTERRUPT_PRO_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map MAC_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_MAC_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_MAC_INTR_MAP_M (INTERRUPT_PRO_MAC_INTR_MAP_V << INTERRUPT_PRO_MAC_INTR_MAP_S) +#define INTERRUPT_PRO_MAC_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_MAC_INTR_MAP_S 0 + +/* INTERRUPT_PRO_MAC_NMI_MAP_REG register + * MAC_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4) + +/* INTERRUPT_PRO_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map MAC_NMI interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_MAC_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_MAC_NMI_MAP_M (INTERRUPT_PRO_MAC_NMI_MAP_V << INTERRUPT_PRO_MAC_NMI_MAP_S) +#define INTERRUPT_PRO_MAC_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_MAC_NMI_MAP_S 0 + +/* INTERRUPT_PRO_PWR_INTR_MAP_REG register + * PWR_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8) + +/* INTERRUPT_PRO_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWR_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWR_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWR_INTR_MAP_M (INTERRUPT_PRO_PWR_INTR_MAP_V << INTERRUPT_PRO_PWR_INTR_MAP_S) +#define INTERRUPT_PRO_PWR_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWR_INTR_MAP_S 0 + +/* INTERRUPT_PRO_BB_INT_MAP_REG register + * BB_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc) + +/* INTERRUPT_PRO_BB_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map BB_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_BB_INT_MAP 0x0000001F +#define INTERRUPT_PRO_BB_INT_MAP_M (INTERRUPT_PRO_BB_INT_MAP_V << INTERRUPT_PRO_BB_INT_MAP_S) +#define INTERRUPT_PRO_BB_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_BB_INT_MAP_S 0 + +/* INTERRUPT_PRO_BT_MAC_INT_MAP_REG register + * BT_MAC_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10) + +/* INTERRUPT_PRO_BT_MAC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map BT_MAC_INT interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_BT_MAC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_BT_MAC_INT_MAP_M (INTERRUPT_PRO_BT_MAC_INT_MAP_V << INTERRUPT_PRO_BT_MAC_INT_MAP_S) +#define INTERRUPT_PRO_BT_MAC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_BT_MAC_INT_MAP_S 0 + +/* INTERRUPT_PRO_BT_BB_INT_MAP_REG register + * BT_BB_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14) + +/* INTERRUPT_PRO_BT_BB_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map BT_BB_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_BT_BB_INT_MAP 0x0000001F +#define INTERRUPT_PRO_BT_BB_INT_MAP_M (INTERRUPT_PRO_BT_BB_INT_MAP_V << INTERRUPT_PRO_BT_BB_INT_MAP_S) +#define INTERRUPT_PRO_BT_BB_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_BT_BB_INT_MAP_S 0 + +/* INTERRUPT_PRO_BT_BB_NMI_MAP_REG register + * BT_BB_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x18) + +/* INTERRUPT_PRO_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map BT_BB_NMI interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_BT_BB_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_BT_BB_NMI_MAP_M (INTERRUPT_PRO_BT_BB_NMI_MAP_V << INTERRUPT_PRO_BT_BB_NMI_MAP_S) +#define INTERRUPT_PRO_BT_BB_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_BT_BB_NMI_MAP_S 0 + +/* INTERRUPT_PRO_RWBT_IRQ_MAP_REG register + * RWBT_IRQ interrupt configuration register + */ + +#define INTERRUPT_PRO_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x1c) + +/* INTERRUPT_PRO_RWBT_IRQ_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RWBT_IRQ interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RWBT_IRQ_MAP 0x0000001F +#define INTERRUPT_PRO_RWBT_IRQ_MAP_M (INTERRUPT_PRO_RWBT_IRQ_MAP_V << INTERRUPT_PRO_RWBT_IRQ_MAP_S) +#define INTERRUPT_PRO_RWBT_IRQ_MAP_V 0x0000001F +#define INTERRUPT_PRO_RWBT_IRQ_MAP_S 0 + +/* INTERRUPT_PRO_RWBLE_IRQ_MAP_REG register + * RWBLE_IRQ interrupt configuration register + */ + +#define INTERRUPT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x20) + +/* INTERRUPT_PRO_RWBLE_IRQ_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RWBLE_IRQ interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RWBLE_IRQ_MAP 0x0000001F +#define INTERRUPT_PRO_RWBLE_IRQ_MAP_M (INTERRUPT_PRO_RWBLE_IRQ_MAP_V << INTERRUPT_PRO_RWBLE_IRQ_MAP_S) +#define INTERRUPT_PRO_RWBLE_IRQ_MAP_V 0x0000001F +#define INTERRUPT_PRO_RWBLE_IRQ_MAP_S 0 + +/* INTERRUPT_PRO_RWBT_NMI_MAP_REG register + * RWBT_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x24) + +/* INTERRUPT_PRO_RWBT_NMI_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RWBT_NMI interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RWBT_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_RWBT_NMI_MAP_M (INTERRUPT_PRO_RWBT_NMI_MAP_V << INTERRUPT_PRO_RWBT_NMI_MAP_S) +#define INTERRUPT_PRO_RWBT_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_RWBT_NMI_MAP_S 0 + +/* INTERRUPT_PRO_RWBLE_NMI_MAP_REG register + * RWBLE_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x28) + +/* INTERRUPT_PRO_RWBLE_NMI_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RWBLE_NMI interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RWBLE_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_RWBLE_NMI_MAP_M (INTERRUPT_PRO_RWBLE_NMI_MAP_V << INTERRUPT_PRO_RWBLE_NMI_MAP_S) +#define INTERRUPT_PRO_RWBLE_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_RWBLE_NMI_MAP_S 0 + +/* INTERRUPT_PRO_SLC0_INTR_MAP_REG register + * SLC0_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x2c) + +/* INTERRUPT_PRO_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SLC0_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SLC0_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_SLC0_INTR_MAP_M (INTERRUPT_PRO_SLC0_INTR_MAP_V << INTERRUPT_PRO_SLC0_INTR_MAP_S) +#define INTERRUPT_PRO_SLC0_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_SLC0_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SLC1_INTR_MAP_REG register + * SLC1_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x30) + +/* INTERRUPT_PRO_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SLC1_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SLC1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_SLC1_INTR_MAP_M (INTERRUPT_PRO_SLC1_INTR_MAP_V << INTERRUPT_PRO_SLC1_INTR_MAP_S) +#define INTERRUPT_PRO_SLC1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_SLC1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_UHCI0_INTR_MAP_REG register + * UHCI0_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x34) + +/* INTERRUPT_PRO_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UHCI0_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_UHCI0_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UHCI0_INTR_MAP_M (INTERRUPT_PRO_UHCI0_INTR_MAP_V << INTERRUPT_PRO_UHCI0_INTR_MAP_S) +#define INTERRUPT_PRO_UHCI0_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UHCI0_INTR_MAP_S 0 + +/* INTERRUPT_PRO_UHCI1_INTR_MAP_REG register + * UHCI1_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x38) + +/* INTERRUPT_PRO_UHCI1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UHCI1_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_UHCI1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UHCI1_INTR_MAP_M (INTERRUPT_PRO_UHCI1_INTR_MAP_V << INTERRUPT_PRO_UHCI1_INTR_MAP_S) +#define INTERRUPT_PRO_UHCI1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UHCI1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_REG register + * TG_T0_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x3c) + +/* INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_T0_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_REG register + * TG_T1_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x40) + +/* INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_T1_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_REG register + * TG_WDT_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x44) + +/* INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_WDT_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_REG register + * TG_LACT_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x48) + +/* INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_LACT_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_REG register + * TG1_T0_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4c) + +/* INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_T0_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_REG register + * TG1_T1_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x50) + +/* INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_T1_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_REG register + * TG1_WDT_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x54) + +/* INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_WDT_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_REG register + * TG1_LACT_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x58) + +/* INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_LACT_LEVEL_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_REG register + * GPIO_INTERRUPT_PRO interrupt configuration register + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_BASE + 0x5c) + +/* INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map GPIO_INTERRUPT_PRO interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_S) +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 + +/* INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG register + * GPIO_INTERRUPT_PRO_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x60) + +/* INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map GPIO_INTERRUPT_PRO_NMI interrupt signal to + * one of the CPU interrupts. + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S) +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +/* INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_REG register + * GPIO_INTERRUPT_APP interrupt configuration register + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_BASE + 0x64) + +/* INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map GPIO_INTERRUPT_APP interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_M (INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_V << INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_S) +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_V 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_S 0 + +/* INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_REG register + * GPIO_INTERRUPT_APP_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x68) + +/* INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map GPIO_INTERRUPT_APP_NMI interrupt signal to + * one of the CPU interrupts. + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_M (INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_V << INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_S) +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_S 0 + +/* INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG register + * DEDICATED_GPIO_IN_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x6c) + +/* INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map DEDICATED_GPIO_IN_INTR interrupt signal to + * one of the CPU interrupts. + */ + +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_M (INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V << INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S) +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S 0 + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG register + * CPU_INTR_FROM_CPU_0 interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_BASE + 0x70) + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_INTR_FROM_CPU_0 interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG register + * CPU_INTR_FROM_CPU_1 interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x74) + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_INTR_FROM_CPU_1 interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG register + * CPU_INTR_FROM_CPU_2 interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x78) + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_INTR_FROM_CPU_2 interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG register + * CPU_INTR_FROM_CPU_3 interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x7c) + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_INTR_FROM_CPU_3 interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 + +/* INTERRUPT_PRO_SPI_INTR_1_MAP_REG register + * SPI_INTR_1 interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x80) + +/* INTERRUPT_PRO_SPI_INTR_1_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_INTR_1 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_INTR_1_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_1_MAP_M (INTERRUPT_PRO_SPI_INTR_1_MAP_V << INTERRUPT_PRO_SPI_INTR_1_MAP_S) +#define INTERRUPT_PRO_SPI_INTR_1_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_1_MAP_S 0 + +/* INTERRUPT_PRO_SPI_INTR_2_MAP_REG register + * SPI_INTR_2 interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x84) + +/* INTERRUPT_PRO_SPI_INTR_2_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_INTR_2 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_INTR_2_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_2_MAP_M (INTERRUPT_PRO_SPI_INTR_2_MAP_V << INTERRUPT_PRO_SPI_INTR_2_MAP_S) +#define INTERRUPT_PRO_SPI_INTR_2_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_2_MAP_S 0 + +/* INTERRUPT_PRO_SPI_INTR_3_MAP_REG register + * SPI_INTR_3 interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x88) + +/* INTERRUPT_PRO_SPI_INTR_3_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_INTR_3 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_INTR_3_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_3_MAP_M (INTERRUPT_PRO_SPI_INTR_3_MAP_V << INTERRUPT_PRO_SPI_INTR_3_MAP_S) +#define INTERRUPT_PRO_SPI_INTR_3_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_3_MAP_S 0 + +/* INTERRUPT_PRO_I2S0_INT_MAP_REG register + * I2S0_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8c) + +/* INTERRUPT_PRO_I2S0_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map I2S0_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_I2S0_INT_MAP 0x0000001F +#define INTERRUPT_PRO_I2S0_INT_MAP_M (INTERRUPT_PRO_I2S0_INT_MAP_V << INTERRUPT_PRO_I2S0_INT_MAP_S) +#define INTERRUPT_PRO_I2S0_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_I2S0_INT_MAP_S 0 + +/* INTERRUPT_PRO_I2S1_INT_MAP_REG register + * I2S1_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x90) + +/* INTERRUPT_PRO_I2S1_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map I2S1_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_I2S1_INT_MAP 0x0000001F +#define INTERRUPT_PRO_I2S1_INT_MAP_M (INTERRUPT_PRO_I2S1_INT_MAP_V << INTERRUPT_PRO_I2S1_INT_MAP_S) +#define INTERRUPT_PRO_I2S1_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_I2S1_INT_MAP_S 0 + +/* INTERRUPT_PRO_UART_INTR_MAP_REG register + * UART_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x94) + +/* INTERRUPT_PRO_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UART_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_UART_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UART_INTR_MAP_M (INTERRUPT_PRO_UART_INTR_MAP_V << INTERRUPT_PRO_UART_INTR_MAP_S) +#define INTERRUPT_PRO_UART_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UART_INTR_MAP_S 0 + +/* INTERRUPT_PRO_UART1_INTR_MAP_REG register + * UART1_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x98) + +/* INTERRUPT_PRO_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UART1_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_UART1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UART1_INTR_MAP_M (INTERRUPT_PRO_UART1_INTR_MAP_V << INTERRUPT_PRO_UART1_INTR_MAP_S) +#define INTERRUPT_PRO_UART1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UART1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_UART2_INTR_MAP_REG register + * UART2_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x9c) + +/* INTERRUPT_PRO_UART2_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UART2_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_UART2_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UART2_INTR_MAP_M (INTERRUPT_PRO_UART2_INTR_MAP_V << INTERRUPT_PRO_UART2_INTR_MAP_S) +#define INTERRUPT_PRO_UART2_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UART2_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_REG register + * SDIO_HOST_INTERRUPT configuration register + */ + +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa0) + +/* INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SDIO_HOST_INTERRUPT signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_M (INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_V << INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_S) +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 + +/* INTERRUPT_PRO_PWM0_INTR_MAP_REG register + * PWM0_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa4) + +/* INTERRUPT_PRO_PWM0_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWM0_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWM0_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWM0_INTR_MAP_M (INTERRUPT_PRO_PWM0_INTR_MAP_V << INTERRUPT_PRO_PWM0_INTR_MAP_S) +#define INTERRUPT_PRO_PWM0_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWM0_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PWM1_INTR_MAP_REG register + * PWM1_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa8) + +/* INTERRUPT_PRO_PWM1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWM1_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWM1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWM1_INTR_MAP_M (INTERRUPT_PRO_PWM1_INTR_MAP_V << INTERRUPT_PRO_PWM1_INTR_MAP_S) +#define INTERRUPT_PRO_PWM1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWM1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PWM2_INTR_MAP_REG register + * PWM2_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xac) + +/* INTERRUPT_PRO_PWM2_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWM2_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWM2_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWM2_INTR_MAP_M (INTERRUPT_PRO_PWM2_INTR_MAP_V << INTERRUPT_PRO_PWM2_INTR_MAP_S) +#define INTERRUPT_PRO_PWM2_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWM2_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PWM3_INTR_MAP_REG register + * PWM3_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb0) + +/* INTERRUPT_PRO_PWM3_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWM3_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWM3_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWM3_INTR_MAP_M (INTERRUPT_PRO_PWM3_INTR_MAP_V << INTERRUPT_PRO_PWM3_INTR_MAP_S) +#define INTERRUPT_PRO_PWM3_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWM3_INTR_MAP_S 0 + +/* INTERRUPT_PRO_LEDC_INT_MAP_REG register + * LEDC_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb4) + +/* INTERRUPT_PRO_LEDC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map LEDC_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_LEDC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_LEDC_INT_MAP_M (INTERRUPT_PRO_LEDC_INT_MAP_V << INTERRUPT_PRO_LEDC_INT_MAP_S) +#define INTERRUPT_PRO_LEDC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_LEDC_INT_MAP_S 0 + +/* INTERRUPT_PRO_EFUSE_INT_MAP_REG register + * EFUSE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb8) + +/* INTERRUPT_PRO_EFUSE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map EFUSE_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_EFUSE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_EFUSE_INT_MAP_M (INTERRUPT_PRO_EFUSE_INT_MAP_V << INTERRUPT_PRO_EFUSE_INT_MAP_S) +#define INTERRUPT_PRO_EFUSE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_EFUSE_INT_MAP_S 0 + +/* INTERRUPT_PRO_CAN_INT_MAP_REG register + * CAN_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_CAN_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xbc) + +/* INTERRUPT_PRO_CAN_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CAN_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_CAN_INT_MAP 0x0000001F +#define INTERRUPT_PRO_CAN_INT_MAP_M (INTERRUPT_PRO_CAN_INT_MAP_V << INTERRUPT_PRO_CAN_INT_MAP_S) +#define INTERRUPT_PRO_CAN_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_CAN_INT_MAP_S 0 + +/* INTERRUPT_PRO_USB_INTR_MAP_REG register + * USB_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_USB_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc0) + +/* INTERRUPT_PRO_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map USB_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_USB_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_USB_INTR_MAP_M (INTERRUPT_PRO_USB_INTR_MAP_V << INTERRUPT_PRO_USB_INTR_MAP_S) +#define INTERRUPT_PRO_USB_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_USB_INTR_MAP_S 0 + +/* INTERRUPT_PRO_RTC_CORE_INTR_MAP_REG register + * RTC_CORE_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc4) + +/* INTERRUPT_PRO_RTC_CORE_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RTC_CORE_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP_M (INTERRUPT_PRO_RTC_CORE_INTR_MAP_V << INTERRUPT_PRO_RTC_CORE_INTR_MAP_S) +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP_S 0 + +/* INTERRUPT_PRO_RMT_INTR_MAP_REG register + * RMT_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc8) + +/* INTERRUPT_PRO_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RMT_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RMT_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_RMT_INTR_MAP_M (INTERRUPT_PRO_RMT_INTR_MAP_V << INTERRUPT_PRO_RMT_INTR_MAP_S) +#define INTERRUPT_PRO_RMT_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_RMT_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PCNT_INTR_MAP_REG register + * PCNT_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xcc) + +/* INTERRUPT_PRO_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PCNT_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PCNT_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PCNT_INTR_MAP_M (INTERRUPT_PRO_PCNT_INTR_MAP_V << INTERRUPT_PRO_PCNT_INTR_MAP_S) +#define INTERRUPT_PRO_PCNT_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PCNT_INTR_MAP_S 0 + +/* INTERRUPT_PRO_I2C_EXT0_INTR_MAP_REG register + * I2C_EXT0_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd0) + +/* INTERRUPT_PRO_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map I2C_EXT0_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP_M (INTERRUPT_PRO_I2C_EXT0_INTR_MAP_V << INTERRUPT_PRO_I2C_EXT0_INTR_MAP_S) +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP_S 0 + +/* INTERRUPT_PRO_I2C_EXT1_INTR_MAP_REG register + * I2C_EXT1_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd4) + +/* INTERRUPT_PRO_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map I2C_EXT1_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP_M (INTERRUPT_PRO_I2C_EXT1_INTR_MAP_V << INTERRUPT_PRO_I2C_EXT1_INTR_MAP_S) +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_RSA_INTR_MAP_REG register + * RSA_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd8) + +/* INTERRUPT_PRO_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RSA_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RSA_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_RSA_INTR_MAP_M (INTERRUPT_PRO_RSA_INTR_MAP_V << INTERRUPT_PRO_RSA_INTR_MAP_S) +#define INTERRUPT_PRO_RSA_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_RSA_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SHA_INTR_MAP_REG register + * SHA_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xdc) + +/* INTERRUPT_PRO_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SHA_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SHA_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_SHA_INTR_MAP_M (INTERRUPT_PRO_SHA_INTR_MAP_V << INTERRUPT_PRO_SHA_INTR_MAP_S) +#define INTERRUPT_PRO_SHA_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_SHA_INTR_MAP_S 0 + +/* INTERRUPT_PRO_AES_INTR_MAP_REG register + * AES_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_AES_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe0) + +/* INTERRUPT_PRO_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map AES_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_AES_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_AES_INTR_MAP_M (INTERRUPT_PRO_AES_INTR_MAP_V << INTERRUPT_PRO_AES_INTR_MAP_S) +#define INTERRUPT_PRO_AES_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_AES_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SPI2_DMA_INT_MAP_REG register + * SPI2_DMA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe4) + +/* INTERRUPT_PRO_SPI2_DMA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map AES_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP_M (INTERRUPT_PRO_SPI2_DMA_INT_MAP_V << INTERRUPT_PRO_SPI2_DMA_INT_MAP_S) +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP_S 0 + +/* INTERRUPT_PRO_SPI3_DMA_INT_MAP_REG register + * SPI3_DMA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe8) + +/* INTERRUPT_PRO_SPI3_DMA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI3_DMA_INT dma interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP_M (INTERRUPT_PRO_SPI3_DMA_INT_MAP_V << INTERRUPT_PRO_SPI3_DMA_INT_MAP_S) +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP_S 0 + +/* INTERRUPT_PRO_WDG_INT_MAP_REG register + * WDG_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_WDG_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xec) + +/* INTERRUPT_PRO_WDG_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map WDG_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_WDG_INT_MAP 0x0000001F +#define INTERRUPT_PRO_WDG_INT_MAP_M (INTERRUPT_PRO_WDG_INT_MAP_V << INTERRUPT_PRO_WDG_INT_MAP_S) +#define INTERRUPT_PRO_WDG_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_WDG_INT_MAP_S 0 + +/* INTERRUPT_PRO_TIMER_INT1_MAP_REG register + * TIMER_INT1 interrupt configuration register + */ + +#define INTERRUPT_PRO_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf0) + +/* INTERRUPT_PRO_TIMER_INT1_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TIMER_INT1 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_TIMER_INT1_MAP 0x0000001F +#define INTERRUPT_PRO_TIMER_INT1_MAP_M (INTERRUPT_PRO_TIMER_INT1_MAP_V << INTERRUPT_PRO_TIMER_INT1_MAP_S) +#define INTERRUPT_PRO_TIMER_INT1_MAP_V 0x0000001F +#define INTERRUPT_PRO_TIMER_INT1_MAP_S 0 + +/* INTERRUPT_PRO_TIMER_INT2_MAP_REG register + * TIMER_INT2 interrupt configuration register + */ + +#define INTERRUPT_PRO_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf4) + +/* INTERRUPT_PRO_TIMER_INT2_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TIMER_INT2 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_TIMER_INT2_MAP 0x0000001F +#define INTERRUPT_PRO_TIMER_INT2_MAP_M (INTERRUPT_PRO_TIMER_INT2_MAP_V << INTERRUPT_PRO_TIMER_INT2_MAP_S) +#define INTERRUPT_PRO_TIMER_INT2_MAP_V 0x0000001F +#define INTERRUPT_PRO_TIMER_INT2_MAP_S 0 + +/* INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_REG register + * TG_T0_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf8) + +/* INTERRUPT_PRO_TG_T0_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_T0_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_M (INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_V << INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_REG register + * TG_T1_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xfc) + +/* INTERRUPT_PRO_TG_T1_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_T1_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_M (INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_V << INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_REG register + * TG_WDT_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100) + +/* INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_WDT_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_M (INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_V << INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_REG register + * TG_LACT_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104) + +/* INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_LACT_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_M (INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_V << INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_REG register + * TG1_T0_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108) + +/* INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_T0_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_M (INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_V << INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_REG register + * TG1_T1_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10c) + +/* INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_T1_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_M (INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_V << INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_REG register + * TG1_WDT_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110) + +/* INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_WDT_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_M (INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_V << INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_REG register + * TG1_LACT_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114) + +/* INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_LACT_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_M (INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_V << INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_CACHE_IA_INT_MAP_REG register + * CACHE_IA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x118) + +/* INTERRUPT_PRO_CACHE_IA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CACHE_IA_INT interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_CACHE_IA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_CACHE_IA_INT_MAP_M (INTERRUPT_PRO_CACHE_IA_INT_MAP_V << INTERRUPT_PRO_CACHE_IA_INT_MAP_S) +#define INTERRUPT_PRO_CACHE_IA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_CACHE_IA_INT_MAP_S 0 + +/* INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_REG register + * SYSTIMER_TARGET0_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x11c) + +/* INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SYSTIMER_TARGET0_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_M (INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_V << INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_S) +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_S 0 + +/* INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_REG register + * SYSTIMER_TARGET1_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x120) + +/* INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SYSTIMER_TARGET1_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_M (INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_V << INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_S) +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_S 0 + +/* INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_REG register + * SYSTIMER_TARGET2_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x124) + +/* INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SYSTIMER_TARGET2_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_M (INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_V << INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_S) +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_S 0 + +/* INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_REG register + * ASSIST_DEBUG_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x128) + +/* INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map ASSIST_DEBUG_INTR interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_S) +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG register + * PMS_PRO_IRAM0_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x12c) + +/* INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_PRO_IRAM0_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG register + * PMS_PRO_DRAM0_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x130) + +/* INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_PRO_DRAM0_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG register + * PMS_PRO_DPORT_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x134) + +/* INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_PRO_DPORT_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG register + * PMS_PRO_AHB_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x138) + +/* INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PMS_PRO_AHB_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG register + * PMS_PRO_CACHE_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x13c) + +/* INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_PRO_CACHE_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG register + * PMS_DMA_APB_I_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x140) + +/* INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_DMA_APB_I_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG register + * PMS_DMA_RX_I_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x144) + +/* INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PMS_DMA_RX_I_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG register + * PMS_DMA_TX_I_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x148) + +/* INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PMS_DMA_TX_I_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_REG register + * SPI_MEM_REJECT_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14c) + +/* INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_MEM_REJECT_INTR interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_M (INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_V << INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_S) +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_S 0 + +/* INTERRUPT_PRO_DMA_COPY_INTR_MAP_REG register + * DMA_COPY_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x150) + +/* INTERRUPT_PRO_DMA_COPY_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map DMA_COPY_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP_M (INTERRUPT_PRO_DMA_COPY_INTR_MAP_V << INTERRUPT_PRO_DMA_COPY_INTR_MAP_S) +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SPI4_DMA_INT_MAP_REG register + * SPI4_DMA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x154) + +/* INTERRUPT_PRO_SPI4_DMA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI4_DMA_INT interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP_M (INTERRUPT_PRO_SPI4_DMA_INT_MAP_V << INTERRUPT_PRO_SPI4_DMA_INT_MAP_S) +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP_S 0 + +/* INTERRUPT_PRO_SPI_INTR_4_MAP_REG register + * SPI_INTR_4 interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_BASE + 0x158) + +/* INTERRUPT_PRO_SPI_INTR_4_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_INTR_4 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_INTR_4_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_4_MAP_M (INTERRUPT_PRO_SPI_INTR_4_MAP_V << INTERRUPT_PRO_SPI_INTR_4_MAP_S) +#define INTERRUPT_PRO_SPI_INTR_4_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_4_MAP_S 0 + +/* INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_REG register + * DCACHE_PRELOAD_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x15c) + +/* INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map DCACHE_PRELOAD_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_M (INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_V << INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_S) +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_S 0 + +/* INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_REG register + * ICACHE_PRELOAD_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x160) + +/* INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map ICACHE_PRELOAD_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_M (INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_V << INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_S) +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_S 0 + +/* INTERRUPT_PRO_APB_ADC_INT_MAP_REG register + * APB_ADC_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x164) + +/* INTERRUPT_PRO_APB_ADC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map APB_ADC_INT interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_APB_ADC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_APB_ADC_INT_MAP_M (INTERRUPT_PRO_APB_ADC_INT_MAP_V << INTERRUPT_PRO_APB_ADC_INT_MAP_S) +#define INTERRUPT_PRO_APB_ADC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_APB_ADC_INT_MAP_S 0 + +/* INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_REG register + * CRYPTO_DMA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x168) + +/* INTERRUPT_PRO_CRYPTO_DMA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CRYPTO_DMA_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_M (INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_V << INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_S) +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_S 0 + +/* INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_REG register + * CPU_PERI_ERROR_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x16c) + +/* INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_PERI_ERROR_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_M (INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_V << INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_S) +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_S 0 + +/* INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_REG register + * APB_PERI_ERROR_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x170) + +/* INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map APB_PERI_ERROR_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP 0x0000001F +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_M (INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_V << INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_S) +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_S 0 + +/* INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_REG register + * DCACHE_SYNC_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x174) + +/* INTERRUPT_PRO_DCACHE_SYNC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map DCACHE_SYNC_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_M (INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_V << INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_S) +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_S 0 + +/* INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_REG register + * ICACHE_SYNC_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x178) + +/* INTERRUPT_PRO_ICACHE_SYNC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map ICACHE_SYNC_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_M (INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_V << INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_S) +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_S 0 + +/* INTERRUPT_PRO_INTR_STATUS_REG_0_REG register + * Interrupt status register 0 + */ + +#define INTERRUPT_PRO_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_BASE + 0x17c) + +/* INTERRUPT_PRO_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * This register stores the status of the first 32 input interrupt sources. + */ + +#define INTERRUPT_PRO_INTR_STATUS_0 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_0_M (INTERRUPT_PRO_INTR_STATUS_0_V << INTERRUPT_PRO_INTR_STATUS_0_S) +#define INTERRUPT_PRO_INTR_STATUS_0_V 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_0_S 0 + +/* INTERRUPT_PRO_INTR_STATUS_REG_1_REG register + * Interrupt status register 1 + */ + +#define INTERRUPT_PRO_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_BASE + 0x180) + +/* INTERRUPT_PRO_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * This register stores the status of the second 32 input interrupt sources. + */ + +#define INTERRUPT_PRO_INTR_STATUS_1 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_1_M (INTERRUPT_PRO_INTR_STATUS_1_V << INTERRUPT_PRO_INTR_STATUS_1_S) +#define INTERRUPT_PRO_INTR_STATUS_1_V 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_1_S 0 + +/* INTERRUPT_PRO_INTR_STATUS_REG_2_REG register + * Interrupt status register 2 + */ + +#define INTERRUPT_PRO_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_BASE + 0x184) + +/* INTERRUPT_PRO_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * This register stores the status of the last 31 input interrupt sources. + */ + +#define INTERRUPT_PRO_INTR_STATUS_2 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_2_M (INTERRUPT_PRO_INTR_STATUS_2_V << INTERRUPT_PRO_INTR_STATUS_2_S) +#define INTERRUPT_PRO_INTR_STATUS_2_V 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_2_S 0 + +/* INTERRUPT_CLOCK_GATE_REG register + * NMI interrupt signals mask register + */ + +#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x188) + +/* INTERRUPT_PRO_NMI_MASK_HW : R/W; bitpos: [1]; default: 0; + * This bit is used to disable all NMI interrupt signals to CPU. + */ + +#define INTERRUPT_PRO_NMI_MASK_HW (BIT(1)) +#define INTERRUPT_PRO_NMI_MASK_HW_M (INTERRUPT_PRO_NMI_MASK_HW_V << INTERRUPT_PRO_NMI_MASK_HW_S) +#define INTERRUPT_PRO_NMI_MASK_HW_V 0x00000001 +#define INTERRUPT_PRO_NMI_MASK_HW_S 1 + +/* INTERRUPT_CLK_EN : R/W; bitpos: [0]; default: 1; + * This bit is used to enable or disable the clock of interrupt matrix. 1: + * enable the clock. 0: disable the clock. + */ + +#define INTERRUPT_CLK_EN (BIT(0)) +#define INTERRUPT_CLK_EN_M (INTERRUPT_CLK_EN_V << INTERRUPT_CLK_EN_S) +#define INTERRUPT_CLK_EN_V 0x00000001 +#define INTERRUPT_CLK_EN_S 0 + +/* INTERRUPT_REG_DATE_REG register + * Version control register + */ + +#define INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_BASE + 0xffc) + +/* INTERRUPT_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 26231168; + * This is the version register. + */ + +#define INTERRUPT_INTERRUPT_REG_DATE 0x0FFFFFFF +#define INTERRUPT_INTERRUPT_REG_DATE_M (INTERRUPT_INTERRUPT_REG_DATE_V << INTERRUPT_INTERRUPT_REG_DATE_S) +#define INTERRUPT_INTERRUPT_REG_DATE_V 0x0FFFFFFF +#define INTERRUPT_INTERRUPT_REG_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_INTERRUPT_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h new file mode 100644 index 00000000000..818c987236c --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h @@ -0,0 +1,460 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_IOMUM_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_IOMUM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers + * Output enable in sleep mode + */ + +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 + +/* Pin used for wakeup from sleep */ + +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 + +/* Pulldown enable in sleep mode */ + +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 + +/* Pullup enable in sleep mode */ + +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 + +/* Input enable in sleep mode */ + +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 + +/* Drive strength in sleep mode */ + +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 + +/* Pulldown enable */ + +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 + +/* Pullup enable */ + +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 + +/* Input enable */ + +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 + +/* Drive strength */ + +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 + +/* Function select (possible values are defined for each pin as + * FUNC_pinname_function below) + */ + +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U +#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U +#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U +#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U +#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U +#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U +#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U +#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U + +#define FUNC_GPIO_GPIO 1 +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define U1RXD_GPIO_NUM 18 +#define U1TXD_GPIO_NUM 17 +#define U0RXD_GPIO_NUM 44 +#define U0TXD_GPIO_NUM 43 + +#define SPI_CS1_GPIO_NUM 26 +#define SPI_HD_GPIO_NUM 27 +#define SPI_WP_GPIO_NUM 28 +#define SPI_CS0_GPIO_NUM 29 +#define SPI_CLK_GPIO_NUM 30 +#define SPI_Q_GPIO_NUM 31 +#define SPI_D_GPIO_NUM 32 +#define SPI_D4_GPIO_NUM 33 +#define SPI_D5_GPIO_NUM 34 +#define SPI_D6_GPIO_NUM 35 +#define SPI_D7_GPIO_NUM 36 +#define SPI_DQS_GPIO_NUM 37 + +#define MAX_RTC_GPIO_NUM 21 +#define MAX_PAD_GPIO_NUM 46 +#define MAX_GPIO_NUM 53 + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 0xf +#define CLK_OUT3_V CLK_OUT3 +#define CLK_OUT3_S 8 +#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) +#define CLK_OUT2 0xf +#define CLK_OUT2_V CLK_OUT2 +#define CLK_OUT2_S 4 +#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) +#define CLK_OUT1 0xf +#define CLK_OUT1_V CLK_OUT1 +#define CLK_OUT1_S 0 +#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) + +#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04) +#define FUNC_GPIO0_GPIO0 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08) +#define FUNC_GPIO1_GPIO1 1 +#define FUNC_GPIO1_GPIO1_0 0 + +#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c) +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10) +#define FUNC_GPIO3_GPIO3 1 +#define FUNC_GPIO3_GPIO3_0 0 + +#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14) +#define FUNC_GPIO4_GPIO4 1 +#define FUNC_GPIO4_GPIO4_0 0 + +#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18) +#define FUNC_GPIO5_GPIO5 1 +#define FUNC_GPIO5_GPIO5_0 0 + +#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c) +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_GPIO6_0 0 + +#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20) +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO8_SUBSPICS1 3 +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO9_FSPIHD 4 +#define FUNC_GPIO9_SUBSPIHD 3 +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO10_FSPICS0 4 +#define FUNC_GPIO10_SUBSPICS0 3 +#define FUNC_GPIO10_FSPIIO4 2 +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_GPIO10_0 0 + +#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30) +#define FUNC_GPIO11_FSPID 4 +#define FUNC_GPIO11_SUBSPID 3 +#define FUNC_GPIO11_FSPIIO5 2 +#define FUNC_GPIO11_GPIO11 1 +#define FUNC_GPIO11_GPIO11_0 0 + +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34) +#define FUNC_GPIO12_FSPICLK 4 +#define FUNC_GPIO12_SUBSPICLK 3 +#define FUNC_GPIO12_FSPIIO6 2 +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38) +#define FUNC_GPIO13_FSPIQ 4 +#define FUNC_GPIO13_SUBSPIQ 3 +#define FUNC_GPIO13_FSPIIO7 2 +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c) +#define FUNC_GPIO14_FSPIWP 4 +#define FUNC_GPIO14_SUBSPIWP 3 +#define FUNC_GPIO14_FSPIDQS 2 +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40) +#define FUNC_XTAL_32K_P_U0RTS 2 +#define FUNC_XTAL_32K_P_GPIO15 1 +#define FUNC_XTAL_32K_P_GPIO15_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44) +#define FUNC_XTAL_32K_N_U0CTS 2 +#define FUNC_XTAL_32K_N_GPIO16 1 +#define FUNC_XTAL_32K_N_GPIO16_0 0 + +#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48) +#define FUNC_DAC_1_U1TXD 2 +#define FUNC_DAC_1_GPIO17 1 +#define FUNC_DAC_1_GPIO17_0 0 + +#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c) +#define FUNC_DAC_2_CLK_OUT3 3 +#define FUNC_DAC_2_U1RXD 2 +#define FUNC_DAC_2_GPIO18 1 +#define FUNC_DAC_2_GPIO18_0 0 + +#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50) +#define FUNC_GPIO19_CLK_OUT2 3 +#define FUNC_GPIO19_U1RTS 2 +#define FUNC_GPIO19_GPIO19 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54) +#define FUNC_GPIO20_CLK_OUT1 3 +#define FUNC_GPIO20_U1CTS 2 +#define FUNC_GPIO20_GPIO20 1 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58) +#define FUNC_GPIO21_GPIO21 1 +#define FUNC_GPIO21_GPIO21_0 0 + +#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c) +#define FUNC_SPICS1_GPIO26 1 +#define FUNC_SPICS1_SPICS1 0 + +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70) +#define FUNC_SPIHD_GPIO27 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74) +#define FUNC_SPIWP_GPIO28 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78) +#define FUNC_SPICS0_GPIO29 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c) +#define FUNC_SPICLK_GPIO30 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80) +#define FUNC_SPIQ_GPIO31 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84) +#define FUNC_SPID_GPIO32 1 +#define FUNC_SPID_SPID 0 + +#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88) +#define FUNC_GPIO33_SPIIO4 4 +#define FUNC_GPIO33_SUBSPIHD 3 +#define FUNC_GPIO33_FSPIHD 2 +#define FUNC_GPIO33_GPIO33 1 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c) +#define FUNC_GPIO34_SPIIO5 4 +#define FUNC_GPIO34_SUBSPICS0 3 +#define FUNC_GPIO34_FSPICS0 2 +#define FUNC_GPIO34_GPIO34 1 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90) +#define FUNC_GPIO35_SPIIO6 4 +#define FUNC_GPIO35_SUBSPID 3 +#define FUNC_GPIO35_FSPID 2 +#define FUNC_GPIO35_GPIO35 1 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94) +#define FUNC_GPIO36_SPIIO7 4 +#define FUNC_GPIO36_SUBSPICLK 3 +#define FUNC_GPIO36_FSPICLK 2 +#define FUNC_GPIO36_GPIO36 1 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98) +#define FUNC_GPIO37_SPIDQS 4 +#define FUNC_GPIO37_SUBSPIQ 3 +#define FUNC_GPIO37_FSPIQ 2 +#define FUNC_GPIO37_GPIO37 1 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c) +#define FUNC_GPIO38_SUBSPIWP 3 +#define FUNC_GPIO38_FSPIWP 2 +#define FUNC_GPIO38_GPIO38 1 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0) +#define FUNC_MTCK_SUBSPICS1 3 +#define FUNC_MTCK_CLK_OUT3 2 +#define FUNC_MTCK_GPIO39 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4) +#define FUNC_MTDO_CLK_OUT2 2 +#define FUNC_MTDO_GPIO40 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8) +#define FUNC_MTDI_CLK_OUT1 2 +#define FUNC_MTDI_GPIO41 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac) +#define FUNC_MTMS_GPIO42 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0) +#define FUNC_U0TXD_CLK_OUT1 2 +#define FUNC_U0TXD_GPIO43 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4) +#define FUNC_U0RXD_CLK_OUT2 2 +#define FUNC_U0RXD_GPIO44 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8) +#define FUNC_GPIO45_GPIO45 1 +#define FUNC_GPIO45_GPIO45_0 0 + +#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc) +#define FUNC_GPIO46_GPIO46 1 +#define FUNC_GPIO46_GPIO46_0 0 + +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) +#define IO_MUX_DATE 0xFFFFFFFF +#define IO_MUX_DATE_S 0 +#define IO_MUX_DATE_VERSION 0x1907160 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h new file mode 100644 index 00000000000..8d2b5d28836 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h @@ -0,0 +1,233 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RSA_M_PRIME_REG register + * Register to store M' + */ + +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) + +/* RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Stores M' + */ + +#define RSA_M_PRIME 0xFFFFFFFF +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFF +#define RSA_M_PRIME_S 0 + +/* RSA_MODE_REG register + * RSA length mode + */ + +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) + +/* RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Stores the mode of modular exponentiation. + */ + +#define RSA_MODE 0x0000007F +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007F +#define RSA_MODE_S 0 + +/* RSA_CLEAN_REG register + * RSA clean register + */ + +#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x808) + +/* RSA_CLEAN : RO; bitpos: [0]; default: 0; + * The content of this bit is 1 when memories complete initialization. + */ + +#define RSA_CLEAN (BIT(0)) +#define RSA_CLEAN_M (RSA_CLEAN_V << RSA_CLEAN_S) +#define RSA_CLEAN_V 0x00000001 +#define RSA_CLEAN_S 0 + +/* RSA_MODEXP_START_REG register + * Modular exponentiation starting bit + */ + +#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) + +/* RSA_MODEXP_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the modular exponentiation. + */ + +#define RSA_MODEXP_START (BIT(0)) +#define RSA_MODEXP_START_M (RSA_MODEXP_START_V << RSA_MODEXP_START_S) +#define RSA_MODEXP_START_V 0x00000001 +#define RSA_MODEXP_START_S 0 + +/* RSA_MODMULT_START_REG register + * Modular multiplication starting bit + */ + +#define RSA_MODMULT_START_REG (DR_REG_RSA_BASE + 0x810) + +/* RSA_MODMULT_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the modular multiplication. + */ + +#define RSA_MODMULT_START (BIT(0)) +#define RSA_MODMULT_START_M (RSA_MODMULT_START_V << RSA_MODMULT_START_S) +#define RSA_MODMULT_START_V 0x00000001 +#define RSA_MODMULT_START_S 0 + +/* RSA_MULT_START_REG register + * Normal multiplicaiton starting bit + */ + +#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) + +/* RSA_MULT_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the multiplication. + */ + +#define RSA_MULT_START (BIT(0)) +#define RSA_MULT_START_M (RSA_MULT_START_V << RSA_MULT_START_S) +#define RSA_MULT_START_V 0x00000001 +#define RSA_MULT_START_S 0 + +/* RSA_IDLE_REG register + * RSA idle register + */ + +#define RSA_IDLE_REG (DR_REG_RSA_BASE + 0x818) + +/* RSA_IDLE : RO; bitpos: [0]; default: 0; + * The content of this bit is 1 when the RSA accelerator is idle. + */ + +#define RSA_IDLE (BIT(0)) +#define RSA_IDLE_M (RSA_IDLE_V << RSA_IDLE_S) +#define RSA_IDLE_V 0x00000001 +#define RSA_IDLE_S 0 + +/* RSA_CLEAR_INTERRUPT_REG register + * RSA clear interrupt register + */ + +#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81c) + +/* RSA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear the RSA interrupts. + */ + +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001 +#define RSA_CLEAR_INTERRUPT_S 0 + +/* RSA_CONSTANT_TIME_REG register + * The constant_time option + */ + +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) + +/* RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Set this bit to 0 to enable the acceleration option of constant_time for + * modular exponentiation. Set to 1 to disable the acceleration (by default). + */ + +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001 +#define RSA_CONSTANT_TIME_S 0 + +/* RSA_SEARCH_ENABLE_REG register + * The search option + */ + +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) + +/* RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable the acceleration option of search for modular + * exponentiation. Set to 0 to disable the acceleration (by default). + */ + +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001 +#define RSA_SEARCH_ENABLE_S 0 + +/* RSA_SEARCH_POS_REG register + * The search position + */ + +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) + +/* RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Is used to configure the starting address when the acceleration option of + * search is used. + */ + +#define RSA_SEARCH_POS 0x00000FFF +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFF +#define RSA_SEARCH_POS_S 0 + +/* RSA_INTERRUPT_ENA_REG register + * RSA interrupt enable register + */ + +#define RSA_INTERRUPT_ENA_REG (DR_REG_RSA_BASE + 0x82c) + +/* RSA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable the RSA interrupt. This option is enabled by + * default. + */ + +#define RSA_INTERRUPT_ENA (BIT(0)) +#define RSA_INTERRUPT_ENA_M (RSA_INTERRUPT_ENA_V << RSA_INTERRUPT_ENA_S) +#define RSA_INTERRUPT_ENA_V 0x00000001 +#define RSA_INTERRUPT_ENA_S 0 + +/* RSA_DATE_REG register + * Version control register + */ + +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) + +/* RSA_DATE : R/W; bitpos: [29:0]; default: 538510373; + * Version control register + */ + +#define RSA_DATE 0x3FFFFFFF +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFF +#define RSA_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h new file mode 100644 index 00000000000..e0f6f151305 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h @@ -0,0 +1,3704 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCIO_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RTCIO_RTC_GPIO_OUT_REG register + * RTC GPIO output register + */ + +#define RTCIO_RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) + +/* RTCIO_GPIO_OUT_DATA : R/W; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corre- + * sponds to GPIO1, etc. + */ + +#define RTCIO_GPIO_OUT_DATA 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_M (RTCIO_GPIO_OUT_DATA_V << RTCIO_GPIO_OUT_DATA_S) +#define RTCIO_GPIO_OUT_DATA_V 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_S 10 + +/* RTCIO_RTC_GPIO_OUT_W1TS_REG register + * RTC GPIO output bit set register + */ + +#define RTCIO_RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) + +/* RTCIO_GPIO_OUT_DATA_W1TS : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, + * the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. + * Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG. + */ + +#define RTCIO_GPIO_OUT_DATA_W1TS 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_W1TS_M (RTCIO_GPIO_OUT_DATA_W1TS_V << RTCIO_GPIO_OUT_DATA_W1TS_S) +#define RTCIO_GPIO_OUT_DATA_W1TS_V 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_W1TS_S 10 + +/* RTCIO_RTC_GPIO_OUT_W1TC_REG register + * RTC GPIO output bit clear register + */ + +#define RTCIO_RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) + +/* RTCIO_GPIO_OUT_DATA_W1TC : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output clear register. If the value 1 is written to a bit + * here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. + * Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG. + */ + +#define RTCIO_GPIO_OUT_DATA_W1TC 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_W1TC_M (RTCIO_GPIO_OUT_DATA_W1TC_V << RTCIO_GPIO_OUT_DATA_W1TC_S) +#define RTCIO_GPIO_OUT_DATA_W1TC_V 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_W1TC_S 10 + +/* RTCIO_RTC_GPIO_ENABLE_REG register + * RTC GPIO output enable register + */ + +#define RTCIO_RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) + +/* RTCIO_REG_RTCIO_REG_GPIO_ENABLE : R/W; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds + * to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output. + */ + +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_M (RTCIO_REG_RTCIO_REG_GPIO_ENABLE_V << RTCIO_REG_RTCIO_REG_GPIO_ENABLE_S) +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_V 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_S 10 + +/* RTCIO_RTC_GPIO_ENABLE_W1TS_REG register + * RTC GPIO output enable bit set register + */ + +#define RTCIO_RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) + +/* RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit + * here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to + * 1. Recommended operation: use this register to set + * RTCIO_RTC_GPIO_ENABLE_REG. + */ + +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_M (RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_V << RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_S) +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_V 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_S 10 + +/* RTCIO_RTC_GPIO_ENABLE_W1TC_REG register + * RTC GPIO output enable bit clear register + */ + +#define RTCIO_RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) + +/* RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output enable clear register. If the value 1 is written to a + * bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be + * cleared. Recom- mended operation: use this register to clear + * RTCIO_RTC_GPIO_ENABLE_REG. + */ + +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_M (RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_V << RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_S) +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_V 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_S 10 + +/* RTCIO_RTC_GPIO_STATUS_REG register + * RTC GPIO interrupt status register + */ + +#define RTCIO_RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) + +/* RTCIO_GPIO_STATUS_INT : R/W; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 + * corresponds to GPIO1, etc. This register should be used together with RT- + * CIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; + * 1: corresponding interrupt. + */ + +#define RTCIO_GPIO_STATUS_INT 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_M (RTCIO_GPIO_STATUS_INT_V << RTCIO_GPIO_STATUS_INT_S) +#define RTCIO_GPIO_STATUS_INT_V 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_S 10 + +/* RTCIO_RTC_GPIO_STATUS_W1TS_REG register + * RTC GPIO interrupt status bit set register + */ + +#define RTCIO_RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) + +/* RTCIO_GPIO_STATUS_INT_W1TS : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit + * here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. + * Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT. + */ + +#define RTCIO_GPIO_STATUS_INT_W1TS 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_W1TS_M (RTCIO_GPIO_STATUS_INT_W1TS_V << RTCIO_GPIO_STATUS_INT_W1TS_S) +#define RTCIO_GPIO_STATUS_INT_W1TS_V 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_W1TS_S 10 + +/* RTCIO_RTC_GPIO_STATUS_W1TC_REG register + * RTC GPIO interrupt status bit clear register + */ + +#define RTCIO_RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) + +/* RTCIO_GPIO_STATUS_INT_W1TC : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit + * here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. + * Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT. + */ + +#define RTCIO_GPIO_STATUS_INT_W1TC 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_W1TC_M (RTCIO_GPIO_STATUS_INT_W1TC_V << RTCIO_GPIO_STATUS_INT_W1TC_S) +#define RTCIO_GPIO_STATUS_INT_W1TC_V 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_W1TC_S 10 + +/* RTCIO_RTC_GPIO_IN_REG register + * RTC GPIO input register + */ + +#define RTCIO_RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) + +/* RTCIO_GPIO_IN_NEXT : RO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to + * GPIO1, etc. Each bit represents a pad input value, 1 for high level, and + * 0 for low level. + */ + +#define RTCIO_GPIO_IN_NEXT 0x003FFFFF +#define RTCIO_GPIO_IN_NEXT_M (RTCIO_GPIO_IN_NEXT_V << RTCIO_GPIO_IN_NEXT_S) +#define RTCIO_GPIO_IN_NEXT_V 0x003FFFFF +#define RTCIO_GPIO_IN_NEXT_S 10 + +/* RTCIO_RTC_GPIO_PIN0_REG register + * RTC configuration for pin 0 + */ + +#define RTCIO_RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) + +/* RTCIO_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN0_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN0_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN0_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN0_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN0_INT_TYPE_M (RTCIO_GPIO_PIN0_INT_TYPE_V << RTCIO_GPIO_PIN0_INT_TYPE_S) +#define RTCIO_GPIO_PIN0_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN0_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN0_PAD_DRIVER_M (RTCIO_GPIO_PIN0_PAD_DRIVER_V << RTCIO_GPIO_PIN0_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN0_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN0_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN1_REG register + * RTC configuration for pin 1 + */ + +#define RTCIO_RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) + +/* RTCIO_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN1_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN1_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN1_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN1_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN1_INT_TYPE_M (RTCIO_GPIO_PIN1_INT_TYPE_V << RTCIO_GPIO_PIN1_INT_TYPE_S) +#define RTCIO_GPIO_PIN1_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN1_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN1_PAD_DRIVER_M (RTCIO_GPIO_PIN1_PAD_DRIVER_V << RTCIO_GPIO_PIN1_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN1_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN1_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN2_REG register + * RTC configuration for pin 2 + */ + +#define RTCIO_RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) + +/* RTCIO_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN2_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN2_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN2_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN2_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN2_INT_TYPE_M (RTCIO_GPIO_PIN2_INT_TYPE_V << RTCIO_GPIO_PIN2_INT_TYPE_S) +#define RTCIO_GPIO_PIN2_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN2_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN2_PAD_DRIVER_M (RTCIO_GPIO_PIN2_PAD_DRIVER_V << RTCIO_GPIO_PIN2_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN2_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN2_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN3_REG register + * RTC configuration for pin 3 + */ + +#define RTCIO_RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) + +/* RTCIO_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN3_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN3_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN3_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN3_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN3_INT_TYPE_M (RTCIO_GPIO_PIN3_INT_TYPE_V << RTCIO_GPIO_PIN3_INT_TYPE_S) +#define RTCIO_GPIO_PIN3_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN3_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN3_PAD_DRIVER_M (RTCIO_GPIO_PIN3_PAD_DRIVER_V << RTCIO_GPIO_PIN3_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN3_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN3_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN4_REG register + * RTC configuration for pin 4 + */ + +#define RTCIO_RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) + +/* RTCIO_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN4_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN4_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN4_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN4_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN4_INT_TYPE_M (RTCIO_GPIO_PIN4_INT_TYPE_V << RTCIO_GPIO_PIN4_INT_TYPE_S) +#define RTCIO_GPIO_PIN4_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN4_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN4_PAD_DRIVER_M (RTCIO_GPIO_PIN4_PAD_DRIVER_V << RTCIO_GPIO_PIN4_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN4_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN4_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN5_REG register + * RTC configuration for pin 5 + */ + +#define RTCIO_RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) + +/* RTCIO_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN5_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN5_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN5_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN5_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN5_INT_TYPE_M (RTCIO_GPIO_PIN5_INT_TYPE_V << RTCIO_GPIO_PIN5_INT_TYPE_S) +#define RTCIO_GPIO_PIN5_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN5_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN5_PAD_DRIVER_M (RTCIO_GPIO_PIN5_PAD_DRIVER_V << RTCIO_GPIO_PIN5_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN5_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN5_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN6_REG register + * RTC configuration for pin 6 + */ + +#define RTCIO_RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) + +/* RTCIO_GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN6_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN6_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN6_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN6_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN6_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN6_INT_TYPE_M (RTCIO_GPIO_PIN6_INT_TYPE_V << RTCIO_GPIO_PIN6_INT_TYPE_S) +#define RTCIO_GPIO_PIN6_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN6_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN6_PAD_DRIVER_M (RTCIO_GPIO_PIN6_PAD_DRIVER_V << RTCIO_GPIO_PIN6_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN6_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN6_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN7_REG register + * RTC configuration for pin 7 + */ + +#define RTCIO_RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) + +/* RTCIO_GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN7_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN7_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN7_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN7_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN7_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN7_INT_TYPE_M (RTCIO_GPIO_PIN7_INT_TYPE_V << RTCIO_GPIO_PIN7_INT_TYPE_S) +#define RTCIO_GPIO_PIN7_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN7_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN7_PAD_DRIVER_M (RTCIO_GPIO_PIN7_PAD_DRIVER_V << RTCIO_GPIO_PIN7_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN7_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN7_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN8_REG register + * RTC configuration for pin 8 + */ + +#define RTCIO_RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) + +/* RTCIO_GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN8_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN8_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN8_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN8_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN8_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN8_INT_TYPE_M (RTCIO_GPIO_PIN8_INT_TYPE_V << RTCIO_GPIO_PIN8_INT_TYPE_S) +#define RTCIO_GPIO_PIN8_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN8_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN8_PAD_DRIVER_M (RTCIO_GPIO_PIN8_PAD_DRIVER_V << RTCIO_GPIO_PIN8_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN8_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN8_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN9_REG register + * RTC configuration for pin 9 + */ + +#define RTCIO_RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) + +/* RTCIO_GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN9_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN9_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN9_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN9_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN9_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN9_INT_TYPE_M (RTCIO_GPIO_PIN9_INT_TYPE_V << RTCIO_GPIO_PIN9_INT_TYPE_S) +#define RTCIO_GPIO_PIN9_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN9_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN9_PAD_DRIVER_M (RTCIO_GPIO_PIN9_PAD_DRIVER_V << RTCIO_GPIO_PIN9_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN9_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN9_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN10_REG register + * RTC configuration for pin 10 + */ + +#define RTCIO_RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) + +/* RTCIO_GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN10_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN10_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN10_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN10_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN10_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN10_INT_TYPE_M (RTCIO_GPIO_PIN10_INT_TYPE_V << RTCIO_GPIO_PIN10_INT_TYPE_S) +#define RTCIO_GPIO_PIN10_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN10_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN10_PAD_DRIVER_M (RTCIO_GPIO_PIN10_PAD_DRIVER_V << RTCIO_GPIO_PIN10_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN10_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN10_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN11_REG register + * RTC configuration for pin 11 + */ + +#define RTCIO_RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) + +/* RTCIO_GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN11_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN11_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN11_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN11_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN11_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN11_INT_TYPE_M (RTCIO_GPIO_PIN11_INT_TYPE_V << RTCIO_GPIO_PIN11_INT_TYPE_S) +#define RTCIO_GPIO_PIN11_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN11_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN11_PAD_DRIVER_M (RTCIO_GPIO_PIN11_PAD_DRIVER_V << RTCIO_GPIO_PIN11_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN11_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN11_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN12_REG register + * RTC configuration for pin 12 + */ + +#define RTCIO_RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) + +/* RTCIO_GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN12_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN12_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN12_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN12_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN12_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN12_INT_TYPE_M (RTCIO_GPIO_PIN12_INT_TYPE_V << RTCIO_GPIO_PIN12_INT_TYPE_S) +#define RTCIO_GPIO_PIN12_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN12_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN12_PAD_DRIVER_M (RTCIO_GPIO_PIN12_PAD_DRIVER_V << RTCIO_GPIO_PIN12_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN12_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN12_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN13_REG register + * RTC configuration for pin 13 + */ + +#define RTCIO_RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) + +/* RTCIO_GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN13_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN13_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN13_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN13_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN13_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN13_INT_TYPE_M (RTCIO_GPIO_PIN13_INT_TYPE_V << RTCIO_GPIO_PIN13_INT_TYPE_S) +#define RTCIO_GPIO_PIN13_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN13_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN13_PAD_DRIVER_M (RTCIO_GPIO_PIN13_PAD_DRIVER_V << RTCIO_GPIO_PIN13_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN13_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN13_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN14_REG register + * RTC configuration for pin 14 + */ + +#define RTCIO_RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) + +/* RTCIO_GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN14_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN14_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN14_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN14_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN14_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN14_INT_TYPE_M (RTCIO_GPIO_PIN14_INT_TYPE_V << RTCIO_GPIO_PIN14_INT_TYPE_S) +#define RTCIO_GPIO_PIN14_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN14_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN14_PAD_DRIVER_M (RTCIO_GPIO_PIN14_PAD_DRIVER_V << RTCIO_GPIO_PIN14_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN14_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN14_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN15_REG register + * RTC configuration for pin 15 + */ + +#define RTCIO_RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) + +/* RTCIO_GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN15_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN15_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN15_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN15_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN15_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN15_INT_TYPE_M (RTCIO_GPIO_PIN15_INT_TYPE_V << RTCIO_GPIO_PIN15_INT_TYPE_S) +#define RTCIO_GPIO_PIN15_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN15_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN15_PAD_DRIVER_M (RTCIO_GPIO_PIN15_PAD_DRIVER_V << RTCIO_GPIO_PIN15_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN15_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN15_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN16_REG register + * RTC configuration for pin 16 + */ + +#define RTCIO_RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) + +/* RTCIO_GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN16_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN16_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN16_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN16_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN16_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN16_INT_TYPE_M (RTCIO_GPIO_PIN16_INT_TYPE_V << RTCIO_GPIO_PIN16_INT_TYPE_S) +#define RTCIO_GPIO_PIN16_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN16_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN16_PAD_DRIVER_M (RTCIO_GPIO_PIN16_PAD_DRIVER_V << RTCIO_GPIO_PIN16_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN16_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN16_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN17_REG register + * RTC configuration for pin 17 + */ + +#define RTCIO_RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) + +/* RTCIO_GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN17_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN17_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN17_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN17_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN17_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN17_INT_TYPE_M (RTCIO_GPIO_PIN17_INT_TYPE_V << RTCIO_GPIO_PIN17_INT_TYPE_S) +#define RTCIO_GPIO_PIN17_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN17_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN17_PAD_DRIVER_M (RTCIO_GPIO_PIN17_PAD_DRIVER_V << RTCIO_GPIO_PIN17_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN17_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN17_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN18_REG register + * RTC configuration for pin 18 + */ + +#define RTCIO_RTC_GPIO_PIN18_REG (DR_REG_RTCIO_BASE + 0x70) + +/* RTCIO_GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN18_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN18_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN18_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN18_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN18_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN18_INT_TYPE_M (RTCIO_GPIO_PIN18_INT_TYPE_V << RTCIO_GPIO_PIN18_INT_TYPE_S) +#define RTCIO_GPIO_PIN18_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN18_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN18_PAD_DRIVER_M (RTCIO_GPIO_PIN18_PAD_DRIVER_V << RTCIO_GPIO_PIN18_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN18_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN18_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN19_REG register + * RTC configuration for pin 19 + */ + +#define RTCIO_RTC_GPIO_PIN19_REG (DR_REG_RTCIO_BASE + 0x74) + +/* RTCIO_GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN19_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN19_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN19_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN19_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN19_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN19_INT_TYPE_M (RTCIO_GPIO_PIN19_INT_TYPE_V << RTCIO_GPIO_PIN19_INT_TYPE_S) +#define RTCIO_GPIO_PIN19_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN19_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN19_PAD_DRIVER_M (RTCIO_GPIO_PIN19_PAD_DRIVER_V << RTCIO_GPIO_PIN19_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN19_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN19_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN20_REG register + * RTC configuration for pin 20 + */ + +#define RTCIO_RTC_GPIO_PIN20_REG (DR_REG_RTCIO_BASE + 0x78) + +/* RTCIO_GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN20_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN20_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN20_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN20_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN20_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN20_INT_TYPE_M (RTCIO_GPIO_PIN20_INT_TYPE_V << RTCIO_GPIO_PIN20_INT_TYPE_S) +#define RTCIO_GPIO_PIN20_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN20_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN20_PAD_DRIVER_M (RTCIO_GPIO_PIN20_PAD_DRIVER_V << RTCIO_GPIO_PIN20_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN20_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN20_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN21_REG register + * RTC configuration for pin 21 + */ + +#define RTCIO_RTC_GPIO_PIN21_REG (DR_REG_RTCIO_BASE + 0x7c) + +/* RTCIO_GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN21_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN21_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN21_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN21_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN21_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN21_INT_TYPE_M (RTCIO_GPIO_PIN21_INT_TYPE_V << RTCIO_GPIO_PIN21_INT_TYPE_S) +#define RTCIO_GPIO_PIN21_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN21_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN21_PAD_DRIVER_M (RTCIO_GPIO_PIN21_PAD_DRIVER_V << RTCIO_GPIO_PIN21_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN21_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN21_PAD_DRIVER_S 2 + +/* RTCIO_RTC_DEBUG_SEL_REG register + * RTC debug select register + */ + +#define RTCIO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x80) + +/* RTCIO_RTC_DEBUG_12M_NO_GATING : R/W; bitpos: [25]; default: 0; */ + +#define RTCIO_RTC_DEBUG_12M_NO_GATING (BIT(25)) +#define RTCIO_RTC_DEBUG_12M_NO_GATING_M (RTCIO_RTC_DEBUG_12M_NO_GATING_V << RTCIO_RTC_DEBUG_12M_NO_GATING_S) +#define RTCIO_RTC_DEBUG_12M_NO_GATING_V 0x00000001 +#define RTCIO_RTC_DEBUG_12M_NO_GATING_S 25 + +/* RTCIO_RTC_DEBUG_SEL4 : R/W; bitpos: [24:20]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL4 0x0000001F +#define RTCIO_RTC_DEBUG_SEL4_M (RTCIO_RTC_DEBUG_SEL4_V << RTCIO_RTC_DEBUG_SEL4_S) +#define RTCIO_RTC_DEBUG_SEL4_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL4_S 20 + +/* RTCIO_RTC_DEBUG_SEL3 : R/W; bitpos: [19:15]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL3 0x0000001F +#define RTCIO_RTC_DEBUG_SEL3_M (RTCIO_RTC_DEBUG_SEL3_V << RTCIO_RTC_DEBUG_SEL3_S) +#define RTCIO_RTC_DEBUG_SEL3_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL3_S 15 + +/* RTCIO_RTC_DEBUG_SEL2 : R/W; bitpos: [14:10]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL2 0x0000001F +#define RTCIO_RTC_DEBUG_SEL2_M (RTCIO_RTC_DEBUG_SEL2_V << RTCIO_RTC_DEBUG_SEL2_S) +#define RTCIO_RTC_DEBUG_SEL2_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL2_S 10 + +/* RTCIO_RTC_DEBUG_SEL1 : R/W; bitpos: [9:5]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL1 0x0000001F +#define RTCIO_RTC_DEBUG_SEL1_M (RTCIO_RTC_DEBUG_SEL1_V << RTCIO_RTC_DEBUG_SEL1_S) +#define RTCIO_RTC_DEBUG_SEL1_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL1_S 5 + +/* RTCIO_RTC_DEBUG_SEL0 : R/W; bitpos: [4:0]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL0 0x0000001F +#define RTCIO_RTC_DEBUG_SEL0_M (RTCIO_RTC_DEBUG_SEL0_V << RTCIO_RTC_DEBUG_SEL0_S) +#define RTCIO_RTC_DEBUG_SEL0_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL0_S 0 + +/* RTCIO_TOUCH_PAD0_REG register + * Touch pad 0 configuration register + */ + +#define RTCIO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x84) + +/* RTCIO_TOUCH_PAD0_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD0_DRV 0x00000003 +#define RTCIO_TOUCH_PAD0_DRV_M (RTCIO_TOUCH_PAD0_DRV_V << RTCIO_TOUCH_PAD0_DRV_S) +#define RTCIO_TOUCH_PAD0_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD0_DRV_S 29 + +/* RTCIO_TOUCH_PAD0_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD0_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD0_RDE_M (RTCIO_TOUCH_PAD0_RDE_V << RTCIO_TOUCH_PAD0_RDE_S) +#define RTCIO_TOUCH_PAD0_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_RDE_S 28 + +/* RTCIO_TOUCH_PAD0_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD0_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD0_RUE_M (RTCIO_TOUCH_PAD0_RUE_V << RTCIO_TOUCH_PAD0_RUE_S) +#define RTCIO_TOUCH_PAD0_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_RUE_S 27 + +/* RTCIO_TOUCH_PAD0_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD0_DAC 0x00000007 +#define RTCIO_TOUCH_PAD0_DAC_M (RTCIO_TOUCH_PAD0_DAC_V << RTCIO_TOUCH_PAD0_DAC_S) +#define RTCIO_TOUCH_PAD0_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD0_DAC_S 23 + +/* RTCIO_TOUCH_PAD0_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD0_START (BIT(22)) +#define RTCIO_TOUCH_PAD0_START_M (RTCIO_TOUCH_PAD0_START_V << RTCIO_TOUCH_PAD0_START_S) +#define RTCIO_TOUCH_PAD0_START_V 0x00000001 +#define RTCIO_TOUCH_PAD0_START_S 22 + +/* RTCIO_TOUCH_PAD0_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD0_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD0_TIE_OPT_M (RTCIO_TOUCH_PAD0_TIE_OPT_V << RTCIO_TOUCH_PAD0_TIE_OPT_S) +#define RTCIO_TOUCH_PAD0_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD0_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD0_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD0_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD0_XPD_M (RTCIO_TOUCH_PAD0_XPD_V << RTCIO_TOUCH_PAD0_XPD_S) +#define RTCIO_TOUCH_PAD0_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD0_XPD_S 20 + +/* RTCIO_TOUCH_PAD0_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD0_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD0_MUX_SEL_M (RTCIO_TOUCH_PAD0_MUX_SEL_V << RTCIO_TOUCH_PAD0_MUX_SEL_S) +#define RTCIO_TOUCH_PAD0_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD0_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD0_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD0_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD0_FUN_SEL_M (RTCIO_TOUCH_PAD0_FUN_SEL_V << RTCIO_TOUCH_PAD0_FUN_SEL_S) +#define RTCIO_TOUCH_PAD0_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD0_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD0_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD0_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD0_SLP_SEL_M (RTCIO_TOUCH_PAD0_SLP_SEL_V << RTCIO_TOUCH_PAD0_SLP_SEL_S) +#define RTCIO_TOUCH_PAD0_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD0_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD0_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD0_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD0_SLP_IE_M (RTCIO_TOUCH_PAD0_SLP_IE_V << RTCIO_TOUCH_PAD0_SLP_IE_S) +#define RTCIO_TOUCH_PAD0_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD0_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD0_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD0_SLP_OE_M (RTCIO_TOUCH_PAD0_SLP_OE_V << RTCIO_TOUCH_PAD0_SLP_OE_S) +#define RTCIO_TOUCH_PAD0_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD0_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD0_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD0_FUN_IE_M (RTCIO_TOUCH_PAD0_FUN_IE_V << RTCIO_TOUCH_PAD0_FUN_IE_S) +#define RTCIO_TOUCH_PAD0_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD1_REG register + * Touch pad 1 configuration register + */ + +#define RTCIO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x88) + +/* RTCIO_TOUCH_PAD1_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD1_DRV 0x00000003 +#define RTCIO_TOUCH_PAD1_DRV_M (RTCIO_TOUCH_PAD1_DRV_V << RTCIO_TOUCH_PAD1_DRV_S) +#define RTCIO_TOUCH_PAD1_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD1_DRV_S 29 + +/* RTCIO_TOUCH_PAD1_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD1_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD1_RDE_M (RTCIO_TOUCH_PAD1_RDE_V << RTCIO_TOUCH_PAD1_RDE_S) +#define RTCIO_TOUCH_PAD1_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_RDE_S 28 + +/* RTCIO_TOUCH_PAD1_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD1_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD1_RUE_M (RTCIO_TOUCH_PAD1_RUE_V << RTCIO_TOUCH_PAD1_RUE_S) +#define RTCIO_TOUCH_PAD1_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_RUE_S 27 + +/* RTCIO_TOUCH_PAD1_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD1_DAC 0x00000007 +#define RTCIO_TOUCH_PAD1_DAC_M (RTCIO_TOUCH_PAD1_DAC_V << RTCIO_TOUCH_PAD1_DAC_S) +#define RTCIO_TOUCH_PAD1_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD1_DAC_S 23 + +/* RTCIO_TOUCH_PAD1_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD1_START (BIT(22)) +#define RTCIO_TOUCH_PAD1_START_M (RTCIO_TOUCH_PAD1_START_V << RTCIO_TOUCH_PAD1_START_S) +#define RTCIO_TOUCH_PAD1_START_V 0x00000001 +#define RTCIO_TOUCH_PAD1_START_S 22 + +/* RTCIO_TOUCH_PAD1_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD1_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD1_TIE_OPT_M (RTCIO_TOUCH_PAD1_TIE_OPT_V << RTCIO_TOUCH_PAD1_TIE_OPT_S) +#define RTCIO_TOUCH_PAD1_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD1_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD1_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD1_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD1_XPD_M (RTCIO_TOUCH_PAD1_XPD_V << RTCIO_TOUCH_PAD1_XPD_S) +#define RTCIO_TOUCH_PAD1_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD1_XPD_S 20 + +/* RTCIO_TOUCH_PAD1_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD1_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD1_MUX_SEL_M (RTCIO_TOUCH_PAD1_MUX_SEL_V << RTCIO_TOUCH_PAD1_MUX_SEL_S) +#define RTCIO_TOUCH_PAD1_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD1_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD1_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD1_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD1_FUN_SEL_M (RTCIO_TOUCH_PAD1_FUN_SEL_V << RTCIO_TOUCH_PAD1_FUN_SEL_S) +#define RTCIO_TOUCH_PAD1_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD1_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD1_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD1_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD1_SLP_SEL_M (RTCIO_TOUCH_PAD1_SLP_SEL_V << RTCIO_TOUCH_PAD1_SLP_SEL_S) +#define RTCIO_TOUCH_PAD1_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD1_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD1_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD1_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD1_SLP_IE_M (RTCIO_TOUCH_PAD1_SLP_IE_V << RTCIO_TOUCH_PAD1_SLP_IE_S) +#define RTCIO_TOUCH_PAD1_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD1_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD1_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD1_SLP_OE_M (RTCIO_TOUCH_PAD1_SLP_OE_V << RTCIO_TOUCH_PAD1_SLP_OE_S) +#define RTCIO_TOUCH_PAD1_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD1_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD1_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD1_FUN_IE_M (RTCIO_TOUCH_PAD1_FUN_IE_V << RTCIO_TOUCH_PAD1_FUN_IE_S) +#define RTCIO_TOUCH_PAD1_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD2_REG register + * Touch pad 2 configuration register + */ + +#define RTCIO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x8c) + +/* RTCIO_TOUCH_PAD2_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD2_DRV 0x00000003 +#define RTCIO_TOUCH_PAD2_DRV_M (RTCIO_TOUCH_PAD2_DRV_V << RTCIO_TOUCH_PAD2_DRV_S) +#define RTCIO_TOUCH_PAD2_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD2_DRV_S 29 + +/* RTCIO_TOUCH_PAD2_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD2_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD2_RDE_M (RTCIO_TOUCH_PAD2_RDE_V << RTCIO_TOUCH_PAD2_RDE_S) +#define RTCIO_TOUCH_PAD2_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_RDE_S 28 + +/* RTCIO_TOUCH_PAD2_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD2_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD2_RUE_M (RTCIO_TOUCH_PAD2_RUE_V << RTCIO_TOUCH_PAD2_RUE_S) +#define RTCIO_TOUCH_PAD2_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_RUE_S 27 + +/* RTCIO_TOUCH_PAD2_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD2_DAC 0x00000007 +#define RTCIO_TOUCH_PAD2_DAC_M (RTCIO_TOUCH_PAD2_DAC_V << RTCIO_TOUCH_PAD2_DAC_S) +#define RTCIO_TOUCH_PAD2_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD2_DAC_S 23 + +/* RTCIO_TOUCH_PAD2_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD2_START (BIT(22)) +#define RTCIO_TOUCH_PAD2_START_M (RTCIO_TOUCH_PAD2_START_V << RTCIO_TOUCH_PAD2_START_S) +#define RTCIO_TOUCH_PAD2_START_V 0x00000001 +#define RTCIO_TOUCH_PAD2_START_S 22 + +/* RTCIO_TOUCH_PAD2_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD2_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD2_TIE_OPT_M (RTCIO_TOUCH_PAD2_TIE_OPT_V << RTCIO_TOUCH_PAD2_TIE_OPT_S) +#define RTCIO_TOUCH_PAD2_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD2_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD2_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD2_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD2_XPD_M (RTCIO_TOUCH_PAD2_XPD_V << RTCIO_TOUCH_PAD2_XPD_S) +#define RTCIO_TOUCH_PAD2_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD2_XPD_S 20 + +/* RTCIO_TOUCH_PAD2_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD2_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD2_MUX_SEL_M (RTCIO_TOUCH_PAD2_MUX_SEL_V << RTCIO_TOUCH_PAD2_MUX_SEL_S) +#define RTCIO_TOUCH_PAD2_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD2_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD2_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD2_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD2_FUN_SEL_M (RTCIO_TOUCH_PAD2_FUN_SEL_V << RTCIO_TOUCH_PAD2_FUN_SEL_S) +#define RTCIO_TOUCH_PAD2_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD2_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD2_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD2_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD2_SLP_SEL_M (RTCIO_TOUCH_PAD2_SLP_SEL_V << RTCIO_TOUCH_PAD2_SLP_SEL_S) +#define RTCIO_TOUCH_PAD2_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD2_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD2_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD2_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD2_SLP_IE_M (RTCIO_TOUCH_PAD2_SLP_IE_V << RTCIO_TOUCH_PAD2_SLP_IE_S) +#define RTCIO_TOUCH_PAD2_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD2_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD2_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD2_SLP_OE_M (RTCIO_TOUCH_PAD2_SLP_OE_V << RTCIO_TOUCH_PAD2_SLP_OE_S) +#define RTCIO_TOUCH_PAD2_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD2_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD2_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD2_FUN_IE_M (RTCIO_TOUCH_PAD2_FUN_IE_V << RTCIO_TOUCH_PAD2_FUN_IE_S) +#define RTCIO_TOUCH_PAD2_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD3_REG register + * Touch pad 3 configuration register + */ + +#define RTCIO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0x90) + +/* RTCIO_TOUCH_PAD3_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD3_DRV 0x00000003 +#define RTCIO_TOUCH_PAD3_DRV_M (RTCIO_TOUCH_PAD3_DRV_V << RTCIO_TOUCH_PAD3_DRV_S) +#define RTCIO_TOUCH_PAD3_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD3_DRV_S 29 + +/* RTCIO_TOUCH_PAD3_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD3_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD3_RDE_M (RTCIO_TOUCH_PAD3_RDE_V << RTCIO_TOUCH_PAD3_RDE_S) +#define RTCIO_TOUCH_PAD3_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_RDE_S 28 + +/* RTCIO_TOUCH_PAD3_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD3_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD3_RUE_M (RTCIO_TOUCH_PAD3_RUE_V << RTCIO_TOUCH_PAD3_RUE_S) +#define RTCIO_TOUCH_PAD3_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_RUE_S 27 + +/* RTCIO_TOUCH_PAD3_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD3_DAC 0x00000007 +#define RTCIO_TOUCH_PAD3_DAC_M (RTCIO_TOUCH_PAD3_DAC_V << RTCIO_TOUCH_PAD3_DAC_S) +#define RTCIO_TOUCH_PAD3_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD3_DAC_S 23 + +/* RTCIO_TOUCH_PAD3_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD3_START (BIT(22)) +#define RTCIO_TOUCH_PAD3_START_M (RTCIO_TOUCH_PAD3_START_V << RTCIO_TOUCH_PAD3_START_S) +#define RTCIO_TOUCH_PAD3_START_V 0x00000001 +#define RTCIO_TOUCH_PAD3_START_S 22 + +/* RTCIO_TOUCH_PAD3_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD3_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD3_TIE_OPT_M (RTCIO_TOUCH_PAD3_TIE_OPT_V << RTCIO_TOUCH_PAD3_TIE_OPT_S) +#define RTCIO_TOUCH_PAD3_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD3_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD3_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD3_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD3_XPD_M (RTCIO_TOUCH_PAD3_XPD_V << RTCIO_TOUCH_PAD3_XPD_S) +#define RTCIO_TOUCH_PAD3_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD3_XPD_S 20 + +/* RTCIO_TOUCH_PAD3_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD3_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD3_MUX_SEL_M (RTCIO_TOUCH_PAD3_MUX_SEL_V << RTCIO_TOUCH_PAD3_MUX_SEL_S) +#define RTCIO_TOUCH_PAD3_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD3_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD3_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD3_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD3_FUN_SEL_M (RTCIO_TOUCH_PAD3_FUN_SEL_V << RTCIO_TOUCH_PAD3_FUN_SEL_S) +#define RTCIO_TOUCH_PAD3_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD3_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD3_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD3_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD3_SLP_SEL_M (RTCIO_TOUCH_PAD3_SLP_SEL_V << RTCIO_TOUCH_PAD3_SLP_SEL_S) +#define RTCIO_TOUCH_PAD3_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD3_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD3_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD3_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD3_SLP_IE_M (RTCIO_TOUCH_PAD3_SLP_IE_V << RTCIO_TOUCH_PAD3_SLP_IE_S) +#define RTCIO_TOUCH_PAD3_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD3_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD3_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD3_SLP_OE_M (RTCIO_TOUCH_PAD3_SLP_OE_V << RTCIO_TOUCH_PAD3_SLP_OE_S) +#define RTCIO_TOUCH_PAD3_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD3_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD3_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD3_FUN_IE_M (RTCIO_TOUCH_PAD3_FUN_IE_V << RTCIO_TOUCH_PAD3_FUN_IE_S) +#define RTCIO_TOUCH_PAD3_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD4_REG register + * Touch pad 4 configuration register + */ + +#define RTCIO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0x94) + +/* RTCIO_TOUCH_PAD4_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD4_DRV 0x00000003 +#define RTCIO_TOUCH_PAD4_DRV_M (RTCIO_TOUCH_PAD4_DRV_V << RTCIO_TOUCH_PAD4_DRV_S) +#define RTCIO_TOUCH_PAD4_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD4_DRV_S 29 + +/* RTCIO_TOUCH_PAD4_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD4_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD4_RDE_M (RTCIO_TOUCH_PAD4_RDE_V << RTCIO_TOUCH_PAD4_RDE_S) +#define RTCIO_TOUCH_PAD4_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_RDE_S 28 + +/* RTCIO_TOUCH_PAD4_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD4_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD4_RUE_M (RTCIO_TOUCH_PAD4_RUE_V << RTCIO_TOUCH_PAD4_RUE_S) +#define RTCIO_TOUCH_PAD4_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_RUE_S 27 + +/* RTCIO_TOUCH_PAD4_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD4_DAC 0x00000007 +#define RTCIO_TOUCH_PAD4_DAC_M (RTCIO_TOUCH_PAD4_DAC_V << RTCIO_TOUCH_PAD4_DAC_S) +#define RTCIO_TOUCH_PAD4_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD4_DAC_S 23 + +/* RTCIO_TOUCH_PAD4_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD4_START (BIT(22)) +#define RTCIO_TOUCH_PAD4_START_M (RTCIO_TOUCH_PAD4_START_V << RTCIO_TOUCH_PAD4_START_S) +#define RTCIO_TOUCH_PAD4_START_V 0x00000001 +#define RTCIO_TOUCH_PAD4_START_S 22 + +/* RTCIO_TOUCH_PAD4_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD4_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD4_TIE_OPT_M (RTCIO_TOUCH_PAD4_TIE_OPT_V << RTCIO_TOUCH_PAD4_TIE_OPT_S) +#define RTCIO_TOUCH_PAD4_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD4_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD4_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD4_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD4_XPD_M (RTCIO_TOUCH_PAD4_XPD_V << RTCIO_TOUCH_PAD4_XPD_S) +#define RTCIO_TOUCH_PAD4_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD4_XPD_S 20 + +/* RTCIO_TOUCH_PAD4_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD4_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD4_MUX_SEL_M (RTCIO_TOUCH_PAD4_MUX_SEL_V << RTCIO_TOUCH_PAD4_MUX_SEL_S) +#define RTCIO_TOUCH_PAD4_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD4_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD4_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD4_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD4_FUN_SEL_M (RTCIO_TOUCH_PAD4_FUN_SEL_V << RTCIO_TOUCH_PAD4_FUN_SEL_S) +#define RTCIO_TOUCH_PAD4_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD4_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD4_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD4_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD4_SLP_SEL_M (RTCIO_TOUCH_PAD4_SLP_SEL_V << RTCIO_TOUCH_PAD4_SLP_SEL_S) +#define RTCIO_TOUCH_PAD4_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD4_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD4_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD4_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD4_SLP_IE_M (RTCIO_TOUCH_PAD4_SLP_IE_V << RTCIO_TOUCH_PAD4_SLP_IE_S) +#define RTCIO_TOUCH_PAD4_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD4_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD4_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD4_SLP_OE_M (RTCIO_TOUCH_PAD4_SLP_OE_V << RTCIO_TOUCH_PAD4_SLP_OE_S) +#define RTCIO_TOUCH_PAD4_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD4_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD4_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD4_FUN_IE_M (RTCIO_TOUCH_PAD4_FUN_IE_V << RTCIO_TOUCH_PAD4_FUN_IE_S) +#define RTCIO_TOUCH_PAD4_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD5_REG register + * Touch pad 5 configuration register + */ + +#define RTCIO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0x98) + +/* RTCIO_TOUCH_PAD5_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD5_DRV 0x00000003 +#define RTCIO_TOUCH_PAD5_DRV_M (RTCIO_TOUCH_PAD5_DRV_V << RTCIO_TOUCH_PAD5_DRV_S) +#define RTCIO_TOUCH_PAD5_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD5_DRV_S 29 + +/* RTCIO_TOUCH_PAD5_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD5_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD5_RDE_M (RTCIO_TOUCH_PAD5_RDE_V << RTCIO_TOUCH_PAD5_RDE_S) +#define RTCIO_TOUCH_PAD5_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_RDE_S 28 + +/* RTCIO_TOUCH_PAD5_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD5_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD5_RUE_M (RTCIO_TOUCH_PAD5_RUE_V << RTCIO_TOUCH_PAD5_RUE_S) +#define RTCIO_TOUCH_PAD5_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_RUE_S 27 + +/* RTCIO_TOUCH_PAD5_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD5_DAC 0x00000007 +#define RTCIO_TOUCH_PAD5_DAC_M (RTCIO_TOUCH_PAD5_DAC_V << RTCIO_TOUCH_PAD5_DAC_S) +#define RTCIO_TOUCH_PAD5_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD5_DAC_S 23 + +/* RTCIO_TOUCH_PAD5_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD5_START (BIT(22)) +#define RTCIO_TOUCH_PAD5_START_M (RTCIO_TOUCH_PAD5_START_V << RTCIO_TOUCH_PAD5_START_S) +#define RTCIO_TOUCH_PAD5_START_V 0x00000001 +#define RTCIO_TOUCH_PAD5_START_S 22 + +/* RTCIO_TOUCH_PAD5_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD5_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD5_TIE_OPT_M (RTCIO_TOUCH_PAD5_TIE_OPT_V << RTCIO_TOUCH_PAD5_TIE_OPT_S) +#define RTCIO_TOUCH_PAD5_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD5_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD5_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD5_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD5_XPD_M (RTCIO_TOUCH_PAD5_XPD_V << RTCIO_TOUCH_PAD5_XPD_S) +#define RTCIO_TOUCH_PAD5_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD5_XPD_S 20 + +/* RTCIO_TOUCH_PAD5_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD5_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD5_MUX_SEL_M (RTCIO_TOUCH_PAD5_MUX_SEL_V << RTCIO_TOUCH_PAD5_MUX_SEL_S) +#define RTCIO_TOUCH_PAD5_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD5_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD5_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD5_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD5_FUN_SEL_M (RTCIO_TOUCH_PAD5_FUN_SEL_V << RTCIO_TOUCH_PAD5_FUN_SEL_S) +#define RTCIO_TOUCH_PAD5_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD5_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD5_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD5_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD5_SLP_SEL_M (RTCIO_TOUCH_PAD5_SLP_SEL_V << RTCIO_TOUCH_PAD5_SLP_SEL_S) +#define RTCIO_TOUCH_PAD5_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD5_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD5_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD5_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD5_SLP_IE_M (RTCIO_TOUCH_PAD5_SLP_IE_V << RTCIO_TOUCH_PAD5_SLP_IE_S) +#define RTCIO_TOUCH_PAD5_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD5_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD5_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD5_SLP_OE_M (RTCIO_TOUCH_PAD5_SLP_OE_V << RTCIO_TOUCH_PAD5_SLP_OE_S) +#define RTCIO_TOUCH_PAD5_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD5_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD5_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD5_FUN_IE_M (RTCIO_TOUCH_PAD5_FUN_IE_V << RTCIO_TOUCH_PAD5_FUN_IE_S) +#define RTCIO_TOUCH_PAD5_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD6_REG register + * Touch pad 6 configuration register + */ + +#define RTCIO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0x9c) + +/* RTCIO_TOUCH_PAD6_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD6_DRV 0x00000003 +#define RTCIO_TOUCH_PAD6_DRV_M (RTCIO_TOUCH_PAD6_DRV_V << RTCIO_TOUCH_PAD6_DRV_S) +#define RTCIO_TOUCH_PAD6_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD6_DRV_S 29 + +/* RTCIO_TOUCH_PAD6_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD6_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD6_RDE_M (RTCIO_TOUCH_PAD6_RDE_V << RTCIO_TOUCH_PAD6_RDE_S) +#define RTCIO_TOUCH_PAD6_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_RDE_S 28 + +/* RTCIO_TOUCH_PAD6_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD6_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD6_RUE_M (RTCIO_TOUCH_PAD6_RUE_V << RTCIO_TOUCH_PAD6_RUE_S) +#define RTCIO_TOUCH_PAD6_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_RUE_S 27 + +/* RTCIO_TOUCH_PAD6_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD6_DAC 0x00000007 +#define RTCIO_TOUCH_PAD6_DAC_M (RTCIO_TOUCH_PAD6_DAC_V << RTCIO_TOUCH_PAD6_DAC_S) +#define RTCIO_TOUCH_PAD6_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD6_DAC_S 23 + +/* RTCIO_TOUCH_PAD6_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD6_START (BIT(22)) +#define RTCIO_TOUCH_PAD6_START_M (RTCIO_TOUCH_PAD6_START_V << RTCIO_TOUCH_PAD6_START_S) +#define RTCIO_TOUCH_PAD6_START_V 0x00000001 +#define RTCIO_TOUCH_PAD6_START_S 22 + +/* RTCIO_TOUCH_PAD6_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD6_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD6_TIE_OPT_M (RTCIO_TOUCH_PAD6_TIE_OPT_V << RTCIO_TOUCH_PAD6_TIE_OPT_S) +#define RTCIO_TOUCH_PAD6_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD6_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD6_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD6_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD6_XPD_M (RTCIO_TOUCH_PAD6_XPD_V << RTCIO_TOUCH_PAD6_XPD_S) +#define RTCIO_TOUCH_PAD6_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD6_XPD_S 20 + +/* RTCIO_TOUCH_PAD6_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD6_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD6_MUX_SEL_M (RTCIO_TOUCH_PAD6_MUX_SEL_V << RTCIO_TOUCH_PAD6_MUX_SEL_S) +#define RTCIO_TOUCH_PAD6_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD6_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD6_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD6_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD6_FUN_SEL_M (RTCIO_TOUCH_PAD6_FUN_SEL_V << RTCIO_TOUCH_PAD6_FUN_SEL_S) +#define RTCIO_TOUCH_PAD6_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD6_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD6_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD6_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD6_SLP_SEL_M (RTCIO_TOUCH_PAD6_SLP_SEL_V << RTCIO_TOUCH_PAD6_SLP_SEL_S) +#define RTCIO_TOUCH_PAD6_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD6_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD6_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD6_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD6_SLP_IE_M (RTCIO_TOUCH_PAD6_SLP_IE_V << RTCIO_TOUCH_PAD6_SLP_IE_S) +#define RTCIO_TOUCH_PAD6_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD6_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD6_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD6_SLP_OE_M (RTCIO_TOUCH_PAD6_SLP_OE_V << RTCIO_TOUCH_PAD6_SLP_OE_S) +#define RTCIO_TOUCH_PAD6_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD6_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD6_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD6_FUN_IE_M (RTCIO_TOUCH_PAD6_FUN_IE_V << RTCIO_TOUCH_PAD6_FUN_IE_S) +#define RTCIO_TOUCH_PAD6_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD7_REG register + * Touch pad 7 configuration register + */ + +#define RTCIO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xa0) + +/* RTCIO_TOUCH_PAD7_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD7_DRV 0x00000003 +#define RTCIO_TOUCH_PAD7_DRV_M (RTCIO_TOUCH_PAD7_DRV_V << RTCIO_TOUCH_PAD7_DRV_S) +#define RTCIO_TOUCH_PAD7_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD7_DRV_S 29 + +/* RTCIO_TOUCH_PAD7_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD7_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD7_RDE_M (RTCIO_TOUCH_PAD7_RDE_V << RTCIO_TOUCH_PAD7_RDE_S) +#define RTCIO_TOUCH_PAD7_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_RDE_S 28 + +/* RTCIO_TOUCH_PAD7_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD7_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD7_RUE_M (RTCIO_TOUCH_PAD7_RUE_V << RTCIO_TOUCH_PAD7_RUE_S) +#define RTCIO_TOUCH_PAD7_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_RUE_S 27 + +/* RTCIO_TOUCH_PAD7_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD7_DAC 0x00000007 +#define RTCIO_TOUCH_PAD7_DAC_M (RTCIO_TOUCH_PAD7_DAC_V << RTCIO_TOUCH_PAD7_DAC_S) +#define RTCIO_TOUCH_PAD7_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD7_DAC_S 23 + +/* RTCIO_TOUCH_PAD7_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD7_START (BIT(22)) +#define RTCIO_TOUCH_PAD7_START_M (RTCIO_TOUCH_PAD7_START_V << RTCIO_TOUCH_PAD7_START_S) +#define RTCIO_TOUCH_PAD7_START_V 0x00000001 +#define RTCIO_TOUCH_PAD7_START_S 22 + +/* RTCIO_TOUCH_PAD7_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD7_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD7_TIE_OPT_M (RTCIO_TOUCH_PAD7_TIE_OPT_V << RTCIO_TOUCH_PAD7_TIE_OPT_S) +#define RTCIO_TOUCH_PAD7_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD7_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD7_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD7_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD7_XPD_M (RTCIO_TOUCH_PAD7_XPD_V << RTCIO_TOUCH_PAD7_XPD_S) +#define RTCIO_TOUCH_PAD7_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD7_XPD_S 20 + +/* RTCIO_TOUCH_PAD7_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD7_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD7_MUX_SEL_M (RTCIO_TOUCH_PAD7_MUX_SEL_V << RTCIO_TOUCH_PAD7_MUX_SEL_S) +#define RTCIO_TOUCH_PAD7_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD7_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD7_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD7_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD7_FUN_SEL_M (RTCIO_TOUCH_PAD7_FUN_SEL_V << RTCIO_TOUCH_PAD7_FUN_SEL_S) +#define RTCIO_TOUCH_PAD7_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD7_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD7_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD7_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD7_SLP_SEL_M (RTCIO_TOUCH_PAD7_SLP_SEL_V << RTCIO_TOUCH_PAD7_SLP_SEL_S) +#define RTCIO_TOUCH_PAD7_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD7_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD7_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD7_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD7_SLP_IE_M (RTCIO_TOUCH_PAD7_SLP_IE_V << RTCIO_TOUCH_PAD7_SLP_IE_S) +#define RTCIO_TOUCH_PAD7_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD7_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD7_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD7_SLP_OE_M (RTCIO_TOUCH_PAD7_SLP_OE_V << RTCIO_TOUCH_PAD7_SLP_OE_S) +#define RTCIO_TOUCH_PAD7_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD7_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD7_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD7_FUN_IE_M (RTCIO_TOUCH_PAD7_FUN_IE_V << RTCIO_TOUCH_PAD7_FUN_IE_S) +#define RTCIO_TOUCH_PAD7_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD8_REG register + * Touch pad 8 configuration register + */ + +#define RTCIO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xa4) + +/* RTCIO_TOUCH_PAD8_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD8_DRV 0x00000003 +#define RTCIO_TOUCH_PAD8_DRV_M (RTCIO_TOUCH_PAD8_DRV_V << RTCIO_TOUCH_PAD8_DRV_S) +#define RTCIO_TOUCH_PAD8_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD8_DRV_S 29 + +/* RTCIO_TOUCH_PAD8_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD8_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD8_RDE_M (RTCIO_TOUCH_PAD8_RDE_V << RTCIO_TOUCH_PAD8_RDE_S) +#define RTCIO_TOUCH_PAD8_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_RDE_S 28 + +/* RTCIO_TOUCH_PAD8_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD8_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD8_RUE_M (RTCIO_TOUCH_PAD8_RUE_V << RTCIO_TOUCH_PAD8_RUE_S) +#define RTCIO_TOUCH_PAD8_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_RUE_S 27 + +/* RTCIO_TOUCH_PAD8_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD8_DAC 0x00000007 +#define RTCIO_TOUCH_PAD8_DAC_M (RTCIO_TOUCH_PAD8_DAC_V << RTCIO_TOUCH_PAD8_DAC_S) +#define RTCIO_TOUCH_PAD8_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD8_DAC_S 23 + +/* RTCIO_TOUCH_PAD8_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD8_START (BIT(22)) +#define RTCIO_TOUCH_PAD8_START_M (RTCIO_TOUCH_PAD8_START_V << RTCIO_TOUCH_PAD8_START_S) +#define RTCIO_TOUCH_PAD8_START_V 0x00000001 +#define RTCIO_TOUCH_PAD8_START_S 22 + +/* RTCIO_TOUCH_PAD8_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD8_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD8_TIE_OPT_M (RTCIO_TOUCH_PAD8_TIE_OPT_V << RTCIO_TOUCH_PAD8_TIE_OPT_S) +#define RTCIO_TOUCH_PAD8_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD8_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD8_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD8_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD8_XPD_M (RTCIO_TOUCH_PAD8_XPD_V << RTCIO_TOUCH_PAD8_XPD_S) +#define RTCIO_TOUCH_PAD8_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD8_XPD_S 20 + +/* RTCIO_TOUCH_PAD8_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD8_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD8_MUX_SEL_M (RTCIO_TOUCH_PAD8_MUX_SEL_V << RTCIO_TOUCH_PAD8_MUX_SEL_S) +#define RTCIO_TOUCH_PAD8_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD8_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD8_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD8_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD8_FUN_SEL_M (RTCIO_TOUCH_PAD8_FUN_SEL_V << RTCIO_TOUCH_PAD8_FUN_SEL_S) +#define RTCIO_TOUCH_PAD8_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD8_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD8_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD8_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD8_SLP_SEL_M (RTCIO_TOUCH_PAD8_SLP_SEL_V << RTCIO_TOUCH_PAD8_SLP_SEL_S) +#define RTCIO_TOUCH_PAD8_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD8_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD8_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD8_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD8_SLP_IE_M (RTCIO_TOUCH_PAD8_SLP_IE_V << RTCIO_TOUCH_PAD8_SLP_IE_S) +#define RTCIO_TOUCH_PAD8_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD8_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD8_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD8_SLP_OE_M (RTCIO_TOUCH_PAD8_SLP_OE_V << RTCIO_TOUCH_PAD8_SLP_OE_S) +#define RTCIO_TOUCH_PAD8_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD8_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD8_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD8_FUN_IE_M (RTCIO_TOUCH_PAD8_FUN_IE_V << RTCIO_TOUCH_PAD8_FUN_IE_S) +#define RTCIO_TOUCH_PAD8_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD9_REG register + * Touch pad 9 configuration register + */ + +#define RTCIO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xa8) + +/* RTCIO_TOUCH_PAD9_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD9_DRV 0x00000003 +#define RTCIO_TOUCH_PAD9_DRV_M (RTCIO_TOUCH_PAD9_DRV_V << RTCIO_TOUCH_PAD9_DRV_S) +#define RTCIO_TOUCH_PAD9_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD9_DRV_S 29 + +/* RTCIO_TOUCH_PAD9_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD9_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD9_RDE_M (RTCIO_TOUCH_PAD9_RDE_V << RTCIO_TOUCH_PAD9_RDE_S) +#define RTCIO_TOUCH_PAD9_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_RDE_S 28 + +/* RTCIO_TOUCH_PAD9_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD9_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD9_RUE_M (RTCIO_TOUCH_PAD9_RUE_V << RTCIO_TOUCH_PAD9_RUE_S) +#define RTCIO_TOUCH_PAD9_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_RUE_S 27 + +/* RTCIO_TOUCH_PAD9_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD9_DAC 0x00000007 +#define RTCIO_TOUCH_PAD9_DAC_M (RTCIO_TOUCH_PAD9_DAC_V << RTCIO_TOUCH_PAD9_DAC_S) +#define RTCIO_TOUCH_PAD9_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD9_DAC_S 23 + +/* RTCIO_TOUCH_PAD9_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD9_START (BIT(22)) +#define RTCIO_TOUCH_PAD9_START_M (RTCIO_TOUCH_PAD9_START_V << RTCIO_TOUCH_PAD9_START_S) +#define RTCIO_TOUCH_PAD9_START_V 0x00000001 +#define RTCIO_TOUCH_PAD9_START_S 22 + +/* RTCIO_TOUCH_PAD9_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD9_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD9_TIE_OPT_M (RTCIO_TOUCH_PAD9_TIE_OPT_V << RTCIO_TOUCH_PAD9_TIE_OPT_S) +#define RTCIO_TOUCH_PAD9_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD9_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD9_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD9_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD9_XPD_M (RTCIO_TOUCH_PAD9_XPD_V << RTCIO_TOUCH_PAD9_XPD_S) +#define RTCIO_TOUCH_PAD9_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD9_XPD_S 20 + +/* RTCIO_TOUCH_PAD9_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD9_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD9_MUX_SEL_M (RTCIO_TOUCH_PAD9_MUX_SEL_V << RTCIO_TOUCH_PAD9_MUX_SEL_S) +#define RTCIO_TOUCH_PAD9_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD9_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD9_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD9_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD9_FUN_SEL_M (RTCIO_TOUCH_PAD9_FUN_SEL_V << RTCIO_TOUCH_PAD9_FUN_SEL_S) +#define RTCIO_TOUCH_PAD9_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD9_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD9_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD9_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD9_SLP_SEL_M (RTCIO_TOUCH_PAD9_SLP_SEL_V << RTCIO_TOUCH_PAD9_SLP_SEL_S) +#define RTCIO_TOUCH_PAD9_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD9_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD9_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD9_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD9_SLP_IE_M (RTCIO_TOUCH_PAD9_SLP_IE_V << RTCIO_TOUCH_PAD9_SLP_IE_S) +#define RTCIO_TOUCH_PAD9_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD9_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD9_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD9_SLP_OE_M (RTCIO_TOUCH_PAD9_SLP_OE_V << RTCIO_TOUCH_PAD9_SLP_OE_S) +#define RTCIO_TOUCH_PAD9_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD9_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD9_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD9_FUN_IE_M (RTCIO_TOUCH_PAD9_FUN_IE_V << RTCIO_TOUCH_PAD9_FUN_IE_S) +#define RTCIO_TOUCH_PAD9_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD10_REG register + * Touch pad 10 configuration register + */ + +#define RTCIO_TOUCH_PAD10_REG (DR_REG_RTCIO_BASE + 0xac) + +/* RTCIO_TOUCH_PAD10_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD10_DRV 0x00000003 +#define RTCIO_TOUCH_PAD10_DRV_M (RTCIO_TOUCH_PAD10_DRV_V << RTCIO_TOUCH_PAD10_DRV_S) +#define RTCIO_TOUCH_PAD10_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD10_DRV_S 29 + +/* RTCIO_TOUCH_PAD10_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD10_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD10_RDE_M (RTCIO_TOUCH_PAD10_RDE_V << RTCIO_TOUCH_PAD10_RDE_S) +#define RTCIO_TOUCH_PAD10_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_RDE_S 28 + +/* RTCIO_TOUCH_PAD10_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD10_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD10_RUE_M (RTCIO_TOUCH_PAD10_RUE_V << RTCIO_TOUCH_PAD10_RUE_S) +#define RTCIO_TOUCH_PAD10_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_RUE_S 27 + +/* RTCIO_TOUCH_PAD10_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD10_DAC 0x00000007 +#define RTCIO_TOUCH_PAD10_DAC_M (RTCIO_TOUCH_PAD10_DAC_V << RTCIO_TOUCH_PAD10_DAC_S) +#define RTCIO_TOUCH_PAD10_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD10_DAC_S 23 + +/* RTCIO_TOUCH_PAD10_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD10_START (BIT(22)) +#define RTCIO_TOUCH_PAD10_START_M (RTCIO_TOUCH_PAD10_START_V << RTCIO_TOUCH_PAD10_START_S) +#define RTCIO_TOUCH_PAD10_START_V 0x00000001 +#define RTCIO_TOUCH_PAD10_START_S 22 + +/* RTCIO_TOUCH_PAD10_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD10_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD10_TIE_OPT_M (RTCIO_TOUCH_PAD10_TIE_OPT_V << RTCIO_TOUCH_PAD10_TIE_OPT_S) +#define RTCIO_TOUCH_PAD10_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD10_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD10_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD10_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD10_XPD_M (RTCIO_TOUCH_PAD10_XPD_V << RTCIO_TOUCH_PAD10_XPD_S) +#define RTCIO_TOUCH_PAD10_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD10_XPD_S 20 + +/* RTCIO_TOUCH_PAD10_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD10_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD10_MUX_SEL_M (RTCIO_TOUCH_PAD10_MUX_SEL_V << RTCIO_TOUCH_PAD10_MUX_SEL_S) +#define RTCIO_TOUCH_PAD10_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD10_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD10_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD10_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD10_FUN_SEL_M (RTCIO_TOUCH_PAD10_FUN_SEL_V << RTCIO_TOUCH_PAD10_FUN_SEL_S) +#define RTCIO_TOUCH_PAD10_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD10_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD10_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD10_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD10_SLP_SEL_M (RTCIO_TOUCH_PAD10_SLP_SEL_V << RTCIO_TOUCH_PAD10_SLP_SEL_S) +#define RTCIO_TOUCH_PAD10_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD10_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD10_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD10_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD10_SLP_IE_M (RTCIO_TOUCH_PAD10_SLP_IE_V << RTCIO_TOUCH_PAD10_SLP_IE_S) +#define RTCIO_TOUCH_PAD10_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD10_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD10_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD10_SLP_OE_M (RTCIO_TOUCH_PAD10_SLP_OE_V << RTCIO_TOUCH_PAD10_SLP_OE_S) +#define RTCIO_TOUCH_PAD10_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD10_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD10_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD10_FUN_IE_M (RTCIO_TOUCH_PAD10_FUN_IE_V << RTCIO_TOUCH_PAD10_FUN_IE_S) +#define RTCIO_TOUCH_PAD10_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD11_REG register + * Touch pad 11 configuration register + */ + +#define RTCIO_TOUCH_PAD11_REG (DR_REG_RTCIO_BASE + 0xb0) + +/* RTCIO_TOUCH_PAD11_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD11_DRV 0x00000003 +#define RTCIO_TOUCH_PAD11_DRV_M (RTCIO_TOUCH_PAD11_DRV_V << RTCIO_TOUCH_PAD11_DRV_S) +#define RTCIO_TOUCH_PAD11_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD11_DRV_S 29 + +/* RTCIO_TOUCH_PAD11_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD11_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD11_RDE_M (RTCIO_TOUCH_PAD11_RDE_V << RTCIO_TOUCH_PAD11_RDE_S) +#define RTCIO_TOUCH_PAD11_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_RDE_S 28 + +/* RTCIO_TOUCH_PAD11_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD11_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD11_RUE_M (RTCIO_TOUCH_PAD11_RUE_V << RTCIO_TOUCH_PAD11_RUE_S) +#define RTCIO_TOUCH_PAD11_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_RUE_S 27 + +/* RTCIO_TOUCH_PAD11_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD11_DAC 0x00000007 +#define RTCIO_TOUCH_PAD11_DAC_M (RTCIO_TOUCH_PAD11_DAC_V << RTCIO_TOUCH_PAD11_DAC_S) +#define RTCIO_TOUCH_PAD11_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD11_DAC_S 23 + +/* RTCIO_TOUCH_PAD11_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD11_START (BIT(22)) +#define RTCIO_TOUCH_PAD11_START_M (RTCIO_TOUCH_PAD11_START_V << RTCIO_TOUCH_PAD11_START_S) +#define RTCIO_TOUCH_PAD11_START_V 0x00000001 +#define RTCIO_TOUCH_PAD11_START_S 22 + +/* RTCIO_TOUCH_PAD11_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD11_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD11_TIE_OPT_M (RTCIO_TOUCH_PAD11_TIE_OPT_V << RTCIO_TOUCH_PAD11_TIE_OPT_S) +#define RTCIO_TOUCH_PAD11_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD11_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD11_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD11_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD11_XPD_M (RTCIO_TOUCH_PAD11_XPD_V << RTCIO_TOUCH_PAD11_XPD_S) +#define RTCIO_TOUCH_PAD11_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD11_XPD_S 20 + +/* RTCIO_TOUCH_PAD11_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD11_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD11_MUX_SEL_M (RTCIO_TOUCH_PAD11_MUX_SEL_V << RTCIO_TOUCH_PAD11_MUX_SEL_S) +#define RTCIO_TOUCH_PAD11_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD11_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD11_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD11_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD11_FUN_SEL_M (RTCIO_TOUCH_PAD11_FUN_SEL_V << RTCIO_TOUCH_PAD11_FUN_SEL_S) +#define RTCIO_TOUCH_PAD11_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD11_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD11_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD11_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD11_SLP_SEL_M (RTCIO_TOUCH_PAD11_SLP_SEL_V << RTCIO_TOUCH_PAD11_SLP_SEL_S) +#define RTCIO_TOUCH_PAD11_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD11_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD11_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD11_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD11_SLP_IE_M (RTCIO_TOUCH_PAD11_SLP_IE_V << RTCIO_TOUCH_PAD11_SLP_IE_S) +#define RTCIO_TOUCH_PAD11_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD11_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD11_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD11_SLP_OE_M (RTCIO_TOUCH_PAD11_SLP_OE_V << RTCIO_TOUCH_PAD11_SLP_OE_S) +#define RTCIO_TOUCH_PAD11_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD11_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD11_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD11_FUN_IE_M (RTCIO_TOUCH_PAD11_FUN_IE_V << RTCIO_TOUCH_PAD11_FUN_IE_S) +#define RTCIO_TOUCH_PAD11_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD12_REG register + * Touch pad 12 configuration register + */ + +#define RTCIO_TOUCH_PAD12_REG (DR_REG_RTCIO_BASE + 0xb4) + +/* RTCIO_TOUCH_PAD12_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD12_DRV 0x00000003 +#define RTCIO_TOUCH_PAD12_DRV_M (RTCIO_TOUCH_PAD12_DRV_V << RTCIO_TOUCH_PAD12_DRV_S) +#define RTCIO_TOUCH_PAD12_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD12_DRV_S 29 + +/* RTCIO_TOUCH_PAD12_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD12_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD12_RDE_M (RTCIO_TOUCH_PAD12_RDE_V << RTCIO_TOUCH_PAD12_RDE_S) +#define RTCIO_TOUCH_PAD12_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_RDE_S 28 + +/* RTCIO_TOUCH_PAD12_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD12_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD12_RUE_M (RTCIO_TOUCH_PAD12_RUE_V << RTCIO_TOUCH_PAD12_RUE_S) +#define RTCIO_TOUCH_PAD12_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_RUE_S 27 + +/* RTCIO_TOUCH_PAD12_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD12_DAC 0x00000007 +#define RTCIO_TOUCH_PAD12_DAC_M (RTCIO_TOUCH_PAD12_DAC_V << RTCIO_TOUCH_PAD12_DAC_S) +#define RTCIO_TOUCH_PAD12_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD12_DAC_S 23 + +/* RTCIO_TOUCH_PAD12_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD12_START (BIT(22)) +#define RTCIO_TOUCH_PAD12_START_M (RTCIO_TOUCH_PAD12_START_V << RTCIO_TOUCH_PAD12_START_S) +#define RTCIO_TOUCH_PAD12_START_V 0x00000001 +#define RTCIO_TOUCH_PAD12_START_S 22 + +/* RTCIO_TOUCH_PAD12_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD12_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD12_TIE_OPT_M (RTCIO_TOUCH_PAD12_TIE_OPT_V << RTCIO_TOUCH_PAD12_TIE_OPT_S) +#define RTCIO_TOUCH_PAD12_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD12_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD12_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD12_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD12_XPD_M (RTCIO_TOUCH_PAD12_XPD_V << RTCIO_TOUCH_PAD12_XPD_S) +#define RTCIO_TOUCH_PAD12_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD12_XPD_S 20 + +/* RTCIO_TOUCH_PAD12_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD12_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD12_MUX_SEL_M (RTCIO_TOUCH_PAD12_MUX_SEL_V << RTCIO_TOUCH_PAD12_MUX_SEL_S) +#define RTCIO_TOUCH_PAD12_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD12_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD12_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD12_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD12_FUN_SEL_M (RTCIO_TOUCH_PAD12_FUN_SEL_V << RTCIO_TOUCH_PAD12_FUN_SEL_S) +#define RTCIO_TOUCH_PAD12_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD12_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD12_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD12_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD12_SLP_SEL_M (RTCIO_TOUCH_PAD12_SLP_SEL_V << RTCIO_TOUCH_PAD12_SLP_SEL_S) +#define RTCIO_TOUCH_PAD12_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD12_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD12_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD12_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD12_SLP_IE_M (RTCIO_TOUCH_PAD12_SLP_IE_V << RTCIO_TOUCH_PAD12_SLP_IE_S) +#define RTCIO_TOUCH_PAD12_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD12_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD12_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD12_SLP_OE_M (RTCIO_TOUCH_PAD12_SLP_OE_V << RTCIO_TOUCH_PAD12_SLP_OE_S) +#define RTCIO_TOUCH_PAD12_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD12_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD12_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD12_FUN_IE_M (RTCIO_TOUCH_PAD12_FUN_IE_V << RTCIO_TOUCH_PAD12_FUN_IE_S) +#define RTCIO_TOUCH_PAD12_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD13_REG register + * Touch pad 13 configuration register + */ + +#define RTCIO_TOUCH_PAD13_REG (DR_REG_RTCIO_BASE + 0xb8) + +/* RTCIO_TOUCH_PAD13_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD13_DRV 0x00000003 +#define RTCIO_TOUCH_PAD13_DRV_M (RTCIO_TOUCH_PAD13_DRV_V << RTCIO_TOUCH_PAD13_DRV_S) +#define RTCIO_TOUCH_PAD13_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD13_DRV_S 29 + +/* RTCIO_TOUCH_PAD13_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD13_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD13_RDE_M (RTCIO_TOUCH_PAD13_RDE_V << RTCIO_TOUCH_PAD13_RDE_S) +#define RTCIO_TOUCH_PAD13_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_RDE_S 28 + +/* RTCIO_TOUCH_PAD13_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD13_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD13_RUE_M (RTCIO_TOUCH_PAD13_RUE_V << RTCIO_TOUCH_PAD13_RUE_S) +#define RTCIO_TOUCH_PAD13_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_RUE_S 27 + +/* RTCIO_TOUCH_PAD13_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD13_DAC 0x00000007 +#define RTCIO_TOUCH_PAD13_DAC_M (RTCIO_TOUCH_PAD13_DAC_V << RTCIO_TOUCH_PAD13_DAC_S) +#define RTCIO_TOUCH_PAD13_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD13_DAC_S 23 + +/* RTCIO_TOUCH_PAD13_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD13_START (BIT(22)) +#define RTCIO_TOUCH_PAD13_START_M (RTCIO_TOUCH_PAD13_START_V << RTCIO_TOUCH_PAD13_START_S) +#define RTCIO_TOUCH_PAD13_START_V 0x00000001 +#define RTCIO_TOUCH_PAD13_START_S 22 + +/* RTCIO_TOUCH_PAD13_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD13_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD13_TIE_OPT_M (RTCIO_TOUCH_PAD13_TIE_OPT_V << RTCIO_TOUCH_PAD13_TIE_OPT_S) +#define RTCIO_TOUCH_PAD13_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD13_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD13_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD13_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD13_XPD_M (RTCIO_TOUCH_PAD13_XPD_V << RTCIO_TOUCH_PAD13_XPD_S) +#define RTCIO_TOUCH_PAD13_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD13_XPD_S 20 + +/* RTCIO_TOUCH_PAD13_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD13_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD13_MUX_SEL_M (RTCIO_TOUCH_PAD13_MUX_SEL_V << RTCIO_TOUCH_PAD13_MUX_SEL_S) +#define RTCIO_TOUCH_PAD13_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD13_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD13_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD13_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD13_FUN_SEL_M (RTCIO_TOUCH_PAD13_FUN_SEL_V << RTCIO_TOUCH_PAD13_FUN_SEL_S) +#define RTCIO_TOUCH_PAD13_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD13_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD13_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD13_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD13_SLP_SEL_M (RTCIO_TOUCH_PAD13_SLP_SEL_V << RTCIO_TOUCH_PAD13_SLP_SEL_S) +#define RTCIO_TOUCH_PAD13_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD13_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD13_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD13_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD13_SLP_IE_M (RTCIO_TOUCH_PAD13_SLP_IE_V << RTCIO_TOUCH_PAD13_SLP_IE_S) +#define RTCIO_TOUCH_PAD13_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD13_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD13_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD13_SLP_OE_M (RTCIO_TOUCH_PAD13_SLP_OE_V << RTCIO_TOUCH_PAD13_SLP_OE_S) +#define RTCIO_TOUCH_PAD13_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD13_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD13_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD13_FUN_IE_M (RTCIO_TOUCH_PAD13_FUN_IE_V << RTCIO_TOUCH_PAD13_FUN_IE_S) +#define RTCIO_TOUCH_PAD13_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD14_REG register + * Touch pad 14 configuration register + */ + +#define RTCIO_TOUCH_PAD14_REG (DR_REG_RTCIO_BASE + 0xbc) + +/* RTCIO_TOUCH_PAD14_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD14_DRV 0x00000003 +#define RTCIO_TOUCH_PAD14_DRV_M (RTCIO_TOUCH_PAD14_DRV_V << RTCIO_TOUCH_PAD14_DRV_S) +#define RTCIO_TOUCH_PAD14_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD14_DRV_S 29 + +/* RTCIO_TOUCH_PAD14_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD14_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD14_RDE_M (RTCIO_TOUCH_PAD14_RDE_V << RTCIO_TOUCH_PAD14_RDE_S) +#define RTCIO_TOUCH_PAD14_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_RDE_S 28 + +/* RTCIO_TOUCH_PAD14_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD14_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD14_RUE_M (RTCIO_TOUCH_PAD14_RUE_V << RTCIO_TOUCH_PAD14_RUE_S) +#define RTCIO_TOUCH_PAD14_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_RUE_S 27 + +/* RTCIO_TOUCH_PAD14_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD14_DAC 0x00000007 +#define RTCIO_TOUCH_PAD14_DAC_M (RTCIO_TOUCH_PAD14_DAC_V << RTCIO_TOUCH_PAD14_DAC_S) +#define RTCIO_TOUCH_PAD14_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD14_DAC_S 23 + +/* RTCIO_TOUCH_PAD14_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD14_START (BIT(22)) +#define RTCIO_TOUCH_PAD14_START_M (RTCIO_TOUCH_PAD14_START_V << RTCIO_TOUCH_PAD14_START_S) +#define RTCIO_TOUCH_PAD14_START_V 0x00000001 +#define RTCIO_TOUCH_PAD14_START_S 22 + +/* RTCIO_TOUCH_PAD14_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD14_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD14_TIE_OPT_M (RTCIO_TOUCH_PAD14_TIE_OPT_V << RTCIO_TOUCH_PAD14_TIE_OPT_S) +#define RTCIO_TOUCH_PAD14_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD14_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD14_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD14_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD14_XPD_M (RTCIO_TOUCH_PAD14_XPD_V << RTCIO_TOUCH_PAD14_XPD_S) +#define RTCIO_TOUCH_PAD14_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD14_XPD_S 20 + +/* RTCIO_TOUCH_PAD14_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD14_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD14_MUX_SEL_M (RTCIO_TOUCH_PAD14_MUX_SEL_V << RTCIO_TOUCH_PAD14_MUX_SEL_S) +#define RTCIO_TOUCH_PAD14_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD14_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD14_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD14_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD14_FUN_SEL_M (RTCIO_TOUCH_PAD14_FUN_SEL_V << RTCIO_TOUCH_PAD14_FUN_SEL_S) +#define RTCIO_TOUCH_PAD14_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD14_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD14_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD14_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD14_SLP_SEL_M (RTCIO_TOUCH_PAD14_SLP_SEL_V << RTCIO_TOUCH_PAD14_SLP_SEL_S) +#define RTCIO_TOUCH_PAD14_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD14_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD14_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD14_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD14_SLP_IE_M (RTCIO_TOUCH_PAD14_SLP_IE_V << RTCIO_TOUCH_PAD14_SLP_IE_S) +#define RTCIO_TOUCH_PAD14_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD14_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD14_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD14_SLP_OE_M (RTCIO_TOUCH_PAD14_SLP_OE_V << RTCIO_TOUCH_PAD14_SLP_OE_S) +#define RTCIO_TOUCH_PAD14_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD14_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD14_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD14_FUN_IE_M (RTCIO_TOUCH_PAD14_FUN_IE_V << RTCIO_TOUCH_PAD14_FUN_IE_S) +#define RTCIO_TOUCH_PAD14_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_FUN_IE_S 13 + +/* RTCIO_XTAL_32P_PAD_REG register + * 32KHz crystal P-pad configuration register + */ + +#define RTCIO_XTAL_32P_PAD_REG (DR_REG_RTCIO_BASE + 0xc0) + +/* RTCIO_X32P_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_X32P_DRV 0x00000003 +#define RTCIO_X32P_DRV_M (RTCIO_X32P_DRV_V << RTCIO_X32P_DRV_S) +#define RTCIO_X32P_DRV_V 0x00000003 +#define RTCIO_X32P_DRV_S 29 + +/* RTCIO_X32P_RDE : R/W; bitpos: [28]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_X32P_RDE (BIT(28)) +#define RTCIO_X32P_RDE_M (RTCIO_X32P_RDE_V << RTCIO_X32P_RDE_S) +#define RTCIO_X32P_RDE_V 0x00000001 +#define RTCIO_X32P_RDE_S 28 + +/* RTCIO_X32P_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_X32P_RUE (BIT(27)) +#define RTCIO_X32P_RUE_M (RTCIO_X32P_RUE_V << RTCIO_X32P_RUE_S) +#define RTCIO_X32P_RUE_V 0x00000001 +#define RTCIO_X32P_RUE_S 27 + +/* RTCIO_X32P_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO,0: use digital GPIO + */ + +#define RTCIO_X32P_MUX_SEL (BIT(19)) +#define RTCIO_X32P_MUX_SEL_M (RTCIO_X32P_MUX_SEL_V << RTCIO_X32P_MUX_SEL_S) +#define RTCIO_X32P_MUX_SEL_V 0x00000001 +#define RTCIO_X32P_MUX_SEL_S 19 + +/* RTCIO_X32P_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_X32P_FUN_SEL 0x00000003 +#define RTCIO_X32P_FUN_SEL_M (RTCIO_X32P_FUN_SEL_V << RTCIO_X32P_FUN_SEL_S) +#define RTCIO_X32P_FUN_SEL_V 0x00000003 +#define RTCIO_X32P_FUN_SEL_S 17 + +/* RTCIO_X32P_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_X32P_SLP_SEL (BIT(16)) +#define RTCIO_X32P_SLP_SEL_M (RTCIO_X32P_SLP_SEL_V << RTCIO_X32P_SLP_SEL_S) +#define RTCIO_X32P_SLP_SEL_V 0x00000001 +#define RTCIO_X32P_SLP_SEL_S 16 + +/* RTCIO_X32P_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_X32P_SLP_IE (BIT(15)) +#define RTCIO_X32P_SLP_IE_M (RTCIO_X32P_SLP_IE_V << RTCIO_X32P_SLP_IE_S) +#define RTCIO_X32P_SLP_IE_V 0x00000001 +#define RTCIO_X32P_SLP_IE_S 15 + +/* RTCIO_X32P_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_X32P_SLP_OE (BIT(14)) +#define RTCIO_X32P_SLP_OE_M (RTCIO_X32P_SLP_OE_V << RTCIO_X32P_SLP_OE_S) +#define RTCIO_X32P_SLP_OE_V 0x00000001 +#define RTCIO_X32P_SLP_OE_S 14 + +/* RTCIO_X32P_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_X32P_FUN_IE (BIT(13)) +#define RTCIO_X32P_FUN_IE_M (RTCIO_X32P_FUN_IE_V << RTCIO_X32P_FUN_IE_S) +#define RTCIO_X32P_FUN_IE_V 0x00000001 +#define RTCIO_X32P_FUN_IE_S 13 + +/* RTCIO_XTAL_32N_PAD_REG register + * 32KHz crystal N-pad configuration register + */ + +#define RTCIO_XTAL_32N_PAD_REG (DR_REG_RTCIO_BASE + 0xc4) + +/* RTCIO_X32N_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_X32N_DRV 0x00000003 +#define RTCIO_X32N_DRV_M (RTCIO_X32N_DRV_V << RTCIO_X32N_DRV_S) +#define RTCIO_X32N_DRV_V 0x00000003 +#define RTCIO_X32N_DRV_S 29 + +/* RTCIO_X32N_RDE : R/W; bitpos: [28]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_X32N_RDE (BIT(28)) +#define RTCIO_X32N_RDE_M (RTCIO_X32N_RDE_V << RTCIO_X32N_RDE_S) +#define RTCIO_X32N_RDE_V 0x00000001 +#define RTCIO_X32N_RDE_S 28 + +/* RTCIO_X32N_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_X32N_RUE (BIT(27)) +#define RTCIO_X32N_RUE_M (RTCIO_X32N_RUE_V << RTCIO_X32N_RUE_S) +#define RTCIO_X32N_RUE_V 0x00000001 +#define RTCIO_X32N_RUE_S 27 + +/* RTCIO_X32N_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO,0: use digital GPIO + */ + +#define RTCIO_X32N_MUX_SEL (BIT(19)) +#define RTCIO_X32N_MUX_SEL_M (RTCIO_X32N_MUX_SEL_V << RTCIO_X32N_MUX_SEL_S) +#define RTCIO_X32N_MUX_SEL_V 0x00000001 +#define RTCIO_X32N_MUX_SEL_S 19 + +/* RTCIO_X32N_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_X32N_FUN_SEL 0x00000003 +#define RTCIO_X32N_FUN_SEL_M (RTCIO_X32N_FUN_SEL_V << RTCIO_X32N_FUN_SEL_S) +#define RTCIO_X32N_FUN_SEL_V 0x00000003 +#define RTCIO_X32N_FUN_SEL_S 17 + +/* RTCIO_X32N_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_X32N_SLP_SEL (BIT(16)) +#define RTCIO_X32N_SLP_SEL_M (RTCIO_X32N_SLP_SEL_V << RTCIO_X32N_SLP_SEL_S) +#define RTCIO_X32N_SLP_SEL_V 0x00000001 +#define RTCIO_X32N_SLP_SEL_S 16 + +/* RTCIO_X32N_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_X32N_SLP_IE (BIT(15)) +#define RTCIO_X32N_SLP_IE_M (RTCIO_X32N_SLP_IE_V << RTCIO_X32N_SLP_IE_S) +#define RTCIO_X32N_SLP_IE_V 0x00000001 +#define RTCIO_X32N_SLP_IE_S 15 + +/* RTCIO_X32N_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_X32N_SLP_OE (BIT(14)) +#define RTCIO_X32N_SLP_OE_M (RTCIO_X32N_SLP_OE_V << RTCIO_X32N_SLP_OE_S) +#define RTCIO_X32N_SLP_OE_V 0x00000001 +#define RTCIO_X32N_SLP_OE_S 14 + +/* RTCIO_X32N_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_X32N_FUN_IE (BIT(13)) +#define RTCIO_X32N_FUN_IE_M (RTCIO_X32N_FUN_IE_V << RTCIO_X32N_FUN_IE_S) +#define RTCIO_X32N_FUN_IE_V 0x00000001 +#define RTCIO_X32N_FUN_IE_S 13 + +/* RTCIO_PAD_DAC1_REG register + * DAC1 configuration register + */ + +#define RTCIO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0xc8) + +/* RTCIO_PDAC1_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_PDAC1_DRV 0x00000003 +#define RTCIO_PDAC1_DRV_M (RTCIO_PDAC1_DRV_V << RTCIO_PDAC1_DRV_S) +#define RTCIO_PDAC1_DRV_V 0x00000003 +#define RTCIO_PDAC1_DRV_S 29 + +/* RTCIO_PDAC1_RDE : R/W; bitpos: [28]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_PDAC1_RDE (BIT(28)) +#define RTCIO_PDAC1_RDE_M (RTCIO_PDAC1_RDE_V << RTCIO_PDAC1_RDE_S) +#define RTCIO_PDAC1_RDE_V 0x00000001 +#define RTCIO_PDAC1_RDE_S 28 + +/* RTCIO_PDAC1_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_PDAC1_RUE (BIT(27)) +#define RTCIO_PDAC1_RUE_M (RTCIO_PDAC1_RUE_V << RTCIO_PDAC1_RUE_S) +#define RTCIO_PDAC1_RUE_V 0x00000001 +#define RTCIO_PDAC1_RUE_S 27 + +/* RTCIO_PDAC1_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_PDAC1_MUX_SEL (BIT(19)) +#define RTCIO_PDAC1_MUX_SEL_M (RTCIO_PDAC1_MUX_SEL_V << RTCIO_PDAC1_MUX_SEL_S) +#define RTCIO_PDAC1_MUX_SEL_V 0x00000001 +#define RTCIO_PDAC1_MUX_SEL_S 19 + +/* RTCIO_PDAC1_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * DAC_1 function selection. + */ + +#define RTCIO_PDAC1_FUN_SEL 0x00000003 +#define RTCIO_PDAC1_FUN_SEL_M (RTCIO_PDAC1_FUN_SEL_V << RTCIO_PDAC1_FUN_SEL_S) +#define RTCIO_PDAC1_FUN_SEL_V 0x00000003 +#define RTCIO_PDAC1_FUN_SEL_S 17 + +/* RTCIO_PDAC1_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_PDAC1_SLP_SEL (BIT(16)) +#define RTCIO_PDAC1_SLP_SEL_M (RTCIO_PDAC1_SLP_SEL_V << RTCIO_PDAC1_SLP_SEL_S) +#define RTCIO_PDAC1_SLP_SEL_V 0x00000001 +#define RTCIO_PDAC1_SLP_SEL_S 16 + +/* RTCIO_PDAC1_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_PDAC1_SLP_IE (BIT(15)) +#define RTCIO_PDAC1_SLP_IE_M (RTCIO_PDAC1_SLP_IE_V << RTCIO_PDAC1_SLP_IE_S) +#define RTCIO_PDAC1_SLP_IE_V 0x00000001 +#define RTCIO_PDAC1_SLP_IE_S 15 + +/* RTCIO_PDAC1_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_PDAC1_SLP_OE (BIT(14)) +#define RTCIO_PDAC1_SLP_OE_M (RTCIO_PDAC1_SLP_OE_V << RTCIO_PDAC1_SLP_OE_S) +#define RTCIO_PDAC1_SLP_OE_V 0x00000001 +#define RTCIO_PDAC1_SLP_OE_S 14 + +/* RTCIO_PDAC1_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_PDAC1_FUN_IE (BIT(13)) +#define RTCIO_PDAC1_FUN_IE_M (RTCIO_PDAC1_FUN_IE_V << RTCIO_PDAC1_FUN_IE_S) +#define RTCIO_PDAC1_FUN_IE_V 0x00000001 +#define RTCIO_PDAC1_FUN_IE_S 13 + +/* RTCIO_PDAC1_DAC_XPD_FORCE : R/W; bitpos: [12]; default: 0; + * 1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output; 0: use SAR ADC FSM to + * control DAC_1 output. + */ + +#define RTCIO_PDAC1_DAC_XPD_FORCE (BIT(12)) +#define RTCIO_PDAC1_DAC_XPD_FORCE_M (RTCIO_PDAC1_DAC_XPD_FORCE_V << RTCIO_PDAC1_DAC_XPD_FORCE_S) +#define RTCIO_PDAC1_DAC_XPD_FORCE_V 0x00000001 +#define RTCIO_PDAC1_DAC_XPD_FORCE_S 12 + +/* RTCIO_PDAC1_XPD_DAC : R/W; bitpos: [11]; default: 0; + * When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output; 0: + * disable DAC_1 output. + */ + +#define RTCIO_PDAC1_XPD_DAC (BIT(11)) +#define RTCIO_PDAC1_XPD_DAC_M (RTCIO_PDAC1_XPD_DAC_V << RTCIO_PDAC1_XPD_DAC_S) +#define RTCIO_PDAC1_XPD_DAC_V 0x00000001 +#define RTCIO_PDAC1_XPD_DAC_S 11 + +/* RTCIO_PDAC1_DAC : R/W; bitpos: [10:3]; default: 0; + * Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. + */ + +#define RTCIO_PDAC1_DAC 0x000000FF +#define RTCIO_PDAC1_DAC_M (RTCIO_PDAC1_DAC_V << RTCIO_PDAC1_DAC_S) +#define RTCIO_PDAC1_DAC_V 0x000000FF +#define RTCIO_PDAC1_DAC_S 3 + +/* RTCIO_PAD_DAC2_REG register + * DAC2 configuration register + */ + +#define RTCIO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0xcc) + +/* RTCIO_PDAC2_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_PDAC2_DRV 0x00000003 +#define RTCIO_PDAC2_DRV_M (RTCIO_PDAC2_DRV_V << RTCIO_PDAC2_DRV_S) +#define RTCIO_PDAC2_DRV_V 0x00000003 +#define RTCIO_PDAC2_DRV_S 29 + +/* RTCIO_PDAC2_RDE : R/W; bitpos: [28]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_PDAC2_RDE (BIT(28)) +#define RTCIO_PDAC2_RDE_M (RTCIO_PDAC2_RDE_V << RTCIO_PDAC2_RDE_S) +#define RTCIO_PDAC2_RDE_V 0x00000001 +#define RTCIO_PDAC2_RDE_S 28 + +/* RTCIO_PDAC2_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_PDAC2_RUE (BIT(27)) +#define RTCIO_PDAC2_RUE_M (RTCIO_PDAC2_RUE_V << RTCIO_PDAC2_RUE_S) +#define RTCIO_PDAC2_RUE_V 0x00000001 +#define RTCIO_PDAC2_RUE_S 27 + +/* RTCIO_PDAC2_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_PDAC2_MUX_SEL (BIT(19)) +#define RTCIO_PDAC2_MUX_SEL_M (RTCIO_PDAC2_MUX_SEL_V << RTCIO_PDAC2_MUX_SEL_S) +#define RTCIO_PDAC2_MUX_SEL_V 0x00000001 +#define RTCIO_PDAC2_MUX_SEL_S 19 + +/* RTCIO_PDAC2_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * DAC_2 function selection. + */ + +#define RTCIO_PDAC2_FUN_SEL 0x00000003 +#define RTCIO_PDAC2_FUN_SEL_M (RTCIO_PDAC2_FUN_SEL_V << RTCIO_PDAC2_FUN_SEL_S) +#define RTCIO_PDAC2_FUN_SEL_V 0x00000003 +#define RTCIO_PDAC2_FUN_SEL_S 17 + +/* RTCIO_PDAC2_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_PDAC2_SLP_SEL (BIT(16)) +#define RTCIO_PDAC2_SLP_SEL_M (RTCIO_PDAC2_SLP_SEL_V << RTCIO_PDAC2_SLP_SEL_S) +#define RTCIO_PDAC2_SLP_SEL_V 0x00000001 +#define RTCIO_PDAC2_SLP_SEL_S 16 + +/* RTCIO_PDAC2_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_PDAC2_SLP_IE (BIT(15)) +#define RTCIO_PDAC2_SLP_IE_M (RTCIO_PDAC2_SLP_IE_V << RTCIO_PDAC2_SLP_IE_S) +#define RTCIO_PDAC2_SLP_IE_V 0x00000001 +#define RTCIO_PDAC2_SLP_IE_S 15 + +/* RTCIO_PDAC2_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_PDAC2_SLP_OE (BIT(14)) +#define RTCIO_PDAC2_SLP_OE_M (RTCIO_PDAC2_SLP_OE_V << RTCIO_PDAC2_SLP_OE_S) +#define RTCIO_PDAC2_SLP_OE_V 0x00000001 +#define RTCIO_PDAC2_SLP_OE_S 14 + +/* RTCIO_PDAC2_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_PDAC2_FUN_IE (BIT(13)) +#define RTCIO_PDAC2_FUN_IE_M (RTCIO_PDAC2_FUN_IE_V << RTCIO_PDAC2_FUN_IE_S) +#define RTCIO_PDAC2_FUN_IE_V 0x00000001 +#define RTCIO_PDAC2_FUN_IE_S 13 + +/* RTCIO_PDAC2_DAC_XPD_FORCE : R/W; bitpos: [12]; default: 0; + * 1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output; 0: use SAR ADC FSM to + * control DAC_2 output. + */ + +#define RTCIO_PDAC2_DAC_XPD_FORCE (BIT(12)) +#define RTCIO_PDAC2_DAC_XPD_FORCE_M (RTCIO_PDAC2_DAC_XPD_FORCE_V << RTCIO_PDAC2_DAC_XPD_FORCE_S) +#define RTCIO_PDAC2_DAC_XPD_FORCE_V 0x00000001 +#define RTCIO_PDAC2_DAC_XPD_FORCE_S 12 + +/* RTCIO_PDAC2_XPD_DAC : R/W; bitpos: [11]; default: 0; + * When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output; 0: + * disable DAC_2 output. + */ + +#define RTCIO_PDAC2_XPD_DAC (BIT(11)) +#define RTCIO_PDAC2_XPD_DAC_M (RTCIO_PDAC2_XPD_DAC_V << RTCIO_PDAC2_XPD_DAC_S) +#define RTCIO_PDAC2_XPD_DAC_V 0x00000001 +#define RTCIO_PDAC2_XPD_DAC_S 11 + +/* RTCIO_PDAC2_DAC : R/W; bitpos: [10:3]; default: 0; + * Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. + */ + +#define RTCIO_PDAC2_DAC 0x000000FF +#define RTCIO_PDAC2_DAC_M (RTCIO_PDAC2_DAC_V << RTCIO_PDAC2_DAC_S) +#define RTCIO_PDAC2_DAC_V 0x000000FF +#define RTCIO_PDAC2_DAC_S 3 + +/* RTCIO_RTC_PAD19_REG register + * Touch pad 19 configuration register + */ + +#define RTCIO_RTC_PAD19_REG (DR_REG_RTCIO_BASE + 0xd0) + +/* RTCIO_RTC_PAD19_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_RTC_PAD19_DRV 0x00000003 +#define RTCIO_RTC_PAD19_DRV_M (RTCIO_RTC_PAD19_DRV_V << RTCIO_RTC_PAD19_DRV_S) +#define RTCIO_RTC_PAD19_DRV_V 0x00000003 +#define RTCIO_RTC_PAD19_DRV_S 29 + +/* RTCIO_RTC_PAD19_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_RTC_PAD19_RDE (BIT(28)) +#define RTCIO_RTC_PAD19_RDE_M (RTCIO_RTC_PAD19_RDE_V << RTCIO_RTC_PAD19_RDE_S) +#define RTCIO_RTC_PAD19_RDE_V 0x00000001 +#define RTCIO_RTC_PAD19_RDE_S 28 + +/* RTCIO_RTC_PAD19_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_RTC_PAD19_RUE (BIT(27)) +#define RTCIO_RTC_PAD19_RUE_M (RTCIO_RTC_PAD19_RUE_V << RTCIO_RTC_PAD19_RUE_S) +#define RTCIO_RTC_PAD19_RUE_V 0x00000001 +#define RTCIO_RTC_PAD19_RUE_S 27 + +/* RTCIO_RTC_PAD19_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_RTC_PAD19_MUX_SEL (BIT(19)) +#define RTCIO_RTC_PAD19_MUX_SEL_M (RTCIO_RTC_PAD19_MUX_SEL_V << RTCIO_RTC_PAD19_MUX_SEL_S) +#define RTCIO_RTC_PAD19_MUX_SEL_V 0x00000001 +#define RTCIO_RTC_PAD19_MUX_SEL_S 19 + +/* RTCIO_RTC_PAD19_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_RTC_PAD19_FUN_SEL 0x00000003 +#define RTCIO_RTC_PAD19_FUN_SEL_M (RTCIO_RTC_PAD19_FUN_SEL_V << RTCIO_RTC_PAD19_FUN_SEL_S) +#define RTCIO_RTC_PAD19_FUN_SEL_V 0x00000003 +#define RTCIO_RTC_PAD19_FUN_SEL_S 17 + +/* RTCIO_RTC_PAD19_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_RTC_PAD19_SLP_SEL (BIT(16)) +#define RTCIO_RTC_PAD19_SLP_SEL_M (RTCIO_RTC_PAD19_SLP_SEL_V << RTCIO_RTC_PAD19_SLP_SEL_S) +#define RTCIO_RTC_PAD19_SLP_SEL_V 0x00000001 +#define RTCIO_RTC_PAD19_SLP_SEL_S 16 + +/* RTCIO_RTC_PAD19_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_RTC_PAD19_SLP_IE (BIT(15)) +#define RTCIO_RTC_PAD19_SLP_IE_M (RTCIO_RTC_PAD19_SLP_IE_V << RTCIO_RTC_PAD19_SLP_IE_S) +#define RTCIO_RTC_PAD19_SLP_IE_V 0x00000001 +#define RTCIO_RTC_PAD19_SLP_IE_S 15 + +/* RTCIO_RTC_PAD19_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_RTC_PAD19_SLP_OE (BIT(14)) +#define RTCIO_RTC_PAD19_SLP_OE_M (RTCIO_RTC_PAD19_SLP_OE_V << RTCIO_RTC_PAD19_SLP_OE_S) +#define RTCIO_RTC_PAD19_SLP_OE_V 0x00000001 +#define RTCIO_RTC_PAD19_SLP_OE_S 14 + +/* RTCIO_RTC_PAD19_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_RTC_PAD19_FUN_IE (BIT(13)) +#define RTCIO_RTC_PAD19_FUN_IE_M (RTCIO_RTC_PAD19_FUN_IE_V << RTCIO_RTC_PAD19_FUN_IE_S) +#define RTCIO_RTC_PAD19_FUN_IE_V 0x00000001 +#define RTCIO_RTC_PAD19_FUN_IE_S 13 + +/* RTCIO_RTC_PAD20_REG register + * Touch pad 20 configuration register + */ + +#define RTCIO_RTC_PAD20_REG (DR_REG_RTCIO_BASE + 0xd4) + +/* RTCIO_RTC_PAD20_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_RTC_PAD20_DRV 0x00000003 +#define RTCIO_RTC_PAD20_DRV_M (RTCIO_RTC_PAD20_DRV_V << RTCIO_RTC_PAD20_DRV_S) +#define RTCIO_RTC_PAD20_DRV_V 0x00000003 +#define RTCIO_RTC_PAD20_DRV_S 29 + +/* RTCIO_RTC_PAD20_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_RTC_PAD20_RDE (BIT(28)) +#define RTCIO_RTC_PAD20_RDE_M (RTCIO_RTC_PAD20_RDE_V << RTCIO_RTC_PAD20_RDE_S) +#define RTCIO_RTC_PAD20_RDE_V 0x00000001 +#define RTCIO_RTC_PAD20_RDE_S 28 + +/* RTCIO_RTC_PAD20_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_RTC_PAD20_RUE (BIT(27)) +#define RTCIO_RTC_PAD20_RUE_M (RTCIO_RTC_PAD20_RUE_V << RTCIO_RTC_PAD20_RUE_S) +#define RTCIO_RTC_PAD20_RUE_V 0x00000001 +#define RTCIO_RTC_PAD20_RUE_S 27 + +/* RTCIO_RTC_PAD20_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_RTC_PAD20_MUX_SEL (BIT(19)) +#define RTCIO_RTC_PAD20_MUX_SEL_M (RTCIO_RTC_PAD20_MUX_SEL_V << RTCIO_RTC_PAD20_MUX_SEL_S) +#define RTCIO_RTC_PAD20_MUX_SEL_V 0x00000001 +#define RTCIO_RTC_PAD20_MUX_SEL_S 19 + +/* RTCIO_RTC_PAD20_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_RTC_PAD20_FUN_SEL 0x00000003 +#define RTCIO_RTC_PAD20_FUN_SEL_M (RTCIO_RTC_PAD20_FUN_SEL_V << RTCIO_RTC_PAD20_FUN_SEL_S) +#define RTCIO_RTC_PAD20_FUN_SEL_V 0x00000003 +#define RTCIO_RTC_PAD20_FUN_SEL_S 17 + +/* RTCIO_RTC_PAD20_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_RTC_PAD20_SLP_SEL (BIT(16)) +#define RTCIO_RTC_PAD20_SLP_SEL_M (RTCIO_RTC_PAD20_SLP_SEL_V << RTCIO_RTC_PAD20_SLP_SEL_S) +#define RTCIO_RTC_PAD20_SLP_SEL_V 0x00000001 +#define RTCIO_RTC_PAD20_SLP_SEL_S 16 + +/* RTCIO_RTC_PAD20_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_RTC_PAD20_SLP_IE (BIT(15)) +#define RTCIO_RTC_PAD20_SLP_IE_M (RTCIO_RTC_PAD20_SLP_IE_V << RTCIO_RTC_PAD20_SLP_IE_S) +#define RTCIO_RTC_PAD20_SLP_IE_V 0x00000001 +#define RTCIO_RTC_PAD20_SLP_IE_S 15 + +/* RTCIO_RTC_PAD20_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_RTC_PAD20_SLP_OE (BIT(14)) +#define RTCIO_RTC_PAD20_SLP_OE_M (RTCIO_RTC_PAD20_SLP_OE_V << RTCIO_RTC_PAD20_SLP_OE_S) +#define RTCIO_RTC_PAD20_SLP_OE_V 0x00000001 +#define RTCIO_RTC_PAD20_SLP_OE_S 14 + +/* RTCIO_RTC_PAD20_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_RTC_PAD20_FUN_IE (BIT(13)) +#define RTCIO_RTC_PAD20_FUN_IE_M (RTCIO_RTC_PAD20_FUN_IE_V << RTCIO_RTC_PAD20_FUN_IE_S) +#define RTCIO_RTC_PAD20_FUN_IE_V 0x00000001 +#define RTCIO_RTC_PAD20_FUN_IE_S 13 + +/* RTCIO_RTC_PAD21_REG register + * Touch pad 21 configuration register + */ + +#define RTCIO_RTC_PAD21_REG (DR_REG_RTCIO_BASE + 0xd8) + +/* RTCIO_RTC_PAD21_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_RTC_PAD21_DRV 0x00000003 +#define RTCIO_RTC_PAD21_DRV_M (RTCIO_RTC_PAD21_DRV_V << RTCIO_RTC_PAD21_DRV_S) +#define RTCIO_RTC_PAD21_DRV_V 0x00000003 +#define RTCIO_RTC_PAD21_DRV_S 29 + +/* RTCIO_RTC_PAD21_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_RTC_PAD21_RDE (BIT(28)) +#define RTCIO_RTC_PAD21_RDE_M (RTCIO_RTC_PAD21_RDE_V << RTCIO_RTC_PAD21_RDE_S) +#define RTCIO_RTC_PAD21_RDE_V 0x00000001 +#define RTCIO_RTC_PAD21_RDE_S 28 + +/* RTCIO_RTC_PAD21_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_RTC_PAD21_RUE (BIT(27)) +#define RTCIO_RTC_PAD21_RUE_M (RTCIO_RTC_PAD21_RUE_V << RTCIO_RTC_PAD21_RUE_S) +#define RTCIO_RTC_PAD21_RUE_V 0x00000001 +#define RTCIO_RTC_PAD21_RUE_S 27 + +/* RTCIO_RTC_PAD21_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_RTC_PAD21_MUX_SEL (BIT(19)) +#define RTCIO_RTC_PAD21_MUX_SEL_M (RTCIO_RTC_PAD21_MUX_SEL_V << RTCIO_RTC_PAD21_MUX_SEL_S) +#define RTCIO_RTC_PAD21_MUX_SEL_V 0x00000001 +#define RTCIO_RTC_PAD21_MUX_SEL_S 19 + +/* RTCIO_RTC_PAD21_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_RTC_PAD21_FUN_SEL 0x00000003 +#define RTCIO_RTC_PAD21_FUN_SEL_M (RTCIO_RTC_PAD21_FUN_SEL_V << RTCIO_RTC_PAD21_FUN_SEL_S) +#define RTCIO_RTC_PAD21_FUN_SEL_V 0x00000003 +#define RTCIO_RTC_PAD21_FUN_SEL_S 17 + +/* RTCIO_RTC_PAD21_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_RTC_PAD21_SLP_SEL (BIT(16)) +#define RTCIO_RTC_PAD21_SLP_SEL_M (RTCIO_RTC_PAD21_SLP_SEL_V << RTCIO_RTC_PAD21_SLP_SEL_S) +#define RTCIO_RTC_PAD21_SLP_SEL_V 0x00000001 +#define RTCIO_RTC_PAD21_SLP_SEL_S 16 + +/* RTCIO_RTC_PAD21_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_RTC_PAD21_SLP_IE (BIT(15)) +#define RTCIO_RTC_PAD21_SLP_IE_M (RTCIO_RTC_PAD21_SLP_IE_V << RTCIO_RTC_PAD21_SLP_IE_S) +#define RTCIO_RTC_PAD21_SLP_IE_V 0x00000001 +#define RTCIO_RTC_PAD21_SLP_IE_S 15 + +/* RTCIO_RTC_PAD21_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_RTC_PAD21_SLP_OE (BIT(14)) +#define RTCIO_RTC_PAD21_SLP_OE_M (RTCIO_RTC_PAD21_SLP_OE_V << RTCIO_RTC_PAD21_SLP_OE_S) +#define RTCIO_RTC_PAD21_SLP_OE_V 0x00000001 +#define RTCIO_RTC_PAD21_SLP_OE_S 14 + +/* RTCIO_RTC_PAD21_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_RTC_PAD21_FUN_IE (BIT(13)) +#define RTCIO_RTC_PAD21_FUN_IE_M (RTCIO_RTC_PAD21_FUN_IE_V << RTCIO_RTC_PAD21_FUN_IE_S) +#define RTCIO_RTC_PAD21_FUN_IE_V 0x00000001 +#define RTCIO_RTC_PAD21_FUN_IE_S 13 + +/* RTCIO_EXT_WAKEUP0_REG register + * External wake up configuration register + */ + +#define RTCIO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xdc) + +/* RTCIO_EXT_WAKEUP0_SEL : R/W; bitpos: [31:27]; default: 0; + * GPIO[0-17] can be used to wake up the chip when the chip is in the sleep + * mode. This register prompts the pad source to wake up the chip when the + * latter is indeep/light sleep mode. + * 0: select GPIO0; 1: select GPIO2, etc + */ + +#define RTCIO_EXT_WAKEUP0_SEL 0x0000001F +#define RTCIO_EXT_WAKEUP0_SEL_M (RTCIO_EXT_WAKEUP0_SEL_V << RTCIO_EXT_WAKEUP0_SEL_S) +#define RTCIO_EXT_WAKEUP0_SEL_V 0x0000001F +#define RTCIO_EXT_WAKEUP0_SEL_S 27 + +/* RTCIO_XTL_EXT_CTR_REG register + * Crystal power down enable GPIO source + */ + +#define RTCIO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xe0) + +/* RTCIO_XTL_EXT_CTR_SEL : R/W; bitpos: [31:27]; default: 0; + * Select the external crystal power down enable source to get into sleep + * mode. 0: select GPIO0; 1: select GPIO1, etc. The input value on this pin + * XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal. + */ + +#define RTCIO_XTL_EXT_CTR_SEL 0x0000001F +#define RTCIO_XTL_EXT_CTR_SEL_M (RTCIO_XTL_EXT_CTR_SEL_V << RTCIO_XTL_EXT_CTR_SEL_S) +#define RTCIO_XTL_EXT_CTR_SEL_V 0x0000001F +#define RTCIO_XTL_EXT_CTR_SEL_S 27 + +/* RTCIO_SAR_I2C_IO_REG register + * RTC I²C pad selection + */ + +#define RTCIO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xe4) + +/* RTCIO_SAR_I2C_SDA_SEL : R/W; bitpos: [31:30]; default: 0; + * Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1; 1: + * use TOUCH PAD3. + */ + +#define RTCIO_SAR_I2C_SDA_SEL 0x00000003 +#define RTCIO_SAR_I2C_SDA_SEL_M (RTCIO_SAR_I2C_SDA_SEL_V << RTCIO_SAR_I2C_SDA_SEL_S) +#define RTCIO_SAR_I2C_SDA_SEL_V 0x00000003 +#define RTCIO_SAR_I2C_SDA_SEL_S 30 + +/* RTCIO_SAR_I2C_SCL_SEL : R/W; bitpos: [29:28]; default: 0; + * Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0; 1: + * use TOUCH PAD2. + */ + +#define RTCIO_SAR_I2C_SCL_SEL 0x00000003 +#define RTCIO_SAR_I2C_SCL_SEL_M (RTCIO_SAR_I2C_SCL_SEL_V << RTCIO_SAR_I2C_SCL_SEL_S) +#define RTCIO_SAR_I2C_SCL_SEL_V 0x00000003 +#define RTCIO_SAR_I2C_SCL_SEL_S 28 + +/* RTCIO_SAR_DEBUG_BIT_SEL : R/W; bitpos: [27:23]; default: 0; */ + +#define RTCIO_SAR_DEBUG_BIT_SEL 0x0000001F +#define RTCIO_SAR_DEBUG_BIT_SEL_M (RTCIO_SAR_DEBUG_BIT_SEL_V << RTCIO_SAR_DEBUG_BIT_SEL_S) +#define RTCIO_SAR_DEBUG_BIT_SEL_V 0x0000001F +#define RTCIO_SAR_DEBUG_BIT_SEL_S 23 + +/* RTCIO_RTC_IO_TOUCH_CTRL_REG register + * Touch Control register + */ + +#define RTCIO_RTC_IO_TOUCH_CTRL_REG (DR_REG_RTCIO_BASE + 0xe8) + +/* RTCIO_IO_TOUCH_BUFMODE : R/W; bitpos: [4]; default: 0; */ + +#define RTCIO_IO_TOUCH_BUFMODE (BIT(4)) +#define RTCIO_IO_TOUCH_BUFMODE_M (RTCIO_IO_TOUCH_BUFMODE_V << RTCIO_IO_TOUCH_BUFMODE_S) +#define RTCIO_IO_TOUCH_BUFMODE_V 0x00000001 +#define RTCIO_IO_TOUCH_BUFMODE_S 4 + +/* RTCIO_IO_TOUCH_BUFSEL : R/W; bitpos: [3:0]; default: 0; */ + +#define RTCIO_IO_TOUCH_BUFSEL 0x0000000F +#define RTCIO_IO_TOUCH_BUFSEL_M (RTCIO_IO_TOUCH_BUFSEL_V << RTCIO_IO_TOUCH_BUFSEL_S) +#define RTCIO_IO_TOUCH_BUFSEL_V 0x0000000F +#define RTCIO_IO_TOUCH_BUFSEL_S 0 + +/* RTCIO_RTC_IO_DATE_REG register + * Version control register + */ + +#define RTCIO_RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x1fc) + +/* RTCIO_IO_DATE : R/W; bitpos: [27:0]; default: 26227056; + * Version control register + */ + +#define RTCIO_IO_DATE 0x0FFFFFFF +#define RTCIO_IO_DATE_M (RTCIO_IO_DATE_V << RTCIO_IO_DATE_S) +#define RTCIO_IO_DATE_V 0x0FFFFFFF +#define RTCIO_IO_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCIO_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h new file mode 100644 index 00000000000..7b7f7b37c56 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h @@ -0,0 +1,4419 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTC_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DPORT_CPUPERIOD_SEL_80 0 +#define DPORT_CPUPERIOD_SEL_160 1 +#define DPORT_CPUPERIOD_SEL_240 2 + +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG + +/* RTC_CNTL_OPTIONS0_REG register + * set xtal and pll power and sw reset register + */ + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) + +/* RTC_CNTL_SW_SYS_RST : WO; bitpos: [31]; default: 0; + * SW system reset + */ + +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (RTC_CNTL_SW_SYS_RST_V << RTC_CNTL_SW_SYS_RST_S) +#define RTC_CNTL_SW_SYS_RST_V 0x00000001 +#define RTC_CNTL_SW_SYS_RST_S 31 + +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W; bitpos: [30]; default: 0; + * digital core force no reset in deep sleep + */ + +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (RTC_CNTL_DG_WRAP_FORCE_NORST_V << RTC_CNTL_DG_WRAP_FORCE_NORST_S) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 + +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W; bitpos: [29]; default: 0; + * digital wrap force reset in deep sleep + */ + +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (RTC_CNTL_DG_WRAP_FORCE_RST_V << RTC_CNTL_DG_WRAP_FORCE_RST_S) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 + +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W; bitpos: [28]; default: 1; */ + +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (RTC_CNTL_ANALOG_FORCE_NOISO_V << RTC_CNTL_ANALOG_FORCE_NOISO_S) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 + +/* RTC_CNTL_PLL_FORCE_NOISO : R/W; bitpos: [27]; default: 1; */ + +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (RTC_CNTL_PLL_FORCE_NOISO_V << RTC_CNTL_PLL_FORCE_NOISO_S) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 + +/* RTC_CNTL_XTL_FORCE_NOISO : R/W; bitpos: [26]; default: 1; */ + +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (RTC_CNTL_XTL_FORCE_NOISO_V << RTC_CNTL_XTL_FORCE_NOISO_S) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 + +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W; bitpos: [25]; default: 0; */ + +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (RTC_CNTL_ANALOG_FORCE_ISO_V << RTC_CNTL_ANALOG_FORCE_ISO_S) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 + +/* RTC_CNTL_PLL_FORCE_ISO : R/W; bitpos: [24]; default: 0; */ + +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (RTC_CNTL_PLL_FORCE_ISO_V << RTC_CNTL_PLL_FORCE_ISO_S) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 + +/* RTC_CNTL_XTL_FORCE_ISO : R/W; bitpos: [23]; default: 0; */ + +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (RTC_CNTL_XTL_FORCE_ISO_V << RTC_CNTL_XTL_FORCE_ISO_S) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 + +/* RTC_CNTL_XTL_FORCE_PU : R/W; bitpos: [13]; default: 1; + * crystall force power up + */ + +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (RTC_CNTL_XTL_FORCE_PU_V << RTC_CNTL_XTL_FORCE_PU_S) +#define RTC_CNTL_XTL_FORCE_PU_V 0x00000001 +#define RTC_CNTL_XTL_FORCE_PU_S 13 + +/* RTC_CNTL_XTL_FORCE_PD : R/W; bitpos: [12]; default: 0; + * crystall force power down + */ + +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (RTC_CNTL_XTL_FORCE_PD_V << RTC_CNTL_XTL_FORCE_PD_S) +#define RTC_CNTL_XTL_FORCE_PD_V 0x00000001 +#define RTC_CNTL_XTL_FORCE_PD_S 12 + +/* RTC_CNTL_BBPLL_FORCE_PU : R/W; bitpos: [11]; default: 0; + * BB_PLL force power up + */ + +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (RTC_CNTL_BBPLL_FORCE_PU_V << RTC_CNTL_BBPLL_FORCE_PU_S) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x00000001 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 + +/* RTC_CNTL_BBPLL_FORCE_PD : R/W; bitpos: [10]; default: 0; + * BB_PLL force power down + */ + +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (RTC_CNTL_BBPLL_FORCE_PD_V << RTC_CNTL_BBPLL_FORCE_PD_S) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x00000001 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 + +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W; bitpos: [9]; default: 0; + * BB_PLL_I2C force power up + */ + +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (RTC_CNTL_BBPLL_I2C_FORCE_PU_V << RTC_CNTL_BBPLL_I2C_FORCE_PU_S) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x00000001 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 + +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W; bitpos: [8]; default: 0; + * BB_PLL _I2C force power down + */ + +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (RTC_CNTL_BBPLL_I2C_FORCE_PD_V << RTC_CNTL_BBPLL_I2C_FORCE_PD_S) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x00000001 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 + +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W; bitpos: [7]; default: 0; + * BB_I2C force power up + */ + +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (RTC_CNTL_BB_I2C_FORCE_PU_V << RTC_CNTL_BB_I2C_FORCE_PU_S) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x00000001 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 + +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W; bitpos: [6]; default: 0; + * BB_I2C force power down + */ + +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (RTC_CNTL_BB_I2C_FORCE_PD_V << RTC_CNTL_BB_I2C_FORCE_PD_S) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x00000001 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 + +/* RTC_CNTL_SW_PROCPU_RST : WO; bitpos: [5]; default: 0; + * PRO CPU SW reset + */ + +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (RTC_CNTL_SW_PROCPU_RST_V << RTC_CNTL_SW_PROCPU_RST_S) +#define RTC_CNTL_SW_PROCPU_RST_V 0x00000001 +#define RTC_CNTL_SW_PROCPU_RST_S 5 + +/* RTC_CNTL_SW_APPCPU_RST : WO; bitpos: [4]; default: 0; + * APP CPU SW reset + */ + +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (RTC_CNTL_SW_APPCPU_RST_V << RTC_CNTL_SW_APPCPU_RST_S) +#define RTC_CNTL_SW_APPCPU_RST_V 0x00000001 +#define RTC_CNTL_SW_APPCPU_RST_S 4 + +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W; bitpos: [3:2]; default: 0; + * {reg_sw_stall_procpu_c1[5:0] , reg_sw_stall_procpu_c0[1:0]} == 0x86 will + * stall PRO CPU + */ + +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M (RTC_CNTL_SW_STALL_PROCPU_C0_V << RTC_CNTL_SW_STALL_PROCPU_C0_S) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 + +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W; bitpos: [1:0]; default: 0; + * {reg_sw_stall_appcpu_c1[5:0] , reg_sw_stall_appcpu_c0[1:0]} == 0x86 will + * stall APP CPU + */ + +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M (RTC_CNTL_SW_STALL_APPCPU_C0_V << RTC_CNTL_SW_STALL_APPCPU_C0_S) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +/* RTC_CNTL_SLP_TIMER0_REG register + * rtc_sleep_timer0 register + */ + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) + +/* RTC_CNTL_SLP_VAL_LO : R/W; bitpos: [31:0]; default: 0; + * RTC sleep timer low 32 bits + */ + +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M (RTC_CNTL_SLP_VAL_LO_V << RTC_CNTL_SLP_VAL_LO_S) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +/* RTC_CNTL_SLP_TIMER1_REG register + * rtc_sleep_timer1 register + */ + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) + +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO; bitpos: [16]; default: 0; + * timer alarm enable bit + */ + +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (RTC_CNTL_MAIN_TIMER_ALARM_EN_V << RTC_CNTL_MAIN_TIMER_ALARM_EN_S) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 + +/* RTC_CNTL_SLP_VAL_HI : R/W; bitpos: [15:0]; default: 0; + * RTC sleep timer high 16 bits + */ + +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M (RTC_CNTL_SLP_VAL_HI_V << RTC_CNTL_SLP_VAL_HI_S) +#define RTC_CNTL_SLP_VAL_HI_V 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +/* RTC_CNTL_TIME_UPDATE_REG register + * rtc time update register + */ + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) + +/* RTC_CNTL_TIME_UPDATE : WO; bitpos: [31]; default: 0; + * Set 1: to update register with RTC timer + */ + +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (RTC_CNTL_TIME_UPDATE_V << RTC_CNTL_TIME_UPDATE_S) +#define RTC_CNTL_TIME_UPDATE_V 0x00000001 +#define RTC_CNTL_TIME_UPDATE_S 31 + +/* RTC_CNTL_TIMER_SYS_RST : R/W; bitpos: [29]; default: 0; + * enable to record system reset time + */ + +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (RTC_CNTL_TIMER_SYS_RST_V << RTC_CNTL_TIMER_SYS_RST_S) +#define RTC_CNTL_TIMER_SYS_RST_V 0x00000001 +#define RTC_CNTL_TIMER_SYS_RST_S 29 + +/* RTC_CNTL_TIMER_XTL_OFF : R/W; bitpos: [28]; default: 0; + * Enable to record 40M XTAL OFF time + */ + +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (RTC_CNTL_TIMER_XTL_OFF_V << RTC_CNTL_TIMER_XTL_OFF_S) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x00000001 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 + +/* RTC_CNTL_TIMER_SYS_STALL : R/W; bitpos: [27]; default: 0; + * Enable to record system stall time + */ + +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (RTC_CNTL_TIMER_SYS_STALL_V << RTC_CNTL_TIMER_SYS_STALL_S) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x00000001 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +/* RTC_CNTL_TIME_LOW0_REG register + * RTC timer0 low 32 bits + */ + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) + +/* RTC_CNTL_TIMER_VALUE0_LOW : RO; bitpos: [31:0]; default: 0; + * RTC timer low 32 bits + */ + +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M (RTC_CNTL_TIMER_VALUE0_LOW_V << RTC_CNTL_TIMER_VALUE0_LOW_S) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +/* RTC_CNTL_TIME_HIGH0_REG register + * RTC timer0 high16 bits + */ + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) + +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO; bitpos: [15:0]; default: 0; + * RTC timer high 16 bits + */ + +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M (RTC_CNTL_TIMER_VALUE0_HIGH_V << RTC_CNTL_TIMER_VALUE0_HIGH_S) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +/* RTC_CNTL_STATE0_REG register + * configure sleep/reject/wakeup state + */ + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) + +/* RTC_CNTL_SLEEP_EN : R/W; bitpos: [31]; default: 0; + * sleep enable bit + */ + +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (RTC_CNTL_SLEEP_EN_V << RTC_CNTL_SLEEP_EN_S) +#define RTC_CNTL_SLEEP_EN_V 0x00000001 +#define RTC_CNTL_SLEEP_EN_S 31 + +/* RTC_CNTL_SLP_REJECT : R/W; bitpos: [30]; default: 0; + * leep reject bit + */ + +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (RTC_CNTL_SLP_REJECT_V << RTC_CNTL_SLP_REJECT_S) +#define RTC_CNTL_SLP_REJECT_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_S 30 + +/* RTC_CNTL_SLP_WAKEUP : R/W; bitpos: [29]; default: 0; + * leep wakeup bit + */ + +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (RTC_CNTL_SLP_WAKEUP_V << RTC_CNTL_SLP_WAKEUP_S) +#define RTC_CNTL_SLP_WAKEUP_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_S 29 + +/* RTC_CNTL_SDIO_ACTIVE_IND : RO; bitpos: [28]; default: 0; + * SDIO active indication + */ + +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (RTC_CNTL_SDIO_ACTIVE_IND_V << RTC_CNTL_SDIO_ACTIVE_IND_S) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x00000001 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 + +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W; bitpos: [22]; default: 0; + * 1: APB to RTC using bridge 0: APB to RTC using sync + */ + +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (RTC_CNTL_APB2RTC_BRIDGE_SEL_V << RTC_CNTL_APB2RTC_BRIDGE_SEL_S) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x00000001 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 + +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; + *description: clear rtc sleep reject cause + */ + +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 + +/* RTC_CNTL_SW_CPU_INT : WO; bitpos: [0]; default: 0; + * rtc software interrupt to main cpu + */ + +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (RTC_CNTL_SW_CPU_INT_V << RTC_CNTL_SW_CPU_INT_S) +#define RTC_CNTL_SW_CPU_INT_V 0x00000001 +#define RTC_CNTL_SW_CPU_INT_S 0 + +/* RTC_CNTL_TIMER1_REG register + * configure time that wait analog state stable + */ + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) + +/* RTC_CNTL_PLL_BUF_WAIT : R/W; bitpos: [31:24]; default: 40; + * PLL wait cycles in slow_clk_rtc + */ + +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M (RTC_CNTL_PLL_BUF_WAIT_V << RTC_CNTL_PLL_BUF_WAIT_S) +#define RTC_CNTL_PLL_BUF_WAIT_V 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 + +/* RTC_CNTL_XTL_BUF_WAIT : R/W; bitpos: [23:14]; default: 80; + * XTAL wait cycles in slow_clk_rtc + */ + +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M (RTC_CNTL_XTL_BUF_WAIT_V << RTC_CNTL_XTL_BUF_WAIT_S) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 + +/* RTC_CNTL_CK8M_WAIT : R/W; bitpos: [13:6]; default: 16; + * CK8M wait cycles in slow_clk_rtc + */ + +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M (RTC_CNTL_CK8M_WAIT_V << RTC_CNTL_CK8M_WAIT_S) +#define RTC_CNTL_CK8M_WAIT_V 0x000000FF +#define RTC_CNTL_CK8M_WAIT_S 6 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 + +/* RTC_CNTL_CPU_STALL_WAIT : R/W; bitpos: [5:1]; default: 1; + * CPU stall wait cycles in fast_clk_rtc + */ + +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M (RTC_CNTL_CPU_STALL_WAIT_V << RTC_CNTL_CPU_STALL_WAIT_S) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 + +/* RTC_CNTL_CPU_STALL_EN : R/W; bitpos: [0]; default: 1; + * CPU stall enable bit + */ + +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (RTC_CNTL_CPU_STALL_EN_V << RTC_CNTL_CPU_STALL_EN_S) +#define RTC_CNTL_CPU_STALL_EN_V 0x00000001 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +/* RTC_CNTL_TIMER2_REG register + * configure time that wait analog state stable + */ + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) + +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W; bitpos: [31:24]; default: 1; + * minimal cycles in slow_clk_rtc for CK8M in power down state + */ + +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M (RTC_CNTL_MIN_TIME_CK8M_OFF_V << RTC_CNTL_MIN_TIME_CK8M_OFF_S) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 + +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W; bitpos: [23:15]; default: 16; + * wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + * start to work + */ + +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M (RTC_CNTL_ULPCP_TOUCH_START_WAIT_V << RTC_CNTL_ULPCP_TOUCH_START_WAIT_S) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +/* RTC_CNTL_TIMER3_REG register + * configure some wait time for power on + */ + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) + +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 10; */ + +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M (RTC_CNTL_ROM_RAM_POWERUP_TIMER_V << RTC_CNTL_ROM_RAM_POWERUP_TIMER_S) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 + +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W; bitpos: [24:16]; default: 22; */ + +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M (RTC_CNTL_ROM_RAM_WAIT_TIMER_V << RTC_CNTL_ROM_RAM_WAIT_TIMER_S) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 + +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; */ + +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M (RTC_CNTL_WIFI_POWERUP_TIMER_V << RTC_CNTL_WIFI_POWERUP_TIMER_S) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 + +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; */ + +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M (RTC_CNTL_WIFI_WAIT_TIMER_V << RTC_CNTL_WIFI_WAIT_TIMER_S) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +/* RTC_CNTL_TIMER4_REG register + * configure some wait time for power on + */ + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) + +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; */ + +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M (RTC_CNTL_DG_WRAP_POWERUP_TIMER_V << RTC_CNTL_DG_WRAP_POWERUP_TIMER_S) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 + +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; */ + +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M (RTC_CNTL_DG_WRAP_WAIT_TIMER_V << RTC_CNTL_DG_WRAP_WAIT_TIMER_S) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 + +/* RTC_CNTL_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; */ + +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M (RTC_CNTL_POWERUP_TIMER_V << RTC_CNTL_POWERUP_TIMER_S) +#define RTC_CNTL_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_S 9 + +/* RTC_CNTL_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; */ + +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M (RTC_CNTL_WAIT_TIMER_V << RTC_CNTL_WAIT_TIMER_S) +#define RTC_CNTL_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +/* RTC_CNTL_TIMER5_REG register + * Configure minimal sleep cycles register + */ + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) + +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 9; */ + +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M (RTC_CNTL_RTCMEM_POWERUP_TIMER_V << RTC_CNTL_RTCMEM_POWERUP_TIMER_S) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 + +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W; bitpos: [24:16]; default: 20; */ + +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M (RTC_CNTL_RTCMEM_WAIT_TIMER_V << RTC_CNTL_RTCMEM_WAIT_TIMER_S) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 + +/* RTC_CNTL_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 128; + * minimal sleep cycles in slow_clk_rtc + */ + +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M (RTC_CNTL_MIN_SLP_VAL_V << RTC_CNTL_MIN_SLP_VAL_S) +#define RTC_CNTL_MIN_SLP_VAL_V 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +#define RTC_CNTL_MIN_SLP_VAL_MIN 2 + +/* RTC_CNTL_TIMER6_REG register + * Configure minimal sleep cycles register + */ + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) + +/* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; */ + +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M (RTC_CNTL_DG_DCDC_POWERUP_TIMER_V << RTC_CNTL_DG_DCDC_POWERUP_TIMER_S) +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 + +/* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; */ + +#define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M (RTC_CNTL_DG_DCDC_WAIT_TIMER_V << RTC_CNTL_DG_DCDC_WAIT_TIMER_S) +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 + +/* RTC_CNTL_ANA_CONF_REG register + * configure some i2c and plla power + */ + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) + +/* RTC_CNTL_PLL_I2C_PU : R/W; bitpos: [31]; default: 0; + * 1. PLL_I2C power up ,otherwise power down + */ + +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (RTC_CNTL_PLL_I2C_PU_V << RTC_CNTL_PLL_I2C_PU_S) +#define RTC_CNTL_PLL_I2C_PU_V 0x00000001 +#define RTC_CNTL_PLL_I2C_PU_S 31 + +/* RTC_CNTL_CKGEN_I2C_PU : R/W; bitpos: [30]; default: 0; + * 1: CKGEN_I2C power up , otherwise power down + */ + +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (RTC_CNTL_CKGEN_I2C_PU_V << RTC_CNTL_CKGEN_I2C_PU_S) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x00000001 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 + +/* RTC_CNTL_RFRX_PBUS_PU : R/W; bitpos: [28]; default: 0; + * 1: RFRX_PBUS power up , otherwise power down + */ + +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (RTC_CNTL_RFRX_PBUS_PU_V << RTC_CNTL_RFRX_PBUS_PU_S) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x00000001 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 + +/* RTC_CNTL_TXRF_I2C_PU : R/W; bitpos: [27]; default: 0; + * 1: TXRF_I2C power up , otherwise power down + */ + +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (RTC_CNTL_TXRF_I2C_PU_V << RTC_CNTL_TXRF_I2C_PU_S) +#define RTC_CNTL_TXRF_I2C_PU_V 0x00000001 +#define RTC_CNTL_TXRF_I2C_PU_S 27 + +/* RTC_CNTL_PVTMON_PU : R/W; bitpos: [26]; default: 0; + * 1: PVTMON power up , otherwise power down + */ + +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (RTC_CNTL_PVTMON_PU_V << RTC_CNTL_PVTMON_PU_S) +#define RTC_CNTL_PVTMON_PU_V 0x00000001 +#define RTC_CNTL_PVTMON_PU_S 26 + +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W; bitpos: [25]; default: 0; + * start BBPLL calibration during sleep + */ + +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (RTC_CNTL_BBPLL_CAL_SLP_START_V << RTC_CNTL_BBPLL_CAL_SLP_START_S) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x00000001 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 + +/* RTC_CNTL_PLLA_FORCE_PU : R/W; bitpos: [24]; default: 0; + * PLLA force power up + */ + +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (RTC_CNTL_PLLA_FORCE_PU_V << RTC_CNTL_PLLA_FORCE_PU_S) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x00000001 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 + +/* RTC_CNTL_PLLA_FORCE_PD : R/W; bitpos: [23]; default: 1; + * PLLA force power down + */ + +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (RTC_CNTL_PLLA_FORCE_PD_V << RTC_CNTL_PLLA_FORCE_PD_S) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x00000001 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +/* RTC_CNTL_SAR_I2C_FORCE_PU : R/W; bitpos: [22]; default: 0; + * SAR_I2C force power up + */ + +#define RTC_CNTL_SAR_I2C_FORCE_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_FORCE_PU_M (RTC_CNTL_SAR_I2C_FORCE_PU_V << RTC_CNTL_SAR_I2C_FORCE_PU_S) +#define RTC_CNTL_SAR_I2C_FORCE_PU_V 0x00000001 +#define RTC_CNTL_SAR_I2C_FORCE_PU_S 22 + +/* RTC_CNTL_SAR_I2C_FORCE_PD : R/W; bitpos: [21]; default: 1; + * SAR_I2C force power down + */ + +#define RTC_CNTL_SAR_I2C_FORCE_PD (BIT(21)) +#define RTC_CNTL_SAR_I2C_FORCE_PD_M (RTC_CNTL_SAR_I2C_FORCE_PD_V << RTC_CNTL_SAR_I2C_FORCE_PD_S) +#define RTC_CNTL_SAR_I2C_FORCE_PD_V 0x00000001 +#define RTC_CNTL_SAR_I2C_FORCE_PD_S 21 + +/* RTC_CNTL_GLITCH_RST_EN : R/W; bitpos: [20]; default: 0; + * enable glitch reset if system detect glitch + */ + +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (RTC_CNTL_GLITCH_RST_EN_V << RTC_CNTL_GLITCH_RST_EN_S) +#define RTC_CNTL_GLITCH_RST_EN_V 0x00000001 +#define RTC_CNTL_GLITCH_RST_EN_S 20 + +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W; bitpos: [19]; default: 0; + * SLEEP_I2CPOR force pu + */ + +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (RTC_CNTL_I2C_RESET_POR_FORCE_PU_V << RTC_CNTL_I2C_RESET_POR_FORCE_PU_S) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x00000001 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 + +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W; bitpos: [18]; default: 1; + * SLEEP_I2CPOR force pd + */ + +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (RTC_CNTL_I2C_RESET_POR_FORCE_PD_V << RTC_CNTL_I2C_RESET_POR_FORCE_PD_S) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x00000001 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 + +/* RTC_CNTL_RESET_STATE_REG register + * reset cause state register + */ + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) + +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W; bitpos: [13]; default: 1; + * PRO CPU state vector sel + */ + +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V << RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x00000001 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 + +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W; bitpos: [12]; default: 1; + * APP CPU state vector sel + */ + +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V << RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x00000001 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 + +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO; bitpos: [11:6]; default: 0; + * reset cause of APP CPU + */ + +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M (RTC_CNTL_RESET_CAUSE_APPCPU_V << RTC_CNTL_RESET_CAUSE_APPCPU_S) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 + +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO; bitpos: [5:0]; default: 0; + * reset cause of PRO CPU + */ + +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M (RTC_CNTL_RESET_CAUSE_PROCPU_V << RTC_CNTL_RESET_CAUSE_PROCPU_S) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +/* RTC_CNTL_WAKEUP_STATE_REG register + * wakeup enable register + */ + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3c) + +/* RTC_CNTL_WAKEUP_ENA : R/W; bitpos: [31:15]; default: 12; + * wakeup enable bitmap + */ + +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M (RTC_CNTL_WAKEUP_ENA_V << RTC_CNTL_WAKEUP_ENA_S) +#define RTC_CNTL_WAKEUP_ENA_V 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 + +/* RTC_CNTL_INT_ENA_RTC_REG register + * rtc interrupt enable register + */ + +#define RTC_CNTL_INT_ENA_RTC_REG (DR_REG_RTCCNTL_BASE + 0x40) + +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W; bitpos: [19]; default: 0; + * enbale gitch det interrupt + */ + +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (RTC_CNTL_GLITCH_DET_INT_ENA_V << RTC_CNTL_GLITCH_DET_INT_ENA_S) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x00000001 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 + +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [18]; default: 0; + * enable touch timeout interrupt + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V << RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 + +/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W; bitpos: [17]; default: 0; + * enable cocpu trap interrupt + */ + +#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_M (RTC_CNTL_COCPU_TRAP_INT_ENA_V << RTC_CNTL_COCPU_TRAP_INT_ENA_S) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x00000001 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 + +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W; bitpos: [16]; default: 0; + * enable xtal32k_dead interrupt + */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (RTC_CNTL_XTAL32K_DEAD_INT_ENA_V << RTC_CNTL_XTAL32K_DEAD_INT_ENA_S) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x00000001 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 + +/* RTC_CNTL_SWD_INT_ENA : R/W; bitpos: [15]; default: 0; + * enable super watch dog interrupt + */ + +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (RTC_CNTL_SWD_INT_ENA_V << RTC_CNTL_SWD_INT_ENA_S) +#define RTC_CNTL_SWD_INT_ENA_V 0x00000001 +#define RTC_CNTL_SWD_INT_ENA_S 15 + +/* RTC_CNTL_SARADC2_INT_ENA : R/W; bitpos: [14]; default: 0; + * enable saradc2 interrupt + */ + +#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_M (RTC_CNTL_SARADC2_INT_ENA_V << RTC_CNTL_SARADC2_INT_ENA_S) +#define RTC_CNTL_SARADC2_INT_ENA_V 0x00000001 +#define RTC_CNTL_SARADC2_INT_ENA_S 14 + +/* RTC_CNTL_COCPU_INT_ENA : R/W; bitpos: [13]; default: 0; + * enable riscV cocpu interrupt + */ + +#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_M (RTC_CNTL_COCPU_INT_ENA_V << RTC_CNTL_COCPU_INT_ENA_S) +#define RTC_CNTL_COCPU_INT_ENA_V 0x00000001 +#define RTC_CNTL_COCPU_INT_ENA_S 13 + +/* RTC_CNTL_TSENS_INT_ENA : R/W; bitpos: [12]; default: 0; + * enable tsens interrupt + */ + +#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_M (RTC_CNTL_TSENS_INT_ENA_V << RTC_CNTL_TSENS_INT_ENA_S) +#define RTC_CNTL_TSENS_INT_ENA_V 0x00000001 +#define RTC_CNTL_TSENS_INT_ENA_S 12 + +/* RTC_CNTL_SARADC1_INT_ENA : R/W; bitpos: [11]; default: 0; + * enable saradc1 interrupt + */ + +#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_M (RTC_CNTL_SARADC1_INT_ENA_V << RTC_CNTL_SARADC1_INT_ENA_S) +#define RTC_CNTL_SARADC1_INT_ENA_V 0x00000001 +#define RTC_CNTL_SARADC1_INT_ENA_S 11 + +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W; bitpos: [10]; default: 0; + * enable RTC main timer interrupt + */ + +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (RTC_CNTL_MAIN_TIMER_INT_ENA_V << RTC_CNTL_MAIN_TIMER_INT_ENA_S) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W; bitpos: [9]; default: 0; + * enable brown out interrupt + */ + +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (RTC_CNTL_BROWN_OUT_INT_ENA_V << RTC_CNTL_BROWN_OUT_INT_ENA_S) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [8]; default: 0; + * enable touch inactive interrupt + */ + +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V << RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 + +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [7]; default: 0; + * enable touch active interrupt + */ + +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V << RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 + +/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; + * enable touch done interrupt + */ + +#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_M (RTC_CNTL_TOUCH_DONE_INT_ENA_V << RTC_CNTL_TOUCH_DONE_INT_ENA_S) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 + +/* RTC_CNTL_ULP_CP_INT_ENA : R/W; bitpos: [5]; default: 0; + * enable ULP-coprocessor interrupt + */ + +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (RTC_CNTL_ULP_CP_INT_ENA_V << RTC_CNTL_ULP_CP_INT_ENA_S) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x00000001 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 + +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * enable touch scan done interrupt + */ + +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 + +/* RTC_CNTL_WDT_INT_ENA : R/W; bitpos: [3]; default: 0; + * enable RTC WDT interrupt + */ + +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (RTC_CNTL_WDT_INT_ENA_V << RTC_CNTL_WDT_INT_ENA_S) +#define RTC_CNTL_WDT_INT_ENA_V 0x00000001 +#define RTC_CNTL_WDT_INT_ENA_S 3 + +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W; bitpos: [2]; default: 0; + * enable SDIO idle interrupt + */ + +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (RTC_CNTL_SDIO_IDLE_INT_ENA_V << RTC_CNTL_SDIO_IDLE_INT_ENA_S) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x00000001 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 + +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W; bitpos: [1]; default: 0; + * enable sleep reject interrupt + */ + +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (RTC_CNTL_SLP_REJECT_INT_ENA_V << RTC_CNTL_SLP_REJECT_INT_ENA_S) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W; bitpos: [0]; default: 0; + * enable sleep wakeup interrupt + */ + +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_S) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +/* RTC_CNTL_INT_RAW_RTC_REG register + * rtc_interrupt raw register + */ + +#define RTC_CNTL_INT_RAW_RTC_REG (DR_REG_RTCCNTL_BASE + 0x44) + +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO; bitpos: [19]; default: 0; + * glitch_det_interrupt_raw + */ + +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (RTC_CNTL_GLITCH_DET_INT_RAW_V << RTC_CNTL_GLITCH_DET_INT_RAW_S) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x00000001 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 + +/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO; bitpos: [18]; default: 0; + * touch timeout interrupt raw + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V << RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 + +/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO; bitpos: [17]; default: 0; + * cocpu trap interrupt raw + */ + +#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_M (RTC_CNTL_COCPU_TRAP_INT_RAW_V << RTC_CNTL_COCPU_TRAP_INT_RAW_S) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x00000001 +#define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 + +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO; bitpos: [16]; default: 0; + * xtal32k dead detection interrupt raw + */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (RTC_CNTL_XTAL32K_DEAD_INT_RAW_V << RTC_CNTL_XTAL32K_DEAD_INT_RAW_S) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x00000001 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 + +/* RTC_CNTL_SWD_INT_RAW : RO; bitpos: [15]; default: 0; + * super watch dog interrupt raw + */ + +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (RTC_CNTL_SWD_INT_RAW_V << RTC_CNTL_SWD_INT_RAW_S) +#define RTC_CNTL_SWD_INT_RAW_V 0x00000001 +#define RTC_CNTL_SWD_INT_RAW_S 15 + +/* RTC_CNTL_SARADC2_INT_RAW : RO; bitpos: [14]; default: 0; + * saradc2 interrupt raw + */ + +#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_M (RTC_CNTL_SARADC2_INT_RAW_V << RTC_CNTL_SARADC2_INT_RAW_S) +#define RTC_CNTL_SARADC2_INT_RAW_V 0x00000001 +#define RTC_CNTL_SARADC2_INT_RAW_S 14 + +/* RTC_CNTL_COCPU_INT_RAW : RO; bitpos: [13]; default: 0; + * riscV cocpu interrupt raw + */ + +#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_M (RTC_CNTL_COCPU_INT_RAW_V << RTC_CNTL_COCPU_INT_RAW_S) +#define RTC_CNTL_COCPU_INT_RAW_V 0x00000001 +#define RTC_CNTL_COCPU_INT_RAW_S 13 + +/* RTC_CNTL_TSENS_INT_RAW : RO; bitpos: [12]; default: 0; + * tsens interrupt raw + */ + +#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_M (RTC_CNTL_TSENS_INT_RAW_V << RTC_CNTL_TSENS_INT_RAW_S) +#define RTC_CNTL_TSENS_INT_RAW_V 0x00000001 +#define RTC_CNTL_TSENS_INT_RAW_S 12 + +/* RTC_CNTL_SARADC1_INT_RAW : RO; bitpos: [11]; default: 0; + * saradc1 interrupt raw + */ + +#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_M (RTC_CNTL_SARADC1_INT_RAW_V << RTC_CNTL_SARADC1_INT_RAW_S) +#define RTC_CNTL_SARADC1_INT_RAW_V 0x00000001 +#define RTC_CNTL_SARADC1_INT_RAW_S 11 + +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO; bitpos: [10]; default: 0; + * RTC main timer interrupt raw + */ + +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (RTC_CNTL_MAIN_TIMER_INT_RAW_V << RTC_CNTL_MAIN_TIMER_INT_RAW_S) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO; bitpos: [9]; default: 0; + * brown out interrupt raw + */ + +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (RTC_CNTL_BROWN_OUT_INT_RAW_V << RTC_CNTL_BROWN_OUT_INT_RAW_S) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO; bitpos: [8]; default: 0; + * touch inactive interrupt raw + */ + +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V << RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 + +/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO; bitpos: [7]; default: 0; + * touch active interrupt raw + */ + +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V << RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 + +/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO; bitpos: [6]; default: 0; + * touch interrupt raw + */ + +#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (RTC_CNTL_TOUCH_DONE_INT_RAW_V << RTC_CNTL_TOUCH_DONE_INT_RAW_S) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 + +/* RTC_CNTL_ULP_CP_INT_RAW : RO; bitpos: [5]; default: 0; + * ULP-coprocessor interrupt raw + */ + +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (RTC_CNTL_ULP_CP_INT_RAW_V << RTC_CNTL_ULP_CP_INT_RAW_S) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x00000001 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 + +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO; bitpos: [4]; default: 0; + * touch complete a loop interrupt raw + */ + +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 + +/* RTC_CNTL_WDT_INT_RAW : RO; bitpos: [3]; default: 0; + * RTC WDT interrupt raw + */ + +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (RTC_CNTL_WDT_INT_RAW_V << RTC_CNTL_WDT_INT_RAW_S) +#define RTC_CNTL_WDT_INT_RAW_V 0x00000001 +#define RTC_CNTL_WDT_INT_RAW_S 3 + +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO; bitpos: [2]; default: 0; + * SDIO idle interrupt raw + */ + +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (RTC_CNTL_SDIO_IDLE_INT_RAW_V << RTC_CNTL_SDIO_IDLE_INT_RAW_S) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x00000001 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 + +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO; bitpos: [1]; default: 0; + * sleep reject interrupt raw + */ + +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (RTC_CNTL_SLP_REJECT_INT_RAW_V << RTC_CNTL_SLP_REJECT_INT_RAW_S) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO; bitpos: [0]; default: 0; + * sleep wakeup interrupt raw + */ + +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (RTC_CNTL_SLP_WAKEUP_INT_RAW_V << RTC_CNTL_SLP_WAKEUP_INT_RAW_S) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +/* RTC_CNTL_INT_ST_RTC_REG register + * rtc_interrupt state register + */ + +#define RTC_CNTL_INT_ST_RTC_REG (DR_REG_RTCCNTL_BASE + 0x48) + +/* RTC_CNTL_GLITCH_DET_INT_ST : RO; bitpos: [19]; default: 0; + * glitch_det_interrupt state + */ + +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (RTC_CNTL_GLITCH_DET_INT_ST_V << RTC_CNTL_GLITCH_DET_INT_ST_S) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x00000001 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 + +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [18]; default: 0; + * Touch timeout interrupt state + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V << RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 + +/* RTC_CNTL_COCPU_TRAP_INT_ST : RO; bitpos: [17]; default: 0; + * cocpu trap interrupt state + */ + +#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_M (RTC_CNTL_COCPU_TRAP_INT_ST_V << RTC_CNTL_COCPU_TRAP_INT_ST_S) +#define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x00000001 +#define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 + +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO; bitpos: [16]; default: 0; + * xtal32k dead detection interrupt state + */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (RTC_CNTL_XTAL32K_DEAD_INT_ST_V << RTC_CNTL_XTAL32K_DEAD_INT_ST_S) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x00000001 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 + +/* RTC_CNTL_SWD_INT_ST : RO; bitpos: [15]; default: 0; + * super watch dog interrupt state + */ + +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (RTC_CNTL_SWD_INT_ST_V << RTC_CNTL_SWD_INT_ST_S) +#define RTC_CNTL_SWD_INT_ST_V 0x00000001 +#define RTC_CNTL_SWD_INT_ST_S 15 + +/* RTC_CNTL_SARADC2_INT_ST : RO; bitpos: [14]; default: 0; + * saradc2 interrupt state + */ + +#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_M (RTC_CNTL_SARADC2_INT_ST_V << RTC_CNTL_SARADC2_INT_ST_S) +#define RTC_CNTL_SARADC2_INT_ST_V 0x00000001 +#define RTC_CNTL_SARADC2_INT_ST_S 14 + +/* RTC_CNTL_COCPU_INT_ST : RO; bitpos: [13]; default: 0; + * riscV cocpu interrupt state + */ + +#define RTC_CNTL_COCPU_INT_ST (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_M (RTC_CNTL_COCPU_INT_ST_V << RTC_CNTL_COCPU_INT_ST_S) +#define RTC_CNTL_COCPU_INT_ST_V 0x00000001 +#define RTC_CNTL_COCPU_INT_ST_S 13 + +/* RTC_CNTL_TSENS_INT_ST : RO; bitpos: [12]; default: 0; + * tsens interrupt state + */ + +#define RTC_CNTL_TSENS_INT_ST (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_M (RTC_CNTL_TSENS_INT_ST_V << RTC_CNTL_TSENS_INT_ST_S) +#define RTC_CNTL_TSENS_INT_ST_V 0x00000001 +#define RTC_CNTL_TSENS_INT_ST_S 12 + +/* RTC_CNTL_SARADC1_INT_ST : RO; bitpos: [11]; default: 0; + * saradc1 interrupt state + */ + +#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_M (RTC_CNTL_SARADC1_INT_ST_V << RTC_CNTL_SARADC1_INT_ST_S) +#define RTC_CNTL_SARADC1_INT_ST_V 0x00000001 +#define RTC_CNTL_SARADC1_INT_ST_S 11 + +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO; bitpos: [10]; default: 0; + * RTC main timer interrupt state + */ + +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (RTC_CNTL_MAIN_TIMER_INT_ST_V << RTC_CNTL_MAIN_TIMER_INT_ST_S) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_ST : RO; bitpos: [9]; default: 0; + * brown out interrupt state + */ + +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (RTC_CNTL_BROWN_OUT_INT_ST_V << RTC_CNTL_BROWN_OUT_INT_ST_S) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO; bitpos: [8]; default: 0; + * touch inactive interrupt state + */ + +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (RTC_CNTL_TOUCH_INACTIVE_INT_ST_V << RTC_CNTL_TOUCH_INACTIVE_INT_ST_S) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 + +/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO; bitpos: [7]; default: 0; + * touch active interrupt state + */ + +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (RTC_CNTL_TOUCH_ACTIVE_INT_ST_V << RTC_CNTL_TOUCH_ACTIVE_INT_ST_S) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 + +/* RTC_CNTL_TOUCH_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * touch done interrupt state + */ + +#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_M (RTC_CNTL_TOUCH_DONE_INT_ST_V << RTC_CNTL_TOUCH_DONE_INT_ST_S) +#define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 + +/* RTC_CNTL_ULP_CP_INT_ST : RO; bitpos: [5]; default: 0; + * ULP-coprocessor interrupt state + */ + +#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_M (RTC_CNTL_ULP_CP_INT_ST_V << RTC_CNTL_ULP_CP_INT_ST_S) +#define RTC_CNTL_ULP_CP_INT_ST_V 0x00000001 +#define RTC_CNTL_ULP_CP_INT_ST_S 5 + +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * touch complete a loop interrupt state + */ + +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 + +/* RTC_CNTL_WDT_INT_ST : RO; bitpos: [3]; default: 0; + * RTC WDT interrupt state + */ + +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (RTC_CNTL_WDT_INT_ST_V << RTC_CNTL_WDT_INT_ST_S) +#define RTC_CNTL_WDT_INT_ST_V 0x00000001 +#define RTC_CNTL_WDT_INT_ST_S 3 + +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO; bitpos: [2]; default: 0; + * SDIO idle interrupt state + */ + +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (RTC_CNTL_SDIO_IDLE_INT_ST_V << RTC_CNTL_SDIO_IDLE_INT_ST_S) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x00000001 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 + +/* RTC_CNTL_SLP_REJECT_INT_ST : RO; bitpos: [1]; default: 0; + * sleep reject interrupt state + */ + +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (RTC_CNTL_SLP_REJECT_INT_ST_V << RTC_CNTL_SLP_REJECT_INT_ST_S) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO; bitpos: [0]; default: 0; + * sleep wakeup interrupt state + */ + +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (RTC_CNTL_SLP_WAKEUP_INT_ST_V << RTC_CNTL_SLP_WAKEUP_INT_ST_S) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +/* RTC_CNTL_INT_CLR_RTC_REG register + * Clear rtc_interrupt register + */ + +#define RTC_CNTL_INT_CLR_RTC_REG (DR_REG_RTCCNTL_BASE + 0x4c) + +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO; bitpos: [19]; default: 0; + * Clear glitch det interrupt state + */ + +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (RTC_CNTL_GLITCH_DET_INT_CLR_V << RTC_CNTL_GLITCH_DET_INT_CLR_S) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x00000001 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 + +/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO; bitpos: [18]; default: 0; + * Clear touch timeout interrupt state + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V << RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 + +/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO; bitpos: [17]; default: 0; + * Clear cocpu trap interrupt state + */ + +#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_M (RTC_CNTL_COCPU_TRAP_INT_CLR_V << RTC_CNTL_COCPU_TRAP_INT_CLR_S) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x00000001 +#define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 + +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO; bitpos: [16]; default: 0; + * Clear RTC WDT interrupt state + */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (RTC_CNTL_XTAL32K_DEAD_INT_CLR_V << RTC_CNTL_XTAL32K_DEAD_INT_CLR_S) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x00000001 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 + +/* RTC_CNTL_SWD_INT_CLR : WO; bitpos: [15]; default: 0; + * Clear super watch dog interrupt state + */ + +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (RTC_CNTL_SWD_INT_CLR_V << RTC_CNTL_SWD_INT_CLR_S) +#define RTC_CNTL_SWD_INT_CLR_V 0x00000001 +#define RTC_CNTL_SWD_INT_CLR_S 15 + +/* RTC_CNTL_SARADC2_INT_CLR : WO; bitpos: [14]; default: 0; + * Clear saradc2 interrupt state + */ + +#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_M (RTC_CNTL_SARADC2_INT_CLR_V << RTC_CNTL_SARADC2_INT_CLR_S) +#define RTC_CNTL_SARADC2_INT_CLR_V 0x00000001 +#define RTC_CNTL_SARADC2_INT_CLR_S 14 + +/* RTC_CNTL_COCPU_INT_CLR : WO; bitpos: [13]; default: 0; + * Clear riscV cocpu interrupt state + */ + +#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_M (RTC_CNTL_COCPU_INT_CLR_V << RTC_CNTL_COCPU_INT_CLR_S) +#define RTC_CNTL_COCPU_INT_CLR_V 0x00000001 +#define RTC_CNTL_COCPU_INT_CLR_S 13 + +/* RTC_CNTL_TSENS_INT_CLR : WO; bitpos: [12]; default: 0; + * Clear tsens interrupt state + */ + +#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_M (RTC_CNTL_TSENS_INT_CLR_V << RTC_CNTL_TSENS_INT_CLR_S) +#define RTC_CNTL_TSENS_INT_CLR_V 0x00000001 +#define RTC_CNTL_TSENS_INT_CLR_S 12 + +/* RTC_CNTL_SARADC1_INT_CLR : WO; bitpos: [11]; default: 0; + * Clear saradc1 interrupt state + */ + +#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_M (RTC_CNTL_SARADC1_INT_CLR_V << RTC_CNTL_SARADC1_INT_CLR_S) +#define RTC_CNTL_SARADC1_INT_CLR_V 0x00000001 +#define RTC_CNTL_SARADC1_INT_CLR_S 11 + +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO; bitpos: [10]; default: 0; + * Clear RTC main timer interrupt state + */ + +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (RTC_CNTL_MAIN_TIMER_INT_CLR_V << RTC_CNTL_MAIN_TIMER_INT_CLR_S) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO; bitpos: [9]; default: 0; + * Clear brown out interrupt state + */ + +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (RTC_CNTL_BROWN_OUT_INT_CLR_V << RTC_CNTL_BROWN_OUT_INT_CLR_S) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO; bitpos: [8]; default: 0; + * Clear touch inactive interrupt state + */ + +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V << RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 + +/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO; bitpos: [7]; default: 0; + * Clear touch active interrupt state + */ + +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V << RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 + +/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO; bitpos: [6]; default: 0; + * Clear touch done interrupt state + */ + +#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_M (RTC_CNTL_TOUCH_DONE_INT_CLR_V << RTC_CNTL_TOUCH_DONE_INT_CLR_S) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 + +/* RTC_CNTL_ULP_CP_INT_CLR : WO; bitpos: [5]; default: 0; + * Clear ULP-coprocessor interrupt state + */ + +#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_M (RTC_CNTL_ULP_CP_INT_CLR_V << RTC_CNTL_ULP_CP_INT_CLR_S) +#define RTC_CNTL_ULP_CP_INT_CLR_V 0x00000001 +#define RTC_CNTL_ULP_CP_INT_CLR_S 5 + +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO; bitpos: [4]; default: 0; + * Clear touch complete a loop interrupt state + */ + +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 + +/* RTC_CNTL_WDT_INT_CLR : WO; bitpos: [3]; default: 0; + * Clear RTC WDT interrupt state + */ + +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (RTC_CNTL_WDT_INT_CLR_V << RTC_CNTL_WDT_INT_CLR_S) +#define RTC_CNTL_WDT_INT_CLR_V 0x00000001 +#define RTC_CNTL_WDT_INT_CLR_S 3 + +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO; bitpos: [2]; default: 0; + * Clear SDIO idle interrupt state + */ + +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (RTC_CNTL_SDIO_IDLE_INT_CLR_V << RTC_CNTL_SDIO_IDLE_INT_CLR_S) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x00000001 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 + +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO; bitpos: [1]; default: 0; + * Clear sleep reject interrupt state + */ + +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (RTC_CNTL_SLP_REJECT_INT_CLR_V << RTC_CNTL_SLP_REJECT_INT_CLR_S) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO; bitpos: [0]; default: 0; + * Clear sleep wakeup interrupt state + */ + +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (RTC_CNTL_SLP_WAKEUP_INT_CLR_V << RTC_CNTL_SLP_WAKEUP_INT_CLR_S) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +/* RTC_CNTL_STORE0_REG register + * reservation register0 + */ + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) + +/* RTC_CNTL_SCRATCH0 : R/W; bitpos: [31:0]; default: 0; + * reservation register0 + */ + +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M (RTC_CNTL_SCRATCH0_V << RTC_CNTL_SCRATCH0_S) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +/* RTC_CNTL_STORE1_REG register + * reservation register1 + */ + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) + +#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG + +/* RTC_CNTL_SCRATCH1 : R/W; bitpos: [31:0]; default: 0; + * reservation register1 + */ + +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M (RTC_CNTL_SCRATCH1_V << RTC_CNTL_SCRATCH1_S) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +/* RTC_CNTL_STORE2_REG register + * reservation register2 + */ + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) + +/* RTC_CNTL_SCRATCH2 : R/W; bitpos: [31:0]; default: 0; + * reservation register2 + */ + +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M (RTC_CNTL_SCRATCH2_V << RTC_CNTL_SCRATCH2_S) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +/* RTC_CNTL_STORE3_REG register + * reservation register3 + */ + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5c) + +/* RTC_CNTL_SCRATCH3 : R/W; bitpos: [31:0]; default: 0; + * reservation register3 + */ + +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M (RTC_CNTL_SCRATCH3_V << RTC_CNTL_SCRATCH3_S) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +/* RTC_CNTL_EXT_XTL_CONF_REG register + * configure 32k xtal register + */ + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) + +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W; bitpos: [31]; default: 0; + * enable gpio power down XTAL + */ + +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (RTC_CNTL_XTL_EXT_CTR_EN_V << RTC_CNTL_XTL_EXT_CTR_EN_S) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x00000001 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 + +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W; bitpos: [30]; default: 0; + * 0: power down XTAL at high level 1: power down XTAL at low level + */ + +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (RTC_CNTL_XTL_EXT_CTR_LV_V << RTC_CNTL_XTL_EXT_CTR_LV_S) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x00000001 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 + +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W; bitpos: [23]; default: 0; + * XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C + */ + +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (RTC_CNTL_XTAL32K_GPIO_SEL_V << RTC_CNTL_XTAL32K_GPIO_SEL_S) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x00000001 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 + +/* RTC_CNTL_WDT_STATE : RO; bitpos: [22:20]; default: 0; + * state of 32k_wdt + */ + +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M (RTC_CNTL_WDT_STATE_V << RTC_CNTL_WDT_STATE_S) +#define RTC_CNTL_WDT_STATE_V 0x00000007 +#define RTC_CNTL_WDT_STATE_S 20 + +/* RTC_CNTL_DAC_XTAL_32K : R/W; bitpos: [19:17]; default: 3; + * DAC_XTAL_32K + */ + +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M (RTC_CNTL_DAC_XTAL_32K_V << RTC_CNTL_DAC_XTAL_32K_S) +#define RTC_CNTL_DAC_XTAL_32K_V 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_S 17 + +/* RTC_CNTL_XPD_XTAL_32K : R/W; bitpos: [16]; default: 0; + * XPD_XTAL_32K + */ + +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (RTC_CNTL_XPD_XTAL_32K_V << RTC_CNTL_XPD_XTAL_32K_S) +#define RTC_CNTL_XPD_XTAL_32K_V 0x00000001 +#define RTC_CNTL_XPD_XTAL_32K_S 16 + +/* RTC_CNTL_DRES_XTAL_32K : R/W; bitpos: [15:13]; default: 3; + * DRES_XTAL_32K + */ + +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M (RTC_CNTL_DRES_XTAL_32K_V << RTC_CNTL_DRES_XTAL_32K_S) +#define RTC_CNTL_DRES_XTAL_32K_V 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_S 13 + +/* RTC_CNTL_DGM_XTAL_32K : R/W; bitpos: [12:10]; default: 3; + * xtal_32k gm control + */ + +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M (RTC_CNTL_DGM_XTAL_32K_V << RTC_CNTL_DGM_XTAL_32K_S) +#define RTC_CNTL_DGM_XTAL_32K_V 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_S 10 + +/* RTC_CNTL_DBUF_XTAL_32K : R/W; bitpos: [9]; default: 0; + * 0: single-end buffer 1: differential buffer + */ + +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (RTC_CNTL_DBUF_XTAL_32K_V << RTC_CNTL_DBUF_XTAL_32K_S) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x00000001 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 + +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W; bitpos: [8]; default: 0; + * apply an internal clock to help xtal 32k to start + */ + +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (RTC_CNTL_ENCKINIT_XTAL_32K_V << RTC_CNTL_ENCKINIT_XTAL_32K_S) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x00000001 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 + +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W; bitpos: [7]; default: 1; + * Xtal 32k xpd control by sw or fsm + */ + +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (RTC_CNTL_XTAL32K_XPD_FORCE_V << RTC_CNTL_XTAL32K_XPD_FORCE_S) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x00000001 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 + +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W; bitpos: [6]; default: 0; + * xtal 32k switch back xtal when xtal is restarted + */ + +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (RTC_CNTL_XTAL32K_AUTO_RETURN_V << RTC_CNTL_XTAL32K_AUTO_RETURN_S) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x00000001 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 + +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W; bitpos: [5]; default: 0; + * xtal 32k restart xtal when xtal is dead + */ + +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (RTC_CNTL_XTAL32K_AUTO_RESTART_V << RTC_CNTL_XTAL32K_AUTO_RESTART_S) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x00000001 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 + +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W; bitpos: [4]; default: 0; + * xtal 32k switch to back up clock when xtal is dead + */ + +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (RTC_CNTL_XTAL32K_AUTO_BACKUP_V << RTC_CNTL_XTAL32K_AUTO_BACKUP_S) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x00000001 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 + +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W; bitpos: [3]; default: 0; + * xtal 32k external xtal clock force on + */ + +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (RTC_CNTL_XTAL32K_EXT_CLK_FO_V << RTC_CNTL_XTAL32K_EXT_CLK_FO_S) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x00000001 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 + +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W; bitpos: [2]; default: 0; + * xtal 32k watch dog sw reset + */ + +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (RTC_CNTL_XTAL32K_WDT_RESET_V << RTC_CNTL_XTAL32K_WDT_RESET_S) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x00000001 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 + +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W; bitpos: [1]; default: 0; + * xtal 32k watch dog clock force on + */ + +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (RTC_CNTL_XTAL32K_WDT_CLK_FO_V << RTC_CNTL_XTAL32K_WDT_CLK_FO_S) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x00000001 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 + +/* RTC_CNTL_XTAL32K_WDT_EN : R/W; bitpos: [0]; default: 0; + * xtal 32k watch dog enable + */ + +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (RTC_CNTL_XTAL32K_WDT_EN_V << RTC_CNTL_XTAL32K_WDT_EN_S) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x00000001 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +/* RTC_CNTL_EXT_WAKEUP_CONF_REG register + * configure gpio wakeup register + */ + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) + +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W; bitpos: [31]; default: 0; + * 0: external wakeup at low level 1: external wakeup at high level + */ + +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (RTC_CNTL_EXT_WAKEUP1_LV_V << RTC_CNTL_EXT_WAKEUP1_LV_S) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x00000001 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 + +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W; bitpos: [30]; default: 0; + * 0: external wakeup at low level 1: external wakeup at high level + */ + +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (RTC_CNTL_EXT_WAKEUP0_LV_V << RTC_CNTL_EXT_WAKEUP0_LV_S) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x00000001 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 + +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W; bitpos: [29]; default: 0; + * enable filter for gpio wakeup event + */ + +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (RTC_CNTL_GPIO_WAKEUP_FILTER_V << RTC_CNTL_GPIO_WAKEUP_FILTER_S) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x00000001 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 + +/* RTC_CNTL_SLP_REJECT_CONF_REG register + * configure sleep reject register + */ + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) + +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * enable reject for deep sleep + */ + +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (RTC_CNTL_DEEP_SLP_REJECT_EN_V << RTC_CNTL_DEEP_SLP_REJECT_EN_S) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x00000001 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 + +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W; bitpos: [30]; default: 0; + * enable reject for light sleep + */ + +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (RTC_CNTL_LIGHT_SLP_REJECT_EN_V << RTC_CNTL_LIGHT_SLP_REJECT_EN_S) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x00000001 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 + +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W; bitpos: [29:13]; default: 0; + * sleep reject enable + */ + +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0001FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M (RTC_CNTL_SLEEP_REJECT_ENA_V << RTC_CNTL_SLEEP_REJECT_ENA_S) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x0001FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 13 + +/* RTC_CNTL_CPU_PERIOD_CONF_REG register + * CPU sel option + */ + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) + +/* RTC_CNTL_CPUPERIOD_SEL : R/W; bitpos: [31:30]; default: 0; */ + +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M (RTC_CNTL_CPUPERIOD_SEL_V << RTC_CNTL_CPUPERIOD_SEL_S) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 + +/* RTC_CNTL_CPUSEL_CONF : R/W; bitpos: [29]; default: 0; + * CPU sel option + */ + +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (RTC_CNTL_CPUSEL_CONF_V << RTC_CNTL_CPUSEL_CONF_S) +#define RTC_CNTL_CPUSEL_CONF_V 0x00000001 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +/* RTC_CNTL_SDIO_ACT_CONF_REG register + * configure sdio active register + */ + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) + +/* RTC_CNTL_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 0; + * configure sdio act dnum + */ + +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M (RTC_CNTL_SDIO_ACT_DNUM_V << RTC_CNTL_SDIO_ACT_DNUM_S) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +/* RTC_CNTL_CLK_CONF_REG register + * configure rtc clk register + */ + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) + +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W; bitpos: [31:30]; default: 0; + * slow clk sel 0 : 90K rtc_clk 1 : 32k XTAL 2 : 8md256 + */ + +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M (RTC_CNTL_ANA_CLK_RTC_SEL_V << RTC_CNTL_ANA_CLK_RTC_SEL_S) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 + +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W; bitpos: [29]; default: 0; + * fast_clk_rtc sel. 0: XTAL div 4 1: CK8M + */ + +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (RTC_CNTL_FAST_CLK_RTC_SEL_V << RTC_CNTL_FAST_CLK_RTC_SEL_S) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x00000001 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 + +/* RTC_CNTL_CK8M_FORCE_PU : R/W; bitpos: [26]; default: 0; + * CK8M force power up + */ + +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (RTC_CNTL_CK8M_FORCE_PU_V << RTC_CNTL_CK8M_FORCE_PU_S) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x00000001 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 + +/* RTC_CNTL_CK8M_FORCE_PD : R/W; bitpos: [25]; default: 0; + * CK8M force power down + */ + +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (RTC_CNTL_CK8M_FORCE_PD_V << RTC_CNTL_CK8M_FORCE_PD_S) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x00000001 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 + +/* RTC_CNTL_CK8M_DFREQ : R/W; bitpos: [24:17]; default: 172; + * CK8M_DFREQ + */ + +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M (RTC_CNTL_CK8M_DFREQ_V << RTC_CNTL_CK8M_DFREQ_S) +#define RTC_CNTL_CK8M_DFREQ_V 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_S 17 + +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W; bitpos: [16]; default: 0; + * CK8M force no gating during sleep + */ + +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (RTC_CNTL_CK8M_FORCE_NOGATING_V << RTC_CNTL_CK8M_FORCE_NOGATING_S) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x00000001 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 + +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W; bitpos: [15]; default: 0; + * XTAL force no gating during sleep + */ + +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_FORCE_NOGATING_S) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x00000001 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 + +/* RTC_CNTL_CK8M_DIV_SEL : R/W; bitpos: [14:12]; default: 3; + * divider = reg_ck8m_div_sel + 1 + */ + +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M (RTC_CNTL_CK8M_DIV_SEL_V << RTC_CNTL_CK8M_DIV_SEL_S) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 + +/* RTC_CNTL_DIG_CLK8M_EN : R/W; bitpos: [10]; default: 0; + * enable CK8M for digital core (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (RTC_CNTL_DIG_CLK8M_EN_V << RTC_CNTL_DIG_CLK8M_EN_S) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x00000001 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 + +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W; bitpos: [9]; default: 1; + * enable CK8M_D256_OUT for digital core (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (RTC_CNTL_DIG_CLK8M_D256_EN_V << RTC_CNTL_DIG_CLK8M_D256_EN_S) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x00000001 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 + +/* RTC_CNTL_DIG_XTAL32K_EN : R/W; bitpos: [8]; default: 0; + * enable CK_XTAL_32K for digital core (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (RTC_CNTL_DIG_XTAL32K_EN_V << RTC_CNTL_DIG_XTAL32K_EN_S) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x00000001 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 + +/* RTC_CNTL_ENB_CK8M_DIV : R/W; bitpos: [7]; default: 0; + * 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by + * 256 + */ + +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (RTC_CNTL_ENB_CK8M_DIV_V << RTC_CNTL_ENB_CK8M_DIV_S) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x00000001 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 + +/* RTC_CNTL_ENB_CK8M : R/W; bitpos: [6]; default: 0; + * disable CK8M and CK8M_D256_OUT + */ + +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (RTC_CNTL_ENB_CK8M_V << RTC_CNTL_ENB_CK8M_S) +#define RTC_CNTL_ENB_CK8M_V 0x00000001 +#define RTC_CNTL_ENB_CK8M_S 6 + +/* RTC_CNTL_CK8M_DIV : R/W; bitpos: [5:4]; default: 1; + * CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: + * div1024. + */ + +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M (RTC_CNTL_CK8M_DIV_V << RTC_CNTL_CK8M_DIV_S) +#define RTC_CNTL_CK8M_DIV_V 0x00000003 +#define RTC_CNTL_CK8M_DIV_S 4 + +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W; bitpos: [3]; default: 1; + * used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel + * then set vld to actually switch the clk + */ + +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (RTC_CNTL_CK8M_DIV_SEL_VLD_V << RTC_CNTL_CK8M_DIV_SEL_VLD_S) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x00000001 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 + +/* RTC_CNTL_SLOW_CLK_CONF_REG register + * configure rtc slow clk register + */ + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) + +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W; bitpos: [31]; default: 0; */ + +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (RTC_CNTL_SLOW_CLK_NEXT_EDGE_V << RTC_CNTL_SLOW_CLK_NEXT_EDGE_S) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x00000001 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 + +/* RTC_CNTL_ANA_CLK_DIV : R/W; bitpos: [30:23]; default: 0; + * rtc_clk divider + */ + +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M (RTC_CNTL_ANA_CLK_DIV_V << RTC_CNTL_ANA_CLK_DIV_S) +#define RTC_CNTL_ANA_CLK_DIV_V 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_S 23 + +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W; bitpos: [22]; default: 1; + * used to sync div bus. clear vld before set reg_rtc_ana_clk_div then set + * vld to actually switch the clk + */ + +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (RTC_CNTL_ANA_CLK_DIV_VLD_V << RTC_CNTL_ANA_CLK_DIV_VLD_S) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x00000001 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 + +/* RTC_CNTL_SDIO_CONF_REG register + * configure vddsdio register + */ + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7c) + +/* RTC_CNTL_XPD_SDIO_REG : R/W; bitpos: [31]; default: 0; + * SW option for XPD_VOOSDIO. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (RTC_CNTL_XPD_SDIO_REG_V << RTC_CNTL_XPD_SDIO_REG_S) +#define RTC_CNTL_XPD_SDIO_REG_V 0x00000001 +#define RTC_CNTL_XPD_SDIO_REG_S 31 + +/* RTC_CNTL_DREFH_SDIO : R/W; bitpos: [30:29]; default: 0; + * SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M (RTC_CNTL_DREFH_SDIO_V << RTC_CNTL_DREFH_SDIO_S) +#define RTC_CNTL_DREFH_SDIO_V 0x00000003 +#define RTC_CNTL_DREFH_SDIO_S 29 + +/* RTC_CNTL_DREFM_SDIO : R/W; bitpos: [28:27]; default: 0; + * SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M (RTC_CNTL_DREFM_SDIO_V << RTC_CNTL_DREFM_SDIO_S) +#define RTC_CNTL_DREFM_SDIO_V 0x00000003 +#define RTC_CNTL_DREFM_SDIO_S 27 + +/* RTC_CNTL_DREFL_SDIO : R/W; bitpos: [26:25]; default: 1; + * SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M (RTC_CNTL_DREFL_SDIO_V << RTC_CNTL_DREFL_SDIO_S) +#define RTC_CNTL_DREFL_SDIO_V 0x00000003 +#define RTC_CNTL_DREFL_SDIO_S 25 + +/* RTC_CNTL_REG1P8_READY : RO; bitpos: [24]; default: 0; + * read only register for REG1P8_READY + */ + +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (RTC_CNTL_REG1P8_READY_V << RTC_CNTL_REG1P8_READY_S) +#define RTC_CNTL_REG1P8_READY_V 0x00000001 +#define RTC_CNTL_REG1P8_READY_S 24 + +/* RTC_CNTL_SDIO_TIEH : R/W; bitpos: [23]; default: 1; + * SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (RTC_CNTL_SDIO_TIEH_V << RTC_CNTL_SDIO_TIEH_S) +#define RTC_CNTL_SDIO_TIEH_V 0x00000001 +#define RTC_CNTL_SDIO_TIEH_S 23 + +/* RTC_CNTL_SDIO_FORCE : R/W; bitpos: [22]; default: 0; + * 1: use SW option to control SDIO_REG 0: use state machine + */ + +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (RTC_CNTL_SDIO_FORCE_V << RTC_CNTL_SDIO_FORCE_S) +#define RTC_CNTL_SDIO_FORCE_V 0x00000001 +#define RTC_CNTL_SDIO_FORCE_S 22 + +/* RTC_CNTL_SDIO_REG_PD_EN : R/W; bitpos: [21]; default: 1; + * power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + */ + +#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_REG_PD_EN_M (RTC_CNTL_SDIO_REG_PD_EN_V << RTC_CNTL_SDIO_REG_PD_EN_S) +#define RTC_CNTL_SDIO_REG_PD_EN_V 0x00000001 +#define RTC_CNTL_SDIO_REG_PD_EN_S 21 + +/* RTC_CNTL_SDIO_ENCURLIM : R/W; bitpos: [20]; default: 1; + * enable current limit + */ + +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (RTC_CNTL_SDIO_ENCURLIM_V << RTC_CNTL_SDIO_ENCURLIM_S) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x00000001 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 + +/* RTC_CNTL_SDIO_MODECURLIM : R/W; bitpos: [19]; default: 0; + * select current limit mode + */ + +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (RTC_CNTL_SDIO_MODECURLIM_V << RTC_CNTL_SDIO_MODECURLIM_S) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x00000001 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 + +/* RTC_CNTL_SDIO_DCURLIM : R/W; bitpos: [18:16]; default: 0; + * tune current limit threshold when tieh = 0. About 800mA/(8+d) + */ + +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M (RTC_CNTL_SDIO_DCURLIM_V << RTC_CNTL_SDIO_DCURLIM_S) +#define RTC_CNTL_SDIO_DCURLIM_V 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_S 16 + +/* RTC_CNTL_SDIO_EN_INITI : R/W; bitpos: [15]; default: 1; + * 0 to set init[1:0]=0 + */ + +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (RTC_CNTL_SDIO_EN_INITI_V << RTC_CNTL_SDIO_EN_INITI_S) +#define RTC_CNTL_SDIO_EN_INITI_V 0x00000001 +#define RTC_CNTL_SDIO_EN_INITI_S 15 + +/* RTC_CNTL_SDIO_INITI : R/W; bitpos: [14:13]; default: 1; + * add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k + */ + +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M (RTC_CNTL_SDIO_INITI_V << RTC_CNTL_SDIO_INITI_S) +#define RTC_CNTL_SDIO_INITI_V 0x00000003 +#define RTC_CNTL_SDIO_INITI_S 13 + +/* RTC_CNTL_SDIO_DCAP : R/W; bitpos: [12:11]; default: 3; + * ability to prevent LDO from overshoot + */ + +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M (RTC_CNTL_SDIO_DCAP_V << RTC_CNTL_SDIO_DCAP_S) +#define RTC_CNTL_SDIO_DCAP_V 0x00000003 +#define RTC_CNTL_SDIO_DCAP_S 11 + +/* RTC_CNTL_SDIO_DTHDRV : R/W; bitpos: [10:9]; default: 3; + * Tieh = 1 mode drive ability. Initially set to 0 to limit charge current + * set to 3 after several us. + */ + +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M (RTC_CNTL_SDIO_DTHDRV_V << RTC_CNTL_SDIO_DTHDRV_S) +#define RTC_CNTL_SDIO_DTHDRV_V 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_S 9 + +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W; bitpos: [7:0]; default: 10; + * timer count to apply reg_sdio_dcap after sdio power on + */ + +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M (RTC_CNTL_SDIO_TIMER_TARGET_V << RTC_CNTL_SDIO_TIMER_TARGET_S) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +/* RTC_CNTL_BIAS_CONF_REG register + * configure power register + */ + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) + +/* RTC_CNTL_RST_BIAS_I2C : R/W; bitpos: [31]; default: 0; */ + +#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_M (RTC_CNTL_RST_BIAS_I2C_V << RTC_CNTL_RST_BIAS_I2C_S) +#define RTC_CNTL_RST_BIAS_I2C_V 0x00000001 +#define RTC_CNTL_RST_BIAS_I2C_S 31 + +/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W; bitpos: [30]; default: 0; + * DEC_HEARTBEAT_WIDTH + */ + +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (RTC_CNTL_DEC_HEARTBEAT_WIDTH_V << RTC_CNTL_DEC_HEARTBEAT_WIDTH_S) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x00000001 +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 + +/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W; bitpos: [29]; default: 0; + * INC_HEARTBEAT_PERIOD + */ + +#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (RTC_CNTL_INC_HEARTBEAT_PERIOD_V << RTC_CNTL_INC_HEARTBEAT_PERIOD_S) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x00000001 +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 + +/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W; bitpos: [28]; default: 0; + * DEC_HEARTBEAT_PERIOD + */ + +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (RTC_CNTL_DEC_HEARTBEAT_PERIOD_V << RTC_CNTL_DEC_HEARTBEAT_PERIOD_S) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x00000001 +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 + +/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W; bitpos: [27]; default: 0; + * INC_HEARTBEAT_REFRESH + */ + +#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (RTC_CNTL_INC_HEARTBEAT_REFRESH_V << RTC_CNTL_INC_HEARTBEAT_REFRESH_S) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x00000001 +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 + +/* RTC_CNTL_ENB_SCK_XTAL : R/W; bitpos: [26]; default: 0; + * ENB_SCK_XTAL + */ + +#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_M (RTC_CNTL_ENB_SCK_XTAL_V << RTC_CNTL_ENB_SCK_XTAL_S) +#define RTC_CNTL_ENB_SCK_XTAL_V 0x00000001 +#define RTC_CNTL_ENB_SCK_XTAL_S 26 + +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W; bitpos: [25:22]; default: 0; + * DBG_ATTEN when rtc in monitor state + */ + +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M (RTC_CNTL_DBG_ATTEN_MONITOR_V << RTC_CNTL_DBG_ATTEN_MONITOR_S) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 + +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W; bitpos: [21:18]; default: 0; + * DBG_ATTEN when rtc in sleep state + */ + +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M (RTC_CNTL_DBG_ATTEN_DEEP_SLP_V << RTC_CNTL_DBG_ATTEN_DEEP_SLP_S) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 + +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W; bitpos: [17]; default: 0; + * bias_sleep when rtc in monitor state + */ + +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (RTC_CNTL_BIAS_SLEEP_MONITOR_V << RTC_CNTL_BIAS_SLEEP_MONITOR_S) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x00000001 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 + +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W; bitpos: [16]; default: 1; + * bias_sleep when rtc in sleep_state + */ + +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V << RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x00000001 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 + +/* RTC_CNTL_PD_CUR_MONITOR : R/W; bitpos: [15]; default: 0; + * xpd cur when rtc in monitor state + */ + +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (RTC_CNTL_PD_CUR_MONITOR_V << RTC_CNTL_PD_CUR_MONITOR_S) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x00000001 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 + +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W; bitpos: [14]; default: 0; + * xpd cur when rtc in sleep_state + */ + +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (RTC_CNTL_PD_CUR_DEEP_SLP_V << RTC_CNTL_PD_CUR_DEEP_SLP_S) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x00000001 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 + +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W; bitpos: [13]; default: 0; + * open bias buf when rtc in monitor state + */ + +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (RTC_CNTL_BIAS_BUF_MONITOR_V << RTC_CNTL_BIAS_BUF_MONITOR_S) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x00000001 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 + +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W; bitpos: [12]; default: 0; + * open bias buf when rtc in deep sleep + */ + +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (RTC_CNTL_BIAS_BUF_DEEP_SLP_V << RTC_CNTL_BIAS_BUF_DEEP_SLP_S) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x00000001 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 + +/* RTC_CNTL_BIAS_BUF_WAKE : R/W; bitpos: [11]; default: 1; + * open bias buf when rtc in wakeup + */ + +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (RTC_CNTL_BIAS_BUF_WAKE_V << RTC_CNTL_BIAS_BUF_WAKE_S) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x00000001 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 + +/* RTC_CNTL_BIAS_BUF_IDLE : R/W; bitpos: [10]; default: 0; + * open bias buf when system in active + */ + +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (RTC_CNTL_BIAS_BUF_IDLE_V << RTC_CNTL_BIAS_BUF_IDLE_S) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x00000001 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 + +/* RTC_CNTL_REG register + * configure rtc/dig regulator register + */ +#define RTC_CNTL_DIG_DBIAS_0V85 0 +#define RTC_CNTL_DIG_DBIAS_0V90 1 +#define RTC_CNTL_DIG_DBIAS_0V95 2 +#define RTC_CNTL_DIG_DBIAS_1V00 3 +#define RTC_CNTL_DIG_DBIAS_1V05 4 +#define RTC_CNTL_DIG_DBIAS_1V10 5 +#define RTC_CNTL_DIG_DBIAS_1V15 6 +#define RTC_CNTL_DIG_DBIAS_1V20 7 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84) + +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W; bitpos: [31]; default: 1; + * RTC_REG force power pu + */ + +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (RTC_CNTL_REGULATOR_FORCE_PU_V << RTC_CNTL_REGULATOR_FORCE_PU_S) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x00000001 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 + +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W; bitpos: [30]; default: 0; + * RTC_REG force power down (for RTC_REG power down means decrease the + * voltage to 0.8v or lower ) + */ + +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (RTC_CNTL_REGULATOR_FORCE_PD_V << RTC_CNTL_REGULATOR_FORCE_PD_S) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x00000001 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 + +/* RTC_CNTL_DBOOST_FORCE_PU : R/W; bitpos: [29]; default: 1; + * RTC_DBOOST force power up + */ + +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (RTC_CNTL_DBOOST_FORCE_PU_V << RTC_CNTL_DBOOST_FORCE_PU_S) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x00000001 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 + +/* RTC_CNTL_DBOOST_FORCE_PD : R/W; bitpos: [28]; default: 0; + * RTC_DBOOST force power down + */ + +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (RTC_CNTL_DBOOST_FORCE_PD_V << RTC_CNTL_DBOOST_FORCE_PD_S) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x00000001 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 + +/* RTC_CNTL_DBIAS_WAK : R/W; bitpos: [27:25]; default: 4; + * RTC_DBIAS during wakeup + */ + +#define RTC_CNTL_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DBIAS_WAK_M (RTC_CNTL_DBIAS_WAK_V << RTC_CNTL_DBIAS_WAK_S) +#define RTC_CNTL_DBIAS_WAK_V 0x00000007 +#define RTC_CNTL_DBIAS_WAK_S 25 + +/* RTC_CNTL_DBIAS_SLP : R/W; bitpos: [24:22]; default: 4; + * RTC_DBIAS during sleep + */ + +#define RTC_CNTL_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DBIAS_SLP_M (RTC_CNTL_DBIAS_SLP_V << RTC_CNTL_DBIAS_SLP_S) +#define RTC_CNTL_DBIAS_SLP_V 0x00000007 +#define RTC_CNTL_DBIAS_SLP_S 22 + +/* RTC_CNTL_SCK_DCAP : R/W; bitpos: [21:14]; default: 0; + * SCK_DCAP + */ + +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M (RTC_CNTL_SCK_DCAP_V << RTC_CNTL_SCK_DCAP_S) +#define RTC_CNTL_SCK_DCAP_V 0x000000FF +#define RTC_CNTL_SCK_DCAP_S 14 + +/* RTC_CNTL_DIG_REG_DBIAS_WAK : R/W; bitpos: [13:11]; default: 4; + * DIG_REG_DBIAS during wakeup + */ + +#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_M (RTC_CNTL_DIG_DBIAS_WAK_V << RTC_CNTL_DIG_DBIAS_WAK_S) +#define RTC_CNTL_DIG_DBIAS_WAK_V 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_S 11 + +/* RTC_CNTL_DIG_REG_DBIAS_SLP : R/W; bitpos: [10:8]; default: 4; + * DIG_REG_DBIAS during sleep + */ + +#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_M (RTC_CNTL_DIG_DBIAS_SLP_V << RTC_CNTL_DIG_DBIAS_SLP_S) +#define RTC_CNTL_DIG_DBIAS_SLP_V 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_S 8 + +/* RTC_CNTL_PWC_REG register + * configure rtc power configure + */ + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) + +/* RTC_CNTL_PAD_FORCE_HOLD : R/W; bitpos: [21]; default: 0; + * rtc pad force hold + */ + +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (RTC_CNTL_PAD_FORCE_HOLD_V << RTC_CNTL_PAD_FORCE_HOLD_S) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x00000001 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 + +/* RTC_CNTL_PD_EN : R/W; bitpos: [20]; default: 0; + * enable power down rtc_peri in sleep + */ + +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (RTC_CNTL_PD_EN_V << RTC_CNTL_PD_EN_S) +#define RTC_CNTL_PD_EN_V 0x00000001 +#define RTC_CNTL_PD_EN_S 20 + +/* RTC_CNTL_FORCE_PU : R/W; bitpos: [19]; default: 0; + * rtc_peri force power up + */ + +#define RTC_CNTL_FORCE_PU (BIT(19)) +#define RTC_CNTL_FORCE_PU_M (RTC_CNTL_FORCE_PU_V << RTC_CNTL_FORCE_PU_S) +#define RTC_CNTL_FORCE_PU_V 0x00000001 +#define RTC_CNTL_FORCE_PU_S 19 + +/* RTC_CNTL_FORCE_PD : R/W; bitpos: [18]; default: 0; + * rtc_peri force power down + */ + +#define RTC_CNTL_FORCE_PD (BIT(18)) +#define RTC_CNTL_FORCE_PD_M (RTC_CNTL_FORCE_PD_V << RTC_CNTL_FORCE_PD_S) +#define RTC_CNTL_FORCE_PD_V 0x00000001 +#define RTC_CNTL_FORCE_PD_S 18 + +/* RTC_CNTL_SLOWMEM_PD_EN : R/W; bitpos: [17]; default: 0; + * enable power down RTC memory in sleep + */ + +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (RTC_CNTL_SLOWMEM_PD_EN_V << RTC_CNTL_SLOWMEM_PD_EN_S) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x00000001 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 + +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W; bitpos: [16]; default: 1; + * RTC memory force power up + */ + +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (RTC_CNTL_SLOWMEM_FORCE_PU_V << RTC_CNTL_SLOWMEM_FORCE_PU_S) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 + +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W; bitpos: [15]; default: 0; + * RTC memory force power down + */ + +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (RTC_CNTL_SLOWMEM_FORCE_PD_V << RTC_CNTL_SLOWMEM_FORCE_PD_S) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 + +/* RTC_CNTL_FASTMEM_PD_EN : R/W; bitpos: [14]; default: 0; + * enable power down fast RTC memory in sleep + */ + +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (RTC_CNTL_FASTMEM_PD_EN_V << RTC_CNTL_FASTMEM_PD_EN_S) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x00000001 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 + +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W; bitpos: [13]; default: 1; + * Fast RTC memory force power up + */ + +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (RTC_CNTL_FASTMEM_FORCE_PU_V << RTC_CNTL_FASTMEM_FORCE_PU_S) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 + +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W; bitpos: [12]; default: 0; + * Fast RTC memory force power down + */ + +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (RTC_CNTL_FASTMEM_FORCE_PD_V << RTC_CNTL_FASTMEM_FORCE_PD_S) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 + +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W; bitpos: [11]; default: 1; + * RTC memory force no PD + */ + +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (RTC_CNTL_SLOWMEM_FORCE_LPU_V << RTC_CNTL_SLOWMEM_FORCE_LPU_S) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 + +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W; bitpos: [10]; default: 0; + * RTC memory force PD + */ + +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (RTC_CNTL_SLOWMEM_FORCE_LPD_V << RTC_CNTL_SLOWMEM_FORCE_LPD_S) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 + +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W; bitpos: [9]; default: 0; + * 1: RTC memory PD following CPU 0: RTC memory PD following RTC state + * machine + */ + +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (RTC_CNTL_SLOWMEM_FOLW_CPU_V << RTC_CNTL_SLOWMEM_FOLW_CPU_S) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 + +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W; bitpos: [8]; default: 1; + * Fast RTC memory force no PD + */ + +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (RTC_CNTL_FASTMEM_FORCE_LPU_V << RTC_CNTL_FASTMEM_FORCE_LPU_S) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 + +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W; bitpos: [7]; default: 0; + * Fast RTC memory force PD + */ + +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (RTC_CNTL_FASTMEM_FORCE_LPD_V << RTC_CNTL_FASTMEM_FORCE_LPD_S) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 + +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W; bitpos: [6]; default: 0; + * 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC + * state machine + */ + +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (RTC_CNTL_FASTMEM_FOLW_CPU_V << RTC_CNTL_FASTMEM_FOLW_CPU_S) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x00000001 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 + +/* RTC_CNTL_FORCE_NOISO : R/W; bitpos: [5]; default: 1; + * rtc_peri force no ISO + */ + +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (RTC_CNTL_FORCE_NOISO_V << RTC_CNTL_FORCE_NOISO_S) +#define RTC_CNTL_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_FORCE_NOISO_S 5 + +/* RTC_CNTL_FORCE_ISO : R/W; bitpos: [4]; default: 0; + * rtc_peri force ISO + */ + +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (RTC_CNTL_FORCE_ISO_V << RTC_CNTL_FORCE_ISO_S) +#define RTC_CNTL_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_FORCE_ISO_S 4 + +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W; bitpos: [3]; default: 0; + * RTC memory force ISO + */ + +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (RTC_CNTL_SLOWMEM_FORCE_ISO_V << RTC_CNTL_SLOWMEM_FORCE_ISO_S) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 + +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W; bitpos: [2]; default: 1; + * RTC memory force no ISO + */ + +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (RTC_CNTL_SLOWMEM_FORCE_NOISO_V << RTC_CNTL_SLOWMEM_FORCE_NOISO_S) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 + +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W; bitpos: [1]; default: 0; + * Fast RTC memory force ISO + */ + +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (RTC_CNTL_FASTMEM_FORCE_ISO_V << RTC_CNTL_FASTMEM_FORCE_ISO_S) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 + +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W; bitpos: [0]; default: 1; + * Fast RTC memory force no ISO + */ + +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (RTC_CNTL_FASTMEM_FORCE_NOISO_V << RTC_CNTL_FASTMEM_FORCE_NOISO_S) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +/* RTC_CNTL_DIG_PWC_REG register + * configure power of digital core + */ + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x8c) + +/* RTC_CNTL_DG_WRAP_PD_EN : R/W; bitpos: [31]; default: 0; + * enable power down digital core in sleep + */ + +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (RTC_CNTL_DG_WRAP_PD_EN_V << RTC_CNTL_DG_WRAP_PD_EN_S) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x00000001 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 + +/* RTC_CNTL_WIFI_PD_EN : R/W; bitpos: [30]; default: 0; + * enable power down wifi in sleep + */ + +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (RTC_CNTL_WIFI_PD_EN_V << RTC_CNTL_WIFI_PD_EN_S) +#define RTC_CNTL_WIFI_PD_EN_V 0x00000001 +#define RTC_CNTL_WIFI_PD_EN_S 30 + +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W; bitpos: [29]; default: 0; + * enable power down internal SRAM 4 in sleep + */ + +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (RTC_CNTL_INTER_RAM4_PD_EN_V << RTC_CNTL_INTER_RAM4_PD_EN_S) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 + +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W; bitpos: [28]; default: 0; + * enable power down internal SRAM 3 in sleep + */ + +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (RTC_CNTL_INTER_RAM3_PD_EN_V << RTC_CNTL_INTER_RAM3_PD_EN_S) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 + +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W; bitpos: [27]; default: 0; + * enable power down internal SRAM 2 in sleep + */ + +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (RTC_CNTL_INTER_RAM2_PD_EN_V << RTC_CNTL_INTER_RAM2_PD_EN_S) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 + +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W; bitpos: [26]; default: 0; + * enable power down internal SRAM 1 in sleep + */ + +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (RTC_CNTL_INTER_RAM1_PD_EN_V << RTC_CNTL_INTER_RAM1_PD_EN_S) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 + +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W; bitpos: [25]; default: 0; + * enable power down internal SRAM 0 in sleep + */ + +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (RTC_CNTL_INTER_RAM0_PD_EN_V << RTC_CNTL_INTER_RAM0_PD_EN_S) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 + +/* RTC_CNTL_ROM0_PD_EN : R/W; bitpos: [24]; default: 0; + * enable power down ROM in sleep + */ + +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (RTC_CNTL_ROM0_PD_EN_V << RTC_CNTL_ROM0_PD_EN_S) +#define RTC_CNTL_ROM0_PD_EN_V 0x00000001 +#define RTC_CNTL_ROM0_PD_EN_S 24 + +/* RTC_CNTL_DG_DCDC_PD_EN : R/W; bitpos: [23]; default: 0; + * enable power down digital dcdc in sleep + */ + +#define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) +#define RTC_CNTL_DG_DCDC_PD_EN_M (RTC_CNTL_DG_DCDC_PD_EN_V << RTC_CNTL_DG_DCDC_PD_EN_S) +#define RTC_CNTL_DG_DCDC_PD_EN_V 0x00000001 +#define RTC_CNTL_DG_DCDC_PD_EN_S 23 + +/* RTC_CNTL_DG_DCDC_FORCE_PU : R/W; bitpos: [22]; default: 1; + * digital dcdc force power up + */ + +#define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) +#define RTC_CNTL_DG_DCDC_FORCE_PU_M (RTC_CNTL_DG_DCDC_FORCE_PU_V << RTC_CNTL_DG_DCDC_FORCE_PU_S) +#define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x00000001 +#define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 + +/* RTC_CNTL_DG_DCDC_FORCE_PD : R/W; bitpos: [21]; default: 0; + * digital dcdc force power down + */ + +#define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) +#define RTC_CNTL_DG_DCDC_FORCE_PD_M (RTC_CNTL_DG_DCDC_FORCE_PD_V << RTC_CNTL_DG_DCDC_FORCE_PD_S) +#define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x00000001 +#define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 + +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W; bitpos: [20]; default: 1; + * digital core force power up + */ + +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (RTC_CNTL_DG_WRAP_FORCE_PU_V << RTC_CNTL_DG_WRAP_FORCE_PU_S) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 + +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W; bitpos: [19]; default: 0; + * digital core force power down + */ + +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (RTC_CNTL_DG_WRAP_FORCE_PD_V << RTC_CNTL_DG_WRAP_FORCE_PD_S) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 + +/* RTC_CNTL_WIFI_FORCE_PU : R/W; bitpos: [18]; default: 1; + * wifi force power up + */ + +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (RTC_CNTL_WIFI_FORCE_PU_V << RTC_CNTL_WIFI_FORCE_PU_S) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x00000001 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 + +/* RTC_CNTL_WIFI_FORCE_PD : R/W; bitpos: [17]; default: 0; + * wifi force power down + */ + +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (RTC_CNTL_WIFI_FORCE_PD_V << RTC_CNTL_WIFI_FORCE_PD_S) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x00000001 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 + +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W; bitpos: [16]; default: 1; + * internal SRAM 4 force power up + */ + +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (RTC_CNTL_INTER_RAM4_FORCE_PU_V << RTC_CNTL_INTER_RAM4_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 + +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W; bitpos: [15]; default: 0; + * internal SRAM 4 force power down + */ + +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (RTC_CNTL_INTER_RAM4_FORCE_PD_V << RTC_CNTL_INTER_RAM4_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 + +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W; bitpos: [14]; default: 1; + * internal SRAM 3 force power up + */ + +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (RTC_CNTL_INTER_RAM3_FORCE_PU_V << RTC_CNTL_INTER_RAM3_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 + +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W; bitpos: [13]; default: 0; + * internal SRAM 3 force power down + */ + +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (RTC_CNTL_INTER_RAM3_FORCE_PD_V << RTC_CNTL_INTER_RAM3_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 + +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W; bitpos: [12]; default: 1; + * internal SRAM 2 force power up + */ + +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (RTC_CNTL_INTER_RAM2_FORCE_PU_V << RTC_CNTL_INTER_RAM2_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 + +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W; bitpos: [11]; default: 0; + * internal SRAM 2 force power down + */ + +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (RTC_CNTL_INTER_RAM2_FORCE_PD_V << RTC_CNTL_INTER_RAM2_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 + +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W; bitpos: [10]; default: 1; + * internal SRAM 1 force power up + */ + +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (RTC_CNTL_INTER_RAM1_FORCE_PU_V << RTC_CNTL_INTER_RAM1_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 + +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W; bitpos: [9]; default: 0; + * internal SRAM 1 force power down + */ + +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (RTC_CNTL_INTER_RAM1_FORCE_PD_V << RTC_CNTL_INTER_RAM1_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 + +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W; bitpos: [8]; default: 1; + * internal SRAM 0 force power up + */ + +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (RTC_CNTL_INTER_RAM0_FORCE_PU_V << RTC_CNTL_INTER_RAM0_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 + +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W; bitpos: [7]; default: 0; + * internal SRAM 0 force power down + */ + +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (RTC_CNTL_INTER_RAM0_FORCE_PD_V << RTC_CNTL_INTER_RAM0_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 + +/* RTC_CNTL_ROM0_FORCE_PU : R/W; bitpos: [6]; default: 1; + * ROM force power up + */ + +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (RTC_CNTL_ROM0_FORCE_PU_V << RTC_CNTL_ROM0_FORCE_PU_S) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x00000001 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 + +/* RTC_CNTL_ROM0_FORCE_PD : R/W; bitpos: [5]; default: 0; + * ROM force power down + */ + +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (RTC_CNTL_ROM0_FORCE_PD_V << RTC_CNTL_ROM0_FORCE_PD_S) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x00000001 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 + +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; + * memories in digital core force no PD in sleep + */ + +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (RTC_CNTL_LSLP_MEM_FORCE_PU_V << RTC_CNTL_LSLP_MEM_FORCE_PU_S) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x00000001 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 + +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; + * memories in digital core force PD in sleep + */ + +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (RTC_CNTL_LSLP_MEM_FORCE_PD_V << RTC_CNTL_LSLP_MEM_FORCE_PD_S) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x00000001 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +/* RTC_CNTL_DIG_ISO_REG register + * configure ISO of digital core + */ + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x90) + +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W; bitpos: [31]; default: 1; + * digital core force no ISO + */ + +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (RTC_CNTL_DG_WRAP_FORCE_NOISO_V << RTC_CNTL_DG_WRAP_FORCE_NOISO_S) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 + +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W; bitpos: [30]; default: 0; + * digital core force ISO + */ + +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (RTC_CNTL_DG_WRAP_FORCE_ISO_V << RTC_CNTL_DG_WRAP_FORCE_ISO_S) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 + +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W; bitpos: [29]; default: 1; + * wifi force no ISO + */ + +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (RTC_CNTL_WIFI_FORCE_NOISO_V << RTC_CNTL_WIFI_FORCE_NOISO_S) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 + +/* RTC_CNTL_WIFI_FORCE_ISO : R/W; bitpos: [28]; default: 0; + * wifi force ISO + */ + +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (RTC_CNTL_WIFI_FORCE_ISO_V << RTC_CNTL_WIFI_FORCE_ISO_S) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 + +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W; bitpos: [27]; default: 1; + * internal SRAM 4 force no ISO + */ + +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (RTC_CNTL_INTER_RAM4_FORCE_NOISO_V << RTC_CNTL_INTER_RAM4_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 + +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W; bitpos: [26]; default: 0; + * internal SRAM 4 force ISO + */ + +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (RTC_CNTL_INTER_RAM4_FORCE_ISO_V << RTC_CNTL_INTER_RAM4_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 + +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W; bitpos: [25]; default: 1; + * internal SRAM 3 force no ISO + */ + +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (RTC_CNTL_INTER_RAM3_FORCE_NOISO_V << RTC_CNTL_INTER_RAM3_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 + +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W; bitpos: [24]; default: 0; + * internal SRAM 3 force ISO + */ + +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (RTC_CNTL_INTER_RAM3_FORCE_ISO_V << RTC_CNTL_INTER_RAM3_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 + +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W; bitpos: [23]; default: 1; + * internal SRAM 2 force no ISO + */ + +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (RTC_CNTL_INTER_RAM2_FORCE_NOISO_V << RTC_CNTL_INTER_RAM2_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 + +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W; bitpos: [22]; default: 0; + * internal SRAM 2 force ISO + */ + +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (RTC_CNTL_INTER_RAM2_FORCE_ISO_V << RTC_CNTL_INTER_RAM2_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 + +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W; bitpos: [21]; default: 1; + * internal SRAM 1 force no ISO + */ + +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (RTC_CNTL_INTER_RAM1_FORCE_NOISO_V << RTC_CNTL_INTER_RAM1_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 + +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W; bitpos: [20]; default: 0; + * internal SRAM 1 force ISO + */ + +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (RTC_CNTL_INTER_RAM1_FORCE_ISO_V << RTC_CNTL_INTER_RAM1_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 + +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W; bitpos: [19]; default: 1; + * internal SRAM 0 force no ISO + */ + +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (RTC_CNTL_INTER_RAM0_FORCE_NOISO_V << RTC_CNTL_INTER_RAM0_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 + +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W; bitpos: [18]; default: 0; + * internal SRAM 0 force ISO + */ + +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (RTC_CNTL_INTER_RAM0_FORCE_ISO_V << RTC_CNTL_INTER_RAM0_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 + +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W; bitpos: [17]; default: 1; + * ROM force no ISO + */ + +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (RTC_CNTL_ROM0_FORCE_NOISO_V << RTC_CNTL_ROM0_FORCE_NOISO_S) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 + +/* RTC_CNTL_ROM0_FORCE_ISO : R/W; bitpos: [16]; default: 0; + * ROM force ISO + */ + +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (RTC_CNTL_ROM0_FORCE_ISO_V << RTC_CNTL_ROM0_FORCE_ISO_S) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 + +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W; bitpos: [15]; default: 0; + * digital pad force hold + */ + +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (RTC_CNTL_DG_PAD_FORCE_HOLD_V << RTC_CNTL_DG_PAD_FORCE_HOLD_S) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x00000001 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 + +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W; bitpos: [14]; default: 1; + * digital pad force un-hold + */ + +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (RTC_CNTL_DG_PAD_FORCE_UNHOLD_V << RTC_CNTL_DG_PAD_FORCE_UNHOLD_S) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x00000001 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 + +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W; bitpos: [13]; default: 0; + * digital pad force ISO + */ + +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (RTC_CNTL_DG_PAD_FORCE_ISO_V << RTC_CNTL_DG_PAD_FORCE_ISO_S) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 + +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W; bitpos: [12]; default: 1; + * digital pad force no ISO + */ + +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (RTC_CNTL_DG_PAD_FORCE_NOISO_V << RTC_CNTL_DG_PAD_FORCE_NOISO_S) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 + +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W; bitpos: [11]; default: 0; + * digital pad enable auto-hold + */ + +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (RTC_CNTL_DG_PAD_AUTOHOLD_EN_V << RTC_CNTL_DG_PAD_AUTOHOLD_EN_S) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x00000001 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 + +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO; bitpos: [10]; default: 0; + * wtite only register to clear digital pad auto-hold + */ + +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V << RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x00000001 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 + +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO; bitpos: [9]; default: 0; + * read only register to indicate digital pad auto-hold status + */ + +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (RTC_CNTL_DG_PAD_AUTOHOLD_V << RTC_CNTL_DG_PAD_AUTOHOLD_S) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x00000001 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 + +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W; bitpos: [8]; default: 0; */ + +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (RTC_CNTL_DIG_ISO_FORCE_ON_V << RTC_CNTL_DIG_ISO_FORCE_ON_S) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x00000001 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 + +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W; bitpos: [7]; default: 0; */ + +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (RTC_CNTL_DIG_ISO_FORCE_OFF_V << RTC_CNTL_DIG_ISO_FORCE_OFF_S) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x00000001 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +/* RTC_CNTL_WDTCONFIG0_REG register + * configure rtc watch dog register + */ + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x94) + +/* RTC_CNTL_WDT_EN : R/W; bitpos: [31]; default: 0; + * enable rtc wdt + */ + +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (RTC_CNTL_WDT_EN_V << RTC_CNTL_WDT_EN_S) +#define RTC_CNTL_WDT_EN_V 0x00000001 +#define RTC_CNTL_WDT_EN_S 31 + +/* RTC_CNTL_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en + * 4: RTC reset stage en + */ + +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M (RTC_CNTL_WDT_STG0_V << RTC_CNTL_WDT_STG0_S) +#define RTC_CNTL_WDT_STG0_V 0x00000007 +#define RTC_CNTL_WDT_STG0_S 28 + +/* RTC_CNTL_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en + * 4: RTC reset stage en + */ + +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M (RTC_CNTL_WDT_STG1_V << RTC_CNTL_WDT_STG1_S) +#define RTC_CNTL_WDT_STG1_V 0x00000007 +#define RTC_CNTL_WDT_STG1_S 25 + +/* RTC_CNTL_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en + * 4: RTC reset stage en + */ + +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M (RTC_CNTL_WDT_STG2_V << RTC_CNTL_WDT_STG2_S) +#define RTC_CNTL_WDT_STG2_V 0x00000007 +#define RTC_CNTL_WDT_STG2_S 22 + +/* RTC_CNTL_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en + * 4: RTC reset stage en + */ + +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M (RTC_CNTL_WDT_STG3_V << RTC_CNTL_WDT_STG3_S) +#define RTC_CNTL_WDT_STG3_V 0x00000007 +#define RTC_CNTL_WDT_STG3_S 19 + +/* RTC_CNTL_WDT_STGX : + * description: stage action selection values + */ + +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * CPU reset counter length + */ + +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M (RTC_CNTL_WDT_CPU_RESET_LENGTH_V << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 + +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * system reset counter length + */ + +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M (RTC_CNTL_WDT_SYS_RESET_LENGTH_V << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 + +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * enable WDT in flash boot + */ + +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V << RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x00000001 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 + +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * enable WDT reset PRO CPU + */ + +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (RTC_CNTL_WDT_PROCPU_RESET_EN_V << RTC_CNTL_WDT_PROCPU_RESET_EN_S) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x00000001 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 + +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * enable WDT reset APP CPU + */ + +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (RTC_CNTL_WDT_APPCPU_RESET_EN_V << RTC_CNTL_WDT_APPCPU_RESET_EN_S) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x00000001 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 + +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * pause WDT in sleep + */ + +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (RTC_CNTL_WDT_PAUSE_IN_SLP_V << RTC_CNTL_WDT_PAUSE_IN_SLP_S) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x00000001 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 + +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; + * wdt reset whole chip enable + */ + +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (RTC_CNTL_WDT_CHIP_RESET_EN_V << RTC_CNTL_WDT_CHIP_RESET_EN_S) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x00000001 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 + +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20; + * chip reset siginal pulse width + */ + +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M (RTC_CNTL_WDT_CHIP_RESET_WIDTH_V << RTC_CNTL_WDT_CHIP_RESET_WIDTH_S) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +/* RTC_CNTL_WDTCONFIG1_REG register + * Configure hold time of rtc wdt at level1 + */ + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x98) + +/* RTC_CNTL_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * Configure hold time of rtc wdt at level1 + */ + +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M (RTC_CNTL_WDT_STG0_HOLD_V << RTC_CNTL_WDT_STG0_HOLD_S) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +/* RTC_CNTL_WDTCONFIG2_REG register + * Configure hold time of rtc wdt at level2 + */ + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x9c) + +/* RTC_CNTL_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * Configure hold time of rtc wdt at level2 + */ + +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M (RTC_CNTL_WDT_STG1_HOLD_V << RTC_CNTL_WDT_STG1_HOLD_S) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +/* RTC_CNTL_WDTCONFIG3_REG register + * Configure hold time of rtc wdt at level3 + */ + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xa0) + +/* RTC_CNTL_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * Configure hold time of rtc wdt at level3 + */ + +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M (RTC_CNTL_WDT_STG2_HOLD_V << RTC_CNTL_WDT_STG2_HOLD_S) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +/* RTC_CNTL_WDTCONFIG4_REG register + * Configure hold time of rtc wdt at level4 + */ + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xa4) + +/* RTC_CNTL_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * Configure hold time of rtc wdt at level4 + */ + +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M (RTC_CNTL_WDT_STG3_HOLD_V << RTC_CNTL_WDT_STG3_HOLD_S) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +/* RTC_CNTL_WDTFEED_REG register + * feed rtc wdt by sw + */ + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa8) + +/* RTC_CNTL_WDT_FEED : WO; bitpos: [31]; default: 0; + * Set 1 to feed rtc wdt + */ + +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (RTC_CNTL_WDT_FEED_V << RTC_CNTL_WDT_FEED_S) +#define RTC_CNTL_WDT_FEED_V 0x00000001 +#define RTC_CNTL_WDT_FEED_S 31 + +/* RTC_CNTL_WDTWPROTECT_REG register + * configure rtc wdt write protect + */ + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xac) + +/* RTC_CNTL_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * wdt_wprotectn + */ + +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M (RTC_CNTL_WDT_WKEY_V << RTC_CNTL_WDT_WKEY_S) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +/* RTC_CNTL_SWD_CONF_REG register + * configure super watch dog + */ + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xb0) + +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W; bitpos: [31]; default: 0; + * automatically feed swd when int comes + */ + +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (RTC_CNTL_SWD_AUTO_FEED_EN_V << RTC_CNTL_SWD_AUTO_FEED_EN_S) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x00000001 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 + +/* RTC_CNTL_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * disabel SWD + */ + +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (RTC_CNTL_SWD_DISABLE_V << RTC_CNTL_SWD_DISABLE_S) +#define RTC_CNTL_SWD_DISABLE_V 0x00000001 +#define RTC_CNTL_SWD_DISABLE_S 30 + +/* RTC_CNTL_SWD_FEED : WO; bitpos: [29]; default: 0; + * Sw feed swd + */ + +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (RTC_CNTL_SWD_FEED_V << RTC_CNTL_SWD_FEED_S) +#define RTC_CNTL_SWD_FEED_V 0x00000001 +#define RTC_CNTL_SWD_FEED_S 29 + +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO; bitpos: [28]; default: 0; + * reset swd reset flag + */ + +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (RTC_CNTL_SWD_RST_FLAG_CLR_V << RTC_CNTL_SWD_RST_FLAG_CLR_S) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x00000001 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 + +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W; bitpos: [27:18]; default: 300; + * adjust signal width send to swd + */ + +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M (RTC_CNTL_SWD_SIGNAL_WIDTH_V << RTC_CNTL_SWD_SIGNAL_WIDTH_S) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 + +/* RTC_CNTL_SWD_FEED_INT : RO; bitpos: [1]; default: 0; + * swd interrupt for feeding + */ + +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (RTC_CNTL_SWD_FEED_INT_V << RTC_CNTL_SWD_FEED_INT_S) +#define RTC_CNTL_SWD_FEED_INT_V 0x00000001 +#define RTC_CNTL_SWD_FEED_INT_S 1 + +/* RTC_CNTL_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * swd reset flag + */ + +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (RTC_CNTL_SWD_RESET_FLAG_V << RTC_CNTL_SWD_RESET_FLAG_S) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x00000001 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +/* RTC_CNTL_SWD_WPROTECT_REG register + * configure super watch dog write protect + */ + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xb4) + +/* RTC_CNTL_SWD_WKEY : R/W; bitpos: [31:0]; default: 2401055018; + * swd write protect + */ + +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M (RTC_CNTL_SWD_WKEY_V << RTC_CNTL_SWD_WKEY_S) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +/* RTC_CNTL_SW_CPU_STALL_REG register + * configure cpu stall register + */ + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xb8) + +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W; bitpos: [31:26]; default: 0; + * enable cpu enter stall status by sw + */ + +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M (RTC_CNTL_SW_STALL_PROCPU_C1_V << RTC_CNTL_SW_STALL_PROCPU_C1_S) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 + +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W; bitpos: [25:20]; default: 0; + * {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will + * stall APP CPU + */ + +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M (RTC_CNTL_SW_STALL_APPCPU_C1_V << RTC_CNTL_SW_STALL_APPCPU_C1_S) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +/* RTC_CNTL_STORE4_REG register + * reservation register4 + */ + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xbc) + +/* RTC_CNTL_SCRATCH4 : R/W; bitpos: [31:0]; default: 0; + * reservation register4 + */ + +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M (RTC_CNTL_SCRATCH4_V << RTC_CNTL_SCRATCH4_S) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +/* RTC_CNTL_STORE5_REG register + * reservation register5 + */ + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xc0) + +/* RTC_CNTL_SCRATCH5 : R/W; bitpos: [31:0]; default: 0; + * reservation register5 + */ + +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M (RTC_CNTL_SCRATCH5_V << RTC_CNTL_SCRATCH5_S) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +/* RTC_CNTL_STORE6_REG register + * reservation register6 + */ + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xc4) + +/* RTC_CNTL_SCRATCH6 : R/W; bitpos: [31:0]; default: 0; + * reservation register6 + */ + +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M (RTC_CNTL_SCRATCH6_V << RTC_CNTL_SCRATCH6_S) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +/* RTC_CNTL_STORE7_REG register + * reservation register7 + */ + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xc8) + +/* RTC_CNTL_SCRATCH7 : R/W; bitpos: [31:0]; default: 0; + * reservation register7 + */ + +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M (RTC_CNTL_SCRATCH7_V << RTC_CNTL_SCRATCH7_S) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +/* RTC_CNTL_LOW_POWER_ST_REG register + * rtc main state machine status + */ + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xcc) + +/* RTC_CNTL_MAIN_STATE : RO; bitpos: [31:28]; default: 0; + * rtc main state machine status + */ + +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M (RTC_CNTL_MAIN_STATE_V << RTC_CNTL_MAIN_STATE_S) +#define RTC_CNTL_MAIN_STATE_V 0x0000000F +#define RTC_CNTL_MAIN_STATE_S 28 + +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO; bitpos: [27]; default: 0; + * rtc main state machine is in idle state + */ + +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (RTC_CNTL_MAIN_STATE_IN_IDLE_V << RTC_CNTL_MAIN_STATE_IN_IDLE_S) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 + +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO; bitpos: [26]; default: 0; + * rtc main state machine is in sleep state + */ + +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (RTC_CNTL_MAIN_STATE_IN_SLP_V << RTC_CNTL_MAIN_STATE_IN_SLP_S) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO; bitpos: [25]; default: 0; + * rtc main state machine is in wait xtal state + */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V << RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO; bitpos: [24]; default: 0; + * rtc main state machine is in wait pll state + */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V << RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO; bitpos: [23]; default: 0; + * rtc main state machine is in wait 8m state + */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V << RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 + +/* RTC_CNTL_IN_LOW_POWER_STATE : RO; bitpos: [22]; default: 0; + * rtc main state machine is in the states of low power + */ + +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (RTC_CNTL_IN_LOW_POWER_STATE_V << RTC_CNTL_IN_LOW_POWER_STATE_S) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x00000001 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 + +/* RTC_CNTL_IN_WAKEUP_STATE : RO; bitpos: [21]; default: 0; + * rtc main state machine is in the states of wakeup process + */ + +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (RTC_CNTL_IN_WAKEUP_STATE_V << RTC_CNTL_IN_WAKEUP_STATE_S) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x00000001 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 + +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO; bitpos: [20]; default: 0; + * rtc main state machine has been waited for some cycles + */ + +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (RTC_CNTL_MAIN_STATE_WAIT_END_V << RTC_CNTL_MAIN_STATE_WAIT_END_S) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 + +/* RTC_CNTL_RDY_FOR_WAKEUP : RO; bitpos: [19]; default: 0; + * rtc is ready to receive wake up trigger from wake up source + */ + +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (RTC_CNTL_RDY_FOR_WAKEUP_V << RTC_CNTL_RDY_FOR_WAKEUP_S) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x00000001 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 + +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO; bitpos: [18]; default: 0; + * rtc main state machine is in states that pll should be running + */ + +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (RTC_CNTL_MAIN_STATE_PLL_ON_V << RTC_CNTL_MAIN_STATE_PLL_ON_S) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 + +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO; bitpos: [17]; default: 0; + * no use any more + */ + +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (RTC_CNTL_MAIN_STATE_XTAL_ISO_V << RTC_CNTL_MAIN_STATE_XTAL_ISO_S) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 + +/* RTC_CNTL_COCPU_STATE_DONE : RO; bitpos: [16]; default: 0; + * ulp/cocpu is done + */ + +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (RTC_CNTL_COCPU_STATE_DONE_V << RTC_CNTL_COCPU_STATE_DONE_S) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x00000001 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 + +/* RTC_CNTL_COCPU_STATE_SLP : RO; bitpos: [15]; default: 0; + * ulp/cocpu is in sleep state + */ + +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (RTC_CNTL_COCPU_STATE_SLP_V << RTC_CNTL_COCPU_STATE_SLP_S) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x00000001 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 + +/* RTC_CNTL_COCPU_STATE_SWITCH : RO; bitpos: [14]; default: 0; + * ulp/cocpu is about to working. Switch rtc main state + */ + +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (RTC_CNTL_COCPU_STATE_SWITCH_V << RTC_CNTL_COCPU_STATE_SWITCH_S) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x00000001 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 + +/* RTC_CNTL_COCPU_STATE_START : RO; bitpos: [13]; default: 0; + * ulp/cocpu should start to work + */ + +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (RTC_CNTL_COCPU_STATE_START_V << RTC_CNTL_COCPU_STATE_START_S) +#define RTC_CNTL_COCPU_STATE_START_V 0x00000001 +#define RTC_CNTL_COCPU_STATE_START_S 13 + +/* RTC_CNTL_TOUCH_STATE_DONE : RO; bitpos: [12]; default: 0; + * touch is done + */ + +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (RTC_CNTL_TOUCH_STATE_DONE_V << RTC_CNTL_TOUCH_STATE_DONE_S) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x00000001 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 + +/* RTC_CNTL_TOUCH_STATE_SLP : RO; bitpos: [11]; default: 0; + * touch is in sleep state + */ + +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (RTC_CNTL_TOUCH_STATE_SLP_V << RTC_CNTL_TOUCH_STATE_SLP_S) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x00000001 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 + +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO; bitpos: [10]; default: 0; + * touch is about to working. Switch rtc main state + */ + +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (RTC_CNTL_TOUCH_STATE_SWITCH_V << RTC_CNTL_TOUCH_STATE_SWITCH_S) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x00000001 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 + +/* RTC_CNTL_TOUCH_STATE_START : RO; bitpos: [9]; default: 0; + * touch should start to work + */ + +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (RTC_CNTL_TOUCH_STATE_START_V << RTC_CNTL_TOUCH_STATE_START_S) +#define RTC_CNTL_TOUCH_STATE_START_V 0x00000001 +#define RTC_CNTL_TOUCH_STATE_START_S 9 + +/* RTC_CNTL_XPD_DIG : RO; bitpos: [8]; default: 0; + * digital wrap power down + */ + +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (RTC_CNTL_XPD_DIG_V << RTC_CNTL_XPD_DIG_S) +#define RTC_CNTL_XPD_DIG_V 0x00000001 +#define RTC_CNTL_XPD_DIG_S 8 + +/* RTC_CNTL_DIG_ISO : RO; bitpos: [7]; default: 0; + * digital wrap iso + */ + +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (RTC_CNTL_DIG_ISO_V << RTC_CNTL_DIG_ISO_S) +#define RTC_CNTL_DIG_ISO_V 0x00000001 +#define RTC_CNTL_DIG_ISO_S 7 + +/* RTC_CNTL_XPD_WIFI : RO; bitpos: [6]; default: 0; + * wifi wrap power down + */ + +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (RTC_CNTL_XPD_WIFI_V << RTC_CNTL_XPD_WIFI_S) +#define RTC_CNTL_XPD_WIFI_V 0x00000001 +#define RTC_CNTL_XPD_WIFI_S 6 + +/* RTC_CNTL_WIFI_ISO : RO; bitpos: [5]; default: 0; + * wifi iso + */ + +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (RTC_CNTL_WIFI_ISO_V << RTC_CNTL_WIFI_ISO_S) +#define RTC_CNTL_WIFI_ISO_V 0x00000001 +#define RTC_CNTL_WIFI_ISO_S 5 + +/* RTC_CNTL_XPD_RTC_PERI : RO; bitpos: [4]; default: 0; + * rtc peripheral power down + */ + +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (RTC_CNTL_XPD_RTC_PERI_V << RTC_CNTL_XPD_RTC_PERI_S) +#define RTC_CNTL_XPD_RTC_PERI_V 0x00000001 +#define RTC_CNTL_XPD_RTC_PERI_S 4 + +/* RTC_CNTL_PERI_ISO : RO; bitpos: [3]; default: 0; + * rtc peripheral iso + */ + +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (RTC_CNTL_PERI_ISO_V << RTC_CNTL_PERI_ISO_S) +#define RTC_CNTL_PERI_ISO_V 0x00000001 +#define RTC_CNTL_PERI_ISO_S 3 + +/* RTC_CNTL_XPD_DIG_DCDC : RO; bitpos: [2]; default: 0; + * External DCDC power down + */ + +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (RTC_CNTL_XPD_DIG_DCDC_V << RTC_CNTL_XPD_DIG_DCDC_S) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x00000001 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 + +/* RTC_CNTL_XPD_ROM0 : RO; bitpos: [0]; default: 0; + * rom0 power down + */ + +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (RTC_CNTL_XPD_ROM0_V << RTC_CNTL_XPD_ROM0_S) +#define RTC_CNTL_XPD_ROM0_V 0x00000001 +#define RTC_CNTL_XPD_ROM0_S 0 + +/* RTC_CNTL_DIAG0_REG register + * debug register + */ + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xd0) + +/* RTC_CNTL_LOW_POWER_DIAG1 : RO; bitpos: [31:0]; default: 0; */ + +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M (RTC_CNTL_LOW_POWER_DIAG1_V << RTC_CNTL_LOW_POWER_DIAG1_S) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +/* RTC_CNTL_PAD_HOLD_REG register + * configure rtc pad hold register + */ + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xd4) + +/* RTC_CNTL_PAD21_HOLD : R/W; bitpos: [21]; default: 0; + * set rtc_pad21_hold + */ + +#define RTC_CNTL_PAD21_HOLD (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_M (RTC_CNTL_PAD21_HOLD_V << RTC_CNTL_PAD21_HOLD_S) +#define RTC_CNTL_PAD21_HOLD_V 0x00000001 +#define RTC_CNTL_PAD21_HOLD_S 21 + +/* RTC_CNTL_PAD20_HOLD : R/W; bitpos: [20]; default: 0; + * set rtc_pad20_hold + */ + +#define RTC_CNTL_PAD20_HOLD (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_M (RTC_CNTL_PAD20_HOLD_V << RTC_CNTL_PAD20_HOLD_S) +#define RTC_CNTL_PAD20_HOLD_V 0x00000001 +#define RTC_CNTL_PAD20_HOLD_S 20 + +/* RTC_CNTL_PAD19_HOLD : R/W; bitpos: [19]; default: 0; + * set rtc_pad19_hold + */ + +#define RTC_CNTL_PAD19_HOLD (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_M (RTC_CNTL_PAD19_HOLD_V << RTC_CNTL_PAD19_HOLD_S) +#define RTC_CNTL_PAD19_HOLD_V 0x00000001 +#define RTC_CNTL_PAD19_HOLD_S 19 + +/* RTC_CNTL_PDAC2_HOLD : R/W; bitpos: [18]; default: 0; + * set pdac2_hold + */ + +#define RTC_CNTL_PDAC2_HOLD (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_M (RTC_CNTL_PDAC2_HOLD_V << RTC_CNTL_PDAC2_HOLD_S) +#define RTC_CNTL_PDAC2_HOLD_V 0x00000001 +#define RTC_CNTL_PDAC2_HOLD_S 18 + +/* RTC_CNTL_PDAC1_HOLD : R/W; bitpos: [17]; default: 0; + * set pdac1_hold + */ + +#define RTC_CNTL_PDAC1_HOLD (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_M (RTC_CNTL_PDAC1_HOLD_V << RTC_CNTL_PDAC1_HOLD_S) +#define RTC_CNTL_PDAC1_HOLD_V 0x00000001 +#define RTC_CNTL_PDAC1_HOLD_S 17 + +/* RTC_CNTL_X32N_HOLD : R/W; bitpos: [16]; default: 0; + * set x32n_hold + */ + +#define RTC_CNTL_X32N_HOLD (BIT(16)) +#define RTC_CNTL_X32N_HOLD_M (RTC_CNTL_X32N_HOLD_V << RTC_CNTL_X32N_HOLD_S) +#define RTC_CNTL_X32N_HOLD_V 0x00000001 +#define RTC_CNTL_X32N_HOLD_S 16 + +/* RTC_CNTL_X32P_HOLD : R/W; bitpos: [15]; default: 0; + * Set x32p_hold + */ + +#define RTC_CNTL_X32P_HOLD (BIT(15)) +#define RTC_CNTL_X32P_HOLD_M (RTC_CNTL_X32P_HOLD_V << RTC_CNTL_X32P_HOLD_S) +#define RTC_CNTL_X32P_HOLD_V 0x00000001 +#define RTC_CNTL_X32P_HOLD_S 15 + +/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W; bitpos: [14]; default: 0; + * set touch_pad14_hold + */ + +#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_M (RTC_CNTL_TOUCH_PAD14_HOLD_V << RTC_CNTL_TOUCH_PAD14_HOLD_S) +#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 + +/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W; bitpos: [13]; default: 0; + * set touch_pad13_hold + */ + +#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_M (RTC_CNTL_TOUCH_PAD13_HOLD_V << RTC_CNTL_TOUCH_PAD13_HOLD_S) +#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 + +/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W; bitpos: [12]; default: 0; + * set touch_pad12_hold + */ + +#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_M (RTC_CNTL_TOUCH_PAD12_HOLD_V << RTC_CNTL_TOUCH_PAD12_HOLD_S) +#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 + +/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W; bitpos: [11]; default: 0; + * set touch_pad11_hold + */ + +#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_M (RTC_CNTL_TOUCH_PAD11_HOLD_V << RTC_CNTL_TOUCH_PAD11_HOLD_S) +#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 + +/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W; bitpos: [10]; default: 0; + * set touch_pad10_hold + */ + +#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_M (RTC_CNTL_TOUCH_PAD10_HOLD_V << RTC_CNTL_TOUCH_PAD10_HOLD_S) +#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 + +/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W; bitpos: [9]; default: 0; + * set touch_pad9_hold + */ + +#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_M (RTC_CNTL_TOUCH_PAD9_HOLD_V << RTC_CNTL_TOUCH_PAD9_HOLD_S) +#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 + +/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W; bitpos: [8]; default: 0; + * set touch_pad8_hold + */ + +#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_M (RTC_CNTL_TOUCH_PAD8_HOLD_V << RTC_CNTL_TOUCH_PAD8_HOLD_S) +#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 + +/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W; bitpos: [7]; default: 0; + * set touch_pad7_hold + */ + +#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_M (RTC_CNTL_TOUCH_PAD7_HOLD_V << RTC_CNTL_TOUCH_PAD7_HOLD_S) +#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 + +/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W; bitpos: [6]; default: 0; + * set touch_pad6_hold + */ + +#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_M (RTC_CNTL_TOUCH_PAD6_HOLD_V << RTC_CNTL_TOUCH_PAD6_HOLD_S) +#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 + +/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W; bitpos: [5]; default: 0; + * set touch_pad5_hold + */ + +#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_M (RTC_CNTL_TOUCH_PAD5_HOLD_V << RTC_CNTL_TOUCH_PAD5_HOLD_S) +#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 + +/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W; bitpos: [4]; default: 0; + * set touch_pad4_hold + */ + +#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_M (RTC_CNTL_TOUCH_PAD4_HOLD_V << RTC_CNTL_TOUCH_PAD4_HOLD_S) +#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 + +/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W; bitpos: [3]; default: 0; + * set touch_pad3_hold + */ + +#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_M (RTC_CNTL_TOUCH_PAD3_HOLD_V << RTC_CNTL_TOUCH_PAD3_HOLD_S) +#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 + +/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W; bitpos: [2]; default: 0; + * set touch_pad2_hold + */ + +#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_M (RTC_CNTL_TOUCH_PAD2_HOLD_V << RTC_CNTL_TOUCH_PAD2_HOLD_S) +#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 + +/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W; bitpos: [1]; default: 0; + * set touch_pad1_hold + */ + +#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_M (RTC_CNTL_TOUCH_PAD1_HOLD_V << RTC_CNTL_TOUCH_PAD1_HOLD_S) +#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 + +/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W; bitpos: [0]; default: 0; + * set touch_pad0_hold + */ + +#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_M (RTC_CNTL_TOUCH_PAD0_HOLD_V << RTC_CNTL_TOUCH_PAD0_HOLD_S) +#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 + +/* RTC_CNTL_DIG_PAD_HOLD_REG register + * configure digital pad hold register + */ + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xd8) + +/* RTC_CNTL_DIG_PAD_HOLD : R/W; bitpos: [31:0]; default: 0; + * Hold GPIO21~GPIO45 base on bitmap + */ + +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M (RTC_CNTL_DIG_PAD_HOLD_V << RTC_CNTL_DIG_PAD_HOLD_S) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +/* RTC_CNTL_EXT_WAKEUP1_REG register + * configure EXT1 wakeup register + */ + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xdc) + +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO; bitpos: [22]; default: 0; + * clear ext wakeup1 status + */ + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V << RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x00000001 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 + +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W; bitpos: [21:0]; default: 0; + * Bitmap to select RTC pads for ext wakeup1 + */ + +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M (RTC_CNTL_EXT_WAKEUP1_SEL_V << RTC_CNTL_EXT_WAKEUP1_SEL_S) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +/* RTC_CNTL_EXT_WAKEUP1_STATUS_REG register + * EXT1 wakeup source register + */ + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xe0) + +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO; bitpos: [21:0]; default: 0; + * ext wakeup1 status + */ + +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M (RTC_CNTL_EXT_WAKEUP1_STATUS_V << RTC_CNTL_EXT_WAKEUP1_STATUS_S) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +/* RTC_CNTL_BROWN_OUT_REG register + * configure brownout register + */ + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xe4) + +/* RTC_CNTL_BROWN_OUT_DET : RO; bitpos: [31]; default: 0; + * status of brown detcet signal + */ + +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (RTC_CNTL_BROWN_OUT_DET_V << RTC_CNTL_BROWN_OUT_DET_S) +#define RTC_CNTL_BROWN_OUT_DET_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_DET_S 31 + +/* RTC_CNTL_BROWN_OUT_ENA : R/W; bitpos: [30]; default: 0; + * enable brown out + */ + +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (RTC_CNTL_BROWN_OUT_ENA_V << RTC_CNTL_BROWN_OUT_ENA_S) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 + +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO; bitpos: [29]; default: 0; + * clear brown out counter + */ + +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (RTC_CNTL_BROWN_OUT_CNT_CLR_V << RTC_CNTL_BROWN_OUT_CNT_CLR_S) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 + +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W; bitpos: [27]; default: 0; + * 1: chip reset 0: sys_reset + */ + +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (RTC_CNTL_BROWN_OUT_RST_SEL_V << RTC_CNTL_BROWN_OUT_RST_SEL_S) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 + +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W; bitpos: [26]; default: 0; + * enable brown out reset + */ + +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (RTC_CNTL_BROWN_OUT_RST_ENA_V << RTC_CNTL_BROWN_OUT_RST_ENA_S) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 + +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W; bitpos: [25:16]; default: 1023; + * brown out reset wait cycles + */ + +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M (RTC_CNTL_BROWN_OUT_RST_WAIT_V << RTC_CNTL_BROWN_OUT_RST_WAIT_S) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 + +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W; bitpos: [15]; default: 0; + * enable power down RF when brown out happens + */ + +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (RTC_CNTL_BROWN_OUT_PD_RF_ENA_V << RTC_CNTL_BROWN_OUT_PD_RF_ENA_S) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 + +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W; bitpos: [14]; default: 0; + * enable close flash when brown out happens + */ + +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V << RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 + +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W; bitpos: [13:4]; default: 767; + * brown out interrupt wait cycles + */ + +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M (RTC_CNTL_BROWN_OUT_INT_WAIT_V << RTC_CNTL_BROWN_OUT_INT_WAIT_S) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 + +/* RTC_CNTL_BROWN_OUT2_ENA : R/W; bitpos: [0]; default: 1; + * enable brown_out2 to start chip reset + */ + +#define RTC_CNTL_BROWN_OUT2_ENA (BIT(0)) +#define RTC_CNTL_BROWN_OUT2_ENA_M (RTC_CNTL_BROWN_OUT2_ENA_V << RTC_CNTL_BROWN_OUT2_ENA_S) +#define RTC_CNTL_BROWN_OUT2_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT2_ENA_S 0 + +/* RTC_CNTL_TIME_LOW1_REG register + * RTC timer1 low 32 bits + */ + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xe8) + +/* RTC_CNTL_TIMER_VALUE1_LOW : RO; bitpos: [31:0]; default: 0; + * RTC timer low 32 bits + */ + +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M (RTC_CNTL_TIMER_VALUE1_LOW_V << RTC_CNTL_TIMER_VALUE1_LOW_S) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +/* RTC_CNTL_TIME_HIGH1_REG register + * RTC timer1 high 16 bits + */ + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xec) + +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO; bitpos: [15:0]; default: 0; + * RTC timer high 16 bits + */ + +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M (RTC_CNTL_TIMER_VALUE1_HIGH_V << RTC_CNTL_TIMER_VALUE1_HIGH_S) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +/* RTC_CNTL_XTAL32K_CLK_FACTOR_REG register + * configure xtal32k backup fatcor register + */ + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xf0) + +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W; bitpos: [31:0]; default: 0; + * xtal 32k watch dog backup clock factor + */ + +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M (RTC_CNTL_XTAL32K_CLK_FACTOR_V << RTC_CNTL_XTAL32K_CLK_FACTOR_S) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +/* RTC_CNTL_XTAL32K_CONF_REG register + * configure xtal32k register + */ + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xf4) + +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W; bitpos: [31:28]; default: 0; + * if restarted xtal32k period is smaller than this it is regarded as stable + */ + +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M (RTC_CNTL_XTAL32K_STABLE_THRES_V << RTC_CNTL_XTAL32K_STABLE_THRES_S) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 + +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W; bitpos: [27:20]; default: 255; + * If no clock detected for this amount of time 32k is regarded as dead + */ + +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M (RTC_CNTL_XTAL32K_WDT_TIMEOUT_V << RTC_CNTL_XTAL32K_WDT_TIMEOUT_S) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 + +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W; bitpos: [19:4]; default: 0; + * cycles to wait to repower on xtal 32k + */ + +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M (RTC_CNTL_XTAL32K_RESTART_WAIT_V << RTC_CNTL_XTAL32K_RESTART_WAIT_S) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 + +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W; bitpos: [3:0]; default: 0; + * cycles to wait to return noral xtal 32k + */ + +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M (RTC_CNTL_XTAL32K_RETURN_WAIT_V << RTC_CNTL_XTAL32K_RETURN_WAIT_S) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +/* RTC_CNTL_USB_CONF_REG register + * configure usb control register + */ + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x11c) + +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W; bitpos: [18]; default: 0; */ + +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (RTC_CNTL_IO_MUX_RESET_DISABLE_V << RTC_CNTL_IO_MUX_RESET_DISABLE_S) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x00000001 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 + +/* RTC_CNTL_USB_RESET_DISABLE : R/W; bitpos: [17]; default: 0; */ + +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_M (RTC_CNTL_USB_RESET_DISABLE_V << RTC_CNTL_USB_RESET_DISABLE_S) +#define RTC_CNTL_USB_RESET_DISABLE_V 0x00000001 +#define RTC_CNTL_USB_RESET_DISABLE_S 17 + +/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W; bitpos: [16]; default: 0; */ + +#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (RTC_CNTL_USB_TX_EN_OVERRIDE_V << RTC_CNTL_USB_TX_EN_OVERRIDE_S) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x00000001 +#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 + +/* RTC_CNTL_USB_TX_EN : R/W; bitpos: [15]; default: 0; */ + +#define RTC_CNTL_USB_TX_EN (BIT(15)) +#define RTC_CNTL_USB_TX_EN_M (RTC_CNTL_USB_TX_EN_V << RTC_CNTL_USB_TX_EN_S) +#define RTC_CNTL_USB_TX_EN_V 0x00000001 +#define RTC_CNTL_USB_TX_EN_S 15 + +/* RTC_CNTL_USB_TXP : R/W; bitpos: [14]; default: 0; */ + +#define RTC_CNTL_USB_TXP (BIT(14)) +#define RTC_CNTL_USB_TXP_M (RTC_CNTL_USB_TXP_V << RTC_CNTL_USB_TXP_S) +#define RTC_CNTL_USB_TXP_V 0x00000001 +#define RTC_CNTL_USB_TXP_S 14 + +/* RTC_CNTL_USB_TXM : R/W; bitpos: [13]; default: 0; */ + +#define RTC_CNTL_USB_TXM (BIT(13)) +#define RTC_CNTL_USB_TXM_M (RTC_CNTL_USB_TXM_V << RTC_CNTL_USB_TXM_S) +#define RTC_CNTL_USB_TXM_V 0x00000001 +#define RTC_CNTL_USB_TXM_S 13 + +/* RTC_CNTL_USB_PAD_ENABLE : R/W; bitpos: [12]; default: 0; */ + +#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_M (RTC_CNTL_USB_PAD_ENABLE_V << RTC_CNTL_USB_PAD_ENABLE_S) +#define RTC_CNTL_USB_PAD_ENABLE_V 0x00000001 +#define RTC_CNTL_USB_PAD_ENABLE_S 12 + +/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W; bitpos: [11]; default: 0; */ + +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V << RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x00000001 +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 + +/* RTC_CNTL_USB_PULLUP_VALUE : R/W; bitpos: [10]; default: 0; */ + +#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_M (RTC_CNTL_USB_PULLUP_VALUE_V << RTC_CNTL_USB_PULLUP_VALUE_S) +#define RTC_CNTL_USB_PULLUP_VALUE_V 0x00000001 +#define RTC_CNTL_USB_PULLUP_VALUE_S 10 + +/* RTC_CNTL_USB_DM_PULLDOWN : R/W; bitpos: [9]; default: 0; */ + +#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_M (RTC_CNTL_USB_DM_PULLDOWN_V << RTC_CNTL_USB_DM_PULLDOWN_S) +#define RTC_CNTL_USB_DM_PULLDOWN_V 0x00000001 +#define RTC_CNTL_USB_DM_PULLDOWN_S 9 + +/* RTC_CNTL_USB_DM_PULLUP : R/W; bitpos: [8]; default: 0; */ + +#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_M (RTC_CNTL_USB_DM_PULLUP_V << RTC_CNTL_USB_DM_PULLUP_S) +#define RTC_CNTL_USB_DM_PULLUP_V 0x00000001 +#define RTC_CNTL_USB_DM_PULLUP_S 8 + +/* RTC_CNTL_USB_DP_PULLDOWN : R/W; bitpos: [7]; default: 0; */ + +#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_M (RTC_CNTL_USB_DP_PULLDOWN_V << RTC_CNTL_USB_DP_PULLDOWN_S) +#define RTC_CNTL_USB_DP_PULLDOWN_V 0x00000001 +#define RTC_CNTL_USB_DP_PULLDOWN_S 7 + +/* RTC_CNTL_USB_DP_PULLUP : R/W; bitpos: [6]; default: 0; */ + +#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_M (RTC_CNTL_USB_DP_PULLUP_V << RTC_CNTL_USB_DP_PULLUP_S) +#define RTC_CNTL_USB_DP_PULLUP_V 0x00000001 +#define RTC_CNTL_USB_DP_PULLUP_S 6 + +/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W; bitpos: [5]; default: 0; */ + +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (RTC_CNTL_USB_PAD_PULL_OVERRIDE_V << RTC_CNTL_USB_PAD_PULL_OVERRIDE_S) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x00000001 +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 + +/* RTC_CNTL_USB_VREF_OVERRIDE : R/W; bitpos: [4]; default: 0; */ + +#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_M (RTC_CNTL_USB_VREF_OVERRIDE_V << RTC_CNTL_USB_VREF_OVERRIDE_S) +#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x00000001 +#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 + +/* RTC_CNTL_USB_VREFL : R/W; bitpos: [3:2]; default: 0; */ + +#define RTC_CNTL_USB_VREFL 0x00000003 +#define RTC_CNTL_USB_VREFL_M (RTC_CNTL_USB_VREFL_V << RTC_CNTL_USB_VREFL_S) +#define RTC_CNTL_USB_VREFL_V 0x00000003 +#define RTC_CNTL_USB_VREFL_S 2 + +/* RTC_CNTL_USB_VREFH : R/W; bitpos: [1:0]; default: 0; */ + +#define RTC_CNTL_USB_VREFH 0x00000003 +#define RTC_CNTL_USB_VREFH_M (RTC_CNTL_USB_VREFH_V << RTC_CNTL_USB_VREFH_S) +#define RTC_CNTL_USB_VREFH_V 0x00000003 +#define RTC_CNTL_USB_VREFH_S 0 + +/* RTC_CNTL_SLP_REJECT_CAUSE_REG register + * sleep reject casue register + */ + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x124) + +/* RTC_CNTL_REJECT_CAUSE : RO; bitpos: [16:0]; default: 0; + * sleep reject cause + */ + +#define RTC_CNTL_REJECT_CAUSE 0x0001FFFF +#define RTC_CNTL_REJECT_CAUSE_M (RTC_CNTL_REJECT_CAUSE_V << RTC_CNTL_REJECT_CAUSE_S) +#define RTC_CNTL_REJECT_CAUSE_V 0x0001FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +/* RTC_CNTL_OPTION1_REG register + * configure rtc option + */ + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x128) + +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [0]; default: 0; + * force chip boot from download mode + */ + +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (RTC_CNTL_FORCE_DOWNLOAD_BOOT_V << RTC_CNTL_FORCE_DOWNLOAD_BOOT_S) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x00000001 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +/* RTC_CNTL_SLP_WAKEUP_CAUSE_REG register + * sleep wakeup cause state register + */ + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x12c) + +/* RTC_CNTL_WAKEUP_CAUSE : RO; bitpos: [16:0]; default: 0; + * sleep wakeup cause + */ + +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M (RTC_CNTL_WAKEUP_CAUSE_V << RTC_CNTL_WAKEUP_CAUSE_S) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +/* RTC_CNTL_DATE_REG register */ + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x138) + +/* RTC_CNTL_CNTL_DATE : R/W; bitpos: [27:0]; default: 26239377; */ + +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M (RTC_CNTL_CNTL_DATE_V << RTC_CNTL_CNTL_DATE_S) +#define RTC_CNTL_CNTL_DATE_V 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTC_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h new file mode 100644 index 00000000000..df560af5e27 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h @@ -0,0 +1,767 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "xtensa_attr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Bits */ + +#define BIT31 0x80000000 +#define BIT30 0x40000000 +#define BIT29 0x20000000 +#define BIT28 0x10000000 +#define BIT27 0x08000000 +#define BIT26 0x04000000 +#define BIT25 0x02000000 +#define BIT24 0x01000000 +#define BIT23 0x00800000 +#define BIT22 0x00400000 +#define BIT21 0x00200000 +#define BIT20 0x00100000 +#define BIT19 0x00080000 +#define BIT18 0x00040000 +#define BIT17 0x00020000 +#define BIT16 0x00010000 +#define BIT15 0x00008000 +#define BIT14 0x00004000 +#define BIT13 0x00002000 +#define BIT12 0x00001000 +#define BIT11 0x00000800 +#define BIT10 0x00000400 +#define BIT9 0x00000200 +#define BIT8 0x00000100 +#define BIT7 0x00000080 +#define BIT6 0x00000040 +#define BIT5 0x00000020 +#define BIT4 0x00000010 +#define BIT3 0x00000008 +#define BIT2 0x00000004 +#define BIT1 0x00000002 +#define BIT0 0x00000001 + +#define PRO_CPU_NUM (0) + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) /* Largest span of contiguous memory (DRAM or IRAM) in the address space */ + +/* Registers Operation */ + +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#define BIT(nr) (1UL << (nr)) + +/* Write value to register */ + +#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +/* Read value from register */ + +#define REG_READ(_r) (*(volatile uint32_t *)(_r)) + +/* Get bit or get bits from register */ + +#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) + +/* Set bit or set bits to register */ + +#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) + +/* Clear bit or clear bits of register */ + +#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) + +/* Set bits of register controlled by mask */ + +#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) + +/* Get field from register, + * used when _f is not left shifted by _f##_S + */ + +#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +/* Set field to register, + * used when _f is not left shifted by _f##_S + */ + +#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))) + +/* Set field value from a variable, + * used when _f is not left shifted by _f##_S + */ + +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +/* Get field value from a variable, + * used when _f is left shifted by _f##_S + */ + +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +/* Set field value to a variable, + * used when _f is not left shifted by _f##_S + */ + +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +/* Set field value to a variable, + * used when _f is left shifted by _f##_S + */ + +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +/* Generate a value from a field value, + * used when _f is not left shifted by _f##_S + */ + +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +/* Generate a value from a field value, + * used when _f is left shifted by _f##_S + */ + +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +/* Read value from register */ + +#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) + +/* Write value to register */ + +#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) + +/* Clear bits of register controlled by mask */ + +#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) + +/* Set bits of register controlled by mask */ + +#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) + +/* Get bits of register controlled by mask */ + +#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) + +/* Get bits of register controlled by highest bit and lowest bit */ + +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +/* Set bits of register controlled by mask and shift */ + +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) + +/* Get field of register */ + +#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) + +/* Extract the field from the register and shift it to avoid wrong reading */ + +#define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S)) + +/* Helper to place a value in a field */ + +#define VALUE_TO_FIELD(_value, _field) ((_value << (_field##_S)) & (_field##_M)) + +/* Periheral Clock */ + +#define APB_CLK_FREQ_ROM 40 * 1000000 +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ 80 * 1000000 /* Unit: Hz */ +#define REF_CLK_FREQ (1000000) +#define UART_CLK_FREQ APB_CLK_FREQ +#define MWDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */ +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 40 /* CPU is 80MHz */ + +#define DR_REG_SYSTEM_BASE 0x3f4c0000 +#define DR_REG_SENSITIVE_BASE 0x3f4c1000 +#define DR_REG_INTERRUPT_BASE 0x3f4c2000 +#define DR_REG_DMA_COPY_BASE 0x3f4c3000 +#define DR_REG_EXTMEM_BASE 0x61800000 +#define DR_REG_MMU_TABLE 0x61801000 +#define DR_REG_ITAG_TABLE 0x61802000 +#define DR_REG_DTAG_TABLE 0x61803000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000 +#define DR_REG_INTRUSION_BASE 0x3f4d0000 +#define DR_REG_DPORT_END 0x3f4d3FFC +#define DR_REG_UART_BASE 0x3f400000 +#define DR_REG_SPI1_BASE 0x3f402000 +#define DR_REG_SPI0_BASE 0x3f403000 +#define DR_REG_GPIO_BASE 0x3f404000 +#define DR_REG_GPIO_SD_BASE 0x3f404f00 +#define DR_REG_FE2_BASE 0x3f405000 +#define DR_REG_FE_BASE 0x3f406000 +#define DR_REG_FRC_TIMER_BASE 0x3f407000 +#define DR_REG_RTCCNTL_BASE 0x3f408000 +#define DR_REG_RTCIO_BASE 0x3f408400 +#define DR_REG_SENS_BASE 0x3f408800 +#define DR_REG_RTC_I2C_BASE 0x3f408C00 +#define DR_REG_IO_MUX_BASE 0x3f409000 +#define DR_REG_HINF_BASE 0x3f40B000 +#define DR_REG_I2S_BASE 0x3f40F000 +#define DR_REG_UART1_BASE 0x3f410000 +#define DR_REG_I2C_EXT_BASE 0x3f413000 +#define DR_REG_UHCI0_BASE 0x3f414000 +#define DR_REG_SLCHOST_BASE 0x3f415000 +#define DR_REG_RMT_BASE 0x3f416000 +#define DR_REG_PCNT_BASE 0x3f417000 +#define DR_REG_SLC_BASE 0x3f418000 +#define DR_REG_LEDC_BASE 0x3f419000 +#define DR_REG_CP_BASE 0x3f4c3000 +#define DR_REG_EFUSE_BASE 0x3f41A000 +#define DR_REG_NRX_BASE 0x3f41CC00 +#define DR_REG_BB_BASE 0x3f41D000 +#define DR_REG_TIMERGROUP0_BASE 0x3f41F000 +#define DR_REG_TIMERGROUP1_BASE 0x3f420000 +#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000 +#define DR_REG_SYSTIMER_BASE 0x3f423000 +#define DR_REG_SPI2_BASE 0x3f424000 +#define DR_REG_SPI3_BASE 0x3f425000 +#define DR_REG_SYSCON_BASE 0x3f426000 +#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x3f427000 +#define DR_REG_SPI4_BASE 0x3f437000 +#define DR_REG_USB_WRAP_BASE 0x3f439000 +#define DR_REG_APB_SARADC_BASE 0x3f440000 +#define DR_REG_USB_BASE 0x60080000 + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) +#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +/* Registers Operation */ + +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) + +/* Overall memory map */ + +#define SOC_DROM_LOW 0x3f000000 /* drom0 low address for icache */ +#define SOC_DROM_HIGH 0x3ff80000 /* dram0 high address for dcache */ +#define SOC_IROM_LOW 0x40080000 +#define SOC_IROM_HIGH 0x40800000 +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40020000 +#define SOC_IRAM_LOW 0x40020000 +#define SOC_IRAM_HIGH 0x40070000 +#define SOC_DRAM_LOW 0x3ffb0000 +#define SOC_DRAM_HIGH 0x40000000 +#define SOC_RTC_IRAM_LOW 0x40070000 +#define SOC_RTC_IRAM_HIGH 0x40072000 +#define SOC_RTC_DRAM_LOW 0x3ff9e000 +#define SOC_RTC_DRAM_HIGH 0x3ffa0000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50002000 +#define SOC_EXTRAM_DATA_LOW 0x3f500000 +#define SOC_EXTRAM_DATA_HIGH 0x3ff80000 + +/* Virtual address 0 */ + +#define VADDR0_START_ADDR SOC_DROM_LOW +#define VADDR0_END_ADDR (SOC_DROM_HIGH - 1) + +/* Interrupt hardware source table + * This table is decided by hardware, don't touch this. + */ + +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) + +/* Interrupt cpu using table */ + +/**************************************************************************** + *Intr num Level Type PRO CPU usage APP CPU uasge + * 0 1 extern level WMAC Reserved + * 1 1 extern level BT/BLE Host VHCI Reserved + * 2 1 extern level FROM_CPU FROM_CPU + * 3 1 extern level TG0_WDT Reserved + * 4 1 extern level WBB + * 5 1 extern level BT Controller + * 6 1 timer RTOS Tick RTOS Tick + * 7 1 software Reserved Reserved + * 8 1 extern level BLE Controller + * 9 1 extern level + * 10 1 extern edge Internal Timer + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved Reserved + * 15 3 timer Internal Timer + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level + * 25 4 extern level Reserved Reserved + * 26 5 extern level Reserved Reserved + * 27 3 extern level Reserved Reserved + * 28 4 extern edge + * 29 3 software Reserved Reserved + * 30 4 extern edge Reserved Reserved + * 31 5 extern level Reserved Reserved + ****************************************************************************/ + +/* CPU0 Interrupt number reserved, not touch this. */ + +#define ETS_WMAC_INUM 0 +#define ETS_BT_HOST_INUM 1 +#define ETS_FROM_CPU_INUM 2 +#define ETS_T0_WDT_INUM 3 +#define ETS_WBB_INUM 4 +#define ETS_TG0_T1_INUM 10 /* Use edge interrupt */ + +/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */ + +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 + +/* Other interrupt numbers should be managed by the user */ + +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) +#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) + +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ + +#define APB_CTRL_PRE_DIV_CNT 0x000003ff +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << \ + (APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3ff +#define APB_CTRL_PRE_DIV_CNT_S 0 + +/* ROM functions which read/write internal control bus */ + +extern uint8_t rom_i2c_readreg(uint8_t block, uint8_t host_id, + uint8_t reg_add); +extern uint8_t rom_i2c_readreg_mask(uint8_t block, uint8_t host_id, + uint8_t reg_add, uint8_t msb, uint8_t lsb); +extern void rom_i2c_writereg(uint8_t block, uint8_t host_id, + uint8_t reg_add, uint8_t data); +extern void rom_i2c_writereg_mask(uint8_t block, uint8_t host_id, + uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); + +#define I2C_WRITEREG_RTC(block, reg_add, indata) \ + rom_i2c_writereg(block, block##_HOSTID, reg_add, indata) + +#define I2C_READREG_RTC(block, reg_add) \ + rom_i2c_readreg(block, block##_HOSTID, reg_add) + +#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \ + rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) + +#define I2C_READREG_MASK_RTC(block, reg_add) \ + rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) + +/* BBPLL configuration values */ + +#define BBPLL_ENDIV5_VAL_320M 0x43 +#define BBPLL_BBADC_DSMP_VAL_320M 0x84 +#define BBPLL_ENDIV5_VAL_480M 0xc3 +#define BBPLL_BBADC_DSMP_VAL_480M 0x74 + +#define BBPLL_IR_CAL_DELAY_VAL 0x18 +#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20 +#define BBPLL_OC_ENB_FCAL_VAL 0x9a +#define BBPLL_OC_ENB_VCON_VAL 0x00 +#define BBPLL_BBADC_CAL_7_0_VAL 0x00 + +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) + +/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ + +/* description: This field stores the voltage level for + * CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. + * 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ + +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << (EFUSE_RD_VOL_LEVEL_HP_INV_S)) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 + +/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ + +/* description: read for sdio_force */ + +#define EFUSE_RD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_V 0x1 +#define EFUSE_RD_SDIO_FORCE_S 16 + +/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ + +/* description: read for XPD_SDIO_REG */ + +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_V 0x1 +#define EFUSE_RD_XPD_SDIO_REG_S 14 + +/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ + +/* description: read for SDIO_TIEH */ + +#define EFUSE_RD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_V 0x1 +#define EFUSE_RD_SDIO_TIEH_S 15 + +/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ + +/* description: If set, this bit indicates that + * BLOCK3[143:96] is reserved for internal use + */ + +#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << (EFUSE_RD_BLK3_PART_RESERVE_S)) +#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 +#define EFUSE_RD_BLK3_PART_RESERVE_S 14 + +/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ + +#define EFUSE_RD_SDIO_DREFH 0x00000003 +#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << (EFUSE_RD_SDIO_DREFH_S)) +#define EFUSE_RD_SDIO_DREFH_V 0x3 +#define EFUSE_RD_SDIO_DREFH_S 8 + +/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ + +#define EFUSE_RD_SDIO_DREFM 0x00000003 +#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << (EFUSE_RD_SDIO_DREFM_S)) +#define EFUSE_RD_SDIO_DREFM_V 0x3 +#define EFUSE_RD_SDIO_DREFM_S 10 + +/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. + * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, + * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 + */ + +/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ + +#define EFUSE_RD_SDIO_DREFL 0x00000003 +#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << (EFUSE_RD_SDIO_DREFL_S)) +#define EFUSE_RD_SDIO_DREFL_V 0x3 +#define EFUSE_RD_SDIO_DREFL_S 12 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) + +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ + +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V25 7 + +/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; + * description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL + */ + +#define RTC_CNTL_SOC_CLK_SEL 0x00000003 +#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V) << (RTC_CNTL_SOC_CLK_SEL_S)) +#define RTC_CNTL_SOC_CLK_SEL_V 0x3 +#define RTC_CNTL_SOC_CLK_SEL_S 27 +#define RTC_CNTL_SOC_CLK_SEL_XTL 0 +#define RTC_CNTL_SOC_CLK_SEL_PLL 1 +#define RTC_CNTL_SOC_CLK_SEL_8M 2 +#define RTC_CNTL_SOC_CLK_SEL_APLL 3 + +/* Core voltage needs to be increased in two cases: + * 1. running at 240 MHz + * 2. running with 80MHz Flash frequency + * There is a record in efuse which indicates the + * proper voltage for these two cases. + */ + +#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - \ + (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, \ + EFUSE_RD_VOL_LEVEL_HP_INV))) + +#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT +#else +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 +#endif +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define DELAY_PLL_DBIAS_RAISE 3 +#define DELAY_PLL_ENABLE_WITH_150K 80 +#define DELAY_PLL_ENABLE_WITH_32K 160 + +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; + * description: BB_I2C force power down + */ + +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) + +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; + * description: BB_PLL force power down + */ + +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) + +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; + * description: BB_PLL _I2C force power down + */ + +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) + +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; + * description: PLLA force power down + */ + +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; + * description: BIAS_I2C force power down + */ + +#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) + +#define MHZ (1000000) +#define RTC_PLL_FREQ_320M 320 +#define RTC_PLL_FREQ_480M 480 + +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ + +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V) << (TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 + +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ + +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 + +/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ + +#define TIMG_RTC_CALI_MAX 0x00007fff +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V) << (TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7fff +#define TIMG_RTC_CALI_MAX_S 16 + +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ + +#define TIMG_RTC_CALI_VALUE 0x01ffffff +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V) << (TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1ffffff +#define TIMG_RTC_CALI_VALUE_S 7 + +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ + +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) + +/* Some of the baseband control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) +#define BB_FFT_FORCE_PU (BIT(3)) +#define BB_FFT_FORCE_PU_M (BIT(3)) +#define BB_FFT_FORCE_PU_V 1 +#define BB_FFT_FORCE_PU_S 3 +#define BB_FFT_FORCE_PD (BIT(2)) +#define BB_FFT_FORCE_PD_M (BIT(2)) +#define BB_FFT_FORCE_PD_V 1 +#define BB_FFT_FORCE_PD_S 2 +#define BB_DC_EST_FORCE_PU (BIT(1)) +#define BB_DC_EST_FORCE_PU_M (BIT(1)) +#define BB_DC_EST_FORCE_PU_V 1 +#define BB_DC_EST_FORCE_PU_S 1 +#define BB_DC_EST_FORCE_PD (BIT(0)) +#define BB_DC_EST_FORCE_PD_M (BIT(0)) +#define BB_DC_EST_FORCE_PD_V 1 +#define BB_DC_EST_FORCE_PD_S 0 + +/* Some of the WiFi RX control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) +#define NRX_RX_ROT_FORCE_PU (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_M (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_V 1 +#define NRX_RX_ROT_FORCE_PU_S 5 +#define NRX_RX_ROT_FORCE_PD (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_M (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_V 1 +#define NRX_RX_ROT_FORCE_PD_S 4 +#define NRX_VIT_FORCE_PU (BIT(3)) +#define NRX_VIT_FORCE_PU_M (BIT(3)) +#define NRX_VIT_FORCE_PU_V 1 +#define NRX_VIT_FORCE_PU_S 3 +#define NRX_VIT_FORCE_PD (BIT(2)) +#define NRX_VIT_FORCE_PD_M (BIT(2)) +#define NRX_VIT_FORCE_PD_V 1 +#define NRX_VIT_FORCE_PD_S 2 +#define NRX_DEMAP_FORCE_PU (BIT(1)) +#define NRX_DEMAP_FORCE_PU_M (BIT(1)) +#define NRX_DEMAP_FORCE_PU_V 1 +#define NRX_DEMAP_FORCE_PU_S 1 +#define NRX_DEMAP_FORCE_PD (BIT(0)) +#define NRX_DEMAP_FORCE_PD_M (BIT(0)) +#define NRX_DEMAP_FORCE_PD_V 1 +#define NRX_DEMAP_FORCE_PD_S 0 + +/* Some of the RF frontend control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) +#define FE_IQ_EST_FORCE_PU (BIT(5)) +#define FE_IQ_EST_FORCE_PU_M (BIT(5)) +#define FE_IQ_EST_FORCE_PU_V 1 +#define FE_IQ_EST_FORCE_PU_S 5 +#define FE_IQ_EST_FORCE_PD (BIT(4)) +#define FE_IQ_EST_FORCE_PD_M (BIT(4)) +#define FE_IQ_EST_FORCE_PD_V 1 +#define FE_IQ_EST_FORCE_PD_S 4 + +#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) +#define FE2_TX_INF_FORCE_PU (BIT(10)) +#define FE2_TX_INF_FORCE_PU_M (BIT(10)) +#define FE2_TX_INF_FORCE_PU_V 1 +#define FE2_TX_INF_FORCE_PU_S 10 +#define FE2_TX_INF_FORCE_PD (BIT(9)) +#define FE2_TX_INF_FORCE_PD_M (BIT(9)) +#define FE2_TX_INF_FORCE_PD_V 1 +#define FE2_TX_INF_FORCE_PD_S 9 + +/* RO data page in MMU index */ + +#define DROM0_PAGES_START 0 +#define DROM0_PAGES_END 64 + +#define IROM0_PAGES_START 64 +#define IROM0_PAGES_END 256 + +/* MMU invalid value */ + +#define INVALID_MMU_VAL 0x100 + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_sp_dram + * + * Description: + * Check if the stack pointer is in DRAM. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32s2_sp_dram(uint32_t sp) +{ + return (sp >= SOC_DRAM_LOW + 0x10 && sp < SOC_DRAM_HIGH - 0x10); +} + +/**************************************************************************** + * Name: esp32s2_ptr_extram + * + * Description: + * Check if the buffer comes from the external RAM + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32s2_ptr_extram(const void *p) +{ + return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && + (intptr_t)p < SOC_EXTRAM_DATA_HIGH); +} + +/**************************************************************************** + * Name: esp32s2_ptr_exec + * + * Description: + * Check if the pointer is within an executable range. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32s2_ptr_exec(const void *p) +{ + intptr_t ip = (intptr_t)p; + return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH) + || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH) + || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH) +#if defined(SOC_CACHE_APP_LOW) && !defined(CONFIG_SMP) + || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH) +#endif + || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH); +} + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h new file mode 100644 index 00000000000..1fa5538c474 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h @@ -0,0 +1,3139 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SPI_CMD_REG register */ + +#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0) + +/* SPI_USR : R/W; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit + * is set. The bit will be cleared once the operation done.1: enable 0: + * disable. Can not be changed by CONF_buf. + */ + +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001 +#define SPI_USR_S 24 + +/* SPI_CONF_BITLEN : R/W; bitpos: [22:0]; default: 104; + * Define the spi_clk cycles of SPI_CONF state. + */ + +#define SPI_CONF_BITLEN 0x007FFFFF +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x007FFFFF +#define SPI_CONF_BITLEN_S 0 + +/* SPI_ADDR_REG register */ + +#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4) + +/* SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * [31:8]:address to slave, [7:0]:Reserved. + */ + +#define SPI_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_S 0 + +/* SPI_CTRL_REG register */ + +#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8) + +/* SPI_WR_BIT_ORDER : R/W; bitpos: [26]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first + */ + +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000001 +#define SPI_WR_BIT_ORDER_S 26 + +/* SPI_RD_BIT_ORDER : R/W; bitpos: [25]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first + */ + +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000001 +#define SPI_RD_BIT_ORDER_S 25 + +/* SPI_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output + * low. + */ + +#define SPI_WP_REG (BIT(21)) +#define SPI_WP_REG_M (SPI_WP_REG_V << SPI_WP_REG_S) +#define SPI_WP_REG_V 0x00000001 +#define SPI_WP_REG_S 21 + +/* SPI_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001 +#define SPI_D_POL_S 19 + +/* SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001 +#define SPI_Q_POL_S 18 + +/* SPI_FREAD_OCT : R/W; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: + * disable. + */ + +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S) +#define SPI_FREAD_OCT_V 0x00000001 +#define SPI_FREAD_OCT_S 16 + +/* SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: + * disable. + */ + +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001 +#define SPI_FREAD_QUAD_S 15 + +/* SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: + * disable. + */ + +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001 +#define SPI_FREAD_DUAL_S 14 + +/* SPI_FCMD_OCT : R/W; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S) +#define SPI_FCMD_OCT_V 0x00000001 +#define SPI_FCMD_OCT_S 10 + +/* SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001 +#define SPI_FCMD_QUAD_S 9 + +/* SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable + */ + +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001 +#define SPI_FCMD_DUAL_S 8 + +/* SPI_FADDR_OCT : R/W; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable + */ + +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S) +#define SPI_FADDR_OCT_V 0x00000001 +#define SPI_FADDR_OCT_S 7 + +/* SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable + */ + +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001 +#define SPI_FADDR_QUAD_S 6 + +/* SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable + */ + +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001 +#define SPI_FADDR_DUAL_S 5 + +/* SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * In the dummy phase the signal level of spi is output by the spi + * controller. + */ + +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001 +#define SPI_DUMMY_OUT_S 3 + +/* SPI_EXT_HOLD_EN : R/W; bitpos: [2]; default: 0; + * Set the bit to hold spi. The bit is combined with + * spi_usr_prep_hold,spi_usr_cmd_hold,spi_usr_addr_hold, spi_usr_dummy_hold, + * spi_usr_din_hold,spi_usr_dout_hold and spi_usr_hold_pol. + */ + +#define SPI_EXT_HOLD_EN (BIT(2)) +#define SPI_EXT_HOLD_EN_M (SPI_EXT_HOLD_EN_V << SPI_EXT_HOLD_EN_S) +#define SPI_EXT_HOLD_EN_V 0x00000001 +#define SPI_EXT_HOLD_EN_S 2 + +/* SPI_CTRL1_REG register */ + +#define SPI_CTRL1_REG (DR_REG_SPI_BASE + 0xc) + +/* SPI_CS_HOLD_DELAY : R/W; bitpos: [19:14]; default: 1; + * SPI cs signal is delayed by spi clock cycles. + */ + +#define SPI_CS_HOLD_DELAY 0x0000003F +#define SPI_CS_HOLD_DELAY_M (SPI_CS_HOLD_DELAY_V << SPI_CS_HOLD_DELAY_S) +#define SPI_CS_HOLD_DELAY_V 0x0000003F +#define SPI_CS_HOLD_DELAY_S 14 + +/* SPI_W16_17_WR_ENA : R/W; bitpos: [4]; default: 1; + * 1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be + * written. + */ + +#define SPI_W16_17_WR_ENA (BIT(4)) +#define SPI_W16_17_WR_ENA_M (SPI_W16_17_WR_ENA_V << SPI_W16_17_WR_ENA_S) +#define SPI_W16_17_WR_ENA_V 0x00000001 +#define SPI_W16_17_WR_ENA_S 4 + +/* SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at + * rsck posedge 0: output data at tsck posedge + */ + +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001 +#define SPI_RSCK_DATA_OUT_S 3 + +/* SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data + * B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data + * B[1]/B[6]. + */ + +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001 +#define SPI_CLK_MODE_13_S 2 + +/* SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is + * delayed one cycle after CS inactive 2: SPI clock is delayed two cycles + * after CS inactive 3: SPI clock is alwasy on. + */ + +#define SPI_CLK_MODE 0x00000003 +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003 +#define SPI_CLK_MODE_S 0 + +/* SPI_CTRL2_REG register */ + +#define SPI_CTRL2_REG (DR_REG_SPI_BASE + 0x10) + +/* SPI_CS_DELAY_NUM : R/W; bitpos: [30:29]; default: 0; + * spi_cs signal is delayed by system clock cycles + */ + +#define SPI_CS_DELAY_NUM 0x00000003 +#define SPI_CS_DELAY_NUM_M (SPI_CS_DELAY_NUM_V << SPI_CS_DELAY_NUM_S) +#define SPI_CS_DELAY_NUM_V 0x00000003 +#define SPI_CS_DELAY_NUM_S 29 + +/* SPI_CS_DELAY_MODE : R/W; bitpos: [28:26]; default: 0; + * spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or + * spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle + * 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle, + * else delayed by half cycle 3: delayed one cycle + */ + +#define SPI_CS_DELAY_MODE 0x00000007 +#define SPI_CS_DELAY_MODE_M (SPI_CS_DELAY_MODE_V << SPI_CS_DELAY_MODE_S) +#define SPI_CS_DELAY_MODE_V 0x00000007 +#define SPI_CS_DELAY_MODE_S 26 + +/* SPI_CS_HOLD_TIME : R/W; bitpos: [25:13]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with + * spi_cs_hold bit. + */ + +#define SPI_CS_HOLD_TIME 0x00001FFF +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x00001FFF +#define SPI_CS_HOLD_TIME_S 13 + +/* SPI_CS_SETUP_TIME : R/W; bitpos: [12:0]; default: 1; + * (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_cs_setup bit. + */ + +#define SPI_CS_SETUP_TIME 0x00001FFF +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x00001FFF +#define SPI_CS_SETUP_TIME_S 0 + +/* SPI_CLOCK_REG register */ + +#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0x14) + +/* SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided + * from system clock. + */ + +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001 +#define SPI_CLK_EQU_SYSCLK_S 31 + +/* SPI_CLKDIV_PRE : R/W; bitpos: [30:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. + */ + +#define SPI_CLKDIV_PRE 0x00001FFF +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x00001FFF +#define SPI_CLKDIV_PRE_S 18 + +/* SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + */ + +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003F +#define SPI_CLKCNT_N_S 12 + +/* SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave + * mode it must be 0. + */ + +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003F +#define SPI_CLKCNT_H_S 6 + +/* SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it + * must be 0. + */ + +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003F +#define SPI_CLKCNT_L_S 0 + +/* SPI_USER_REG register */ + +#define SPI_USER_REG (DR_REG_SPI_BASE + 0x18) + +/* SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ + +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001 +#define SPI_USR_COMMAND_S 31 + +/* SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ + +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001 +#define SPI_USR_ADDR_S 30 + +/* SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001 +#define SPI_USR_DUMMY_S 29 + +/* SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ + +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001 +#define SPI_USR_MISO_S 28 + +/* SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ + +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001 +#define SPI_USR_MOSI_S 27 + +/* SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ + +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001 +#define SPI_USR_DUMMY_IDLE_S 26 + +/* SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. + * 1: enable 0: disable. + */ + +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001 +#define SPI_USR_MOSI_HIGHPART_S 25 + +/* SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: + * enable 0: disable. + */ + +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001 +#define SPI_USR_MISO_HIGHPART_S 24 + +/* SPI_USR_PREP_HOLD : R/W; bitpos: [23]; default: 0; + * spi is hold at prepare state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_PREP_HOLD (BIT(23)) +#define SPI_USR_PREP_HOLD_M (SPI_USR_PREP_HOLD_V << SPI_USR_PREP_HOLD_S) +#define SPI_USR_PREP_HOLD_V 0x00000001 +#define SPI_USR_PREP_HOLD_S 23 + +/* SPI_USR_CMD_HOLD : R/W; bitpos: [22]; default: 0; + * spi is hold at command state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_CMD_HOLD (BIT(22)) +#define SPI_USR_CMD_HOLD_M (SPI_USR_CMD_HOLD_V << SPI_USR_CMD_HOLD_S) +#define SPI_USR_CMD_HOLD_V 0x00000001 +#define SPI_USR_CMD_HOLD_S 22 + +/* SPI_USR_ADDR_HOLD : R/W; bitpos: [21]; default: 0; + * spi is hold at address state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_ADDR_HOLD (BIT(21)) +#define SPI_USR_ADDR_HOLD_M (SPI_USR_ADDR_HOLD_V << SPI_USR_ADDR_HOLD_S) +#define SPI_USR_ADDR_HOLD_V 0x00000001 +#define SPI_USR_ADDR_HOLD_S 21 + +/* SPI_USR_DUMMY_HOLD : R/W; bitpos: [20]; default: 0; + * spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit. + */ + +#define SPI_USR_DUMMY_HOLD (BIT(20)) +#define SPI_USR_DUMMY_HOLD_M (SPI_USR_DUMMY_HOLD_V << SPI_USR_DUMMY_HOLD_S) +#define SPI_USR_DUMMY_HOLD_V 0x00000001 +#define SPI_USR_DUMMY_HOLD_S 20 + +/* SPI_USR_DIN_HOLD : R/W; bitpos: [19]; default: 0; + * spi is hold at data in state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_DIN_HOLD (BIT(19)) +#define SPI_USR_DIN_HOLD_M (SPI_USR_DIN_HOLD_V << SPI_USR_DIN_HOLD_S) +#define SPI_USR_DIN_HOLD_V 0x00000001 +#define SPI_USR_DIN_HOLD_S 19 + +/* SPI_USR_DOUT_HOLD : R/W; bitpos: [18]; default: 0; + * spi is hold at data out state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_DOUT_HOLD (BIT(18)) +#define SPI_USR_DOUT_HOLD_M (SPI_USR_DOUT_HOLD_V << SPI_USR_DOUT_HOLD_S) +#define SPI_USR_DOUT_HOLD_V 0x00000001 +#define SPI_USR_DOUT_HOLD_S 18 + +/* SPI_USR_HOLD_POL : R/W; bitpos: [17]; default: 0; + * It is combined with hold bits to set the polarity of spi hold line 1: spi + * will be held when spi hold line is high 0: spi will be held when spi hold + * line is low + */ + +#define SPI_USR_HOLD_POL (BIT(17)) +#define SPI_USR_HOLD_POL_M (SPI_USR_HOLD_POL_V << SPI_USR_HOLD_POL_S) +#define SPI_USR_HOLD_POL_V 0x00000001 +#define SPI_USR_HOLD_POL_S 17 + +/* SPI_SIO : R/W; bitpos: [16]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso + * signals share the same pin. 1: enable 0: disable. + */ + +#define SPI_SIO (BIT(16)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001 +#define SPI_SIO_S 16 + +/* SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means + * seg-trans will continue. 0: The seg-trans will end after the current SPI + * seg-trans or this is not seg-trans mode. + */ + +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001 +#define SPI_USR_CONF_NXT_S 15 + +/* SPI_FWRITE_OCT : R/W; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals + */ + +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S) +#define SPI_FWRITE_OCT_V 0x00000001 +#define SPI_FWRITE_OCT_S 14 + +/* SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ + +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001 +#define SPI_FWRITE_QUAD_S 13 + +/* SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ + +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001 +#define SPI_FWRITE_DUAL_S 12 + +/* SPI_WR_BYTE_ORDER : R/W; bitpos: [11]; default: 0; + * In command address write-data (MOSI) phases 1: big-endian 0: litte_endian + */ + +#define SPI_WR_BYTE_ORDER (BIT(11)) +#define SPI_WR_BYTE_ORDER_M (SPI_WR_BYTE_ORDER_V << SPI_WR_BYTE_ORDER_S) +#define SPI_WR_BYTE_ORDER_V 0x00000001 +#define SPI_WR_BYTE_ORDER_S 11 + +/* SPI_RD_BYTE_ORDER : R/W; bitpos: [10]; default: 0; + * In read-data (MISO) phase 1: big-endian 0: little_endian + */ + +#define SPI_RD_BYTE_ORDER (BIT(10)) +#define SPI_RD_BYTE_ORDER_M (SPI_RD_BYTE_ORDER_V << SPI_RD_BYTE_ORDER_S) +#define SPI_RD_BYTE_ORDER_V 0x00000001 +#define SPI_RD_BYTE_ORDER_S 10 + +/* SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay + * mode. + */ + +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001 +#define SPI_CK_OUT_EDGE_S 9 + +/* SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. + * 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + */ + +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001 +#define SPI_RSCK_I_EDGE_S 8 + +/* SPI_CS_SETUP : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ + +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001 +#define SPI_CS_SETUP_S 7 + +/* SPI_CS_HOLD : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001 +#define SPI_CS_HOLD_S 6 + +/* SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. + * 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + */ + +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001 +#define SPI_TSCK_I_EDGE_S 5 + +/* SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. + */ + +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001 +#define SPI_DOUTDIN_S 0 + +/* SPI_USER1_REG register */ + +#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x1c) + +/* SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be + * (bit_num-1). + */ + +#define SPI_USR_ADDR_BITLEN 0x0000001F +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001F +#define SPI_USR_ADDR_BITLEN_S 27 + +/* SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +/* SPI_USER2_REG register */ + +#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x20) + +/* SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be + * (bit_num-1) + */ + +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000F +#define SPI_USR_COMMAND_BITLEN_S 28 + +/* SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +/* SPI_MOSI_DLEN_REG register */ + +#define SPI_MOSI_DLEN_REG (DR_REG_SPI_BASE + 0x24) + +/* SPI_USR_MOSI_DBITLEN : R/W; bitpos: [22:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ + +#define SPI_USR_MOSI_DBITLEN 0x007FFFFF +#define SPI_USR_MOSI_DBITLEN_M (SPI_USR_MOSI_DBITLEN_V << SPI_USR_MOSI_DBITLEN_S) +#define SPI_USR_MOSI_DBITLEN_V 0x007FFFFF +#define SPI_USR_MOSI_DBITLEN_S 0 + +/* SPI_MISO_DLEN_REG register */ + +#define SPI_MISO_DLEN_REG (DR_REG_SPI_BASE + 0x28) + +/* SPI_USR_MISO_DBITLEN : R/W; bitpos: [22:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ + +#define SPI_USR_MISO_DBITLEN 0x007FFFFF +#define SPI_USR_MISO_DBITLEN_M (SPI_USR_MISO_DBITLEN_V << SPI_USR_MISO_DBITLEN_S) +#define SPI_USR_MISO_DBITLEN_V 0x007FFFFF +#define SPI_USR_MISO_DBITLEN_S 0 + +/* SPI_SLV_WR_STATUS_REG register */ + +#define SPI_SLV_WR_STATUS_REG (DR_REG_SPI_BASE + 0x2c) + +/* SPI_OPI_MODE : R/W; bitpos: [1]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: + * others. + */ + +#define SPI_OPI_MODE (BIT(1)) +#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S) +#define SPI_OPI_MODE_V 0x00000001 +#define SPI_OPI_MODE_S 1 + +/* SPI_QPI_MODE : R/W; bitpos: [0]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: + * others. + */ + +#define SPI_QPI_MODE (BIT(0)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001 +#define SPI_QPI_MODE_S 0 + +/* SPI_MISC_REG register */ + +#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x30) + +/* SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: spi quad input swap enable 0: spi quad input swap disable + */ + +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001 +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/* SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. + */ + +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001 +#define SPI_CS_KEEP_ACTIVE_S 30 + +/* SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ + +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001 +#define SPI_CK_IDLE_EDGE_S 29 + +/* SPI_CD_IDLE_EDGE : R/W; bitpos: [26]; default: 0; + * The default value of spi_cd. + */ + +#define SPI_CD_IDLE_EDGE (BIT(26)) +#define SPI_CD_IDLE_EDGE_M (SPI_CD_IDLE_EDGE_V << SPI_CD_IDLE_EDGE_S) +#define SPI_CD_IDLE_EDGE_V 0x00000001 +#define SPI_CD_IDLE_EDGE_S 26 + +/* SPI_CD_CMD_SET : R/W; bitpos: [25]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state. + * 0: spi_cd = spi_cd_idle_edge. + */ + +#define SPI_CD_CMD_SET (BIT(25)) +#define SPI_CD_CMD_SET_M (SPI_CD_CMD_SET_V << SPI_CD_CMD_SET_S) +#define SPI_CD_CMD_SET_V 0x00000001 +#define SPI_CD_CMD_SET_S 25 + +/* SPI_DQS_IDLE_EDGE : R/W; bitpos: [24]; default: 0; + * The default value of spi_dqs. + */ + +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S) +#define SPI_DQS_IDLE_EDGE_V 0x00000001 +#define SPI_DQS_IDLE_EDGE_S 24 + +/* SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change + */ + +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001 +#define SPI_SLAVE_CS_POL_S 23 + +/* SPI_CD_ADDR_SET : R/W; bitpos: [22]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state. + * 0: spi_cd = spi_cd_idle_edge. + */ + +#define SPI_CD_ADDR_SET (BIT(22)) +#define SPI_CD_ADDR_SET_M (SPI_CD_ADDR_SET_V << SPI_CD_ADDR_SET_S) +#define SPI_CD_ADDR_SET_V 0x00000001 +#define SPI_CD_ADDR_SET_S 22 + +/* SPI_CD_DUMMY_SET : R/W; bitpos: [21]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0: + * spi_cd = spi_cd_idle_edge. + */ + +#define SPI_CD_DUMMY_SET (BIT(21)) +#define SPI_CD_DUMMY_SET_M (SPI_CD_DUMMY_SET_V << SPI_CD_DUMMY_SET_S) +#define SPI_CD_DUMMY_SET_V 0x00000001 +#define SPI_CD_DUMMY_SET_S 21 + +/* SPI_CD_DATA_SET : R/W; bitpos: [20]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN + * state. 0: spi_cd = spi_cd_idle_edge. + */ + +#define SPI_CD_DATA_SET (BIT(20)) +#define SPI_CD_DATA_SET_M (SPI_CD_DATA_SET_V << SPI_CD_DATA_SET_S) +#define SPI_CD_DATA_SET_V 0x00000001 +#define SPI_CD_DATA_SET_S 20 + +/* SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. + */ + +#define SPI_MASTER_CS_POL 0x0000003F +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003F +#define SPI_MASTER_CS_POL_S 7 + +/* SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable + */ + +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001 +#define SPI_CK_DIS_S 6 + +/* SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * SPI CS5 pin enable, 1: disable CS5, 0: SPI_CS5 signal is from/to CS5 pin + */ + +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001 +#define SPI_CS5_DIS_S 5 + +/* SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * SPI CS4 pin enable, 1: disable CS4, 0: SPI_CS4 signal is from/to CS4 pin + */ + +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001 +#define SPI_CS4_DIS_S 4 + +/* SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * SPI CS3 pin enable, 1: disable CS3, 0: SPI_CS3 signal is from/to CS3 pin + */ + +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001 +#define SPI_CS3_DIS_S 3 + +/* SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * SPI CS2 pin enable, 1: disable CS2, 0: SPI_CS2 signal is from/to CS2 pin + */ + +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001 +#define SPI_CS2_DIS_S 2 + +/* SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI CS1 pin enable, 1: disable CS1, 0: SPI_CS1 signal is from/to CS1 pin + */ + +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001 +#define SPI_CS1_DIS_S 1 + +/* SPI_CS0_DIS : R/W; bitpos: [0]; default: 1; + * SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin + */ + +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001 +#define SPI_CS0_DIS_S 0 + +/* SPI_SLAVE_REG register */ + +#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0x34) + +/* SPI_SOFT_RESET : R/W; bitpos: [31]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. + */ + +#define SPI_SOFT_RESET (BIT(31)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001 +#define SPI_SOFT_RESET_S 31 + +/* SPI_SLAVE_MODE : R/W; bitpos: [30]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + +#define SPI_SLAVE_MODE (BIT(30)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001 +#define SPI_SLAVE_MODE_S 30 + +/* SPI_TRANS_DONE_AUTO_CLR_EN : R/W; bitpos: [29]; default: 0; + * spi_trans_done auto clear enable, clear it 3 apb cycles after the pos + * edge of spi_trans_done. 0:disable. 1: enable. + */ + +#define SPI_TRANS_DONE_AUTO_CLR_EN (BIT(29)) +#define SPI_TRANS_DONE_AUTO_CLR_EN_M (SPI_TRANS_DONE_AUTO_CLR_EN_V << SPI_TRANS_DONE_AUTO_CLR_EN_S) +#define SPI_TRANS_DONE_AUTO_CLR_EN_V 0x00000001 +#define SPI_TRANS_DONE_AUTO_CLR_EN_S 29 + +/* SPI_TRANS_CNT : RO; bitpos: [26:23]; default: 0; + * The operations counter in both the master mode and the slave mode. + */ + +#define SPI_TRANS_CNT 0x0000000F +#define SPI_TRANS_CNT_M (SPI_TRANS_CNT_V << SPI_TRANS_CNT_S) +#define SPI_TRANS_CNT_V 0x0000000F +#define SPI_TRANS_CNT_S 23 + +/* SPI_SEG_MAGIC_ERR_INT_EN : R/W; bitpos: [11]; default: 0; + * 1: Enable seg magic value error interrupt. 0: Others + */ + +#define SPI_SEG_MAGIC_ERR_INT_EN (BIT(11)) +#define SPI_SEG_MAGIC_ERR_INT_EN_M (SPI_SEG_MAGIC_ERR_INT_EN_V << SPI_SEG_MAGIC_ERR_INT_EN_S) +#define SPI_SEG_MAGIC_ERR_INT_EN_V 0x00000001 +#define SPI_SEG_MAGIC_ERR_INT_EN_S 11 + +/* SPI_INT_DMA_SEG_TRANS_EN : R/W; bitpos: [10]; default: 0; + * spi_dma_seg_trans_done Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_DMA_SEG_TRANS_EN (BIT(10)) +#define SPI_INT_DMA_SEG_TRANS_EN_M (SPI_INT_DMA_SEG_TRANS_EN_V << SPI_INT_DMA_SEG_TRANS_EN_S) +#define SPI_INT_DMA_SEG_TRANS_EN_V 0x00000001 +#define SPI_INT_DMA_SEG_TRANS_EN_S 10 + +/* SPI_INT_TRANS_DONE_EN : R/W; bitpos: [9]; default: 1; + * spi_trans_done Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_TRANS_DONE_EN (BIT(9)) +#define SPI_INT_TRANS_DONE_EN_M (SPI_INT_TRANS_DONE_EN_V << SPI_INT_TRANS_DONE_EN_S) +#define SPI_INT_TRANS_DONE_EN_V 0x00000001 +#define SPI_INT_TRANS_DONE_EN_S 9 + +/* SPI_INT_WR_DMA_DONE_EN : R/W; bitpos: [8]; default: 0; + * spi_slv_wr_dma Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_WR_DMA_DONE_EN (BIT(8)) +#define SPI_INT_WR_DMA_DONE_EN_M (SPI_INT_WR_DMA_DONE_EN_V << SPI_INT_WR_DMA_DONE_EN_S) +#define SPI_INT_WR_DMA_DONE_EN_V 0x00000001 +#define SPI_INT_WR_DMA_DONE_EN_S 8 + +/* SPI_INT_RD_DMA_DONE_EN : R/W; bitpos: [7]; default: 0; + * spi_slv_rd_dma Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_RD_DMA_DONE_EN (BIT(7)) +#define SPI_INT_RD_DMA_DONE_EN_M (SPI_INT_RD_DMA_DONE_EN_V << SPI_INT_RD_DMA_DONE_EN_S) +#define SPI_INT_RD_DMA_DONE_EN_V 0x00000001 +#define SPI_INT_RD_DMA_DONE_EN_S 7 + +/* SPI_INT_WR_BUF_DONE_EN : R/W; bitpos: [6]; default: 0; + * spi_slv_wr_buf Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_WR_BUF_DONE_EN (BIT(6)) +#define SPI_INT_WR_BUF_DONE_EN_M (SPI_INT_WR_BUF_DONE_EN_V << SPI_INT_WR_BUF_DONE_EN_S) +#define SPI_INT_WR_BUF_DONE_EN_V 0x00000001 +#define SPI_INT_WR_BUF_DONE_EN_S 6 + +/* SPI_INT_RD_BUF_DONE_EN : R/W; bitpos: [5]; default: 0; + * spi_slv_rd_buf Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_RD_BUF_DONE_EN (BIT(5)) +#define SPI_INT_RD_BUF_DONE_EN_M (SPI_INT_RD_BUF_DONE_EN_V << SPI_INT_RD_BUF_DONE_EN_S) +#define SPI_INT_RD_BUF_DONE_EN_V 0x00000001 +#define SPI_INT_RD_BUF_DONE_EN_S 5 + +/* SPI_TRANS_DONE : R/W; bitpos: [4]; default: 0; + * The interrupt raw bit for the completion of any operation in both the + * master mode and the slave mode. Can not be changed by CONF_buf. + */ + +#define SPI_TRANS_DONE (BIT(4)) +#define SPI_TRANS_DONE_M (SPI_TRANS_DONE_V << SPI_TRANS_DONE_S) +#define SPI_TRANS_DONE_V 0x00000001 +#define SPI_TRANS_DONE_S 4 + +/* SPI_SLAVE1_REG register */ + +#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0x38) + +/* SPI_SLV_LAST_ADDR : R/W; bitpos: [31:24]; default: 0; + * In the slave mode it is the value of address. + */ + +#define SPI_SLV_LAST_ADDR 0x000000FF +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x000000FF +#define SPI_SLV_LAST_ADDR_S 24 + +/* SPI_SLV_LAST_COMMAND : R/W; bitpos: [23:16]; default: 0; + * In the slave mode it is the value of command. + */ + +#define SPI_SLV_LAST_COMMAND 0x000000FF +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FF +#define SPI_SLV_LAST_COMMAND_S 16 + +/* SPI_SLV_WR_DMA_DONE : R/W; bitpos: [15]; default: 0; + * The interrupt raw bit for the completion of dma write operation in the + * slave mode. Can not be changed by CONF_buf. + */ + +#define SPI_SLV_WR_DMA_DONE (BIT(15)) +#define SPI_SLV_WR_DMA_DONE_M (SPI_SLV_WR_DMA_DONE_V << SPI_SLV_WR_DMA_DONE_S) +#define SPI_SLV_WR_DMA_DONE_V 0x00000001 +#define SPI_SLV_WR_DMA_DONE_S 15 + +/* SPI_SLV_CMD_ERR : R/W; bitpos: [14]; default: 0; + * 1: The command value of the last SPI transfer is not supported by SPI + * slave. 0: The command value is supported or no command value is received. + */ + +#define SPI_SLV_CMD_ERR (BIT(14)) +#define SPI_SLV_CMD_ERR_M (SPI_SLV_CMD_ERR_V << SPI_SLV_CMD_ERR_S) +#define SPI_SLV_CMD_ERR_V 0x00000001 +#define SPI_SLV_CMD_ERR_S 14 + +/* SPI_SLV_ADDR_ERR : R/W; bitpos: [13]; default: 0; + * 1: The address value of the last SPI transfer is not supported by SPI + * slave. 0: The address value is supported or no address value is received. + */ + +#define SPI_SLV_ADDR_ERR (BIT(13)) +#define SPI_SLV_ADDR_ERR_M (SPI_SLV_ADDR_ERR_V << SPI_SLV_ADDR_ERR_S) +#define SPI_SLV_ADDR_ERR_V 0x00000001 +#define SPI_SLV_ADDR_ERR_S 13 + +/* SPI_SLAVE2_REG register */ + +#define SPI_SLAVE2_REG (DR_REG_SPI_BASE + 0x3c) + +/* SPI_SLV_RD_DMA_DONE : R/W; bitpos: [8]; default: 0; + * The interrupt raw bit for the completion of Rd-DMA operation in the slave + * mode. Can not be changed by CONF_buf. + */ + +#define SPI_SLV_RD_DMA_DONE (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_M (SPI_SLV_RD_DMA_DONE_V << SPI_SLV_RD_DMA_DONE_S) +#define SPI_SLV_RD_DMA_DONE_V 0x00000001 +#define SPI_SLV_RD_DMA_DONE_S 8 + +/* SPI_SLV_WRBUF_DLEN_REG register */ + +#define SPI_SLV_WRBUF_DLEN_REG (DR_REG_SPI_BASE + 0x40) + +/* SPI_CONF_BASE_BITLEN : R/W; bitpos: [31:25]; default: 108; + * The basic spi_clk cycles of CONF state. The real cycle length of CONF + * state, if spi_usr_conf is enabled, is spi_conf_base_bitlen[6:0] + + * spi_conf_bitlen[23:0]. + */ + +#define SPI_CONF_BASE_BITLEN 0x0000007F +#define SPI_CONF_BASE_BITLEN_M (SPI_CONF_BASE_BITLEN_V << SPI_CONF_BASE_BITLEN_S) +#define SPI_CONF_BASE_BITLEN_V 0x0000007F +#define SPI_CONF_BASE_BITLEN_S 25 + +/* SPI_SLV_WR_BUF_DONE : R/W; bitpos: [24]; default: 0; + * The interrupt raw bit for the completion of write-buffer operation in the + * slave mode. Can not be changed by CONF_buf. + */ + +#define SPI_SLV_WR_BUF_DONE (BIT(24)) +#define SPI_SLV_WR_BUF_DONE_M (SPI_SLV_WR_BUF_DONE_V << SPI_SLV_WR_BUF_DONE_S) +#define SPI_SLV_WR_BUF_DONE_V 0x00000001 +#define SPI_SLV_WR_BUF_DONE_S 24 + +/* SPI_SLV_RDBUF_DLEN_REG register */ + +#define SPI_SLV_RDBUF_DLEN_REG (DR_REG_SPI_BASE + 0x44) + +/* SPI_SEG_MAGIC_ERR : R/W; bitpos: [25]; default: 0; + * 1: The recent magic value in CONF buffer is not right in master DMA + * seg-trans mode. 0: others. + */ + +#define SPI_SEG_MAGIC_ERR (BIT(25)) +#define SPI_SEG_MAGIC_ERR_M (SPI_SEG_MAGIC_ERR_V << SPI_SEG_MAGIC_ERR_S) +#define SPI_SEG_MAGIC_ERR_V 0x00000001 +#define SPI_SEG_MAGIC_ERR_S 25 + +/* SPI_SLV_RD_BUF_DONE : R/W; bitpos: [24]; default: 0; + * The interrupt raw bit for the completion of read-buffer operation in the + * slave mode. Can not be changed by CONF_buf. + */ + +#define SPI_SLV_RD_BUF_DONE (BIT(24)) +#define SPI_SLV_RD_BUF_DONE_M (SPI_SLV_RD_BUF_DONE_V << SPI_SLV_RD_BUF_DONE_S) +#define SPI_SLV_RD_BUF_DONE_V 0x00000001 +#define SPI_SLV_RD_BUF_DONE_S 24 + +/* SPI_SLV_DMA_RD_BYTELEN : R/W; bitpos: [19:0]; default: 0; + * In the slave mode it is the length in bytes for read operations. The + * register value shall be byte_num. + */ + +#define SPI_SLV_DMA_RD_BYTELEN 0x000FFFFF +#define SPI_SLV_DMA_RD_BYTELEN_M (SPI_SLV_DMA_RD_BYTELEN_V << SPI_SLV_DMA_RD_BYTELEN_S) +#define SPI_SLV_DMA_RD_BYTELEN_V 0x000FFFFF +#define SPI_SLV_DMA_RD_BYTELEN_S 0 + +/* SPI_SLV_RD_BYTE_REG register */ + +#define SPI_SLV_RD_BYTE_REG (DR_REG_SPI_BASE + 0x48) + +/* SPI_USR_CONF : R/W; bitpos: [31]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means + * seg-trans will start. 0: This is not seg-trans mode. + */ + +#define SPI_USR_CONF (BIT(31)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001 +#define SPI_USR_CONF_S 31 + +/* SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [29:24]; default: 23; + * The magic value of BM table in master DMA seg-trans. + */ + +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000003F +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000003F +#define SPI_DMA_SEG_MAGIC_VALUE_S 24 + +/* SPI_SLV_WRBUF_BYTELEN_EN : R/W; bitpos: [23]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave + * data length in CPU controlled mode(Wr_BUF). 0: others + */ + +#define SPI_SLV_WRBUF_BYTELEN_EN (BIT(23)) +#define SPI_SLV_WRBUF_BYTELEN_EN_M (SPI_SLV_WRBUF_BYTELEN_EN_V << SPI_SLV_WRBUF_BYTELEN_EN_S) +#define SPI_SLV_WRBUF_BYTELEN_EN_V 0x00000001 +#define SPI_SLV_WRBUF_BYTELEN_EN_S 23 + +/* SPI_SLV_RDBUF_BYTELEN_EN : R/W; bitpos: [22]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-read-slave data + * length in CPU controlled mode(Rd_BUF). 0: others + */ + +#define SPI_SLV_RDBUF_BYTELEN_EN (BIT(22)) +#define SPI_SLV_RDBUF_BYTELEN_EN_M (SPI_SLV_RDBUF_BYTELEN_EN_V << SPI_SLV_RDBUF_BYTELEN_EN_S) +#define SPI_SLV_RDBUF_BYTELEN_EN_V 0x00000001 +#define SPI_SLV_RDBUF_BYTELEN_EN_S 22 + +/* SPI_SLV_WRDMA_BYTELEN_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave + * data length in DMA controlled mode(Wr_DMA). 0: others + */ + +#define SPI_SLV_WRDMA_BYTELEN_EN (BIT(21)) +#define SPI_SLV_WRDMA_BYTELEN_EN_M (SPI_SLV_WRDMA_BYTELEN_EN_V << SPI_SLV_WRDMA_BYTELEN_EN_S) +#define SPI_SLV_WRDMA_BYTELEN_EN_V 0x00000001 +#define SPI_SLV_WRDMA_BYTELEN_EN_S 21 + +/* SPI_SLV_RDDMA_BYTELEN_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-read-slave data + * length in DMA controlled mode(Rd_DMA). 0: others + */ + +#define SPI_SLV_RDDMA_BYTELEN_EN (BIT(20)) +#define SPI_SLV_RDDMA_BYTELEN_EN_M (SPI_SLV_RDDMA_BYTELEN_EN_V << SPI_SLV_RDDMA_BYTELEN_EN_S) +#define SPI_SLV_RDDMA_BYTELEN_EN_V 0x00000001 +#define SPI_SLV_RDDMA_BYTELEN_EN_S 20 + +/* SPI_SLV_DATA_BYTELEN : R/W; bitpos: [19:0]; default: 0; + * The full-duplex or half-duplex data byte length of the last SPI transfer + * in slave mode. In half-duplex mode, this value is controlled by bits + * [23:20]. + */ + +#define SPI_SLV_DATA_BYTELEN 0x000FFFFF +#define SPI_SLV_DATA_BYTELEN_M (SPI_SLV_DATA_BYTELEN_V << SPI_SLV_DATA_BYTELEN_S) +#define SPI_SLV_DATA_BYTELEN_V 0x000FFFFF +#define SPI_SLV_DATA_BYTELEN_S 0 + +/* SPI_FSM_REG register */ + +#define SPI_FSM_REG (DR_REG_SPI_BASE + 0x50) + +/* SPI_MST_DMA_RD_BYTELEN : R/W; bitpos: [31:12]; default: 0; + * Define the master DMA read byte length in non seg-trans or seg-trans + * mode. Invalid when spi_rx_eof_en is 0. + */ + +#define SPI_MST_DMA_RD_BYTELEN 0x000FFFFF +#define SPI_MST_DMA_RD_BYTELEN_M (SPI_MST_DMA_RD_BYTELEN_V << SPI_MST_DMA_RD_BYTELEN_S) +#define SPI_MST_DMA_RD_BYTELEN_V 0x000FFFFF +#define SPI_MST_DMA_RD_BYTELEN_S 12 + +/* SPI_ST : RO; bitpos: [3:0]; default: 0; + * The status of spi state machine. 0: idle state, 1: preparation state, 2: + * send command state, 3: send data state, 4: red data state, 5:write data + * state, 6: wait state, 7: done state. + */ + +#define SPI_ST 0x0000000F +#define SPI_ST_M (SPI_ST_V << SPI_ST_S) +#define SPI_ST_V 0x0000000F +#define SPI_ST_S 0 + +/* SPI_HOLD_REG register */ + +#define SPI_HOLD_REG (DR_REG_SPI_BASE + 0x54) + +/* SPI_DMA_SEG_TRANS_DONE : R/W; bitpos: [7]; default: 0; + * 1: spi master DMA full-duplex/half-duplex seg-trans ends or slave + * half-duplex seg-trans ends. And data has been pushed to corresponding + * memory. 0: seg-trans is not ended or not occurred. Can not be changed + * by CONF_buf. + */ + +#define SPI_DMA_SEG_TRANS_DONE (BIT(7)) +#define SPI_DMA_SEG_TRANS_DONE_M (SPI_DMA_SEG_TRANS_DONE_V << SPI_DMA_SEG_TRANS_DONE_S) +#define SPI_DMA_SEG_TRANS_DONE_V 0x00000001 +#define SPI_DMA_SEG_TRANS_DONE_S 7 + +/* SPI_HOLD_OUT_TIME : R/W; bitpos: [6:4]; default: 0; + * set the hold cycles of output spi_hold signal when spi_hold_out_en is + * enable. + */ + +#define SPI_HOLD_OUT_TIME 0x00000007 +#define SPI_HOLD_OUT_TIME_M (SPI_HOLD_OUT_TIME_V << SPI_HOLD_OUT_TIME_S) +#define SPI_HOLD_OUT_TIME_V 0x00000007 +#define SPI_HOLD_OUT_TIME_S 4 + +/* SPI_HOLD_OUT_EN : R/W; bitpos: [3]; default: 0; + * Enable set spi output hold value to spi_hold_reg. It can be used to hold + * spi state machine with spi_ext_hold_en and other usr hold signals. + */ + +#define SPI_HOLD_OUT_EN (BIT(3)) +#define SPI_HOLD_OUT_EN_M (SPI_HOLD_OUT_EN_V << SPI_HOLD_OUT_EN_S) +#define SPI_HOLD_OUT_EN_V 0x00000001 +#define SPI_HOLD_OUT_EN_S 3 + +/* SPI_HOLD_VAL_REG : R/W; bitpos: [2]; default: 0; + * spi hold output value, which should be used with spi_hold_out_en. + */ + +#define SPI_HOLD_VAL_REG (BIT(2)) +#define SPI_HOLD_VAL_REG_M (SPI_HOLD_VAL_REG_V << SPI_HOLD_VAL_REG_S) +#define SPI_HOLD_VAL_REG_V 0x00000001 +#define SPI_HOLD_VAL_REG_S 2 + +/* SPI_INT_HOLD_ENA : R/W; bitpos: [1:0]; default: 0; + * This register is for two SPI masters to share the same cs clock and data + * signals. The bits of one SPI are set, if the other SPI is busy, the SPI + * will be hold. 1(3): hold at idle phase 2: hold at prepare phase. + */ + +#define SPI_INT_HOLD_ENA 0x00000003 +#define SPI_INT_HOLD_ENA_M (SPI_INT_HOLD_ENA_V << SPI_INT_HOLD_ENA_S) +#define SPI_INT_HOLD_ENA_V 0x00000003 +#define SPI_INT_HOLD_ENA_S 0 + +/* SPI_DMA_CONF_REG register */ + +#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x58) + +/* SPI_EXT_MEM_BK_SIZE : R/W; bitpos: [27:26]; default: 0; + * Select the external memory block size. + */ + +#define SPI_EXT_MEM_BK_SIZE 0x00000003 +#define SPI_EXT_MEM_BK_SIZE_M (SPI_EXT_MEM_BK_SIZE_V << SPI_EXT_MEM_BK_SIZE_S) +#define SPI_EXT_MEM_BK_SIZE_V 0x00000003 +#define SPI_EXT_MEM_BK_SIZE_S 26 + +/* SPI_DMA_OUTFIFO_EMPTY_ERR : R/W; bitpos: [25]; default: 0; + * 1:spi_dma_outfifo_empty and spi_pop_data_prep are valid, which means that + * there is no data to pop but pop is valid. 0: Others. Can not be changed + * by CONF_buf. + */ + +#define SPI_DMA_OUTFIFO_EMPTY_ERR (BIT(25)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_S 25 + +/* SPI_DMA_INFIFO_FULL_ERR : R/W; bitpos: [24]; default: 0; + * 1:spi_dma_infifo_full and spi_push_data_prep are valid, which means that + * DMA Rx buffer is full but push is valid. 0: Others. Can not be changed + * by CONF_buf. + */ + +#define SPI_DMA_INFIFO_FULL_ERR (BIT(24)) +#define SPI_DMA_INFIFO_FULL_ERR_M (SPI_DMA_INFIFO_FULL_ERR_V << SPI_DMA_INFIFO_FULL_ERR_S) +#define SPI_DMA_INFIFO_FULL_ERR_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_ERR_S 24 + +/* SPI_DMA_OUTFIFO_EMPTY_CLR : R/W; bitpos: [23]; default: 0; + * 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it. + */ + +#define SPI_DMA_OUTFIFO_EMPTY_CLR (BIT(23)) +#define SPI_DMA_OUTFIFO_EMPTY_CLR_M (SPI_DMA_OUTFIFO_EMPTY_CLR_V << SPI_DMA_OUTFIFO_EMPTY_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_CLR_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_CLR_S 23 + +/* SPI_DMA_INFIFO_FULL_CLR : R/W; bitpos: [22]; default: 0; + * 1:Clear spi_dma_infifo_full_vld. 0: Do not control it. + */ + +#define SPI_DMA_INFIFO_FULL_CLR (BIT(22)) +#define SPI_DMA_INFIFO_FULL_CLR_M (SPI_DMA_INFIFO_FULL_CLR_V << SPI_DMA_INFIFO_FULL_CLR_S) +#define SPI_DMA_INFIFO_FULL_CLR_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_CLR_S 22 + +/* SPI_REG_SPI_REG_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is + * equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma + * transition. 0: spi_dma_inlink_eof is set by spi_trans_done in + * non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ + +#define SPI_REG_SPI_REG_RX_EOF_EN (BIT(21)) +#define SPI_REG_SPI_REG_RX_EOF_EN_M (SPI_REG_SPI_REG_RX_EOF_EN_V << SPI_REG_SPI_REG_RX_EOF_EN_S) +#define SPI_REG_SPI_REG_RX_EOF_EN_V 0x00000001 +#define SPI_REG_SPI_REG_RX_EOF_EN_S 21 + +/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001 +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 + +/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001 +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 + +/* SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: + * disable. + */ + +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001 +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 + +/* SPI_SLV_LAST_SEG_POP_CLR : R/W; bitpos: [17]; default: 0; + * 1: Clear spi_slv_seg_frt_pop_mask. 0 : others + */ + +#define SPI_SLV_LAST_SEG_POP_CLR (BIT(17)) +#define SPI_SLV_LAST_SEG_POP_CLR_M (SPI_SLV_LAST_SEG_POP_CLR_V << SPI_SLV_LAST_SEG_POP_CLR_S) +#define SPI_SLV_LAST_SEG_POP_CLR_V 0x00000001 +#define SPI_SLV_LAST_SEG_POP_CLR_S 17 + +/* SPI_DMA_CONTINUE : R/W; bitpos: [16]; default: 0; + * spi dma continue tx/rx data. + */ + +#define SPI_DMA_CONTINUE (BIT(16)) +#define SPI_DMA_CONTINUE_M (SPI_DMA_CONTINUE_V << SPI_DMA_CONTINUE_S) +#define SPI_DMA_CONTINUE_V 0x00000001 +#define SPI_DMA_CONTINUE_S 16 + +/* SPI_DMA_TX_STOP : R/W; bitpos: [15]; default: 0; + * spi dma write data stop when in continue tx/rx mode. + */ + +#define SPI_DMA_TX_STOP (BIT(15)) +#define SPI_DMA_TX_STOP_M (SPI_DMA_TX_STOP_V << SPI_DMA_TX_STOP_S) +#define SPI_DMA_TX_STOP_V 0x00000001 +#define SPI_DMA_TX_STOP_S 15 + +/* SPI_REG_SPI_REG_DMA_RX_STOP : R/W; bitpos: [14]; default: 0; + * spi dma read data stop when in continue tx/rx mode. + */ + +#define SPI_REG_SPI_REG_DMA_RX_STOP (BIT(14)) +#define SPI_REG_SPI_REG_DMA_RX_STOP_M (SPI_REG_SPI_REG_DMA_RX_STOP_V << SPI_REG_SPI_REG_DMA_RX_STOP_S) +#define SPI_REG_SPI_REG_DMA_RX_STOP_V 0x00000001 +#define SPI_REG_SPI_REG_DMA_RX_STOP_S 14 + +/* SPI_MEM_TRANS_EN : R/W; bitpos: [13]; default: 0; + * DMA internal memory data transfer enable signal. + */ + +#define SPI_MEM_TRANS_EN (BIT(13)) +#define SPI_MEM_TRANS_EN_M (SPI_MEM_TRANS_EN_V << SPI_MEM_TRANS_EN_S) +#define SPI_MEM_TRANS_EN_V 0x00000001 +#define SPI_MEM_TRANS_EN_S 13 + +/* SPI_OUT_DATA_BURST_EN : R/W; bitpos: [12]; default: 0; + * spi dma read data from memory in burst mode. + */ + +#define SPI_OUT_DATA_BURST_EN (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_M (SPI_OUT_DATA_BURST_EN_V << SPI_OUT_DATA_BURST_EN_S) +#define SPI_OUT_DATA_BURST_EN_V 0x00000001 +#define SPI_OUT_DATA_BURST_EN_S 12 + +/* SPI_INDSCR_BURST_EN : R/W; bitpos: [11]; default: 0; + * read descriptor use burst mode when write data to memory. + */ + +#define SPI_INDSCR_BURST_EN (BIT(11)) +#define SPI_INDSCR_BURST_EN_M (SPI_INDSCR_BURST_EN_V << SPI_INDSCR_BURST_EN_S) +#define SPI_INDSCR_BURST_EN_V 0x00000001 +#define SPI_INDSCR_BURST_EN_S 11 + +/* SPI_OUTDSCR_BURST_EN : R/W; bitpos: [10]; default: 0; + * read descriptor use burst mode when read data for memory. + */ + +#define SPI_OUTDSCR_BURST_EN (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_M (SPI_OUTDSCR_BURST_EN_V << SPI_OUTDSCR_BURST_EN_S) +#define SPI_OUTDSCR_BURST_EN_V 0x00000001 +#define SPI_OUTDSCR_BURST_EN_S 10 + +/* SPI_OUT_EOF_MODE : R/W; bitpos: [9]; default: 1; + * out eof flag generation mode . 1: when dma pop all data from fifo 0:when + * ahb push all data to fifo. + */ + +#define SPI_OUT_EOF_MODE (BIT(9)) +#define SPI_OUT_EOF_MODE_M (SPI_OUT_EOF_MODE_V << SPI_OUT_EOF_MODE_S) +#define SPI_OUT_EOF_MODE_V 0x00000001 +#define SPI_OUT_EOF_MODE_S 9 + +/* SPI_OUT_AUTO_WRBACK : R/W; bitpos: [8]; default: 0; + * when the bit is set, DMA continue to use the next inlink node when the + * length of inlink is 0. + */ + +#define SPI_OUT_AUTO_WRBACK (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_M (SPI_OUT_AUTO_WRBACK_V << SPI_OUT_AUTO_WRBACK_S) +#define SPI_OUT_AUTO_WRBACK_V 0x00000001 +#define SPI_OUT_AUTO_WRBACK_S 8 + +/* SPI_OUT_LOOP_TEST : R/W; bitpos: [7]; default: 0; + * Set bit to test out link. + */ + +#define SPI_OUT_LOOP_TEST (BIT(7)) +#define SPI_OUT_LOOP_TEST_M (SPI_OUT_LOOP_TEST_V << SPI_OUT_LOOP_TEST_S) +#define SPI_OUT_LOOP_TEST_V 0x00000001 +#define SPI_OUT_LOOP_TEST_S 7 + +/* SPI_IN_LOOP_TEST : R/W; bitpos: [6]; default: 0; + * Set bit to test in link. + */ + +#define SPI_IN_LOOP_TEST (BIT(6)) +#define SPI_IN_LOOP_TEST_M (SPI_IN_LOOP_TEST_V << SPI_IN_LOOP_TEST_S) +#define SPI_IN_LOOP_TEST_V 0x00000001 +#define SPI_IN_LOOP_TEST_S 6 + +/* SPI_AHBM_RST : R/W; bitpos: [5]; default: 0; + * Reset spi dma ahb master. + */ + +#define SPI_AHBM_RST (BIT(5)) +#define SPI_AHBM_RST_M (SPI_AHBM_RST_V << SPI_AHBM_RST_S) +#define SPI_AHBM_RST_V 0x00000001 +#define SPI_AHBM_RST_S 5 + +/* SPI_AHBM_FIFO_RST : R/W; bitpos: [4]; default: 0; + * Reset spi dma ahb master fifo pointer. + */ + +#define SPI_AHBM_FIFO_RST (BIT(4)) +#define SPI_AHBM_FIFO_RST_M (SPI_AHBM_FIFO_RST_V << SPI_AHBM_FIFO_RST_S) +#define SPI_AHBM_FIFO_RST_V 0x00000001 +#define SPI_AHBM_FIFO_RST_S 4 + +/* SPI_OUT_RST : R/W; bitpos: [3]; default: 0; + * The bit is used to reset out dma fsm and out data fifo pointer. + */ + +#define SPI_OUT_RST (BIT(3)) +#define SPI_OUT_RST_M (SPI_OUT_RST_V << SPI_OUT_RST_S) +#define SPI_OUT_RST_V 0x00000001 +#define SPI_OUT_RST_S 3 + +/* SPI_IN_RST : R/W; bitpos: [2]; default: 0; + * The bit is used to reset in dma fsm and in data fifo pointer. + */ + +#define SPI_IN_RST (BIT(2)) +#define SPI_IN_RST_M (SPI_IN_RST_V << SPI_IN_RST_S) +#define SPI_IN_RST_V 0x00000001 +#define SPI_IN_RST_S 2 + +/* SPI_DMA_OUT_LINK_REG register */ + +#define SPI_DMA_OUT_LINK_REG (DR_REG_SPI_BASE + 0x5c) + +/* SPI_DMA_TX_ENA : R/W; bitpos: [31]; default: 0; + * spi dma write data status bit. + */ + +#define SPI_DMA_TX_ENA (BIT(31)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001 +#define SPI_DMA_TX_ENA_S 31 + +/* SPI_OUTLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set the bit to mount on new outlink descriptors. + */ + +#define SPI_OUTLINK_RESTART (BIT(30)) +#define SPI_OUTLINK_RESTART_M (SPI_OUTLINK_RESTART_V << SPI_OUTLINK_RESTART_S) +#define SPI_OUTLINK_RESTART_V 0x00000001 +#define SPI_OUTLINK_RESTART_S 30 + +/* SPI_OUTLINK_START : R/W; bitpos: [29]; default: 0; + * Set the bit to start to use outlink descriptor. + */ + +#define SPI_OUTLINK_START (BIT(29)) +#define SPI_OUTLINK_START_M (SPI_OUTLINK_START_V << SPI_OUTLINK_START_S) +#define SPI_OUTLINK_START_V 0x00000001 +#define SPI_OUTLINK_START_S 29 + +/* SPI_OUTLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set the bit to stop to use outlink descriptor. + */ + +#define SPI_OUTLINK_STOP (BIT(28)) +#define SPI_OUTLINK_STOP_M (SPI_OUTLINK_STOP_V << SPI_OUTLINK_STOP_S) +#define SPI_OUTLINK_STOP_V 0x00000001 +#define SPI_OUTLINK_STOP_S 28 + +/* SPI_OUTLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * The address of the first outlink descriptor. + */ + +#define SPI_OUTLINK_ADDR 0x000FFFFF +#define SPI_OUTLINK_ADDR_M (SPI_OUTLINK_ADDR_V << SPI_OUTLINK_ADDR_S) +#define SPI_OUTLINK_ADDR_V 0x000FFFFF +#define SPI_OUTLINK_ADDR_S 0 + +/* SPI_DMA_IN_LINK_REG register */ + +#define SPI_DMA_IN_LINK_REG (DR_REG_SPI_BASE + 0x60) + +/* SPI_DMA_RX_ENA : R/W; bitpos: [31]; default: 0; + * spi dma read data status bit. + */ + +#define SPI_DMA_RX_ENA (BIT(31)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001 +#define SPI_DMA_RX_ENA_S 31 + +/* SPI_INLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set the bit to mount on new inlink descriptors. + */ + +#define SPI_INLINK_RESTART (BIT(30)) +#define SPI_INLINK_RESTART_M (SPI_INLINK_RESTART_V << SPI_INLINK_RESTART_S) +#define SPI_INLINK_RESTART_V 0x00000001 +#define SPI_INLINK_RESTART_S 30 + +/* SPI_INLINK_START : R/W; bitpos: [29]; default: 0; + * Set the bit to start to use inlink descriptor. + */ + +#define SPI_INLINK_START (BIT(29)) +#define SPI_INLINK_START_M (SPI_INLINK_START_V << SPI_INLINK_START_S) +#define SPI_INLINK_START_V 0x00000001 +#define SPI_INLINK_START_S 29 + +/* SPI_INLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set the bit to stop to use inlink descriptor. + */ + +#define SPI_INLINK_STOP (BIT(28)) +#define SPI_INLINK_STOP_M (SPI_INLINK_STOP_V << SPI_INLINK_STOP_S) +#define SPI_INLINK_STOP_V 0x00000001 +#define SPI_INLINK_STOP_S 28 + +/* SPI_INLINK_AUTO_RET : R/W; bitpos: [20]; default: 0; + * when the bit is set, the inlink descriptor returns to the first link node + * when a packet is error. + */ + +#define SPI_INLINK_AUTO_RET (BIT(20)) +#define SPI_INLINK_AUTO_RET_M (SPI_INLINK_AUTO_RET_V << SPI_INLINK_AUTO_RET_S) +#define SPI_INLINK_AUTO_RET_V 0x00000001 +#define SPI_INLINK_AUTO_RET_S 20 + +/* SPI_INLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * The address of the first inlink descriptor. + */ + +#define SPI_INLINK_ADDR 0x000FFFFF +#define SPI_INLINK_ADDR_M (SPI_INLINK_ADDR_V << SPI_INLINK_ADDR_S) +#define SPI_INLINK_ADDR_V 0x000FFFFF +#define SPI_INLINK_ADDR_S 0 + +/* SPI_DMA_INT_ENA_REG register */ + +#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x64) + +/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for sending all the packets to host done. + */ + +#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_M (SPI_OUT_TOTAL_EOF_INT_ENA_V << SPI_OUT_TOTAL_EOF_INT_ENA_S) +#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x00000001 +#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 + +/* SPI_OUT_EOF_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for sending a packet to host done. + */ + +#define SPI_OUT_EOF_INT_ENA (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_M (SPI_OUT_EOF_INT_ENA_V << SPI_OUT_EOF_INT_ENA_S) +#define SPI_OUT_EOF_INT_ENA_V 0x00000001 +#define SPI_OUT_EOF_INT_ENA_S 7 + +/* SPI_OUT_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for completing usage of a outlink descriptor . + */ + +#define SPI_OUT_DONE_INT_ENA (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_M (SPI_OUT_DONE_INT_ENA_V << SPI_OUT_DONE_INT_ENA_S) +#define SPI_OUT_DONE_INT_ENA_V 0x00000001 +#define SPI_OUT_DONE_INT_ENA_S 6 + +/* SPI_IN_SUC_EOF_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for completing receiving all the packets from host. + */ + +#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_M (SPI_IN_SUC_EOF_INT_ENA_V << SPI_IN_SUC_EOF_INT_ENA_S) +#define SPI_IN_SUC_EOF_INT_ENA_V 0x00000001 +#define SPI_IN_SUC_EOF_INT_ENA_S 5 + +/* SPI_IN_ERR_EOF_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for receiving error. + */ + +#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_M (SPI_IN_ERR_EOF_INT_ENA_V << SPI_IN_ERR_EOF_INT_ENA_S) +#define SPI_IN_ERR_EOF_INT_ENA_V 0x00000001 +#define SPI_IN_ERR_EOF_INT_ENA_S 4 + +/* SPI_IN_DONE_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for completing usage of a inlink descriptor. + */ + +#define SPI_IN_DONE_INT_ENA (BIT(3)) +#define SPI_IN_DONE_INT_ENA_M (SPI_IN_DONE_INT_ENA_V << SPI_IN_DONE_INT_ENA_S) +#define SPI_IN_DONE_INT_ENA_V 0x00000001 +#define SPI_IN_DONE_INT_ENA_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for inlink descriptor error. + */ + +#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (SPI_INLINK_DSCR_ERROR_INT_ENA_V << SPI_INLINK_DSCR_ERROR_INT_ENA_S) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x00000001 +#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for outlink descriptor error. + */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (SPI_OUTLINK_DSCR_ERROR_INT_ENA_V << SPI_OUTLINK_DSCR_ERROR_INT_ENA_S) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x00000001 +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for lack of enough inlink descriptors. + */ + +#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (SPI_INLINK_DSCR_EMPTY_INT_ENA_V << SPI_INLINK_DSCR_EMPTY_INT_ENA_S) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x00000001 +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 + +/* SPI_DMA_INT_RAW_REG register */ + +#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x68) + +/* SPI_OUT_TOTAL_EOF_INT_RAW : RO; bitpos: [8]; default: 0; + * The raw bit for sending all the packets to host done. + */ + +#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_M (SPI_OUT_TOTAL_EOF_INT_RAW_V << SPI_OUT_TOTAL_EOF_INT_RAW_S) +#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x00000001 +#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 + +/* SPI_OUT_EOF_INT_RAW : RO; bitpos: [7]; default: 0; + * The raw bit for sending a packet to host done. + */ + +#define SPI_OUT_EOF_INT_RAW (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_M (SPI_OUT_EOF_INT_RAW_V << SPI_OUT_EOF_INT_RAW_S) +#define SPI_OUT_EOF_INT_RAW_V 0x00000001 +#define SPI_OUT_EOF_INT_RAW_S 7 + +/* SPI_OUT_DONE_INT_RAW : RO; bitpos: [6]; default: 0; + * The raw bit for completing usage of a outlink descriptor. + */ + +#define SPI_OUT_DONE_INT_RAW (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_M (SPI_OUT_DONE_INT_RAW_V << SPI_OUT_DONE_INT_RAW_S) +#define SPI_OUT_DONE_INT_RAW_V 0x00000001 +#define SPI_OUT_DONE_INT_RAW_S 6 + +/* SPI_IN_SUC_EOF_INT_RAW : RO; bitpos: [5]; default: 0; + * The raw bit for completing receiving all the packets from host. + */ + +#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_M (SPI_IN_SUC_EOF_INT_RAW_V << SPI_IN_SUC_EOF_INT_RAW_S) +#define SPI_IN_SUC_EOF_INT_RAW_V 0x00000001 +#define SPI_IN_SUC_EOF_INT_RAW_S 5 + +/* SPI_IN_ERR_EOF_INT_RAW : RO; bitpos: [4]; default: 0; + * The raw bit for receiving error. + */ + +#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_M (SPI_IN_ERR_EOF_INT_RAW_V << SPI_IN_ERR_EOF_INT_RAW_S) +#define SPI_IN_ERR_EOF_INT_RAW_V 0x00000001 +#define SPI_IN_ERR_EOF_INT_RAW_S 4 + +/* SPI_IN_DONE_INT_RAW : RO; bitpos: [3]; default: 0; + * The raw bit for completing usage of a inlink descriptor. + */ + +#define SPI_IN_DONE_INT_RAW (BIT(3)) +#define SPI_IN_DONE_INT_RAW_M (SPI_IN_DONE_INT_RAW_V << SPI_IN_DONE_INT_RAW_S) +#define SPI_IN_DONE_INT_RAW_V 0x00000001 +#define SPI_IN_DONE_INT_RAW_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO; bitpos: [2]; default: 0; + * The raw bit for inlink descriptor error. + */ + +#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (SPI_INLINK_DSCR_ERROR_INT_RAW_V << SPI_INLINK_DSCR_ERROR_INT_RAW_S) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x00000001 +#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw bit for outlink descriptor error. + */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (SPI_OUTLINK_DSCR_ERROR_INT_RAW_V << SPI_OUTLINK_DSCR_ERROR_INT_RAW_S) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x00000001 +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw bit for lack of enough inlink descriptors. + */ + +#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (SPI_INLINK_DSCR_EMPTY_INT_RAW_V << SPI_INLINK_DSCR_EMPTY_INT_RAW_S) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x00000001 +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 + +/* SPI_DMA_INT_ST_REG register */ + +#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x6c) + +/* SPI_OUT_TOTAL_EOF_INT_ST : RO; bitpos: [8]; default: 0; + * The status bit for sending all the packets to host done. + */ + +#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_M (SPI_OUT_TOTAL_EOF_INT_ST_V << SPI_OUT_TOTAL_EOF_INT_ST_S) +#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x00000001 +#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 + +/* SPI_OUT_EOF_INT_ST : RO; bitpos: [7]; default: 0; + * The status bit for sending a packet to host done. + */ + +#define SPI_OUT_EOF_INT_ST (BIT(7)) +#define SPI_OUT_EOF_INT_ST_M (SPI_OUT_EOF_INT_ST_V << SPI_OUT_EOF_INT_ST_S) +#define SPI_OUT_EOF_INT_ST_V 0x00000001 +#define SPI_OUT_EOF_INT_ST_S 7 + +/* SPI_OUT_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for completing usage of a outlink descriptor. + */ + +#define SPI_OUT_DONE_INT_ST (BIT(6)) +#define SPI_OUT_DONE_INT_ST_M (SPI_OUT_DONE_INT_ST_V << SPI_OUT_DONE_INT_ST_S) +#define SPI_OUT_DONE_INT_ST_V 0x00000001 +#define SPI_OUT_DONE_INT_ST_S 6 + +/* SPI_IN_SUC_EOF_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for completing receiving all the packets from host. + */ + +#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_M (SPI_IN_SUC_EOF_INT_ST_V << SPI_IN_SUC_EOF_INT_ST_S) +#define SPI_IN_SUC_EOF_INT_ST_V 0x00000001 +#define SPI_IN_SUC_EOF_INT_ST_S 5 + +/* SPI_IN_ERR_EOF_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for receiving error. + */ + +#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_M (SPI_IN_ERR_EOF_INT_ST_V << SPI_IN_ERR_EOF_INT_ST_S) +#define SPI_IN_ERR_EOF_INT_ST_V 0x00000001 +#define SPI_IN_ERR_EOF_INT_ST_S 4 + +/* SPI_IN_DONE_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for completing usage of a inlink descriptor. + */ + +#define SPI_IN_DONE_INT_ST (BIT(3)) +#define SPI_IN_DONE_INT_ST_M (SPI_IN_DONE_INT_ST_V << SPI_IN_DONE_INT_ST_S) +#define SPI_IN_DONE_INT_ST_V 0x00000001 +#define SPI_IN_DONE_INT_ST_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for inlink descriptor error. + */ + +#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_M (SPI_INLINK_DSCR_ERROR_INT_ST_V << SPI_INLINK_DSCR_ERROR_INT_ST_S) +#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x00000001 +#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for outlink descriptor error. + */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (SPI_OUTLINK_DSCR_ERROR_INT_ST_V << SPI_OUTLINK_DSCR_ERROR_INT_ST_S) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x00000001 +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for lack of enough inlink descriptors. + */ + +#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (SPI_INLINK_DSCR_EMPTY_INT_ST_V << SPI_INLINK_DSCR_EMPTY_INT_ST_S) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x00000001 +#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 + +/* SPI_DMA_INT_CLR_REG register */ + +#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x70) + +/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W; bitpos: [8]; default: 0; + * The clear bit for sending all the packets to host done. + */ + +#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_M (SPI_OUT_TOTAL_EOF_INT_CLR_V << SPI_OUT_TOTAL_EOF_INT_CLR_S) +#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x00000001 +#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 + +/* SPI_OUT_EOF_INT_CLR : R/W; bitpos: [7]; default: 0; + * The clear bit for sending a packet to host done. + */ + +#define SPI_OUT_EOF_INT_CLR (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_M (SPI_OUT_EOF_INT_CLR_V << SPI_OUT_EOF_INT_CLR_S) +#define SPI_OUT_EOF_INT_CLR_V 0x00000001 +#define SPI_OUT_EOF_INT_CLR_S 7 + +/* SPI_OUT_DONE_INT_CLR : R/W; bitpos: [6]; default: 0; + * The clear bit for completing usage of a outlink descriptor. + */ + +#define SPI_OUT_DONE_INT_CLR (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_M (SPI_OUT_DONE_INT_CLR_V << SPI_OUT_DONE_INT_CLR_S) +#define SPI_OUT_DONE_INT_CLR_V 0x00000001 +#define SPI_OUT_DONE_INT_CLR_S 6 + +/* SPI_IN_SUC_EOF_INT_CLR : R/W; bitpos: [5]; default: 0; + * The clear bit for completing receiving all the packets from host. + */ + +#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_M (SPI_IN_SUC_EOF_INT_CLR_V << SPI_IN_SUC_EOF_INT_CLR_S) +#define SPI_IN_SUC_EOF_INT_CLR_V 0x00000001 +#define SPI_IN_SUC_EOF_INT_CLR_S 5 + +/* SPI_IN_ERR_EOF_INT_CLR : R/W; bitpos: [4]; default: 0; + * The clear bit for receiving error. + */ + +#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_M (SPI_IN_ERR_EOF_INT_CLR_V << SPI_IN_ERR_EOF_INT_CLR_S) +#define SPI_IN_ERR_EOF_INT_CLR_V 0x00000001 +#define SPI_IN_ERR_EOF_INT_CLR_S 4 + +/* SPI_IN_DONE_INT_CLR : R/W; bitpos: [3]; default: 0; + * The clear bit for completing usage of a inlink descriptor. + */ + +#define SPI_IN_DONE_INT_CLR (BIT(3)) +#define SPI_IN_DONE_INT_CLR_M (SPI_IN_DONE_INT_CLR_V << SPI_IN_DONE_INT_CLR_S) +#define SPI_IN_DONE_INT_CLR_V 0x00000001 +#define SPI_IN_DONE_INT_CLR_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W; bitpos: [2]; default: 0; + * The clear bit for inlink descriptor error. + */ + +#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (SPI_INLINK_DSCR_ERROR_INT_CLR_V << SPI_INLINK_DSCR_ERROR_INT_CLR_S) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x00000001 +#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W; bitpos: [1]; default: 0; + * The clear bit for outlink descriptor error. + */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (SPI_OUTLINK_DSCR_ERROR_INT_CLR_V << SPI_OUTLINK_DSCR_ERROR_INT_CLR_S) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x00000001 +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W; bitpos: [0]; default: 0; + * The clear bit for lack of enough inlink descriptors. + */ + +#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (SPI_INLINK_DSCR_EMPTY_INT_CLR_V << SPI_INLINK_DSCR_EMPTY_INT_CLR_S) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x00000001 +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 + +/* SPI_IN_ERR_EOF_DES_ADDR_REG register */ + +#define SPI_IN_ERR_EOF_DES_ADDR_REG (DR_REG_SPI_BASE + 0x74) + +/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The inlink descriptor address when spi dma produce receiving error. + */ + +#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M (SPI_DMA_IN_ERR_EOF_DES_ADDR_V << SPI_DMA_IN_ERR_EOF_DES_ADDR_S) +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 + +/* SPI_IN_SUC_EOF_DES_ADDR_REG register */ + +#define SPI_IN_SUC_EOF_DES_ADDR_REG (DR_REG_SPI_BASE + 0x78) + +/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The last inlink descriptor address when spi dma produce from_suc_eof. + */ + +#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M (SPI_DMA_IN_SUC_EOF_DES_ADDR_V << SPI_DMA_IN_SUC_EOF_DES_ADDR_S) +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 + +/* SPI_INLINK_DSCR_REG register */ + +#define SPI_INLINK_DSCR_REG (DR_REG_SPI_BASE + 0x7c) + +/* SPI_DMA_INLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The content of current in descriptor pointer. + */ + +#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_M (SPI_DMA_INLINK_DSCR_V << SPI_DMA_INLINK_DSCR_S) +#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_S 0 + +/* SPI_INLINK_DSCR_BF0_REG register */ + +#define SPI_INLINK_DSCR_BF0_REG (DR_REG_SPI_BASE + 0x80) + +/* SPI_DMA_INLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The content of next in descriptor pointer. + */ + +#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_M (SPI_DMA_INLINK_DSCR_BF0_V << SPI_DMA_INLINK_DSCR_BF0_S) +#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_S 0 + +/* SPI_INLINK_DSCR_BF1_REG register */ + +#define SPI_INLINK_DSCR_BF1_REG (DR_REG_SPI_BASE + 0x84) + +/* SPI_DMA_INLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The content of current in descriptor data buffer pointer. + */ + +#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_M (SPI_DMA_INLINK_DSCR_BF1_V << SPI_DMA_INLINK_DSCR_BF1_S) +#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_S 0 + +/* SPI_OUT_EOF_BFR_DES_ADDR_REG register */ + +#define SPI_OUT_EOF_BFR_DES_ADDR_REG (DR_REG_SPI_BASE + 0x88) + +/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The address of buffer relative to the outlink descriptor that produce eof. + */ + +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M (SPI_DMA_OUT_EOF_BFR_DES_ADDR_V << SPI_DMA_OUT_EOF_BFR_DES_ADDR_S) +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 + +/* SPI_OUT_EOF_DES_ADDR_REG register */ + +#define SPI_OUT_EOF_DES_ADDR_REG (DR_REG_SPI_BASE + 0x8c) + +/* SPI_DMA_OUT_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The last outlink descriptor address when spi dma produce to_eof. + */ + +#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_M (SPI_DMA_OUT_EOF_DES_ADDR_V << SPI_DMA_OUT_EOF_DES_ADDR_S) +#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 + +/* SPI_OUTLINK_DSCR_REG register */ + +#define SPI_OUTLINK_DSCR_REG (DR_REG_SPI_BASE + 0x90) + +/* SPI_DMA_OUTLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The content of current out descriptor pointer. + */ + +#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_M (SPI_DMA_OUTLINK_DSCR_V << SPI_DMA_OUTLINK_DSCR_S) +#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_S 0 + +/* SPI_OUTLINK_DSCR_BF0_REG register */ + +#define SPI_OUTLINK_DSCR_BF0_REG (DR_REG_SPI_BASE + 0x94) + +/* SPI_DMA_OUTLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The content of next out descriptor pointer. + */ + +#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_M (SPI_DMA_OUTLINK_DSCR_BF0_V << SPI_DMA_OUTLINK_DSCR_BF0_S) +#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 + +/* SPI_OUTLINK_DSCR_BF1_REG register */ + +#define SPI_OUTLINK_DSCR_BF1_REG (DR_REG_SPI_BASE + 0x98) + +/* SPI_DMA_OUTLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The content of current out descriptor data buffer pointer. + */ + +#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_M (SPI_DMA_OUTLINK_DSCR_BF1_V << SPI_DMA_OUTLINK_DSCR_BF1_S) +#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 + +/* SPI_DMA_OUTSTATUS_REG register */ + +#define SPI_DMA_OUTSTATUS_REG (DR_REG_SPI_BASE + 0x9c) + +/* SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * SPI dma outfifo is empty. + */ + +#define SPI_DMA_OUTFIFO_EMPTY (BIT(31)) +#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_S 31 + +/* SPI_DMA_OUTFIFO_FULL : RO; bitpos: [30]; default: 0; + * SPI dma outfifo is full. + */ + +#define SPI_DMA_OUTFIFO_FULL (BIT(30)) +#define SPI_DMA_OUTFIFO_FULL_M (SPI_DMA_OUTFIFO_FULL_V << SPI_DMA_OUTFIFO_FULL_S) +#define SPI_DMA_OUTFIFO_FULL_V 0x00000001 +#define SPI_DMA_OUTFIFO_FULL_S 30 + +/* SPI_DMA_OUTFIFO_CNT : RO; bitpos: [29:23]; default: 0; + * The remains of SPI dma outfifo data. + */ + +#define SPI_DMA_OUTFIFO_CNT 0x0000007F +#define SPI_DMA_OUTFIFO_CNT_M (SPI_DMA_OUTFIFO_CNT_V << SPI_DMA_OUTFIFO_CNT_S) +#define SPI_DMA_OUTFIFO_CNT_V 0x0000007F +#define SPI_DMA_OUTFIFO_CNT_S 23 + +/* SPI_DMA_OUT_STATE : RO; bitpos: [22:20]; default: 0; + * SPI dma out data state. + */ + +#define SPI_DMA_OUT_STATE 0x00000007 +#define SPI_DMA_OUT_STATE_M (SPI_DMA_OUT_STATE_V << SPI_DMA_OUT_STATE_S) +#define SPI_DMA_OUT_STATE_V 0x00000007 +#define SPI_DMA_OUT_STATE_S 20 + +/* SPI_DMA_OUTDSCR_STATE : RO; bitpos: [19:18]; default: 0; + * SPI dma out descriptor state. + */ + +#define SPI_DMA_OUTDSCR_STATE 0x00000003 +#define SPI_DMA_OUTDSCR_STATE_M (SPI_DMA_OUTDSCR_STATE_V << SPI_DMA_OUTDSCR_STATE_S) +#define SPI_DMA_OUTDSCR_STATE_V 0x00000003 +#define SPI_DMA_OUTDSCR_STATE_S 18 + +/* SPI_DMA_OUTDSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * SPI dma out descriptor address. + */ + +#define SPI_DMA_OUTDSCR_ADDR 0x0003FFFF +#define SPI_DMA_OUTDSCR_ADDR_M (SPI_DMA_OUTDSCR_ADDR_V << SPI_DMA_OUTDSCR_ADDR_S) +#define SPI_DMA_OUTDSCR_ADDR_V 0x0003FFFF +#define SPI_DMA_OUTDSCR_ADDR_S 0 + +/* SPI_DMA_INSTATUS_REG register */ + +#define SPI_DMA_INSTATUS_REG (DR_REG_SPI_BASE + 0xa0) + +/* SPI_DMA_INFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * SPI dma infifo is empty. + */ + +#define SPI_DMA_INFIFO_EMPTY (BIT(31)) +#define SPI_DMA_INFIFO_EMPTY_M (SPI_DMA_INFIFO_EMPTY_V << SPI_DMA_INFIFO_EMPTY_S) +#define SPI_DMA_INFIFO_EMPTY_V 0x00000001 +#define SPI_DMA_INFIFO_EMPTY_S 31 + +/* SPI_DMA_INFIFO_FULL : RO; bitpos: [30]; default: 0; + * SPI dma infifo is full. + */ + +#define SPI_DMA_INFIFO_FULL (BIT(30)) +#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) +#define SPI_DMA_INFIFO_FULL_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_S 30 + +/* SPI_DMA_INFIFO_CNT : RO; bitpos: [29:23]; default: 0; + * The remains of SPI dma infifo data. + */ + +#define SPI_DMA_INFIFO_CNT 0x0000007F +#define SPI_DMA_INFIFO_CNT_M (SPI_DMA_INFIFO_CNT_V << SPI_DMA_INFIFO_CNT_S) +#define SPI_DMA_INFIFO_CNT_V 0x0000007F +#define SPI_DMA_INFIFO_CNT_S 23 + +/* SPI_DMA_IN_STATE : RO; bitpos: [22:20]; default: 0; + * SPI dma in data state. + */ + +#define SPI_DMA_IN_STATE 0x00000007 +#define SPI_DMA_IN_STATE_M (SPI_DMA_IN_STATE_V << SPI_DMA_IN_STATE_S) +#define SPI_DMA_IN_STATE_V 0x00000007 +#define SPI_DMA_IN_STATE_S 20 + +/* SPI_DMA_INDSCR_STATE : RO; bitpos: [19:18]; default: 0; + * SPI dma in descriptor state. + */ + +#define SPI_DMA_INDSCR_STATE 0x00000003 +#define SPI_DMA_INDSCR_STATE_M (SPI_DMA_INDSCR_STATE_V << SPI_DMA_INDSCR_STATE_S) +#define SPI_DMA_INDSCR_STATE_V 0x00000003 +#define SPI_DMA_INDSCR_STATE_S 18 + +/* SPI_DMA_INDSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * SPI dma in descriptor address. + */ + +#define SPI_DMA_INDSCR_ADDR 0x0003FFFF +#define SPI_DMA_INDSCR_ADDR_M (SPI_DMA_INDSCR_ADDR_V << SPI_DMA_INDSCR_ADDR_S) +#define SPI_DMA_INDSCR_ADDR_V 0x0003FFFF +#define SPI_DMA_INDSCR_ADDR_S 0 + +/* SPI_W0_REG register */ + +#define SPI_W0_REG (DR_REG_SPI_BASE + 0xa4) + +/* SPI_BUF0 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +/* SPI_W1_REG register */ + +#define SPI_W1_REG (DR_REG_SPI_BASE + 0xa8) + +/* SPI_BUF1 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +/* SPI_W2_REG register */ + +#define SPI_W2_REG (DR_REG_SPI_BASE + 0xac) + +/* SPI_BUF2 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +/* SPI_W3_REG register */ + +#define SPI_W3_REG (DR_REG_SPI_BASE + 0xb0) + +/* SPI_BUF3 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +/* SPI_W4_REG register */ + +#define SPI_W4_REG (DR_REG_SPI_BASE + 0xb4) + +/* SPI_BUF4 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +/* SPI_W5_REG register */ + +#define SPI_W5_REG (DR_REG_SPI_BASE + 0xb8) + +/* SPI_BUF5 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +/* SPI_W6_REG register */ + +#define SPI_W6_REG (DR_REG_SPI_BASE + 0xbc) + +/* SPI_BUF6 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +/* SPI_W7_REG register */ + +#define SPI_W7_REG (DR_REG_SPI_BASE + 0xc0) + +/* SPI_BUF7 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +/* SPI_W8_REG register */ + +#define SPI_W8_REG (DR_REG_SPI_BASE + 0xc4) + +/* SPI_BUF8 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +/* SPI_W9_REG register */ + +#define SPI_W9_REG (DR_REG_SPI_BASE + 0xc8) + +/* SPI_BUF9 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +/* SPI_W10_REG register */ + +#define SPI_W10_REG (DR_REG_SPI_BASE + 0xcc) + +/* SPI_BUF10 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +/* SPI_W11_REG register */ + +#define SPI_W11_REG (DR_REG_SPI_BASE + 0xd0) + +/* SPI_BUF11 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +/* SPI_W12_REG register */ + +#define SPI_W12_REG (DR_REG_SPI_BASE + 0xd4) + +/* SPI_BUF12 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +/* SPI_W13_REG register */ + +#define SPI_W13_REG (DR_REG_SPI_BASE + 0xd8) + +/* SPI_BUF13 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +/* SPI_W14_REG register */ + +#define SPI_W14_REG (DR_REG_SPI_BASE + 0xdc) + +/* SPI_BUF14 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +/* SPI_W15_REG register */ + +#define SPI_W15_REG (DR_REG_SPI_BASE + 0xe0) + +/* SPI_BUF15 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +/* SPI_W16_REG register */ + +#define SPI_W16_REG (DR_REG_SPI_BASE + 0xe4) + +/* SPI_BUF16 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF16 0xFFFFFFFF +#define SPI_BUF16_M (SPI_BUF16_V << SPI_BUF16_S) +#define SPI_BUF16_V 0xFFFFFFFF +#define SPI_BUF16_S 0 + +/* SPI_W17_REG register */ + +#define SPI_W17_REG (DR_REG_SPI_BASE + 0xe8) + +/* SPI_BUF17 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF17 0xFFFFFFFF +#define SPI_BUF17_M (SPI_BUF17_V << SPI_BUF17_S) +#define SPI_BUF17_V 0xFFFFFFFF +#define SPI_BUF17_S 0 + +/* SPI_DIN_MODE_REG register */ + +#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0xec) + +/* SPI_TIMING_CLK_ENA : R/W; bitpos: [24]; default: 0; + * 1:enable hclk in spi_timing.v. 0: disable it. + */ + +#define SPI_TIMING_CLK_ENA (BIT(24)) +#define SPI_TIMING_CLK_ENA_M (SPI_TIMING_CLK_ENA_V << SPI_TIMING_CLK_ENA_S) +#define SPI_TIMING_CLK_ENA_V 0x00000001 +#define SPI_TIMING_CLK_ENA_S 24 + +/* SPI_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN7_MODE 0x00000007 +#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S) +#define SPI_DIN7_MODE_V 0x00000007 +#define SPI_DIN7_MODE_S 21 + +/* SPI_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN6_MODE 0x00000007 +#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S) +#define SPI_DIN6_MODE_V 0x00000007 +#define SPI_DIN6_MODE_S 18 + +/* SPI_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN5_MODE 0x00000007 +#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S) +#define SPI_DIN5_MODE_V 0x00000007 +#define SPI_DIN5_MODE_S 15 + +/* SPI_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN4_MODE 0x00000007 +#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S) +#define SPI_DIN4_MODE_V 0x00000007 +#define SPI_DIN4_MODE_S 12 + +/* SPI_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN3_MODE 0x00000007 +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000007 +#define SPI_DIN3_MODE_S 9 + +/* SPI_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN2_MODE 0x00000007 +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000007 +#define SPI_DIN2_MODE_S 6 + +/* SPI_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN1_MODE 0x00000007 +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000007 +#define SPI_DIN1_MODE_S 3 + +/* SPI_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN0_MODE 0x00000007 +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000007 +#define SPI_DIN0_MODE_S 0 + +/* SPI_DIN_NUM_REG register */ + +#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0xf0) + +/* SPI_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN7_NUM 0x00000003 +#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S) +#define SPI_DIN7_NUM_V 0x00000003 +#define SPI_DIN7_NUM_S 14 + +/* SPI_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN6_NUM 0x00000003 +#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S) +#define SPI_DIN6_NUM_V 0x00000003 +#define SPI_DIN6_NUM_S 12 + +/* SPI_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN5_NUM 0x00000003 +#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S) +#define SPI_DIN5_NUM_V 0x00000003 +#define SPI_DIN5_NUM_S 10 + +/* SPI_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN4_NUM 0x00000003 +#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S) +#define SPI_DIN4_NUM_V 0x00000003 +#define SPI_DIN4_NUM_S 8 + +/* SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN3_NUM 0x00000003 +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003 +#define SPI_DIN3_NUM_S 6 + +/* SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN2_NUM 0x00000003 +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003 +#define SPI_DIN2_NUM_S 4 + +/* SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN1_NUM 0x00000003 +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003 +#define SPI_DIN1_NUM_S 2 + +/* SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN0_NUM 0x00000003 +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003 +#define SPI_DIN0_NUM_S 0 + +/* SPI_DOUT_MODE_REG register */ + +#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0xf4) + +/* SPI_DOUT7_MODE : R/W; bitpos: [23:21]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT7_MODE 0x00000007 +#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S) +#define SPI_DOUT7_MODE_V 0x00000007 +#define SPI_DOUT7_MODE_S 21 + +/* SPI_DOUT6_MODE : R/W; bitpos: [20:18]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT6_MODE 0x00000007 +#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S) +#define SPI_DOUT6_MODE_V 0x00000007 +#define SPI_DOUT6_MODE_S 18 + +/* SPI_DOUT5_MODE : R/W; bitpos: [17:15]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT5_MODE 0x00000007 +#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S) +#define SPI_DOUT5_MODE_V 0x00000007 +#define SPI_DOUT5_MODE_S 15 + +/* SPI_DOUT4_MODE : R/W; bitpos: [14:12]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT4_MODE 0x00000007 +#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S) +#define SPI_DOUT4_MODE_V 0x00000007 +#define SPI_DOUT4_MODE_S 12 + +/* SPI_DOUT3_MODE : R/W; bitpos: [11:9]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT3_MODE 0x00000007 +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000007 +#define SPI_DOUT3_MODE_S 9 + +/* SPI_DOUT2_MODE : R/W; bitpos: [8:6]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT2_MODE 0x00000007 +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000007 +#define SPI_DOUT2_MODE_S 6 + +/* SPI_DOUT1_MODE : R/W; bitpos: [5:3]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT1_MODE 0x00000007 +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000007 +#define SPI_DOUT1_MODE_S 3 + +/* SPI_DOUT0_MODE : R/W; bitpos: [2:0]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT0_MODE 0x00000007 +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000007 +#define SPI_DOUT0_MODE_S 0 + +/* SPI_DOUT_NUM_REG register */ + +#define SPI_DOUT_NUM_REG (DR_REG_SPI_BASE + 0xf8) + +/* SPI_DOUT7_NUM : R/W; bitpos: [15:14]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT7_NUM 0x00000003 +#define SPI_DOUT7_NUM_M (SPI_DOUT7_NUM_V << SPI_DOUT7_NUM_S) +#define SPI_DOUT7_NUM_V 0x00000003 +#define SPI_DOUT7_NUM_S 14 + +/* SPI_DOUT6_NUM : R/W; bitpos: [13:12]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT6_NUM 0x00000003 +#define SPI_DOUT6_NUM_M (SPI_DOUT6_NUM_V << SPI_DOUT6_NUM_S) +#define SPI_DOUT6_NUM_V 0x00000003 +#define SPI_DOUT6_NUM_S 12 + +/* SPI_DOUT5_NUM : R/W; bitpos: [11:10]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT5_NUM 0x00000003 +#define SPI_DOUT5_NUM_M (SPI_DOUT5_NUM_V << SPI_DOUT5_NUM_S) +#define SPI_DOUT5_NUM_V 0x00000003 +#define SPI_DOUT5_NUM_S 10 + +/* SPI_DOUT4_NUM : R/W; bitpos: [9:8]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT4_NUM 0x00000003 +#define SPI_DOUT4_NUM_M (SPI_DOUT4_NUM_V << SPI_DOUT4_NUM_S) +#define SPI_DOUT4_NUM_V 0x00000003 +#define SPI_DOUT4_NUM_S 8 + +/* SPI_DOUT3_NUM : R/W; bitpos: [7:6]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT3_NUM 0x00000003 +#define SPI_DOUT3_NUM_M (SPI_DOUT3_NUM_V << SPI_DOUT3_NUM_S) +#define SPI_DOUT3_NUM_V 0x00000003 +#define SPI_DOUT3_NUM_S 6 + +/* SPI_DOUT2_NUM : R/W; bitpos: [5:4]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT2_NUM 0x00000003 +#define SPI_DOUT2_NUM_M (SPI_DOUT2_NUM_V << SPI_DOUT2_NUM_S) +#define SPI_DOUT2_NUM_V 0x00000003 +#define SPI_DOUT2_NUM_S 4 + +/* SPI_DOUT1_NUM : R/W; bitpos: [3:2]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT1_NUM 0x00000003 +#define SPI_DOUT1_NUM_M (SPI_DOUT1_NUM_V << SPI_DOUT1_NUM_S) +#define SPI_DOUT1_NUM_V 0x00000003 +#define SPI_DOUT1_NUM_S 2 + +/* SPI_DOUT0_NUM : R/W; bitpos: [1:0]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT0_NUM 0x00000003 +#define SPI_DOUT0_NUM_M (SPI_DOUT0_NUM_V << SPI_DOUT0_NUM_S) +#define SPI_DOUT0_NUM_V 0x00000003 +#define SPI_DOUT0_NUM_S 0 + +/* SPI_LCD_CTRL_REG register */ + +#define SPI_LCD_CTRL_REG (DR_REG_SPI_BASE + 0xfc) + +/* SPI_LCD_SRGB_MODE_EN : R/W; bitpos: [31]; default: 0; + * 1: Enable LCD mode output vsync, hsync, de. 0: Disable. + */ + +#define SPI_LCD_SRGB_MODE_EN (BIT(31)) +#define SPI_LCD_SRGB_MODE_EN_M (SPI_LCD_SRGB_MODE_EN_V << SPI_LCD_SRGB_MODE_EN_S) +#define SPI_LCD_SRGB_MODE_EN_V 0x00000001 +#define SPI_LCD_SRGB_MODE_EN_S 31 + +/* SPI_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0; + * It is the vertical total height of a frame. + */ + +#define SPI_LCD_VT_HEIGHT 0x000003FF +#define SPI_LCD_VT_HEIGHT_M (SPI_LCD_VT_HEIGHT_V << SPI_LCD_VT_HEIGHT_S) +#define SPI_LCD_VT_HEIGHT_V 0x000003FF +#define SPI_LCD_VT_HEIGHT_S 21 + +/* SPI_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0; + * It is the vertical active height of a frame. + */ + +#define SPI_LCD_VA_HEIGHT 0x000003FF +#define SPI_LCD_VA_HEIGHT_M (SPI_LCD_VA_HEIGHT_V << SPI_LCD_VA_HEIGHT_S) +#define SPI_LCD_VA_HEIGHT_V 0x000003FF +#define SPI_LCD_VA_HEIGHT_S 11 + +/* SPI_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0; + * It is the horizontal blank front porch of a frame. + */ + +#define SPI_LCD_HB_FRONT 0x000007FF +#define SPI_LCD_HB_FRONT_M (SPI_LCD_HB_FRONT_V << SPI_LCD_HB_FRONT_S) +#define SPI_LCD_HB_FRONT_V 0x000007FF +#define SPI_LCD_HB_FRONT_S 0 + +/* SPI_LCD_CTRL1_REG register */ + +#define SPI_LCD_CTRL1_REG (DR_REG_SPI_BASE + 0x100) + +/* SPI_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0; + * It is the horizontal total width of a frame. + */ + +#define SPI_LCD_HT_WIDTH 0x00000FFF +#define SPI_LCD_HT_WIDTH_M (SPI_LCD_HT_WIDTH_V << SPI_LCD_HT_WIDTH_S) +#define SPI_LCD_HT_WIDTH_V 0x00000FFF +#define SPI_LCD_HT_WIDTH_S 20 + +/* SPI_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0; + * It is the horizontal active width of a frame. + */ + +#define SPI_LCD_HA_WIDTH 0x00000FFF +#define SPI_LCD_HA_WIDTH_M (SPI_LCD_HA_WIDTH_V << SPI_LCD_HA_WIDTH_S) +#define SPI_LCD_HA_WIDTH_V 0x00000FFF +#define SPI_LCD_HA_WIDTH_S 8 + +/* SPI_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0; + * It is the vertical blank front porch of a frame. + */ + +#define SPI_LCD_VB_FRONT 0x000000FF +#define SPI_LCD_VB_FRONT_M (SPI_LCD_VB_FRONT_V << SPI_LCD_VB_FRONT_S) +#define SPI_LCD_VB_FRONT_V 0x000000FF +#define SPI_LCD_VB_FRONT_S 0 + +/* SPI_LCD_CTRL2_REG register */ + +#define SPI_LCD_CTRL2_REG (DR_REG_SPI_BASE + 0x104) + +/* SPI_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0; + * It is the position of spi_hsync_out active pulse in a line. + */ + +#define SPI_LCD_HSYNC_POSITION 0x000000FF +#define SPI_LCD_HSYNC_POSITION_M (SPI_LCD_HSYNC_POSITION_V << SPI_LCD_HSYNC_POSITION_S) +#define SPI_LCD_HSYNC_POSITION_V 0x000000FF +#define SPI_LCD_HSYNC_POSITION_S 24 + +/* SPI_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0; + * It is the idle value of spi_hsync_out. + */ + +#define SPI_HSYNC_IDLE_POL (BIT(23)) +#define SPI_HSYNC_IDLE_POL_M (SPI_HSYNC_IDLE_POL_V << SPI_HSYNC_IDLE_POL_S) +#define SPI_HSYNC_IDLE_POL_V 0x00000001 +#define SPI_HSYNC_IDLE_POL_S 23 + +/* SPI_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 0; + * It is the position of spi_hsync_out active pulse in a line. + */ + +#define SPI_LCD_HSYNC_WIDTH 0x0000007F +#define SPI_LCD_HSYNC_WIDTH_M (SPI_LCD_HSYNC_WIDTH_V << SPI_LCD_HSYNC_WIDTH_S) +#define SPI_LCD_HSYNC_WIDTH_V 0x0000007F +#define SPI_LCD_HSYNC_WIDTH_S 16 + +/* SPI_LCD_VSYNC_POSITION : R/W; bitpos: [15:8]; default: 0; + * It is the position of spi_vsync_out active pulse in a line. + */ + +#define SPI_LCD_VSYNC_POSITION 0x000000FF +#define SPI_LCD_VSYNC_POSITION_M (SPI_LCD_VSYNC_POSITION_V << SPI_LCD_VSYNC_POSITION_S) +#define SPI_LCD_VSYNC_POSITION_V 0x000000FF +#define SPI_LCD_VSYNC_POSITION_S 8 + +/* SPI_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0; + * It is the idle value of spi_vsync_out. + */ + +#define SPI_VSYNC_IDLE_POL (BIT(7)) +#define SPI_VSYNC_IDLE_POL_M (SPI_VSYNC_IDLE_POL_V << SPI_VSYNC_IDLE_POL_S) +#define SPI_VSYNC_IDLE_POL_V 0x00000001 +#define SPI_VSYNC_IDLE_POL_S 7 + +/* SPI_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 0; + * It is the position of spi_vsync_out active pulse in a line. + */ + +#define SPI_LCD_VSYNC_WIDTH 0x0000007F +#define SPI_LCD_VSYNC_WIDTH_M (SPI_LCD_VSYNC_WIDTH_V << SPI_LCD_VSYNC_WIDTH_S) +#define SPI_LCD_VSYNC_WIDTH_V 0x0000007F +#define SPI_LCD_VSYNC_WIDTH_S 0 + +/* SPI_LCD_D_MODE_REG register */ + +#define SPI_LCD_D_MODE_REG (DR_REG_SPI_BASE + 0x108) + +/* SPI_D_VSYNC_MODE : R/W; bitpos: [14:12]; default: 0; + * Configure the output spi_vsync delay mode. 0: without delayed, 1: with + * the posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the + * posedge of hclk, whose frequency is the double of the clk_apb frequency, + * 4: with the negedge of hclk, 5: with the posedge of spi_clk, 6: with the + * negedge of spi_clk. + */ + +#define SPI_D_VSYNC_MODE 0x00000007 +#define SPI_D_VSYNC_MODE_M (SPI_D_VSYNC_MODE_V << SPI_D_VSYNC_MODE_S) +#define SPI_D_VSYNC_MODE_V 0x00000007 +#define SPI_D_VSYNC_MODE_S 12 + +/* SPI_D_HSYNC_MODE : R/W; bitpos: [11:9]; default: 0; + * Configure the output spi_hsync delay mode. 0: without delayed, 1: with + * the posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the + * posedge of hclk, whose frequency is the double of the clk_apb frequency, + * 4: with the negedge of hclk, 5: with the posedge of spi_clk, 6: with the + * negedge of spi_clk. + */ + +#define SPI_D_HSYNC_MODE 0x00000007 +#define SPI_D_HSYNC_MODE_M (SPI_D_HSYNC_MODE_V << SPI_D_HSYNC_MODE_S) +#define SPI_D_HSYNC_MODE_V 0x00000007 +#define SPI_D_HSYNC_MODE_S 9 + +/* SPI_D_DE_MODE : R/W; bitpos: [8:6]; default: 0; + * Configure the output spi_de delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_D_DE_MODE 0x00000007 +#define SPI_D_DE_MODE_M (SPI_D_DE_MODE_V << SPI_D_DE_MODE_S) +#define SPI_D_DE_MODE_V 0x00000007 +#define SPI_D_DE_MODE_S 6 + +/* SPI_D_CD_MODE : R/W; bitpos: [5:3]; default: 0; + * Configure the output spi_cd delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_D_CD_MODE 0x00000007 +#define SPI_D_CD_MODE_M (SPI_D_CD_MODE_V << SPI_D_CD_MODE_S) +#define SPI_D_CD_MODE_V 0x00000007 +#define SPI_D_CD_MODE_S 3 + +/* SPI_D_DQS_MODE : R/W; bitpos: [2:0]; default: 0; + * Configure the output spi_dqs delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_D_DQS_MODE 0x00000007 +#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S) +#define SPI_D_DQS_MODE_V 0x00000007 +#define SPI_D_DQS_MODE_S 0 + +/* SPI_LCD_D_NUM_REG register */ + +#define SPI_LCD_D_NUM_REG (DR_REG_SPI_BASE + 0x10c) + +/* SPI_D_VSYNC_NUM : R/W; bitpos: [9:8]; default: 0; + * the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_VSYNC_NUM 0x00000003 +#define SPI_D_VSYNC_NUM_M (SPI_D_VSYNC_NUM_V << SPI_D_VSYNC_NUM_S) +#define SPI_D_VSYNC_NUM_V 0x00000003 +#define SPI_D_VSYNC_NUM_S 8 + +/* SPI_D_HSYNC_NUM : R/W; bitpos: [7:6]; default: 0; + * the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_HSYNC_NUM 0x00000003 +#define SPI_D_HSYNC_NUM_M (SPI_D_HSYNC_NUM_V << SPI_D_HSYNC_NUM_S) +#define SPI_D_HSYNC_NUM_V 0x00000003 +#define SPI_D_HSYNC_NUM_S 6 + +/* SPI_D_DE_NUM : R/W; bitpos: [5:4]; default: 0; + * the output spi_de is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_DE_NUM 0x00000003 +#define SPI_D_DE_NUM_M (SPI_D_DE_NUM_V << SPI_D_DE_NUM_S) +#define SPI_D_DE_NUM_V 0x00000003 +#define SPI_D_DE_NUM_S 4 + +/* SPI_D_CD_NUM : R/W; bitpos: [3:2]; default: 0; + * the output spi_cd is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_CD_NUM 0x00000003 +#define SPI_D_CD_NUM_M (SPI_D_CD_NUM_V << SPI_D_CD_NUM_S) +#define SPI_D_CD_NUM_V 0x00000003 +#define SPI_D_CD_NUM_S 2 + +/* SPI_D_DQS_NUM : R/W; bitpos: [1:0]; default: 0; + * the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_DQS_NUM 0x00000003 +#define SPI_D_DQS_NUM_M (SPI_D_DQS_NUM_V << SPI_D_DQS_NUM_S) +#define SPI_D_DQS_NUM_V 0x00000003 +#define SPI_D_DQS_NUM_S 0 + +/* SPI_REG_DATE_REG register */ + +#define SPI_REG_DATE_REG (DR_REG_SPI_BASE + 0x3fc) + +/* SPI_DATE : RW; bitpos: [27:0]; default: 26222993; + * SPI register version. + */ + +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFF +#define SPI_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h new file mode 100644 index 00000000000..884298bc197 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h @@ -0,0 +1,1465 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_system.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSTEM_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSTEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SYSTEM_ROM_CTRL_0_REG register + * System ROM configuration register 0 + */ + +#define SYSTEM_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x0) + +/* SYSTEM_ROM_FO : R/W; bitpos: [1:0]; default: 3; + * This field is used to force on clock gate of internal ROM. + */ + +#define SYSTEM_ROM_FO 0x00000003 +#define SYSTEM_ROM_FO_M (SYSTEM_ROM_FO_V << SYSTEM_ROM_FO_S) +#define SYSTEM_ROM_FO_V 0x00000003 +#define SYSTEM_ROM_FO_S 0 + +/* SYSTEM_ROM_CTRL_1_REG register + * System ROM configuration register 1 + */ + +#define SYSTEM_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x4) + +/* SYSTEM_ROM_FORCE_PU : R/W; bitpos: [3:2]; default: 3; + * This field is used to power up internal ROM. + */ + +#define SYSTEM_ROM_FORCE_PU 0x00000003 +#define SYSTEM_ROM_FORCE_PU_M (SYSTEM_ROM_FORCE_PU_V << SYSTEM_ROM_FORCE_PU_S) +#define SYSTEM_ROM_FORCE_PU_V 0x00000003 +#define SYSTEM_ROM_FORCE_PU_S 2 + +/* SYSTEM_ROM_FORCE_PD : R/W; bitpos: [1:0]; default: 0; + * This field is used to power down internal ROM. + */ + +#define SYSTEM_ROM_FORCE_PD 0x00000003 +#define SYSTEM_ROM_FORCE_PD_M (SYSTEM_ROM_FORCE_PD_V << SYSTEM_ROM_FORCE_PD_S) +#define SYSTEM_ROM_FORCE_PD_V 0x00000003 +#define SYSTEM_ROM_FORCE_PD_S 0 + +/* SYSTEM_SRAM_CTRL_0_REG register + * System SRAM configuration register 0 + */ + +#define SYSTEM_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x8) + +/* SYSTEM_SRAM_FO : R/W; bitpos: [21:0]; default: 4194303; + * This field is used to force on clock gate of internal SRAM. + */ + +#define SYSTEM_SRAM_FO 0x003FFFFF +#define SYSTEM_SRAM_FO_M (SYSTEM_SRAM_FO_V << SYSTEM_SRAM_FO_S) +#define SYSTEM_SRAM_FO_V 0x003FFFFF +#define SYSTEM_SRAM_FO_S 0 + +/* SYSTEM_SRAM_CTRL_1_REG register + * System SRAM configuration register 1 + */ + +#define SYSTEM_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0xc) + +/* SYSTEM_SRAM_FORCE_PD : R/W; bitpos: [21:0]; default: 0; + * This field is used to power down internal SRAM. + */ + +#define SYSTEM_SRAM_FORCE_PD 0x003FFFFF +#define SYSTEM_SRAM_FORCE_PD_M (SYSTEM_SRAM_FORCE_PD_V << SYSTEM_SRAM_FORCE_PD_S) +#define SYSTEM_SRAM_FORCE_PD_V 0x003FFFFF +#define SYSTEM_SRAM_FORCE_PD_S 0 + +/* SYSTEM_CPU_PERI_CLK_EN_REG register + * CPU peripheral clock enable register + */ + +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x10) + +/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0; + * Set this bit to enable clock of DEDICATED GPIO module. + */ + +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x00000001 +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 + +/* SYSTEM_CPU_PERI_RST_EN_REG register + * CPU peripheral reset register + */ + +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x14) + +/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1; + * Set this bit to reset DEDICATED GPIO module. + */ + +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x00000001 +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 + +/* SYSTEM_CPU_PER_CONF_REG register + * CPU peripheral clock configuration register + */ + +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x18) +#define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018) /* old name */ + +/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * Sets the number of delay cycles to enter CPU wait mode after a WAITI + * instruction. + */ + +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 + +/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set this bit to force on CPU wait mode. In this mode, the clock gate of + * CPU is turned off until any interrupts happen. This mode could also be + * force on via WAITI instruction. + */ + +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x00000001 +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 + +/* SYSTEM_PLL_FREQ_SEL : R/W; bitpos: [2]; default: 1; + * This field is used to select the PLL clock frequency based on CPU period. + */ + +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (SYSTEM_PLL_FREQ_SEL_V << SYSTEM_PLL_FREQ_SEL_S) +#define SYSTEM_PLL_FREQ_SEL_V 0x00000001 +#define SYSTEM_PLL_FREQ_SEL_S 2 + +/* SYSTEM_CPUPERIOD_SEL : R/W; bitpos: [1:0]; default: 0; + * This field is used to select the clock frequency of CPU or CPU period. + */ + +#define SYSTEM_CPUPERIOD_SEL 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_M (SYSTEM_CPUPERIOD_SEL_V << SYSTEM_CPUPERIOD_SEL_S) +#define SYSTEM_CPUPERIOD_SEL_V 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_S 0 + +/* SYSTEM_JTAG_CTRL_0_REG register + * JTAG configuration register 0 + */ + +#define SYSTEM_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x1c) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 0 to 31 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 + +/* SYSTEM_JTAG_CTRL_1_REG register + * JTAG configuration register 1 + */ + +#define SYSTEM_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x20) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 32 to 63 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 + +/* SYSTEM_JTAG_CTRL_2_REG register + * JTAG configuration register 2 + */ + +#define SYSTEM_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x24) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 64 to 95 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 + +/* SYSTEM_JTAG_CTRL_3_REG register + * JTAG configuration register 3 + */ + +#define SYSTEM_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x28) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 96 to 127 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 + +/* SYSTEM_JTAG_CTRL_4_REG register + * JTAG configuration register 4 + */ + +#define SYSTEM_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x2c) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 128 to 159 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 + +/* SYSTEM_JTAG_CTRL_5_REG register + * JTAG configuration register 5 + */ + +#define SYSTEM_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x30) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 160 to 191 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 + +/* SYSTEM_JTAG_CTRL_6_REG register + * JTAG configuration register 6 + */ + +#define SYSTEM_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x34) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 192 to 223 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 + +/* SYSTEM_JTAG_CTRL_7_REG register + * JTAG configuration register 7 + */ + +#define SYSTEM_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x38) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 0 to 224 bits of the 255 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 + +/* SYSTEM_MEM_PD_MASK_REG register + * Memory power-related controlling register (under low-sleep) + */ + +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x3c) + +/* SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1; + * Set this bit to allow the memory to work as usual when the chip enters + * the light-sleep state. + */ + +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x00000001 +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 + +/* SYSTEM_PERIP_CLK_EN0_REG register + * System peripheral clock (for hardware accelerators) enable register + */ + +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x40) + +/* SYSTEM_SPI4_CLK_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to enable clock of SPI4. + */ + +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (SYSTEM_SPI4_CLK_EN_V << SYSTEM_SPI4_CLK_EN_S) +#define SYSTEM_SPI4_CLK_EN_V 0x00000001 +#define SYSTEM_SPI4_CLK_EN_S 31 + +/* SYSTEM_ADC2_ARB_CLK_EN : R/W; bitpos: [30]; default: 1; + * Set this bit to enable clock of aribiter of ADC2. + */ + +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (SYSTEM_ADC2_ARB_CLK_EN_V << SYSTEM_ADC2_ARB_CLK_EN_S) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x00000001 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 + +/* SYSTEM_SYSTIMER_CLK_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to enable clock of system timer. + */ + +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (SYSTEM_SYSTIMER_CLK_EN_V << SYSTEM_SYSTIMER_CLK_EN_S) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x00000001 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 + +/* SYSTEM_APB_SARADC_CLK_EN : R/W; bitpos: [28]; default: 1; + * Set this bit to enable clock of SAR ADC. + */ + +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (SYSTEM_APB_SARADC_CLK_EN_V << SYSTEM_APB_SARADC_CLK_EN_S) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x00000001 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 + +/* SYSTEM_SPI3_DMA_CLK_EN : R/W; bitpos: [27]; default: 1; + * Set this bit to enable clock of SPI3 DMA. + */ + +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (SYSTEM_SPI3_DMA_CLK_EN_V << SYSTEM_SPI3_DMA_CLK_EN_S) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x00000001 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 + +/* SYSTEM_PWM3_CLK_EN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable clock of PWM3. + */ + +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (SYSTEM_PWM3_CLK_EN_V << SYSTEM_PWM3_CLK_EN_S) +#define SYSTEM_PWM3_CLK_EN_V 0x00000001 +#define SYSTEM_PWM3_CLK_EN_S 26 + +/* SYSTEM_PWM2_CLK_EN : R/W; bitpos: [25]; default: 0; + * Set this bit to enable clock of PWM2. + */ + +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (SYSTEM_PWM2_CLK_EN_V << SYSTEM_PWM2_CLK_EN_S) +#define SYSTEM_PWM2_CLK_EN_V 0x00000001 +#define SYSTEM_PWM2_CLK_EN_S 25 + +/* SYSTEM_UART_MEM_CLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable clock of UART memory. + */ + +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (SYSTEM_UART_MEM_CLK_EN_V << SYSTEM_UART_MEM_CLK_EN_S) +#define SYSTEM_UART_MEM_CLK_EN_V 0x00000001 +#define SYSTEM_UART_MEM_CLK_EN_S 24 + +/* SYSTEM_USB_CLK_EN : R/W; bitpos: [23]; default: 1; + * Set this bit to enable clock of USB. + */ + +#define SYSTEM_USB_CLK_EN (BIT(23)) +#define SYSTEM_USB_CLK_EN_M (SYSTEM_USB_CLK_EN_V << SYSTEM_USB_CLK_EN_S) +#define SYSTEM_USB_CLK_EN_V 0x00000001 +#define SYSTEM_USB_CLK_EN_S 23 + +/* SYSTEM_SPI2_DMA_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set this bit to enable clock of SPI2 DMA. + */ + +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (SYSTEM_SPI2_DMA_CLK_EN_V << SYSTEM_SPI2_DMA_CLK_EN_S) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x00000001 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 + +/* SYSTEM_I2S1_CLK_EN : R/W; bitpos: [21]; default: 0; + * Set this bit to enable clock of I2S1. + */ + +#define SYSTEM_I2S1_CLK_EN (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_M (SYSTEM_I2S1_CLK_EN_V << SYSTEM_I2S1_CLK_EN_S) +#define SYSTEM_I2S1_CLK_EN_V 0x00000001 +#define SYSTEM_I2S1_CLK_EN_S 21 + +/* SYSTEM_PWM1_CLK_EN : R/W; bitpos: [20]; default: 0; + * Set this bit to enable clock of PWM1. + */ + +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (SYSTEM_PWM1_CLK_EN_V << SYSTEM_PWM1_CLK_EN_S) +#define SYSTEM_PWM1_CLK_EN_V 0x00000001 +#define SYSTEM_PWM1_CLK_EN_S 20 + +/* SYSTEM_CAN_CLK_EN : R/W; bitpos: [19]; default: 0; + * Set this bit to enable clock of CAN. + */ + +#define SYSTEM_CAN_CLK_EN (BIT(19)) +#define SYSTEM_CAN_CLK_EN_M (SYSTEM_CAN_CLK_EN_V << SYSTEM_CAN_CLK_EN_S) +#define SYSTEM_CAN_CLK_EN_V 0x00000001 +#define SYSTEM_CAN_CLK_EN_S 19 + +/* SYSTEM_I2C_EXT1_CLK_EN : R/W; bitpos: [18]; default: 0; + * Set this bit to enable clock of I2C EXT1. + */ + +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (SYSTEM_I2C_EXT1_CLK_EN_V << SYSTEM_I2C_EXT1_CLK_EN_S) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x00000001 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 + +/* SYSTEM_PWM0_CLK_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable clock of PWM0. + */ + +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (SYSTEM_PWM0_CLK_EN_V << SYSTEM_PWM0_CLK_EN_S) +#define SYSTEM_PWM0_CLK_EN_V 0x00000001 +#define SYSTEM_PWM0_CLK_EN_S 17 + +/* SYSTEM_SPI3_CLK_EN : R/W; bitpos: [16]; default: 1; + * Set this bit to enable clock of SPI3. + */ + +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (SYSTEM_SPI3_CLK_EN_V << SYSTEM_SPI3_CLK_EN_S) +#define SYSTEM_SPI3_CLK_EN_V 0x00000001 +#define SYSTEM_SPI3_CLK_EN_S 16 + +/* SYSTEM_TIMERGROUP1_CLK_EN : R/W; bitpos: [15]; default: 1; + * Set this bit to enable clock of timer group1. + */ + +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (SYSTEM_TIMERGROUP1_CLK_EN_V << SYSTEM_TIMERGROUP1_CLK_EN_S) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x00000001 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 + +/* SYSTEM_EFUSE_CLK_EN : R/W; bitpos: [14]; default: 1; + * Set this bit to enable clock of eFuse. + */ + +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (SYSTEM_EFUSE_CLK_EN_V << SYSTEM_EFUSE_CLK_EN_S) +#define SYSTEM_EFUSE_CLK_EN_V 0x00000001 +#define SYSTEM_EFUSE_CLK_EN_S 14 + +/* SYSTEM_TIMERGROUP_CLK_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to enable clock of timer group0. + */ + +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (SYSTEM_TIMERGROUP_CLK_EN_V << SYSTEM_TIMERGROUP_CLK_EN_S) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x00000001 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 + +/* SYSTEM_UHCI1_CLK_EN : R/W; bitpos: [12]; default: 0; + * Set this bit to enable clock of UHCI1. + */ + +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (SYSTEM_UHCI1_CLK_EN_V << SYSTEM_UHCI1_CLK_EN_S) +#define SYSTEM_UHCI1_CLK_EN_V 0x00000001 +#define SYSTEM_UHCI1_CLK_EN_S 12 + +/* SYSTEM_LEDC_CLK_EN : R/W; bitpos: [11]; default: 0; + * Set this bit to enable clock of LED PWM. + */ + +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (SYSTEM_LEDC_CLK_EN_V << SYSTEM_LEDC_CLK_EN_S) +#define SYSTEM_LEDC_CLK_EN_V 0x00000001 +#define SYSTEM_LEDC_CLK_EN_S 11 + +/* SYSTEM_PCNT_CLK_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable clock of pulse count. + */ + +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (SYSTEM_PCNT_CLK_EN_V << SYSTEM_PCNT_CLK_EN_S) +#define SYSTEM_PCNT_CLK_EN_V 0x00000001 +#define SYSTEM_PCNT_CLK_EN_S 10 + +/* SYSTEM_RMT_CLK_EN : R/W; bitpos: [9]; default: 0; + * Set this bit to enable clock of remote controller. + */ + +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (SYSTEM_RMT_CLK_EN_V << SYSTEM_RMT_CLK_EN_S) +#define SYSTEM_RMT_CLK_EN_V 0x00000001 +#define SYSTEM_RMT_CLK_EN_S 9 + +/* SYSTEM_UHCI0_CLK_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable clock of UHCI0. + */ + +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (SYSTEM_UHCI0_CLK_EN_V << SYSTEM_UHCI0_CLK_EN_S) +#define SYSTEM_UHCI0_CLK_EN_V 0x00000001 +#define SYSTEM_UHCI0_CLK_EN_S 8 + +/* SYSTEM_I2C_EXT0_CLK_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable clock of I2C EXT0. + */ + +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (SYSTEM_I2C_EXT0_CLK_EN_V << SYSTEM_I2C_EXT0_CLK_EN_S) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x00000001 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 + +/* SYSTEM_SPI2_CLK_EN : R/W; bitpos: [6]; default: 1; + * Set this bit to enable clock of SPI2. + */ + +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (SYSTEM_SPI2_CLK_EN_V << SYSTEM_SPI2_CLK_EN_S) +#define SYSTEM_SPI2_CLK_EN_V 0x00000001 +#define SYSTEM_SPI2_CLK_EN_S 6 + +/* SYSTEM_UART1_CLK_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to enable clock of UART1. + */ + +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (SYSTEM_UART1_CLK_EN_V << SYSTEM_UART1_CLK_EN_S) +#define SYSTEM_UART1_CLK_EN_V 0x00000001 +#define SYSTEM_UART1_CLK_EN_S 5 + +/* SYSTEM_I2S0_CLK_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable clock of I2S0. + */ + +#define SYSTEM_I2S0_CLK_EN (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_M (SYSTEM_I2S0_CLK_EN_V << SYSTEM_I2S0_CLK_EN_S) +#define SYSTEM_I2S0_CLK_EN_V 0x00000001 +#define SYSTEM_I2S0_CLK_EN_S 4 + +/* SYSTEM_WDG_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set this bit to enable clock of WDG. + */ + +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (SYSTEM_WDG_CLK_EN_V << SYSTEM_WDG_CLK_EN_S) +#define SYSTEM_WDG_CLK_EN_V 0x00000001 +#define SYSTEM_WDG_CLK_EN_S 3 + +/* SYSTEM_UART_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set this bit to enable clock of UART0. + */ + +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (SYSTEM_UART_CLK_EN_V << SYSTEM_UART_CLK_EN_S) +#define SYSTEM_UART_CLK_EN_V 0x00000001 +#define SYSTEM_UART_CLK_EN_S 2 + +/* SYSTEM_SPI01_CLK_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable clock of SPI0 and SPI1. + */ + +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (SYSTEM_SPI01_CLK_EN_V << SYSTEM_SPI01_CLK_EN_S) +#define SYSTEM_SPI01_CLK_EN_V 0x00000001 +#define SYSTEM_SPI01_CLK_EN_S 1 + +/* SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable clock of timers. + */ + +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (SYSTEM_TIMERS_CLK_EN_V << SYSTEM_TIMERS_CLK_EN_S) +#define SYSTEM_TIMERS_CLK_EN_V 0x00000001 +#define SYSTEM_TIMERS_CLK_EN_S 0 + +/* SYSTEM_PERIP_CLK_EN1_REG register + * System peripheral clock (for hardware accelerators) enable register 1 + */ + +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x44) + +/* SYSTEM_CRYPTO_DMA_CLK_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to enable clock of cryptography DMA. + */ + +#define SYSTEM_CRYPTO_DMA_CLK_EN (BIT(6)) +#define SYSTEM_CRYPTO_DMA_CLK_EN_M (SYSTEM_CRYPTO_DMA_CLK_EN_V << SYSTEM_CRYPTO_DMA_CLK_EN_S) +#define SYSTEM_CRYPTO_DMA_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_DMA_CLK_EN_S 6 + +/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable clock of cryptography HMAC. + */ + +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (SYSTEM_CRYPTO_HMAC_CLK_EN_V << SYSTEM_CRYPTO_HMAC_CLK_EN_S) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 + +/* SYSTEM_CRYPTO_DS_CLK_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable clock of cryptography Digital Signature. + */ + +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (SYSTEM_CRYPTO_DS_CLK_EN_V << SYSTEM_CRYPTO_DS_CLK_EN_S) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 + +/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable clock of cryptography RSA. + */ + +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (SYSTEM_CRYPTO_RSA_CLK_EN_V << SYSTEM_CRYPTO_RSA_CLK_EN_S) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 + +/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to enable clock of cryptography SHA. + */ + +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (SYSTEM_CRYPTO_SHA_CLK_EN_V << SYSTEM_CRYPTO_SHA_CLK_EN_S) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 + +/* SYSTEM_CRYPTO_AES_CLK_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable clock of cryptography AES. + */ + +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (SYSTEM_CRYPTO_AES_CLK_EN_V << SYSTEM_CRYPTO_AES_CLK_EN_S) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 + +/* SYSTEM_PERIP_RST_EN0_REG register + * System peripheral (hardware accelerators) reset register 0 + */ + +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x48) + +/* SYSTEM_SPI4_RST : R/W; bitpos: [31]; default: 0; + * Set this bit to reset SPI4. + */ + +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (SYSTEM_SPI4_RST_V << SYSTEM_SPI4_RST_S) +#define SYSTEM_SPI4_RST_V 0x00000001 +#define SYSTEM_SPI4_RST_S 31 + +/* SYSTEM_ADC2_ARB_RST : R/W; bitpos: [30]; default: 0; + * Set this bit to reset aribiter of ADC2. + */ + +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (SYSTEM_ADC2_ARB_RST_V << SYSTEM_ADC2_ARB_RST_S) +#define SYSTEM_ADC2_ARB_RST_V 0x00000001 +#define SYSTEM_ADC2_ARB_RST_S 30 + +/* SYSTEM_SYSTIMER_RST : R/W; bitpos: [29]; default: 0; + * Set this bit to reset system timer. + */ + +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (SYSTEM_SYSTIMER_RST_V << SYSTEM_SYSTIMER_RST_S) +#define SYSTEM_SYSTIMER_RST_V 0x00000001 +#define SYSTEM_SYSTIMER_RST_S 29 + +/* SYSTEM_APB_SARADC_RST : R/W; bitpos: [28]; default: 0; + * Set this bit to reset SAR ADC. + */ + +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (SYSTEM_APB_SARADC_RST_V << SYSTEM_APB_SARADC_RST_S) +#define SYSTEM_APB_SARADC_RST_V 0x00000001 +#define SYSTEM_APB_SARADC_RST_S 28 + +/* SYSTEM_SPI3_DMA_RST : R/W; bitpos: [27]; default: 0; + * Set this bit to reset SPI3 DMA. + */ + +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (SYSTEM_SPI3_DMA_RST_V << SYSTEM_SPI3_DMA_RST_S) +#define SYSTEM_SPI3_DMA_RST_V 0x00000001 +#define SYSTEM_SPI3_DMA_RST_S 27 + +/* SYSTEM_PWM3_RST : R/W; bitpos: [26]; default: 0; + * Set this bit to reset PWM3. + */ + +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (SYSTEM_PWM3_RST_V << SYSTEM_PWM3_RST_S) +#define SYSTEM_PWM3_RST_V 0x00000001 +#define SYSTEM_PWM3_RST_S 26 + +/* SYSTEM_PWM2_RST : R/W; bitpos: [25]; default: 0; + * Set this bit to reset PWM2. + */ + +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (SYSTEM_PWM2_RST_V << SYSTEM_PWM2_RST_S) +#define SYSTEM_PWM2_RST_V 0x00000001 +#define SYSTEM_PWM2_RST_S 25 + +/* SYSTEM_UART_MEM_RST : R/W; bitpos: [24]; default: 0; + * Set this bit to reset UART memory. + */ + +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (SYSTEM_UART_MEM_RST_V << SYSTEM_UART_MEM_RST_S) +#define SYSTEM_UART_MEM_RST_V 0x00000001 +#define SYSTEM_UART_MEM_RST_S 24 + +/* SYSTEM_USB_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset USB. + */ + +#define SYSTEM_USB_RST (BIT(23)) +#define SYSTEM_USB_RST_M (SYSTEM_USB_RST_V << SYSTEM_USB_RST_S) +#define SYSTEM_USB_RST_V 0x00000001 +#define SYSTEM_USB_RST_S 23 + +/* SYSTEM_SPI2_DMA_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset SPI2 DMA. + */ + +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (SYSTEM_SPI2_DMA_RST_V << SYSTEM_SPI2_DMA_RST_S) +#define SYSTEM_SPI2_DMA_RST_V 0x00000001 +#define SYSTEM_SPI2_DMA_RST_S 22 + +/* SYSTEM_I2S1_RST : R/W; bitpos: [21]; default: 0; + * Set this bit to reset I2S1. + */ + +#define SYSTEM_I2S1_RST (BIT(21)) +#define SYSTEM_I2S1_RST_M (SYSTEM_I2S1_RST_V << SYSTEM_I2S1_RST_S) +#define SYSTEM_I2S1_RST_V 0x00000001 +#define SYSTEM_I2S1_RST_S 21 + +/* SYSTEM_PWM1_RST : R/W; bitpos: [20]; default: 0; + * Set this bit to reset PWM1. + */ + +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (SYSTEM_PWM1_RST_V << SYSTEM_PWM1_RST_S) +#define SYSTEM_PWM1_RST_V 0x00000001 +#define SYSTEM_PWM1_RST_S 20 + +/* SYSTEM_CAN_RST : R/W; bitpos: [19]; default: 0; + * Set this bit to reset CAN. + */ + +#define SYSTEM_CAN_RST (BIT(19)) +#define SYSTEM_CAN_RST_M (SYSTEM_CAN_RST_V << SYSTEM_CAN_RST_S) +#define SYSTEM_CAN_RST_V 0x00000001 +#define SYSTEM_CAN_RST_S 19 + +/* SYSTEM_I2C_EXT1_RST : R/W; bitpos: [18]; default: 0; + * Set this bit to reset I2C EXT1. + */ + +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (SYSTEM_I2C_EXT1_RST_V << SYSTEM_I2C_EXT1_RST_S) +#define SYSTEM_I2C_EXT1_RST_V 0x00000001 +#define SYSTEM_I2C_EXT1_RST_S 18 + +/* SYSTEM_PWM0_RST : R/W; bitpos: [17]; default: 0; + * Set this bit to reset PWM0. + */ + +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (SYSTEM_PWM0_RST_V << SYSTEM_PWM0_RST_S) +#define SYSTEM_PWM0_RST_V 0x00000001 +#define SYSTEM_PWM0_RST_S 17 + +/* SYSTEM_SPI3_RST : R/W; bitpos: [16]; default: 0; + * Set this bit to reset SPI3. + */ + +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (SYSTEM_SPI3_RST_V << SYSTEM_SPI3_RST_S) +#define SYSTEM_SPI3_RST_V 0x00000001 +#define SYSTEM_SPI3_RST_S 16 + +/* SYSTEM_TIMERGROUP1_RST : R/W; bitpos: [15]; default: 0; + * Set this bit to reset timer group1. + */ + +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (SYSTEM_TIMERGROUP1_RST_V << SYSTEM_TIMERGROUP1_RST_S) +#define SYSTEM_TIMERGROUP1_RST_V 0x00000001 +#define SYSTEM_TIMERGROUP1_RST_S 15 + +/* SYSTEM_EFUSE_RST : R/W; bitpos: [14]; default: 0; + * Set this bit to reset eFuse. + */ + +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (SYSTEM_EFUSE_RST_V << SYSTEM_EFUSE_RST_S) +#define SYSTEM_EFUSE_RST_V 0x00000001 +#define SYSTEM_EFUSE_RST_S 14 + +/* SYSTEM_TIMERGROUP_RST : R/W; bitpos: [13]; default: 0; + * Set this bit to reset timer group0. + */ + +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (SYSTEM_TIMERGROUP_RST_V << SYSTEM_TIMERGROUP_RST_S) +#define SYSTEM_TIMERGROUP_RST_V 0x00000001 +#define SYSTEM_TIMERGROUP_RST_S 13 + +/* SYSTEM_UHCI1_RST : R/W; bitpos: [12]; default: 0; + * Set this bit to reset UHCI1. + */ + +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (SYSTEM_UHCI1_RST_V << SYSTEM_UHCI1_RST_S) +#define SYSTEM_UHCI1_RST_V 0x00000001 +#define SYSTEM_UHCI1_RST_S 12 + +/* SYSTEM_LEDC_RST : R/W; bitpos: [11]; default: 0; + * Set this bit to reset LED PWM. + */ + +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (SYSTEM_LEDC_RST_V << SYSTEM_LEDC_RST_S) +#define SYSTEM_LEDC_RST_V 0x00000001 +#define SYSTEM_LEDC_RST_S 11 + +/* SYSTEM_PCNT_RST : R/W; bitpos: [10]; default: 0; + * Set this bit to reset pulse count. + */ + +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (SYSTEM_PCNT_RST_V << SYSTEM_PCNT_RST_S) +#define SYSTEM_PCNT_RST_V 0x00000001 +#define SYSTEM_PCNT_RST_S 10 + +/* SYSTEM_RMT_RST : R/W; bitpos: [9]; default: 0; + * Set this bit to reset remote controller. + */ + +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (SYSTEM_RMT_RST_V << SYSTEM_RMT_RST_S) +#define SYSTEM_RMT_RST_V 0x00000001 +#define SYSTEM_RMT_RST_S 9 + +/* SYSTEM_UHCI0_RST : R/W; bitpos: [8]; default: 0; + * Set this bit to reset UHCI0. + */ + +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (SYSTEM_UHCI0_RST_V << SYSTEM_UHCI0_RST_S) +#define SYSTEM_UHCI0_RST_V 0x00000001 +#define SYSTEM_UHCI0_RST_S 8 + +/* SYSTEM_I2C_EXT0_RST : R/W; bitpos: [7]; default: 0; + * Set this bit to reset I2C EXT0. + */ + +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (SYSTEM_I2C_EXT0_RST_V << SYSTEM_I2C_EXT0_RST_S) +#define SYSTEM_I2C_EXT0_RST_V 0x00000001 +#define SYSTEM_I2C_EXT0_RST_S 7 + +/* SYSTEM_SPI2_RST : R/W; bitpos: [6]; default: 0; + * Set this bit to reset SPI2. + */ + +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (SYSTEM_SPI2_RST_V << SYSTEM_SPI2_RST_S) +#define SYSTEM_SPI2_RST_V 0x00000001 +#define SYSTEM_SPI2_RST_S 6 + +/* SYSTEM_UART1_RST : R/W; bitpos: [5]; default: 0; + * Set this bit to reset UART1. + */ + +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (SYSTEM_UART1_RST_V << SYSTEM_UART1_RST_S) +#define SYSTEM_UART1_RST_V 0x00000001 +#define SYSTEM_UART1_RST_S 5 + +/* SYSTEM_I2S0_RST : R/W; bitpos: [4]; default: 0; + * Set this bit to reset I2S0. + */ + +#define SYSTEM_I2S0_RST (BIT(4)) +#define SYSTEM_I2S0_RST_M (SYSTEM_I2S0_RST_V << SYSTEM_I2S0_RST_S) +#define SYSTEM_I2S0_RST_V 0x00000001 +#define SYSTEM_I2S0_RST_S 4 + +/* SYSTEM_WDG_RST : R/W; bitpos: [3]; default: 0; + * Set this bit to reset WDG. + */ + +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (SYSTEM_WDG_RST_V << SYSTEM_WDG_RST_S) +#define SYSTEM_WDG_RST_V 0x00000001 +#define SYSTEM_WDG_RST_S 3 + +/* SYSTEM_UART_RST : R/W; bitpos: [2]; default: 0; + * Set this bit to reset UART0. + */ + +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (SYSTEM_UART_RST_V << SYSTEM_UART_RST_S) +#define SYSTEM_UART_RST_V 0x00000001 +#define SYSTEM_UART_RST_S 2 + +/* SYSTEM_SPI01_RST : R/W; bitpos: [1]; default: 0; + * Set this bit to reset SPI0 and SPI1. + */ + +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (SYSTEM_SPI01_RST_V << SYSTEM_SPI01_RST_S) +#define SYSTEM_SPI01_RST_V 0x00000001 +#define SYSTEM_SPI01_RST_S 1 + +/* SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0; + * Set this bit to reset timers. + */ + +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (SYSTEM_TIMERS_RST_V << SYSTEM_TIMERS_RST_S) +#define SYSTEM_TIMERS_RST_V 0x00000001 +#define SYSTEM_TIMERS_RST_S 0 + +/* SYSTEM_PERIP_RST_EN1_REG register + * System peripheral (hardware accelerators) reset register 1 + */ + +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x4c) + +/* SYSTEM_CRYPTO_DMA_RST : R/W; bitpos: [6]; default: 1; + * Set this bit to reset cryptography DMA. + */ + +#define SYSTEM_CRYPTO_DMA_RST (BIT(6)) +#define SYSTEM_CRYPTO_DMA_RST_M (SYSTEM_CRYPTO_DMA_RST_V << SYSTEM_CRYPTO_DMA_RST_S) +#define SYSTEM_CRYPTO_DMA_RST_V 0x00000001 +#define SYSTEM_CRYPTO_DMA_RST_S 6 + +/* SYSTEM_CRYPTO_HMAC_RST : R/W; bitpos: [5]; default: 1; + * Set this bit to reset cryptography HMAC. + */ + +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (SYSTEM_CRYPTO_HMAC_RST_V << SYSTEM_CRYPTO_HMAC_RST_S) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x00000001 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 + +/* SYSTEM_CRYPTO_DS_RST : R/W; bitpos: [4]; default: 1; + * Set this bit to reset cryptography digital signature. + */ + +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (SYSTEM_CRYPTO_DS_RST_V << SYSTEM_CRYPTO_DS_RST_S) +#define SYSTEM_CRYPTO_DS_RST_V 0x00000001 +#define SYSTEM_CRYPTO_DS_RST_S 4 + +/* SYSTEM_CRYPTO_RSA_RST : R/W; bitpos: [3]; default: 1; + * Set this bit to reset cryptography RSA. + */ + +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (SYSTEM_CRYPTO_RSA_RST_V << SYSTEM_CRYPTO_RSA_RST_S) +#define SYSTEM_CRYPTO_RSA_RST_V 0x00000001 +#define SYSTEM_CRYPTO_RSA_RST_S 3 + +/* SYSTEM_CRYPTO_SHA_RST : R/W; bitpos: [2]; default: 1; + * Set this bit to reset cryptography SHA. + */ + +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (SYSTEM_CRYPTO_SHA_RST_V << SYSTEM_CRYPTO_SHA_RST_S) +#define SYSTEM_CRYPTO_SHA_RST_V 0x00000001 +#define SYSTEM_CRYPTO_SHA_RST_S 2 + +/* SYSTEM_CRYPTO_AES_RST : R/W; bitpos: [1]; default: 1; + * Set this bit to reset cryptography AES. + */ + +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (SYSTEM_CRYPTO_AES_RST_V << SYSTEM_CRYPTO_AES_RST_S) +#define SYSTEM_CRYPTO_AES_RST_V 0x00000001 +#define SYSTEM_CRYPTO_AES_RST_S 1 + +/* SYSTEM_LPCK_DIV_INT_REG register + * Low power clock divider integer register + */ + +#define SYSTEM_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x50) + +/* SYSTEM_LPCK_DIV_NUM : R/W; bitpos: [11:0]; default: 255; + * This register is used to set the integer number of divider. + */ + +#define SYSTEM_LPCK_DIV_NUM 0x00000FFF +#define SYSTEM_LPCK_DIV_NUM_M (SYSTEM_LPCK_DIV_NUM_V << SYSTEM_LPCK_DIV_NUM_S) +#define SYSTEM_LPCK_DIV_NUM_V 0x00000FFF +#define SYSTEM_LPCK_DIV_NUM_S 0 + +/* SYSTEM_BT_LPCK_DIV_FRAC_REG register + * Divider fraction configuration register for low-power clock + */ + +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x54) + +/* SYSTEM_LPCLK_RTC_EN : R/W; bitpos: [28]; default: 0; + * Set this bit to enable the RTC low power clock. + */ + +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (SYSTEM_LPCLK_RTC_EN_V << SYSTEM_LPCLK_RTC_EN_S) +#define SYSTEM_LPCLK_RTC_EN_V 0x00000001 +#define SYSTEM_LPCLK_RTC_EN_S 28 + +/* SYSTEM_LPCLK_SEL_XTAL32K : R/W; bitpos: [27]; default: 0; + * Set this bit to select xtal32k clock as the low power clock. + */ + +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (SYSTEM_LPCLK_SEL_XTAL32K_V << SYSTEM_LPCLK_SEL_XTAL32K_S) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x00000001 +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 + +/* SYSTEM_LPCLK_SEL_XTAL : R/W; bitpos: [26]; default: 0; + * Set this bit to select xtal clock as the low power clock. + */ + +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (SYSTEM_LPCLK_SEL_XTAL_V << SYSTEM_LPCLK_SEL_XTAL_S) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x00000001 +#define SYSTEM_LPCLK_SEL_XTAL_S 26 + +/* SYSTEM_LPCLK_SEL_8M : R/W; bitpos: [25]; default: 1; + * Set this bit to select 8m clock as the low power clock. + */ + +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (SYSTEM_LPCLK_SEL_8M_V << SYSTEM_LPCLK_SEL_8M_S) +#define SYSTEM_LPCLK_SEL_8M_V 0x00000001 +#define SYSTEM_LPCLK_SEL_8M_S 25 + +/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W; bitpos: [24]; default: 0; + * Set this bit to select RTC slow clock as the low power clock. + */ + +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (SYSTEM_LPCLK_SEL_RTC_SLOW_V << SYSTEM_LPCLK_SEL_RTC_SLOW_S) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x00000001 +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 + +/* SYSTEM_CPU_INTR_FROM_CPU_0_REG register + * CPU interrupt controlling register 0 + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x58) + +/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * Set this bit to generate CPU interrupt 0. This bit needs to be reset by + * software in the ISR process. + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x00000001 +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 + +/* SYSTEM_CPU_INTR_FROM_CPU_1_REG register + * CPU interrupt controlling register 1 + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x5c) + +/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * Set this bit to generate CPU interrupt 1. This bit needs to be reset by + * software in the ISR process. + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x00000001 +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 + +/* SYSTEM_CPU_INTR_FROM_CPU_2_REG register + * CPU interrupt controlling register 2 + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x60) + +/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * Set this bit to generate CPU interrupt 2. This bit needs to be reset by + * software in the ISR process. + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x00000001 +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 + +/* SYSTEM_CPU_INTR_FROM_CPU_3_REG register + * CPU interrupt controlling register 3 + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x64) + +/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * Set this bit to generate CPU interrupt 3. This bit needs to be reset by + * software in the ISR process. + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x00000001 +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 + +/* SYSTEM_RSA_PD_CTRL_REG register + * RSA memory remapping register + */ + +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x68) + +/* SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down RSA memory. This bit has the highest + * priority. + */ + +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x00000001 +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 + +/* SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set this bit to force power up RSA memory. This bit has the second + * highest priority. + */ + +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x00000001 +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 + +/* SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1; + * Set this bit to power down RSA memory. This bit has the lowest priority. + * When Digital Signature occupies the RSA, this bit is invalid. + */ + +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S) +#define SYSTEM_RSA_MEM_PD_V 0x00000001 +#define SYSTEM_RSA_MEM_PD_S 0 + +/* SYSTEM_BUSTOEXTMEM_ENA_REG register + * EDMA enable register + */ + +#define SYSTEM_BUSTOEXTMEM_ENA_REG (DR_REG_SYSTEM_BASE + 0x6c) + +/* SYSTEM_BUSTOEXTMEM_ENA : R/W; bitpos: [0]; default: 1; + * Set this bit to enable bus to EDMA. + */ + +#define SYSTEM_BUSTOEXTMEM_ENA (BIT(0)) +#define SYSTEM_BUSTOEXTMEM_ENA_M (SYSTEM_BUSTOEXTMEM_ENA_V << SYSTEM_BUSTOEXTMEM_ENA_S) +#define SYSTEM_BUSTOEXTMEM_ENA_V 0x00000001 +#define SYSTEM_BUSTOEXTMEM_ENA_S 0 + +/* SYSTEM_CACHE_CONTROL_REG register + * Cache control register + */ + +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x70) + +/* SYSTEM_PRO_CACHE_RESET : R/W; bitpos: [2]; default: 0; + * Set this bit to reset cache. + */ + +#define SYSTEM_PRO_CACHE_RESET (BIT(2)) +#define SYSTEM_PRO_CACHE_RESET_M (SYSTEM_PRO_CACHE_RESET_V << SYSTEM_PRO_CACHE_RESET_S) +#define SYSTEM_PRO_CACHE_RESET_V 0x00000001 +#define SYSTEM_PRO_CACHE_RESET_S 2 + +/* SYSTEM_PRO_DCACHE_CLK_ON : R/W; bitpos: [1]; default: 1; + * Set this bit to enable clock of d-cache. + */ + +#define SYSTEM_PRO_DCACHE_CLK_ON (BIT(1)) +#define SYSTEM_PRO_DCACHE_CLK_ON_M (SYSTEM_PRO_DCACHE_CLK_ON_V << SYSTEM_PRO_DCACHE_CLK_ON_S) +#define SYSTEM_PRO_DCACHE_CLK_ON_V 0x00000001 +#define SYSTEM_PRO_DCACHE_CLK_ON_S 1 + +/* SYSTEM_PRO_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1; + * Set this bit to enable clock of i-cache. + */ + +#define SYSTEM_PRO_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_PRO_ICACHE_CLK_ON_M (SYSTEM_PRO_ICACHE_CLK_ON_V << SYSTEM_PRO_ICACHE_CLK_ON_S) +#define SYSTEM_PRO_ICACHE_CLK_ON_V 0x00000001 +#define SYSTEM_PRO_ICACHE_CLK_ON_S 0 + +/* SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * External memory encrypt and decrypt controlling register + */ + +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x74) + +/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Set this bit to enable Manual Encryption under Download Boot mode. + */ + +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Set this bit to enable Auto Decryption under Download Boot mode. + */ + +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001 +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 + +/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; + * Set this bit to enable Auto Encryption under Download Boot mode. + */ + +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001 +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 + +/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Set this bit to enable Manual Encryption under SPI Boot mode. + */ + +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 + +/* SYSTEM_RTC_FASTMEM_CONFIG_REG register + * RTC fast memory configuration register + */ + +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x78) + +/* SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0; + * This bit stores the status of RTC memory CRC. High level means finished + * while low level means not finished. + */ + +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x00000001 +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 + +/* SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047; + * This field is used to set length of RTC memory for CRC based on start + * address. + */ + +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 + +/* SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0; + * This field is used to set address of RTC memory for CRC. + */ + +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 + +/* SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0; + * Set this bit to start the CRC of RTC memory. + */ + +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S) +#define SYSTEM_RTC_MEM_CRC_START_V 0x00000001 +#define SYSTEM_RTC_MEM_CRC_START_S 8 + +/* SYSTEM_RTC_FASTMEM_CRC_REG register + * RTC fast memory CRC controlling register + */ + +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x7c) + +/* SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0; + * This field stores the CRC result of RTC memory. + */ + +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_S 0 + +/* SYSTEM_Redundant_ECO_Ctrl_REG register + * Redundant ECO control register + */ + +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x80) + +/* SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0; + * The redundant ECO result bit to avoid optimization in circuits. + */ + +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x00000001 +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 + +/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0; + * The redundant ECO drive bit to avoid optimization in circuits. + */ + +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x00000001 +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 + +/* SYSTEM_CLOCK_GATE_REG register + * Clock gate control register + */ + +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x84) + +/* SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable clock of this module. + */ + +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S) +#define SYSTEM_CLK_EN_V 0x00000001 +#define SYSTEM_CLK_EN_S 0 + +/* SYSTEM_SRAM_CTRL_2_REG register + * System SRAM configuration register 2 + */ + +#define SYSTEM_SRAM_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x88) + +/* SYSTEM_SRAM_FORCE_PU : R/W; bitpos: [21:0]; default: 4194303; + * This field is used to power up internal SRAM. + */ + +#define SYSTEM_SRAM_FORCE_PU 0x003FFFFF +#define SYSTEM_SRAM_FORCE_PU_M (SYSTEM_SRAM_FORCE_PU_V << SYSTEM_SRAM_FORCE_PU_S) +#define SYSTEM_SRAM_FORCE_PU_V 0x003FFFFF +#define SYSTEM_SRAM_FORCE_PU_S 0 + +/* SYSTEM_SYSCLK_CONF_REG register + * SoC clock configuration register + */ + +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x8c) + +/* SYSTEM_CLK_DIV_EN : RO; bitpos: [19]; default: 0; + * Not used, extends from ESP32. + */ + +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (SYSTEM_CLK_DIV_EN_V << SYSTEM_CLK_DIV_EN_S) +#define SYSTEM_CLK_DIV_EN_V 0x00000001 +#define SYSTEM_CLK_DIV_EN_S 19 + +/* SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [18:12]; default: 0; + * This field is used to read XTAL frequency in MHz. + */ + +#define SYSTEM_CLK_XTAL_FREQ 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_M (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S) +#define SYSTEM_CLK_XTAL_FREQ_V 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_S 12 + +/* SYSTEM_SOC_CLK_SEL : R/W; bitpos: [11:10]; default: 0; + * This field is used to select SOC clock. + */ + +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M (SYSTEM_SOC_CLK_SEL_V << SYSTEM_SOC_CLK_SEL_S) +#define SYSTEM_SOC_CLK_SEL_V 0x00000003 +#define SYSTEM_SOC_CLK_SEL_S 10 + +/* SYSTEM_PRE_DIV_CNT : R/W; bitpos: [9:0]; default: 1; + * This field is used to set the count of prescaler of XTAL\_CLK. + */ + +#define SYSTEM_PRE_DIV_CNT 0x000003FF +#define SYSTEM_PRE_DIV_CNT_M (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S) +#define SYSTEM_PRE_DIV_CNT_V 0x000003FF +#define SYSTEM_PRE_DIV_CNT_S 0 + +/* SYSTEM_REG_DATE_REG register + * Version control register + */ + +#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) + +/* SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 26247200; + * This is the date version register. + */ + +#define SYSTEM_SYSTEM_REG_DATE 0x0FFFFFFF +#define SYSTEM_SYSTEM_REG_DATE_M (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S) +#define SYSTEM_SYSTEM_REG_DATE_V 0x0FFFFFFF +#define SYSTEM_SYSTEM_REG_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSTEM_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h new file mode 100644 index 00000000000..52bfe4d6295 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h @@ -0,0 +1,1265 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_TIMG_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_TIMG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ + +#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0) + +/* TIMG_T0_EN : R/W; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ + +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001 +#define TIMG_T0_EN_S 31 + +/* TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. + * When + * + * cleared, the timer 0 time-base counter will decrement. + */ + +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001 +#define TIMG_T0_INCREASE_S 30 + +/* TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ + +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001 +#define TIMG_T0_AUTORELOAD_S 29 + +/* TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ + +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFF +#define TIMG_T0_DIVIDER_S 13 + +/* TIMG_T0_EDGE_INT_EN : R/W; bitpos: [12]; default: 0; + * When set, an alarm will generate an edge type interrupt. + */ + +#define TIMG_T0_EDGE_INT_EN (BIT(12)) +#define TIMG_T0_EDGE_INT_EN_M (TIMG_T0_EDGE_INT_EN_V << TIMG_T0_EDGE_INT_EN_S) +#define TIMG_T0_EDGE_INT_EN_V 0x00000001 +#define TIMG_T0_EDGE_INT_EN_S 12 + +/* TIMG_T0_LEVEL_INT_EN : R/W; bitpos: [11]; default: 0; + * When set, an alarm will generate a level type interrupt. + */ + +#define TIMG_T0_LEVEL_INT_EN (BIT(11)) +#define TIMG_T0_LEVEL_INT_EN_M (TIMG_T0_LEVEL_INT_EN_V << TIMG_T0_LEVEL_INT_EN_S) +#define TIMG_T0_LEVEL_INT_EN_V 0x00000001 +#define TIMG_T0_LEVEL_INT_EN_S 11 + +/* TIMG_T0_ALARM_EN : R/W; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * + * alarm occurs. + */ + +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001 +#define TIMG_T0_ALARM_EN_S 10 + +/* TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the + * source clock of timer group. + */ + +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S) +#define TIMG_T0_USE_XTAL_V 0x00000001 +#define TIMG_T0_USE_XTAL_S 9 + +/* TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ + +#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4) + +/* TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base + * counter + * + * of timer 0 can be read here. + */ + +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +/* TIMG_T0HI_REG register + * Timer 0 current value, high 32 bits + */ + +#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8) + +/* TIMG_T0_HI : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 32 bits of the time-base + * counter + * + * of timer 0 can be read here. + */ + +#define TIMG_T0_HI 0xFFFFFFFF +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0xFFFFFFFF +#define TIMG_T0_HI_S 0 + +/* TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ + +#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc) + +/* TIMG_T0_UPDATE : R/W; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ + +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001 +#define TIMG_T0_UPDATE_S 31 + +/* TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ + +#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10) + +/* TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ + +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +/* TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ + +#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14) + +/* TIMG_T0_ALARM_HI : R/W; bitpos: [31:0]; default: 0; + * + * + * Timer 0 alarm trigger time-base counter value, high 32 bits. + */ + +#define TIMG_T0_ALARM_HI 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_S 0 + +/* TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ + +#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18) + +/* TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * + * + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * + * Counter. + */ + +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +/* TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 32 bits + */ + +#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c) + +/* TIMG_T0_LOAD_HI : R/W; bitpos: [31:0]; default: 0; + * + * + * High 32 bits of the value that a reload will load onto timer 0 time-base + * + * counter. + */ + +#define TIMG_T0_LOAD_HI 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_S 0 + +/* TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ + +#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20) + +/* TIMG_T0_LOAD : WO; bitpos: [31:0]; default: 0; + * + * + * Write any value to trigger a timer 0 time-base counter reload. + */ + +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +/* TIMG_T1CONFIG_REG register + * Timer 1 configuration register + */ + +#define TIMG_T1CONFIG_REG (DR_REG_TIMG_BASE + 0x24) + +/* TIMG_T1_EN : R/W; bitpos: [31]; default: 0; + * When set, the timer 1 time-base counter is enabled. + */ + +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S) +#define TIMG_T1_EN_V 0x00000001 +#define TIMG_T1_EN_S 31 + +/* TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 1 time-base counter will increment every clock tick. + * When + * + * cleared, the timer 1 time-base counter will decrement. + */ + +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S) +#define TIMG_T1_INCREASE_V 0x00000001 +#define TIMG_T1_INCREASE_S 30 + +/* TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 1 auto-reload at alarm is enabled. + */ + +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S) +#define TIMG_T1_AUTORELOAD_V 0x00000001 +#define TIMG_T1_AUTORELOAD_S 29 + +/* TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 1 clock (T1_clk) prescaler value. + */ + +#define TIMG_T1_DIVIDER 0x0000FFFF +#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S) +#define TIMG_T1_DIVIDER_V 0x0000FFFF +#define TIMG_T1_DIVIDER_S 13 + +/* TIMG_T1_EDGE_INT_EN : R/W; bitpos: [12]; default: 0; + * When set, an alarm will generate an edge type interrupt. + */ + +#define TIMG_T1_EDGE_INT_EN (BIT(12)) +#define TIMG_T1_EDGE_INT_EN_M (TIMG_T1_EDGE_INT_EN_V << TIMG_T1_EDGE_INT_EN_S) +#define TIMG_T1_EDGE_INT_EN_V 0x00000001 +#define TIMG_T1_EDGE_INT_EN_S 12 + +/* TIMG_T1_LEVEL_INT_EN : R/W; bitpos: [11]; default: 0; + * When set, an alarm will generate a level type interrupt. + */ + +#define TIMG_T1_LEVEL_INT_EN (BIT(11)) +#define TIMG_T1_LEVEL_INT_EN_M (TIMG_T1_LEVEL_INT_EN_V << TIMG_T1_LEVEL_INT_EN_S) +#define TIMG_T1_LEVEL_INT_EN_V 0x00000001 +#define TIMG_T1_LEVEL_INT_EN_S 11 + +/* TIMG_T1_ALARM_EN : R/W; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * + * alarm occurs. + */ + +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S) +#define TIMG_T1_ALARM_EN_V 0x00000001 +#define TIMG_T1_ALARM_EN_S 10 + +/* TIMG_T1_USE_XTAL : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the + * source clock of timer group. + */ + +#define TIMG_T1_USE_XTAL (BIT(9)) +#define TIMG_T1_USE_XTAL_M (TIMG_T1_USE_XTAL_V << TIMG_T1_USE_XTAL_S) +#define TIMG_T1_USE_XTAL_V 0x00000001 +#define TIMG_T1_USE_XTAL_S 9 + +/* TIMG_T1LO_REG register + * Timer 1 current value, low 32 bits + */ + +#define TIMG_T1LO_REG (DR_REG_TIMG_BASE + 0x28) + +/* TIMG_T1_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base + * counter + * + * of timer 1 can be read here. + */ + +#define TIMG_T1_LO 0xFFFFFFFF +#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S) +#define TIMG_T1_LO_V 0xFFFFFFFF +#define TIMG_T1_LO_S 0 + +/* TIMG_T1HI_REG register + * Timer 1 current value, high 32 bits + */ + +#define TIMG_T1HI_REG (DR_REG_TIMG_BASE + 0x2c) + +/* TIMG_T1_HI : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the high 32 bits of the time-base + * counter + * + * of timer 1 can be read here. + */ + +#define TIMG_T1_HI 0xFFFFFFFF +#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S) +#define TIMG_T1_HI_V 0xFFFFFFFF +#define TIMG_T1_HI_S 0 + +/* TIMG_T1UPDATE_REG register + * Write to copy current timer value to TIMGn_T1_(LO/HI)_REG + */ + +#define TIMG_T1UPDATE_REG (DR_REG_TIMG_BASE + 0x30) + +/* TIMG_T1_UPDATE : R/W; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched. + */ + +#define TIMG_T1_UPDATE (BIT(31)) +#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S) +#define TIMG_T1_UPDATE_V 0x00000001 +#define TIMG_T1_UPDATE_S 31 + +/* TIMG_T1ALARMLO_REG register + * Timer 1 alarm value, low 32 bits + */ + +#define TIMG_T1ALARMLO_REG (DR_REG_TIMG_BASE + 0x34) + +/* TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 1 alarm trigger time-base counter value, low 32 bits. + */ + +#define TIMG_T1_ALARM_LO 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_S 0 + +/* TIMG_T1ALARMHI_REG register + * Timer 1 alarm value, high bits + */ + +#define TIMG_T1ALARMHI_REG (DR_REG_TIMG_BASE + 0x38) + +/* TIMG_T1_ALARM_HI : R/W; bitpos: [31:0]; default: 0; + * + * + * Timer 1 alarm trigger time-base counter value, high 32 bits. + */ + +#define TIMG_T1_ALARM_HI 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S) +#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_S 0 + +/* TIMG_T1LOADLO_REG register + * Timer 1 reload value, low 32 bits + */ + +#define TIMG_T1LOADLO_REG (DR_REG_TIMG_BASE + 0x3c) + +/* TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * + * + * Low 32 bits of the value that a reload will load onto timer 1 time-base + * + * Counter. + */ + +#define TIMG_T1_LOAD_LO 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_S 0 + +/* TIMG_T1LOADHI_REG register + * Timer 1 reload value, high 32 bits + */ + +#define TIMG_T1LOADHI_REG (DR_REG_TIMG_BASE + 0x40) + +/* TIMG_T1_LOAD_HI : R/W; bitpos: [31:0]; default: 0; + * + * + * High 32 bits of the value that a reload will load onto timer 1 time-base + * + * counter. + */ + +#define TIMG_T1_LOAD_HI 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S) +#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_S 0 + +/* TIMG_T1LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ + +#define TIMG_T1LOAD_REG (DR_REG_TIMG_BASE + 0x44) + +/* TIMG_T1_LOAD : WO; bitpos: [31:0]; default: 0; + * + * + * Write any value to trigger a timer 1 time-base counter reload. + */ + +#define TIMG_T1_LOAD 0xFFFFFFFF +#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S) +#define TIMG_T1_LOAD_V 0xFFFFFFFF +#define TIMG_T1_LOAD_S 0 + +/* TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ + +#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48) + +/* TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001 +#define TIMG_WDT_EN_S 31 + +/* TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset + * system. + * + */ + +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003 +#define TIMG_WDT_STG0_S 29 + +/* TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset + * system. + * + */ + +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003 +#define TIMG_WDT_STG1_S 27 + +/* TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset + * system. + * + */ + +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003 +#define TIMG_WDT_STG2_S 25 + +/* TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset + * system. + * + */ + +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003 +#define TIMG_WDT_STG3_S 23 + +/* TIMG_WDT_EDGE_INT_EN : R/W; bitpos: [22]; default: 0; + * When set, an edge type interrupt will occur at the timeout of a stage + * + * configured to generate an interrupt. + */ + +#define TIMG_WDT_EDGE_INT_EN (BIT(22)) +#define TIMG_WDT_EDGE_INT_EN_M (TIMG_WDT_EDGE_INT_EN_V << TIMG_WDT_EDGE_INT_EN_S) +#define TIMG_WDT_EDGE_INT_EN_V 0x00000001 +#define TIMG_WDT_EDGE_INT_EN_S 22 + +/* TIMG_WDT_LEVEL_INT_EN : R/W; bitpos: [21]; default: 0; + * When set, a level type interrupt will occur at the timeout of a stage + * + * configured to generate an interrupt. + */ + +#define TIMG_WDT_LEVEL_INT_EN (BIT(21)) +#define TIMG_WDT_LEVEL_INT_EN_M (TIMG_WDT_LEVEL_INT_EN_V << TIMG_WDT_LEVEL_INT_EN_S) +#define TIMG_WDT_LEVEL_INT_EN_V 0x00000001 +#define TIMG_WDT_LEVEL_INT_EN_S 21 + +/* TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 + +/* TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 + +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 + +/* TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001 +#define TIMG_WDT_PROCPU_RESET_EN_S 13 + +/* TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * Reserved + */ + +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001 +#define TIMG_WDT_APPCPU_RESET_EN_S 12 + +/* TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ + +#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c) + +/* TIMG_WDT_CLK_PRESCALER : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * + * TIMG_WDT_CLK_PRESCALE. + */ + +#define TIMG_WDT_CLK_PRESCALER 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALER_M (TIMG_WDT_CLK_PRESCALER_V << TIMG_WDT_CLK_PRESCALER_S) +#define TIMG_WDT_CLK_PRESCALER_V 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALER_S 16 + +/* TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ + +#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50) + +/* TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +/* TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ + +#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54) + +/* TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +/* TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ + +#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58) + +/* TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +/* TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ + +#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c) + +/* TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +/* TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ + +#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60) + +/* TIMG_WDT_FEED : WO; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +/* TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ + +#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64) + +/* TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * + * protection is enabled. + */ + +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +/* TIMG_RTCCALICFG_REG register + * RTC calibration configuration register + */ + +#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68) + +/* TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Reserved + */ + +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001 +#define TIMG_RTC_CALI_START_S 31 + +/* TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Reserved + */ + +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFF +#define TIMG_RTC_CALI_MAX_S 16 + +/* TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * Reserved + */ + +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001 +#define TIMG_RTC_CALI_RDY_S 15 + +/* TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1; + * 0:rtcslowclock. 1:clk_80m. 2:xtal_32k. + */ + +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_S 13 + +/* TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * Reserved + */ + +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +/* TIMG_RTCCALICFG1_REG register + * RTC calibration configuration1 register + */ + +#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c) + +/* TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * Reserved + */ + +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 + +/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * Reserved + */ + +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001 +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 + +/* TIMG_LACTCONFIG_REG register + * LACT configuration register + */ + +#define TIMG_LACTCONFIG_REG (DR_REG_TIMG_BASE + 0x70) + +/* TIMG_LACT_EN : R/W; bitpos: [31]; default: 0; + * Reserved + */ + +#define TIMG_LACT_EN (BIT(31)) +#define TIMG_LACT_EN_M (TIMG_LACT_EN_V << TIMG_LACT_EN_S) +#define TIMG_LACT_EN_V 0x00000001 +#define TIMG_LACT_EN_S 31 + +/* TIMG_LACT_INCREASE : R/W; bitpos: [30]; default: 1; + * Reserved + */ + +#define TIMG_LACT_INCREASE (BIT(30)) +#define TIMG_LACT_INCREASE_M (TIMG_LACT_INCREASE_V << TIMG_LACT_INCREASE_S) +#define TIMG_LACT_INCREASE_V 0x00000001 +#define TIMG_LACT_INCREASE_S 30 + +/* TIMG_LACT_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * Reserved + */ + +#define TIMG_LACT_AUTORELOAD (BIT(29)) +#define TIMG_LACT_AUTORELOAD_M (TIMG_LACT_AUTORELOAD_V << TIMG_LACT_AUTORELOAD_S) +#define TIMG_LACT_AUTORELOAD_V 0x00000001 +#define TIMG_LACT_AUTORELOAD_S 29 + +/* TIMG_LACT_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Reserved + */ + +#define TIMG_LACT_DIVIDER 0x0000FFFF +#define TIMG_LACT_DIVIDER_M (TIMG_LACT_DIVIDER_V << TIMG_LACT_DIVIDER_S) +#define TIMG_LACT_DIVIDER_V 0x0000FFFF +#define TIMG_LACT_DIVIDER_S 13 + +/* TIMG_LACT_EDGE_INT_EN : R/W; bitpos: [12]; default: 0; + * Reserved + */ + +#define TIMG_LACT_EDGE_INT_EN (BIT(12)) +#define TIMG_LACT_EDGE_INT_EN_M (TIMG_LACT_EDGE_INT_EN_V << TIMG_LACT_EDGE_INT_EN_S) +#define TIMG_LACT_EDGE_INT_EN_V 0x00000001 +#define TIMG_LACT_EDGE_INT_EN_S 12 + +/* TIMG_LACT_LEVEL_INT_EN : R/W; bitpos: [11]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LEVEL_INT_EN (BIT(11)) +#define TIMG_LACT_LEVEL_INT_EN_M (TIMG_LACT_LEVEL_INT_EN_V << TIMG_LACT_LEVEL_INT_EN_S) +#define TIMG_LACT_LEVEL_INT_EN_V 0x00000001 +#define TIMG_LACT_LEVEL_INT_EN_S 11 + +/* TIMG_LACT_ALARM_EN : R/W; bitpos: [10]; default: 0; + * Reserved + */ + +#define TIMG_LACT_ALARM_EN (BIT(10)) +#define TIMG_LACT_ALARM_EN_M (TIMG_LACT_ALARM_EN_V << TIMG_LACT_ALARM_EN_S) +#define TIMG_LACT_ALARM_EN_V 0x00000001 +#define TIMG_LACT_ALARM_EN_S 10 + +/* TIMG_LACT_LAC_EN : R/W; bitpos: [9]; default: 1; + * Reserved + */ + +#define TIMG_LACT_LAC_EN (BIT(9)) +#define TIMG_LACT_LAC_EN_M (TIMG_LACT_LAC_EN_V << TIMG_LACT_LAC_EN_S) +#define TIMG_LACT_LAC_EN_V 0x00000001 +#define TIMG_LACT_LAC_EN_S 9 + +/* TIMG_LACT_CPST_EN : R/W; bitpos: [8]; default: 1; + * Reserved + */ + +#define TIMG_LACT_CPST_EN (BIT(8)) +#define TIMG_LACT_CPST_EN_M (TIMG_LACT_CPST_EN_V << TIMG_LACT_CPST_EN_S) +#define TIMG_LACT_CPST_EN_V 0x00000001 +#define TIMG_LACT_CPST_EN_S 8 + +/* TIMG_LACT_RTC_ONLY : R/W; bitpos: [7]; default: 0; + * Reserved + */ + +#define TIMG_LACT_RTC_ONLY (BIT(7)) +#define TIMG_LACT_RTC_ONLY_M (TIMG_LACT_RTC_ONLY_V << TIMG_LACT_RTC_ONLY_S) +#define TIMG_LACT_RTC_ONLY_V 0x00000001 +#define TIMG_LACT_RTC_ONLY_S 7 + +/* TIMG_LACT_USE_REFTICK : R/W; bitpos: [6]; default: 0; + * Reserved + */ + +#define TIMG_LACT_USE_REFTICK (BIT(6)) +#define TIMG_LACT_USE_REFTICK_M (TIMG_LACT_USE_REFTICK_V << TIMG_LACT_USE_REFTICK_S) +#define TIMG_LACT_USE_REFTICK_V 0x00000001 +#define TIMG_LACT_USE_REFTICK_S 6 + +/* TIMG_LACTRTC_REG register + * LACT RTC register + */ + +#define TIMG_LACTRTC_REG (DR_REG_TIMG_BASE + 0x74) + +/* TIMG_LACT_RTC_STEP_LEN : R/W; bitpos: [31:6]; default: 0; + * Reserved + */ + +#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_M (TIMG_LACT_RTC_STEP_LEN_V << TIMG_LACT_RTC_STEP_LEN_S) +#define TIMG_LACT_RTC_STEP_LEN_V 0x03FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_S 6 + +/* TIMG_LACTLO_REG register + * LACT low register + */ + +#define TIMG_LACTLO_REG (DR_REG_TIMG_BASE + 0x78) + +/* TIMG_LACT_LO : RO; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LO 0xFFFFFFFF +#define TIMG_LACT_LO_M (TIMG_LACT_LO_V << TIMG_LACT_LO_S) +#define TIMG_LACT_LO_V 0xFFFFFFFF +#define TIMG_LACT_LO_S 0 + +/* TIMG_LACTHI_REG register + * LACT high register + */ + +#define TIMG_LACTHI_REG (DR_REG_TIMG_BASE + 0x7c) + +/* TIMG_LACT_HI : RO; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_HI 0xFFFFFFFF +#define TIMG_LACT_HI_M (TIMG_LACT_HI_V << TIMG_LACT_HI_S) +#define TIMG_LACT_HI_V 0xFFFFFFFF +#define TIMG_LACT_HI_S 0 + +/* TIMG_LACTUPDATE_REG register + * LACT update register + */ + +#define TIMG_LACTUPDATE_REG (DR_REG_TIMG_BASE + 0x80) + +/* TIMG_LACT_UPDATE : WO; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_UPDATE 0xFFFFFFFF +#define TIMG_LACT_UPDATE_M (TIMG_LACT_UPDATE_V << TIMG_LACT_UPDATE_S) +#define TIMG_LACT_UPDATE_V 0xFFFFFFFF +#define TIMG_LACT_UPDATE_S 0 + +/* TIMG_LACTALARMLO_REG register + * LACT alarm low register + */ + +#define TIMG_LACTALARMLO_REG (DR_REG_TIMG_BASE + 0x84) + +/* TIMG_LACT_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_ALARM_LO 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_M (TIMG_LACT_ALARM_LO_V << TIMG_LACT_ALARM_LO_S) +#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_S 0 + +/* TIMG_LACTALARMHI_REG register + * LACT alarm high register + */ + +#define TIMG_LACTALARMHI_REG (DR_REG_TIMG_BASE + 0x88) + +/* TIMG_LACT_ALARM_HI : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_ALARM_HI 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_M (TIMG_LACT_ALARM_HI_V << TIMG_LACT_ALARM_HI_S) +#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_S 0 + +/* TIMG_LACTLOADLO_REG register + * LACT load low register + */ + +#define TIMG_LACTLOADLO_REG (DR_REG_TIMG_BASE + 0x8c) + +/* TIMG_LACT_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LOAD_LO 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_M (TIMG_LACT_LOAD_LO_V << TIMG_LACT_LOAD_LO_S) +#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_S 0 + +/* TIMG_LACTLOADHI_REG register + * Timer LACT load high register + */ + +#define TIMG_LACTLOADHI_REG (DR_REG_TIMG_BASE + 0x90) + +/* TIMG_LACT_LOAD_HI : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LOAD_HI 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_M (TIMG_LACT_LOAD_HI_V << TIMG_LACT_LOAD_HI_S) +#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_S 0 + +/* TIMG_LACTLOAD_REG register + * Timer LACT load register + */ + +#define TIMG_LACTLOAD_REG (DR_REG_TIMG_BASE + 0x94) + +/* TIMG_LACT_LOAD : WO; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LOAD 0xFFFFFFFF +#define TIMG_LACT_LOAD_M (TIMG_LACT_LOAD_V << TIMG_LACT_LOAD_S) +#define TIMG_LACT_LOAD_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_S 0 + +/* TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ + +#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x98) + +/* TIMG_LACT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the TIMG_LACT_INT interrupt. + */ + +#define TIMG_LACT_INT_ENA (BIT(3)) +#define TIMG_LACT_INT_ENA_M (TIMG_LACT_INT_ENA_V << TIMG_LACT_INT_ENA_S) +#define TIMG_LACT_INT_ENA_V 0x00000001 +#define TIMG_LACT_INT_ENA_S 3 + +/* TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001 +#define TIMG_WDT_INT_ENA_S 2 + +/* TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_T1_INT interrupt. + */ + +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S) +#define TIMG_T1_INT_ENA_V 0x00000001 +#define TIMG_T1_INT_ENA_S 1 + +/* TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T0_INT interrupt. + */ + +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001 +#define TIMG_T0_INT_ENA_S 0 + +/* TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ + +#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x9c) + +/* TIMG_LACT_INT_RAW : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the TIMG_LACT_INT interrupt. + */ + +#define TIMG_LACT_INT_RAW (BIT(3)) +#define TIMG_LACT_INT_RAW_M (TIMG_LACT_INT_RAW_V << TIMG_LACT_INT_RAW_S) +#define TIMG_LACT_INT_RAW_V 0x00000001 +#define TIMG_LACT_INT_RAW_S 3 + +/* TIMG_WDT_INT_RAW : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001 +#define TIMG_WDT_INT_RAW_S 2 + +/* TIMG_T1_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_T1_INT interrupt. + */ + +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S) +#define TIMG_T1_INT_RAW_V 0x00000001 +#define TIMG_T1_INT_RAW_S 1 + +/* TIMG_T0_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T0_INT interrupt. + */ + +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001 +#define TIMG_T0_INT_RAW_S 0 + +/* TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ + +#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0xa0) + +/* TIMG_LACT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the TIMG_LACT_INT interrupt. + */ + +#define TIMG_LACT_INT_ST (BIT(3)) +#define TIMG_LACT_INT_ST_M (TIMG_LACT_INT_ST_V << TIMG_LACT_INT_ST_S) +#define TIMG_LACT_INT_ST_V 0x00000001 +#define TIMG_LACT_INT_ST_S 3 + +/* TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001 +#define TIMG_WDT_INT_ST_S 2 + +/* TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_T1_INT interrupt. + */ + +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S) +#define TIMG_T1_INT_ST_V 0x00000001 +#define TIMG_T1_INT_ST_S 1 + +/* TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T0_INT interrupt. + */ + +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001 +#define TIMG_T0_INT_ST_S 0 + +/* TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ + +#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0xa4) + +/* TIMG_LACT_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear the TIMG_LACT_INT interrupt. + */ + +#define TIMG_LACT_INT_CLR (BIT(3)) +#define TIMG_LACT_INT_CLR_M (TIMG_LACT_INT_CLR_V << TIMG_LACT_INT_CLR_S) +#define TIMG_LACT_INT_CLR_V 0x00000001 +#define TIMG_LACT_INT_CLR_S 3 + +/* TIMG_WDT_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001 +#define TIMG_WDT_INT_CLR_S 2 + +/* TIMG_T1_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_T1_INT interrupt. + */ + +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S) +#define TIMG_T1_INT_CLR_V 0x00000001 +#define TIMG_T1_INT_CLR_S 1 + +/* TIMG_T0_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T0_INT interrupt. + */ + +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001 +#define TIMG_T0_INT_CLR_S 0 + +/* TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ + +#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0xa8) + +/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's + * value exceeds this threshold, a timeout is triggered. + */ + +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 + +/* TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001 +#define TIMG_RTC_CALI_TIMEOUT_S 0 + +/* TIMG_TIMERS_DATE_REG register + * Version control register + */ + +#define TIMG_TIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8) + +/* TIMG_TIMERS_DATE : R/W; bitpos: [27:0]; default: 26243681; + * Version control register. + */ + +#define TIMG_TIMERS_DATE 0x0FFFFFFF +#define TIMG_TIMERS_DATE_M (TIMG_TIMERS_DATE_V << TIMG_TIMERS_DATE_S) +#define TIMG_TIMERS_DATE_V 0x0FFFFFFF +#define TIMG_TIMERS_DATE_S 0 + +/* TIMG_REGCLK_REG register + * Timer group clock gate register + */ + +#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc) + +/* TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by + * software. 0: Registers can not be read or written to by software. + */ + +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001 +#define TIMG_CLK_EN_S 31 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_TIMG_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h new file mode 100644 index 00000000000..c9e5a01ffbb --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h @@ -0,0 +1,1846 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_UART_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UART_FIFO_REG register + * FIFO data register + */ + +#define UART_FIFO_REG(i) (REG_UART_AHB_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * This register stores one byte data read from RX FIFO. + */ + +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FF +#define UART_RXFIFO_RD_BYTE_S 0 + +/* UART_INT_RAW_REG register + * Raw interrupt status + */ + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) + +/* UART_WAKEUP_INT_RAW : RO; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes + * more times than what UART_ACTIVE_THRESHOLD specifies in Light-sleep mode. + */ + +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001 +#define UART_WAKEUP_INT_RAW_S 19 + +/* UART_AT_CMD_CHAR_DET_INT_RAW : RO; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the + * configured UART_AT_CMD CHAR. + */ + +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 + +/* UART_RS485_CLASH_INT_RAW : RO; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between + * transmitter and receiver in RS485 mode. + */ + +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001 +#define UART_RS485_CLASH_INT_RAW_S 17 + +/* UART_RS485_FRM_ERR_INT_RAW : RO; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data + * frame error from the echo of transmitter in RS485 mode. + */ + +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 + +/* UART_RS485_PARITY_ERR_INT_RAW : RO; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity + * error from the echo of transmitter in RS485 mode. + */ + +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 + +/* UART_TX_DONE_INT_RAW : RO; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has sent out + * all data in FIFO. + */ + +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001 +#define UART_TX_DONE_INT_RAW_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the + * shortest duration after sending the last data. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 + +/* UART_TX_BRK_DONE_INT_RAW : RO; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes + * sending NULL characters, after all data in TX FIFO are sent. + */ + +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001 +#define UART_TX_BRK_DONE_INT_RAW_S 12 + +/* UART_GLITCH_DET_INT_RAW : RO; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch + * in the middle of a start bit. + */ + +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001 +#define UART_GLITCH_DET_INT_RAW_S 11 + +/* UART_SW_XOFF_INT_RAW : RO; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives XOFF + * character when UART_SW_FLOW_CON_EN is set to 1. + */ + +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001 +#define UART_SW_XOFF_INT_RAW_S 10 + +/* UART_SW_XON_INT_RAW : RO; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver receives XON + * character when UART_SW_FLOW_CON_EN is set to 1. + */ + +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001 +#define UART_SW_XON_INT_RAW_S 9 + +/* UART_RXFIFO_TOUT_INT_RAW : RO; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time + * than UART_RX_TOUT_THRHD to receive a byte. + */ + +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 + +/* UART_BRK_DET_INT_RAW : RO; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 + * after the stop bit. + */ + +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001 +#define UART_BRK_DET_INT_RAW_S 7 + +/* UART_CTS_CHG_INT_RAW : RO; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge + * change of CTSn signal. + */ + +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001 +#define UART_CTS_CHG_INT_RAW_S 6 + +/* UART_DSR_CHG_INT_RAW : RO; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge + * change of DSRn signal. + */ + +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001 +#define UART_DSR_CHG_INT_RAW_S 5 + +/* UART_RXFIFO_OVF_INT_RAW : RO; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more + * data than the FIFO can store. + */ + +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001 +#define UART_RXFIFO_OVF_INT_RAW_S 4 + +/* UART_FRM_ERR_INT_RAW : RO; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data + * frame error. + */ + +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001 +#define UART_FRM_ERR_INT_RAW_S 3 + +/* UART_PARITY_ERR_INT_RAW : RO; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity + * error in the data. + */ + +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001 +#define UART_PARITY_ERR_INT_RAW_S 2 + +/* UART_TXFIFO_EMPTY_INT_RAW : RO; bitpos: [1]; default: 0; + * This interrupt raw bit turns to high level when the amount of data in TX + * FIFO is less than what UART_TXFIFO_EMPTY_THRHD specifies. + */ + +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 + +/* UART_RXFIFO_FULL_INT_RAW : RO; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more + * data than what UART_RXFIFO_FULL_THRHD specifies. + */ + +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +/* UART_INT_ST_REG register + * Masked interrupt status + */ + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) + +/* UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for UART_WAKEUP_INT_RAW when UART_WAKEUP_INT_ENA + * is set to 1. + */ + +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001 +#define UART_WAKEUP_INT_ST_S 19 + +/* UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for UART_AT_CMD_DET_INT_RAW when + * UART_AT_CMD_CHAR_DET_INT_ENA is set to 1. + */ + +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 + +/* UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for UART_RS485_CLASH_INT_RAW when + * UART_RS485_CLASH_INT_ENA is set to 1. + */ + +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001 +#define UART_RS485_CLASH_INT_ST_S 17 + +/* UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for UART_RS485_FRM_ERR_INT_RAW when + * UART_RS485_FM_ERR_INT_ENA is set to 1. + */ + +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_ST_S 16 + +/* UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for UART_RS485_PARITY_ERR_INT_RAW when + * UART_RS485_PARITY_INT_ENA is set to 1. + */ + +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 + +/* UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for UART_TX_DONE_INT_RAW when UART_TX_DONE_INT_ENA + * is set to 1. + */ + +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001 +#define UART_TX_DONE_INT_ST_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the status bit for UART_TX_BRK_IDLE_DONE_INT_RAW when + * UART_TX_BRK_IDLE_DONE_INT_ENA is set to 1. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 + +/* UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for UART_TX_BRK_DONE_INT_RAW when + * UART_TX_BRK_DONE_INT_ENA is set to 1. + */ + +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001 +#define UART_TX_BRK_DONE_INT_ST_S 12 + +/* UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for UART_GLITCH_DET_INT_RAW when + * UART_GLITCH_DET_INT_ENA is set to 1. + */ + +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001 +#define UART_GLITCH_DET_INT_ST_S 11 + +/* UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for UART_SW_XOFF_INT_RAW when UART_SW_XOFF_INT_ENA + * is set to 1. + */ + +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001 +#define UART_SW_XOFF_INT_ST_S 10 + +/* UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for UART_SW_XON_INT_RAW when UART_SW_XON_INT_ENA + * is set to 1. + */ + +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001 +#define UART_SW_XON_INT_ST_S 9 + +/* UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for UART_RXFIFO_TOUT_INT_RAW when + * UART_RXFIFO_TOUT_INT_ENA is set to 1. + */ + +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_ST_S 8 + +/* UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for UART_BRK_DET_INT_RAW when UART_BRK_DET_INT_ENA + * is set to 1. + */ + +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001 +#define UART_BRK_DET_INT_ST_S 7 + +/* UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for UART_CTS_CHG_INT_RAW when UART_CTS_CHG_INT_ENA + * is set to 1. + */ + +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001 +#define UART_CTS_CHG_INT_ST_S 6 + +/* UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for UART_DSR_CHG_INT_RAW when UART_DSR_CHG_INT_ENA + * is set to 1. + */ + +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001 +#define UART_DSR_CHG_INT_ST_S 5 + +/* UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for UART_RXFIFO_OVF_INT_RAW when + * UART_RXFIFO_OVF_INT_ENA is set to 1. + */ + +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001 +#define UART_RXFIFO_OVF_INT_ST_S 4 + +/* UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for UART_FRM_ERR_INT_RAW when UART_FRM_ERR_INT_ENA + * is set to 1. + */ + +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001 +#define UART_FRM_ERR_INT_ST_S 3 + +/* UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for UART_PARITY_ERR_INT_RAW when + * UART_PARITY_ERR_INT_ENA is set to 1. + */ + +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001 +#define UART_PARITY_ERR_INT_ST_S 2 + +/* UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for UART_TXFIFO_EMPTY_INT_RAW when + * UART_TXFIFO_EMPTY_INT_ENA is set to 1. + */ + +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 + +/* UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for UART_RXFIFO_FULL_INT_RAW when + * UART_RXFIFO_FULL_INT_ENA is set to 1. + */ + +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +/* UART_INT_ENA_REG register + * Interrupt enable bits + */ + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) + +/* UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for UART_WAKEUP_INT_ST register. + */ + +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001 +#define UART_WAKEUP_INT_ENA_S 19 + +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for UART_AT_CMD_CHAR_DET_INT_ST register. + */ + +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 + +/* UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for UART_RS485_CLASH_INT_ST register. + */ + +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001 +#define UART_RS485_CLASH_INT_ENA_S 17 + +/* UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for UART_RS485_PARITY_ERR_INT_ST register. + */ + +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 + +/* UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for UART_RS485_PARITY_ERR_INT_ST register. + */ + +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 + +/* UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for UART_TX_DONE_INT_ST register. + */ + +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001 +#define UART_TX_DONE_INT_ENA_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for UART_TX_BRK_IDLE_DONE_INT_ST register. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 + +/* UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for UART_TX_BRK_DONE_INT_ST register. + */ + +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001 +#define UART_TX_BRK_DONE_INT_ENA_S 12 + +/* UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for UART_GLITCH_DET_INT_ST register. + */ + +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001 +#define UART_GLITCH_DET_INT_ENA_S 11 + +/* UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for UART_SW_XOFF_INT_ST register. + */ + +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001 +#define UART_SW_XOFF_INT_ENA_S 10 + +/* UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for UART_SW_XON_INT_ST register. + */ + +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001 +#define UART_SW_XON_INT_ENA_S 9 + +/* UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for UART_RXFIFO_TOUT_INT_ST register. + */ + +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 + +/* UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for UART_BRK_DET_INT_ST register. + */ + +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001 +#define UART_BRK_DET_INT_ENA_S 7 + +/* UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for UART_CTS_CHG_INT_ST register. + */ + +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001 +#define UART_CTS_CHG_INT_ENA_S 6 + +/* UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for UART_DSR_CHG_INT_ST register. + */ + +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001 +#define UART_DSR_CHG_INT_ENA_S 5 + +/* UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for UART_RXFIFO_OVF_INT_ST register. + */ + +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001 +#define UART_RXFIFO_OVF_INT_ENA_S 4 + +/* UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for UART_FRM_ERR_INT_ST register. + */ + +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001 +#define UART_FRM_ERR_INT_ENA_S 3 + +/* UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for UART_PARITY_ERR_INT_ST register. + */ + +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001 +#define UART_PARITY_ERR_INT_ENA_S 2 + +/* UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for UART_TXFIFO_EMPTY_INT_ST register. + */ + +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 + +/* UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for UART_RXFIFO_FULL_INT_ST register. + */ + +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +/* UART_INT_CLR_REG register + * Interrupt clear bits + */ + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) + +/* UART_WAKEUP_INT_CLR : WO; bitpos: [19]; default: 0; + * Set this bit to clear UART_WAKEUP_INT_RAW interrupt. + */ + +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001 +#define UART_WAKEUP_INT_CLR_S 19 + +/* UART_AT_CMD_CHAR_DET_INT_CLR : WO; bitpos: [18]; default: 0; + * Set this bit to clear UART_AT_CMD_CHAR_DET_INT_RAW interrupt. + */ + +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 + +/* UART_RS485_CLASH_INT_CLR : WO; bitpos: [17]; default: 0; + * Set this bit to clear UART_RS485_CLASH_INT_RAW interrupt. + */ + +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001 +#define UART_RS485_CLASH_INT_CLR_S 17 + +/* UART_RS485_FRM_ERR_INT_CLR : WO; bitpos: [16]; default: 0; + * Set this bit to clear UART_RS485_FRM_ERR_INT_RAW interrupt. + */ + +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 + +/* UART_RS485_PARITY_ERR_INT_CLR : WO; bitpos: [15]; default: 0; + * Set this bit to clear UART_RS485_PARITY_ERR_INT_RAW interrupt. + */ + +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 + +/* UART_TX_DONE_INT_CLR : WO; bitpos: [14]; default: 0; + * Set this bit to clear UART_TX_DONE_INT_RAW interrupt. + */ + +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001 +#define UART_TX_DONE_INT_CLR_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO; bitpos: [13]; default: 0; + * Set this bit to clear UART_TX_BRK_IDLE_DONE_INT_RAW interrupt. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 + +/* UART_TX_BRK_DONE_INT_CLR : WO; bitpos: [12]; default: 0; + * Set this bit to clear UART_TX_BRK_DONE_INT_RAW interrupt. + */ + +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001 +#define UART_TX_BRK_DONE_INT_CLR_S 12 + +/* UART_GLITCH_DET_INT_CLR : WO; bitpos: [11]; default: 0; + * Set this bit to clear UART_GLITCH_DET_INT_RAW interrupt. + */ + +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001 +#define UART_GLITCH_DET_INT_CLR_S 11 + +/* UART_SW_XOFF_INT_CLR : WO; bitpos: [10]; default: 0; + * Set this bit to clear UART_SW_XOFF_INT_RAW interrupt. + */ + +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001 +#define UART_SW_XOFF_INT_CLR_S 10 + +/* UART_SW_XON_INT_CLR : WO; bitpos: [9]; default: 0; + * Set this bit to clear UART_SW_XON_INT_RAW interrupt. + */ + +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001 +#define UART_SW_XON_INT_CLR_S 9 + +/* UART_RXFIFO_TOUT_INT_CLR : WO; bitpos: [8]; default: 0; + * Set this bit to clear UART_RXFIFO_TOUT_INT_RAW interrupt. + */ + +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 + +/* UART_BRK_DET_INT_CLR : WO; bitpos: [7]; default: 0; + * Set this bit to clear UART_BRK_DET_INT_RAW interrupt. + */ + +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001 +#define UART_BRK_DET_INT_CLR_S 7 + +/* UART_CTS_CHG_INT_CLR : WO; bitpos: [6]; default: 0; + * Set this bit to clear UART_CTS_CHG_INT_RAW interrupt. + */ + +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001 +#define UART_CTS_CHG_INT_CLR_S 6 + +/* UART_DSR_CHG_INT_CLR : WO; bitpos: [5]; default: 0; + * Set this bit to clear UART_DSR_CHG_INT_RAW interrupt. + */ + +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001 +#define UART_DSR_CHG_INT_CLR_S 5 + +/* UART_RXFIFO_OVF_INT_CLR : WO; bitpos: [4]; default: 0; + * Set this bit to clear UART_UART_RXFIFO_OVF_INT_RAW interrupt. + */ + +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001 +#define UART_RXFIFO_OVF_INT_CLR_S 4 + +/* UART_FRM_ERR_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear UART_FRM_ERR_INT_RAW interrupt. + */ + +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001 +#define UART_FRM_ERR_INT_CLR_S 3 + +/* UART_PARITY_ERR_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear UART_PARITY_ERR_INT_RAW interrupt. + */ + +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001 +#define UART_PARITY_ERR_INT_CLR_S 2 + +/* UART_TXFIFO_EMPTY_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear UART_TXFIFO_EMPTY_INT_RAW interrupt. + */ + +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 + +/* UART_RXFIFO_FULL_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear UART_THE RXFIFO_FULL_INT_RAW interrupt. + */ + +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +/* UART_CLKDIV_REG register + * Clock divider configuration + */ + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) + +/* UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divisor. + */ + +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000F +#define UART_CLKDIV_FRAG_S 20 + +/* UART_CLKDIV : R/W; bitpos: [19:0]; default: 694; + * The integral part of the frequency divisor. + */ + +#define UART_CLKDIV 0x000FFFFF +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x000FFFFF +#define UART_CLKDIV_S 0 + +/* UART_AUTOBAUD_REG register + * Autobaud configuration register + */ + +#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) + +/* UART_GLITCH_FILT : R/W; bitpos: [15:8]; default: 16; + * when input pulse width is lower than this value, the pulse is ignored. + * This register is used in autobaud detect process. + */ + +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FF +#define UART_GLITCH_FILT_S 8 + +/* UART_AUTOBAUD_EN : R/W; bitpos: [0]; default: 0; + * This is the enable bit for detecting baudrate. + */ + +#define UART_AUTOBAUD_EN (BIT(0)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001 +#define UART_AUTOBAUD_EN_S 0 + +/* UART_STATUS_REG register + * UART status register + */ + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) + +/* UART_TXD : RO; bitpos: [31]; default: 0; + * This bit represents the level of the internal UART TXD signal. + */ + +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001 +#define UART_TXD_S 31 + +/* UART_RTSN : RO; bitpos: [30]; default: 0; + * This bit represents the level of the internal UART RTS signal. + */ + +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001 +#define UART_RTSN_S 30 + +/* UART_DTRN : RO; bitpos: [29]; default: 0; + * This bit represents the level of the internal UART DTR signal. + */ + +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001 +#define UART_DTRN_S 29 + +/* UART_TXFIFO_CNT : RO; bitpos: [25:16]; default: 0; + * Stores the byte number of data in TX FIFO. + */ + +#define UART_TXFIFO_CNT 0x000003FF +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000003FF +#define UART_TXFIFO_CNT_S 16 + +/* UART_RXD : RO; bitpos: [15]; default: 0; + * This register represent the level value of the internal UART RXD signal. + */ + +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001 +#define UART_RXD_S 15 + +/* UART_CTSN : RO; bitpos: [14]; default: 0; + * This register represent the level value of the internal UART CTS signal. + */ + +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001 +#define UART_CTSN_S 14 + +/* UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal UART DSR signal. + */ + +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001 +#define UART_DSRN_S 13 + +/* UART_RXFIFO_CNT : RO; bitpos: [9:0]; default: 0; + * Stores the byte number of valid data in RX FIFO. + */ + +#define UART_RXFIFO_CNT 0x000003FF +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000003FF +#define UART_RXFIFO_CNT_S 0 + +/* UART_CONF0_REG register + * Configuration register 0 + */ + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) + +/* UART_MEM_CLK_EN : R/W; bitpos: [28]; default: 1; + * UART memory clock gate enable signal. + * 1: UART memory powers on, the data of which can be read and written. + * 0: UART memory powers down. + */ + +#define UART_MEM_CLK_EN (BIT(28)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001 +#define UART_MEM_CLK_EN_S 28 + +/* UART_TICK_REF_ALWAYS_ON : R/W; bitpos: [27]; default: 1; + * This register is used to select the clock. + * 1'h1: APB_CLK. + * 1'h0: REF_TICK. + */ + +#define UART_TICK_REF_ALWAYS_ON (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_M (UART_TICK_REF_ALWAYS_ON_V << UART_TICK_REF_ALWAYS_ON_S) +#define UART_TICK_REF_ALWAYS_ON_V 0x00000001 +#define UART_TICK_REF_ALWAYS_ON_S 27 + +/* UART_ERR_WR_MASK : R/W; bitpos: [26]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: + * Receiver stores the data even if the received data is wrong. + */ + +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001 +#define UART_ERR_WR_MASK_S 26 + +/* UART_CLK_EN : R/W; bitpos: [25]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when + * application writes registers. + */ + +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001 +#define UART_CLK_EN_S 25 + +/* UART_DTR_INV : R/W; bitpos: [24]; default: 0; + * Set this bit to inverse the level value of UART DTR signal. + */ + +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001 +#define UART_DTR_INV_S 24 + +/* UART_RTS_INV : R/W; bitpos: [23]; default: 0; + * Set this bit to inverse the level value of UART RTS signal. + */ + +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001 +#define UART_RTS_INV_S 23 + +/* UART_TXD_INV : R/W; bitpos: [22]; default: 0; + * Set this bit to inverse the level value of UART TXD signal. + */ + +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001 +#define UART_TXD_INV_S 22 + +/* UART_DSR_INV : R/W; bitpos: [21]; default: 0; + * Set this bit to inverse the level value of UART DSR signal. + */ + +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001 +#define UART_DSR_INV_S 21 + +/* UART_CTS_INV : R/W; bitpos: [20]; default: 0; + * Set this bit to inverse the level value of UART CTS signal. + */ + +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001 +#define UART_CTS_INV_S 20 + +/* UART_RXD_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of UART RXD signal. + */ + +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001 +#define UART_RXD_INV_S 19 + +/* UART_TXFIFO_RST : R/W; bitpos: [18]; default: 0; + * Set this bit to reset the UART TX FIFO. + */ + +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001 +#define UART_TXFIFO_RST_S 18 + +/* UART_RXFIFO_RST : R/W; bitpos: [17]; default: 0; + * Set this bit to reset the UART RX FIFO. + */ + +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001 +#define UART_RXFIFO_RST_S 17 + +/* UART_IRDA_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to enable IrDA protocol. + */ + +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001 +#define UART_IRDA_EN_S 16 + +/* UART_TX_FLOW_EN : R/W; bitpos: [15]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001 +#define UART_TX_FLOW_EN_S 15 + +/* UART_LOOPBACK : R/W; bitpos: [14]; default: 0; + * Set this bit to enable UART loopback test mode. + */ + +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001 +#define UART_LOOPBACK_S 14 + +/* UART_IRDA_RX_INV : R/W; bitpos: [13]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001 +#define UART_IRDA_RX_INV_S 13 + +/* UART_IRDA_TX_INV : R/W; bitpos: [12]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001 +#define UART_IRDA_TX_INV_S 12 + +/* UART_IRDA_WCTL : R/W; bitpos: [11]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set + * IrDA transmitter's 11th bit to 0. + */ + +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001 +#define UART_IRDA_WCTL_S 11 + +/* UART_IRDA_TX_EN : R/W; bitpos: [10]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001 +#define UART_IRDA_TX_EN_S 10 + +/* UART_IRDA_DPLX : R/W; bitpos: [9]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001 +#define UART_IRDA_DPLX_S 9 + +/* UART_TXD_BRK : R/W; bitpos: [8]; default: 0; + * Set this bit to enable transmitter to send NULL when the process of + * sending data is done. + */ + +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001 +#define UART_TXD_BRK_S 8 + +/* UART_SW_DTR : R/W; bitpos: [7]; default: 0; + * This register is used to configure the software DTR signal which is used + * in software flow control. + */ + +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001 +#define UART_SW_DTR_S 7 + +/* UART_SW_RTS : R/W; bitpos: [6]; default: 0; + * This register is used to configure the software RTS signal which is used + * in software flow control. + */ + +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001 +#define UART_SW_RTS_S 6 + +/* UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + * 1: 1 bit 2: 1.5 bits 3: 2 bits. + */ + +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003 +#define UART_STOP_BIT_NUM_S 4 + +/* UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + * 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits. + */ + +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003 +#define UART_BIT_NUM_S 2 + +/* UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable UART parity check. + */ + +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001 +#define UART_PARITY_EN_S 1 + +/* UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + * 1'h0: even. 1'h1: odd. + */ + +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001 +#define UART_PARITY_S 0 + +/* UART_CONF1_REG register + * Configuration register 1 + */ + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) + +/* UART_RX_TOUT_EN : R/W; bitpos: [31]; default: 0; + * This is the enable bit for UART receiver's timeout function. + */ + +#define UART_RX_TOUT_EN (BIT(31)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001 +#define UART_RX_TOUT_EN_S 31 + +/* UART_RX_FLOW_EN : R/W; bitpos: [30]; default: 0; + * This is the flow enable bit for UART receiver. + * 1'h1: Choose software flow control with configuring sw_rts signal. 1'h0: + * Disable software flow control. + */ + +#define UART_RX_FLOW_EN (BIT(30)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001 +#define UART_RX_FLOW_EN_S 30 + +/* UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [29]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control + * works. + */ + +#define UART_RX_TOUT_FLOW_DIS (BIT(29)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001 +#define UART_RX_TOUT_FLOW_DIS_S 29 + +/* UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [17:9]; default: 96; + * It will produce UART_TXFIFO_EMPTY_INT interrupt when the data amount in + * TX FIFO is less than this register value. + */ + +#define UART_TXFIFO_EMPTY_THRHD 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_S 9 + +/* UART_RXFIFO_FULL_THRHD : R/W; bitpos: [8:0]; default: 96; + * It will produce UART_RXFIFO_FULL_INT interrupt when receiver receives + * more data than this register value. + */ + +#define UART_RXFIFO_FULL_THRHD 0x000001FF +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000001FF +#define UART_RXFIFO_FULL_THRHD_S 0 + +/* UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration register + */ + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) + +/* UART_LOWPULSE_MIN_CNT : RO; bitpos: [19:0]; default: 1048575; + * This register stores the value of the minimum duration time of the low + * level pulse. It is used in baud rate detection. + */ + +#define UART_LOWPULSE_MIN_CNT 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +/* UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration register + */ + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c) + +/* UART_HIGHPULSE_MIN_CNT : RO; bitpos: [19:0]; default: 1048575; + * This register stores the value of the maximum duration time for the high + * level pulse. It is used in baud rate detection. + */ + +#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/* UART_RXD_CNT_REG register + * Autobaud edge change count register + */ + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) + +/* UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud + * rate detection. + */ + +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FF +#define UART_RXD_EDGE_CNT_S 0 + +/* UART_FLOW_CONF_REG register + * Software flow control configuration + */ + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) + +/* UART_SEND_XOFF : R/W; bitpos: [5]; default: 0; + * Set this bit to send XOFF character. It is cleared by hardware + * automatically. + */ + +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001 +#define UART_SEND_XOFF_S 5 + +/* UART_SEND_XON : R/W; bitpos: [4]; default: 0; + * Set this bit to send XON character. It is cleared by hardware + * automatically. + */ + +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001 +#define UART_SEND_XON_S 4 + +/* UART_FORCE_XOFF : R/W; bitpos: [3]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001 +#define UART_FORCE_XOFF_S 3 + +/* UART_FORCE_XON : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001 +#define UART_FORCE_XON_S 2 + +/* UART_XONOFF_DEL : R/W; bitpos: [1]; default: 0; + * Set this bit to remove flow control character from the received data. + */ + +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001 +#define UART_XONOFF_DEL_S 1 + +/* UART_SW_FLOW_CON_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable software flow control. It is used with register + * SW_XON or SW_XOFF. + */ + +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001 +#define UART_SW_FLOW_CON_EN_S 0 + +/* UART_SLEEP_CONF_REG register + * Sleeping mode configuration + */ + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) + +/* UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The UART is activated from light sleeping mode when the input rxd edge + * changes more times than this register value. + */ + +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FF +#define UART_ACTIVE_THRESHOLD_S 0 + +/* UART_SWFC_CONF0_REG register + * Software flow control character configuration + */ + +#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3c) + +/* UART_XOFF_CHAR : R/W; bitpos: [16:9]; default: 19; + * This register stores the XOFF flow control character. + */ + +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FF +#define UART_XOFF_CHAR_S 9 + +/* UART_XOFF_THRESHOLD : R/W; bitpos: [8:0]; default: 224; + * When the data amount in RX FIFO is more than this register value with + * UART_SW_FLOW_CON_EN set to 1, it will send a XOFF character. + */ + +#define UART_XOFF_THRESHOLD 0x000001FF +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000001FF +#define UART_XOFF_THRESHOLD_S 0 + +/* UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ + +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) + +/* UART_XON_CHAR : R/W; bitpos: [16:9]; default: 17; + * This register stores the XON flow control character. + */ + +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FF +#define UART_XON_CHAR_S 9 + +/* UART_XON_THRESHOLD : R/W; bitpos: [8:0]; default: 0; + * When the data amount in RX FIFO is less than this register value with + * UART_SW_FLOW_CON_EN set to 1, it will send a XON character. + */ + +#define UART_XON_THRESHOLD 0x000001FF +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000001FF +#define UART_XON_THRESHOLD_S 0 + +/* UART_IDLE_CONF_REG register + * Frame-end idle configuration + */ + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x44) + +/* UART_TX_BRK_NUM : R/W; bitpos: [27:20]; default: 10; + * This register is used to configure the number of 0 to be sent after the + * process of sending data is done. It is active when UART_TXD_BRK is set to + * 1. + */ + +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FF +#define UART_TX_BRK_NUM_S 20 + +/* UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FF +#define UART_TX_IDLE_NUM_S 10 + +/* UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive + * one byte data than this register value. + */ + +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FF +#define UART_RX_IDLE_THRHD_S 0 + +/* UART_RS485_CONF_REG register + * RS485 mode configuration + */ + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x48) + +/* UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000F +#define UART_RS485_TX_DLY_NUM_S 6 + +/* UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001 +#define UART_RS485_RX_DLY_NUM_S 5 + +/* UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable RS485 transmitter to send data when RS485 receiver line is + * busy. + * 1'h0: RS485 transmitter should not send data when its receiver is busy. + */ + +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001 +#define UART_RS485RXBY_TX_EN_S 4 + +/* UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter + * is transmitting data in RS485 mode. + */ + +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001 +#define UART_RS485TX_RX_EN_S 3 + +/* UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001 +#define UART_DL1_EN_S 2 + +/* UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001 +#define UART_DL0_EN_S 1 + +/* UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the RS485 mode. + */ + +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001 +#define UART_RS485_EN_S 0 + +/* UART_AT_CMD_PRECNT_REG register + * Pre-sequence timing configuration + */ + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x4c) + +/* UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the + * first AT_CMD is received by receiver. + * It will not take the next data received as AT_CMD character when the + * duration is less than this register value. + */ + +#define UART_PRE_IDLE_NUM 0x0000FFFF +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFF +#define UART_PRE_IDLE_NUM_S 0 + +/* UART_AT_CMD_POSTCNT_REG register + * Post-sequence timing configuration + */ + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x50) + +/* UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last + * AT_CMD and the next data. + * It will not take the previous data as AT_CMD character when the duration + * is less than this register value. + */ + +#define UART_POST_IDLE_NUM 0x0000FFFF +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFF +#define UART_POST_IDLE_NUM_S 0 + +/* UART_AT_CMD_GAPTOUT_REG register + * Timeout configuration + */ + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x54) + +/* UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the AT_CMD + * chars. + * It will not take the data as continuous AT_CMD chars when the duration + * time is less than this register value. + */ + +#define UART_RX_GAP_TOUT 0x0000FFFF +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFF +#define UART_RX_GAP_TOUT_S 0 + +/* UART_AT_CMD_CHAR_REG register + * AT Escape Sequence Selection Configuration + */ + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x58) + +/* UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the number of continuous AT_CMD chars + * received by receiver. + */ + +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FF +#define UART_CHAR_NUM_S 8 + +/* UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of AT_CMD character. + */ + +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FF +#define UART_AT_CMD_CHAR_S 0 + +/* UART_MEM_CONF_REG register + * UART threshold and allocation configuration + */ + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x5c) + +/* UART_MEM_FORCE_PU : R/W; bitpos: [27]; default: 0; + * Set this bit to force power up UART memory. + */ + +#define UART_MEM_FORCE_PU (BIT(27)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001 +#define UART_MEM_FORCE_PU_S 27 + +/* UART_MEM_FORCE_PD : R/W; bitpos: [26]; default: 0; + * Set this bit to force power down UART memory. + */ + +#define UART_MEM_FORCE_PD (BIT(26)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001 +#define UART_MEM_FORCE_PD_S 26 + +/* UART_RX_TOUT_THRHD : R/W; bitpos: [25:16]; default: 10; + * This register is used to configure the threshold time that receiver takes + * to receive one byte. + * The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver + * takes more time to receive one byte with UART RX_TOUT_EN set to 1. + */ + +#define UART_RX_TOUT_THRHD 0x000003FF +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FF +#define UART_RX_TOUT_THRHD_S 16 + +/* UART_RX_FLOW_THRHD : R/W; bitpos: [15:7]; default: 0; + * This register is used to configure the maximum amount of data that can be + * received when hardware flow control works. + */ + +#define UART_RX_FLOW_THRHD 0x000001FF +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000001FF +#define UART_RX_FLOW_THRHD_S 7 + +/* UART_TX_SIZE : R/W; bitpos: [6:4]; default: 1; + * This register is used to configure the amount of mem allocated for TX + * FIFO. The default number is 128 bytes. + */ + +#define UART_TX_SIZE 0x00000007 +#define UART_TX_SIZE_M (UART_TX_SIZE_V << UART_TX_SIZE_S) +#define UART_TX_SIZE_V 0x00000007 +#define UART_TX_SIZE_S 4 + +/* UART_RX_SIZE : R/W; bitpos: [3:1]; default: 1; + * This register is used to configure the amount of mem allocated for RX + * FIFO. The default number is 128 bytes. + */ + +#define UART_RX_SIZE 0x00000007 +#define UART_RX_SIZE_M (UART_RX_SIZE_V << UART_RX_SIZE_S) +#define UART_RX_SIZE_V 0x00000007 +#define UART_RX_SIZE_S 1 + +/* UART_MEM_TX_STATUS_REG register + * TX FIFO write and read offset address + */ + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) + +/* UART_TX_RADDR : RO; bitpos: [20:11]; default: 0; + * This register stores the offset address in TX FIFO when TX FSM reads data + * via Tx_FIFO_Ctrl. + */ + +#define UART_TX_RADDR 0x000003FF +#define UART_TX_RADDR_M (UART_TX_RADDR_V << UART_TX_RADDR_S) +#define UART_TX_RADDR_V 0x000003FF +#define UART_TX_RADDR_S 11 + +/* UART_APB_TX_WADDR : RO; bitpos: [9:0]; default: 0; + * This register stores the offset address in TX FIFO when software writes + * TX FIFO via APB. + */ + +#define UART_APB_TX_WADDR 0x000003FF +#define UART_APB_TX_WADDR_M (UART_APB_TX_WADDR_V << UART_APB_TX_WADDR_S) +#define UART_APB_TX_WADDR_V 0x000003FF +#define UART_APB_TX_WADDR_S 0 + +/* UART_MEM_RX_STATUS_REG register + * RX FIFO write and read offset address + */ + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) + +/* UART_RX_WADDR : RO; bitpos: [20:11]; default: 0; + * This register stores the offset address in RX FIFO when Rx_FIFO_Ctrl + * writes RX FIFO. + */ + +#define UART_RX_WADDR 0x000003FF +#define UART_RX_WADDR_M (UART_RX_WADDR_V << UART_RX_WADDR_S) +#define UART_RX_WADDR_V 0x000003FF +#define UART_RX_WADDR_S 11 + +/* UART_APB_RX_RADDR : RO; bitpos: [9:0]; default: 0; + * This register stores the offset address in RX_FIFO when software reads + * data from RX FIFO via APB. + */ + +#define UART_APB_RX_RADDR 0x000003FF +#define UART_APB_RX_RADDR_M (UART_APB_RX_RADDR_V << UART_APB_RX_RADDR_S) +#define UART_APB_RX_RADDR_V 0x000003FF +#define UART_APB_RX_RADDR_S 0 + +/* UART_FSM_STATUS_REG register + * UART transmit and receive status + */ + +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) + +/* UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000F +#define UART_ST_UTX_OUT_S 4 + +/* UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000F +#define UART_ST_URX_OUT_S 0 + +/* UART_POSPULSE_REG register + * Autobaud high pulse register + */ + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) + +/* UART_POSEDGE_MIN_CNT : RO; bitpos: [19:0]; default: 1048575; + * This register stores the minimal input clock count between two positive + * edges. It is used in baud rate detection. + */ + +#define UART_POSEDGE_MIN_CNT 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +/* UART_NEGPULSE_REG register + * Autobaud low pulse register + */ + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x70) + +/* UART_NEGEDGE_MIN_CNT : RO; bitpos: [19:0]; default: 1048575; + * This register stores the minimal input clock count between two negative + * edges. It is used in baud rate detection. + */ + +#define UART_NEGEDGE_MIN_CNT 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +/* UART_DATE_REG register + * UART version control register + */ + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x74) + +/* UART_DATE : R/W; bitpos: [31:0]; default: 403187712; + * This is the version control register. + */ + +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +/* UART_ID_REG register + * UART ID register + */ + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x78) + +/* UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the UART_ID. + */ + +#define UART_ID 0xFFFFFFFF +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFF +#define UART_ID_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_UART_H */ diff --git a/arch/xtensa/src/lx6/Toolchain.defs b/arch/xtensa/src/lx6/Toolchain.defs index 72181b673fb..525cb4f481c 100644 --- a/arch/xtensa/src/lx6/Toolchain.defs +++ b/arch/xtensa/src/lx6/Toolchain.defs @@ -36,7 +36,7 @@ ARCHCPUFLAGS = ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) else - MAXOPTIMIZATION := -Os + MAXOPTIMIZATION ?= -Os endif # Default toolchain diff --git a/arch/xtensa/src/lx7/Kconfig b/arch/xtensa/src/lx7/Kconfig new file mode 100644 index 00000000000..78fc8a49e0a --- /dev/null +++ b/arch/xtensa/src/lx7/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_LX7 + +endif # ARCH_CHIP_LX7 diff --git a/arch/xtensa/src/lx7/Toolchain.defs b/arch/xtensa/src/lx7/Toolchain.defs new file mode 100644 index 00000000000..01d6d193ca4 --- /dev/null +++ b/arch/xtensa/src/lx7/Toolchain.defs @@ -0,0 +1,67 @@ +############################################################################ +# arch/xtensa/src/lx7/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Supported toolchains +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# FPU options, etc. +# MAXOPTIMIZATION The maximum optimization level that results in +# reliable code generation. +# + +CROSSDEV = xtensa-esp32s2-elf- + +ARCHCPUFLAGS = + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION := -Os +endif + +# Default toolchain + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E -P -x c +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +# Add the builtin library + +EXTRA_LIBS += -lgcc +EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name`"}" + +ifneq ($(CONFIG_LIBM),y) + EXTRA_LIBS += -lm + EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a`"}" +endif + +ifeq ($(CONFIG_CXX_LIBSUPCXX),y) + EXTRA_LIBS += -lsupc++ + EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a`"}" +endif diff --git a/arch/z16/src/common/z16_blocktask.c b/arch/z16/src/common/z16_blocktask.c index 3de333b145a..0428f7c1878 100644 --- a/arch/z16/src/common/z16_blocktask.c +++ b/arch/z16/src/common/z16_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/z16/src/common/z16_createstack.c b/arch/z16/src/common/z16_createstack.c index 356bde3e5b4..2810ddab2d8 100644 --- a/arch/z16/src/common/z16_createstack.c +++ b/arch/z16/src/common/z16_createstack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/z16/src/common/z16_reprioritizertr.c b/arch/z16/src/common/z16_reprioritizertr.c index b047dcc33c1..c688493d741 100644 --- a/arch/z16/src/common/z16_reprioritizertr.c +++ b/arch/z16/src/common/z16_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/z16/src/common/z16_sigdeliver.c b/arch/z16/src/common/z16_sigdeliver.c index 2a91f25897f..28bb314bdbb 100644 --- a/arch/z16/src/common/z16_sigdeliver.c +++ b/arch/z16/src/common/z16_sigdeliver.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/z16/src/common/z16_unblocktask.c b/arch/z16/src/common/z16_unblocktask.c index f113ca2d0ef..74d2d6664e9 100644 --- a/arch/z16/src/common/z16_unblocktask.c +++ b/arch/z16/src/common/z16_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/z16/src/common/z16_usestack.c b/arch/z16/src/common/z16_usestack.c index a5a374c8de9..cc5e3c5c942 100644 --- a/arch/z16/src/common/z16_usestack.c +++ b/arch/z16/src/common/z16_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/z16/src/z16f/z16f_serial.c b/arch/z16/src/z16f/z16f_serial.c index a6b8db21601..8b7ce5cd2e5 100644 --- a/arch/z16/src/z16f/z16f_serial.c +++ b/arch/z16/src/z16f/z16f_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/z16/src/z16f/z16f_sysexec.c b/arch/z16/src/z16f/z16f_sysexec.c index fafcc13fa70..296b427457c 100644 --- a/arch/z16/src/z16f/z16f_sysexec.c +++ b/arch/z16/src/z16f/z16f_sysexec.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/z16/src/z16f/z16f_timerisr.c b/arch/z16/src/z16f/z16f_timerisr.c index b5204f20ff3..63cd38d8906 100644 --- a/arch/z16/src/z16f/z16f_timerisr.c +++ b/arch/z16/src/z16f/z16f_timerisr.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/z80/src/Makefile.clang b/arch/z80/src/Makefile.clang index cb18d0f9312..93d8d918890 100644 --- a/arch/z80/src/Makefile.clang +++ b/arch/z80/src/Makefile.clang @@ -90,7 +90,7 @@ NUTTX = "$(TOPDIR)$(DELIM)nuttx$(EXEEXT)" nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT) $(LINKCMD) $(Q) echo "LD: nuttx into $(NUTTX)" $(Q) "$(LD)" -o $(NUTTX) $(HEAD_OBJ) -T $(LINKCMD) --orphan-handling=error --print-memory-usage \ - $(LIBPATHS) "-(" $(LDLIBS) "-)" $(LDFLAGS) -Map="$(TOPDIR)$(DELIM)nuttx.map" + $(LIBPATHS) "-(" $(LDLIBS) "-)" $(LDFLAGS) -Wl,-Map="$(TOPDIR)$(DELIM)nuttx.map" .depend: Makefile chip$(DELIM)Make.defs $(DEPSRCS) $(TOPDIR)$(DELIM).config $(Q) if [ -e board$(DELIM)Makefile ]; then \ diff --git a/arch/z80/src/common/z80_blocktask.c b/arch/z80/src/common/z80_blocktask.c index 5d521081757..ed40a561058 100644 --- a/arch/z80/src/common/z80_blocktask.c +++ b/arch/z80/src/common/z80_blocktask.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/arch/z80/src/common/z80_createstack.c b/arch/z80/src/common/z80_createstack.c index 16f837cfac6..5ba592387a2 100644 --- a/arch/z80/src/common/z80_createstack.c +++ b/arch/z80/src/common/z80_createstack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/z80/src/common/z80_reprioritizertr.c b/arch/z80/src/common/z80_reprioritizertr.c index 70a28325d20..fe8ba0e8452 100644 --- a/arch/z80/src/common/z80_reprioritizertr.c +++ b/arch/z80/src/common/z80_reprioritizertr.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/z80/src/common/z80_unblocktask.c b/arch/z80/src/common/z80_unblocktask.c index d88672ee415..bad43f0be34 100644 --- a/arch/z80/src/common/z80_unblocktask.c +++ b/arch/z80/src/common/z80_unblocktask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/z80/src/common/z80_usestack.c b/arch/z80/src/common/z80_usestack.c index 65bdef6a0b4..c11d4dd71b6 100644 --- a/arch/z80/src/common/z80_usestack.c +++ b/arch/z80/src/common/z80_usestack.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/z80/src/ez80/Toolchain.defs b/arch/z80/src/ez80/Toolchain.defs index f546288575a..eedd6d4dcd1 100644 --- a/arch/z80/src/ez80/Toolchain.defs +++ b/arch/z80/src/ez80/Toolchain.defs @@ -64,7 +64,7 @@ ARCHASMINCLUDES = -include chip/clang-compat.asm ARCHASMLIST = ARCHASMWARNINGS = -W -LDFLAGS += -gc-sections +LDFLAGS += -Wl,-gc-sections # Tool names/paths. @@ -72,7 +72,7 @@ CROSSDEV = ez80-none-elf- CC = $(CROSSDEV)clang CPP = $(CC) -E -P -x c STRIP = $(CROSSDEV)strip --strip-unneeded -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc AS = $(CROSSDEV)as AR = $(CROSSDEV)ar -r OBJCOPY= $(CROSSDEV)objcopy diff --git a/arch/z80/src/ez80/ez80_rtc.c b/arch/z80/src/ez80/ez80_rtc.c index 1a021dc5be2..040fdaf3d0f 100644 --- a/arch/z80/src/ez80/ez80_rtc.c +++ b/arch/z80/src/ez80/ez80_rtc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/z80/src/ez80/ez80_rtc_lowerhalf.c b/arch/z80/src/ez80/ez80_rtc_lowerhalf.c index 8b3bb874233..f7231b496bc 100644 --- a/arch/z80/src/ez80/ez80_rtc_lowerhalf.c +++ b/arch/z80/src/ez80/ez80_rtc_lowerhalf.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/z80/src/ez80/ez80_serial.c b/arch/z80/src/ez80/ez80_serial.c index 882c4372ea2..41e159b8a19 100644 --- a/arch/z80/src/ez80/ez80_serial.c +++ b/arch/z80/src/ez80/ez80_serial.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/z80/src/ez80/ez80_sigdeliver.c b/arch/z80/src/ez80/ez80_sigdeliver.c index 4f203a15e88..72e51fc3746 100644 --- a/arch/z80/src/ez80/ez80_sigdeliver.c +++ b/arch/z80/src/ez80/ez80_sigdeliver.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c index aaedd87ce97..90976cffd6f 100644 --- a/arch/z80/src/ez80/ez80_spi.c +++ b/arch/z80/src/ez80/ez80_spi.c @@ -274,19 +274,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = SPI_CTL_CPHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = SPI_CTL_CPOL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = (SPI_CTL_CPOL | SPI_CTL_CPHA); break; diff --git a/arch/z80/src/z180/Kconfig b/arch/z80/src/z180/Kconfig index f622c2eaac2..0ebfcb64233 100644 --- a/arch/z80/src/z180/Kconfig +++ b/arch/z80/src/z180/Kconfig @@ -318,6 +318,13 @@ config Z180_TOOLCHAIN_SDCCW endchoice +config Z180_MAX_TASKS + int "Max number of tasks for arch chip z180" + default 8 + ---help--- + The maximum number of simultaneously active tasks. This value must be + a power of two. + config LINKER_HOME_AREA hex "Physical start of _HOME area" default 0x0000 diff --git a/arch/z80/src/z180/z180_mmu.c b/arch/z80/src/z180/z180_mmu.c index 937d5f5a512..29e5d318965 100644 --- a/arch/z80/src/z180/z180_mmu.c +++ b/arch/z80/src/z180/z180_mmu.c @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -57,7 +58,7 @@ ****************************************************************************/ static GRAN_HANDLE g_physhandle; -static struct z180_cbr_s g_cbrs[CONFIG_MAX_TASKS]; +static struct z180_cbr_s g_cbrs[CONFIG_Z180_MAX_TASKS]; /**************************************************************************** * Private Functions @@ -78,7 +79,7 @@ static inline FAR struct z180_cbr_s *z180_mmu_alloccbr(void) { int i; - for (i = 0; i < CONFIG_MAX_TASKS; i++) + for (i = 0; i < CONFIG_Z180_MAX_TASKS; i++) { FAR struct z180_cbr_s *cbr = &g_cbrs[i]; if (cbr->crefs == 0) diff --git a/arch/z80/src/z180/z180_sigdeliver.c b/arch/z80/src/z180/z180_sigdeliver.c index 529d698d649..9045ec35564 100644 --- a/arch/z80/src/z180/z180_sigdeliver.c +++ b/arch/z80/src/z180/z180_sigdeliver.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c index e2c6976f951..fda6db6f03a 100644 --- a/arch/z80/src/z8/z8_serial.c +++ b/arch/z80/src/z8/z8_serial.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/z80/src/z8/z8_sigdeliver.c b/arch/z80/src/z8/z8_sigdeliver.c index 1b01f249317..5f72af98996 100644 --- a/arch/z80/src/z8/z8_sigdeliver.c +++ b/arch/z80/src/z8/z8_sigdeliver.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/z80/src/z80/z80_sigdeliver.c b/arch/z80/src/z80/z80_sigdeliver.c index d3574c3c05e..1ecf020852c 100644 --- a/arch/z80/src/z80/z80_sigdeliver.c +++ b/arch/z80/src/z80/z80_sigdeliver.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/audio/pcm_decode.c b/audio/pcm_decode.c index 69530f1f39d..15a4116632b 100644 --- a/audio/pcm_decode.c +++ b/audio/pcm_decode.c @@ -1182,14 +1182,16 @@ static int pcm_enqueuebuffer(FAR struct audio_lowerhalf_s *dev, priv->export.upper(priv->export.priv, AUDIO_CALLBACK_COMPLETE, NULL, OK); #endif - } #ifndef CONFIG_AUDIO_FORMAT_RAW + } + /* This is not a WAV file! */ auderr("ERROR: Invalid PCM WAV file\n"); - return -EINVAL; #endif + + return -EINVAL; } /**************************************************************************** diff --git a/binfmt/binfmt_initialize.c b/binfmt/binfmt_initialize.c index ccdad71449d..c660ad121c9 100644 --- a/binfmt/binfmt_initialize.c +++ b/binfmt/binfmt_initialize.c @@ -29,6 +29,8 @@ #include #include +#include + #include "binfmt.h" #ifndef CONFIG_BINFMT_DISABLE diff --git a/binfmt/binfmt_unloadmodule.c b/binfmt/binfmt_unloadmodule.c index 323e3c62806..e9b44555e7e 100644 --- a/binfmt/binfmt_unloadmodule.c +++ b/binfmt/binfmt_unloadmodule.c @@ -156,7 +156,7 @@ int unload_module(FAR struct binary_s *binp) { binfo("Unmapping address space: %p\n", binp->mapped); - munmap(binp->mapped, binp->mapsize); + file_munmap(binp->mapped, binp->mapsize); } /* Free allocated address spaces */ @@ -166,7 +166,11 @@ int unload_module(FAR struct binary_s *binp) if (binp->alloc[i]) { binfo("Freeing alloc[%d]: %p\n", i, binp->alloc[i]); +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) + up_textheap_free((FAR void *)binp->alloc[i]); +#else kumm_free((FAR void *)binp->alloc[i]); +#endif } } diff --git a/binfmt/builtin.c b/binfmt/builtin.c index 2bb7826af81..d6d79c17bae 100644 --- a/binfmt/builtin.c +++ b/binfmt/builtin.c @@ -78,7 +78,7 @@ static int builtin_loadbinary(FAR struct binary_s *binp, int nexports) { FAR const struct builtin_s *builtin; - int fd; + struct file file; int index; int ret; @@ -86,22 +86,23 @@ static int builtin_loadbinary(FAR struct binary_s *binp, /* Open the binary file for reading (only) */ - fd = nx_open(filename, O_RDONLY); - if (fd < 0) + ret = file_open(&file, filename, O_RDONLY); + if (ret < 0) { - berr("ERROR: Failed to open binary %s: %d\n", filename, fd); - return fd; + berr("ERROR: Failed to open binary %s: %d\n", filename, ret); + return ret; } /* If this file is a BINFS file system, then we can recover the name of * the file using the FIOC_FILENAME ioctl() call. */ - ret = nx_ioctl(fd, FIOC_FILENAME, (unsigned long)((uintptr_t)&filename)); + ret = file_ioctl(&file, FIOC_FILENAME, + (unsigned long)((uintptr_t)&filename)); if (ret < 0) { berr("ERROR: FIOC_FILENAME ioctl failed: %d\n", ret); - nx_close(fd); + file_close(&file); return ret; } @@ -113,7 +114,7 @@ static int builtin_loadbinary(FAR struct binary_s *binp, if (index < 0) { berr("ERROR: %s is not a builtin application\n", filename); - nx_close(fd); + file_close(&file); return index; } @@ -125,7 +126,7 @@ static int builtin_loadbinary(FAR struct binary_s *binp, binp->entrypt = builtin->main; binp->stacksize = builtin->stacksize; binp->priority = builtin->priority; - nx_close(fd); + file_close(&file); return OK; } diff --git a/binfmt/elf.c b/binfmt/elf.c index aeecb3edf53..fd99c3d58ae 100644 --- a/binfmt/elf.c +++ b/binfmt/elf.c @@ -114,7 +114,6 @@ static void elf_dumploadinfo(FAR struct elf_loadinfo_s *loadinfo) binfo(" dtors: %08lx\n", (long)loadinfo->dtors); binfo(" ndtors: %d\n", loadinfo->ndtors); #endif - binfo(" filfd: %d\n", loadinfo->filfd); binfo(" symtabidx: %d\n", loadinfo->symtabidx); binfo(" strtabidx: %d\n", loadinfo->strtabidx); @@ -226,7 +225,7 @@ static int elf_loadbinary(FAR struct binary_s *binp, if (ret != 0) { berr("Failed to initialize for load of ELF program: %d\n", ret); - goto errout; + goto errout_with_init; } /* Load the program binary */ @@ -293,7 +292,6 @@ errout_with_load: elf_unload(&loadinfo); errout_with_init: elf_uninit(&loadinfo); -errout: return ret; } diff --git a/binfmt/libelf/libelf_addrenv.c b/binfmt/libelf/libelf_addrenv.c index ff2be063365..1fd5be96e35 100644 --- a/binfmt/libelf/libelf_addrenv.c +++ b/binfmt/libelf/libelf_addrenv.c @@ -117,13 +117,30 @@ int elf_addrenv_alloc(FAR struct elf_loadinfo_s *loadinfo, size_t textsize, #else /* Allocate memory to hold the ELF image */ +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) + loadinfo->textalloc = (uintptr_t) + up_textheap_memalign(loadinfo->textalign, + textsize); +#else loadinfo->textalloc = (uintptr_t)kumm_malloc(textsize + datasize); +#endif + if (!loadinfo->textalloc) { return -ENOMEM; } +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) + loadinfo->dataalloc = (uintptr_t)kumm_malloc(datasize); + + if (0 != datasize && !loadinfo->dataalloc) + { + return -ENOMEM; + } +#else loadinfo->dataalloc = loadinfo->textalloc + textsize; +#endif + return OK; #endif } @@ -159,12 +176,26 @@ void elf_addrenv_free(FAR struct elf_loadinfo_s *loadinfo) berr("ERROR: up_addrenv_destroy failed: %d\n", ret); } #else + +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) + if (loadinfo->textalloc != 0) + { + up_textheap_free((FAR void *)loadinfo->textalloc); + } + + if (loadinfo->dataalloc != 0) + { + kumm_free((FAR void *)loadinfo->dataalloc); + } +#else /* If there is an allocation for the ELF image, free it */ if (loadinfo->textalloc != 0) { kumm_free((FAR void *)loadinfo->textalloc); } +#endif + #endif /* Clear out all indications of the allocated address environment */ diff --git a/binfmt/libelf/libelf_init.c b/binfmt/libelf/libelf_init.c index 7f4ae3c13a6..d2c1ba4ea5d 100644 --- a/binfmt/libelf/libelf_init.c +++ b/binfmt/libelf/libelf_init.c @@ -146,10 +146,9 @@ int elf_init(FAR const char *filename, FAR struct elf_loadinfo_s *loadinfo) /* Open the binary file for reading (only) */ - loadinfo->filfd = nx_open(filename, O_RDONLY); - if (loadinfo->filfd < 0) + ret = file_open(&loadinfo->file, filename, O_RDONLY); + if (ret < 0) { - ret = loadinfo->filfd; berr("Failed to open ELF binary %s: %d\n", filename, ret); return ret; } @@ -161,7 +160,6 @@ int elf_init(FAR const char *filename, FAR struct elf_loadinfo_s *loadinfo) if (ret < 0) { berr("Failed to read ELF header: %d\n", ret); - nx_close(loadinfo->filfd); return ret; } @@ -181,7 +179,6 @@ int elf_init(FAR const char *filename, FAR struct elf_loadinfo_s *loadinfo) */ berr("Bad ELF header: %d\n", ret); - nx_close(loadinfo->filfd); return ret; } diff --git a/binfmt/libelf/libelf_load.c b/binfmt/libelf/libelf_load.c index 0885b0e5b77..e2c8d398288 100644 --- a/binfmt/libelf/libelf_load.c +++ b/binfmt/libelf/libelf_load.c @@ -239,7 +239,7 @@ int elf_load(FAR struct elf_loadinfo_s *loadinfo) int ret; binfo("loadinfo: %p\n", loadinfo); - DEBUGASSERT(loadinfo && loadinfo->filfd >= 0); + DEBUGASSERT(loadinfo && loadinfo->file.f_inode); /* Load section headers into memory */ diff --git a/binfmt/libelf/libelf_read.c b/binfmt/libelf/libelf_read.c index f3b346944d5..b05cda281e6 100644 --- a/binfmt/libelf/libelf_read.c +++ b/binfmt/libelf/libelf_read.c @@ -108,7 +108,7 @@ int elf_read(FAR struct elf_loadinfo_s *loadinfo, FAR uint8_t *buffer, { /* Seek to the next read position */ - rpos = nx_seek(loadinfo->filfd, offset, SEEK_SET); + rpos = file_seek(&loadinfo->file, offset, SEEK_SET); if (rpos != offset) { berr("Failed to seek to position %lu: %d\n", @@ -118,7 +118,7 @@ int elf_read(FAR struct elf_loadinfo_s *loadinfo, FAR uint8_t *buffer, /* Read the file data at offset into the user buffer */ - nbytes = nx_read(loadinfo->filfd, buffer, readsize); + nbytes = file_read(&loadinfo->file, buffer, readsize); if (nbytes < 0) { /* EINTR just means that we received a signal */ diff --git a/binfmt/libelf/libelf_uninit.c b/binfmt/libelf/libelf_uninit.c index 16552d37d50..54ebee6a344 100644 --- a/binfmt/libelf/libelf_uninit.c +++ b/binfmt/libelf/libelf_uninit.c @@ -70,9 +70,9 @@ int elf_uninit(struct elf_loadinfo_s *loadinfo) /* Close the ELF file */ - if (loadinfo->filfd >= 0) + if (loadinfo->file.f_inode) { - nx_close(loadinfo->filfd); + file_close(&loadinfo->file); } return OK; diff --git a/binfmt/libnxflat/libnxflat_addrenv.c b/binfmt/libnxflat/libnxflat_addrenv.c index d217372f075..97409e1e45b 100644 --- a/binfmt/libnxflat/libnxflat_addrenv.c +++ b/binfmt/libnxflat/libnxflat_addrenv.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/binfmt/libnxflat/libnxflat_init.c b/binfmt/libnxflat/libnxflat_init.c index 0f077ec75e7..c7aba4f3d25 100644 --- a/binfmt/libnxflat/libnxflat_init.c +++ b/binfmt/libnxflat/libnxflat_init.c @@ -94,10 +94,9 @@ int nxflat_init(const char *filename, struct nxflat_loadinfo_s *loadinfo) /* Open the binary file */ - loadinfo->filfd = nx_open(filename, O_RDONLY); - if (loadinfo->filfd < 0) + ret = file_open(&loadinfo->file, filename, O_RDONLY); + if (ret < 0) { - ret = loadinfo->filfd; berr("ERROR: Failed to open NXFLAT binary %s: %d\n", filename, ret); return ret; } @@ -109,7 +108,7 @@ int nxflat_init(const char *filename, struct nxflat_loadinfo_s *loadinfo) if (ret < 0) { berr("ERROR: Failed to read NXFLAT header: %d\n", ret); - nx_close(loadinfo->filfd); + file_close(&loadinfo->file); return ret; } @@ -128,7 +127,7 @@ int nxflat_init(const char *filename, struct nxflat_loadinfo_s *loadinfo) */ berr("ERROR: Bad NXFLAT header\n"); - nx_close(loadinfo->filfd); + file_close(&loadinfo->file); return -ENOEXEC; } diff --git a/binfmt/libnxflat/libnxflat_load.c b/binfmt/libnxflat/libnxflat_load.c index 65c4061e8d9..ffbc24c47cc 100644 --- a/binfmt/libnxflat/libnxflat_load.c +++ b/binfmt/libnxflat/libnxflat_load.c @@ -132,13 +132,12 @@ int nxflat_load(struct nxflat_loadinfo_s *loadinfo) * memory resides as long as it is fully initialized and ready to execute. */ - loadinfo->ispace = (uint32_t)mmap(NULL, loadinfo->isize, PROT_READ, - MAP_SHARED | MAP_FILE, loadinfo->filfd, - 0); - if (loadinfo->ispace == (uint32_t)MAP_FAILED) + ret = file_mmap(&loadinfo->file, NULL, loadinfo->isize, PROT_READ, + MAP_SHARED | MAP_FILE, 0, (FAR void **)&loadinfo->ispace); + if (ret < 0) { - berr("Failed to map NXFLAT ISpace: %d\n", errno); - return -errno; + berr("Failed to map NXFLAT ISpace: %d\n", ret); + return ret; } binfo("Mapped ISpace (%" PRId32 " bytes) at %08x\n", diff --git a/binfmt/libnxflat/libnxflat_read.c b/binfmt/libnxflat/libnxflat_read.c index e90ce4a414c..084e713ec0c 100644 --- a/binfmt/libnxflat/libnxflat_read.c +++ b/binfmt/libnxflat/libnxflat_read.c @@ -113,7 +113,7 @@ int nxflat_read(struct nxflat_loadinfo_s *loadinfo, char *buffer, bytesleft = readsize; do { - rpos = nx_seek(loadinfo->filfd, offset, SEEK_SET); + rpos = file_seek(&loadinfo->file, offset, SEEK_SET); if (rpos != offset) { berr("Failed to seek to position %d: %d\n", offset, (int)rpos); @@ -122,7 +122,7 @@ int nxflat_read(struct nxflat_loadinfo_s *loadinfo, char *buffer, /* Read the file data at offset into the user buffer */ - nbytes = nx_read(loadinfo->filfd, bufptr, bytesleft); + nbytes = file_read(&loadinfo->file, bufptr, bytesleft); if (nbytes < 0) { if (nbytes != -EINTR) diff --git a/binfmt/libnxflat/libnxflat_uninit.c b/binfmt/libnxflat/libnxflat_uninit.c index 5ea6b172811..3c2eb63c692 100644 --- a/binfmt/libnxflat/libnxflat_uninit.c +++ b/binfmt/libnxflat/libnxflat_uninit.c @@ -61,9 +61,9 @@ int nxflat_uninit(struct nxflat_loadinfo_s *loadinfo) { - if (loadinfo->filfd >= 0) + if (loadinfo->file.f_inode) { - nx_close(loadinfo->filfd); + file_close(&loadinfo->file); } return OK; diff --git a/binfmt/libnxflat/libnxflat_unload.c b/binfmt/libnxflat/libnxflat_unload.c index e8da56f0752..cae6e3b2174 100644 --- a/binfmt/libnxflat/libnxflat_unload.c +++ b/binfmt/libnxflat/libnxflat_unload.c @@ -72,7 +72,7 @@ int nxflat_unload(FAR struct nxflat_loadinfo_s *loadinfo) if (loadinfo->ispace) { - munmap((FAR void *)loadinfo->ispace, loadinfo->isize); + file_munmap((FAR void *)loadinfo->ispace, loadinfo->isize); loadinfo->ispace = 0; } diff --git a/binfmt/nxflat.c b/binfmt/nxflat.c index 3be1d4a8ca1..476a04a1797 100644 --- a/binfmt/nxflat.c +++ b/binfmt/nxflat.c @@ -123,9 +123,6 @@ static void nxflat_dumploadinfo(FAR struct nxflat_loadinfo_s *loadinfo) binfo(" RELOCS:\n"); binfo(" relocstart: %08lx\n", loadinfo->relocstart); binfo(" reloccount: %d\n", loadinfo->reloccount); - - binfo(" HANDLES:\n"); - binfo(" filfd: %d\n", loadinfo->filfd); } #else # define nxflat_dumploadinfo(i) diff --git a/boards/Kconfig b/boards/Kconfig index 643ccaae74c..1f4129e959a 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -92,6 +92,14 @@ config ARCH_BOARD_C5471EVM NuttX runs on the ARM core and is built with a GNU arm-nuttx-elf toolchain*. This port is complete and verified. +config ARCH_BOARD_CIRCUIT_EXPRESS + bool "Adafruit Circuit Express" + depends on ARCH_CHIP_SAMD21G18A + select ARCH_HAVE_LEDS + ---help--- + This options selects the Adafruit Circuit Express board featuring the Atmel + ATSAMD21 MCU. + config ARCH_BOARD_CLICKER2_STM32 bool "Mikroe Clicker2 STM32" depends on ARCH_CHIP_STM32F407VG @@ -185,6 +193,14 @@ config ARCH_BOARD_EKKLM3S9B96 TI/Stellaris EKK-LM3S9B96 board. This board is based on the an EKK-LM3S9B96 which is a Cortex-M3. +config ARCH_BOARD_EMW3162 + bool "EMW3162 Wi-Fi board" + depends on ARCH_CHIP_STM32F205RG + select ARCH_HAVE_LEDS + ---help--- + EMW3162 board (https://www.waveshare.com/wiki/EMW3162). This board + features the STM32F205RGY6 MCU and BCM43362KUBG Wi-Fi chip. + config ARCH_BOARD_QUICKFEATHER bool "EOS S3 QuickFeather" depends on ARCH_CHIP_EOSS3 @@ -242,6 +258,21 @@ config ARCH_BOARD_ESP32C3_DEVKIT The ESP32-C3-DevKitM-1 version contains the ESP32-C3-MINI-1 module and the ESP32-C3-DevKitC-02 version the ESP32-C3-WROOM-02. +config ARCH_BOARD_ESP32S2_SAOLA_1 + bool "Espressif ESP32-S2-Saola-1 V1.2" + depends on ARCH_CHIP_ESP32S2WROVER + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS if ESP32S2_GPIO_IRQ + ---help--- + This is the ESP32-S2-Saola-1 board + +config ARCH_BOARD_ET_STM32_STAMP + bool "Futurlec: ET-STM32 Stamp" + depends on ARCH_CHIP_STM32F103RE + ---help--- + The ET-STM32 Stamp features the STM32F103RET6 (Cortex M3) microcontroller. + For board details, see: https://www.futurlec.com/ET-STM32_Stamp.shtml config ARCH_BOARD_EZ80F910200KITG bool "ZiLOG ez80f910200kitg development kit" @@ -619,6 +650,14 @@ config ARCH_BOARD_SMARTL_C906 This is the board configuration for the port of NuttX to the THEAD smartl-c906 board. This board features the RISC-V C906. +config ARCH_BOARD_ICICLE_MPFS + bool "Polarfire Icicle evaluation board for MPFS" + depends on ARCH_CHIP_MPFS + select ARCH_HAVE_LEDS if !MPFS_WITH_QEMU + ---help--- + This is the board configuration for the port of NuttX to the + MicroChip icicle-mpfs board. This board features the RISC-V MPFS. + config ARCH_BOARD_MAX32660_EVSYS bool "Maxim Integrated MAX32660-EVSYS" depends on ARCH_CHIP_MAX32660 @@ -1363,6 +1402,16 @@ config ARCH_BOARD_RX65N_GRROSE This is a port of the renesas RX65N on the Renesas RX65N board. STATUS: Work has just began on this port. +config ARCH_BOARD_RV32M1_VEGA + bool "RV32M1 VEGA board" + depends on ARCH_CHIP_RV32M1 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This is the board configuration for the port of NuttX to the + RV32M1 VEGA board. This board features the RV32M1 RISC-V Core(s). + config ARCH_BOARD_S32K118EVB bool "NXP S32K118EVB" depends on ARCH_CHIP_S32K118 @@ -1831,10 +1880,18 @@ config ARCH_BOARD_B_G431B_ESC1 depends on ARCH_CHIP_STM32G431C select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS ---help--- ST Micro B-G431B-ESC1 Discovery Kit, based on the STM32G431CB MCU, a Cortex-M4 with FPU, 170 MHz, 32 KB SRAM, 128 KB code. +config ARCH_BOARD_NUCLEO_G431KB + bool "STM32G431KB Nucleo G431KB" + depends on ARCH_CHIP_STM32G431K + select ARCH_HAVE_LEDS + ---help--- + STMicro Nucleo-G431KB board based on the STMicro STM32G431KB MCU. + config ARCH_BOARD_NUCLEO_G431RB bool "STM32G431RB Nucleo G431RB" depends on ARCH_CHIP_STM32G431R @@ -2261,6 +2318,7 @@ config ARCH_BOARD default "bambino-200e" if ARCH_BOARD_BAMBINO_200E default "bl602evb" if ARCH_BOARD_BL602EVB default "c5471evm" if ARCH_BOARD_C5471EVM + default "circuit-express" if ARCH_BOARD_CIRCUIT_EXPRESS default "clicker2-stm32" if ARCH_BOARD_CLICKER2_STM32 default "cloudctrl" if ARCH_BOARD_CLOUDCTRL default "demo9s12ne64" if ARCH_BOARD_DEMOS92S12NEC64 @@ -2271,11 +2329,14 @@ config ARCH_BOARD default "efm32-g8xx-stk" if ARCH_BOARD_EFM32G8XXSTK default "efm32gg-stk3700" if ARCH_BOARD_EFM32GG_STK3700 default "ekk-lm3s9b96" if ARCH_BOARD_EKKLM3S9B96 + default "emw3162" if ARCH_BOARD_EMW3162 default "quickfeather" if ARCH_BOARD_QUICKFEATHER default "esp32-devkitc" if ARCH_BOARD_ESP32_DEVKITC default "esp32-ethernet-kit" if ARCH_BOARD_ESP32_ETHERNETKIT default "esp32-wrover-kit" if ARCH_BOARD_ESP32_WROVERKIT default "esp32c3-devkit" if ARCH_BOARD_ESP32C3_DEVKIT + default "esp32s2-saola-1" if ARCH_BOARD_ESP32S2_SAOLA_1 + default "et-stm32-stamp" if ARCH_BOARD_ET_STM32_STAMP default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32 @@ -2313,6 +2374,7 @@ config ARCH_BOARD default "lx_cpu" if ARCH_BOARD_LX_CPU default "maix-bit" if ARCH_BOARD_MAIX_BIT default "smartl-c906" if ARCH_BOARD_SMARTL_C906 + default "icicle" if ARCH_BOARD_ICICLE_MPFS default "maple" if ARCH_BOARD_MAPLE default "makerlisp" if ARCH_BOARD_MAKERLISP default "max32660-evsys" if ARCH_BOARD_MAX32660_EVSYS @@ -2390,6 +2452,7 @@ config ARCH_BOARD default "s32k144evb" if ARCH_BOARD_S32K144EVB default "rddrone-uavcan144" if ARCH_BOARD_RDDRONE_UAVCAN144 default "rddrone-uavcan146" if ARCH_BOARD_RDDRONE_UAVCAN146 + default "rv32m1-vega" if ARCH_BOARD_RV32M1_VEGA default "s32k146evb" if ARCH_BOARD_S32K146EVB default "s32k148evb" if ARCH_BOARD_S32K148EVB default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD @@ -2434,6 +2497,7 @@ config ARCH_BOARD default "stm32f746-ws" if ARCH_BOARD_STM32F746_WS default "b-g474e-dpow1" if ARCH_BOARD_B_G474E_DPOW1 default "b-g431b-esc1" if ARCH_BOARD_B_G431B_ESC1 + default "nucleo-g431kb" if ARCH_BOARD_NUCLEO_G431KB default "nucleo-g431rb" if ARCH_BOARD_NUCLEO_G431RB default "b-l072z-lrwan1" if ARCH_BOARD_B_L072Z_LRWAN1 default "b-l475e-iot01a" if ARCH_BOARD_B_L475E_IOT01A @@ -2713,6 +2777,9 @@ endif if ARCH_BOARD_ARDUINO_M0 source "boards/arm/samd2l2/arduino-m0/Kconfig" endif +if ARCH_BOARD_CIRCUIT_EXPRESS +source "boards/arm/samd2l2/circuit-express/Kconfig" +endif if ARCH_BOARD_FLIPNCLICK_SAM3X source "boards/arm/sam34/flipnclick-sam3x/Kconfig" endif @@ -2776,6 +2843,9 @@ endif if ARCH_BOARD_B_G431B_ESC1 source "boards/arm/stm32/b-g431b-esc1/Kconfig" endif +if ARCH_BOARD_NUCLEO_G431KB +source "boards/arm/stm32/nucleo-g431kb/Kconfig" +endif if ARCH_BOARD_NUCLEO_G431RB source "boards/arm/stm32/nucleo-g431rb/Kconfig" endif @@ -2863,6 +2933,9 @@ endif if ARCH_BOARD_CLOUDCTRL source "boards/arm/stm32/cloudctrl/Kconfig" endif +if ARCH_BOARD_EMW3162 +source "boards/arm/stm32/emw3162/Kconfig" +endif if ARCH_BOARD_FIRE_STM32 source "boards/arm/stm32/fire-stm32v2/Kconfig" endif @@ -2872,6 +2945,9 @@ endif if ARCH_BOARD_MAPLE source "boards/arm/stm32/maple/Kconfig" endif +if ARCH_BOARD_ET_STM32_STAMP +source "boards/arm/stm32/et-stm32-stamp/Kconfig" +endif if ARCH_BOARD_MIKROE_STM32F4 source "boards/arm/stm32/mikroe-stm32f4/Kconfig" endif @@ -3106,9 +3182,18 @@ endif if ARCH_BOARD_SMARTL_C906 source "boards/risc-v/c906/smartl-c906/Kconfig" endif +if ARCH_BOARD_ICICLE_MPFS +source "boards/risc-v/mpfs/icicle/Kconfig" +endif +if ARCH_BOARD_RV32M1_VEGA +source "boards/risc-v/rv32m1/rv32m1-vega/Kconfig" +endif if ARCH_BOARD_ESP32C3_DEVKIT source "boards/risc-v/esp32c3/esp32c3-devkit/Kconfig" endif +if ARCH_BOARD_ESP32S2_SAOLA_1 +source "boards/xtensa/esp32s2/esp32s2-saola-1/Kconfig" +endif if ARCH_BOARD_SIM source "boards/sim/sim/sim/Kconfig" endif @@ -3288,6 +3373,22 @@ config BOARDCTL_UNIQUEID_SIZE Provides the size of the memory buffer that must be provided by the caller of board_uniqueid() in which to receive the board unique ID. +config BOARDCTL_UNIQUEKEY + bool "Return board unique KEY" + default n + ---help--- + Enables support for the BOARDIOC_UNIQUEKEY boardctl() command. + Architecture specific logic must provide the board_uniquekey() + interface. + +config BOARDCTL_UNIQUEKEY_SIZE + int "Size of the board unique KEY (bytes)" + default 16 + depends on BOARDCTL_UNIQUEKEY + ---help--- + Provides the size of the memory buffer that must be provided by the + caller of board_uniquekey() in which to receive the board unique KEY. + config BOARDCTL_MKRD bool "Enable application space creation of RAM disks" default n diff --git a/boards/README.txt b/boards/README.txt index 0f0da393ac3..aa571000f6e 100644 --- a/boards/README.txt +++ b/boards/README.txt @@ -186,6 +186,9 @@ boards/arm/stm32/b-g474e-dpow1 Initial support for booting NuttX to a functional NSH prompt on the STMicro B-G474E-DPOW1 Discovery kit with STM32G474RE MCU. +boards/arm/stm32/nucleo-g431kb + STMicro Nucleo G431KB board based on the STMicro STM32G431KB MCU. + boards/arm/stm32/nucleo-g431rb STMicro Nucleo G431RB board based on the STMicro STM32G431RB MCU. @@ -255,6 +258,11 @@ boards/arm/tiva/ekk-lm3s9b96 TI/Stellaris EKK-LM3S9B96 board. This board is based on the an EKK-LM3S9B96 which is a Cortex-M3. +boards/arm/stm32/emw3162 + A configuration for the EMW3162 Wi-Fi board + (https://www.waveshare.com/wiki/EMW3162). This board features + the STM32F205RGY6 MCU from STMicro. + boards/xtensa/esp32/esp-core The ESP32 is a dual-core system from Espressif with two Harvard architecture Xtensa LX6 CPUs. All embedded memory, external memory and peripherals are diff --git a/boards/arm/a1x/pcduino-a10/configs/nsh/defconfig b/boards/arm/a1x/pcduino-a10/configs/nsh/defconfig index 9f7c2d026f1..3c84b6fe1b2 100644 --- a/boards/arm/a1x/pcduino-a10/configs/nsh/defconfig +++ b/boards/arm/a1x/pcduino-a10/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y diff --git a/boards/arm/a1x/pcduino-a10/scripts/Make.defs b/boards/arm/a1x/pcduino-a10/scripts/Make.defs index 0f9f87375ea..487a6447643 100644 --- a/boards/arm/a1x/pcduino-a10/scripts/Make.defs +++ b/boards/arm/a1x/pcduino-a10/scripts/Make.defs @@ -52,8 +52,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/am335x/beaglebone-black/configs/lcd/defconfig b/boards/arm/am335x/beaglebone-black/configs/lcd/defconfig index 0dce351bf79..34066c11359 100644 --- a/boards/arm/am335x/beaglebone-black/configs/lcd/defconfig +++ b/boards/arm/am335x/beaglebone-black/configs/lcd/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_FAT=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y diff --git a/boards/arm/am335x/beaglebone-black/configs/nsh/defconfig b/boards/arm/am335x/beaglebone-black/configs/nsh/defconfig index 1146a77cfb3..a212138d67c 100644 --- a/boards/arm/am335x/beaglebone-black/configs/nsh/defconfig +++ b/boards/arm/am335x/beaglebone-black/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y diff --git a/boards/arm/am335x/beaglebone-black/scripts/Make.defs b/boards/arm/am335x/beaglebone-black/scripts/Make.defs index ce87731f799..59475a7539d 100644 --- a/boards/arm/am335x/beaglebone-black/scripts/Make.defs +++ b/boards/arm/am335x/beaglebone-black/scripts/Make.defs @@ -70,8 +70,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/c5471/c5471evm/configs/httpd/defconfig b/boards/arm/c5471/c5471evm/configs/httpd/defconfig index c943b48d635..a23e5b621d3 100644 --- a/boards/arm/c5471/c5471evm/configs/httpd/defconfig +++ b/boards/arm/c5471/c5471evm/configs/httpd/defconfig @@ -19,7 +19,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_EXAMPLES_WEBSERVER=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NETUTILS_WEBSERVER=y diff --git a/boards/arm/c5471/c5471evm/configs/nettest/defconfig b/boards/arm/c5471/c5471evm/configs/nettest/defconfig index 59c2f1c2106..7ecb7f35c64 100644 --- a/boards/arm/c5471/c5471evm/configs/nettest/defconfig +++ b/boards/arm/c5471/c5471evm/configs/nettest/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_NETTEST=y CONFIG_EXAMPLES_NETTEST_NOMAC=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NET_ICMP=y diff --git a/boards/arm/c5471/c5471evm/configs/nsh/defconfig b/boards/arm/c5471/c5471evm/configs/nsh/defconfig index c596024b23d..73f83f3fdd1 100644 --- a/boards/arm/c5471/c5471evm/configs/nsh/defconfig +++ b/boards/arm/c5471/c5471evm/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 diff --git a/boards/arm/c5471/c5471evm/scripts/Make.defs b/boards/arm/c5471/c5471evm/scripts/Make.defs index 71b1671bd4b..bbbd85dd142 100644 --- a/boards/arm/c5471/c5471evm/scripts/Make.defs +++ b/boards/arm/c5471/c5471evm/scripts/Make.defs @@ -74,10 +74,10 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld \ - -no-check-sections + -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/cxd56xx/common/src/Make.defs b/boards/arm/cxd56xx/common/src/Make.defs index 0895c224801..239b84432ab 100644 --- a/boards/arm/cxd56xx/common/src/Make.defs +++ b/boards/arm/cxd56xx/common/src/Make.defs @@ -88,7 +88,7 @@ ifeq ($(CONFIG_SENSORS_BMI160_SPI),y) CSRCS += cxd56_bmi160_spi.c endif -ifeq ($(CONFIG_SENSORS_BMP280_I2C),y) +ifeq ($(CONFIG_SENSORS_BMP280),y) CSRCS += cxd56_bmp280_i2c.c endif diff --git a/boards/arm/cxd56xx/common/src/cxd56_altmdm.c b/boards/arm/cxd56xx/common/src/cxd56_altmdm.c index 7753a90e59a..47d129e19d1 100644 --- a/boards/arm/cxd56xx/common/src/cxd56_altmdm.c +++ b/boards/arm/cxd56xx/common/src/cxd56_altmdm.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -74,6 +75,8 @@ # error "Select LTE SPI 4 or 5" #endif +#define WAIT_READY_TO_GPIO_INTERRUPT 300 /* micro seconds */ + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -313,6 +316,12 @@ static bool altmdm_sready(void) static void altmdm_master_request(bool request) { + /* If the GPIO falls within 300us after raising + * (or GPIO raises within 300us after falling), the modem may miss the GPIO + * interrupt. So delay by 300us before changing the GPIO. + */ + + up_udelay(WAIT_READY_TO_GPIO_INTERRUPT); cxd56_gpio_write(ALTMDM_MASTER_REQ, request); } diff --git a/boards/arm/cxd56xx/common/src/cxd56_audio.c b/boards/arm/cxd56xx/common/src/cxd56_audio.c index 692fa160f14..023b8c0cd0e 100644 --- a/boards/arm/cxd56xx/common/src/cxd56_audio.c +++ b/boards/arm/cxd56xx/common/src/cxd56_audio.c @@ -453,6 +453,7 @@ void board_audio_finalize(void) board_audio_i2s_disable(); } +#ifdef CONFIG_AUDIO_CXD56 /**************************************************************************** * Name: board_audio_initialize_driver * @@ -530,3 +531,4 @@ int board_audio_initialize_driver(int minor) return ret; } +#endif /* CONFIG_AUDIO_CXD56 */ diff --git a/boards/arm/cxd56xx/common/src/cxd56_crashdump.c b/boards/arm/cxd56xx/common/src/cxd56_crashdump.c index 8ccf65f9136..0278b09f569 100644 --- a/boards/arm/cxd56xx/common/src/cxd56_crashdump.c +++ b/boards/arm/cxd56xx/common/src/cxd56_crashdump.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -188,7 +189,11 @@ void board_crashdump(uintptr_t currentsp, FAR void *tcb, #if CONFIG_ARCH_INTERRUPTSTACK > 3 /* Get the limits on the interrupt stack memory */ +#ifdef CONFIG_SMP + pdump->info.stacks.interrupt.top = (uint32_t)arm_intstack_top(); +#else pdump->info.stacks.interrupt.top = (uint32_t)&g_intstacktop; +#endif pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); /* If In interrupt Context save the interrupt stack data centered diff --git a/boards/arm/cxd56xx/common/src/cxd56_imageproc.c b/boards/arm/cxd56xx/common/src/cxd56_imageproc.c index ba2ef3f5c32..72a1112982b 100644 --- a/boards/arm/cxd56xx/common/src/cxd56_imageproc.c +++ b/boards/arm/cxd56xx/common/src/cxd56_imageproc.c @@ -37,6 +37,7 @@ #include #include +#include #include #include "chip.h" @@ -346,8 +347,8 @@ static void *set_rop_cmd(void *cmdbuf, rc->fixedcolor = patcolor; rc->srch = srcwidth - 1; rc->srcv = srcheight - 1; - rc->saddr = (uint32_t) (uintptr_t) srcaddr | MSEL; - rc->daddr = (uint32_t) (uintptr_t) destaddr | MSEL; + rc->saddr = CXD56_PHYSADDR(srcaddr) | MSEL; + rc->daddr = CXD56_PHYSADDR(destaddr) | MSEL; rc->spitch = srcpitch - 1; rc->dpitch = destpitch - 1; rc->desth = destwidth - 1; @@ -377,19 +378,19 @@ static void *set_ab_cmd(void *cmdbuf, void *srcaddr, void *destaddr, ac->mode = fixedalpha; ac->srch = srcwidth - 1; ac->srcv = srcheight - 1; - ac->saddr = (uint32_t)(uintptr_t)srcaddr | MSEL; - ac->daddr = (uint32_t)(uintptr_t)destaddr | MSEL; + ac->saddr = CXD56_PHYSADDR(srcaddr) | MSEL; + ac->daddr = CXD56_PHYSADDR(destaddr) | MSEL; ac->spitch = srcpitch - 1; ac->dpitch = destpitch - 1; ac->fixedsrc = (uint32_t)fixedsrc; if (aaddr) { - ac->aaddr = (uint32_t)(uintptr_t)aaddr | MSEL; + ac->aaddr = CXD56_PHYSADDR(aaddr) | MSEL; ac->apitch = apitch - 1; } else { - ac->aaddr = (uint32_t)(uintptr_t)destaddr | MSEL; + ac->aaddr = CXD56_PHYSADDR(destaddr) | MSEL; ac->apitch = destpitch - 1; } @@ -433,10 +434,10 @@ static void imageproc_convert_(int is_yuv2rgb, putreg32(hsize, ROT_SET_SRC_HSIZE); putreg32(vsize, ROT_SET_SRC_VSIZE); - putreg32((uint32_t) (uintptr_t) ibuf, ROT_SET_SRC_ADDRESS); + putreg32(CXD56_PHYSADDR(ibuf), ROT_SET_SRC_ADDRESS); putreg32(hsize, ROT_SET_SRC_PITCH); - putreg32((uint32_t) (uintptr_t) ibuf, ROT_SET_DST_ADDRESS); + putreg32(CXD56_PHYSADDR(ibuf), ROT_SET_DST_ADDRESS); putreg32(hsize, ROT_SET_DST_PITCH); diff --git a/boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.c b/boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.c index 7aa5113ac49..d0fe9c68d00 100644 --- a/boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.c +++ b/boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.c @@ -519,7 +519,7 @@ CXD56_AUDIO_ECODE cxd56_audio_dma_start(cxd56_audio_dma_t handle, return CXD56_AUDIO_ECODE_DMA_BUSY; } - cxd56_audio_bca_reg_set_start_addr(handle, addr); + cxd56_audio_bca_reg_set_start_addr(handle, CXD56_PHYSADDR(addr)); cxd56_audio_bca_reg_set_sample_no(handle, sample); if (s_work_arroud_dmac[handle]) diff --git a/boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.h b/boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.h index 8a7d4683448..e9fcfa9bb23 100644 --- a/boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.h +++ b/boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.h @@ -26,6 +26,7 @@ ****************************************************************************/ #include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/cxd56xx/drivers/sensors/ak09912_scu.c b/boards/arm/cxd56xx/drivers/sensors/ak09912_scu.c index 0ea21771476..8ce669bf7e6 100644 --- a/boards/arm/cxd56xx/drivers/sensors/ak09912_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/ak09912_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/apds9930_scu.c b/boards/arm/cxd56xx/drivers/sensors/apds9930_scu.c index 6f15d9ef4af..128290c78f6 100644 --- a/boards/arm/cxd56xx/drivers/sensors/apds9930_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/apds9930_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/bh1721fvc_scu.c b/boards/arm/cxd56xx/drivers/sensors/bh1721fvc_scu.c index 33e00f28a45..1a916f3e198 100644 --- a/boards/arm/cxd56xx/drivers/sensors/bh1721fvc_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/bh1721fvc_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/bh1745nuc_scu.c b/boards/arm/cxd56xx/drivers/sensors/bh1745nuc_scu.c index ea51d5d6d31..b47ebfd8fd0 100644 --- a/boards/arm/cxd56xx/drivers/sensors/bh1745nuc_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/bh1745nuc_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/bm1383glv_scu.c b/boards/arm/cxd56xx/drivers/sensors/bm1383glv_scu.c index 79b5936f406..b5d5f8cb934 100644 --- a/boards/arm/cxd56xx/drivers/sensors/bm1383glv_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/bm1383glv_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/bm1422gmv_scu.c b/boards/arm/cxd56xx/drivers/sensors/bm1422gmv_scu.c index d692e1d86b5..2d8b0f6f115 100644 --- a/boards/arm/cxd56xx/drivers/sensors/bm1422gmv_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/bm1422gmv_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c b/boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c index 534ad3c3f7f..2ee33643529 100644 --- a/boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/bmp280_scu.c b/boards/arm/cxd56xx/drivers/sensors/bmp280_scu.c index 4cf274b0f80..ceb272bdb13 100644 --- a/boards/arm/cxd56xx/drivers/sensors/bmp280_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/bmp280_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -464,7 +465,7 @@ static int bmp280_initialize(FAR struct bmp280_dev_s *priv) { int ret; - ret = bmp280_set_standby(priv, BMP280_STANDBY_1_MS); + ret = bmp280_set_standby(priv, BMP280_STANDBY_05_MS); if (ret != OK) { diff --git a/boards/arm/cxd56xx/drivers/sensors/kx022_scu.c b/boards/arm/cxd56xx/drivers/sensors/kx022_scu.c index 2d4bf9affd1..39eaa998ee3 100644 --- a/boards/arm/cxd56xx/drivers/sensors/kx022_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/kx022_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/lt1pa01_scu.c b/boards/arm/cxd56xx/drivers/sensors/lt1pa01_scu.c index 67121bb6dfb..7e943061935 100644 --- a/boards/arm/cxd56xx/drivers/sensors/lt1pa01_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/lt1pa01_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/drivers/sensors/rpr0521rs_scu.c b/boards/arm/cxd56xx/drivers/sensors/rpr0521rs_scu.c index 40b53c178b5..a34fe4e8538 100644 --- a/boards/arm/cxd56xx/drivers/sensors/rpr0521rs_scu.c +++ b/boards/arm/cxd56xx/drivers/sensors/rpr0521rs_scu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/cxd56xx/spresense/README.txt b/boards/arm/cxd56xx/spresense/README.txt index 85f4cd51bde..8763112b37e 100644 --- a/boards/arm/cxd56xx/spresense/README.txt +++ b/boards/arm/cxd56xx/spresense/README.txt @@ -19,6 +19,10 @@ as the more advanced NuttX based SDK. Refer to https://developer.sony.com/develop/spresense/ for further information about this board. +NOTICE: + +To run the nuttx, bootloader for Spresense SDK 2.1.0 or later must be installed. + Configuration sub-directories ----------------------------- @@ -36,9 +40,7 @@ Configuration sub-directories smp - This is a configuration to run Spresense in SMP mode. To use this - configuration, bootloader for Spresense SDK 1.5.0 or later must be - installed. + This is a configuration to run Spresense in SMP mode. wifi diff --git a/boards/arm/cxd56xx/spresense/configs/audio/defconfig b/boards/arm/cxd56xx/spresense/configs/audio/defconfig index 9f170db788b..beea53e265f 100644 --- a/boards/arm/cxd56xx/spresense/configs/audio/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/audio/defconfig @@ -43,8 +43,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_SMARTFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD_BYTE_WRITE=y diff --git a/boards/arm/cxd56xx/spresense/configs/audio_sdk/defconfig b/boards/arm/cxd56xx/spresense/configs/audio_sdk/defconfig index f2a0b417fd3..28de200c339 100644 --- a/boards/arm/cxd56xx/spresense/configs/audio_sdk/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/audio_sdk/defconfig @@ -41,8 +41,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_SMARTFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD_BYTE_WRITE=y diff --git a/boards/arm/cxd56xx/spresense/configs/camera/defconfig b/boards/arm/cxd56xx/spresense/configs/camera/defconfig index 4b258699977..9aa56e9723a 100644 --- a/boards/arm/cxd56xx/spresense/configs/camera/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/camera/defconfig @@ -43,7 +43,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_SMARTFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD_BYTE_WRITE=y diff --git a/boards/arm/cxd56xx/spresense/configs/elf/defconfig b/boards/arm/cxd56xx/spresense/configs/elf/defconfig index 964cd582c65..a91441ad7ab 100644 --- a/boards/arm/cxd56xx/spresense/configs/elf/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/elf/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_CHIP="cxd56xx" CONFIG_ARCH_CHIP_CXD56XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=5434 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILTIN=y @@ -24,6 +25,8 @@ CONFIG_CXD56_I2C=y CONFIG_CXD56_SPI4=y CONFIG_CXD56_SPI5=y CONFIG_CXD56_SPI=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y CONFIG_ELF=y CONFIG_EXAMPLES_ELF=y CONFIG_FS_PROCFS=y @@ -32,7 +35,6 @@ CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_PATH_INITIAL="/mnt/romfs" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=1572864 @@ -43,6 +45,7 @@ CONFIG_RTC_DRIVER=y CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y CONFIG_SPI=y +CONFIG_STACK_COLORATION=y CONFIG_START_DAY=4 CONFIG_START_MONTH=2 CONFIG_START_YEAR=2020 diff --git a/boards/arm/cxd56xx/spresense/configs/example_camera/defconfig b/boards/arm/cxd56xx/spresense/configs/example_camera/defconfig index a49ec705711..96ac6328221 100644 --- a/boards/arm/cxd56xx/spresense/configs/example_camera/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/example_camera/defconfig @@ -43,7 +43,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_SMARTFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD_BYTE_WRITE=y diff --git a/boards/arm/cxd56xx/spresense/configs/example_lcd/defconfig b/boards/arm/cxd56xx/spresense/configs/example_lcd/defconfig index d483e506f91..156d45c4b20 100644 --- a/boards/arm/cxd56xx/spresense/configs/example_lcd/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/example_lcd/defconfig @@ -58,7 +58,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_LCD=y CONFIG_LCD_ILI9340=y CONFIG_LCD_ILI9340_IFACE0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/cxd56xx/spresense/configs/lcd/defconfig b/boards/arm/cxd56xx/spresense/configs/lcd/defconfig index 6d3af925eb3..0c5791ffc6b 100644 --- a/boards/arm/cxd56xx/spresense/configs/lcd/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/lcd/defconfig @@ -49,7 +49,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_LCD=y CONFIG_LCD_ILI9340=y CONFIG_LCD_ILI9340_IFACE0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/cxd56xx/spresense/configs/lte/defconfig b/boards/arm/cxd56xx/spresense/configs/lte/defconfig index 5b1f9b74691..e5422b36af2 100644 --- a/boards/arm/cxd56xx/spresense/configs/lte/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/lte/defconfig @@ -40,7 +40,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_SMARTFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MODEM=y diff --git a/boards/arm/cxd56xx/spresense/configs/module/defconfig b/boards/arm/cxd56xx/spresense/configs/module/defconfig index 79d44672300..7273323d9ce 100644 --- a/boards/arm/cxd56xx/spresense/configs/module/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/module/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_CHIP="cxd56xx" CONFIG_ARCH_CHIP_CXD56XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=5434 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILTIN=y @@ -33,7 +34,6 @@ CONFIG_HAVE_CXX=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_MODULE=y CONFIG_PATH_INITIAL="/mnt/romfs" CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/cxd56xx/spresense/configs/mpy/defconfig b/boards/arm/cxd56xx/spresense/configs/mpy/defconfig index 3e8ddc70d8b..ebd22f3aab5 100644 --- a/boards/arm/cxd56xx/spresense/configs/mpy/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/mpy/defconfig @@ -52,7 +52,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_SMARTFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD_BYTE_WRITE=y diff --git a/boards/arm/cxd56xx/spresense/configs/nsh/defconfig b/boards/arm/cxd56xx/spresense/configs/nsh/defconfig index d215a85c90a..e5fc64c37ac 100644 --- a/boards/arm/cxd56xx/spresense/configs/nsh/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y diff --git a/boards/arm/cxd56xx/spresense/configs/nsh_trace/defconfig b/boards/arm/cxd56xx/spresense/configs/nsh_trace/defconfig new file mode 100644 index 00000000000..bd3fee875eb --- /dev/null +++ b/boards/arm/cxd56xx/spresense/configs/nsh_trace/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_CXD56_I2C0_SCUSEQ is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="spresense" +CONFIG_ARCH_BOARD_SPRESENSE=y +CONFIG_ARCH_CHIP="cxd56xx" +CONFIG_ARCH_CHIP_CXD56XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=5434 +CONFIG_BOOT_RUNFROMISRAM=y +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_CXD56_BINARY=y +CONFIG_CXD56_I2C0=y +CONFIG_CXD56_I2C=y +CONFIG_CXD56_SPI4=y +CONFIG_CXD56_SPI5=y +CONFIG_CXD56_SPI=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVER_NOTE=y +CONFIG_DRIVER_NOTECTL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=1572864 +CONFIG_RAM_START=0x0d000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_FILTER=y +CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y +CONFIG_SCHED_INSTRUMENTATION_SYSCALL=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_SYSTEM_TRACE=y +CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="spresense_main" diff --git a/boards/arm/cxd56xx/spresense/configs/posix_spawn/defconfig b/boards/arm/cxd56xx/spresense/configs/posix_spawn/defconfig index 8801b49394b..42aefac60b3 100644 --- a/boards/arm/cxd56xx/spresense/configs/posix_spawn/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/posix_spawn/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_CHIP_CXD56XX=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=5434 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILTIN=y @@ -37,7 +38,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_PATH_INITIAL="/mnt/romfs" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=1572864 diff --git a/boards/arm/cxd56xx/spresense/configs/rndis/defconfig b/boards/arm/cxd56xx/spresense/configs/rndis/defconfig index e7a66de03ab..65913981038 100644 --- a/boards/arm/cxd56xx/spresense/configs/rndis/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/rndis/defconfig @@ -61,7 +61,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_IOB_NBUFFERS=128 CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_SENDFILE_BUFSIZE=1024 CONFIG_MEMCPY_VIK=y @@ -104,8 +103,9 @@ CONFIG_NET_ROUTE=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y -CONFIG_NET_UDP_BINDTODEVICE=y +CONFIG_NFS=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_TELNETD=y @@ -150,11 +150,11 @@ CONFIG_SYSTEM_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_SYSTEM_NXPLAYER=y CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y -CONFIG_TELNET_CHARACTER_MODE=y CONFIG_TESTING_OSTEST=y CONFIG_TESTING_OSTEST_FPUSIZE=64 CONFIG_UART1_SERIAL_CONSOLE=y CONFIG_USBDEV=y CONFIG_USBDEV_DMA=y CONFIG_USBDEV_DUALSPEED=y +CONFIG_USERMAIN_STACKSIZE=3072 CONFIG_USER_ENTRYPOINT="spresense_main" diff --git a/boards/arm/cxd56xx/spresense/configs/rndis_smp/defconfig b/boards/arm/cxd56xx/spresense/configs/rndis_smp/defconfig index 3f783aa721a..ef676f8c4bf 100644 --- a/boards/arm/cxd56xx/spresense/configs/rndis_smp/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/rndis_smp/defconfig @@ -22,6 +22,7 @@ CONFIG_AUDIO=y CONFIG_AUDIO_CXD56=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=5434 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILTIN=y @@ -32,7 +33,6 @@ CONFIG_CXD56_AUDIO_NUM_BUFFERS=64 CONFIG_CXD56_AUDIO_WORKER_STACKSIZE=1024 CONFIG_CXD56_BINARY=y CONFIG_CXD56_SDIO=y -CONFIG_CXD56_TESTSET=y CONFIG_CXD56_USBDEV=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_HARDFAULT_ALERT=y @@ -63,7 +63,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_IOB_NBUFFERS=128 CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_SENDFILE_BUFSIZE=1024 CONFIG_MEMCPY_VIK=y @@ -106,8 +105,9 @@ CONFIG_NET_ROUTE=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y -CONFIG_NET_UDP_BINDTODEVICE=y +CONFIG_NFS=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_TELNETD=y @@ -155,7 +155,6 @@ CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TASKSET=y -CONFIG_TELNET_CHARACTER_MODE=y CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y CONFIG_TESTING_OSTEST_FPUSIZE=64 diff --git a/boards/arm/cxd56xx/spresense/configs/smp/defconfig b/boards/arm/cxd56xx/spresense/configs/smp/defconfig index 4c599b47cab..dac871a16a9 100644 --- a/boards/arm/cxd56xx/spresense/configs/smp/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/smp/defconfig @@ -12,8 +12,10 @@ CONFIG_ARCH_BOARD="spresense" CONFIG_ARCH_BOARD_SPRESENSE=y CONFIG_ARCH_CHIP="cxd56xx" CONFIG_ARCH_CHIP_CXD56XX=y +CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=5434 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILTIN=y @@ -31,7 +33,6 @@ CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y diff --git a/boards/arm/cxd56xx/spresense/configs/usbmsc/defconfig b/boards/arm/cxd56xx/spresense/configs/usbmsc/defconfig index 7bf95b0f56e..8f9acf138ed 100644 --- a/boards/arm/cxd56xx/spresense/configs/usbmsc/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/usbmsc/defconfig @@ -47,7 +47,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_SMARTFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD_BYTE_WRITE=y diff --git a/boards/arm/cxd56xx/spresense/configs/usbnsh/defconfig b/boards/arm/cxd56xx/spresense/configs/usbnsh/defconfig index c801f29e1ec..d95edb8751b 100644 --- a/boards/arm/cxd56xx/spresense/configs/usbnsh/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/usbnsh/defconfig @@ -40,7 +40,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_SMARTFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD_BYTE_WRITE=y diff --git a/boards/arm/cxd56xx/spresense/configs/wifi/defconfig b/boards/arm/cxd56xx/spresense/configs/wifi/defconfig index b452d3486ce..333d9068fd6 100644 --- a/boards/arm/cxd56xx/spresense/configs/wifi/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/wifi/defconfig @@ -75,7 +75,6 @@ CONFIG_LCD=y CONFIG_LCD_ILI9340=y CONFIG_LCD_ILI9340_IFACE0=y CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_SENDFILE_BUFSIZE=1024 CONFIG_MEMCPY_VIK=y @@ -109,6 +108,7 @@ CONFIG_NET_UDP_NO_STACK=y CONFIG_NET_USRSOCK=y CONFIG_NET_USRSOCK_CONNS=16 CONFIG_NET_USRSOCK_UDP=y +CONFIG_NFS=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_ARP=y diff --git a/boards/arm/cxd56xx/spresense/configs/wifi_smp/defconfig b/boards/arm/cxd56xx/spresense/configs/wifi_smp/defconfig index 948693c4e57..5b04caf5497 100644 --- a/boards/arm/cxd56xx/spresense/configs/wifi_smp/defconfig +++ b/boards/arm/cxd56xx/spresense/configs/wifi_smp/defconfig @@ -22,6 +22,7 @@ CONFIG_ARMV7M_USEBASEPRI=y CONFIG_AUDIO=y CONFIG_AUDIO_CXD56=y CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=5434 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILTIN=y @@ -36,7 +37,6 @@ CONFIG_CXD56_DMAC_SPI5_TX=y CONFIG_CXD56_SDIO=y CONFIG_CXD56_SPI5=y CONFIG_CXD56_SPI=y -CONFIG_CXD56_TESTSET=y CONFIG_CXD56_USBDEV=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_HARDFAULT_ALERT=y @@ -78,7 +78,6 @@ CONFIG_LCD=y CONFIG_LCD_ILI9340=y CONFIG_LCD_ILI9340_IFACE0=y CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_SENDFILE_BUFSIZE=1024 CONFIG_MEMCPY_VIK=y @@ -112,6 +111,7 @@ CONFIG_NET_UDP_NO_STACK=y CONFIG_NET_USRSOCK=y CONFIG_NET_USRSOCK_CONNS=16 CONFIG_NET_USRSOCK_UDP=y +CONFIG_NFS=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_ARP=y diff --git a/boards/arm/cxd56xx/spresense/scripts/Make.defs b/boards/arm/cxd56xx/spresense/scripts/Make.defs index 2f5e7ee7fd7..03001a31dae 100644 --- a/boards/arm/cxd56xx/spresense/scripts/Make.defs +++ b/boards/arm/cxd56xx/spresense/scripts/Make.defs @@ -25,7 +25,11 @@ include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs # Setup for the kind of memory that we are executing from -LDSCRIPT = ramconfig.ld +ifeq ($(CONFIG_CXD56_USE_SYSBUS), y) + LDSCRIPT = ramconfig-new.ld +else + LDSCRIPT = ramconfig.ld +endif ifeq ($(CONFIG_CYGWIN_WINTOOL),y) ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" @@ -45,7 +49,7 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y) endif ARCHCFLAGS = -fno-builtin -mabi=aapcs -ffunction-sections -fdata-sections -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti -std=c++98 +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti -std=c++11 ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef ARCHWARNINGSXX = -Wall -Wshadow -Wundef ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 @@ -57,8 +61,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions @@ -84,7 +88,7 @@ else LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld endif -LDFLAGS += --gc-sections +LDFLAGS += -Wl,--gc-sections ifneq ($(CROSSDEV),arm-nuttx-elf-) LDFLAGS += -nostartfiles -nodefaultlibs @@ -98,11 +102,11 @@ endif # Output map file with cross reference table ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - LDFLAGS += -Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" --cref + LDFLAGS += -Wl,-Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" -Wl,--cref else - LDFLAGS += -Map=$(TOPDIR)/nuttx.map --cref + LDFLAGS += -Wl,-Map=$(TOPDIR)/nuttx.map -Wl,--cref endif ifneq ($(CONFIG_ASMP_MEMSIZE),) - LDFLAGS += --defsym=__reserved_ramsize=$(CONFIG_ASMP_MEMSIZE) + LDFLAGS += -Wl,--defsym=__reserved_ramsize=$(CONFIG_ASMP_MEMSIZE) endif diff --git a/boards/arm/cxd56xx/spresense/scripts/ramconfig-new.ld b/boards/arm/cxd56xx/spresense/scripts/ramconfig-new.ld new file mode 100644 index 00000000000..12d08499d44 --- /dev/null +++ b/boards/arm/cxd56xx/spresense/scripts/ramconfig-new.ld @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/cxd56xx/spresense/scripts/ramconfig-new.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + ram (rwx) : ORIGIN = 0x0d000000, LENGTH = 1536K +} + +OUTPUT_ARCH(arm) +ENTRY(__start) /* Treat __start as the anchor for dead code stripping */ +EXTERN(_vectors) /* Force the vectors to be included in the output */ +EXTERN(__stack) /* Force the __stack to be included in the output */ +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _image_modlist_base = .; + KEEP(*(.modulelist)) + _image_modlist_limit = .; + _etext = ABSOLUTE(.); + } > ram + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > ram + + .ARM.extab : { + *(.ARM.extab*) + } > ram + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > ram + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + /* Map .data and .bss sections to system bus */ + + . = ALIGN(16); + . |= 0x20000000; + + .data . : ALIGN(16) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } AT > ram + + .bss . : { /* BSS */ + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } AT > ram + + /* __stack symbol is referred from mkspk tool + * and means the end address of heap region */ + PROVIDE(__stack = ORIGIN(ram) + LENGTH(ram) + 0x20000000); + __stack -= DEFINED(__reserved_ramsize) ? __reserved_ramsize : 0; + + ASSERT(_ebss < __stack, "Error: Out of memory") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/cxd56xx/spresense/src/cxd56_appinit.c b/boards/arm/cxd56xx/spresense/src/cxd56_appinit.c index 1dd02758e58..eb0f656bdff 100644 --- a/boards/arm/cxd56xx/spresense/src/cxd56_appinit.c +++ b/boards/arm/cxd56xx/spresense/src/cxd56_appinit.c @@ -77,3 +77,28 @@ int board_app_initialize(uintptr_t arg) return cxd56_bringup(); #endif } + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize board- + * specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board bring-up here instead of from the + * board_app_initialize(). + */ + + cxd56_bringup(); +} +#endif diff --git a/boards/arm/cxd56xx/spresense/src/cxd56_gpioif.c b/boards/arm/cxd56xx/spresense/src/cxd56_gpioif.c index 236a34dc2a2..39356a4c1c6 100644 --- a/boards/arm/cxd56xx/spresense/src/cxd56_gpioif.c +++ b/boards/arm/cxd56xx/spresense/src/cxd56_gpioif.c @@ -25,6 +25,7 @@ #include #include +#include #include #include @@ -188,7 +189,8 @@ int board_gpio_intconfig(uint32_t pin, int mode, bool filter, xcpt_t isr) gpiocfg |= GPIOINT_NOISE_FILTER_ENABLE; } - ret = cxd56_gpioint_config(pin, gpiocfg, isr, NULL); + ret = cxd56_gpioint_config(pin, gpiocfg, isr, (void *)pin); + return ret; #else return -ENOTSUP; diff --git a/boards/arm/cxd56xx/spresense/src/cxd56_power.c b/boards/arm/cxd56xx/spresense/src/cxd56_power.c index 7a02860059c..5305d8e342a 100644 --- a/boards/arm/cxd56xx/spresense/src/cxd56_power.c +++ b/boards/arm/cxd56xx/spresense/src/cxd56_power.c @@ -127,7 +127,8 @@ int board_pmic_write(uint8_t addr, void *buf, uint32_t size) int board_power_setup(int status) { #ifdef CONFIG_BOARD_USB_DISABLE_IN_DEEP_SLEEPING - uint8_t val; + int ret; + uint8_t val = 0; uint32_t bootcause; /* Enable USB after wakeup from deep sleeping */ @@ -140,8 +141,8 @@ int board_power_setup(int status) case PM_BOOT_DEEP_WKUPS: case PM_BOOT_DEEP_RTC: case PM_BOOT_DEEP_OTHERS: - cxd56_pmic_read(PMIC_REG_CNT_USB2, &val, sizeof(val)); - if (val & PMIC_SET_CHGOFF) + ret = cxd56_pmic_read(PMIC_REG_CNT_USB2, &val, sizeof(val)); + if ((ret == 0) && (val & PMIC_SET_CHGOFF)) { val &= ~PMIC_SET_CHGOFF; cxd56_pmic_write(PMIC_REG_CNT_USB2, &val, sizeof(val)); @@ -205,6 +206,13 @@ int board_power_control(int target, bool en) if (pfunc) { ret = pfunc(PMIC_GET_CH(target), en); + + /* If RTC clock is unstable, delay 1 tick for PMIC GPO setting. */ + + if (!g_rtc_enabled && (PMIC_GET_TYPE(target) == PMIC_TYPE_GPO)) + { + usleep(1); + } } return ret; @@ -236,6 +244,13 @@ int board_power_control_tristate(int target, int value) /* set HiZ to PMIC GPO channel */ ret = cxd56_pmic_set_gpo_hiz(PMIC_GET_CH(target)); + + /* If RTC clock is unstable, delay 1 tick for PMIC setting. */ + + if (!g_rtc_enabled) + { + usleep(1); + } } else { @@ -495,9 +510,12 @@ int board_reset(int status) { /* Restore the original state for bootup after power cycle */ - board_xtal_power_control(true); - board_flash_power_control(true); - up_pm_acquire_freqlock(&g_hv_lock); + if (!up_interrupt_context()) + { + board_xtal_power_control(true); + board_flash_power_control(true); + up_pm_acquire_freqlock(&g_hv_lock); + } /* System reboot */ diff --git a/boards/arm/cxd56xx/spresense/src/cxd56_pwm.c b/boards/arm/cxd56xx/spresense/src/cxd56_pwm.c index d211c62787e..ebcf01a1d13 100644 --- a/boards/arm/cxd56xx/spresense/src/cxd56_pwm.c +++ b/boards/arm/cxd56xx/spresense/src/cxd56_pwm.c @@ -60,13 +60,13 @@ static int pwm_initialize(uint32_t channel) pwm = cxd56_pwminitialize(channel); if (!pwm) { - pwmerr("Failed to get the CXD56 PWM%d lower half\n", channel); + pwmerr("Failed to get the CXD56 PWM%ld lower half\n", channel); return -ENODEV; } /* Register the PWM driver at "/dev/pwmX" */ - snprintf(devname, sizeof(devname), "/dev/pwm%d", channel); + snprintf(devname, sizeof(devname), "/dev/pwm%ld", channel); ret = pwm_register(devname, pwm); if (ret < 0) { diff --git a/boards/arm/dm320/ntosd-dm320/configs/nettest/defconfig b/boards/arm/dm320/ntosd-dm320/configs/nettest/defconfig index c6987c76d5d..a91531445dd 100644 --- a/boards/arm/dm320/ntosd-dm320/configs/nettest/defconfig +++ b/boards/arm/dm320/ntosd-dm320/configs/nettest/defconfig @@ -20,7 +20,6 @@ CONFIG_DM9X_BASE=0xd0000300 CONFIG_DM9X_IRQ=27 CONFIG_EXAMPLES_NETTEST=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/dm320/ntosd-dm320/configs/nsh/defconfig b/boards/arm/dm320/ntosd-dm320/configs/nsh/defconfig index 51957bd73e0..76a7691ff0b 100644 --- a/boards/arm/dm320/ntosd-dm320/configs/nsh/defconfig +++ b/boards/arm/dm320/ntosd-dm320/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_DM9X_IRQ=27 CONFIG_FS_FAT=y CONFIG_FS_ROMFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=64 CONFIG_MMCSD=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/dm320/ntosd-dm320/configs/poll/defconfig b/boards/arm/dm320/ntosd-dm320/configs/poll/defconfig index 354abb87eb3..aee56779a32 100644 --- a/boards/arm/dm320/ntosd-dm320/configs/poll/defconfig +++ b/boards/arm/dm320/ntosd-dm320/configs/poll/defconfig @@ -20,7 +20,6 @@ CONFIG_DM9X_BASE=0xd0000300 CONFIG_DM9X_IRQ=27 CONFIG_EXAMPLES_POLL=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/dm320/ntosd-dm320/configs/udp/defconfig b/boards/arm/dm320/ntosd-dm320/configs/udp/defconfig index 52a8e61000b..7ebc5699aa0 100644 --- a/boards/arm/dm320/ntosd-dm320/configs/udp/defconfig +++ b/boards/arm/dm320/ntosd-dm320/configs/udp/defconfig @@ -21,7 +21,6 @@ CONFIG_DM9X_BASE=0xd0000300 CONFIG_DM9X_IRQ=27 CONFIG_EXAMPLES_UDP=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/dm320/ntosd-dm320/configs/webserver/defconfig b/boards/arm/dm320/ntosd-dm320/configs/webserver/defconfig index 40127e1337b..f7a1fd00a08 100644 --- a/boards/arm/dm320/ntosd-dm320/configs/webserver/defconfig +++ b/boards/arm/dm320/ntosd-dm320/configs/webserver/defconfig @@ -20,7 +20,6 @@ CONFIG_DM9X_BASE=0xd0000300 CONFIG_DM9X_IRQ=27 CONFIG_EXAMPLES_WEBSERVER=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/dm320/ntosd-dm320/scripts/Make.defs b/boards/arm/dm320/ntosd-dm320/scripts/Make.defs index 1dee61197f8..532f80bef29 100644 --- a/boards/arm/dm320/ntosd-dm320/scripts/Make.defs +++ b/boards/arm/dm320/ntosd-dm320/scripts/Make.defs @@ -71,10 +71,10 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld \ - -no-check-sections + -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CONFIG_ARM_TOOLCHAIN_BUILDROOT),y) diff --git a/boards/arm/efm32/efm32-g8xx-stk/configs/nsh/defconfig b/boards/arm/efm32/efm32-g8xx-stk/configs/nsh/defconfig index 00e51a6c3de..58a3e7e7501 100644 --- a/boards/arm/efm32/efm32-g8xx-stk/configs/nsh/defconfig +++ b/boards/arm/efm32/efm32-g8xx-stk/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_EFM32_GPIO_IRQ=y CONFIG_EFM32_LEUART0=y CONFIG_HOST_WINDOWS=y CONFIG_LEUART0_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_FILEIOSIZE=256 CONFIG_NSH_LINELEN=78 CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/efm32/efm32-g8xx-stk/scripts/Make.defs b/boards/arm/efm32/efm32-g8xx-stk/scripts/Make.defs index 7dbbb058900..f4f9a45845f 100644 --- a/boards/arm/efm32/efm32-g8xx-stk/scripts/Make.defs +++ b/boards/arm/efm32/efm32-g8xx-stk/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/efm32/efm32gg-stk3700/configs/nsh/defconfig b/boards/arm/efm32/efm32gg-stk3700/configs/nsh/defconfig index b044d84ed07..c1ff8491909 100644 --- a/boards/arm/efm32/efm32gg-stk3700/configs/nsh/defconfig +++ b/boards/arm/efm32/efm32gg-stk3700/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_EFM32_LEUART0=y CONFIG_HOST_WINDOWS=y CONFIG_LEUART0_BAUD=9600 CONFIG_LEUART0_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_FILEIOSIZE=256 CONFIG_NSH_LINELEN=78 CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/efm32/efm32gg-stk3700/scripts/Make.defs b/boards/arm/efm32/efm32gg-stk3700/scripts/Make.defs index 4854442f999..ba1e40083e7 100644 --- a/boards/arm/efm32/efm32gg-stk3700/scripts/Make.defs +++ b/boards/arm/efm32/efm32gg-stk3700/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/efm32/olimex-efm32g880f128-stk/configs/nsh/defconfig b/boards/arm/efm32/olimex-efm32g880f128-stk/configs/nsh/defconfig index 3cf91e17302..64599e4c1a9 100644 --- a/boards/arm/efm32/olimex-efm32g880f128-stk/configs/nsh/defconfig +++ b/boards/arm/efm32/olimex-efm32g880f128-stk/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_EFM32_GPIO_IRQ=y CONFIG_EFM32_LEUART1=y CONFIG_HOST_WINDOWS=y CONFIG_LEUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_FILEIOSIZE=256 CONFIG_NSH_LINELEN=78 CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/efm32/olimex-efm32g880f128-stk/scripts/Make.defs b/boards/arm/efm32/olimex-efm32g880f128-stk/scripts/Make.defs index e9ceee8f938..2df3d322d2d 100644 --- a/boards/arm/efm32/olimex-efm32g880f128-stk/scripts/Make.defs +++ b/boards/arm/efm32/olimex-efm32g880f128-stk/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/eoss3/quickfeather/scripts/Make.defs b/boards/arm/eoss3/quickfeather/scripts/Make.defs index 0f9a6105d0b..68a8c9f155f 100644 --- a/boards/arm/eoss3/quickfeather/scripts/Make.defs +++ b/boards/arm/eoss3/quickfeather/scripts/Make.defs @@ -63,6 +63,10 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS = -nostartfiles -nodefaultlibs +endif + +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/imx6/sabre-6quad/configs/elf/defconfig b/boards/arm/imx6/sabre-6quad/configs/elf/defconfig new file mode 100644 index 00000000000..8295c635d83 --- /dev/null +++ b/boards/arm/imx6/sabre-6quad/configs/elf/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="sabre-6quad" +CONFIG_ARCH_BOARD_SABRE_6QUAD=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="imx6" +CONFIG_ARCH_CHIP_IMX6=y +CONFIG_ARCH_CHIP_IMX6_6QUAD=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_LOWVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7A_ASSOCIATIVITY_16WAY=y +CONFIG_ARMV7A_L2CC_PL310=y +CONFIG_ARMV7A_WAYSIZE_64KB=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=99369 +CONFIG_BOOT_RUNFROMSDRAM=y +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_ELF=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_IMX6_UART1=y +CONFIG_IMX_DDR_SIZE=1073741824 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIB_BOARDCTL=y +CONFIG_PL310_LOCKDOWN_BY_LINE=y +CONFIG_PL310_LOCKDOWN_BY_MASTER=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=1073741824 +CONFIG_RAM_START=0x10000000 +CONFIG_RAM_VSTART=0x10000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2021 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="elf_main" diff --git a/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig index d186fca3782..c0da06ce253 100644 --- a/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig @@ -21,11 +21,13 @@ CONFIG_BOARD_LOOPSPERMSEC=99369 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y CONFIG_CLOCK_MONOTONIC=y +CONFIG_CODECS_HASH_MD5=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y +CONFIG_ELF=y CONFIG_ETH0_PHY_KSZ8081=y -CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO=m CONFIG_EXAMPLES_TCPBLASTER=y CONFIG_EXAMPLES_TCPBLASTER_GROUPSIZE=500 CONFIG_EXAMPLES_TCPBLASTER_SERVER=y @@ -40,7 +42,8 @@ CONFIG_IMX6_UART1=y CONFIG_IMX_DDR_SIZE=1073741824 CONFIG_IMX_ENET_NTXBUFFERS=1 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIB_ENVPATH=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 @@ -48,6 +51,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y CONFIG_NETINIT_DRIPADDR=0x0a000202 CONFIG_NETINIT_IPADDR=0x0a00020f CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_CODECS=y CONFIG_NETUTILS_IPERF=y CONFIG_NETUTILS_IPERFTEST_DEVNAME="eth0" CONFIG_NETUTILS_TELNETD=y @@ -62,10 +66,12 @@ CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NFS=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/mnt/nfs/bin" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=1073741824 CONFIG_RAM_START=0x10000000 @@ -84,8 +90,12 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_SYMTAB=y +CONFIG_SYSTEM_NSH_SYMTAB_ARRAYNAME="g_symtab" +CONFIG_SYSTEM_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_SYSTEM_PING=y CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USERMAIN_STACKSIZE=3072 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig b/boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig index b7471906cab..0d33db93fa1 100644 --- a/boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig @@ -21,11 +21,13 @@ CONFIG_BOARD_LOOPSPERMSEC=99369 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y CONFIG_CLOCK_MONOTONIC=y +CONFIG_CODECS_HASH_MD5=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y +CONFIG_ELF=y CONFIG_ETH0_PHY_KSZ8081=y -CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO=m CONFIG_EXAMPLES_TCPBLASTER=y CONFIG_EXAMPLES_TCPBLASTER_GROUPSIZE=500 CONFIG_EXAMPLES_TCPBLASTER_SERVER=y @@ -40,6 +42,8 @@ CONFIG_IMX6_UART1=y CONFIG_IMX_DDR_SIZE=1073741824 CONFIG_IMX_ENET_NTXBUFFERS=1 CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIB_ENVPATH=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 @@ -47,6 +51,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y CONFIG_NETINIT_DRIPADDR=0x0a000202 CONFIG_NETINIT_IPADDR=0x0a00020f CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_CODECS=y CONFIG_NETUTILS_IPERF=y CONFIG_NETUTILS_IPERFTEST_DEVNAME="eth0" CONFIG_NETUTILS_TELNETD=y @@ -61,10 +66,12 @@ CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NFS=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/mnt/nfs/bin" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=1073741824 CONFIG_RAM_START=0x10000000 @@ -83,6 +90,9 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_SYMTAB=y +CONFIG_SYSTEM_NSH_SYMTAB_ARRAYNAME="g_symtab" +CONFIG_SYSTEM_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TASKSET=y @@ -90,4 +100,5 @@ CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y CONFIG_TESTING_SMP=y CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USERMAIN_STACKSIZE=3072 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig index 1dd056567e1..9edeba2f5f9 100644 --- a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig @@ -35,7 +35,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IMX6_UART1=y CONFIG_IMX_DDR_SIZE=1073741824 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/imx6/sabre-6quad/configs/posix_spawn/defconfig b/boards/arm/imx6/sabre-6quad/configs/posix_spawn/defconfig new file mode 100644 index 00000000000..37e07688554 --- /dev/null +++ b/boards/arm/imx6/sabre-6quad/configs/posix_spawn/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="sabre-6quad" +CONFIG_ARCH_BOARD_SABRE_6QUAD=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="imx6" +CONFIG_ARCH_CHIP_IMX6=y +CONFIG_ARCH_CHIP_IMX6_6QUAD=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_LOWVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7A_ASSOCIATIVITY_16WAY=y +CONFIG_ARMV7A_L2CC_PL310=y +CONFIG_ARMV7A_WAYSIZE_64KB=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=99369 +CONFIG_BOOT_RUNFROMSDRAM=y +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_POSIXSPAWN=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IMX6_UART1=y +CONFIG_IMX_DDR_SIZE=1073741824 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIB_BOARDCTL=y +CONFIG_LIB_ENVPATH=y +CONFIG_PATH_INITIAL="/mnt/romfs" +CONFIG_PL310_LOCKDOWN_BY_LINE=y +CONFIG_PL310_LOCKDOWN_BY_MASTER=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=1073741824 +CONFIG_RAM_START=0x10000000 +CONFIG_RAM_VSTART=0x10000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2021 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="posix_spawn_main" diff --git a/boards/arm/imx6/sabre-6quad/scripts/Make.defs b/boards/arm/imx6/sabre-6quad/scripts/Make.defs index 09bd2edce37..8617cf732fe 100644 --- a/boards/arm/imx6/sabre-6quad/scripts/Make.defs +++ b/boards/arm/imx6/sabre-6quad/scripts/Make.defs @@ -54,8 +54,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 @@ -71,7 +71,7 @@ else LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld endif -LDFLAGS += --gc-sections +LDFLAGS += -Wl,--gc-sections ifneq ($(CROSSDEV),arm-nuttx-elf-) LDFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/arm/imxrt/imxrt1020-evk/README.txt b/boards/arm/imxrt/imxrt1020-evk/README.txt deleted file mode 100644 index df3277180c7..00000000000 --- a/boards/arm/imxrt/imxrt1020-evk/README.txt +++ /dev/null @@ -1,167 +0,0 @@ -README -====== - -README for NuttX port to the IMXRT1020-EVK, an IMXRT1020 based -board with various capabilities, featuring the NXP -IMXRT1021DAG5A CPU. - - o Processor - - - MIMXRT1021DAG5A processor - - o Memory - - - 256 Mb SDRAM memory - - 64 Mb QSPI Flash - - TF socket for SD card - - o Display and Audio - - - Audio CODEC - - 4-pole audio headphone jack - - External speaker connection - - Microphone - - o Connectivity - - - Micro USB host and OTG connectors - - Ethernet (10/100T) connector - - CAN transceivers - - Arduino® interface - -Serial Console -============== - - The EVK default console is on LPUART1, which is multiplexed onto - the debug port (either OpenSDA or SEGGER JLink). - - It runs at 115200,n,8,1. - -LEDs and Buttons -================ - - There is one user accessible LED status indicator located on the 1020-EVK, - USERLED. The function of the LEDs include: - - D3: Power (Green) & Overpower (Red) - D5: User LED (Green) GPIO_AD_B0_05 - D15: RST LED (Red) - - This LED is not used by the board port unless CONFIG_ARCH_LEDS is - defined. In that case, the usage by the board port is defined in - include/board.h and src/imxrt_autoleds.c. The LED is used to encode - OS-related events as documented in board.h - - --------------------------------------------------- - SYMBOL Meaning USERLED - --------------------------------------------------- - - LED_STARTED NuttX has been started OFF - LED_HEAPALLOCATE Heap has been allocated OFF - LED_IRQSENABLED Interrupts enabled OFF - LED_STACKCREATED Idle stack created ON - LED_INIRQ In an interrupt N/C - LED_SIGNAL In a signal handler N/C - LED_ASSERTION An assertion failed N/C - LED_PANIC The system has crashed FLASH - LED_IDLE Not used - - In addition the LED is illuminated during an interrupt. - - This IMXRT board has three external buttons - - 1. SW2 (IRQ88, ONOFF) Not on a GPIO, No muxing - 2. SW3 (IRQ88, POR) Not on a GPIO, No muxing - 3. SW4 (IRQ88, USER) Wakeup, GPIO5-0 - -Configurations -============== - - Information Common to All Configurations - ---------------------------------------- - - Each i.MX RT 1020 configuration is maintained in a sub-directory and - can be selected as follow: - - tools/configure.sh [OPTIONS] imxrt1020-evk: - - Where typical options are -l to configure to build on Linux or -c to - configure for Cygwin under Linux. 'tools/configure.sh -h' will show - you all of the options. - - Before building, make sure the PATH environment variable include the - correct path to the directory than holds your toolchain binaries. - - And then build NuttX by simply typing the following. At the conclusion of - the make, the nuttx binary will reside in an ELF file called, simply, nuttx. - - make - - The that is provided above as an argument to the tools/configure.sh - must be is one of the following. - - NOTES: - - 1. These configurations use the mconf-based configuration tool. To - change any of these configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. Unless stated otherwise, all configurations generate console - output on UART1 (i.e. the multiplexed OpenSDA/JLink serial port). - - 3. All of these configurations are set up to build under Windows using the - "GNU Tools for ARM Embedded Processors" that is maintained by ARM - (unless stated otherwise in the description of the configuration). - - https://developer.arm.com/open-source/gnu-toolchain/gnu-rm - - That toolchain selection can easily be reconfigured using - 'make menuconfig'. Here are the relevant current settings: - - Build Setup: - CONFIG_HOST_WINDOWS=y : Window environment - CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows - - System Type -> Toolchain: - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain - -Configuration sub-directories ------------------------------ - - netnsh: - - This configuration is similar to the nsh configuration except that is - has networking enabled, both IPv4 and IPv6. This NSH configuration is - focused on network-related testing. - - NOTES: - - 1. LED support is disabled because there is a conflict between the LED - GPIO and PHY pin usage. - - 2. Telnet is enabled. But since both IPv4 and IPv6 are enabled, it - will default to IPv6. That means that to connect a Telnet session - from a PC, you will need to use the IPv6 address which by defaault - is: - - telnet fc00::2 - - Or, disable IPv4 support so that only IPv4 addressing is used. - - 3. The network monitor is not enabled in this configuration. As a - result, the Ethernet cable must be connected when the board is - powered up. Otherwise, it will stall for a long period of time - before the NSH prompt appears and you will not be able to used - the board. - - nsh: - - Configures the NuttShell (nsh) located at examples/nsh. This NSH - configuration is focused on low level, command-line driver testing. - Built-in applications are supported, but none are enabled. This - configuration does not support a network. diff --git a/boards/arm/imxrt/imxrt1020-evk/configs/netnsh/defconfig b/boards/arm/imxrt/imxrt1020-evk/configs/netnsh/defconfig index 8fc309ff599..7b26255ee5d 100644 --- a/boards/arm/imxrt/imxrt1020-evk/configs/netnsh/defconfig +++ b/boards/arm/imxrt/imxrt1020-evk/configs/netnsh/defconfig @@ -35,7 +35,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_RXBUFSIZE=1024 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=1024 -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETUTILS_TELNETD=y CONFIG_NET_ICMP=y diff --git a/boards/arm/imxrt/imxrt1020-evk/configs/nsh/defconfig b/boards/arm/imxrt/imxrt1020-evk/configs/nsh/defconfig index c4bc1b529ee..ca47ea3e7e0 100644 --- a/boards/arm/imxrt/imxrt1020-evk/configs/nsh/defconfig +++ b/boards/arm/imxrt/imxrt1020-evk/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_RXBUFSIZE=1024 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=1024 -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/imxrt/imxrt1020-evk/configs/usdhc/defconfig b/boards/arm/imxrt/imxrt1020-evk/configs/usdhc/defconfig index e3e4b8dc8e8..1eab4e9171f 100644 --- a/boards/arm/imxrt/imxrt1020-evk/configs/usdhc/defconfig +++ b/boards/arm/imxrt/imxrt1020-evk/configs/usdhc/defconfig @@ -44,7 +44,6 @@ CONFIG_LIBC_STRERROR=y CONFIG_LPUART1_RXBUFSIZE=1024 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=1024 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_IOB=y diff --git a/boards/arm/imxrt/imxrt1020-evk/scripts/Make.defs b/boards/arm/imxrt/imxrt1020-evk/scripts/Make.defs index 52546a2133e..19ea5694365 100644 --- a/boards/arm/imxrt/imxrt1020-evk/scripts/Make.defs +++ b/boards/arm/imxrt/imxrt1020-evk/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/imxrt1050-evk/README.txt b/boards/arm/imxrt/imxrt1050-evk/README.txt deleted file mode 100644 index 0d4fbec8891..00000000000 --- a/boards/arm/imxrt/imxrt1050-evk/README.txt +++ /dev/null @@ -1,297 +0,0 @@ -README -====== - - This README file provides information about the port of NuttX to the NXP - i.MXRT evaluation kit, MIMXRT1050-EVKB. This board features the - MIMXRT1052DVL6A MCU. Some of the features of this board include: - - o Processor - - - MIMXRT1052DVL6A processor - - o Memory - - - 256 Mb SDRAM memory - - 512 Mb Hyper Flash - - Footprint for QSPI Flash - - TF socket for SD card - - o Display and Audio - - - Parallel LCD connector - - Camera connector - - Audio CODEC - - 4-pole audio headphone jack - - External speaker connection - - Microphone - - SPDIF connector - - o Connectivity - - - Micro USB host and OTG connectors - - Ethernet (10/100T) connector - - CAN transceivers - - Arduino® interface - -Contents -======== - - o Serial Console - o LEDs and buttons - o Configurations - - Configuration sub-directories - -Serial Console -============== - - Virtual console port provided by OpenSDA: - - UART1_TXD GPIO_AD_B0_12 LPUART1_TX - UART1_RXD GPIO_AD_B0_13 LPUART1_RX - - Arduino RS-232 Shield: - - J22 D0 UART_RX/D0 GPIO_AD_B1_07 LPUART3_RX - J22 D1 UART_TX/D1 GPIO_AD_B1_06 LPUART3_TX - -LEDs and buttons -================ - - LEDs - ---- - - There are four LED status indicators located on the EVK Board. The - functions of these LEDs include: - - - Main Power Supply(D3) - Green: DC 5V main supply is normal. - Red: J2 input voltage is over 5.6V. - Off: The board is not powered. - - Reset RED LED(D15) - - OpenSDA LED(D16) - - USER LED(D18) - - Only a single LED, D18, is under software control. It connects to - GPIO_AD_B0_09 which is shared with JTAG_TDI and ENET_RST - - This LED is not used by the board port unless CONFIG_ARCH_LEDS is - defined. In that case, the usage by the board port is defined in - include/board.h and src/imxrt_autoleds.c. The LED is used to encode - OS-related events as follows: - - ------------------- ----------------------- ------ - SYMBOL Meaning LED - ------------------- ----------------------- ------ - LED_STARTED NuttX has been started OFF - LED_HEAPALLOCATE Heap has been allocated OFF - LED_IRQSENABLED Interrupts enabled OFF - LED_STACKCREATED Idle stack created ON - LED_INIRQ In an interrupt N/C - LED_SIGNAL In a signal handler N/C - LED_ASSERTION An assertion failed N/C - LED_PANIC The system has crashed FLASH - - Thus if the LED is statically on, NuttX has successfully booted and is, - apparently, running normally. If the LED is flashing at approximately - 2Hz, then a fatal error has been detected and the system has halted. - - Buttons - ------- - - There are four user interface switches on the MIMXRT1050 EVK Board: - - - SW1: Power Switch (slide switch) - - SW2: ON/OFF Button - - SW3: Reset button - - SW8: User button - - Only the user button is available to the software. It is sensed on the - WAKEUP pin which will be pulled low when the button is pressed. - -Configurations -============== - - Information Common to All Configurations - ---------------------------------------- - Each i.MX RT 10050 configuration is maintained in a sub-directory and - can be selected as follow: - - tools/configure.sh [OPTIONS] imxrt1050-evk: - - Where typical options are -l to configure to build on Linux or -c to - configure for Cygwin under Linux. 'tools/configure.sh -h' will show - you all of the options. - - Before building, make sure the PATH environment variable include the - correct path to the directory than holds your toolchain binaries. - - And then build NuttX by simply typing the following. At the conclusion of - the make, the nuttx binary will reside in an ELF file called, simply, nuttx. - - make - - The that is provided above as an argument to the tools/configure.sh - must be is one of the following. - - NOTES: - - 1. These configurations use the mconf-based configuration tool. To - change any of these configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. Unless stated otherwise, all configurations generate console - output on UART3 (i.e., for the Arduino serial shield). - - 3. All of these configurations are set up to build under Windows using the - "GNU Tools for ARM Embedded Processors" that is maintained by ARM - (unless stated otherwise in the description of the configuration). - - https://developer.arm.com/open-source/gnu-toolchain/gnu-rm - - That toolchain selection can easily be reconfigured using - 'make menuconfig'. Here are the relevant current settings: - - Build Setup: - CONFIG_HOST_WINDOWS=y : Window environment - CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows - - System Type -> Toolchain: - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain - -Configuration sub-directories ------------------------------ - - knsh: - - This is identical to the nsh configuration below except that NuttX - is built as a protected mode, monolithic module and the user applications - are built separately. It is recommends to use a special make command; - not just 'make' but make with the following two arguments: - - make pass1 pass2 - - In the normal case (just 'make'), make will attempt to build both user- - and kernel-mode blobs more or less interleaved. This actual works! - However, for me it is very confusing so I prefer the above make command: - Make the user-space binaries first (pass1), then make the kernel-space - binaries (pass2) - - NOTES: - - 1. At the end of the build, there will be several files in the top-level - NuttX build directory: - - PASS1: - nuttx_user.elf - The pass1 user-space ELF file - nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig) - User.map - Symbols in the user-space ELF file - - PASS2: - nuttx - The pass2 kernel-space ELF file - nuttx.hex - The pass2 Intel HEX file (selected in defconfig) - System.map - Symbols in the kernel-space ELF file - - The J-Link programmer will except files in .hex, .mot, .srec, and .bin - formats. - - 2. Combining .hex files. If you plan to use the .hex files with your - debugger or FLASH utility, then you may need to combine the two hex - files into a single .hex file. Here is how you can do that. - - a. The 'tail' of the nuttx.hex file should look something like this - (with my comments added beginning with #): - - $ tail nuttx.hex - #xx xxxx 00 data records - ... - :10 C93C 00 000000000040184000C2010000000000 90 - :10 C94C 00 2400080000801B4000C01B4000001C40 5D - :10 C95C 00 00401C4000000C4050BF0060FF000100 74 - #xx xxxx 05 Start Linear Address Record - :04 0000 05 6000 02C1 D4 - #xx xxxx 01 End Of File record - :00 0000 01 FF - - Use an editor such as vi to remove the 05 and 01 records. - - b. The 'head' of the nuttx_user.hex file should look something like - this (again with my comments added beginning with #): - - $ head nuttx_user.hex - #xx xxxx 04 Extended Linear Address Record - :02 0000 04 6020 7A - #xx xxxx 00 data records - :10 0000 00 8905206030002060F2622060FC622060 80 - :10 0010 00 0000242008002420080024205C012420 63 - :10 0020 00 140024203D0020603100206071052060 14 - ... - - Nothing needs to be done here. The nuttx_user.hex file should - be fine. - - c. Combine the edited nuttx.hex and un-edited nuttx_user.hex - file to produce a single combined hex file: - - $ cat nuttx.hex nuttx_user.hex >combined.hex - - Then use the combined.hex file with the to write the FLASH image. - If you do this a lot, you will probably want to invest a little time - to develop a tool to automate these steps. - - STATUS: This configuration was added on 8 June 2018 primarily to assure - that all of the components are in place to support the PROTECTED mode - build. This configuration, however, has not been verified as of this - writing. - - netnsh: - - This configuration is similar to the nsh configuration except that is - has networking enabled, both IPv4 and IPv6. This NSH configuration is - focused on network-related testing. - - NOTES: - - 1. LED support is disabled because there is a conflict between the LED - GPIO and PHY pin usage. - - 2. Telnet is enabled. But since both IPv4 and IPv6 are enabled, it - will default to IPv6. That means that to connect a Telnet session - from a PC, you will need to use the IPv6 address which by defaault - is: - - telnet fc00::2 - - Or, disable IPv4 support so that only IPv4 addressing is used. - - 3. The network monitor is not enabled in this configuration. As a - result, the Ethernet cable must be connected when the board is - powered up. Otherwise, it will stall for a long period of time - before the NSH prompt appears and you will not be able to used - the board. - - The following configuration options should be added to your - configuration in order to use the network monitor: - - CONFIG_IMXRT_ENET_PHYINIT=y - CONFIG_IMXRT_GPIO1_0_15_IRQ=y - CONFIG_IMXRT_GPIO_IRQ=y - CONFIG_NETDEV_IOCTL=y - CONFIG_NETDEV_PHY_IOCTL=y - CONFIG_NSH_NETINIT_MONITOR=y - CONFIG_NSH_NETINIT_RETRYMSEC=2000 - CONFIG_NSH_NETINIT_SIGNO=18 - CONFIG_NSH_NETINIT_THREAD=y - CONFIG_NSH_NETINIT_THREAD_PRIORITY=80 - CONFIG_NSH_NETINIT_THREAD_STACKSIZE=1568 - - nsh: - - Configures the NuttShell (nsh) located at examples/nsh. This NSH - configuration is focused on low level, command-line driver testing. - Built-in applications are supported, but none are enabled. This - configuration does not support a network. diff --git a/boards/arm/imxrt/imxrt1050-evk/configs/knsh/Make.defs b/boards/arm/imxrt/imxrt1050-evk/configs/knsh/Make.defs index 765d5f0dbfc..21e8f75e0d7 100644 --- a/boards/arm/imxrt/imxrt1050-evk/configs/knsh/Make.defs +++ b/boards/arm/imxrt/imxrt1050-evk/configs/knsh/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/imxrt1050-evk/configs/knsh/defconfig b/boards/arm/imxrt/imxrt1050-evk/configs/knsh/defconfig index b13be818720..dcaa91cd3ab 100644 --- a/boards/arm/imxrt/imxrt1050-evk/configs/knsh/defconfig +++ b/boards/arm/imxrt/imxrt1050-evk/configs/knsh/defconfig @@ -26,7 +26,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_DISABLE_MKRD=y CONFIG_NSH_FILEIOSIZE=512 @@ -40,5 +39,5 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=8 CONFIG_START_MONTH=6 CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/imxrt/imxrt1050-evk/configs/libcxxtest/Make.defs b/boards/arm/imxrt/imxrt1050-evk/configs/libcxxtest/Make.defs index d45992426a0..27b25fecbaf 100644 --- a/boards/arm/imxrt/imxrt1050-evk/configs/libcxxtest/Make.defs +++ b/boards/arm/imxrt/imxrt1050-evk/configs/libcxxtest/Make.defs @@ -81,8 +81,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/imxrt1050-evk/configs/libcxxtest/defconfig b/boards/arm/imxrt/imxrt1050-evk/configs/libcxxtest/defconfig index 890b0492922..91e8c4e4d52 100644 --- a/boards/arm/imxrt/imxrt1050-evk/configs/libcxxtest/defconfig +++ b/boards/arm/imxrt/imxrt1050-evk/configs/libcxxtest/defconfig @@ -26,7 +26,6 @@ CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LOCALTIME=y CONFIG_LIBM=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/imxrt/imxrt1050-evk/configs/netnsh/defconfig b/boards/arm/imxrt/imxrt1050-evk/configs/netnsh/defconfig index 31db8b1c549..b3263fa9941 100644 --- a/boards/arm/imxrt/imxrt1050-evk/configs/netnsh/defconfig +++ b/boards/arm/imxrt/imxrt1050-evk/configs/netnsh/defconfig @@ -27,7 +27,6 @@ CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HOSTNAME="i.MXRT1050 EVK" CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEV_STATISTICS=y CONFIG_NETINIT_NOMAC=y diff --git a/boards/arm/imxrt/imxrt1050-evk/configs/nsh/defconfig b/boards/arm/imxrt/imxrt1050-evk/configs/nsh/defconfig index 82a272320ea..c316f3d17ae 100644 --- a/boards/arm/imxrt/imxrt1050-evk/configs/nsh/defconfig +++ b/boards/arm/imxrt/imxrt1050-evk/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/imxrt/imxrt1050-evk/kernel/Makefile b/boards/arm/imxrt/imxrt1050-evk/kernel/Makefile index 8c41c6e49b7..01b45b59e76 100644 --- a/boards/arm/imxrt/imxrt1050-evk/kernel/Makefile +++ b/boards/arm/imxrt/imxrt1050-evk/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/imxrt/imxrt1050-evk/kernel/imxrt_userspace.c b/boards/arm/imxrt/imxrt1050-evk/kernel/imxrt_userspace.c index 2654b3b93a4..0f0ee111308 100644 --- a/boards/arm/imxrt/imxrt1050-evk/kernel/imxrt_userspace.c +++ b/boards/arm/imxrt/imxrt1050-evk/kernel/imxrt_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/imxrt/imxrt1050-evk/scripts/Make.defs b/boards/arm/imxrt/imxrt1050-evk/scripts/Make.defs index 4c6fa003d22..aa4c48a9891 100644 --- a/boards/arm/imxrt/imxrt1050-evk/scripts/Make.defs +++ b/boards/arm/imxrt/imxrt1050-evk/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/imxrt1060-evk/README.txt b/boards/arm/imxrt/imxrt1060-evk/README.txt deleted file mode 100644 index 2cf84946602..00000000000 --- a/boards/arm/imxrt/imxrt1060-evk/README.txt +++ /dev/null @@ -1,363 +0,0 @@ -README -====== - - This README file provides information about the port of NuttX to the NXP - i.MXRT evaluation kit, MIMXRT1060-EVK. This board features the - MIMXRT1062DVL6A MCU. Some of the features of this board include: - - o Processor - - - MIMXRT1062DVL6A processor - - o Memory - - - 1 Mb OCRAM memory - - 256 Mb SDRAM memory - - 512 Mb Hyper Flash - Populated but 0 ohm DNP - - 64 Mb QSPI Flash - - TF socket for SD card - - o Display and Audio - - - Parallel LCD connector - - Camera connector - - Audio CODEC - - 4-pole audio headphone jack - - External speaker connection - - Microphone - - SPDIF connector - - o Connectivity - - - Micro USB host and OTG connectors - - Ethernet (10/100T) connector - - CAN transceivers - - Arduino® interface - - o Sensors - - - FXOS8700CQ 6-Axis Ecompass (3-Axis Mag, 3-Axis Accel) - -Contents -======== - - o Serial Console - o LEDs and buttons - o J-Link External Debug Probe - o Configurations - - Configuration sub-directories - -Serial Console -============== - - Virtual console port provided by OpenSDA: - - UART1_TXD GPIO_AD_B0_12 LPUART1_TX - UART1_RXD GPIO_AD_B0_13 LPUART1_RX - - Arduino RS-232 Shield: - - J22 D0 UART_RX/D0 GPIO_AD_B1_07 LPUART3_RX - J22 D1 UART_TX/D1 GPIO_AD_B1_06 LPUART3_TX - -LEDs and buttons -================ - - LEDs - ---- - - There are four LED status indicators located on the EVK Board. The - functions of these LEDs include: - - - Main Power Supply(D3) - Green: DC 5V main supply is normal. - Red: J2 input voltage is over 5.6V. - Off: The board is not powered. - - Reset RED LED(D21) - - OpenSDA LED(D20) - - USER LED(D18) - - Only a single LED, D18, is under software control. It connects to - GPIO_AD_B0_09 which is shared with JTAG_TDI and ENET_RST - - This LED is not used by the board port unless CONFIG_ARCH_LEDS is - defined. In that case, the usage by the board port is defined in - include/board.h and src/imxrt_autoleds.c. The LED is used to encode - OS-related events as follows: - - ------------------- ----------------------- ------ - SYMBOL Meaning LED - ------------------- ----------------------- ------ - LED_STARTED NuttX has been started OFF - LED_HEAPALLOCATE Heap has been allocated OFF - LED_IRQSENABLED Interrupts enabled OFF - LED_STACKCREATED Idle stack created ON - LED_INIRQ In an interrupt N/C - LED_SIGNAL In a signal handler N/C - LED_ASSERTION An assertion failed N/C - LED_PANIC The system has crashed FLASH - - Thus if the LED is statically on, NuttX has successfully booted and is, - apparently, running normally. If the LED is flashing at approximately - 2Hz, then a fatal error has been detected and the system has halted. - - Buttons - ------- - - There are four user interface switches on the MIMXRT1050 EVK Board: - - - SW1: Power Switch (slide switch fir power from J2) - - SW2: ON/OFF Button - - SW3: Power-on Reset button state forces to reset the system power except - SNVS domain - - SW9: Reset button - - SW8: User button GPIO5-00 - - Only the user button is available to the software. It is sensed on the - WAKEUP pin which will be pulled low when the button is pressed. - - -J-Link External Debug Probe -=========================== - - Install the J-Link Debug Host Tools and make sure they are in your search path. - - Attach a J-Link 20-pin connector to J21. Check that jumpers J47 and J48 are - off (they are on by default when boards ship from the factory) to ensure SWD - signals are disconnected from the OpenSDA microcontroller. - -Configurations -============== - - Information Common to All Configurations - ---------------------------------------- - Each i.MX RT 1060 configuration is maintained in a sub-directory and - can be selected as follow: - - tools/configure.sh [OPTIONS] imxrt1060-evk: - - Where typical options are -l to configure to build on Linux or -c to - configure for Cygwin under Linux. 'tools/configure.sh -h' will show - you all of the options. - - Before building, make sure the PATH environment variable include the - correct path to the directory than holds your toolchain binaries. - - And then build NuttX by simply typing the following. At the conclusion of - the make, the nuttx binary will reside in an ELF file called, simply, nuttx. - - make - - The that is provided above as an argument to the tools/configure.sh - must be is one of the following. - - NOTES: - - 1. These configurations use the mconf-based configuration tool. To - change any of these configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. Unless stated otherwise, all configurations generate console - output on UART3 (i.e., for the Arduino serial shield). - - 3. All of these configurations are set up to build under Windows using the - "GNU Tools for ARM Embedded Processors" that is maintained by ARM - (unless stated otherwise in the description of the configuration). - - https://developer.arm.com/open-source/gnu-toolchain/gnu-rm - - That toolchain selection can easily be reconfigured using - 'make menuconfig'. Here are the relevant current settings: - - Build Setup: - CONFIG_HOST_WINDOWS=y : Window environment - CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows - - System Type -> Toolchain: - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain - -Configuration sub-directories ------------------------------ - - can: - - This is an nsh configuration (see below) with added support of CAN driver. - FlexCAN3 is chosen as default, the change can be made at System type peripheral - selection. Please note that only FlexCAN3 and FlexCAN2 is available on this board. - - Bitrate and sample point can be also changed at System type peripheral selection, - basic values are 1 MHz for bitrate and 0.80 for sample point. The FlexCAN driver - for imxrt runs at 80 MHz clock frequency. - - The configuration also includes CAN utilities as candump and cansend. - - canfd: - - This is an nsh configuration (see below) with added support of CAN_FD driver. - FlexCAN3 is chosen as default, please note that only FlexCAN3 is capable of - providing CAN_FD support. - - Bitrate and sample point can be also changed at System type peripheral selection, - basic values are 1 MHz for bitrate and 0.80 for sample point for arbitration phase - and 4 MHz (bitrate) and 0.90 (sample point) for data phase. The FlexCAN driver - for imxrt runs at 80 MHz clock frequency. - - The configuration also includes CAN utilities as candump and cansend. - - knsh: - - This is identical to the nsh configuration below except that NuttX - is built as a protected mode, monolithic module and the user applications - are built separately. It is recommends to use a special make command; - not just 'make' but make with the following two arguments: - - make pass1 pass2 - - In the normal case (just 'make'), make will attempt to build both user- - and kernel-mode blobs more or less interleaved. This actual works! - However, for me it is very confusing so I prefer the above make command: - Make the user-space binaries first (pass1), then make the kernel-space - binaries (pass2) - - NOTES: - - 1. At the end of the build, there will be several files in the top-level - NuttX build directory: - - PASS1: - nuttx_user.elf - The pass1 user-space ELF file - nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig) - User.map - Symbols in the user-space ELF file - - PASS2: - nuttx - The pass2 kernel-space ELF file - nuttx.hex - The pass2 Intel HEX file (selected in defconfig) - System.map - Symbols in the kernel-space ELF file - - The J-Link programmer will except files in .hex, .mot, .srec, and .bin - formats. - - 2. Combining .hex files. If you plan to use the .hex files with your - debugger or FLASH utility, then you may need to combine the two hex - files into a single .hex file. Here is how you can do that. - - a. The 'tail' of the nuttx.hex file should look something like this - (with my comments added beginning with #): - - $ tail nuttx.hex - #xx xxxx 00 data records - ... - :10 C93C 00 000000000040184000C2010000000000 90 - :10 C94C 00 2400080000801B4000C01B4000001C40 5D - :10 C95C 00 00401C4000000C4050BF0060FF000100 74 - #xx xxxx 05 Start Linear Address Record - :04 0000 05 6000 02C1 D4 - #xx xxxx 01 End Of File record - :00 0000 01 FF - - Use an editor such as vi to remove the 05 and 01 records. - - b. The 'head' of the nuttx_user.hex file should look something like - this (again with my comments added beginning with #): - - $ head nuttx_user.hex - #xx xxxx 04 Extended Linear Address Record - :02 0000 04 6020 7A - #xx xxxx 00 data records - :10 0000 00 8905206030002060F2622060FC622060 80 - :10 0010 00 0000242008002420080024205C012420 63 - :10 0020 00 140024203D0020603100206071052060 14 - ... - - Nothing needs to be done here. The nuttx_user.hex file should - be fine. - - c. Combine the edited nuttx.hex and un-edited nuttx_user.hex - file to produce a single combined hex file: - - $ cat nuttx.hex nuttx_user.hex >combined.hex - - Then use the combined.hex file with the to write the FLASH image. - If you do this a lot, you will probably want to invest a little time - to develop a tool to automate these steps. - - STATUS: This configuration was added on 8 June 2018 primarily to assure - that all of the components are in place to support the PROTECTED mode - build. This configuration, however, has not been verified as of this - writing. - - netnsh: - - This configuration is similar to the nsh configuration except that is - has networking enabled, both IPv4 and IPv6. This NSH configuration is - focused on network-related testing. - - NOTES: - - 1. LED support is disabled because there is a conflict between the LED - GPIO and PHY pin usage. - - 2. Telnet is enabled. But since both IPv4 and IPv6 are enabled, it - will default to IPv6. That means that to connect a Telnet session - from a PC, you will need to use the IPv6 address which by defaault - is: - - telnet fc00::2 - - Or, disable IPv4 support so that only IPv4 addressing is used. - - 3. The network monitor is not enabled in this configuration. As a - result, the Ethernet cable must be connected when the board is - powered up. Otherwise, it will stall for a long period of time - before the NSH prompt appears and you will not be able to used - the board. - - The following configuration options should be added to your - configuration in order to use the network monitor: - - CONFIG_IMXRT_ENET_PHYINIT=y - CONFIG_IMXRT_GPIO1_0_15_IRQ=y - CONFIG_IMXRT_GPIO_IRQ=y - CONFIG_NETDEV_IOCTL=y - CONFIG_NETDEV_PHY_IOCTL=y - CONFIG_NSH_NETINIT_MONITOR=y - CONFIG_NSH_NETINIT_RETRYMSEC=2000 - CONFIG_NSH_NETINIT_SIGNO=18 - CONFIG_NSH_NETINIT_THREAD=y - CONFIG_NSH_NETINIT_THREAD_PRIORITY=80 - CONFIG_NSH_NETINIT_THREAD_STACKSIZE=1568 - - nsh: - - Configures the NuttShell (nsh) located at examples/nsh. This NSH - configuration is focused on low level, command-line driver testing. - Built-in applications are supported, but none are enabled. This - configuration does not support a network. - - lvgl: - - Configures the Littlev graphic library (lvgl) demo located under - examples/lvgldemo. This configuration needs the optional LCD model - RK043FN02H-CT from NXP. The LCD panel comes with the integrated - capacitive touchscreen sensor FT5336GQQ connected to the LPI2C1 bus, - address 0x38. NuttX support such touchscreen device via the driver - ft5x06 (drivers/input/ft5x06.c). At the moment only the polling - method is available, the board features an interrupt line connected - to the touchscreen sensor IC. - - IMXRT1062 MCU provides the integrated LCD driver. - - The LCD panel features: - - size 4.3" - - resolution 480×272 RGB - - backlight driver - - dimensions [mm]: 105.5 (W) x 67.2(H) x 4.35(D) Max. - - To run the lvgl demo please type "lvgldemo" at nsh prompt: - - nsh> lvgldemo diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/can/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/can/defconfig index e260ab93d5a..979dab99f09 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/can/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/can/defconfig @@ -52,7 +52,6 @@ CONFIG_IMXRT_FLEXCAN3=y CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_IFINDEX=y diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/canfd/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/canfd/defconfig index 418a49c525c..f9c42445055 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/canfd/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/canfd/defconfig @@ -53,7 +53,6 @@ CONFIG_IMXRT_FLEXCAN3=y CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_IFINDEX=y diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/knsh/Make.defs b/boards/arm/imxrt/imxrt1060-evk/configs/knsh/Make.defs index c1a94e746fc..90a487e5d4f 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/knsh/Make.defs +++ b/boards/arm/imxrt/imxrt1060-evk/configs/knsh/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/knsh/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/knsh/defconfig index 2fe1cdadbb9..b83b40f9b47 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/knsh/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/knsh/defconfig @@ -26,7 +26,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_DISABLE_MKRD=y CONFIG_NSH_FILEIOSIZE=512 @@ -40,5 +39,5 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=8 CONFIG_START_MONTH=6 CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/libcxxtest/Make.defs b/boards/arm/imxrt/imxrt1060-evk/configs/libcxxtest/Make.defs index c4c21108a8e..10954e43451 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/libcxxtest/Make.defs +++ b/boards/arm/imxrt/imxrt1060-evk/configs/libcxxtest/Make.defs @@ -81,8 +81,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/libcxxtest/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/libcxxtest/defconfig index e5853672845..8dd80423c89 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/libcxxtest/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/libcxxtest/defconfig @@ -26,7 +26,6 @@ CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LOCALTIME=y CONFIG_LIBM=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/lvgl/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/lvgl/defconfig index 9a3d2b3ff7a..ace1258dc47 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/lvgl/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/lvgl/defconfig @@ -44,7 +44,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LV_HOR_RES=480 CONFIG_LV_VER_RES=272 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/netnsh/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/netnsh/defconfig index badf30b5055..a6860f54119 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/netnsh/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/netnsh/defconfig @@ -28,7 +28,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=128 CONFIG_LIB_HOSTNAME="i.MXRT1060 EVK" CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_STATISTICS=y @@ -46,7 +45,6 @@ CONFIG_NET_ICMPv6=y CONFIG_NET_ICMPv6_NEIGHBOR=y CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/nsh/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/nsh/defconfig index 78ca4c5be39..a9f61192338 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/nsh/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/nshocram/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/nshocram/defconfig index 8636ce1c4aa..c216a36d929 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/nshocram/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/nshocram/defconfig @@ -27,7 +27,6 @@ CONFIG_IMXRT_DTCM_HEAP=y CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/imxrt/imxrt1060-evk/kernel/Makefile b/boards/arm/imxrt/imxrt1060-evk/kernel/Makefile index f1f49268a48..7f514050145 100644 --- a/boards/arm/imxrt/imxrt1060-evk/kernel/Makefile +++ b/boards/arm/imxrt/imxrt1060-evk/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/imxrt/imxrt1060-evk/kernel/imxrt_userspace.c b/boards/arm/imxrt/imxrt1060-evk/kernel/imxrt_userspace.c index 3a706f3b4a7..e2557c7b358 100644 --- a/boards/arm/imxrt/imxrt1060-evk/kernel/imxrt_userspace.c +++ b/boards/arm/imxrt/imxrt1060-evk/kernel/imxrt_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/imxrt/imxrt1060-evk/scripts/Make.defs b/boards/arm/imxrt/imxrt1060-evk/scripts/Make.defs index 19198c662ec..dde6d3b8a6e 100644 --- a/boards/arm/imxrt/imxrt1060-evk/scripts/Make.defs +++ b/boards/arm/imxrt/imxrt1060-evk/scripts/Make.defs @@ -29,9 +29,9 @@ else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y) endif ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" + ARCHSCRIPT = -Wl,-T"${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" else - ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + ARCHSCRIPT = -Wl,-T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions @@ -73,9 +73,9 @@ endif ifneq ($(CROSSDEV),arm-nuttx-elf-) LDFLAGS += -nostartfiles -nodefaultlibs ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - LDFLAGS += -Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" + LDFLAGS += -Wl,-Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" else - LDFLAGS += -Map=$(TOPDIR)/nuttx.map + LDFLAGS += -Wl,-Map=$(TOPDIR)/nuttx.map endif endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) diff --git a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_ft5x06.c b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_ft5x06.c index 85f337e83e5..3b086d8652c 100644 --- a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_ft5x06.c +++ b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_ft5x06.c @@ -44,6 +44,7 @@ #include #include +#include #include #include diff --git a/boards/arm/imxrt/imxrt1064-evk/README.txt b/boards/arm/imxrt/imxrt1064-evk/README.txt deleted file mode 100644 index 0947793acf7..00000000000 --- a/boards/arm/imxrt/imxrt1064-evk/README.txt +++ /dev/null @@ -1,363 +0,0 @@ -README -====== - - This README file provides information about the port of NuttX to the NXP - i.MXRT evaluation kit, MIMXRT1064-EVK. This board features the - MIMXRT1064DVL6A MCU. Some of the features of this board include: - - o Processor - - - MIMXRT1066DVL6A processor - - o Memory - - - 1 Mb OCRAM memory - - 256 Mb SDRAM memory - - 512 Mb Hyper Flash - Populated but 0 ohm DNP - - 64 Mb QSPI Flash - - TF socket for SD card - - o Display and Audio - - - Parallel LCD connector - - Camera connector - - Audio CODEC - - 4-pole audio headphone jack - - External speaker connection - - Microphone - - SPDIF connector - - o Connectivity - - - Micro USB host and OTG connectors - - Ethernet (10/100T) connector - - CAN transceivers - - Arduino® interface - - o Sensors - - - FXOS8700CQ 6-Axis Ecompass (3-Axis Mag, 3-Axis Accel) - -Contents -======== - - o Serial Console - o LEDs and buttons - o J-Link External Debug Probe - o Configurations - - Configuration sub-directories - -Serial Console -============== - - Virtual console port provided by OpenSDA: - - UART1_TXD GPIO_AD_B0_12 LPUART1_TX - UART1_RXD GPIO_AD_B0_13 LPUART1_RX - - Arduino RS-232 Shield: - - J22 D0 UART_RX/D0 GPIO_AD_B1_07 LPUART3_RX - J22 D1 UART_TX/D1 GPIO_AD_B1_06 LPUART3_TX - -LEDs and buttons -================ - - LEDs - ---- - - There are four LED status indicators located on the EVK Board. The - functions of these LEDs include: - - - Main Power Supply(D3) - Green: DC 5V main supply is normal. - Red: J2 input voltage is over 5.6V. - Off: The board is not powered. - - Reset RED LED(D21) - - OpenSDA LED(D20) - - USER LED(D18) - - Only a single LED, D18, is under software control. It connects to - GPIO_AD_B0_09 which is shared with JTAG_TDI and ENET_RST - - This LED is not used by the board port unless CONFIG_ARCH_LEDS is - defined. In that case, the usage by the board port is defined in - include/board.h and src/imxrt_autoleds.c. The LED is used to encode - OS-related events as follows: - - ------------------- ----------------------- ------ - SYMBOL Meaning LED - ------------------- ----------------------- ------ - LED_STARTED NuttX has been started OFF - LED_HEAPALLOCATE Heap has been allocated OFF - LED_IRQSENABLED Interrupts enabled OFF - LED_STACKCREATED Idle stack created ON - LED_INIRQ In an interrupt N/C - LED_SIGNAL In a signal handler N/C - LED_ASSERTION An assertion failed N/C - LED_PANIC The system has crashed FLASH - - Thus if the LED is statically on, NuttX has successfully booted and is, - apparently, running normally. If the LED is flashing at approximately - 2Hz, then a fatal error has been detected and the system has halted. - - Buttons - ------- - - There are four user interface switches on the MIMXRT1050 EVK Board: - - - SW1: Power Switch (slide switch fir power from J2) - - SW2: ON/OFF Button - - SW3: Power-on Reset button state forces to reset the system power except - SNVS domain - - SW9: Reset button - - SW8: User button GPIO5-00 - - Only the user button is available to the software. It is sensed on the - WAKEUP pin which will be pulled low when the button is pressed. - - -J-Link External Debug Probe -=========================== - - Install the J-Link Debug Host Tools and make sure they are in your search path. - - Attach a J-Link 20-pin connector to J21. Check that jumpers J47 and J48 are - off (they are on by default when boards ship from the factory) to ensure SWD - signals are disconnected from the OpenSDA microcontroller. - -Configurations -============== - - Information Common to All Configurations - ---------------------------------------- - Each i.MX RT 1064 configuration is maintained in a sub-directory and - can be selected as follow: - - tools/configure.sh [OPTIONS] imxrt1064-evk: - - Where typical options are -l to configure to build on Linux or -c to - configure for Cygwin under Linux. 'tools/configure.sh -h' will show - you all of the options. - - Before building, make sure the PATH environment variable include the - correct path to the directory than holds your toolchain binaries. - - And then build NuttX by simply typing the following. At the conclusion of - the make, the nuttx binary will reside in an ELF file called, simply, nuttx. - - make - - The that is provided above as an argument to the tools/configure.sh - must be is one of the following. - - NOTES: - - 1. These configurations use the mconf-based configuration tool. To - change any of these configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. Unless stated otherwise, all configurations generate console - output on UART3 (i.e., for the Arduino serial shield). - - 3. All of these configurations are set up to build under Windows using the - "GNU Tools for ARM Embedded Processors" that is maintained by ARM - (unless stated otherwise in the description of the configuration). - - https://developer.arm.com/open-source/gnu-toolchain/gnu-rm - - That toolchain selection can easily be reconfigured using - 'make menuconfig'. Here are the relevant current settings: - - Build Setup: - CONFIG_HOST_WINDOWS=y : Window environment - CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows - - System Type -> Toolchain: - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain - -Configuration sub-directories ------------------------------ - - can: - - This is an nsh configuration (see below) with added support of CAN driver. - FlexCAN3 is chosen as default, the change can be made at System type peripheral - selection. Please note that only FlexCAN3 and FlexCAN2 is available on this board. - - Bitrate and sample point can be also changed at System type peripheral selection, - basic values are 1 MHz for bitrate and 0.80 for sample point. The FlexCAN driver - for imxrt runs at 80 MHz clock frequency. - - The configuration also includes CAN utilities as candump and cansend. - - canfd: - - This is an nsh configuration (see below) with added support of CAN_FD driver. - FlexCAN3 is chosen as default, please note that only FlexCAN3 is capable of - providing CAN_FD support. - - Bitrate and sample point can be also changed at System type peripheral selection, - basic values are 1 MHz for bitrate and 0.80 for sample point for arbitration phase - and 4 MHz (bitrate) and 0.90 (sample point) for data phase. The FlexCAN driver - for imxrt runs at 80 MHz clock frequency. - - The configuration also includes CAN utilities as candump and cansend. - - knsh: - - This is identical to the nsh configuration below except that NuttX - is built as a protected mode, monolithic module and the user applications - are built separately. It is recommends to use a special make command; - not just 'make' but make with the following two arguments: - - make pass1 pass2 - - In the normal case (just 'make'), make will attempt to build both user- - and kernel-mode blobs more or less interleaved. This actual works! - However, for me it is very confusing so I prefer the above make command: - Make the user-space binaries first (pass1), then make the kernel-space - binaries (pass2) - - NOTES: - - 1. At the end of the build, there will be several files in the top-level - NuttX build directory: - - PASS1: - nuttx_user.elf - The pass1 user-space ELF file - nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig) - User.map - Symbols in the user-space ELF file - - PASS2: - nuttx - The pass2 kernel-space ELF file - nuttx.hex - The pass2 Intel HEX file (selected in defconfig) - System.map - Symbols in the kernel-space ELF file - - The J-Link programmer will except files in .hex, .mot, .srec, and .bin - formats. - - 2. Combining .hex files. If you plan to use the .hex files with your - debugger or FLASH utility, then you may need to combine the two hex - files into a single .hex file. Here is how you can do that. - - a. The 'tail' of the nuttx.hex file should look something like this - (with my comments added beginning with #): - - $ tail nuttx.hex - #xx xxxx 00 data records - ... - :10 C93C 00 000000000040184000C2010000000000 90 - :10 C94C 00 2400080000801B4000C01B4000001C40 5D - :10 C95C 00 00401C4000000C4050BF0060FF000100 74 - #xx xxxx 05 Start Linear Address Record - :04 0000 05 6000 02C1 D4 - #xx xxxx 01 End Of File record - :00 0000 01 FF - - Use an editor such as vi to remove the 05 and 01 records. - - b. The 'head' of the nuttx_user.hex file should look something like - this (again with my comments added beginning with #): - - $ head nuttx_user.hex - #xx xxxx 04 Extended Linear Address Record - :02 0000 04 6020 7A - #xx xxxx 00 data records - :10 0000 00 8905206030002060F2622060FC622060 80 - :10 0010 00 0000242008002420080024205C012420 63 - :10 0020 00 140024203D0020603100206071052060 14 - ... - - Nothing needs to be done here. The nuttx_user.hex file should - be fine. - - c. Combine the edited nuttx.hex and un-edited nuttx_user.hex - file to produce a single combined hex file: - - $ cat nuttx.hex nuttx_user.hex >combined.hex - - Then use the combined.hex file with the to write the FLASH image. - If you do this a lot, you will probably want to invest a little time - to develop a tool to automate these steps. - - STATUS: This configuration was added on 8 June 2018 primarily to assure - that all of the components are in place to support the PROTECTED mode - build. This configuration, however, has not been verified as of this - writing. - - netnsh: - - This configuration is similar to the nsh configuration except that is - has networking enabled, both IPv4 and IPv6. This NSH configuration is - focused on network-related testing. - - NOTES: - - 1. LED support is disabled because there is a conflict between the LED - GPIO and PHY pin usage. - - 2. Telnet is enabled. But since both IPv4 and IPv6 are enabled, it - will default to IPv6. That means that to connect a Telnet session - from a PC, you will need to use the IPv6 address which by defaault - is: - - telnet fc00::2 - - Or, disable IPv4 support so that only IPv4 addressing is used. - - 3. The network monitor is not enabled in this configuration. As a - result, the Ethernet cable must be connected when the board is - powered up. Otherwise, it will stall for a long period of time - before the NSH prompt appears and you will not be able to used - the board. - - The following configuration options should be added to your - configuration in order to use the network monitor: - - CONFIG_IMXRT_ENET_PHYINIT=y - CONFIG_IMXRT_GPIO1_0_15_IRQ=y - CONFIG_IMXRT_GPIO_IRQ=y - CONFIG_NETDEV_IOCTL=y - CONFIG_NETDEV_PHY_IOCTL=y - CONFIG_NSH_NETINIT_MONITOR=y - CONFIG_NSH_NETINIT_RETRYMSEC=2000 - CONFIG_NSH_NETINIT_SIGNO=18 - CONFIG_NSH_NETINIT_THREAD=y - CONFIG_NSH_NETINIT_THREAD_PRIORITY=80 - CONFIG_NSH_NETINIT_THREAD_STACKSIZE=1568 - - nsh: - - Configures the NuttShell (nsh) located at examples/nsh. This NSH - configuration is focused on low level, command-line driver testing. - Built-in applications are supported, but none are enabled. This - configuration does not support a network. - - lvgl: - - Configures the Littlev graphic library (lvgl) demo located under - examples/lvgldemo. This configuration needs the optional LCD model - RK043FN02H-CT from NXP. The LCD panel comes with the integrated - capacitive touchscreen sensor FT5336GQQ connected to the LPI2C1 bus, - address 0x38. NuttX support such touchscreen device via the driver - ft5x06 (drivers/input/ft5x06.c). At the moment only the polling - method is available, the board features an interrupt line connected - to the touchscreen sensor IC. - - IMXRT1062 MCU provides the integrated LCD driver. - - The LCD panel features: - - size 4.3" - - resolution 480×272 RGB - - backlight driver - - dimensions [mm]: 105.5 (W) x 67.2(H) x 4.35(D) Max. - - To run the lvgl demo please type "lvgldemo" at nsh prompt: - - nsh> lvgldemo diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/can/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/can/defconfig index dbe25bce7ee..8ca07659ad7 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/can/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/can/defconfig @@ -52,7 +52,6 @@ CONFIG_IMXRT_FLEXCAN3=y CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_IFINDEX=y diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/canfd/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/canfd/defconfig index 9d1e92f4317..83c239149c3 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/canfd/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/canfd/defconfig @@ -53,7 +53,6 @@ CONFIG_IMXRT_FLEXCAN3=y CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_IFINDEX=y diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs b/boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs index c1a94e746fc..90a487e5d4f 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs +++ b/boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/knsh/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/knsh/defconfig index 1c0ed8c7c75..c82f3456391 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/knsh/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/knsh/defconfig @@ -26,7 +26,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_DISABLE_MKRD=y CONFIG_NSH_FILEIOSIZE=512 @@ -40,5 +39,5 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=8 CONFIG_START_MONTH=6 CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/libcxxtest/Make.defs b/boards/arm/imxrt/imxrt1064-evk/configs/libcxxtest/Make.defs index c4c21108a8e..10954e43451 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/libcxxtest/Make.defs +++ b/boards/arm/imxrt/imxrt1064-evk/configs/libcxxtest/Make.defs @@ -81,8 +81,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/libcxxtest/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/libcxxtest/defconfig index c751349f3bb..d73afbf2bde 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/libcxxtest/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/libcxxtest/defconfig @@ -26,7 +26,6 @@ CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LOCALTIME=y CONFIG_LIBM=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/lvgl/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/lvgl/defconfig index 57b2e645e95..b0d2cfb599c 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/lvgl/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/lvgl/defconfig @@ -44,7 +44,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LV_HOR_RES=480 CONFIG_LV_VER_RES=272 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/netnsh/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/netnsh/defconfig index 2fbf3d3a6c6..a3809c48a88 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/netnsh/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/netnsh/defconfig @@ -28,7 +28,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=128 CONFIG_LIB_HOSTNAME="i.MXRT1060 EVK" CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_STATISTICS=y @@ -46,7 +45,6 @@ CONFIG_NET_ICMPv6=y CONFIG_NET_ICMPv6_NEIGHBOR=y CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/nsh/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/nsh/defconfig index c5d6843902a..898d977d6ce 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/nsh/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/nshocram/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/nshocram/defconfig index 98c187db1e4..6a417670ff6 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/nshocram/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/nshocram/defconfig @@ -27,7 +27,6 @@ CONFIG_IMXRT_DTCM_HEAP=y CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/imxrt/imxrt1064-evk/kernel/Makefile b/boards/arm/imxrt/imxrt1064-evk/kernel/Makefile index 301e7d5fadf..675d07089f9 100644 --- a/boards/arm/imxrt/imxrt1064-evk/kernel/Makefile +++ b/boards/arm/imxrt/imxrt1064-evk/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/imxrt/imxrt1064-evk/scripts/Make.defs b/boards/arm/imxrt/imxrt1064-evk/scripts/Make.defs index 576e0340c3f..e58d322e92f 100644 --- a/boards/arm/imxrt/imxrt1064-evk/scripts/Make.defs +++ b/boards/arm/imxrt/imxrt1064-evk/scripts/Make.defs @@ -29,9 +29,9 @@ else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y) endif ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" + ARCHSCRIPT = -Wl,-T"${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" else - ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + ARCHSCRIPT = -Wl,-T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions @@ -73,9 +73,9 @@ endif ifneq ($(CROSSDEV),arm-nuttx-elf-) LDFLAGS += -nostartfiles -nodefaultlibs ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - LDFLAGS += -Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" + LDFLAGS += -Wl,-Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" else - LDFLAGS += -Map=$(TOPDIR)/nuttx.map + LDFLAGS += -Wl,-Map=$(TOPDIR)/nuttx.map endif endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) diff --git a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_ft5x06.c b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_ft5x06.c index 94f13cde56b..ad66230c090 100644 --- a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_ft5x06.c +++ b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_ft5x06.c @@ -44,6 +44,7 @@ #include #include +#include #include #include diff --git a/boards/arm/imxrt/teensy-4.x/configs/can-4.1/defconfig b/boards/arm/imxrt/teensy-4.x/configs/can-4.1/defconfig index 99f5488041c..65c14c12741 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/can-4.1/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/can-4.1/defconfig @@ -30,7 +30,6 @@ CONFIG_IMXRT_FLEXCAN3=y CONFIG_IMXRT_LPUART1=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_IFINDEX=y diff --git a/boards/arm/imxrt/teensy-4.x/configs/enc-4.1/defconfig b/boards/arm/imxrt/teensy-4.x/configs/enc-4.1/defconfig new file mode 100644 index 00000000000..451a8d31f54 --- /dev/null +++ b/boards/arm/imxrt/teensy-4.x/configs/enc-4.1/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="teensy-4.x" +CONFIG_ARCH_BOARD_TEENSY_4X=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1062DVL6A=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_BUILTIN=y +CONFIG_ENC1_XIP=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_ENC1=y +CONFIG_IMXRT_LPUART1=y +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_NCHAINS=24 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_MM_IOB=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=1048576 +CONFIG_RAM_START=0x20200000 +CONFIG_SCHED_HPWORK=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_NSH=y +CONFIG_TEENSY_41=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/imxrt/teensy-4.x/configs/lcd-4.1/defconfig b/boards/arm/imxrt/teensy-4.x/configs/lcd-4.1/defconfig index aba08c9377b..7a620c9c1a3 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/lcd-4.1/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/lcd-4.1/defconfig @@ -32,7 +32,6 @@ CONFIG_LCD=y CONFIG_LCD_FRAMEBUFFER=y CONFIG_LCD_PORTRAIT=y CONFIG_LCD_ST7789=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/imxrt/teensy-4.x/configs/netnsh-4.1/defconfig b/boards/arm/imxrt/teensy-4.x/configs/netnsh-4.1/defconfig index bf9284ee86a..ab10887c533 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/netnsh-4.1/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/netnsh-4.1/defconfig @@ -29,7 +29,6 @@ CONFIG_IMXRT_LPUART1=y CONFIG_IMXRT_USBDEV=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HOSTNAME="Teensy 4.x" -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_STATISTICS=y @@ -44,7 +43,6 @@ CONFIG_NET_ICMPv6=y CONFIG_NET_ICMPv6_NEIGHBOR=y CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/imxrt/teensy-4.x/configs/nsh-4.0/defconfig b/boards/arm/imxrt/teensy-4.x/configs/nsh-4.0/defconfig index d5d367ba951..7b57dc5053b 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/nsh-4.0/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/nsh-4.0/defconfig @@ -25,7 +25,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IMXRT_LPUART6=y CONFIG_IMXRT_USBDEV=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/imxrt/teensy-4.x/configs/nsh-4.1/defconfig b/boards/arm/imxrt/teensy-4.x/configs/nsh-4.1/defconfig index 4386bf2fdcc..a9a9d535b1e 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/nsh-4.1/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/nsh-4.1/defconfig @@ -25,7 +25,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IMXRT_LPUART1=y CONFIG_IMXRT_USBDEV=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/imxrt/teensy-4.x/configs/pikron-bb/defconfig b/boards/arm/imxrt/teensy-4.x/configs/pikron-bb/defconfig index ce1a6905a8f..2abd15ff351 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/pikron-bb/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/pikron-bb/defconfig @@ -73,7 +73,6 @@ CONFIG_LIBC_STRERROR=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_HOSTNAME="Teensy 4.x" CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/imxrt/teensy-4.x/configs/pwm-4.1/defconfig b/boards/arm/imxrt/teensy-4.x/configs/pwm-4.1/defconfig new file mode 100644 index 00000000000..9f76a8ace86 --- /dev/null +++ b/boards/arm/imxrt/teensy-4.x/configs/pwm-4.1/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="teensy-4.x" +CONFIG_ARCH_BOARD_TEENSY_4X=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1062DVL6A=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm1" +CONFIG_EXAMPLES_PWM_DURATION=10 +CONFIG_EXAMPLES_PWM_DUTYPCT1=30 +CONFIG_EXAMPLES_PWM_DUTYPCT2=80 +CONFIG_EXAMPLES_PWM_FREQUENCY=4000 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_FLEXPWM2=y +CONFIG_IMXRT_FLEXPWM2_MOD1=y +CONFIG_IMXRT_FLEXPWM2_MOD2=y +CONFIG_IMXRT_LPUART1=y +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_NCHAINS=24 +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_MM_IOB=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PWM=y +CONFIG_PWM_MULTICHAN=y +CONFIG_PWM_NCHANNELS=2 +CONFIG_RAM_SIZE=1048576 +CONFIG_RAM_START=0x20200000 +CONFIG_SCHED_HPWORK=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_NSH=y +CONFIG_TEENSY_41=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/imxrt/teensy-4.x/configs/sd-4.1/defconfig b/boards/arm/imxrt/teensy-4.x/configs/sd-4.1/defconfig index 81577d12f5b..0d36e163b4e 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/sd-4.1/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/sd-4.1/defconfig @@ -33,7 +33,6 @@ CONFIG_IMXRT_USDHC1=y CONFIG_IMXRT_USDHC1_INVERT_CD=y CONFIG_IMXRT_USDHC1_WIDTH_D1_D4=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/imxrt/teensy-4.x/include/board.h b/boards/arm/imxrt/teensy-4.x/include/board.h index ec9f415c933..0814c2d20a0 100644 --- a/boards/arm/imxrt/teensy-4.x/include/board.h +++ b/boards/arm/imxrt/teensy-4.x/include/board.h @@ -276,6 +276,11 @@ #define GPIO_FLEXCAN3_TX (GPIO_FLEXCAN3_TX_3|IOMUX_CAN_DEFAULT) /* GPIO_EMC_36 */ #define GPIO_FLEXCAN3_RX (GPIO_FLEXCAN3_RX_3|IOMUX_CAN_DEFAULT) /* GPIO_EMC_37 */ +/* FlexPWM */ + +#define GPIO_FLEXPWM2_MOD1_A (GPIO_FLEXPWM2_PWMA00_1|IOMUX_PWM_DEFAULT) /* GPIO_EMC_06 */ +#define GPIO_FLEXPWM2_MOD2_A (GPIO_FLEXPWM2_PWMA01_1|IOMUX_PWM_DEFAULT) /* GPIO_EMC_08 */ + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/boards/arm/imxrt/teensy-4.x/kernel/Makefile b/boards/arm/imxrt/teensy-4.x/kernel/Makefile index 9747245bbb8..a1b7c5110af 100644 --- a/boards/arm/imxrt/teensy-4.x/kernel/Makefile +++ b/boards/arm/imxrt/teensy-4.x/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/imxrt/teensy-4.x/scripts/Make.defs b/boards/arm/imxrt/teensy-4.x/scripts/Make.defs index 918effcb137..b3bc1fda34e 100644 --- a/boards/arm/imxrt/teensy-4.x/scripts/Make.defs +++ b/boards/arm/imxrt/teensy-4.x/scripts/Make.defs @@ -37,7 +37,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm @@ -68,8 +68,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS = $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/imxrt/teensy-4.x/src/Makefile b/boards/arm/imxrt/teensy-4.x/src/Makefile index 1fdea29693e..d31beb00363 100644 --- a/boards/arm/imxrt/teensy-4.x/src/Makefile +++ b/boards/arm/imxrt/teensy-4.x/src/Makefile @@ -46,10 +46,18 @@ ifeq ($(CONFIG_IMXRT_FLEXCAN),y) CSRCS += imxrt_flexcan.c endif +ifeq ($(CONFIG_IMXRT_FLEXPWM),y) +CSRCS += imxrt_flexpwm.c +endif + ifeq ($(CONFIG_IMXRT_ENET),y) CSRCS += imxrt_ethernet.c endif +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += imxrt_gpio.c +endif + ifeq ($(CONFIG_IMXRT_ADC),y) CSRCS += imxrt_adc.c endif @@ -58,4 +66,8 @@ ifeq ($(CONFIG_LCD_ST7789),y) CSRCS += imxrt_st7789.c endif +ifeq ($(CONFIG_IMXRT_ENC),y) +CSRCS += imxrt_enc.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c b/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c index 6c84308c7d7..0b091182960 100644 --- a/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c @@ -163,6 +163,15 @@ int imxrt_bringup(void) } #endif +#ifdef CONFIG_IMXRT_FLEXPWM + ret = imxrt_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: imxrt_pwm_setup() failed: %d\n", ret); + return ret; + } +#endif + #ifdef CONFIG_VIDEO_FB /* Initialize and register the framebuffer driver */ @@ -183,6 +192,26 @@ int imxrt_bringup(void) } #endif +#ifdef CONFIG_DEV_GPIO + /* Initialize GPIO driver */ + + ret = imxrt_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: imxrt_gpio_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_IMXRT_ENC + /* Initialize ENC and register the ENC driver. */ + + ret = imxrt_enc_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: imxrt_enc_initialize() failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_enc.c b/boards/arm/imxrt/teensy-4.x/src/imxrt_enc.c new file mode 100644 index 00000000000..0aa0226eb35 --- /dev/null +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_enc.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/imxrt/teensy-4.x/src/imxrt_enc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "imxrt_enc.h" +#include "imxrt_xbar.h" +#include "teensy-4.h" + +#if defined(CONFIG_IMXRT_ENC) && defined(CONFIG_SENSORS_QENCODER) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_enc_initialize + * + * Description: + * Initialize the quadrature encoder driver for the given timer + * + ****************************************************************************/ + +int imxrt_enc_initialize(void) +{ + int ret; +#ifdef CONFIG_IMXRT_ENC1 + /* Initialize a quadrature encoder interface. */ + + imxrt_config_gpio(GPIO_ENC1_PHASE_A); + imxrt_config_gpio(GPIO_ENC1_PHASE_B); + imxrt_config_gpio(GPIO_ENC1_INDEX); + + /* Connect XBAR pins */ + + ret = imxrt_xbar_connect(IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET, + IMXRT_XBARA1_IN_IOMUX_XBAR_IO09); + if (ret < 0) + { + snerr("ERROR: imxrt_xbar_connect failed: %d\n", ret); + return -ENODEV; + } + + ret = imxrt_xbar_connect(IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET, + IMXRT_XBARA1_IN_IOMUX_XBAR_IO08); + if (ret < 0) + { + snerr("ERROR: imxrt_xbar_connect failed: %d\n", ret); + return -ENODEV; + } + + ret = imxrt_xbar_connect(IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET, + IMXRT_XBARA1_IN_IOMUX_XBAR_IO10); + if (ret < 0) + { + snerr("ERROR: imxrt_xbar_connect failed: %d\n", ret); + return -ENODEV; + } + + ret = imxrt_qeinitialize("dev/qe0", 1); + if (ret < 0) + { + snerr("ERROR: imxrt_qeinitialize failed: %d\n", ret); + return -ENODEV; + } + +#endif +#ifdef CONFIG_IMXRT_ENC2 + /* Initialize a quadrature encoder interface. */ + + ret = imxrt_qeinitialize("dev/qe1", 2) + if (ret < 0) + { + snerr("ERROR: imxrt_qeinitialize failed: %d\n", ret); + return -ENODEV; + } + +#endif +#ifdef CONFIG_IMXRT_ENC3 + /* Initialize a quadrature encoder interface. */ + + ret = imxrt_qeinitialize("dev/qe2", 3) + if (ret < 0) + { + snerr("ERROR: imxrt_qeinitialize failed: %d\n", ret); + return -ENODEV; + } + +#endif +#ifdef CONFIG_IMXRT_ENC4 + /* Initialize a quadrature encoder interface. */ + + ret = imxrt_qeinitialize("dev/qe4", 4) + if (ret < 0) + { + snerr("ERROR: imxrt_qeinitialize failed: %d\n", ret); + return -ENODEV; + } + +#endif + UNUSED(ret); + return OK; +} +#endif /* CONFIG_IMXRT_ENC */ \ No newline at end of file diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_flexpwm.c b/boards/arm/imxrt/teensy-4.x/src/imxrt_flexpwm.c new file mode 100644 index 00000000000..fe17cb838d4 --- /dev/null +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_flexpwm.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/imxrt/teensy-4.x/src/imxrt_flexpwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "imxrt_flexpwm.h" +#include "teensy-4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_PWM + +extern struct pwm_lowerhalf_s *imxrt_pwminitialize(int pwm); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int imxrt_pwm_setup(void) +{ + struct pwm_lowerhalf_s *pwm; + int ret; + +#ifdef CONFIG_IMXRT_FLEXPWM1 + /* Call imxrt_pwminitialize() to get an instance of the PWM interface */ + + pwm = imxrt_pwminitialize(1); + if (!pwm) + { + aerr("ERROR: Failed to get the IMXRT PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif +#ifdef CONFIG_IMXRT_FLEXPWM2 + /* Call imxrt_pwminitialize() to get an instance of the PWM interface */ + + pwm = imxrt_pwminitialize(2); + if (!pwm) + { + aerr("ERROR: Failed to get the IMXRT PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm1" */ + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif +#ifdef CONFIG_IMXRT_FLEXPWM3 + /* Call imxrt_pwminitialize() to get an instance of the PWM interface */ + + pwm = imxrt_pwminitialize(3); + if (!pwm) + { + aerr("ERROR: Failed to get the IMXRT PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm2" */ + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif +#ifdef CONFIG_IMXRT_FLEXPWM4 + /* Call imxrt_pwminitialize() to get an instance of the PWM interface */ + + pwm = imxrt_pwminitialize(4); + if (!pwm) + { + aerr("ERROR: Failed to get the IMXRT PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm3" */ + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif + + UNUSED(ret); + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_gpio.c b/boards/arm/imxrt/teensy-4.x/src/imxrt_gpio.c new file mode 100644 index 00000000000..62b2829a69d --- /dev/null +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_gpio.c @@ -0,0 +1,214 @@ +/**************************************************************************** + * boards/arm/imxrt/teensy-4.x/src/imxrt_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "imxrt_gpio.h" +#include "teensy-4.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imxrtgpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value); +#endif +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpout_write(FAR struct gpio_dev_s *dev, bool value); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct imxrtgpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct imxrtgpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct imxrtgpio_dev_s *imxrtgpio = + (FAR struct imxrtgpio_dev_s *)dev; + + DEBUGASSERT(imxrtgpio != NULL && value != NULL); + DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = imxrt_gpio_read(g_gpioinputs[imxrtgpio->id]); + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct imxrtgpio_dev_s *imxrtgpio = + (FAR struct imxrtgpio_dev_s *)dev; + + DEBUGASSERT(imxrtgpio != NULL && value != NULL); + DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = imxrt_gpio_read(g_gpiooutputs[imxrtgpio->id]); + return OK; +} + +static int gpout_write(FAR struct gpio_dev_s *dev, bool value) +{ + FAR struct imxrtgpio_dev_s *imxrtgpio = + (FAR struct imxrtgpio_dev_s *)dev; + + DEBUGASSERT(imxrtgpio != NULL); + DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + imxrt_gpio_write(g_gpiooutputs[imxrtgpio->id], value); + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int imxrt_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + imxrt_config_gpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + imxrt_gpio_write(g_gpiooutputs[i], 0); + imxrt_config_gpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/imxrt/teensy-4.x/src/teensy-4.h b/boards/arm/imxrt/teensy-4.x/src/teensy-4.h index 430a51f3480..188d53d3c4e 100644 --- a/boards/arm/imxrt/teensy-4.x/src/teensy-4.h +++ b/boards/arm/imxrt/teensy-4.x/src/teensy-4.h @@ -35,6 +35,7 @@ # include "imxrt_gpio.h" # include "imxrt_iomuxc.h" +# include "hardware/imxrt_pinmux.h" /**************************************************************************** * Pre-processor Definitions @@ -111,6 +112,21 @@ #define GPIO_ENET_RST (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \ GPIO_PORT2 | GPIO_PIN14 | IOMUX_ENET_RST_DEFAULT) /* B0_14 */ +/* Quadrature Encoder */ + +#define GPIO_ENC1_PHASE_A (GPIO_XBAR1_INOUT09_1|IOMUX_ENC_DEFAULT|PADMUX_MUXMODE_ALT3) /* EMC_07 */ +#define GPIO_ENC1_PHASE_B (GPIO_XBAR1_INOUT08_1|IOMUX_ENC_DEFAULT|PADMUX_MUXMODE_ALT3) /* EMC_06 */ +#define GPIO_ENC1_INDEX (GPIO_XBAR1_INOUT10_1|IOMUX_ENC_DEFAULT|PADMUX_MUXMODE_ALT1) /* B0_12 */ + +/* GPIO pins used by the GPIO subsystem */ + +#define BOARD_NGPIOIN 1 /* Amount of GPIO input pins */ +#define BOARD_NGPIOOUT 1 /* Amount of GPIO output pins */ + +#define GPIO_IN1 (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN4) /* EMC_04 */ +#define GPIO_OUT1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PORT4 | GPIO_PIN5) /* EMC_05 */ + /**************************************************************************** * Public Types ****************************************************************************/ @@ -155,6 +171,18 @@ void imxrt_spidev_initialize(void); int imxrt_can_setup(void); #endif +/**************************************************************************** + * Name: imxrt_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_FLEXPWM +int imxrt_pwm_setup(void); +#endif + /**************************************************************************** * Name: imxrt_adc_initialize * @@ -167,6 +195,33 @@ int imxrt_can_setup(void); int imxrt_adc_initialize(void); #endif +/**************************************************************************** + * Name: imxrt_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + * Return Value: + * OK on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int imxrt_gpio_initialize(void); +#endif + +/**************************************************************************** + * Name: imxrt_enc_initialize + * + * Description: + * Initialize the quadrature encoder driver for the given timer + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_ENC +int imxrt_enc_initialize(void); +#endif + /**************************************************************************** * Name: imxrt_i2c_setup * diff --git a/boards/arm/kinetis/freedom-k28f/configs/nsh/defconfig b/boards/arm/kinetis/freedom-k28f/configs/nsh/defconfig index c7a7bbd2bb3..01ff5169203 100644 --- a/boards/arm/kinetis/freedom-k28f/configs/nsh/defconfig +++ b/boards/arm/kinetis/freedom-k28f/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_KINETIS_LPUART0=y CONFIG_KINETIS_SERIALBRK_BSDCOMPAT=y CONFIG_KINETIS_UART_BREAKS=y CONFIG_LPUART0_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/kinetis/freedom-k28f/configs/nshsdusb/defconfig b/boards/arm/kinetis/freedom-k28f/configs/nshsdusb/defconfig index 7f2936ad752..011328652c4 100644 --- a/boards/arm/kinetis/freedom-k28f/configs/nshsdusb/defconfig +++ b/boards/arm/kinetis/freedom-k28f/configs/nshsdusb/defconfig @@ -40,7 +40,6 @@ CONFIG_KINETIS_UART_BREAKS=y CONFIG_KINETIS_USBDCD=y CONFIG_KINETIS_USBOTG=y CONFIG_LPUART0_SERIAL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_NET=y diff --git a/boards/arm/kinetis/freedom-k28f/scripts/Make.defs b/boards/arm/kinetis/freedom-k28f/scripts/Make.defs index b57549d49ec..98e92dc81f1 100644 --- a/boards/arm/kinetis/freedom-k28f/scripts/Make.defs +++ b/boards/arm/kinetis/freedom-k28f/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kinetis/freedom-k28f/src/k28_autoleds.c b/boards/arm/kinetis/freedom-k28f/src/k28_autoleds.c index 44d9a022962..5bd6878be39 100644 --- a/boards/arm/kinetis/freedom-k28f/src/k28_autoleds.c +++ b/boards/arm/kinetis/freedom-k28f/src/k28_autoleds.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/freedom-k28f/src/k28_automount.c b/boards/arm/kinetis/freedom-k28f/src/k28_automount.c index a5d2b48e992..f7cb8deadc3 100644 --- a/boards/arm/kinetis/freedom-k28f/src/k28_automount.c +++ b/boards/arm/kinetis/freedom-k28f/src/k28_automount.c @@ -28,6 +28,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/kinetis/freedom-k28f/src/k28_spi.c b/boards/arm/kinetis/freedom-k28f/src/k28_spi.c index f8060b9096e..149a8d3e0ca 100644 --- a/boards/arm/kinetis/freedom-k28f/src/k28_spi.c +++ b/boards/arm/kinetis/freedom-k28f/src/k28_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/freedom-k64f/configs/cdcacm/defconfig b/boards/arm/kinetis/freedom-k64f/configs/cdcacm/defconfig index 30aaafac46c..8bc1036f593 100644 --- a/boards/arm/kinetis/freedom-k64f/configs/cdcacm/defconfig +++ b/boards/arm/kinetis/freedom-k64f/configs/cdcacm/defconfig @@ -36,7 +36,6 @@ CONFIG_KINETIS_PORTEINTS=y CONFIG_KINETIS_SDHC=y CONFIG_KINETIS_UART0=y CONFIG_KINETIS_USBOTG=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/kinetis/freedom-k64f/configs/demo/defconfig b/boards/arm/kinetis/freedom-k64f/configs/demo/defconfig index 5243de198f8..4e0ceba025a 100644 --- a/boards/arm/kinetis/freedom-k64f/configs/demo/defconfig +++ b/boards/arm/kinetis/freedom-k64f/configs/demo/defconfig @@ -40,7 +40,6 @@ CONFIG_KINETIS_I2C0=y CONFIG_KINETIS_PORTEINTS=y CONFIG_KINETIS_SDHC=y CONFIG_KINETIS_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y @@ -48,7 +47,6 @@ CONFIG_MOTOROLA_SREC=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETUTILS_NETCAT=y CONFIG_NET_BROADCAST=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/kinetis/freedom-k64f/configs/netnsh/defconfig b/boards/arm/kinetis/freedom-k64f/configs/netnsh/defconfig index cb31521345f..7634fe3c1b5 100644 --- a/boards/arm/kinetis/freedom-k64f/configs/netnsh/defconfig +++ b/boards/arm/kinetis/freedom-k64f/configs/netnsh/defconfig @@ -26,7 +26,6 @@ CONFIG_KINETIS_ENET=y CONFIG_KINETIS_ENET_MDIOPULLUP=y CONFIG_KINETIS_UART0=y CONFIG_LIB_HOSTNAME="Freedom-K64F" -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_PHY_IOCTL=y diff --git a/boards/arm/kinetis/freedom-k64f/configs/nsh/defconfig b/boards/arm/kinetis/freedom-k64f/configs/nsh/defconfig index da0762bb26b..fe3c64ce118 100644 --- a/boards/arm/kinetis/freedom-k64f/configs/nsh/defconfig +++ b/boards/arm/kinetis/freedom-k64f/configs/nsh/defconfig @@ -35,7 +35,6 @@ CONFIG_KINETIS_GPIOIRQ=y CONFIG_KINETIS_PORTEINTS=y CONFIG_KINETIS_SDHC=y CONFIG_KINETIS_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/kinetis/freedom-k64f/scripts/Make.defs b/boards/arm/kinetis/freedom-k64f/scripts/Make.defs index 7620d07d298..ed625e238fd 100644 --- a/boards/arm/kinetis/freedom-k64f/scripts/Make.defs +++ b/boards/arm/kinetis/freedom-k64f/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kinetis/freedom-k64f/src/k64_autoleds.c b/boards/arm/kinetis/freedom-k64f/src/k64_autoleds.c index 558c1d79c2f..ecd5de11f90 100644 --- a/boards/arm/kinetis/freedom-k64f/src/k64_autoleds.c +++ b/boards/arm/kinetis/freedom-k64f/src/k64_autoleds.c @@ -52,6 +52,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/freedom-k64f/src/k64_automount.c b/boards/arm/kinetis/freedom-k64f/src/k64_automount.c index a49fe563954..209b2c0b860 100644 --- a/boards/arm/kinetis/freedom-k64f/src/k64_automount.c +++ b/boards/arm/kinetis/freedom-k64f/src/k64_automount.c @@ -28,6 +28,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/kinetis/freedom-k64f/src/k64_spi.c b/boards/arm/kinetis/freedom-k64f/src/k64_spi.c index 58d5eb27a1b..dca9c719972 100644 --- a/boards/arm/kinetis/freedom-k64f/src/k64_spi.c +++ b/boards/arm/kinetis/freedom-k64f/src/k64_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/freedom-k66f/configs/netnsh/defconfig b/boards/arm/kinetis/freedom-k66f/configs/netnsh/defconfig index 79283994476..1bfa81518c1 100644 --- a/boards/arm/kinetis/freedom-k66f/configs/netnsh/defconfig +++ b/boards/arm/kinetis/freedom-k66f/configs/netnsh/defconfig @@ -36,7 +36,6 @@ CONFIG_KINETIS_PORTDINTS=y CONFIG_KINETIS_UART1=y CONFIG_KINETIS_UART4=y CONFIG_LIB_HOSTNAME="Freedom-K66F" -CONFIG_MAX_TASKS=16 CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_PHY_IOCTL=y CONFIG_NETDEV_STATISTICS=y diff --git a/boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig b/boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig index 8d2575d7151..a3cded4673a 100644 --- a/boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig +++ b/boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_KINETIS_UART4=y CONFIG_KINETIS_UART_BREAKS=y CONFIG_KINETIS_UART_EXTEDED_BREAK=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/kinetis/freedom-k66f/scripts/Make.defs b/boards/arm/kinetis/freedom-k66f/scripts/Make.defs index 9e77be1e31d..bfa11ede568 100644 --- a/boards/arm/kinetis/freedom-k66f/scripts/Make.defs +++ b/boards/arm/kinetis/freedom-k66f/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kinetis/freedom-k66f/src/k66_autoleds.c b/boards/arm/kinetis/freedom-k66f/src/k66_autoleds.c index f5d0aed2d4a..852708c44ab 100644 --- a/boards/arm/kinetis/freedom-k66f/src/k66_autoleds.c +++ b/boards/arm/kinetis/freedom-k66f/src/k66_autoleds.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/freedom-k66f/src/k66_automount.c b/boards/arm/kinetis/freedom-k66f/src/k66_automount.c index f3035087f3e..d78a7a7d968 100644 --- a/boards/arm/kinetis/freedom-k66f/src/k66_automount.c +++ b/boards/arm/kinetis/freedom-k66f/src/k66_automount.c @@ -28,6 +28,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/kinetis/freedom-k66f/src/k66_spi.c b/boards/arm/kinetis/freedom-k66f/src/k66_spi.c index 03bd9228319..449907f7d4d 100644 --- a/boards/arm/kinetis/freedom-k66f/src/k66_spi.c +++ b/boards/arm/kinetis/freedom-k66f/src/k66_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/kwikstik-k40/configs/ostest/defconfig b/boards/arm/kinetis/kwikstik-k40/configs/ostest/defconfig index 69f8edeabf8..d67dc722d17 100644 --- a/boards/arm/kinetis/kwikstik-k40/configs/ostest/defconfig +++ b/boards/arm/kinetis/kwikstik-k40/configs/ostest/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_INTELHEX_BINARY=y CONFIG_KINETIS_UART5=y -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65536 CONFIG_RAM_START=0x1fff8000 diff --git a/boards/arm/kinetis/kwikstik-k40/scripts/Make.defs b/boards/arm/kinetis/kwikstik-k40/scripts/Make.defs index 98d9b2a0732..b6a4b9eafda 100644 --- a/boards/arm/kinetis/kwikstik-k40/scripts/Make.defs +++ b/boards/arm/kinetis/kwikstik-k40/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kinetis/kwikstik-k40/src/k40_spi.c b/boards/arm/kinetis/kwikstik-k40/src/k40_spi.c index e8b48633b5b..07c401851ab 100644 --- a/boards/arm/kinetis/kwikstik-k40/src/k40_spi.c +++ b/boards/arm/kinetis/kwikstik-k40/src/k40_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/teensy-3.x/configs/nsh/defconfig b/boards/arm/kinetis/teensy-3.x/configs/nsh/defconfig index f118ce4d03c..2a945a9009f 100644 --- a/boards/arm/kinetis/teensy-3.x/configs/nsh/defconfig +++ b/boards/arm/kinetis/teensy-3.x/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_KINETIS_SERIALBRK_BSDCOMPAT=y CONFIG_KINETIS_UART0=y CONFIG_KINETIS_UARTFIFOS=y CONFIG_KINETIS_UART_BREAKS=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/kinetis/teensy-3.x/configs/usbnsh/defconfig b/boards/arm/kinetis/teensy-3.x/configs/usbnsh/defconfig index 531d528e837..15692673e9f 100644 --- a/boards/arm/kinetis/teensy-3.x/configs/usbnsh/defconfig +++ b/boards/arm/kinetis/teensy-3.x/configs/usbnsh/defconfig @@ -27,7 +27,6 @@ CONFIG_KINETIS_UART0=y CONFIG_KINETIS_UARTFIFOS=y CONFIG_KINETIS_UART_BREAKS=y CONFIG_KINETIS_USBOTG=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/kinetis/teensy-3.x/scripts/Make.defs b/boards/arm/kinetis/teensy-3.x/scripts/Make.defs index 265916b3fab..9413e57fe9f 100644 --- a/boards/arm/kinetis/teensy-3.x/scripts/Make.defs +++ b/boards/arm/kinetis/teensy-3.x/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kinetis/teensy-3.x/src/k20_spi.c b/boards/arm/kinetis/teensy-3.x/src/k20_spi.c index 0cdaad626fd..0ee1d1cb913 100644 --- a/boards/arm/kinetis/teensy-3.x/src/k20_spi.c +++ b/boards/arm/kinetis/teensy-3.x/src/k20_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/twr-k60n512/configs/nsh/defconfig b/boards/arm/kinetis/twr-k60n512/configs/nsh/defconfig index 77628510023..5b531778226 100644 --- a/boards/arm/kinetis/twr-k60n512/configs/nsh/defconfig +++ b/boards/arm/kinetis/twr-k60n512/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=9535 CONFIG_FS_FAT=y CONFIG_INTELHEX_BINARY=y CONFIG_KINETIS_UART3=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y diff --git a/boards/arm/kinetis/twr-k60n512/scripts/Make.defs b/boards/arm/kinetis/twr-k60n512/scripts/Make.defs index 61a2914071e..6520dc910f2 100644 --- a/boards/arm/kinetis/twr-k60n512/scripts/Make.defs +++ b/boards/arm/kinetis/twr-k60n512/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kinetis/twr-k60n512/src/k60_leds.c b/boards/arm/kinetis/twr-k60n512/src/k60_leds.c index 44ef4434421..b6370ff663d 100644 --- a/boards/arm/kinetis/twr-k60n512/src/k60_leds.c +++ b/boards/arm/kinetis/twr-k60n512/src/k60_leds.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/arm/kinetis/twr-k60n512/src/k60_spi.c b/boards/arm/kinetis/twr-k60n512/src/k60_spi.c index 3bf1b7ffacc..0020a4dc00e 100644 --- a/boards/arm/kinetis/twr-k60n512/src/k60_spi.c +++ b/boards/arm/kinetis/twr-k60n512/src/k60_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kinetis/twr-k64f120m/configs/netnsh/defconfig b/boards/arm/kinetis/twr-k64f120m/configs/netnsh/defconfig index e12a095404b..aeaccdfb806 100644 --- a/boards/arm/kinetis/twr-k64f120m/configs/netnsh/defconfig +++ b/boards/arm/kinetis/twr-k64f120m/configs/netnsh/defconfig @@ -27,7 +27,6 @@ CONFIG_KINETIS_PORTBINTS=y CONFIG_KINETIS_SDHC=y CONFIG_KINETIS_UART1=y CONFIG_LIB_HOSTNAME="TWRK64" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_NETINIT_DRIPADDR=0xc0a800fe diff --git a/boards/arm/kinetis/twr-k64f120m/configs/nsh/defconfig b/boards/arm/kinetis/twr-k64f120m/configs/nsh/defconfig index 04457937838..4e96a2132a8 100644 --- a/boards/arm/kinetis/twr-k64f120m/configs/nsh/defconfig +++ b/boards/arm/kinetis/twr-k64f120m/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_KINETIS_GPIOIRQ=y CONFIG_KINETIS_PORTBINTS=y CONFIG_KINETIS_SDHC=y CONFIG_KINETIS_UART1=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/kinetis/twr-k64f120m/scripts/Make.defs b/boards/arm/kinetis/twr-k64f120m/scripts/Make.defs index c860d8862e9..748147ae71d 100644 --- a/boards/arm/kinetis/twr-k64f120m/scripts/Make.defs +++ b/boards/arm/kinetis/twr-k64f120m/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kinetis/twr-k64f120m/src/k64_automount.c b/boards/arm/kinetis/twr-k64f120m/src/k64_automount.c index 5c2ff686f78..8f9a39672bc 100644 --- a/boards/arm/kinetis/twr-k64f120m/src/k64_automount.c +++ b/boards/arm/kinetis/twr-k64f120m/src/k64_automount.c @@ -28,6 +28,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/kinetis/twr-k64f120m/src/k64_leds.c b/boards/arm/kinetis/twr-k64f120m/src/k64_leds.c index 7e6f5225f52..95c5c3f1662 100644 --- a/boards/arm/kinetis/twr-k64f120m/src/k64_leds.c +++ b/boards/arm/kinetis/twr-k64f120m/src/k64_leds.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/arm/kl/freedom-kl25z/configs/nsh/defconfig b/boards/arm/kl/freedom-kl25z/configs/nsh/defconfig index 2afc0a19fba..e36e935802e 100644 --- a/boards/arm/kl/freedom-kl25z/configs/nsh/defconfig +++ b/boards/arm/kl/freedom-kl25z/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_KL_TPM0=y CONFIG_KL_TPM0_PWM=y CONFIG_KL_UART0=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_MOTOROLA_SREC=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 diff --git a/boards/arm/kl/freedom-kl25z/scripts/Make.defs b/boards/arm/kl/freedom-kl25z/scripts/Make.defs index 6881145690f..8efb86f5af0 100644 --- a/boards/arm/kl/freedom-kl25z/scripts/Make.defs +++ b/boards/arm/kl/freedom-kl25z/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kl/freedom-kl25z/src/kl_adxl345.c b/boards/arm/kl/freedom-kl25z/src/kl_adxl345.c index 38a9a6c8e7f..c3b7a9aed67 100644 --- a/boards/arm/kl/freedom-kl25z/src/kl_adxl345.c +++ b/boards/arm/kl/freedom-kl25z/src/kl_adxl345.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kl/freedom-kl25z/src/kl_led.c b/boards/arm/kl/freedom-kl25z/src/kl_led.c index 751d3dc990d..37d3afe5514 100644 --- a/boards/arm/kl/freedom-kl25z/src/kl_led.c +++ b/boards/arm/kl/freedom-kl25z/src/kl_led.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kl/freedom-kl25z/src/kl_spi.c b/boards/arm/kl/freedom-kl25z/src/kl_spi.c index dbd9f75a21a..60b48d17a89 100644 --- a/boards/arm/kl/freedom-kl25z/src/kl_spi.c +++ b/boards/arm/kl/freedom-kl25z/src/kl_spi.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kl/freedom-kl26z/configs/nsh/defconfig b/boards/arm/kl/freedom-kl26z/configs/nsh/defconfig index 1cf9c856c02..6867afc1926 100644 --- a/boards/arm/kl/freedom-kl26z/configs/nsh/defconfig +++ b/boards/arm/kl/freedom-kl26z/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_KL_TPM0=y CONFIG_KL_TPM0_PWM=y CONFIG_KL_UART0=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_MOTOROLA_SREC=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 diff --git a/boards/arm/kl/freedom-kl26z/scripts/Make.defs b/boards/arm/kl/freedom-kl26z/scripts/Make.defs index 88e2e216184..6c7b9b79209 100644 --- a/boards/arm/kl/freedom-kl26z/scripts/Make.defs +++ b/boards/arm/kl/freedom-kl26z/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kl/freedom-kl26z/src/kl_led.c b/boards/arm/kl/freedom-kl26z/src/kl_led.c index ea4a66455aa..80fe3b082f2 100644 --- a/boards/arm/kl/freedom-kl26z/src/kl_led.c +++ b/boards/arm/kl/freedom-kl26z/src/kl_led.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kl/freedom-kl26z/src/kl_spi.c b/boards/arm/kl/freedom-kl26z/src/kl_spi.c index 14be47c3927..bebda6fac8d 100644 --- a/boards/arm/kl/freedom-kl26z/src/kl_spi.c +++ b/boards/arm/kl/freedom-kl26z/src/kl_spi.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/kl/teensy-lc/configs/nsh/defconfig b/boards/arm/kl/teensy-lc/configs/nsh/defconfig index 89a6c0fc559..7032e556880 100644 --- a/boards/arm/kl/teensy-lc/configs/nsh/defconfig +++ b/boards/arm/kl/teensy-lc/configs/nsh/defconfig @@ -44,7 +44,6 @@ CONFIG_KL_TPM2=y CONFIG_KL_TPM2_PWM=y CONFIG_KL_UART0=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/kl/teensy-lc/scripts/Make.defs b/boards/arm/kl/teensy-lc/scripts/Make.defs index e41d4c08189..42773157109 100644 --- a/boards/arm/kl/teensy-lc/scripts/Make.defs +++ b/boards/arm/kl/teensy-lc/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/kl/teensy-lc/src/kl_spi.c b/boards/arm/kl/teensy-lc/src/kl_spi.c index cae585d219b..b95e0ab8593 100644 --- a/boards/arm/kl/teensy-lc/src/kl_spi.c +++ b/boards/arm/kl/teensy-lc/src/kl_spi.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/audio/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/audio/defconfig index c2f81ff4711..baa9f26b7ae 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/audio/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/audio/defconfig @@ -65,7 +65,6 @@ CONFIG_LCD=y CONFIG_LCD_ST7565=y CONFIG_LIBM=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MTD=y diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/bt/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/bt/defconfig index d92cc2f26db..b80edbd15f9 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/bt/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/bt/defconfig @@ -72,7 +72,6 @@ CONFIG_LCD=y CONFIG_LCD_ST7565=y CONFIG_LIBM=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MTD=y @@ -103,7 +102,6 @@ CONFIG_NET_TCP_KEEPALIVE=y CONFIG_NET_TUN=y CONFIG_NET_TUN_PKTSIZE=1500 CONFIG_NET_UDP=y -CONFIG_NET_UDP_BINDTODEVICE=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CMDOPT_DD_STATS=y diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/elf/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/elf/defconfig index 7c5a09bd5e2..1c98b40fbc3 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/elf/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/elf/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_CHIP_LC823450=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STDARG_H=y CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=12061 CONFIG_C99_BOOL8=y @@ -34,7 +35,6 @@ CONFIG_LIBM=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_NAME_MAX=765 CONFIG_NETUTILS_CODECS=y diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/ipl2/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/ipl2/defconfig index 33d08c21144..4cc6b853561 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/ipl2/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/ipl2/defconfig @@ -34,7 +34,6 @@ CONFIG_LC823450_SDIF_SDC=y CONFIG_LC823450_UART0=y CONFIG_LC823450_UART1=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_MTD=y CONFIG_NAME_MAX=765 diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/knsh/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/knsh/defconfig index 3eae4178cd5..aaecfdb5d9d 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/knsh/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/knsh/defconfig @@ -47,7 +47,6 @@ CONFIG_LCD=y CONFIG_LCD_ST7565=y CONFIG_LIBM=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NAME_MAX=765 @@ -109,7 +108,7 @@ CONFIG_START_YEAR=2013 CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TIME64=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=24 CONFIG_UART0_RXBUFSIZE=512 CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/kostest/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/kostest/defconfig index a50cc7a5745..6a7d5957f61 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/kostest/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/kostest/defconfig @@ -23,7 +23,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LC823450_MTM0_TICK=y CONFIG_LC823450_SPIFI=y CONFIG_LC823450_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_NUTTX_USERSPACE=0x05020000 CONFIG_PASS1_BUILDIR="boards/arm/lc823450/lc823450-xgevk/kernel" CONFIG_PREALLOC_TIMERS=4 @@ -40,7 +39,7 @@ CONFIG_START_MONTH=10 CONFIG_START_YEAR=2013 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_TIME64=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TESTING_OSTEST=y CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3 CONFIG_TESTING_OSTEST_STACKSIZE=2048 diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/krndis/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/krndis/defconfig index fcbdd4cc5c9..8800ad015f6 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/krndis/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/krndis/defconfig @@ -78,7 +78,6 @@ CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MTD=y @@ -107,7 +106,6 @@ CONFIG_NET_ROUTE=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y -CONFIG_NET_UDP_BINDTODEVICE=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_CMDOPT_DD_STATS=y CONFIG_NSH_DISABLE_BASENAME=y @@ -174,7 +172,7 @@ CONFIG_SYSTEM_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_SYSTEM_NXPLAYER=y CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_TIME64=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=24 CONFIG_TELNET_CHARACTER_MODE=y CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/nsh/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/nsh/defconfig index 62b61a6bb67..a67d732de90 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/nsh/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/nsh/defconfig @@ -52,7 +52,6 @@ CONFIG_LCD=y CONFIG_LCD_ST7565=y CONFIG_LIBM=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NAME_MAX=765 diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/posix_spawn/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/posix_spawn/defconfig index c4438e5609d..ce10e7909e1 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/posix_spawn/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/posix_spawn/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_CHIP_LC823450=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STDARG_H=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=12061 CONFIG_C99_BOOL8=y CONFIG_CODECS_HASH_MD5=y @@ -33,7 +34,6 @@ CONFIG_LIBM=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_NAME_MAX=765 CONFIG_NETUTILS_CODECS=y diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig index 8735ddd4d4e..7199a9531bd 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig @@ -74,7 +74,6 @@ CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MTD=y @@ -105,7 +104,6 @@ CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y -CONFIG_NET_UDP_BINDTODEVICE=y CONFIG_NFS=y CONFIG_NFS_STATISTICS=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/usb/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/usb/defconfig index 808da783586..fcc9aaaa832 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/usb/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/usb/defconfig @@ -61,7 +61,6 @@ CONFIG_LCD=y CONFIG_LCD_ST7565=y CONFIG_LIBM=y CONFIG_LIB_KBDCODEC=y -CONFIG_MAX_TASKS=64 CONFIG_MEMSET_OPTSPEED=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MTD=y diff --git a/boards/arm/lc823450/lc823450-xgevk/kernel/Makefile b/boards/arm/lc823450/lc823450-xgevk/kernel/Makefile index 384fde4c8d6..a34a392aba4 100644 --- a/boards/arm/lc823450/lc823450-xgevk/kernel/Makefile +++ b/boards/arm/lc823450/lc823450-xgevk/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/lc823450/lc823450-xgevk/kernel/lc823450_userspace.c b/boards/arm/lc823450/lc823450-xgevk/kernel/lc823450_userspace.c index c6ce154b0e3..7eedb98bd30 100644 --- a/boards/arm/lc823450/lc823450-xgevk/kernel/lc823450_userspace.c +++ b/boards/arm/lc823450/lc823450-xgevk/kernel/lc823450_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/lc823450/lc823450-xgevk/scripts/Make.defs b/boards/arm/lc823450/lc823450-xgevk/scripts/Make.defs index 386130b0bd4..9ede77232b2 100644 --- a/boards/arm/lc823450/lc823450-xgevk/scripts/Make.defs +++ b/boards/arm/lc823450/lc823450-xgevk/scripts/Make.defs @@ -61,8 +61,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions @@ -88,7 +88,7 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) LDFLAGS += -g endif -LDFLAGS += --gc-sections +LDFLAGS += -Wl,--gc-sections ifeq ($(CONFIG_LC823450_SDIF_PATCH),y) @@ -102,8 +102,8 @@ ifeq ($(CONFIG_CYGWIN_WINTOOL),y) else ARCH_SYMBOLS = $(TOPDIR)/arch/arm/src/lc823450/lc823450_symbols.ld endif - ARCH_LIBS += $(ARCH_LIBS_OPT) --just-symbols=$(ARCH_SYMBOLS) - LDFLAGS += --no-wchar-size-warning + ARCH_LIBS += $(ARCH_LIBS_OPT) -Wl,--just-symbols=$(ARCH_SYMBOLS) + LDFLAGS += -Wl,--no-wchar-size-warning endif diff --git a/boards/arm/lc823450/lc823450-xgevk/src/lc823450_st7565.c b/boards/arm/lc823450/lc823450-xgevk/src/lc823450_st7565.c index 6724e0fec61..1da8305197f 100644 --- a/boards/arm/lc823450/lc823450-xgevk/src/lc823450_st7565.c +++ b/boards/arm/lc823450/lc823450-xgevk/src/lc823450_st7565.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/lpc17xx_40xx/lincoln60/configs/netnsh/defconfig b/boards/arm/lpc17xx_40xx/lincoln60/configs/netnsh/defconfig index 561d2753705..1c2a9bb49a2 100644 --- a/boards/arm/lpc17xx_40xx/lincoln60/configs/netnsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lincoln60/configs/netnsh/defconfig @@ -26,7 +26,6 @@ CONFIG_LPC17_40_ETH_NTXDESC=6 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_SSP0=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/lpc17xx_40xx/lincoln60/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/lincoln60/configs/nsh/defconfig index 8a5027c84ec..1794862f255 100644 --- a/boards/arm/lpc17xx_40xx/lincoln60/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lincoln60/configs/nsh/defconfig @@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=7982 CONFIG_FS_FAT=y CONFIG_LPC17_40_SSP0=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/lpc17xx_40xx/lincoln60/configs/thttpd-binfs/defconfig b/boards/arm/lpc17xx_40xx/lincoln60/configs/thttpd-binfs/defconfig index dbbaceeeee8..7906130dd86 100644 --- a/boards/arm/lpc17xx_40xx/lincoln60/configs/thttpd-binfs/defconfig +++ b/boards/arm/lpc17xx_40xx/lincoln60/configs/thttpd-binfs/defconfig @@ -34,7 +34,6 @@ CONFIG_LPC17_40_ETH_NRXDESC=8 CONFIG_LPC17_40_ETH_NTXDESC=8 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/lpc17xx_40xx/lincoln60/scripts/Make.defs b/boards/arm/lpc17xx_40xx/lincoln60/scripts/Make.defs index fae787ff7ae..ef989576e06 100644 --- a/boards/arm/lpc17xx_40xx/lincoln60/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/lincoln60/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/lincoln60/src/lpc17_40_leds.c b/boards/arm/lpc17xx_40xx/lincoln60/src/lpc17_40_leds.c index 72fb53cab32..c7ce1ee400a 100644 --- a/boards/arm/lpc17xx_40xx/lincoln60/src/lpc17_40_leds.c +++ b/boards/arm/lpc17xx_40xx/lincoln60/src/lpc17_40_leds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/knsh/Make.defs b/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/knsh/Make.defs index 509ac387de4..d6009d86025 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/knsh/Make.defs +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/knsh/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/knsh/defconfig b/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/knsh/defconfig index 967e9c9cb4c..f27ff57bfd4 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/knsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/knsh/defconfig @@ -31,7 +31,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPC17_40_GPDMA=y CONFIG_LPC17_40_SDCARD=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=2 @@ -57,7 +56,7 @@ CONFIG_START_MONTH=3 CONFIG_START_YEAR=2013 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/nsh/defconfig index ec4f1e0b664..28826f10e97 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/configs/nsh/defconfig @@ -40,7 +40,6 @@ CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_SDCARD=y CONFIG_LPC17_40_UART0=y CONFIG_LPC17_40_UART1=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=2 @@ -53,7 +52,6 @@ CONFIG_NETUTILS_TELNETD=y CONFIG_NETUTILS_WEBSERVER=y CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_NOTIFIER=y CONFIG_NET_TCP_WRITE_BUFFERS=y diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/kernel/Makefile b/boards/arm/lpc17xx_40xx/lpc4088-devkit/kernel/Makefile index a302099439c..1d8508c0e9d 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/kernel/Makefile +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/kernel/lpc17_40_userspace.c b/boards/arm/lpc17xx_40xx/lpc4088-devkit/kernel/lpc17_40_userspace.c index 3e7a9d4a01e..2af4c85cfb4 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/kernel/lpc17_40_userspace.c +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/kernel/lpc17_40_userspace.c @@ -94,15 +94,10 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ -#ifndef CONFIG_DISABLE_SIGNALS .signal_handler = up_signal_handler, -#endif /* User-space work queue support (declared in include/nuttx/wqueue.h) */ diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/scripts/Make.defs b/boards/arm/lpc17xx_40xx/lpc4088-devkit/scripts/Make.defs index 7989f3e0c2a..dfab088e070 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/src/lpc17_40_autoleds.c b/boards/arm/lpc17xx_40xx/lpc4088-devkit/src/lpc17_40_autoleds.c index a461f5b9b66..194407f75c8 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/src/lpc17_40_autoleds.c +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/src/lpc17_40_autoleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/src/lpc17_40_ssp.c b/boards/arm/lpc17xx_40xx/lpc4088-devkit/src/lpc17_40_ssp.c index 2c93f768103..c780044ac9e 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/src/lpc17_40_ssp.c +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/src/lpc17_40_ssp.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/README.txt b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/README.txt index 4db4bba4e3b..44d36da0f2f 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/README.txt +++ b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/README.txt @@ -413,9 +413,6 @@ Configuration Directories CONFIG_LPC17_40_GPIOIRQ=y : GPIO interrupt support CONFIG_LPC17_40_SSP1=y : Enable support for SSP1 - RTOS Features: - CONFIG_DISABLE_SIGNALS=n : Signals are required - Library Support: CONFIG_SCHED_WORKQUEUE=y : Work queue support required diff --git a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/knsh/Make.defs b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/knsh/Make.defs index ab5c3c6ef8c..7102da2eb7a 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/knsh/Make.defs +++ b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/knsh/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/knsh/defconfig b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/knsh/defconfig index 72cfa7c1b64..b510a57c276 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/knsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/knsh/defconfig @@ -30,7 +30,6 @@ CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y CONFIG_LPC17_40_GPDMA=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_DISABLE_DD=y CONFIG_NSH_DISABLE_LOSETUP=y @@ -53,7 +52,7 @@ CONFIG_START_MONTH=3 CONFIG_START_YEAR=2013 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/nsh/defconfig index 3c0d1bdf213..60e07726716 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y CONFIG_LPC17_40_GPDMA=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/kernel/Makefile b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/kernel/Makefile index 4f5babefe3f..53b2b48a72a 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/kernel/Makefile +++ b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/kernel/lpc17_40_userspace.c b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/kernel/lpc17_40_userspace.c index e7aac7431a5..4f5c33cd104 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/kernel/lpc17_40_userspace.c +++ b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/kernel/lpc17_40_userspace.c @@ -94,15 +94,10 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ -#ifndef CONFIG_DISABLE_SIGNALS .signal_handler = up_signal_handler, -#endif /* User-space work queue support (declared in include/nuttx/wqueue.h) */ diff --git a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/scripts/Make.defs b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/scripts/Make.defs index d5b6572572d..e50770b0025 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/dhcpd/defconfig b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/dhcpd/defconfig index ad19dc1e795..eb204b158ca 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/dhcpd/defconfig +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/dhcpd/defconfig @@ -26,7 +26,6 @@ CONFIG_LPC17_40_EMACRAM_SIZE=15776 CONFIG_LPC17_40_ETHERNET=y CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_UART3=y -CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_DHCPD=y diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/nsh/defconfig index ed5d9852bda..6786061f92f 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_LPC17_40_ETH_NTXDESC=6 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_SSP1=y CONFIG_LPC17_40_UART3=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_REGIONS=2 CONFIG_MTD=y diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/nx/defconfig b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/nx/defconfig index e6d48a1b0a9..d370aded3b7 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/nx/defconfig +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/nx/defconfig @@ -35,7 +35,6 @@ CONFIG_LCD_MAXPOWER=2 CONFIG_LCD_UG9664HSWAG01=y CONFIG_LPC17_40_SSP1=y CONFIG_LPC17_40_UART3=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/thttpd/Make.defs b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/thttpd/Make.defs index 2c890cbc08e..abd5dc35ea4 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/thttpd/Make.defs +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/thttpd/Make.defs @@ -54,7 +54,7 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) $(NXFLATLDSCRIPT) -no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/thttpd/defconfig b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/thttpd/defconfig index 55a9eab9302..5ebf896c810 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/thttpd/defconfig +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/thttpd/defconfig @@ -26,7 +26,6 @@ CONFIG_LPC17_40_EMACRAM_SIZE=15776 CONFIG_LPC17_40_ETHERNET=y CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_UART3=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/usbmsc/defconfig b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/usbmsc/defconfig index 09af8a87d5a..46bf3e73827 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/usbmsc/defconfig +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/configs/usbmsc/defconfig @@ -23,7 +23,6 @@ CONFIG_LPC17_40_USBDEV=y CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS=0 CONFIG_LPC17_40_USBDEV_NOLED=y CONFIG_LPC17_40_USBDEV_NOVBUS=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/scripts/Make.defs b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/scripts/Make.defs index 2b84f93d64a..f802798f3a0 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/README.txt b/boards/arm/lpc17xx_40xx/lx_cpu/README.txt index 747163cbff4..8bd9a4b8c77 100644 --- a/boards/arm/lpc17xx_40xx/lx_cpu/README.txt +++ b/boards/arm/lpc17xx_40xx/lx_cpu/README.txt @@ -309,9 +309,6 @@ CONFIGURATION CONFIG_GPIO_IRQ=y : GPIO interrupt support CONFIG_LPC17_SSP1=y : Enable support for SSP1 - RTOS Features: - CONFIG_DISABLE_SIGNALS=n : Signals are required - Library Support: CONFIG_SCHED_WORKQUEUE=y : Work queue support required diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig index bde277413b8..0878b9d3790 100644 --- a/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig @@ -91,7 +91,6 @@ CONFIG_LPC17_40_UART0=y CONFIG_LPC17_40_USBDEV=y CONFIG_LPC17_40_USBHOST=y CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=3 @@ -119,7 +118,6 @@ CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_KEEPALIVE=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y -CONFIG_NET_UDP_BINDTODEVICE=y CONFIG_NET_UDP_CHECKSUMS=y CONFIG_NFS=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/Make.defs b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/Make.defs index d0f8651969f..de893534d8f 100644 --- a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/Make.defs @@ -63,8 +63,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/lpc17xx_40xx/mbed/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/mbed/configs/nsh/defconfig index 69e0da39058..34e4100bd99 100644 --- a/boards/arm/lpc17xx_40xx/mbed/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/mbed/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_BOARD_LOOPSPERMSEC=7982 CONFIG_FS_FAT=y CONFIG_LPC17_40_SSP0=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/mbed/configs/userled/defconfig b/boards/arm/lpc17xx_40xx/mbed/configs/userled/defconfig index 3a2b69ddcaa..7518947a2e3 100644 --- a/boards/arm/lpc17xx_40xx/mbed/configs/userled/defconfig +++ b/boards/arm/lpc17xx_40xx/mbed/configs/userled/defconfig @@ -27,7 +27,6 @@ CONFIG_EXAMPLES_LEDS=y CONFIG_FS_FAT=y CONFIG_LPC17_40_SSP0=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/mbed/scripts/Make.defs b/boards/arm/lpc17xx_40xx/mbed/scripts/Make.defs index 42fe32c2038..30debf46edf 100644 --- a/boards/arm/lpc17xx_40xx/mbed/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/mbed/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/mcb1700/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/mcb1700/configs/nsh/defconfig index d2975807429..65657abb7f7 100644 --- a/boards/arm/lpc17xx_40xx/mcb1700/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/mcb1700/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BOARD_LOOPSPERMSEC=7982 CONFIG_FS_FAT=y CONFIG_LPC17_40_SSP0=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/mcb1700/scripts/Make.defs b/boards/arm/lpc17xx_40xx/mcb1700/scripts/Make.defs index ecbc67a995a..1741c806168 100644 --- a/boards/arm/lpc17xx_40xx/mcb1700/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/mcb1700/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/mcb1700/src/lpc17_40_bringup.c b/boards/arm/lpc17xx_40xx/mcb1700/src/lpc17_40_bringup.c index 6bd1af5a597..db0356bda91 100644 --- a/boards/arm/lpc17xx_40xx/mcb1700/src/lpc17_40_bringup.c +++ b/boards/arm/lpc17xx_40xx/mcb1700/src/lpc17_40_bringup.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/ftpc/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/ftpc/defconfig index 8b2733694c3..8b4b8a75364 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/ftpc/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/ftpc/defconfig @@ -32,7 +32,6 @@ CONFIG_LPC17_40_ETH_NTXDESC=7 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_SSP1=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_REGIONS=2 CONFIG_NET=y @@ -44,7 +43,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_MAX_LISTENPORTS=8 -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_CONNS=16 diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/hidkbd/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/hidkbd/defconfig index 61c6c075e6c..b899c92f8cd 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/hidkbd/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/hidkbd/defconfig @@ -28,7 +28,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPC17_40_UART0=y CONFIG_LPC17_40_USBHOST=y CONFIG_LPC17_40_USBHOST_TDBUFFERS=3 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/hidmouse/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/hidmouse/defconfig index e05d75a8ea3..4bd984b2249 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/hidmouse/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/hidmouse/defconfig @@ -30,7 +30,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPC17_40_ETHERNET=y CONFIG_LPC17_40_UART0=y CONFIG_LPC17_40_USBHOST=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_NOADDR=y diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/nettest/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/nettest/defconfig index 992203a913b..36cc7bc95cd 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/nettest/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/nettest/defconfig @@ -30,7 +30,6 @@ CONFIG_LPC17_40_ETH_NRXDESC=6 CONFIG_LPC17_40_ETH_NTXDESC=6 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/nsh/defconfig index 8dbe7cbd27d..62f35a6241d 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/nsh/defconfig @@ -36,7 +36,6 @@ CONFIG_LPC17_40_ETH_NTXDESC=6 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_SSP1=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/slip-httpd/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/slip-httpd/defconfig index ef33278eace..a60fae3dc16 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/slip-httpd/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/slip-httpd/defconfig @@ -24,7 +24,6 @@ CONFIG_FS_ROMFS=y CONFIG_INTELHEX_BINARY=y CONFIG_LPC17_40_UART0=y CONFIG_LPC17_40_UART1=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-binfs/Make.defs b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-binfs/Make.defs index 7ca9f26372e..71c32dc40c3 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-binfs/Make.defs +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-binfs/Make.defs @@ -52,8 +52,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-binfs/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-binfs/defconfig index 7aebd66a146..d5cc527469e 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-binfs/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-binfs/defconfig @@ -30,7 +30,6 @@ CONFIG_LPC17_40_EMACRAM_SIZE=15776 CONFIG_LPC17_40_ETHERNET=y CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-nxflat/Make.defs b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-nxflat/Make.defs index 9197886efc1..64771cca9fd 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-nxflat/Make.defs +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-nxflat/Make.defs @@ -52,8 +52,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-nxflat/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-nxflat/defconfig index 4ec31128e5c..378f9bd9582 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-nxflat/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/thttpd-nxflat/defconfig @@ -27,7 +27,6 @@ CONFIG_LPC17_40_EMACRAM_SIZE=15776 CONFIG_LPC17_40_ETHERNET=y CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/usbmsc/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/usbmsc/defconfig index fe404255776..4dfb4f6c37e 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/usbmsc/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/usbmsc/defconfig @@ -24,7 +24,6 @@ CONFIG_LPC17_40_SSP1=y CONFIG_LPC17_40_UART0=y CONFIG_LPC17_40_USBDEV=y CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS=0 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/usbserial/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/usbserial/defconfig index b3d345a782f..11cede94523 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/usbserial/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/usbserial/defconfig @@ -22,7 +22,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_LPC17_40_UART0=y CONFIG_LPC17_40_USBDEV=y CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS=0 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PL2303=y CONFIG_PL2303_EPBULKIN=5 diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/zmodem/defconfig b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/zmodem/defconfig index b465a27fc9f..2257c90b38e 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/zmodem/defconfig +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/configs/zmodem/defconfig @@ -35,7 +35,6 @@ CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_SSP1=y CONFIG_LPC17_40_UART0=y CONFIG_LPC17_40_UART1=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/scripts/Make.defs b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/scripts/Make.defs index 174806f09b8..f72b0042c73 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/scripts/Make.defs @@ -52,8 +52,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/src/lpc17_40_bringup.c b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/src/lpc17_40_bringup.c index deb1e7e08bd..d8273a881f9 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/src/lpc17_40_bringup.c +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/src/lpc17_40_bringup.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/src/lpc17_40_leds.c b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/src/lpc17_40_leds.c index 12852d19c63..f445b4b06ea 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/src/lpc17_40_leds.c +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/src/lpc17_40_leds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/fb/defconfig b/boards/arm/lpc17xx_40xx/open1788/configs/fb/defconfig index 31f42a29a4c..5c6dcde02f6 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/fb/defconfig +++ b/boards/arm/lpc17xx_40xx/open1788/configs/fb/defconfig @@ -27,7 +27,6 @@ CONFIG_LPC17_40_GPDMA=y CONFIG_LPC17_40_LCD=y CONFIG_LPC17_40_SDCARD=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=3 diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/knsh/Make.defs b/boards/arm/lpc17xx_40xx/open1788/configs/knsh/Make.defs index c6257507f03..55cefa438ae 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/knsh/Make.defs +++ b/boards/arm/lpc17xx_40xx/open1788/configs/knsh/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/knsh/defconfig b/boards/arm/lpc17xx_40xx/open1788/configs/knsh/defconfig index d32e086df22..6dd104845a3 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/knsh/defconfig +++ b/boards/arm/lpc17xx_40xx/open1788/configs/knsh/defconfig @@ -31,7 +31,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPC17_40_GPDMA=y CONFIG_LPC17_40_SDCARD=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=2 @@ -57,7 +56,7 @@ CONFIG_START_MONTH=3 CONFIG_START_YEAR=2013 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/knxterm/Make.defs b/boards/arm/lpc17xx_40xx/open1788/configs/knxterm/Make.defs index 74bacf090a0..9d8f6f1344a 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/knxterm/Make.defs +++ b/boards/arm/lpc17xx_40xx/open1788/configs/knxterm/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/knxterm/defconfig b/boards/arm/lpc17xx_40xx/open1788/configs/knxterm/defconfig index adbc0748d82..540c9d82652 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/knxterm/defconfig +++ b/boards/arm/lpc17xx_40xx/open1788/configs/knxterm/defconfig @@ -34,7 +34,6 @@ CONFIG_LPC17_40_LCD=y CONFIG_LPC17_40_LCD_BPP16=y CONFIG_LPC17_40_SDCARD=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=3 @@ -67,7 +66,7 @@ CONFIG_START_MONTH=3 CONFIG_START_YEAR=2019 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_CLE=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nxterm_main" diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/open1788/configs/nsh/defconfig index 4062444918d..74e05010060 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/open1788/configs/nsh/defconfig @@ -28,7 +28,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LPC17_40_GPDMA=y CONFIG_LPC17_40_SDCARD=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/nxlines/defconfig b/boards/arm/lpc17xx_40xx/open1788/configs/nxlines/defconfig index 4f362a3eb23..7938c37150a 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/nxlines/defconfig +++ b/boards/arm/lpc17xx_40xx/open1788/configs/nxlines/defconfig @@ -29,7 +29,6 @@ CONFIG_LPC17_40_GPDMA=y CONFIG_LPC17_40_LCD=y CONFIG_LPC17_40_SDCARD=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=3 diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/pdcurses/defconfig b/boards/arm/lpc17xx_40xx/open1788/configs/pdcurses/defconfig index db79cf970b7..5ce255b41b9 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/pdcurses/defconfig +++ b/boards/arm/lpc17xx_40xx/open1788/configs/pdcurses/defconfig @@ -36,7 +36,6 @@ CONFIG_LPC17_40_GPIOIRQ=y CONFIG_LPC17_40_LCD=y CONFIG_LPC17_40_SDCARD=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=3 diff --git a/boards/arm/lpc17xx_40xx/open1788/configs/pwfb/defconfig b/boards/arm/lpc17xx_40xx/open1788/configs/pwfb/defconfig index d334ef86ea1..f2710c4fddb 100644 --- a/boards/arm/lpc17xx_40xx/open1788/configs/pwfb/defconfig +++ b/boards/arm/lpc17xx_40xx/open1788/configs/pwfb/defconfig @@ -37,7 +37,6 @@ CONFIG_LPC17_40_GPDMA=y CONFIG_LPC17_40_LCD=y CONFIG_LPC17_40_LCD_BPP16=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/lpc17xx_40xx/open1788/kernel/Makefile b/boards/arm/lpc17xx_40xx/open1788/kernel/Makefile index fc2210758f7..44fb00071d1 100644 --- a/boards/arm/lpc17xx_40xx/open1788/kernel/Makefile +++ b/boards/arm/lpc17xx_40xx/open1788/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/lpc17xx_40xx/open1788/kernel/lpc17_40_userspace.c b/boards/arm/lpc17xx_40xx/open1788/kernel/lpc17_40_userspace.c index a09ab2d9b16..09450eca6b1 100644 --- a/boards/arm/lpc17xx_40xx/open1788/kernel/lpc17_40_userspace.c +++ b/boards/arm/lpc17xx_40xx/open1788/kernel/lpc17_40_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/lpc17xx_40xx/open1788/scripts/Make.defs b/boards/arm/lpc17xx_40xx/open1788/scripts/Make.defs index 24653b9afb9..e8404f22db3 100644 --- a/boards/arm/lpc17xx_40xx/open1788/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/open1788/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/pnev5180b/configs/knsh/Make.defs b/boards/arm/lpc17xx_40xx/pnev5180b/configs/knsh/Make.defs index 11c597e5d3a..a5ee3a2611f 100644 --- a/boards/arm/lpc17xx_40xx/pnev5180b/configs/knsh/Make.defs +++ b/boards/arm/lpc17xx_40xx/pnev5180b/configs/knsh/Make.defs @@ -56,8 +56,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/pnev5180b/configs/knsh/defconfig b/boards/arm/lpc17xx_40xx/pnev5180b/configs/knsh/defconfig index 2d1f6cb0bd9..542c60bac48 100644 --- a/boards/arm/lpc17xx_40xx/pnev5180b/configs/knsh/defconfig +++ b/boards/arm/lpc17xx_40xx/pnev5180b/configs/knsh/defconfig @@ -21,6 +21,6 @@ CONFIG_PASS1_BUILDIR="boards/arm/lpc17xx_40xx/pnev5180b/kernel" CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x10000000 CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/lpc17xx_40xx/pnev5180b/kernel/Makefile b/boards/arm/lpc17xx_40xx/pnev5180b/kernel/Makefile index 727ba43abc7..af6f307f1b5 100644 --- a/boards/arm/lpc17xx_40xx/pnev5180b/kernel/Makefile +++ b/boards/arm/lpc17xx_40xx/pnev5180b/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/lpc17xx_40xx/pnev5180b/kernel/lpc17_40_userspace.c b/boards/arm/lpc17xx_40xx/pnev5180b/kernel/lpc17_40_userspace.c index 21b4c189339..8a8451c4a34 100644 --- a/boards/arm/lpc17xx_40xx/pnev5180b/kernel/lpc17_40_userspace.c +++ b/boards/arm/lpc17xx_40xx/pnev5180b/kernel/lpc17_40_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/lpc17xx_40xx/pnev5180b/scripts/Make.defs b/boards/arm/lpc17xx_40xx/pnev5180b/scripts/Make.defs index d11368cb471..9abcc6d2a98 100644 --- a/boards/arm/lpc17xx_40xx/pnev5180b/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/pnev5180b/scripts/Make.defs @@ -75,8 +75,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/u-blox-c027/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/u-blox-c027/configs/nsh/defconfig index 7427d733bb1..ffe30bd2675 100644 --- a/boards/arm/lpc17xx_40xx/u-blox-c027/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/u-blox-c027/configs/nsh/defconfig @@ -49,7 +49,6 @@ CONFIG_LPC17_40_UART1=y CONFIG_LPC17_40_UART1_RINGINDICATOR=y CONFIG_LPC17_40_UART2=y CONFIG_LPC17_40_UART3=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MODEM=y CONFIG_MODEM_U_BLOX=y diff --git a/boards/arm/lpc17xx_40xx/u-blox-c027/scripts/Make.defs b/boards/arm/lpc17xx_40xx/u-blox-c027/scripts/Make.defs index f95ffe2e2f6..227b9f0f737 100644 --- a/boards/arm/lpc17xx_40xx/u-blox-c027/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/u-blox-c027/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc17xx_40xx/u-blox-c027/src/lpc17_40_ubxmdm.c b/boards/arm/lpc17xx_40xx/u-blox-c027/src/lpc17_40_ubxmdm.c index edc2d1cc7e5..201a4a40727 100644 --- a/boards/arm/lpc17xx_40xx/u-blox-c027/src/lpc17_40_ubxmdm.c +++ b/boards/arm/lpc17xx_40xx/u-blox-c027/src/lpc17_40_ubxmdm.c @@ -43,6 +43,8 @@ #include #include #include +#include +#include #include #include diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/hello/defconfig b/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/hello/defconfig index 244b1d31c2e..2905037bd13 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/hello/defconfig +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/hello/defconfig @@ -27,7 +27,6 @@ CONFIG_LPC17_40_EMACRAM_SIZE=15776 CONFIG_LPC17_40_ETHERNET=y CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NET_ICMP=y diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/nsh/defconfig index dffa92ffc95..97c91f7d1c0 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/nsh/defconfig @@ -36,7 +36,6 @@ CONFIG_LPC17_40_ETH_NTXDESC=6 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_SPI=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/nxhello/defconfig b/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/nxhello/defconfig index da5de233d52..819d4873197 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/nxhello/defconfig +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/nxhello/defconfig @@ -43,7 +43,6 @@ CONFIG_LPC17_40_ETH_NTXDESC=6 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_SSP0=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MM_REGIONS=2 diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/thttpd/defconfig b/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/thttpd/defconfig index 3f57185892a..3a37cce3111 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/thttpd/defconfig +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/configs/thttpd/defconfig @@ -30,7 +30,6 @@ CONFIG_LPC17_40_ETH_NRXDESC=18 CONFIG_LPC17_40_ETH_NTXDESC=18 CONFIG_LPC17_40_PHY_AUTONEG=y CONFIG_LPC17_40_UART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/scripts/Make.defs b/boards/arm/lpc17xx_40xx/zkit-arm-1769/scripts/Make.defs index 9b947e10001..d61858b7133 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/scripts/Make.defs +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/scripts/Make.defs @@ -75,7 +75,7 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) $(NXFLATLDSCRIPT) -no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/lpc214x/mcu123-lpc214x/configs/composite/defconfig b/boards/arm/lpc214x/mcu123-lpc214x/configs/composite/defconfig index 9da1e9cb9fc..7c2e9c0986a 100644 --- a/boards/arm/lpc214x/mcu123-lpc214x/configs/composite/defconfig +++ b/boards/arm/lpc214x/mcu123-lpc214x/configs/composite/defconfig @@ -31,7 +31,6 @@ CONFIG_COMPOSITE_VERSIONNO=0x0101 CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/lpc214x/mcu123-lpc214x/configs/nsh/defconfig b/boards/arm/lpc214x/mcu123-lpc214x/configs/nsh/defconfig index 306d105ab83..165b0509494 100644 --- a/boards/arm/lpc214x/mcu123-lpc214x/configs/nsh/defconfig +++ b/boards/arm/lpc214x/mcu123-lpc214x/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/lpc214x/mcu123-lpc214x/configs/usbmsc/defconfig b/boards/arm/lpc214x/mcu123-lpc214x/configs/usbmsc/defconfig index 5a700917fc2..6a9dc474775 100644 --- a/boards/arm/lpc214x/mcu123-lpc214x/configs/usbmsc/defconfig +++ b/boards/arm/lpc214x/mcu123-lpc214x/configs/usbmsc/defconfig @@ -19,7 +19,6 @@ CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=3270 CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=32768 diff --git a/boards/arm/lpc214x/mcu123-lpc214x/configs/usbserial/defconfig b/boards/arm/lpc214x/mcu123-lpc214x/configs/usbserial/defconfig index 58d3fc6a19d..26aa1ec1870 100644 --- a/boards/arm/lpc214x/mcu123-lpc214x/configs/usbserial/defconfig +++ b/boards/arm/lpc214x/mcu123-lpc214x/configs/usbserial/defconfig @@ -19,7 +19,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_EXAMPLES_USBSERIAL=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_PL2303=y CONFIG_PL2303_EPBULKIN=5 CONFIG_PL2303_PRODUCTSTR="USBdev Serial" diff --git a/boards/arm/lpc214x/mcu123-lpc214x/scripts/Make.defs b/boards/arm/lpc214x/mcu123-lpc214x/scripts/Make.defs index e5a2e7b544b..1388a45e804 100644 --- a/boards/arm/lpc214x/mcu123-lpc214x/scripts/Make.defs +++ b/boards/arm/lpc214x/mcu123-lpc214x/scripts/Make.defs @@ -74,10 +74,10 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld \ - -no-check-sections + -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc214x/mcu123-lpc214x/src/lpc2148_composite.c b/boards/arm/lpc214x/mcu123-lpc214x/src/lpc2148_composite.c index 17b8e9fb34d..320371f5c7c 100644 --- a/boards/arm/lpc214x/mcu123-lpc214x/src/lpc2148_composite.c +++ b/boards/arm/lpc214x/mcu123-lpc214x/src/lpc2148_composite.c @@ -25,7 +25,8 @@ #include #include -#include +#include +#include #include #include diff --git a/boards/arm/lpc214x/zp214xpa/configs/nsh/defconfig b/boards/arm/lpc214x/zp214xpa/configs/nsh/defconfig index 51eb43c3298..aaa6833298c 100644 --- a/boards/arm/lpc214x/zp214xpa/configs/nsh/defconfig +++ b/boards/arm/lpc214x/zp214xpa/configs/nsh/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_LPC214X=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=3270 CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_MAX_TASKS=16 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y diff --git a/boards/arm/lpc214x/zp214xpa/configs/nxlines/defconfig b/boards/arm/lpc214x/zp214xpa/configs/nxlines/defconfig index 9f49010b48d..4091a7d2cc0 100644 --- a/boards/arm/lpc214x/zp214xpa/configs/nxlines/defconfig +++ b/boards/arm/lpc214x/zp214xpa/configs/nxlines/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=255 CONFIG_LCD_UG2864AMBAG01=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y CONFIG_NXFONT_MONO5X8=y diff --git a/boards/arm/lpc214x/zp214xpa/scripts/Make.defs b/boards/arm/lpc214x/zp214xpa/scripts/Make.defs index b27872a4bd9..ce915cc53c7 100644 --- a/boards/arm/lpc214x/zp214xpa/scripts/Make.defs +++ b/boards/arm/lpc214x/zp214xpa/scripts/Make.defs @@ -74,10 +74,10 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld \ - -no-check-sections + -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc2378/olimex-lpc2378/configs/nsh/defconfig b/boards/arm/lpc2378/olimex-lpc2378/configs/nsh/defconfig index e2e6a92923f..18f35ff3b91 100644 --- a/boards/arm/lpc2378/olimex-lpc2378/configs/nsh/defconfig +++ b/boards/arm/lpc2378/olimex-lpc2378/configs/nsh/defconfig @@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=3270 CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_LPC2378_UART0=y CONFIG_LPC2378_UART2=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y diff --git a/boards/arm/lpc2378/olimex-lpc2378/scripts/Make.defs b/boards/arm/lpc2378/olimex-lpc2378/scripts/Make.defs index e8a4a187d74..58eb123d3c8 100644 --- a/boards/arm/lpc2378/olimex-lpc2378/scripts/Make.defs +++ b/boards/arm/lpc2378/olimex-lpc2378/scripts/Make.defs @@ -94,10 +94,10 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld \ - -no-check-sections + -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc31xx/ea3131/configs/nsh/defconfig b/boards/arm/lpc31xx/ea3131/configs/nsh/defconfig index d5c0e61fdad..f5ad78ddd40 100644 --- a/boards/arm/lpc31xx/ea3131/configs/nsh/defconfig +++ b/boards/arm/lpc31xx/ea3131/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_BOOT_RUNFROMISRAM=y CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_LPC31_UART=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/lpc31xx/ea3131/configs/pgnsh/Make.defs b/boards/arm/lpc31xx/ea3131/configs/pgnsh/Make.defs index b2c4f0c6bca..1a02f3f0941 100644 --- a/boards/arm/lpc31xx/ea3131/configs/pgnsh/Make.defs +++ b/boards/arm/lpc31xx/ea3131/configs/pgnsh/Make.defs @@ -66,8 +66,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CONFIG_ARM_TOOLCHAIN_BUILDROOT),y) diff --git a/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig b/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig index b29e703c82b..8264bac8a65 100644 --- a/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig +++ b/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig @@ -24,7 +24,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_LPC31_SPI=y CONFIG_LPC31_UART=y CONFIG_M25P_SPIMODE=3 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MTD=y CONFIG_MTD_M25P=y @@ -40,7 +39,7 @@ CONFIG_PAGING_NVPAGED=384 CONFIG_PAGING_PAGESIZE=1024 CONFIG_PAGING_STACKSIZE=2048 CONFIG_PASS1_BUILDIR="boards/arm/lpc31xx/ea3131/locked" -CONFIG_PASS1_OBJECT="locked.r" +CONFIG_PASS1_OBJECT="-Wl,locked.r" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=196608 CONFIG_RAM_START=0x11028000 diff --git a/boards/arm/lpc31xx/ea3131/configs/usbserial/defconfig b/boards/arm/lpc31xx/ea3131/configs/usbserial/defconfig index 0bb5da031b8..d93ba4074ee 100644 --- a/boards/arm/lpc31xx/ea3131/configs/usbserial/defconfig +++ b/boards/arm/lpc31xx/ea3131/configs/usbserial/defconfig @@ -23,7 +23,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_LIB_BOARDCTL=y CONFIG_LPC31_UART=y CONFIG_LPC31_USBOTG=y -CONFIG_MAX_TASKS=16 CONFIG_PL2303=y CONFIG_PL2303_EPBULKIN=1 CONFIG_PL2303_EPINTIN=3 diff --git a/boards/arm/lpc31xx/ea3131/locked/Makefile b/boards/arm/lpc31xx/ea3131/locked/Makefile index 98acb99a5c1..a7d835b54e6 100644 --- a/boards/arm/lpc31xx/ea3131/locked/Makefile +++ b/boards/arm/lpc31xx/ea3131/locked/Makefile @@ -76,7 +76,7 @@ $(PASS1_LIBBOARD): locked.r: ld-locked.inc $(PASS1_LIBBOARD) @echo "LD: locked.r" - $(Q) $(LD) -o $@ $(PASS1_LDFLAGS) $(PASS1_LIBPATHS) --start-group $(PASS1_LDLIBS) --end-group $(PASS1_LIBGCC) + $(Q) $(LD) -o $@ $(PASS1_LDFLAGS) $(PASS1_LIBPATHS) -Wl,--start-group $(PASS1_LDLIBS) -Wl,--end-group $(PASS1_LIBGCC) $(Q) $(NM) $@ > locked.map $(Q) fgrep " U " locked.map | grep -v nx_start $(Q) $(CROSSDEV)size $@ diff --git a/boards/arm/lpc31xx/ea3131/scripts/Make.defs b/boards/arm/lpc31xx/ea3131/scripts/Make.defs index d6c25ec0f48..352c266e4f8 100644 --- a/boards/arm/lpc31xx/ea3131/scripts/Make.defs +++ b/boards/arm/lpc31xx/ea3131/scripts/Make.defs @@ -66,8 +66,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CONFIG_ARM_TOOLCHAIN),BUILDROOT) diff --git a/boards/arm/lpc31xx/ea3131/scripts/pg-ld.script b/boards/arm/lpc31xx/ea3131/scripts/pg-ld.script index fe55efa64f3..f652adff5da 100644 --- a/boards/arm/lpc31xx/ea3131/scripts/pg-ld.script +++ b/boards/arm/lpc31xx/ea3131/scripts/pg-ld.script @@ -53,8 +53,8 @@ MEMORY { - locked (rx) : ORIGIN = 0x11029080, LENGTH = 48K - 4224 - paged (rx) : ORIGIN = 0x11034000, LENGTH = 384K + locked (rx) : ORIGIN = 0x11029080, LENGTH = 52K - 4224 + paged (rx) : ORIGIN = 0x11035000, LENGTH = 380K data (rw) : ORIGIN = 0x11094000, LENGTH = 44K } diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c b/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c index 37fad480f04..70b847bb03a 100644 --- a/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c +++ b/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/arm/lpc31xx/ea3152/configs/ostest/defconfig b/boards/arm/lpc31xx/ea3152/configs/ostest/defconfig index fb174d5c332..87a63fa3328 100644 --- a/boards/arm/lpc31xx/ea3152/configs/ostest/defconfig +++ b/boards/arm/lpc31xx/ea3152/configs/ostest/defconfig @@ -22,7 +22,6 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_HOST_WINDOWS=y CONFIG_LPC31_UART=y -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=196608 CONFIG_RAM_START=0x11028000 diff --git a/boards/arm/lpc31xx/ea3152/scripts/Make.defs b/boards/arm/lpc31xx/ea3152/scripts/Make.defs index ff95e629180..a60904abcf2 100644 --- a/boards/arm/lpc31xx/ea3152/scripts/Make.defs +++ b/boards/arm/lpc31xx/ea3152/scripts/Make.defs @@ -66,8 +66,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CONFIG_ARM_TOOLCHAIN_BUILDROOT),y) diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c b/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c index b4b5cb0619f..4c8987b6868 100644 --- a/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c +++ b/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/configs/nsh/defconfig b/boards/arm/lpc31xx/olimex-lpc-h3131/configs/nsh/defconfig index 12e3156bcfc..665868e5788 100644 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/configs/nsh/defconfig +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=768 CONFIG_LPC31_UART=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/scripts/Make.defs b/boards/arm/lpc31xx/olimex-lpc-h3131/scripts/Make.defs index 92291770453..7c959396970 100644 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/scripts/Make.defs +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/scripts/Make.defs @@ -66,8 +66,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CONFIG_ARM_TOOLCHAIN),BUILDROOT) diff --git a/boards/arm/lpc43xx/bambino-200e/configs/knsh/defconfig b/boards/arm/lpc43xx/bambino-200e/configs/knsh/defconfig index 153c52511cc..79011f3db29 100644 --- a/boards/arm/lpc43xx/bambino-200e/configs/knsh/defconfig +++ b/boards/arm/lpc43xx/bambino-200e/configs/knsh/defconfig @@ -29,7 +29,6 @@ CONFIG_LPC43_BOOT_SPIFI=y CONFIG_LPC43_TMR0=y CONFIG_LPC43_UART1=y CONFIG_LPC43_USB0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 @@ -49,7 +48,7 @@ CONFIG_START_MONTH=7 CONFIG_START_YEAR=2012 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_TIMER=y CONFIG_UART1_SERIAL_CONSOLE=y diff --git a/boards/arm/lpc43xx/bambino-200e/configs/max31855/defconfig b/boards/arm/lpc43xx/bambino-200e/configs/max31855/defconfig index 6bff204506b..4e2ded64c78 100644 --- a/boards/arm/lpc43xx/bambino-200e/configs/max31855/defconfig +++ b/boards/arm/lpc43xx/bambino-200e/configs/max31855/defconfig @@ -32,7 +32,6 @@ CONFIG_LPC43_SSP1=y CONFIG_LPC43_TMR0=y CONFIG_LPC43_UART1=y CONFIG_LPC43_USB0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc43xx/bambino-200e/configs/netnsh/Make.defs b/boards/arm/lpc43xx/bambino-200e/configs/netnsh/Make.defs index be09e9f7128..9f44b674191 100644 --- a/boards/arm/lpc43xx/bambino-200e/configs/netnsh/Make.defs +++ b/boards/arm/lpc43xx/bambino-200e/configs/netnsh/Make.defs @@ -91,8 +91,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 EXEEXT = .elf diff --git a/boards/arm/lpc43xx/bambino-200e/configs/netnsh/defconfig b/boards/arm/lpc43xx/bambino-200e/configs/netnsh/defconfig index 4fb7252d950..faec1298197 100644 --- a/boards/arm/lpc43xx/bambino-200e/configs/netnsh/defconfig +++ b/boards/arm/lpc43xx/bambino-200e/configs/netnsh/defconfig @@ -33,7 +33,6 @@ CONFIG_LPC43_PHYSR_ALTMODE=0x7 CONFIG_LPC43_TMR0=y CONFIG_LPC43_UART1=y CONFIG_LPC43_USB0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/lpc43xx/bambino-200e/configs/nsh/defconfig b/boards/arm/lpc43xx/bambino-200e/configs/nsh/defconfig index 8057bca6df5..fb5fa54b5d8 100644 --- a/boards/arm/lpc43xx/bambino-200e/configs/nsh/defconfig +++ b/boards/arm/lpc43xx/bambino-200e/configs/nsh/defconfig @@ -28,7 +28,6 @@ CONFIG_LPC43_BOOT_SPIFI=y CONFIG_LPC43_TMR0=y CONFIG_LPC43_UART1=y CONFIG_LPC43_USB0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc43xx/bambino-200e/configs/usbnsh/defconfig b/boards/arm/lpc43xx/bambino-200e/configs/usbnsh/defconfig index d76a81d2ae1..2dc1dd90bb9 100644 --- a/boards/arm/lpc43xx/bambino-200e/configs/usbnsh/defconfig +++ b/boards/arm/lpc43xx/bambino-200e/configs/usbnsh/defconfig @@ -26,7 +26,6 @@ CONFIG_LPC43_BOOT_SPIFI=y CONFIG_LPC43_TMR0=y CONFIG_LPC43_UART1=y CONFIG_LPC43_USB0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc43xx/bambino-200e/kernel/Makefile b/boards/arm/lpc43xx/bambino-200e/kernel/Makefile index c151e6bf144..379cbfd219b 100644 --- a/boards/arm/lpc43xx/bambino-200e/kernel/Makefile +++ b/boards/arm/lpc43xx/bambino-200e/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/lpc43xx/bambino-200e/kernel/lpc43_userspace.c b/boards/arm/lpc43xx/bambino-200e/kernel/lpc43_userspace.c index 72600e0cbc0..e59fd01c6f8 100644 --- a/boards/arm/lpc43xx/bambino-200e/kernel/lpc43_userspace.c +++ b/boards/arm/lpc43xx/bambino-200e/kernel/lpc43_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/lpc43xx/bambino-200e/scripts/Make.defs b/boards/arm/lpc43xx/bambino-200e/scripts/Make.defs index b74b9e79441..1c490862574 100644 --- a/boards/arm/lpc43xx/bambino-200e/scripts/Make.defs +++ b/boards/arm/lpc43xx/bambino-200e/scripts/Make.defs @@ -67,8 +67,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 EXEEXT = .elf diff --git a/boards/arm/lpc43xx/lpc4330-xplorer/configs/nsh/defconfig b/boards/arm/lpc43xx/lpc4330-xplorer/configs/nsh/defconfig index f49c7a79d9f..795d98f8bab 100644 --- a/boards/arm/lpc43xx/lpc4330-xplorer/configs/nsh/defconfig +++ b/boards/arm/lpc43xx/lpc4330-xplorer/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_LPC43_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/lpc43xx/lpc4330-xplorer/scripts/Make.defs b/boards/arm/lpc43xx/lpc4330-xplorer/scripts/Make.defs index 4391e501f08..6cb6d126bd4 100644 --- a/boards/arm/lpc43xx/lpc4330-xplorer/scripts/Make.defs +++ b/boards/arm/lpc43xx/lpc4330-xplorer/scripts/Make.defs @@ -67,8 +67,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc43xx/lpc4337-ws/configs/nsh/defconfig b/boards/arm/lpc43xx/lpc4337-ws/configs/nsh/defconfig index 924ac024814..d5442e45164 100644 --- a/boards/arm/lpc43xx/lpc4337-ws/configs/nsh/defconfig +++ b/boards/arm/lpc43xx/lpc4337-ws/configs/nsh/defconfig @@ -42,7 +42,6 @@ CONFIG_LPC43_SPIFI=y CONFIG_LPC43_SSP1=y CONFIG_LPC43_USART2=y CONFIG_LPC43_USB0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc43xx/lpc4337-ws/scripts/Make.defs b/boards/arm/lpc43xx/lpc4337-ws/scripts/Make.defs index f0b928cb03b..7d9fa028f4e 100644 --- a/boards/arm/lpc43xx/lpc4337-ws/scripts/Make.defs +++ b/boards/arm/lpc43xx/lpc4337-ws/scripts/Make.defs @@ -67,8 +67,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc43xx/lpc4357-evb/configs/nsh/defconfig b/boards/arm/lpc43xx/lpc4357-evb/configs/nsh/defconfig index 102db87de7e..dcf198442a3 100644 --- a/boards/arm/lpc43xx/lpc4357-evb/configs/nsh/defconfig +++ b/boards/arm/lpc43xx/lpc4357-evb/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_LPC43_BOOT_FLASHA=y CONFIG_LPC43_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/lpc43xx/lpc4357-evb/scripts/Make.defs b/boards/arm/lpc43xx/lpc4357-evb/scripts/Make.defs index 7e376c74daf..27c9de70ee0 100644 --- a/boards/arm/lpc43xx/lpc4357-evb/scripts/Make.defs +++ b/boards/arm/lpc43xx/lpc4357-evb/scripts/Make.defs @@ -67,8 +67,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc43xx/lpc4370-link2/configs/nsh/defconfig b/boards/arm/lpc43xx/lpc4370-link2/configs/nsh/defconfig index 3f44e2ece68..ab6bdf7db7f 100644 --- a/boards/arm/lpc43xx/lpc4370-link2/configs/nsh/defconfig +++ b/boards/arm/lpc43xx/lpc4370-link2/configs/nsh/defconfig @@ -39,7 +39,6 @@ CONFIG_LPC43_SPIFI=y CONFIG_LPC43_SSP1=y CONFIG_LPC43_USART2=y CONFIG_LPC43_USB0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc43xx/lpc4370-link2/scripts/Make.defs b/boards/arm/lpc43xx/lpc4370-link2/scripts/Make.defs index 24ece0a34b3..5531c7322ab 100644 --- a/boards/arm/lpc43xx/lpc4370-link2/scripts/Make.defs +++ b/boards/arm/lpc43xx/lpc4370-link2/scripts/Make.defs @@ -67,8 +67,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/fb/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/fb/defconfig index 9a7602399ff..3943b37617c 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/fb/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/fb/defconfig @@ -48,7 +48,6 @@ CONFIG_LPC54_LCD_VFRONTPORCH=4 CONFIG_LPC54_LCD_VPULSE=10 CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 CONFIG_LPC54_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/lvgl/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/lvgl/defconfig index 312df6db723..2513ff0e63b 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/lvgl/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/lvgl/defconfig @@ -48,7 +48,6 @@ CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 CONFIG_LPC54_USART0=y CONFIG_LV_HOR_RES=480 CONFIG_LV_VER_RES=272 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=163840 diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/netnsh/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/netnsh/defconfig index 3c15a105ede..23178acc139 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/netnsh/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/netnsh/defconfig @@ -31,7 +31,6 @@ CONFIG_LPC54_ETHERNET=y CONFIG_LPC54_ETH_PHYADDR=0 CONFIG_LPC54_GPIOIRQ=y CONFIG_LPC54_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETINIT_NOMAC=y diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/nsh/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/nsh/defconfig index 0f8c9e8a8f1..65c068deaa4 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/nsh/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/nsh/defconfig @@ -35,7 +35,6 @@ CONFIG_LPC54_GPIOIRQ=y CONFIG_LPC54_I2C2_MASTER=y CONFIG_LPC54_RTC=y CONFIG_LPC54_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/nxwm/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/nxwm/defconfig index a7de1a7af20..6b8c499c2b6 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/nxwm/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/nxwm/defconfig @@ -47,7 +47,6 @@ CONFIG_LPC54_LCD_VFRONTPORCH=4 CONFIG_LPC54_LCD_VPULSE=10 CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 CONFIG_LPC54_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/pwfb/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/pwfb/defconfig index 7b77885fcdc..3bae17b0a70 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/pwfb/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/pwfb/defconfig @@ -47,7 +47,6 @@ CONFIG_LPC54_LCD_VFRONTPORCH=4 CONFIG_LPC54_LCD_VPULSE=10 CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 CONFIG_LPC54_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/pwlines/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/pwlines/defconfig index c1b124a5750..b948525f24d 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/pwlines/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/pwlines/defconfig @@ -38,7 +38,6 @@ CONFIG_LPC54_LCD_VFRONTPORCH=4 CONFIG_LPC54_LCD_VPULSE=10 CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 CONFIG_LPC54_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/twm4nx1/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/twm4nx1/defconfig index 62a8a2d967c..a8a2a17b728 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/twm4nx1/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/twm4nx1/defconfig @@ -48,7 +48,6 @@ CONFIG_LPC54_LCD_VFRONTPORCH=4 CONFIG_LPC54_LCD_VPULSE=10 CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 CONFIG_LPC54_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/twm4nx2/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/twm4nx2/defconfig index b10028ef9b1..42b2eb59f8b 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/twm4nx2/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/twm4nx2/defconfig @@ -48,7 +48,6 @@ CONFIG_LPC54_LCD_VFRONTPORCH=4 CONFIG_LPC54_LCD_VPULSE=10 CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 CONFIG_LPC54_USART0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/scripts/Make.defs b/boards/arm/lpc54xx/lpcxpresso-lpc54628/scripts/Make.defs index d75e576cc0b..ed07e26d5fb 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/scripts/Make.defs +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/scripts/Make.defs @@ -53,8 +53,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_ft5x06.c b/boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_ft5x06.c index 44a48d1acdd..72a920c301e 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_ft5x06.c +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_ft5x06.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/max326xx/max32660-evsys/configs/nsh/defconfig b/boards/arm/max326xx/max32660-evsys/configs/nsh/defconfig index 7eefddc54b5..746fc1bf379 100644 --- a/boards/arm/max326xx/max32660-evsys/configs/nsh/defconfig +++ b/boards/arm/max326xx/max32660-evsys/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_BUILTIN=y CONFIG_FS_PROCFS=y CONFIG_INTELHEX_BINARY=y CONFIG_MAX326XX_UART1=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/max326xx/max32660-evsys/scripts/Make.defs b/boards/arm/max326xx/max32660-evsys/scripts/Make.defs index f333502b9da..eda5bede1b2 100644 --- a/boards/arm/max326xx/max32660-evsys/scripts/Make.defs +++ b/boards/arm/max326xx/max32660-evsys/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/moxart/moxa/configs/nsh/defconfig b/boards/arm/moxart/moxa/configs/nsh/defconfig index 6807079452f..31ad5378764 100644 --- a/boards/arm/moxart/moxa/configs/nsh/defconfig +++ b/boards/arm/moxart/moxa/configs/nsh/defconfig @@ -58,7 +58,6 @@ CONFIG_HAVE_CXX=y CONFIG_IOB_NBUFFERS=24 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_LONG_LONG=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETUTILS_TELNETD=y diff --git a/boards/arm/moxart/moxa/scripts/Make.defs b/boards/arm/moxart/moxa/scripts/Make.defs index 2a2b4b9ca8f..d76526e4f0d 100644 --- a/boards/arm/moxart/moxa/scripts/Make.defs +++ b/boards/arm/moxart/moxa/scripts/Make.defs @@ -52,8 +52,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ MKNXFLAT = mknxflat LDNXFLAT = ldnxflat -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/nrf52/nrf52-feather/configs/i2c/defconfig b/boards/arm/nrf52/nrf52-feather/configs/i2c/defconfig index bff6f9d695a..dc201db4124 100644 --- a/boards/arm/nrf52/nrf52-feather/configs/i2c/defconfig +++ b/boards/arm/nrf52/nrf52-feather/configs/i2c/defconfig @@ -23,7 +23,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_I2C=y CONFIG_I2C_POLLED=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_I2C0_MASTER=y CONFIG_NRF52_UART0=y diff --git a/boards/arm/nrf52/nrf52-feather/configs/nsh/defconfig b/boards/arm/nrf52/nrf52-feather/configs/nsh/defconfig index 08ad25ef18a..0e8f7d4a481 100644 --- a/boards/arm/nrf52/nrf52-feather/configs/nsh/defconfig +++ b/boards/arm/nrf52/nrf52-feather/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/nrf52/nrf52-feather/configs/userleds/defconfig b/boards/arm/nrf52/nrf52-feather/configs/userleds/defconfig index 0fe646fdb6e..f7735ca8da3 100644 --- a/boards/arm/nrf52/nrf52-feather/configs/userleds/defconfig +++ b/boards/arm/nrf52/nrf52-feather/configs/userleds/defconfig @@ -23,7 +23,6 @@ CONFIG_EXAMPLES_LEDS=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/nrf52/nrf52-feather/scripts/Make.defs b/boards/arm/nrf52/nrf52-feather/scripts/Make.defs index 3e861e618f8..d33d95f918e 100644 --- a/boards/arm/nrf52/nrf52-feather/scripts/Make.defs +++ b/boards/arm/nrf52/nrf52-feather/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/nrf52/nrf52832-dk/configs/nsh/defconfig b/boards/arm/nrf52/nrf52832-dk/configs/nsh/defconfig index 84e6f5911b8..583166a7eb2 100644 --- a/boards/arm/nrf52/nrf52832-dk/configs/nsh/defconfig +++ b/boards/arm/nrf52/nrf52832-dk/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/nrf52/nrf52832-dk/configs/wdog/defconfig b/boards/arm/nrf52/nrf52832-dk/configs/wdog/defconfig index 1ceb3a75efc..2781b06f6f9 100644 --- a/boards/arm/nrf52/nrf52832-dk/configs/wdog/defconfig +++ b/boards/arm/nrf52/nrf52832-dk/configs/wdog/defconfig @@ -22,7 +22,6 @@ CONFIG_EXAMPLES_WATCHDOG=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_UART0=y CONFIG_NRF52_WDT=y diff --git a/boards/arm/nrf52/nrf52832-dk/scripts/Make.defs b/boards/arm/nrf52/nrf52832-dk/scripts/Make.defs index 78cfeb7af62..0572eec751c 100644 --- a/boards/arm/nrf52/nrf52832-dk/scripts/Make.defs +++ b/boards/arm/nrf52/nrf52832-dk/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/nrf52/nrf52832-mdk/configs/nsh/defconfig b/boards/arm/nrf52/nrf52832-mdk/configs/nsh/defconfig index d6c7968f387..c018ab18799 100644 --- a/boards/arm/nrf52/nrf52832-mdk/configs/nsh/defconfig +++ b/boards/arm/nrf52/nrf52832-mdk/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/nrf52/nrf52832-mdk/configs/sdc/defconfig b/boards/arm/nrf52/nrf52832-mdk/configs/sdc/defconfig index 0bacbd548a1..7f97f26a000 100644 --- a/boards/arm/nrf52/nrf52832-mdk/configs/sdc/defconfig +++ b/boards/arm/nrf52/nrf52832-mdk/configs/sdc/defconfig @@ -34,7 +34,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/nrf52/nrf52832-mdk/scripts/Make.defs b/boards/arm/nrf52/nrf52832-mdk/scripts/Make.defs index dd9ef431d34..e621ba9c5d3 100644 --- a/boards/arm/nrf52/nrf52832-mdk/scripts/Make.defs +++ b/boards/arm/nrf52/nrf52832-mdk/scripts/Make.defs @@ -33,7 +33,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm @@ -64,8 +64,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/nrf52/nrf52832-sparkfun/configs/nsh/defconfig b/boards/arm/nrf52/nrf52832-sparkfun/configs/nsh/defconfig index 859dccada0b..7af6600787a 100644 --- a/boards/arm/nrf52/nrf52832-sparkfun/configs/nsh/defconfig +++ b/boards/arm/nrf52/nrf52832-sparkfun/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/nrf52/nrf52832-sparkfun/scripts/Make.defs b/boards/arm/nrf52/nrf52832-sparkfun/scripts/Make.defs index 2c2d74018ce..fd112697944 100644 --- a/boards/arm/nrf52/nrf52832-sparkfun/scripts/Make.defs +++ b/boards/arm/nrf52/nrf52832-sparkfun/scripts/Make.defs @@ -33,7 +33,7 @@ endif CC = $(CROSSDEV)gcc CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)gcc STRIP = $(CROSSDEV)strip --strip-unneeded AR = $(CROSSDEV)ar rcs NM = $(CROSSDEV)nm @@ -64,8 +64,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/nrf52/nrf52840-dk/configs/adc/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/adc/defconfig index d45d61957f6..7725055111c 100644 --- a/boards/arm/nrf52/nrf52840-dk/configs/adc/defconfig +++ b/boards/arm/nrf52/nrf52840-dk/configs/adc/defconfig @@ -26,7 +26,6 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_SAADC=y CONFIG_NRF52_UART0=y diff --git a/boards/arm/nrf52/nrf52840-dk/configs/highpri/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/highpri/defconfig index 0a66506acfe..6983bfdde53 100644 --- a/boards/arm/nrf52/nrf52840-dk/configs/highpri/defconfig +++ b/boards/arm/nrf52/nrf52840-dk/configs/highpri/defconfig @@ -22,7 +22,6 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52840DK_HIGHPRI=y CONFIG_NRF52_TIMER0=y diff --git a/boards/arm/nrf52/nrf52840-dk/configs/nsh/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/nsh/defconfig index 7e4f6bc7ea0..bb299173d0e 100644 --- a/boards/arm/nrf52/nrf52840-dk/configs/nsh/defconfig +++ b/boards/arm/nrf52/nrf52840-dk/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/nrf52/nrf52840-dk/configs/pwm/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/pwm/defconfig index 823c243b1ac..019944647e1 100644 --- a/boards/arm/nrf52/nrf52840-dk/configs/pwm/defconfig +++ b/boards/arm/nrf52/nrf52840-dk/configs/pwm/defconfig @@ -22,7 +22,6 @@ CONFIG_EXAMPLES_PWM=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_PWM0=y CONFIG_NRF52_PWM0_CH0=y diff --git a/boards/arm/nrf52/nrf52840-dk/configs/sx127x/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/sx127x/defconfig index edf3c6bc873..7d48d60e3b3 100644 --- a/boards/arm/nrf52/nrf52840-dk/configs/sx127x/defconfig +++ b/boards/arm/nrf52/nrf52840-dk/configs/sx127x/defconfig @@ -28,7 +28,6 @@ CONFIG_FS_FAT=y CONFIG_LPWAN_SX127X=y CONFIG_LPWAN_SX127X_RXSUPPORT=y CONFIG_LPWAN_SX127X_TXSUPPORT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_GPIOTE=y CONFIG_NRF52_SPI0_MASTER=y diff --git a/boards/arm/nrf52/nrf52840-dk/configs/timer/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/timer/defconfig index f875e0abff7..4d10f82aa7f 100644 --- a/boards/arm/nrf52/nrf52840-dk/configs/timer/defconfig +++ b/boards/arm/nrf52/nrf52840-dk/configs/timer/defconfig @@ -22,7 +22,6 @@ CONFIG_EXAMPLES_TIMER=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_RTC0=y CONFIG_NRF52_TIMER0=y diff --git a/boards/arm/nrf52/nrf52840-dk/scripts/Make.defs b/boards/arm/nrf52/nrf52840-dk/scripts/Make.defs index c6093b12012..3760058bc6b 100644 --- a/boards/arm/nrf52/nrf52840-dk/scripts/Make.defs +++ b/boards/arm/nrf52/nrf52840-dk/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c b/boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c index 391e8769dd6..2b409832c99 100644 --- a/boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c +++ b/boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/nrf52/nrf52840-dongle/configs/nsh/defconfig b/boards/arm/nrf52/nrf52840-dongle/configs/nsh/defconfig index a606af1a57f..879d8e87969 100644 --- a/boards/arm/nrf52/nrf52840-dongle/configs/nsh/defconfig +++ b/boards/arm/nrf52/nrf52840-dongle/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/nrf52/nrf52840-dongle/scripts/Make.defs b/boards/arm/nrf52/nrf52840-dongle/scripts/Make.defs index 431c39284c9..f94f8d1682d 100644 --- a/boards/arm/nrf52/nrf52840-dongle/scripts/Make.defs +++ b/boards/arm/nrf52/nrf52840-dongle/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/nuc1xx/nutiny-nuc120/configs/nsh/defconfig b/boards/arm/nuc1xx/nutiny-nuc120/configs/nsh/defconfig index 822d831c3c0..e051e1d8204 100644 --- a/boards/arm/nuc1xx/nutiny-nuc120/configs/nsh/defconfig +++ b/boards/arm/nuc1xx/nutiny-nuc120/configs/nsh/defconfig @@ -27,7 +27,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_DISABLE_CD=y diff --git a/boards/arm/nuc1xx/nutiny-nuc120/scripts/Make.defs b/boards/arm/nuc1xx/nutiny-nuc120/scripts/Make.defs index dc4b7f97d4d..c063d911496 100644 --- a/boards/arm/nuc1xx/nutiny-nuc120/scripts/Make.defs +++ b/boards/arm/nuc1xx/nutiny-nuc120/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/rp2040/common/include/rp2040_lcd_backpack.h b/boards/arm/rp2040/common/include/rp2040_lcd_backpack.h new file mode 100644 index 00000000000..1caf3107958 --- /dev/null +++ b/boards/arm/rp2040/common/include/rp2040_lcd_backpack.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/rp2040/common/include/rp2040_lcd_backpack.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __RP2040_LCD_BACKPACK_H +#define __RP2040_LCD_BACKPACK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_backpack_init + * + * Description: + * Initialize the LCD1602 display controlled by Backpack with PCF8574 + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/slcd0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_lcd_backpack_init(int devno, int busno, int rows, int cols); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __RP2040_LCD_BACKPACK_H */ diff --git a/boards/arm/rp2040/common/src/Make.defs b/boards/arm/rp2040/common/src/Make.defs index 68b28c314db..1b68a12ee41 100644 --- a/boards/arm/rp2040/common/src/Make.defs +++ b/boards/arm/rp2040/common/src/Make.defs @@ -38,6 +38,14 @@ ifeq ($(CONFIG_LCD_ST7789),y) CSRCS += rp2040_st7789.c endif +ifeq ($(CONFIG_USBMSC),y) +CSRCS += rp2040_usbmsc.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += rp2040_composite.c +endif + ifeq ($(CONFIG_RP2040_SPISD),y) CSRCS += rp2040_spisd.c endif @@ -54,6 +62,10 @@ ifeq ($(CONFIG_ENC28J60),y) CSRCS += rp2040_enc28j60.c endif +ifeq ($(CONFIG_LCD_BACKPACK),y) + CSRCS += rp2040_lcd_backpack.c +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src) diff --git a/boards/arm/rp2040/common/src/rp2040_bmp180.c b/boards/arm/rp2040/common/src/rp2040_bmp180.c index 8e95a533082..59bea0afae3 100644 --- a/boards/arm/rp2040/common/src/rp2040_bmp180.c +++ b/boards/arm/rp2040/common/src/rp2040_bmp180.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/rp2040/common/src/rp2040_composite.c b/boards/arm/rp2040/common/src/rp2040_composite.c new file mode 100644 index 00000000000..153bf770595 --- /dev/null +++ b/boards/arm/rp2040/common/src/rp2040_composite.c @@ -0,0 +1,276 @@ +/**************************************************************************** + * boards/arm/rp2040/common/src/rp2040_composite.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static FAR void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + FAR struct usbdev_devinfo_s *devinfo, + FAR struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/mmcsd0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. + * This is just an application specific wrapper for usbmsc_unitialize() + * that is called form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instrance previously give to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(FAR struct usbdevclass_driver_s *classdev) +{ + if (g_mschandle) + { + usbmsc_uninitialize(g_mschandle); + } + + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +FAR void *board_composite_connect(int port, int configid) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + if (configid == 0) + { + struct composite_devdesc_s dev[2]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + int n = 0; + +#ifdef CONFIG_USBMSC_COMPOSITE + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[n]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[n].classobject = board_mscclassobject; + dev[n].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[n].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[n].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[n].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[n].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 1; + dev[n].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 2; + + /* Count up the base numbers */ + + ifnobase += dev[n].devinfo.ninterfaces; + strbase += dev[n].devinfo.nstrings; + n++; +#endif + +#ifdef CONFIG_CDCACM_COMPOSITE + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[n]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[n].classobject = cdcacm_classobject; + dev[n].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[n].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[n].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[n].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[n].devinfo.epno[CDCACM_EP_INTIN_IDX] = 3; + dev[n].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 4; + dev[n].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 5; + n++; +#endif + + return composite_initialize(n, dev); + } + else + { + return NULL; + } +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/rp2040/common/src/rp2040_lcd_backpack.c b/boards/arm/rp2040/common/src/rp2040_lcd_backpack.c new file mode 100644 index 00000000000..7b1b8360c62 --- /dev/null +++ b/boards/arm/rp2040/common/src/rp2040_lcd_backpack.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/rp2040/common/src/rp2040_lcd_backpack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "rp2040_i2c.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_backpack_init + * + * Description: + * Initialize the LCD1602 display controlled by Backpack with PCF8574 + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/slcd0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_lcd_backpack_init(int devno, int busno, int rows, int cols) +{ + FAR struct pcf8574_lcd_backpack_config_s cfg = + LCD_I2C_BACKPACK_CFG_ROBOT; + FAR struct i2c_master_s *i2c; + char devpath[12]; + int ret; + + /* Setup the LCD row and cols size. + * Note: We are using the LCD_I2C_BACKPACK_CFG_SAINSMART config that + * defined the I2C Address to 0x27 to PCF8574. Double check if all + * the bits (pins) from PCF8574 connected to the LCD controller + * are correct with this LCD CFG definition. + */ + + cfg.rows = rows; + cfg.cols = cols; + + /* Initialize the I2C0 */ + + i2c = rp2040_i2cbus_initialize(busno); + if (i2c == NULL) + { + return -ENODEV; + } + + /* Regiter the Segment LCD */ + + snprintf(devpath, 12, "/dev/slcd%d", devno); + ret = pcf8574_lcd_backpack_register(devpath, i2c, &cfg); + if (ret < 0) + { + lcderr("ERROR: pcf8574_lcd_backpack_register(%s) failed: %d\n", + devpath, ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/rp2040/common/src/rp2040_st7789.c b/boards/arm/rp2040/common/src/rp2040_st7789.c index bc7084789c3..24cd8fd453e 100644 --- a/boards/arm/rp2040/common/src/rp2040_st7789.c +++ b/boards/arm/rp2040/common/src/rp2040_st7789.c @@ -42,7 +42,15 @@ * Pre-processor Definitions ****************************************************************************/ -#define LCD_SPI_PORTNO 0 +#define LCD_SPI_PORTNO CONFIG_RP2040_LCD_SPI_CH + +#if LCD_SPI_PORTNO +#define LCD_DC CONFIG_RP2040_SPI1_GPIO +#define LCD_RST 12 +#define LCD_BL 13 +#else +#define LCD_DC CONFIG_RP2040_SPI0_GPIO +#endif /**************************************************************************** * Private Data @@ -76,9 +84,25 @@ int board_lcd_initialize(void) /* SPI RX is not used. Same pin is used as LCD Data/Command control */ - rp2040_gpio_init(CONFIG_RP2040_SPI0_GPIO); - rp2040_gpio_setdir(CONFIG_RP2040_SPI0_GPIO, true); - rp2040_gpio_put(CONFIG_RP2040_SPI0_GPIO, true); + rp2040_gpio_init(LCD_DC); + rp2040_gpio_setdir(LCD_DC, true); + rp2040_gpio_put(LCD_DC, true); + +#if LCD_SPI_PORTNO + + /* Pull LCD_RESET high */ + + rp2040_gpio_init(LCD_RST); + rp2040_gpio_setdir(LCD_RST, true); + rp2040_gpio_put(LCD_RST, true); + + /* Set full brightness */ + + rp2040_gpio_init(LCD_BL); + rp2040_gpio_setdir(LCD_BL, true); + rp2040_gpio_put(LCD_BL, true); + +#endif return OK; } @@ -97,11 +121,12 @@ FAR struct lcd_dev_s *board_lcd_getdev(int devno) g_lcd = st7789_lcdinitialize(g_spidev); if (!g_lcd) { - lcderr("ERROR: Failed to bind SPI port 0 to LCD %d\n", devno); + lcderr("ERROR: Failed to bind SPI port %d to LCD %d\n", LCD_SPI_PORTNO, + devno); } else { - lcdinfo("SPI port 0 bound to LCD %d\n", devno); + lcdinfo("SPI port %d bound to LCD %d\n", LCD_SPI_PORTNO, devno); return g_lcd; } diff --git a/boards/arm/rp2040/common/src/rp2040_usbmsc.c b/boards/arm/rp2040/common/src/rp2040_usbmsc.c new file mode 100644 index 00000000000..401f8f5a058 --- /dev/null +++ b/boards/arm/rp2040/common/src/rp2040_usbmsc.c @@ -0,0 +1,61 @@ +/**************************************************************************** + * boards/arm/rp2040/common/src/rp2040_usbmsc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized in board_app_initialize() + * (see stm32_appinit.c). + * In this case, there is nothing further to be done here. + */ + + return OK; +} diff --git a/boards/arm/rp2040/raspberrypi-pico/Kconfig b/boards/arm/rp2040/raspberrypi-pico/Kconfig index 769fb26c972..042ade67144 100644 --- a/boards/arm/rp2040/raspberrypi-pico/Kconfig +++ b/boards/arm/rp2040/raspberrypi-pico/Kconfig @@ -63,6 +63,13 @@ config RP2040_SPI1_GPIO range -1 29 depends on RP2040_SPI1 +config RP2040_LCD_SPI_CH + int "RP2040 LCD SPI channel number" + default 0 + range 0 1 + depends on LCD + ---help--- + Select SPI channel number to use LCD display. config RP2040_ENC28J60_SPI_CH int "ENC28J60 SPI channel number" diff --git a/boards/arm/rp2040/raspberrypi-pico/README.txt b/boards/arm/rp2040/raspberrypi-pico/README.txt index 23fa5f89afb..c043cd320a4 100644 --- a/boards/arm/rp2040/raspberrypi-pico/README.txt +++ b/boards/arm/rp2040/raspberrypi-pico/README.txt @@ -13,6 +13,9 @@ Currently only the following devices are suppored. - I2C - SPI - DMAC + - USB device + - MSC, CDC/ACM serial and these composite device are supported. + - CDC/ACM serial device can be used for the console. - PIO (RP2040 Programmable I/O) - Flash ROM Boot - SRAM Boot @@ -56,6 +59,10 @@ Installation 5. To access the console, GPIO 0 and 1 pins must be connected to the device such as USB-serial converter. + `usbnsh` configuration provides the console access by USB CDC/ACM serial + devcice. The console is available by using a terminal software on the USB + host. + Defconfigs ========== @@ -76,7 +83,15 @@ Defconfigs VCC ----- 3V3 OUT (Pin 36) SDA ----- GP4 (I2C0 SDA) (Pin 6) SCL ----- GP5 (I2C0 SCL) (Pin 7) - + +- lcd1602 + LCD 1602 Segment LCD Disaply (I2C) + Connection: + PCF8574 BackPack Raspberry Pi Pico + GND ----- GND (Pin 3 or 38 or ...) + VCC ----- 5V Vbus (Pin 40) + SDA ----- GP4 (I2C0 SDA) (Pin 6) + SCL ----- GP5 (I2C0 SCL) (Pin 7) - spisd SD card support (SPI connection) Connection: @@ -118,6 +133,19 @@ Defconfigs https://shop.pimoroni.com/products/pico-audio-pack SD card interface is also enabled. +- usbnsh + USB CDC/ACM serial console with NuttShell + +- usbmsc + USB MSC and CDC/ACM support + `msconn` and `sercon` commands enable the MSC and CDC/ACM devices. + The MSC support provides the interface to the SD card with SPI, + so the SD card slot connection like spisd configuraion is requied. + +- composite + USB composite device (MSC + CDC/ACM) support + `conn` command enables the composite device. + License exceptions ================== diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/audiopack/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/audiopack/defconfig index 479ae48f650..c3e8a383aa6 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/audiopack/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/audiopack/defconfig @@ -44,7 +44,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/composite/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/composite/defconfig new file mode 100644 index 00000000000..cd5845f6391 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/configs/composite/defconfig @@ -0,0 +1,77 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="raspberrypi-pico" +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO=y +CONFIG_ARCH_CHIP="rp2040" +CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10450 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_COMPOSITE_IAD=y +CONFIG_COMPOSITE_MSFT_OS_DESCRIPTORS=y +CONFIG_COMPOSITE_PRODUCTID=0x2022 +CONFIG_COMPOSITE_SERIALSTR="12345" +CONFIG_COMPOSITE_VENDORID=0x03eb +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_MMCSD=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=270336 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RP2040_SPI0=y +CONFIG_RP2040_SPI0_GPIO=16 +CONFIG_RP2040_SPI=y +CONFIG_RP2040_SPISD=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y +CONFIG_USBMSC_NOT_STALL_BULKEP=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/displaypack/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/displaypack/defconfig index ea720690399..ae3e480559b 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/displaypack/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/displaypack/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_DEV_CONSOLE is not set # CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set # CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set # CONFIG_LIBC_LONG_LONG is not set @@ -29,6 +30,8 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=10450 CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y @@ -64,12 +67,12 @@ CONFIG_LCD_ST7789_XOFFSET=53 CONFIG_LCD_ST7789_XRES=135 CONFIG_LCD_ST7789_YOFFSET=40 CONFIG_LCD_ST7789_YRES=240 -CONFIG_MAX_TASKS=8 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y +CONFIG_NSH_USBCONSOLE=y CONFIG_NX=y CONFIG_NXFONTS_PACKEDMSFIRST=y CONFIG_NXFONT_SANS40X49B=y @@ -87,12 +90,12 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=9 CONFIG_START_MONTH=2 CONFIG_START_YEAR=2021 -CONFIG_SYSLOG_CONSOLE=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SPITOOL=y CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_VIDEO_FB=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/enc28j60/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/enc28j60/defconfig index 49f4ac57452..22d009521da 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/enc28j60/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/enc28j60/defconfig @@ -32,7 +32,6 @@ CONFIG_ENC28J60=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_NOADDR=y @@ -47,7 +46,6 @@ CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_LOOPBACK=y CONFIG_NET_ROUTE=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/lcd1602/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/lcd1602/defconfig new file mode 100644 index 00000000000..f6e234c1a67 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/configs/lcd1602/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="raspberrypi-pico" +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO=y +CONFIG_ARCH_CHIP="rp2040" +CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10450 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_SLCD=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_LCD_BACKPACK=y +CONFIG_LCD_LCD1602=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=270336 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RP2040_I2C0=y +CONFIG_RP2040_I2C0_GPIO=4 +CONFIG_RP2040_I2C=y +CONFIG_RP2040_I2C_DRIVER=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SLCD=y +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSLOG_CONSOLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/nsh/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/nsh/defconfig index 7663e37defb..75b23e5c973 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/nsh/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/nshsram/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/nshsram/defconfig index bd1b9f9d899..003806fe50f 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/nshsram/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/nshsram/defconfig @@ -30,7 +30,6 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/smp/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/smp/defconfig index 7f35050e0a2..4b861cecde0 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/smp/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/smp/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BOARD="raspberrypi-pico" CONFIG_ARCH_BOARD_RASPBERRYPI_PICO=y CONFIG_ARCH_CHIP="rp2040" CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y @@ -30,7 +31,6 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=16 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/spisd/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/spisd/defconfig index e2edd74ea66..3805106d1cf 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/spisd/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/spisd/defconfig @@ -36,7 +36,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_MMCSD=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/ssd1306/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/ssd1306/defconfig index 4656914342e..d184e0021e5 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/ssd1306/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/ssd1306/defconfig @@ -47,7 +47,6 @@ CONFIG_LCD_FRAMEBUFFER=y CONFIG_LCD_MAXCONTRAST=255 CONFIG_LCD_SH1106_OLED_132=y CONFIG_LCD_SSD1306_I2C=y -CONFIG_MAX_TASKS=8 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/usbmsc/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/usbmsc/defconfig new file mode 100644 index 00000000000..349c51dcb73 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/configs/usbmsc/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="raspberrypi-pico" +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO=y +CONFIG_ARCH_CHIP="rp2040" +CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10450 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_MMCSD=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=270336 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RP2040_SPI0=y +CONFIG_RP2040_SPI0_GPIO=16 +CONFIG_RP2040_SPI=y +CONFIG_RP2040_SPISD=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBMSC=y +CONFIG_USBMSC_NOT_STALL_BULKEP=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/usbnsh/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/usbnsh/defconfig new file mode 100644 index 00000000000..744399cfb8b --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/configs/usbnsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_RP2040_UART0 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="raspberrypi-pico" +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO=y +CONFIG_ARCH_CHIP="rp2040" +CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10450 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_USBCONSOLE=y +CONFIG_RAM_SIZE=270336 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/waveshare-lcd-1.14/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/waveshare-lcd-1.14/defconfig new file mode 100644 index 00000000000..696c8e1cc38 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/configs/waveshare-lcd-1.14/defconfig @@ -0,0 +1,98 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="raspberrypi-pico" +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO=y +CONFIG_ARCH_CHIP="rp2040" +CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10450 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXDEMO=y +CONFIG_EXAMPLES_NXDEMO_BPP=16 +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0 +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 +CONFIG_EXAMPLES_NXLINES_BPP=16 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_I2C=y +CONFIG_LCD=y +CONFIG_LCD_DEV=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_MAXCONTRAST=255 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_ST7789=y +CONFIG_LCD_ST7789_FREQUENCY=64000000 +CONFIG_LCD_ST7789_XOFFSET=53 +CONFIG_LCD_ST7789_XRES=135 +CONFIG_LCD_ST7789_YOFFSET=40 +CONFIG_LCD_ST7789_YRES=240 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONTS_PACKEDMSFIRST=y +CONFIG_NXFONT_SANS40X49B=y +CONFIG_NX_BLOCKING=y +CONFIG_RAM_SIZE=270336 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RP2040_LCD_SPI_CH=1 +CONFIG_RP2040_SPI1=y +CONFIG_RP2040_SPI1_GPIO=8 +CONFIG_RP2040_SPI=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSLOG_CONSOLE=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_VIDEO_FB=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/waveshare-lcd-1.3/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/waveshare-lcd-1.3/defconfig new file mode 100644 index 00000000000..50b3233ae05 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/configs/waveshare-lcd-1.3/defconfig @@ -0,0 +1,95 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="raspberrypi-pico" +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO=y +CONFIG_ARCH_CHIP="rp2040" +CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10450 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXDEMO=y +CONFIG_EXAMPLES_NXDEMO_BPP=16 +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0 +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 +CONFIG_EXAMPLES_NXLINES_BPP=16 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_I2C=y +CONFIG_LCD=y +CONFIG_LCD_DEV=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_MAXCONTRAST=255 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_ST7789=y +CONFIG_LCD_ST7789_FREQUENCY=64000000 +CONFIG_LCD_ST7789_YRES=240 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONTS_PACKEDMSFIRST=y +CONFIG_NXFONT_SANS40X49B=y +CONFIG_NX_BLOCKING=y +CONFIG_RAM_SIZE=270336 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RP2040_LCD_SPI_CH=1 +CONFIG_RP2040_SPI1=y +CONFIG_RP2040_SPI1_GPIO=8 +CONFIG_RP2040_SPI=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSLOG_CONSOLE=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_VIDEO_FB=y diff --git a/boards/arm/rp2040/raspberrypi-pico/include/board.h b/boards/arm/rp2040/raspberrypi-pico/include/board.h index 539c809cf06..05462609f54 100644 --- a/boards/arm/rp2040/raspberrypi-pico/include/board.h +++ b/boards/arm/rp2040/raspberrypi-pico/include/board.h @@ -63,6 +63,9 @@ /* GPIO definitions *********************************************************/ #define BOARD_GPIO_LED_PIN 25 +#define BOARD_NGPIOOUT 1 +#define BOARD_NGPIOIN 1 +#define BOARD_NGPIOINT 1 /**************************************************************************** * Public Types diff --git a/boards/arm/rp2040/raspberrypi-pico/scripts/Make.defs b/boards/arm/rp2040/raspberrypi-pico/scripts/Make.defs index 26943ef4bd5..d04fbd408e6 100644 --- a/boards/arm/rp2040/raspberrypi-pico/scripts/Make.defs +++ b/boards/arm/rp2040/raspberrypi-pico/scripts/Make.defs @@ -30,9 +30,9 @@ else endif ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" + ARCHSCRIPT = -Wl,-T"${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" else - ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + ARCHSCRIPT = -Wl,-T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) @@ -56,8 +56,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/rp2040/raspberrypi-pico/src/Make.defs b/boards/arm/rp2040/raspberrypi-pico/src/Make.defs index 51fc4ae7414..b78129495bb 100644 --- a/boards/arm/rp2040/raspberrypi-pico/src/Make.defs +++ b/boards/arm/rp2040/raspberrypi-pico/src/Make.defs @@ -32,6 +32,10 @@ ifeq ($(CONFIG_SPI),y) CSRCS += rp2040_spi.c endif +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += rp2040_gpio.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_bringup.c b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_bringup.c index 570d0edec19..96ee4804618 100644 --- a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_bringup.c +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_bringup.c @@ -33,6 +33,10 @@ #include "rp2040_pico.h" +#ifdef CONFIG_LCD_BACKPACK +# include "rp2040_lcd_backpack.h" +#endif + #ifdef CONFIG_VIDEO_FB # include #endif @@ -134,6 +138,17 @@ int rp2040_bringup(void) } #endif +#ifdef CONFIG_LCD_BACKPACK + /* slcd:0, i2c:0, rows=2, cols=16 */ + + ret = board_lcd_backpack_init(0, 0, 2, 16); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); + return ret; + } +#endif + #ifdef CONFIG_RP2040_I2S ret = board_i2sdev_initialize(0); if (ret < 0) @@ -142,5 +157,14 @@ int rp2040_bringup(void) } #endif +#ifdef CONFIG_DEV_GPIO + ret = rp2040_dev_gpio_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + return ret; } diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_gpio.c b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_gpio.c new file mode 100644 index 00000000000..eebaa52c6f2 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_gpio.c @@ -0,0 +1,392 @@ +/**************************************************************************** + * boards/arm/rp2040/raspberrypi-pico/src/rp2040_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "arm_arch.h" +#include "chip.h" +#include "rp2040_gpio.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/* Output pins. GPIO25 is onboard LED any other outputs could be used. + */ + +#define GPIO_OUT1 25 + +/* Input pins. + */ + +#define GPIO_IN1 6 + +/* Interrupt pins. + */ + +#define GPIO_IRQPIN1 14 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rp2040gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct rp2040gpint_dev_s +{ + struct rp2040gpio_dev_s rp2040gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpout_write(FAR struct gpio_dev_s *dev, bool value); +#endif + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpint_attach(FAR struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1 +}; + +static struct rp2040gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1 +}; + +static struct rp2040gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_IRQPIN1, +}; + +static struct rp2040gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpout_read + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct rp2040gpio_dev_s *rp2040gpio = + (FAR struct rp2040gpio_dev_s *)dev; + + DEBUGASSERT(rp2040gpio != NULL && value != NULL); + DEBUGASSERT(rp2040gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = rp2040_gpio_get(g_gpiooutputs[rp2040gpio->id]); + return OK; +} + +/**************************************************************************** + * Name: gpout_write + ****************************************************************************/ + +static int gpout_write(FAR struct gpio_dev_s *dev, bool value) +{ + FAR struct rp2040gpio_dev_s *rp2040gpio = + (FAR struct rp2040gpio_dev_s *)dev; + + DEBUGASSERT(rp2040gpio != NULL); + DEBUGASSERT(rp2040gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + rp2040_gpio_put(g_gpiooutputs[rp2040gpio->id], value); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpin_read + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct rp2040gpio_dev_s *rp2040gpio = + (FAR struct rp2040gpio_dev_s *)dev; + + DEBUGASSERT(rp2040gpio != NULL && value != NULL); + DEBUGASSERT(rp2040gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading... pin %d\n", (int)g_gpioinputs[rp2040gpio->id]); + + *value = rp2040_gpio_get(g_gpioinputs[rp2040gpio->id]); + return OK; +} +#endif + +/**************************************************************************** + * Name: rp2040gpio_interrupt + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int rp2040gpio_interrupt(int irq, void *context, void *arg) +{ + FAR struct rp2040gpint_dev_s *rp2040gpint = + (FAR struct rp2040gpint_dev_s *)arg; + + DEBUGASSERT(rp2040gpint != NULL && rp2040gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", rp2040gpint->callback); + + rp2040gpint->callback(&rp2040gpint->rp2040gpio.gpio, + rp2040gpint->rp2040gpio.id); + return OK; +} + +/**************************************************************************** + * Name: gpint_read + ****************************************************************************/ + +static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct rp2040gpint_dev_s *rp2040gpint = + (FAR struct rp2040gpint_dev_s *)dev; + + DEBUGASSERT(rp2040gpint != NULL && value != NULL); + DEBUGASSERT(rp2040gpint->rp2040gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = rp2040_gpio_get(g_gpiointinputs[rp2040gpint->rp2040gpio.id]); + return OK; +} + +/**************************************************************************** + * Name: gpint_attach + ****************************************************************************/ + +static int gpint_attach(FAR struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + FAR struct rp2040gpint_dev_s *rp2040gpint = + (FAR struct rp2040gpint_dev_s *)dev; + int irq = g_gpiointinputs[rp2040gpint->rp2040gpio.id]; + int ret; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + rp2040_gpio_disable_irq(irq); + ret = rp2040_gpio_irq_attach(irq, + RP2040_GPIO_INTR_EDGE_LOW, + rp2040gpio_interrupt, + &g_gpint[rp2040gpint->rp2040gpio.id]); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); + return ret; + } + + gpioinfo("Attach %p\n", callback); + rp2040gpint->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: gpint_enable + ****************************************************************************/ + +static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable) +{ + FAR struct rp2040gpint_dev_s *rp2040gpint = + (FAR struct rp2040gpint_dev_s *)dev; + int irq = g_gpiointinputs[rp2040gpint->rp2040gpio.id]; + + if (enable) + { + if (rp2040gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + rp2040_gpio_enable_irq(irq); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + rp2040_gpio_disable_irq(irq); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_dev_gpio_init + ****************************************************************************/ + +int rp2040_dev_gpio_init(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, g_gpiooutputs[i]); + + /* Configure the pins that will be used as output */ + + rp2040_gpio_init(g_gpiooutputs[i]); + rp2040_gpio_setdir(g_gpiooutputs[i], true); + rp2040_gpio_put(g_gpiooutputs[i], false); + + pincount++; + } +#endif + + pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, g_gpioinputs[i]); + + /* Configure the pins that will be used as INPUT */ + + rp2040_gpio_init(g_gpioinputs[i]); + + pincount++; + } +#endif + + pincount = 0; + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].rp2040gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].rp2040gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].rp2040gpio.id = i; + gpio_pin_register(&g_gpint[i].rp2040gpio.gpio, g_gpiointinputs[i]); + + /* Configure the pins that will be used as interrupt input */ + + rp2040_gpio_init(g_gpiointinputs[i]); + + /* pull-up = false : pull-down = true */ + + rp2040_gpio_set_pulls(g_gpiointinputs[i], false, true); + + pincount++; + } +#endif + + return OK; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_pico.h b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_pico.h index 4762bd7bb4e..21a77bd9e80 100644 --- a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_pico.h +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_pico.h @@ -29,4 +29,8 @@ int rp2040_bringup(void); +#ifdef CONFIG_DEV_GPIO +int rp2040_dev_gpio_init(void); +#endif + #endif /* __BOARDS_ARM_RP2040_RASPBERRYPI_PICO_SRC_RP2040_PICO_H */ diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_spi.c b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_spi.c index fef438d54c6..a0c688366e2 100644 --- a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_spi.c +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_spi.c @@ -131,6 +131,19 @@ uint8_t rp2040_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA int rp2040_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) { +#ifdef CONFIG_LCD_ST7789 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + rp2040_gpio_put(CONFIG_RP2040_SPI1_GPIO, !cmd); + + return OK; + } +#endif + return -ENODEV; } #endif diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig index 01c9bc20aec..d42c12f3d83 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig @@ -34,7 +34,6 @@ CONFIG_LPUART0_TXBUFSIZE=64 CONFIG_LPUART1_RXBUFSIZE=64 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=64 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig index ad621042e90..1b573c90adb 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig +++ b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig @@ -36,7 +36,6 @@ CONFIG_LPUART0_TXBUFSIZE=64 CONFIG_LPUART1_RXBUFSIZE=64 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=64 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs index 4546de7b175..6e3dd507a5f 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs +++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs @@ -58,8 +58,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig index 38661bbc559..20d9e5e108e 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig @@ -36,7 +36,6 @@ CONFIG_LPUART0_TXBUFSIZE=64 CONFIG_LPUART1_RXBUFSIZE=64 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=64 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NET=y CONFIG_NETDEV_IFINDEX=y diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig index 081af734222..65465dc4981 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig +++ b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig @@ -36,7 +36,6 @@ CONFIG_LPUART0_TXBUFSIZE=64 CONFIG_LPUART1_RXBUFSIZE=64 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=64 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h b/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h index ed0236dbfc1..631684b1337 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h +++ b/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h @@ -73,6 +73,12 @@ #define BOARD_LED_G_BIT (1 << BOARD_LED_G) #define BOARD_LED_B_BIT (1 << BOARD_LED_B) +/* Board revision detection pin + * 0 equals UCANS32K146-01 + * 1 equals UCANS32K146B + */ +#define BOARD_REVISION_DETECT_PIN (GPIO_INPUT | PIN_PORTA | PIN10 ) + /* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board * the RDDRONE-UAVCAN146. The following definitions describe how NuttX * controls the LEDs: @@ -138,11 +144,9 @@ /* CAN selections ***********************************************************/ #define PIN_CAN0_TX PIN_CAN0_TX_4 /* PTE5 */ #define PIN_CAN0_RX PIN_CAN0_RX_4 /* PTE4 */ -#define PIN_CAN0_ENABLE (GPIO_OUTPUT | PIN_PORTE | PIN11 ) -#define CAN0_ENABLE_OUT 0 +#define PIN_CAN0_STB (GPIO_OUTPUT | PIN_PORTE | PIN11 ) #define PIN_CAN1_TX PIN_CAN1_TX_1 /* PTA13 */ #define PIN_CAN1_RX PIN_CAN1_RX_1 /* PTA12 */ -#define PIN_CAN1_ENABLE (GPIO_OUTPUT | PIN_PORTE | PIN10 ) -#define CAN1_ENABLE_OUT 0 +#define PIN_CAN1_STB (GPIO_OUTPUT | PIN_PORTE | PIN10 ) #endif /* __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs index d1bbcf85b43..349199ade88 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs +++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs @@ -58,8 +58,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c index 24485d16fd4..e449d5c071a 100644 --- a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c @@ -23,7 +23,7 @@ ****************************************************************************/ #include - +#include #include #include @@ -147,5 +147,23 @@ int s32k1xx_bringup(void) s32k1xx_eeeprom_register(0, 4096); #endif +#ifdef CONFIG_S32K1XX_FLEXCAN + s32k1xx_pinconfig(BOARD_REVISION_DETECT_PIN); + + if (s32k1xx_gpioread(BOARD_REVISION_DETECT_PIN)) + { + /* STB high -> active CAN phy */ + + s32k1xx_pinconfig(PIN_CAN0_STB | GPIO_OUTPUT_ONE); + } + else + { + /* STB low -> active CAN phy */ + + s32k1xx_pinconfig(PIN_CAN0_STB | GPIO_OUTPUT_ZERO); + } + +#endif + return ret; } diff --git a/boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig index f226a1a4170..28cb34fe6ac 100644 --- a/boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig @@ -27,7 +27,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_LPUART0_RXBUFSIZE=64 CONFIG_LPUART0_SERIAL_CONSOLE=y CONFIG_LPUART0_TXBUFSIZE=64 -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_MOTOROLA_SREC=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 diff --git a/boards/arm/s32k1xx/s32k118evb/scripts/Make.defs b/boards/arm/s32k1xx/s32k118evb/scripts/Make.defs index ba46cf48c25..e4dffca0ce7 100644 --- a/boards/arm/s32k1xx/s32k118evb/scripts/Make.defs +++ b/boards/arm/s32k1xx/s32k118evb/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig index 4650d669618..ea1b9f78173 100644 --- a/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_LPUART1_RXBUFSIZE=64 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=64 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs b/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs index 689fea1f9cf..65674b4772e 100644 --- a/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs +++ b/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs @@ -58,8 +58,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig index e5f85facdd1..c17992fd3a2 100644 --- a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_LPUART1_RXBUFSIZE=64 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=64 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/s32k1xx/s32k146evb/scripts/Make.defs b/boards/arm/s32k1xx/s32k146evb/scripts/Make.defs index 4d7a46b46a7..999cdd14535 100644 --- a/boards/arm/s32k1xx/s32k146evb/scripts/Make.defs +++ b/boards/arm/s32k1xx/s32k146evb/scripts/Make.defs @@ -58,8 +58,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig index c8f7cc50fcb..9637952298d 100644 --- a/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_LPUART1_RXBUFSIZE=64 CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_TXBUFSIZE=64 -CONFIG_MAX_TASKS=16 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/Make.defs b/boards/arm/s32k1xx/s32k148evb/scripts/Make.defs index 2c32799b5fa..b16c2b0a0e3 100644 --- a/boards/arm/s32k1xx/s32k148evb/scripts/Make.defs +++ b/boards/arm/s32k1xx/s32k148evb/scripts/Make.defs @@ -58,8 +58,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/arduino-due/configs/nsh/defconfig b/boards/arm/sam34/arduino-due/configs/nsh/defconfig index dce28a59287..88efae5125d 100644 --- a/boards/arm/sam34/arduino-due/configs/nsh/defconfig +++ b/boards/arm/sam34/arduino-due/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_BUILTIN=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/sam34/arduino-due/scripts/Make.defs b/boards/arm/sam34/arduino-due/scripts/Make.defs index b416578667f..49bfe42e7d7 100644 --- a/boards/arm/sam34/arduino-due/scripts/Make.defs +++ b/boards/arm/sam34/arduino-due/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/arduino-due/src/sam_autoleds.c b/boards/arm/sam34/arduino-due/src/sam_autoleds.c index b93f69b29ca..05de20edf9b 100644 --- a/boards/arm/sam34/arduino-due/src/sam_autoleds.c +++ b/boards/arm/sam34/arduino-due/src/sam_autoleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/flipnclick-sam3x/configs/nsh/defconfig b/boards/arm/sam34/flipnclick-sam3x/configs/nsh/defconfig index 54700978fb4..94e65a4f53d 100644 --- a/boards/arm/sam34/flipnclick-sam3x/configs/nsh/defconfig +++ b/boards/arm/sam34/flipnclick-sam3x/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/sam34/flipnclick-sam3x/configs/nxlines/defconfig b/boards/arm/sam34/flipnclick-sam3x/configs/nxlines/defconfig index 127c0f3f5c1..031808a3549 100644 --- a/boards/arm/sam34/flipnclick-sam3x/configs/nxlines/defconfig +++ b/boards/arm/sam34/flipnclick-sam3x/configs/nxlines/defconfig @@ -31,7 +31,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_LCD=y CONFIG_LCD_HILETGO=y CONFIG_LCD_MAXCONTRAST=255 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/sam34/flipnclick-sam3x/scripts/Make.defs b/boards/arm/sam34/flipnclick-sam3x/scripts/Make.defs index d1021027917..8572e54f5f7 100644 --- a/boards/arm/sam34/flipnclick-sam3x/scripts/Make.defs +++ b/boards/arm/sam34/flipnclick-sam3x/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/flipnclick-sam3x/src/sam_autoleds.c b/boards/arm/sam34/flipnclick-sam3x/src/sam_autoleds.c index 0e685a112e8..60b59214d47 100644 --- a/boards/arm/sam34/flipnclick-sam3x/src/sam_autoleds.c +++ b/boards/arm/sam34/flipnclick-sam3x/src/sam_autoleds.c @@ -70,6 +70,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/flipnclick-sam3x/src/sam_spi0.c b/boards/arm/sam34/flipnclick-sam3x/src/sam_spi0.c index 9be54c33f95..88ef925a0ec 100644 --- a/boards/arm/sam34/flipnclick-sam3x/src/sam_spi0.c +++ b/boards/arm/sam34/flipnclick-sam3x/src/sam_spi0.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/sam3u-ek/configs/knsh/Make.defs b/boards/arm/sam34/sam3u-ek/configs/knsh/Make.defs index 4ec675522a5..35802dd168e 100644 --- a/boards/arm/sam34/sam3u-ek/configs/knsh/Make.defs +++ b/boards/arm/sam34/sam3u-ek/configs/knsh/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/sam3u-ek/configs/knsh/defconfig b/boards/arm/sam34/sam3u-ek/configs/knsh/defconfig index 8f5fae050c4..c244ed9aa5f 100644 --- a/boards/arm/sam34/sam3u-ek/configs/knsh/defconfig +++ b/boards/arm/sam34/sam3u-ek/configs/knsh/defconfig @@ -24,7 +24,6 @@ CONFIG_ARM_MPU=y CONFIG_BOARD_LOOPSPERMSEC=8720 CONFIG_BUILD_PROTECTED=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_REGIONS=3 CONFIG_NSH_DISABLE_DD=y @@ -48,7 +47,7 @@ CONFIG_START_DAY=10 CONFIG_START_MONTH=3 CONFIG_START_YEAR=2013 CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/sam34/sam3u-ek/configs/nsh/defconfig b/boards/arm/sam34/sam3u-ek/configs/nsh/defconfig index bb64029c1b1..b7119799e0a 100644 --- a/boards/arm/sam34/sam3u-ek/configs/nsh/defconfig +++ b/boards/arm/sam34/sam3u-ek/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=8720 CONFIG_BUILTIN=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/sam34/sam3u-ek/configs/nx/defconfig b/boards/arm/sam34/sam3u-ek/configs/nx/defconfig index 0d1bf390b27..83193382967 100644 --- a/boards/arm/sam34/sam3u-ek/configs/nx/defconfig +++ b/boards/arm/sam34/sam3u-ek/configs/nx/defconfig @@ -38,7 +38,6 @@ CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_MAXPOWER=31 CONFIG_LCD_PORTRAIT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y diff --git a/boards/arm/sam34/sam3u-ek/configs/nxwm/defconfig b/boards/arm/sam34/sam3u-ek/configs/nxwm/defconfig index 33903bffaac..b6725d54bc0 100644 --- a/boards/arm/sam34/sam3u-ek/configs/nxwm/defconfig +++ b/boards/arm/sam34/sam3u-ek/configs/nxwm/defconfig @@ -34,7 +34,6 @@ CONFIG_INPUT_ADS7843E=y CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_MAXPOWER=31 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/sam34/sam3u-ek/kernel/Makefile b/boards/arm/sam34/sam3u-ek/kernel/Makefile index 141a884133d..0f797415125 100644 --- a/boards/arm/sam34/sam3u-ek/kernel/Makefile +++ b/boards/arm/sam34/sam3u-ek/kernel/Makefile @@ -40,7 +40,7 @@ else USER_LDSCRIPT += -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -61,7 +61,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/sam34/sam3u-ek/kernel/sam_userspace.c b/boards/arm/sam34/sam3u-ek/kernel/sam_userspace.c index 55fa4139c0f..da2e8d808ab 100644 --- a/boards/arm/sam34/sam3u-ek/kernel/sam_userspace.c +++ b/boards/arm/sam34/sam3u-ek/kernel/sam_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/sam34/sam3u-ek/scripts/Make.defs b/boards/arm/sam34/sam3u-ek/scripts/Make.defs index cd0241c0470..66b845d2075 100644 --- a/boards/arm/sam34/sam3u-ek/scripts/Make.defs +++ b/boards/arm/sam34/sam3u-ek/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/sam3u-ek/src/sam_lcd.c b/boards/arm/sam34/sam3u-ek/src/sam_lcd.c index 70faf3192d9..4136881214c 100644 --- a/boards/arm/sam34/sam3u-ek/src/sam_lcd.c +++ b/boards/arm/sam34/sam3u-ek/src/sam_lcd.c @@ -108,6 +108,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/sam34/sam3u-ek/src/sam_leds.c b/boards/arm/sam34/sam3u-ek/src/sam_leds.c index 382dbafb9c8..d2996e22a1f 100644 --- a/boards/arm/sam34/sam3u-ek/src/sam_leds.c +++ b/boards/arm/sam34/sam3u-ek/src/sam_leds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/sam3u-ek/src/sam_spi.c b/boards/arm/sam34/sam3u-ek/src/sam_spi.c index 54bea130c5e..e190a66c79d 100644 --- a/boards/arm/sam34/sam3u-ek/src/sam_spi.c +++ b/boards/arm/sam34/sam3u-ek/src/sam_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/sam4cmp-db/configs/nsh/defconfig b/boards/arm/sam34/sam4cmp-db/configs/nsh/defconfig index f28c8c4895d..38ae5b6915a 100644 --- a/boards/arm/sam34/sam4cmp-db/configs/nsh/defconfig +++ b/boards/arm/sam34/sam4cmp-db/configs/nsh/defconfig @@ -29,14 +29,11 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y -CONFIG_SMP=y -CONFIG_SMP_NCPUS=2 CONFIG_START_DAY=12 CONFIG_START_MONTH=6 CONFIG_START_YEAR=2013 CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=24 CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_SMP=y CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/sam34/sam4cmp-db/scripts/Make.defs b/boards/arm/sam34/sam4cmp-db/scripts/Make.defs index 063939160cf..568356f68fe 100644 --- a/boards/arm/sam34/sam4cmp-db/scripts/Make.defs +++ b/boards/arm/sam34/sam4cmp-db/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/sam4e-ek/configs/nsh/defconfig b/boards/arm/sam34/sam4e-ek/configs/nsh/defconfig index cabf9e7c670..0946740563c 100644 --- a/boards/arm/sam34/sam4e-ek/configs/nsh/defconfig +++ b/boards/arm/sam34/sam4e-ek/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_IOB_NBUFFERS=24 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MTD=y CONFIG_MTD_AT25=y diff --git a/boards/arm/sam34/sam4e-ek/configs/nxwm/defconfig b/boards/arm/sam34/sam4e-ek/configs/nxwm/defconfig index 6821a7bb33b..97b65ad22bb 100644 --- a/boards/arm/sam34/sam4e-ek/configs/nxwm/defconfig +++ b/boards/arm/sam34/sam4e-ek/configs/nxwm/defconfig @@ -40,7 +40,6 @@ CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_MAXPOWER=64 CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MTD=y diff --git a/boards/arm/sam34/sam4e-ek/configs/usbnsh/defconfig b/boards/arm/sam34/sam4e-ek/configs/usbnsh/defconfig index 826fa0e2a60..921d78c3cc4 100644 --- a/boards/arm/sam34/sam4e-ek/configs/usbnsh/defconfig +++ b/boards/arm/sam34/sam4e-ek/configs/usbnsh/defconfig @@ -34,7 +34,6 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MTD=y CONFIG_MTD_AT25=y diff --git a/boards/arm/sam34/sam4e-ek/scripts/Make.defs b/boards/arm/sam34/sam4e-ek/scripts/Make.defs index d2bc516a5e6..e7326c00fb7 100644 --- a/boards/arm/sam34/sam4e-ek/scripts/Make.defs +++ b/boards/arm/sam34/sam4e-ek/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/sam4e-ek/src/sam_ili9325.c b/boards/arm/sam34/sam4e-ek/src/sam_ili9325.c index 07afcd5250e..b4a15c1d972 100644 --- a/boards/arm/sam34/sam4e-ek/src/sam_ili9325.c +++ b/boards/arm/sam34/sam4e-ek/src/sam_ili9325.c @@ -127,6 +127,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/sam34/sam4e-ek/src/sam_ili9341.c b/boards/arm/sam34/sam4e-ek/src/sam_ili9341.c index d26a19cb87b..7db8a74aa6c 100644 --- a/boards/arm/sam34/sam4e-ek/src/sam_ili9341.c +++ b/boards/arm/sam34/sam4e-ek/src/sam_ili9341.c @@ -126,6 +126,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/sam34/sam4e-ek/src/sam_leds.c b/boards/arm/sam34/sam4e-ek/src/sam_leds.c index 9dc1f950ba5..df14bc4c220 100644 --- a/boards/arm/sam34/sam4e-ek/src/sam_leds.c +++ b/boards/arm/sam34/sam4e-ek/src/sam_leds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/sam4e-ek/src/sam_spi.c b/boards/arm/sam34/sam4e-ek/src/sam_spi.c index 14a59ee8c71..71c7713f52c 100644 --- a/boards/arm/sam34/sam4e-ek/src/sam_spi.c +++ b/boards/arm/sam34/sam4e-ek/src/sam_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/sam4l-xplained/configs/nsh/defconfig b/boards/arm/sam34/sam4l-xplained/configs/nsh/defconfig index 347e82487a7..5f02bd0771f 100644 --- a/boards/arm/sam34/sam4l-xplained/configs/nsh/defconfig +++ b/boards/arm/sam34/sam4l-xplained/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_BUILTIN=y CONFIG_DISABLE_ENVIRON=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/sam34/sam4l-xplained/scripts/Make.defs b/boards/arm/sam34/sam4l-xplained/scripts/Make.defs index 8b7bd47445b..a2a63be02c2 100644 --- a/boards/arm/sam34/sam4l-xplained/scripts/Make.defs +++ b/boards/arm/sam34/sam4l-xplained/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/sam4l-xplained/src/sam_autoleds.c b/boards/arm/sam34/sam4l-xplained/src/sam_autoleds.c index ef264f4f7e8..54bb9b0a332 100644 --- a/boards/arm/sam34/sam4l-xplained/src/sam_autoleds.c +++ b/boards/arm/sam34/sam4l-xplained/src/sam_autoleds.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/sam4l-xplained/src/sam_slcd.c b/boards/arm/sam34/sam4l-xplained/src/sam_slcd.c index 775508282e9..9c7440b8c63 100644 --- a/boards/arm/sam34/sam4l-xplained/src/sam_slcd.c +++ b/boards/arm/sam34/sam4l-xplained/src/sam_slcd.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/sam34/sam4s-xplained-pro/configs/fs/defconfig b/boards/arm/sam34/sam4s-xplained-pro/configs/fs/defconfig index c997be0e5b8..e9005e4337e 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/configs/fs/defconfig +++ b/boards/arm/sam34/sam4s-xplained-pro/configs/fs/defconfig @@ -39,7 +39,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_JULIAN_TIME=y CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_SDIO=y CONFIG_MTD=y CONFIG_MTD_NAND=y diff --git a/boards/arm/sam34/sam4s-xplained-pro/configs/nsh/defconfig b/boards/arm/sam34/sam4s-xplained-pro/configs/nsh/defconfig index 4e15807c12a..7d99bac032a 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/configs/nsh/defconfig +++ b/boards/arm/sam34/sam4s-xplained-pro/configs/nsh/defconfig @@ -42,7 +42,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_JULIAN_TIME=y CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_SDIO=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/sam34/sam4s-xplained-pro/scripts/Make.defs b/boards/arm/sam34/sam4s-xplained-pro/scripts/Make.defs index fd888812e4c..30b56007b5f 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/scripts/Make.defs +++ b/boards/arm/sam34/sam4s-xplained-pro/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/sam4s-xplained-pro/src/sam_autoleds.c b/boards/arm/sam34/sam4s-xplained-pro/src/sam_autoleds.c index 03b393d7fad..96abf8ed049 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/src/sam_autoleds.c +++ b/boards/arm/sam34/sam4s-xplained-pro/src/sam_autoleds.c @@ -42,6 +42,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sam34/sam4s-xplained-pro/src/sam_boot.c b/boards/arm/sam34/sam4s-xplained-pro/src/sam_boot.c index 98c279a657e..ad4c9a09cd3 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/src/sam_boot.c +++ b/boards/arm/sam34/sam4s-xplained-pro/src/sam_boot.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/arm/sam34/sam4s-xplained-pro/src/sam_wdt.c b/boards/arm/sam34/sam4s-xplained-pro/src/sam_wdt.c index ef1809122cb..0a00a0f85a3 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/src/sam_wdt.c +++ b/boards/arm/sam34/sam4s-xplained-pro/src/sam_wdt.c @@ -42,6 +42,7 @@ #include #include +#include #include #include #include diff --git a/boards/arm/sam34/sam4s-xplained/configs/nsh/defconfig b/boards/arm/sam34/sam4s-xplained/configs/nsh/defconfig index 580d0153998..ec2d77330e7 100644 --- a/boards/arm/sam34/sam4s-xplained/configs/nsh/defconfig +++ b/boards/arm/sam34/sam4s-xplained/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y diff --git a/boards/arm/sam34/sam4s-xplained/scripts/Make.defs b/boards/arm/sam34/sam4s-xplained/scripts/Make.defs index 84691d8c916..597c2d88bff 100644 --- a/boards/arm/sam34/sam4s-xplained/scripts/Make.defs +++ b/boards/arm/sam34/sam4s-xplained/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/sam34/sam4s-xplained/src/sam_autoleds.c b/boards/arm/sam34/sam4s-xplained/src/sam_autoleds.c index 75edd71efb9..0cd9ecdf882 100644 --- a/boards/arm/sam34/sam4s-xplained/src/sam_autoleds.c +++ b/boards/arm/sam34/sam4s-xplained/src/sam_autoleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/giant-board/configs/netnsh/defconfig b/boards/arm/sama5/giant-board/configs/netnsh/defconfig index e2abc3f82ea..ab28fac1c5f 100644 --- a/boards/arm/sama5/giant-board/configs/netnsh/defconfig +++ b/boards/arm/sama5/giant-board/configs/netnsh/defconfig @@ -44,7 +44,6 @@ CONFIG_I2S=y CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 CONFIG_IOB_THROTTLE=0 -CONFIG_MAX_TASKS=16 CONFIG_NETINIT_NOMAC=y CONFIG_NETUTILS_TELNETD=y CONFIG_NET_ARP_SEND=y diff --git a/boards/arm/sama5/giant-board/configs/nsh/defconfig b/boards/arm/sama5/giant-board/configs/nsh/defconfig index 138bfb53970..ca17fe19ce0 100644 --- a/boards/arm/sama5/giant-board/configs/nsh/defconfig +++ b/boards/arm/sama5/giant-board/configs/nsh/defconfig @@ -34,7 +34,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HIDKBD_POLLUSEC=80000 CONFIG_I2S=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/sama5/giant-board/configs/sdmmc-net-nsh/defconfig b/boards/arm/sama5/giant-board/configs/sdmmc-net-nsh/defconfig index 57e6db4d202..b2a0b5fa3f6 100644 --- a/boards/arm/sama5/giant-board/configs/sdmmc-net-nsh/defconfig +++ b/boards/arm/sama5/giant-board/configs/sdmmc-net-nsh/defconfig @@ -50,7 +50,6 @@ CONFIG_I2S=y CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=72 CONFIG_IOB_THROTTLE=16 -CONFIG_MAX_TASKS=16 CONFIG_NETDB_BUFSIZE=128 CONFIG_NETINIT_NETLOCAL=y CONFIG_NETINIT_NOMAC=y diff --git a/boards/arm/sama5/giant-board/configs/sdmmcnsh/defconfig b/boards/arm/sama5/giant-board/configs/sdmmcnsh/defconfig index fbe88c82207..d2f4cecb11a 100644 --- a/boards/arm/sama5/giant-board/configs/sdmmcnsh/defconfig +++ b/boards/arm/sama5/giant-board/configs/sdmmcnsh/defconfig @@ -50,7 +50,6 @@ CONFIG_I2S=y CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=72 CONFIG_IOB_THROTTLE=16 -CONFIG_MAX_TASKS=16 CONFIG_NETDB_BUFSIZE=128 CONFIG_NETINIT_NETLOCAL=y CONFIG_NETINIT_NOMAC=y diff --git a/boards/arm/sama5/giant-board/scripts/Make.defs b/boards/arm/sama5/giant-board/scripts/Make.defs index 144483ff4b2..1a4fb309620 100644 --- a/boards/arm/sama5/giant-board/scripts/Make.defs +++ b/boards/arm/sama5/giant-board/scripts/Make.defs @@ -64,8 +64,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/sama5/giant-board/src/sam_ajoystick.c b/boards/arm/sama5/giant-board/src/sam_ajoystick.c index 4de0e1d128b..a0fc1d9f019 100644 --- a/boards/arm/sama5/giant-board/src/sam_ajoystick.c +++ b/boards/arm/sama5/giant-board/src/sam_ajoystick.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/giant-board/src/sam_autoleds.c b/boards/arm/sama5/giant-board/src/sam_autoleds.c index 0adfddebf8b..500c9f5b07e 100644 --- a/boards/arm/sama5/giant-board/src/sam_autoleds.c +++ b/boards/arm/sama5/giant-board/src/sam_autoleds.c @@ -58,6 +58,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/sama5d2-xult/configs/netnsh/defconfig b/boards/arm/sama5/sama5d2-xult/configs/netnsh/defconfig index d224b5ed88c..d6eb1177ae1 100644 --- a/boards/arm/sama5/sama5d2-xult/configs/netnsh/defconfig +++ b/boards/arm/sama5/sama5d2-xult/configs/netnsh/defconfig @@ -46,7 +46,6 @@ CONFIG_I2S=y CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 CONFIG_IOB_THROTTLE=0 -CONFIG_MAX_TASKS=16 CONFIG_NETINIT_NOMAC=y CONFIG_NETUTILS_TELNETD=y CONFIG_NET_ARP_SEND=y diff --git a/boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig b/boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig index 8c319684bfc..2f47a0cac0f 100644 --- a/boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig +++ b/boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig @@ -36,7 +36,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HIDKBD_POLLUSEC=80000 CONFIG_I2S=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/sama5/sama5d2-xult/configs/sdmmcnsh/defconfig b/boards/arm/sama5/sama5d2-xult/configs/sdmmcnsh/defconfig index bd15fe78038..9b61d26d312 100644 --- a/boards/arm/sama5/sama5d2-xult/configs/sdmmcnsh/defconfig +++ b/boards/arm/sama5/sama5d2-xult/configs/sdmmcnsh/defconfig @@ -52,7 +52,6 @@ CONFIG_I2S=y CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=72 CONFIG_IOB_THROTTLE=16 -CONFIG_MAX_TASKS=16 CONFIG_NETDB_BUFSIZE=128 CONFIG_NETINIT_NETLOCAL=y CONFIG_NETINIT_NOMAC=y diff --git a/boards/arm/sama5/sama5d2-xult/scripts/Make.defs b/boards/arm/sama5/sama5d2-xult/scripts/Make.defs index 93945adbf70..75b1a4f7924 100644 --- a/boards/arm/sama5/sama5d2-xult/scripts/Make.defs +++ b/boards/arm/sama5/sama5d2-xult/scripts/Make.defs @@ -64,8 +64,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c b/boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c index 2613979b73c..c8ce3def3f2 100644 --- a/boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c +++ b/boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c b/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c index aadf0fe510b..4273325519f 100644 --- a/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c +++ b/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c @@ -61,6 +61,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/sama5d3-xplained/README.txt b/boards/arm/sama5/sama5d3-xplained/README.txt index 8c68bacc3d9..964e258370f 100644 --- a/boards/arm/sama5/sama5d3-xplained/README.txt +++ b/boards/arm/sama5/sama5d3-xplained/README.txt @@ -2247,7 +2247,7 @@ CAN Usage Only messages that have IDs that match the CONFIG_SAMA5_CANn_ADDRn when both the received and the configured address are masked by CONFIG_SAMA5_CANn_MASKn - will be accepted. For example, if the mask is all ones, then only messasges + will be accepted. For example, if the mask is all ones, then only messages with exact address matches will be accepted; if the mask is all zeroes than any address will be accepted. diff --git a/boards/arm/sama5/sama5d3-xplained/configs/bridge/defconfig b/boards/arm/sama5/sama5d3-xplained/configs/bridge/defconfig index 2904dced0b8..c341a3e4556 100644 --- a/boards/arm/sama5/sama5d3-xplained/configs/bridge/defconfig +++ b/boards/arm/sama5/sama5d3-xplained/configs/bridge/defconfig @@ -34,7 +34,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NET_ARP_SEND=y diff --git a/boards/arm/sama5/sama5d3-xplained/configs/ethernet-over-usb-2-high-speed/defconfig b/boards/arm/sama5/sama5d3-xplained/configs/ethernet-over-usb-2-high-speed/defconfig index befe609cb94..0eecf76e60a 100644 --- a/boards/arm/sama5/sama5d3-xplained/configs/ethernet-over-usb-2-high-speed/defconfig +++ b/boards/arm/sama5/sama5d3-xplained/configs/ethernet-over-usb-2-high-speed/defconfig @@ -45,7 +45,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=72 CONFIG_IOB_THROTTLE=16 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NETINIT_NETLOCAL=y CONFIG_NETINIT_NOMAC=y diff --git a/boards/arm/sama5/sama5d3-xplained/configs/nsh/defconfig b/boards/arm/sama5/sama5d3-xplained/configs/nsh/defconfig index 06b763737fd..10f1344fa47 100644 --- a/boards/arm/sama5/sama5d3-xplained/configs/nsh/defconfig +++ b/boards/arm/sama5/sama5d3-xplained/configs/nsh/defconfig @@ -31,7 +31,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y diff --git a/boards/arm/sama5/sama5d3-xplained/scripts/Make.defs b/boards/arm/sama5/sama5d3-xplained/scripts/Make.defs index 06ada43406e..180e5172546 100644 --- a/boards/arm/sama5/sama5d3-xplained/scripts/Make.defs +++ b/boards/arm/sama5/sama5d3-xplained/scripts/Make.defs @@ -60,8 +60,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_ajoystick.c b/boards/arm/sama5/sama5d3-xplained/src/sam_ajoystick.c index 95ae89a47df..7ab59d03644 100644 --- a/boards/arm/sama5/sama5d3-xplained/src/sam_ajoystick.c +++ b/boards/arm/sama5/sama5d3-xplained/src/sam_ajoystick.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_autoleds.c b/boards/arm/sama5/sama5d3-xplained/src/sam_autoleds.c index 7999f8b8c86..70a933ecf01 100644 --- a/boards/arm/sama5/sama5d3-xplained/src/sam_autoleds.c +++ b/boards/arm/sama5/sama5d3-xplained/src/sam_autoleds.c @@ -63,6 +63,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/sama5d3x-ek/README.txt b/boards/arm/sama5/sama5d3x-ek/README.txt index 45559b1d95c..0dc33d34579 100644 --- a/boards/arm/sama5/sama5d3x-ek/README.txt +++ b/boards/arm/sama5/sama5d3x-ek/README.txt @@ -2384,7 +2384,7 @@ CAN Usage Only messages that have IDs that match the CONFIG_SAMA5_CANn_ADDRn when both the received and the configured address are masked by CONFIG_SAMA5_CANn_MASKn - will be accepted. For example, if the mask is all ones, then only messasges + will be accepted. For example, if the mask is all ones, then only messages with exact address matches will be accepted; if the mask is all zeroes than any address will be accepted. diff --git a/boards/arm/sama5/sama5d3x-ek/configs/demo/defconfig b/boards/arm/sama5/sama5d3x-ek/configs/demo/defconfig index 44e421c84cb..49903ffce89 100644 --- a/boards/arm/sama5/sama5d3x-ek/configs/demo/defconfig +++ b/boards/arm/sama5/sama5d3x-ek/configs/demo/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/sama5/sama5d3x-ek/configs/hello/defconfig b/boards/arm/sama5/sama5d3x-ek/configs/hello/defconfig index d68a4b2c943..ffc7205f85d 100644 --- a/boards/arm/sama5/sama5d3x-ek/configs/hello/defconfig +++ b/boards/arm/sama5/sama5d3x-ek/configs/hello/defconfig @@ -22,7 +22,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_EXAMPLES_HELLO=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x00300000 diff --git a/boards/arm/sama5/sama5d3x-ek/configs/norboot/defconfig b/boards/arm/sama5/sama5d3x-ek/configs/norboot/defconfig index 50efb310aac..995e5fc9737 100644 --- a/boards/arm/sama5/sama5d3x-ek/configs/norboot/defconfig +++ b/boards/arm/sama5/sama5d3x-ek/configs/norboot/defconfig @@ -22,7 +22,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_EXAMPLES_HELLO=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x00300000 diff --git a/boards/arm/sama5/sama5d3x-ek/configs/nsh/defconfig b/boards/arm/sama5/sama5d3x-ek/configs/nsh/defconfig index ce9285e6ce9..63c87c37f9f 100644 --- a/boards/arm/sama5/sama5d3x-ek/configs/nsh/defconfig +++ b/boards/arm/sama5/sama5d3x-ek/configs/nsh/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y diff --git a/boards/arm/sama5/sama5d3x-ek/configs/nx/defconfig b/boards/arm/sama5/sama5d3x-ek/configs/nx/defconfig index 1c2a8c7335a..6493bfaaac9 100644 --- a/boards/arm/sama5/sama5d3x-ek/configs/nx/defconfig +++ b/boards/arm/sama5/sama5d3x-ek/configs/nx/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y diff --git a/boards/arm/sama5/sama5d3x-ek/configs/nxplayer/defconfig b/boards/arm/sama5/sama5d3x-ek/configs/nxplayer/defconfig index e426b7402ac..5d0e8212f4d 100644 --- a/boards/arm/sama5/sama5d3x-ek/configs/nxplayer/defconfig +++ b/boards/arm/sama5/sama5d3x-ek/configs/nxplayer/defconfig @@ -39,7 +39,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_I2C=y CONFIG_I2C_RESET=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/sama5/sama5d3x-ek/configs/nxwm/defconfig b/boards/arm/sama5/sama5d3x-ek/configs/nxwm/defconfig index a8e42f54664..ea4989893a5 100644 --- a/boards/arm/sama5/sama5d3x-ek/configs/nxwm/defconfig +++ b/boards/arm/sama5/sama5d3x-ek/configs/nxwm/defconfig @@ -30,7 +30,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/sama5/sama5d3x-ek/configs/ov2640/defconfig b/boards/arm/sama5/sama5d3x-ek/configs/ov2640/defconfig index 9c04e0c4f00..ed89e8d319e 100644 --- a/boards/arm/sama5/sama5d3x-ek/configs/ov2640/defconfig +++ b/boards/arm/sama5/sama5d3x-ek/configs/ov2640/defconfig @@ -25,7 +25,6 @@ CONFIG_FLASH_START=0x10000000 CONFIG_FLASH_VSTART=0x10000000 CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 diff --git a/boards/arm/sama5/sama5d3x-ek/scripts/Make.defs b/boards/arm/sama5/sama5d3x-ek/scripts/Make.defs index 61ea08023e2..1a7eabfc28e 100644 --- a/boards/arm/sama5/sama5d3x-ek/scripts/Make.defs +++ b/boards/arm/sama5/sama5d3x-ek/scripts/Make.defs @@ -80,8 +80,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_autoleds.c b/boards/arm/sama5/sama5d3x-ek/src/sam_autoleds.c index a00192257ca..d4447c15896 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sam_autoleds.c +++ b/boards/arm/sama5/sama5d3x-ek/src/sam_autoleds.c @@ -63,6 +63,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_touchscreen.c b/boards/arm/sama5/sama5d3x-ek/src/sam_touchscreen.c index a264bbb7aa6..6be29486816 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sam_touchscreen.c +++ b/boards/arm/sama5/sama5d3x-ek/src/sam_touchscreen.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/sama5d4-ek/configs/at25boot/defconfig b/boards/arm/sama5/sama5d4-ek/configs/at25boot/defconfig index a8dcaa49631..40d4b240263 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/at25boot/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/at25boot/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HEX2BIN=y -CONFIG_MAX_TASKS=16 CONFIG_MTD=y CONFIG_MTD_AT25=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/sama5/sama5d4-ek/configs/bridge/defconfig b/boards/arm/sama5/sama5d4-ek/configs/bridge/defconfig index 3904b76d662..a6f3f773563 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/bridge/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/bridge/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NET_ARP_SEND=y diff --git a/boards/arm/sama5/sama5d4-ek/configs/dramboot/defconfig b/boards/arm/sama5/sama5d4-ek/configs/dramboot/defconfig index b5f24ce3f61..3c6aed89e33 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/dramboot/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/dramboot/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HEX2BIN=y -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x00200000 diff --git a/boards/arm/sama5/sama5d4-ek/configs/elf/defconfig b/boards/arm/sama5/sama5d4-ek/configs/elf/defconfig index e47e920ab3d..b233920575d 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/elf/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/elf/defconfig @@ -29,6 +29,7 @@ CONFIG_ARCH_PGPOOL_VBASE=0x28000000 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_TEXT_NPAGES=256 CONFIG_ARCH_TEXT_VBASE=0x80000000 +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=65775 CONFIG_BOOT_RUNFROMSDRAM=y @@ -47,8 +48,8 @@ CONFIG_HOST_WINDOWS=y CONFIG_I2C=y CONFIG_I2C_RESET=y CONFIG_INTELHEX_BINARY=y +CONFIG_LIB_BOARDCTL=y CONFIG_LIB_SYSCALL=y -CONFIG_MAX_TASKS=16 CONFIG_MM_PGALLOC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=268435456 diff --git a/boards/arm/sama5/sama5d4-ek/configs/ipv6/defconfig b/boards/arm/sama5/sama5d4-ek/configs/ipv6/defconfig index 5668b8369f5..c4330688878 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/ipv6/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/ipv6/defconfig @@ -53,7 +53,6 @@ CONFIG_I2C_RESET=y CONFIG_INPUT=y CONFIG_INPUT_MXT=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/sama5/sama5d4-ek/configs/knsh/Make.defs b/boards/arm/sama5/sama5d4-ek/configs/knsh/Make.defs index 9f210c83810..edd107f68eb 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/knsh/Make.defs +++ b/boards/arm/sama5/sama5d4-ek/configs/knsh/Make.defs @@ -67,8 +67,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/sama5/sama5d4-ek/configs/knsh/defconfig b/boards/arm/sama5/sama5d4-ek/configs/knsh/defconfig index c5f7f328dd0..e97cc987b44 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/knsh/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/knsh/defconfig @@ -48,7 +48,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_EXECFUNCS=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y @@ -85,5 +84,5 @@ CONFIG_SCHED_WAITPID=y CONFIG_SDIO_BLOCKSETUP=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_PROGNAME="init" -CONFIG_SYS_RESERVED=6 +CONFIG_SYS_RESERVED=7 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/sama5/sama5d4-ek/configs/nsh/defconfig b/boards/arm/sama5/sama5d4-ek/configs/nsh/defconfig index cc3260309e6..86bd6ca98eb 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/nsh/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/nsh/defconfig @@ -53,7 +53,6 @@ CONFIG_INPUT=y CONFIG_INPUT_MXT=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HOSTNAME="SAMA5D4-EK" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/sama5/sama5d4-ek/configs/nxwm/defconfig b/boards/arm/sama5/sama5d4-ek/configs/nxwm/defconfig index 352c82e04e0..172d3db763e 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/nxwm/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/nxwm/defconfig @@ -55,7 +55,6 @@ CONFIG_INPUT_MXT=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/sama5/sama5d4-ek/configs/ramtest/defconfig b/boards/arm/sama5/sama5d4-ek/configs/ramtest/defconfig index f65c5937243..da6dcfd792a 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/ramtest/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/ramtest/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLEBG=y CONFIG_NSH_DISABLESCRIPT=y diff --git a/boards/arm/sama5/sama5d4-ek/scripts/Make.defs b/boards/arm/sama5/sama5d4-ek/scripts/Make.defs index b22c39e5a3a..ae2a2bead04 100644 --- a/boards/arm/sama5/sama5d4-ek/scripts/Make.defs +++ b/boards/arm/sama5/sama5d4-ek/scripts/Make.defs @@ -64,8 +64,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/sama5/sama5d4-ek/src/sam_autoleds.c b/boards/arm/sama5/sama5d4-ek/src/sam_autoleds.c index a18c83fdacb..d301aa6ccba 100644 --- a/boards/arm/sama5/sama5d4-ek/src/sam_autoleds.c +++ b/boards/arm/sama5/sama5d4-ek/src/sam_autoleds.c @@ -69,6 +69,7 @@ #include #include +#include #include #include diff --git a/boards/arm/sama5/sama5d4-ek/src/sam_automount.c b/boards/arm/sama5/sama5d4-ek/src/sam_automount.c index a3492b60d79..9a19d261828 100644 --- a/boards/arm/sama5/sama5d4-ek/src/sam_automount.c +++ b/boards/arm/sama5/sama5d4-ek/src/sam_automount.c @@ -28,6 +28,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/samd2l2/arduino-m0/configs/nsh/defconfig b/boards/arm/samd2l2/arduino-m0/configs/nsh/defconfig index b41092e1038..a1d561f39ff 100644 --- a/boards/arm/samd2l2/arduino-m0/configs/nsh/defconfig +++ b/boards/arm/samd2l2/arduino-m0/configs/nsh/defconfig @@ -36,7 +36,6 @@ CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_DEFAULT=1536 diff --git a/boards/arm/samd2l2/arduino-m0/configs/usbnsh/defconfig b/boards/arm/samd2l2/arduino-m0/configs/usbnsh/defconfig index 28eacddb370..49ef0234ec4 100644 --- a/boards/arm/samd2l2/arduino-m0/configs/usbnsh/defconfig +++ b/boards/arm/samd2l2/arduino-m0/configs/usbnsh/defconfig @@ -39,7 +39,6 @@ CONFIG_CDCACM_CONSOLE=y CONFIG_DEFAULT_SMALL=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_DEFAULT=1536 diff --git a/boards/arm/samd2l2/arduino-m0/scripts/Make.defs b/boards/arm/samd2l2/arduino-m0/scripts/Make.defs index 4812abaf9bb..1946a0b8d50 100644 --- a/boards/arm/samd2l2/arduino-m0/scripts/Make.defs +++ b/boards/arm/samd2l2/arduino-m0/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/samd2l2/arduino-m0/src/sam_autoleds.c b/boards/arm/samd2l2/arduino-m0/src/sam_autoleds.c index e8631fb0fd3..b03e67ce014 100644 --- a/boards/arm/samd2l2/arduino-m0/src/sam_autoleds.c +++ b/boards/arm/samd2l2/arduino-m0/src/sam_autoleds.c @@ -47,6 +47,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samd2l2/circuit-express/Kconfig b/boards/arm/samd2l2/circuit-express/Kconfig new file mode 100644 index 00000000000..4570caee258 --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/Kconfig @@ -0,0 +1,9 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_CIRCUIT_EXPRESS + +endif + diff --git a/boards/arm/samd2l2/circuit-express/configs/nsh/defconfig b/boards/arm/samd2l2/circuit-express/configs/nsh/defconfig new file mode 100644 index 00000000000..2c0cddfee82 --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/configs/nsh/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="circuit-express" +CONFIG_ARCH_BOARD_CIRCUIT_EXPRESS=y +CONFIG_ARCH_CHIP="samd2l2" +CONFIG_ARCH_CHIP_SAMD21G18A=y +CONFIG_ARCH_CHIP_SAMD2X=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3410 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WARN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=32768 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SAMD2L2_SERCOM4=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=21 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2015 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_USART4_RXBUFSIZE=64 +CONFIG_USART4_SERIAL_CONSOLE=y +CONFIG_USART4_TXBUFSIZE=64 +CONFIG_USERMAIN_STACKSIZE=1536 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/samd2l2/circuit-express/configs/usbnsh/defconfig b/boards/arm/samd2l2/circuit-express/configs/usbnsh/defconfig new file mode 100644 index 00000000000..74b059b96c9 --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/configs/usbnsh/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="circuit-express" +CONFIG_ARCH_BOARD_CIRCUIT_EXPRESS=y +CONFIG_ARCH_CHIP="samd2l2" +CONFIG_ARCH_CHIP_SAMD21G18A=y +CONFIG_ARCH_CHIP_SAMD2X=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3410 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_USBCONSOLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=32768 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SAMD2L2_SERCOM4=y +CONFIG_SAMD2L2_USB=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=21 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2015 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_USART4_RXBUFSIZE=64 +CONFIG_USART4_SERIAL_CONSOLE=y +CONFIG_USART4_TXBUFSIZE=64 +CONFIG_USBDEV=y +CONFIG_USERMAIN_STACKSIZE=1536 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/samd2l2/circuit-express/include/board.h b/boards/arm/samd2l2/circuit-express/include/board.h new file mode 100644 index 00000000000..f55fc80c7e8 --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/include/board.h @@ -0,0 +1,410 @@ +/**************************************************************************** + * boards/arm/samd2l2/circuit-express/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_INCLUDE_BOARD_H +#define __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# ifdef CONFIG_SAMD2L2_GPIOIRQ +# include +# endif +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Overview + * + * OSC8M Output = 8MHz + * `- GCLK1 Input = 8MHz Prescaler = 1 output = 8MHz + * `- DFLL Input = 8MHz Multiplier = 6 output = 48MHz + * `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz + * `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz + * APBA divider = 1 APBA frequency = 48MHz + * APBB divider = 1 APBB frequency = 48MHz + * APBC divider = 1 APBC frequency = 48MHz + * + */ + +/* XOSC Configuration -- Not available + * + * BOARD_XOSC_ENABLE - Boolean (defined / not defined) + * BOARD_XOSC_FREQUENCY - In Hz + * BOARD_XOSC_STARTUPTIME - See SYSCTRL_XOSC_STARTUP_* definitions + * BOARD_XOSC_ISCRYSTAL - Boolean (defined / not defined) + * BOARD_XOSC_AMPGC - Boolean (defined / not defined) + * BOARD_XOSC_ONDEMAND - Boolean (defined / not defined) + * BOARD_XOSC_RUNINSTANDBY - Boolean (defined / not defined) + */ + +#undef BOARD_XOSC_ENABLE +#define BOARD_XOSC_FREQUENCY 12000000UL +#define BOARD_XOSC_STARTUPTIME SYSCTRL_XOSC_STARTUP_1S +#define BOARD_XOSC_ISCRYSTAL 1 +#define BOARD_XOSC_AMPGC 1 +#define BOARD_XOSC_ONDEMAND 1 +#undef BOARD_XOSC_RUNINSTANDBY + +/* XOSC32 Configuration -- Not used + * + * BOARD_XOSC32K_ENABLE - Boolean (defined / not defined) + * BOARD_XOSC32K_FREQUENCY - In Hz + * BOARD_XOSC32K_STARTUPTIME - See SYSCTRL_XOSC32K_STARTUP_* definitions + * BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined) + * BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined) + * BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined) + * BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined) + * BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined) + * BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined) + */ + +#undef BOARD_XOSC32K_ENABLE +#define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */ +#define BOARD_XOSC32K_STARTUPTIME SYSCTRL_XOSC32K_STARTUP_2S +#define BOARD_XOSC32K_ISCRYSTAL 1 +#define BOARD_XOSC32K_AAMPEN 1 +#undef BOARD_XOSC32K_EN1KHZ +#define BOARD_XOSC32K_EN32KHZ 1 +#define BOARD_XOSC32K_ONDEMAND 1 +#undef BOARD_XOSC32K_RUNINSTANDBY + +/* OSC32 Configuration -- not used + * + * BOARD_OSC32K_ENABLE - Boolean (defined / not defined) + * BOARD_OSC32K_FREQUENCY - In Hz + * BOARD_OSC32K_STARTUPTIME - See SYSCTRL_OSC32K_STARTUP_* definitions + * BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined) + * BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined) + * BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined) + * BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined) + */ + +#undef BOARD_OSC32K_ENABLE +#define BOARD_OSC32K_FREQUENCY 32768 /* 32.768kHz internal oscillator */ +#define BOARD_OSC32K_STARTUPTIME SYSCTRL_OSC32K_STARTUP_4MS +#define BOARD_OSC32K_EN1KHZ 1 +#define BOARD_OSC32K_EN32KHZ 1 +#define BOARD_OSC32K_ONDEMAND 1 +#undef BOARD_OSC32K_RUNINSTANDBY + +/* OSC8M Configuration -- always enabled + * + * BOARD_OSC8M_PRESCALER - See SYSCTRL_OSC8M_PRESC_DIV* definitions + * BOARD_OSC8M_ONDEMAND - Boolean (defined / not defined) + * BOARD_OSC8M_RUNINSTANDBY - Boolean (defined / not defined) + */ + +#define BOARD_OSC8M_PRESCALER SYSCTRL_OSC8M_PRESC_DIV1 +#define BOARD_OSC8M_ONDEMAND 1 +#undef BOARD_OSC8M_RUNINSTANDBY + +#define BOARD_OSC8M_FREQUENCY 8000000 /* 8MHz high-accuracy internal oscillator */ + +/* OSCULP32K Configuration -- not used. */ + +#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */ + +/* Digital Frequency Locked Loop configuration. In closed-loop mode, the + * DFLL output frequency (Fdfll) is given by: + * + * Fdfll = DFLLmul * Frefclk + * = 6 * 8000000 = 48MHz + * + * Where the reference clock is Generic Clock Channel 0 output of GLCK1. + * GCLCK1 provides OSC8M, undivided. + * + * When operating in open-loop mode, the output frequency of the DFLL will + * be determined by the values written to the DFLL Coarse Value bit group + * and the DFLL Fine Value bit group in the DFLL Value register. + * + * BOARD_DFLL_OPENLOOP - Boolean (defined / not defined) + * BOARD_DFLL_TRACKAFTERFINELOCK - Boolean (defined / not defined) + * BOARD_DFLL_KEEPLOCKONWAKEUP - Boolean (defined / not defined) + * BOARD_DFLL_ENABLECHILLCYCLE - Boolean (defined / not defined) + * BOARD_DFLL_QUICKLOCK - Boolean (defined / not defined) + * BOARD_DFLL_ONDEMAND - Boolean (defined / not defined) + * + * Closed loop mode only: + * BOARD_DFLL_GCLKGEN - GCLK index + * BOARD_DFLL_MULTIPLIER - Value + * BOARD_DFLL_MAXCOARSESTEP - Value + * BOARD_DFLL_MAXFINESTEP - Value + * + * BOARD_DFLL_FREQUENCY - The resulting frequency + */ + +#define BOARD_DFLL_ENABLE 1 +#define BOARD_DFLL_OPENLOOP 1 +#undef BOARD_DFLL_ONDEMAND +#undef BOARD_DFLL_RUNINSTANDBY + +/* DFLL closed loop mode configuration */ + +#define BOARD_DFLL_SRCGCLKGEN 1 +#define BOARD_DFLL_MULTIPLIER 6 +#define BOARD_DFLL_QUICKLOCK 1 +#define BOARD_DFLL_TRACKAFTERFINELOCK 1 +#define BOARD_DFLL_KEEPLOCKONWAKEUP 1 +#define BOARD_DFLL_ENABLECHILLCYCLE 1 +#define BOARD_DFLL_MAXCOARSESTEP (0x1f / 4) +#define BOARD_DFLL_MAXFINESTEP (0xff / 4) + +#define BOARD_DFLL_FREQUENCY (48000000) + +/* GCLK Configuration + * + * Global enable/disable. + * + * BOARD_GCLK_ENABLE - Boolean (defined / not defined) + * + * For n=1-7: + * BOARD_GCLKn_ENABLE - Boolean (defined / not defined) + * + * For n=0-8: + * BOARD_GCLKn_RUN_IN_STANDBY - Boolean (defined / not defined) + * BOARD_GCLKn_CLOCK_SOURCE - See GCLK_GENCTRL_SRC_* definitions + * BOARD_GCLKn_PRESCALER - Value + * BOARD_GCLKn_OUTPUT_ENABLE - Boolean (defined / not defined) + */ + +#define BOARD_GCLK_ENABLE 1 + +/* GCLK generator 0 (Main Clock) - Source is the DFLL */ + +#undef BOARD_GCLK0_RUN_IN_STANDBY +#define BOARD_GCLK0_CLOCK_SOURCE GCLK_GENCTRL_SRC_DFLL48M +#define BOARD_GCLK0_PRESCALER 1 +#undef BOARD_GCLK0_OUTPUT_ENABLE +#define BOARD_GCLK0_FREQUENCY (BOARD_DFLL_FREQUENCY / BOARD_GCLK0_PRESCALER) + +/* Configure GCLK generator 1 - Drives the DFLL */ + +#define BOARD_GCLK1_ENABLE 1 +#undef BOARD_GCLK1_RUN_IN_STANDBY +#define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M +#define BOARD_GCLK1_PRESCALER 1 +#undef BOARD_GCLK1_OUTPUT_ENABLE +#define BOARD_GCLK1_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK1_PRESCALER) + +/* Configure GCLK generator 2 (RTC) */ + +#undef BOARD_GCLK2_ENABLE +#undef BOARD_GCLK2_RUN_IN_STANDBY +#define BOARD_GCLK2_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC32K +#define BOARD_GCLK2_PRESCALER 32 +#undef BOARD_GCLK2_OUTPUT_ENABLE +#define BOARD_GCLK2_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK2_PRESCALER) + +/* Configure GCLK generator 3 */ + +#undef BOARD_GCLK3_ENABLE +#undef BOARD_GCLK3_RUN_IN_STANDBY +#define BOARD_GCLK3_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M +#define BOARD_GCLK3_PRESCALER 1 +#undef BOARD_GCLK3_OUTPUT_ENABLE +#define BOARD_GCLK3_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK3_PRESCALER) + +/* Configure GCLK generator 4 */ + +#undef BOARD_GCLK4_ENABLE +#undef BOARD_GCLK4_RUN_IN_STANDBY +#define BOARD_GCLK4_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M +#define BOARD_GCLK4_PRESCALER 1 +#undef BOARD_GCLK4_OUTPUT_ENABLE +#define BOARD_GCLK4_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK4_PRESCALER) + +/* Configure GCLK generator 5 */ + +#undef BOARD_GCLK5_ENABLE +#undef BOARD_GCLK5_RUN_IN_STANDBY +#define BOARD_GCLK5_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M +#define BOARD_GCLK5_PRESCALER 1 +#undef BOARD_GCLK5_OUTPUT_ENABLE +#define BOARD_GCLK5_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK5_PRESCALER) + +/* Configure GCLK generator 6 */ + +#undef BOARD_GCLK6_ENABLE +#undef BOARD_GCLK6_RUN_IN_STANDBY +#define BOARD_GCLK6_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M +#define BOARD_GCLK6_PRESCALER 1 +#undef BOARD_GCLK6_OUTPUT_ENABLE +#define BOARD_GCLK6_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK6_PRESCALER) + +/* Configure GCLK generator 7 */ + +#undef BOARD_GCLK7_ENABLE +#undef BOARD_GCLK7_RUN_IN_STANDBY +#define BOARD_GCLK7_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M +#define BOARD_GCLK7_PRESCALER 1 +#undef BOARD_GCLK7_OUTPUT_ENABLE +#define BOARD_GCLK7_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK7_PRESCALER) + +/* The source of the main clock is always GCLK_MAIN. Also called GCLKGEN[0], + * this is the clock feeding the Power Manager. + * The Power Manager, in turn, generates main clock which is divided down to + * produce the CPU, AHB, and APB clocks. + * + * The main clock is initially OSC8M divided by 8. + */ + +#define BOARD_GCLK_MAIN_FREQUENCY BOARD_GCLK0_FREQUENCY + +/* Main clock dividers + * + * BOARD_CPU_DIVIDER - See PM_CPUSEL_CPUDIV_* definitions + * BOARD_CPU_FRQUENCY - In Hz + * BOARD_CPU_FAILDECT - Boolean (defined / not defined) + * BOARD_APBA_DIVIDER - See M_APBASEL_APBADIV_* definitions + * BOARD_APBA_FRQUENCY - In Hz + * BOARD_APBB_DIVIDER - See M_APBBSEL_APBBDIV_* definitions + * BOARD_APBB_FRQUENCY - In Hz + * BOARD_APBC_DIVIDER - See M_APBCSEL_APBCDIV_* definitions + * BOARD_APBC_FRQUENCY - In Hz + */ + +#define BOARD_CPU_FAILDECT 1 +#define BOARD_CPU_DIVIDER PM_CPUSEL_CPUDIV_1 +#define BOARD_APBA_DIVIDER PM_APBASEL_APBADIV_1 +#define BOARD_APBB_DIVIDER PM_APBBSEL_APBBDIV_1 +#define BOARD_APBC_DIVIDER PM_APBCSEL_APBCDIV_1 + +/* Resulting frequencies */ + +#define BOARD_MCK_FREQUENCY (BOARD_GCLK_MAIN_FREQUENCY) +#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY) +#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY) +#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY) +#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY) +#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY) + +/* FLASH wait states + * + * Vdd Range Wait states Maximum Operating Frequency + * ------------- -------------- --------------------------- + * 1.62V to 2.7V 0 14 MHz + * 1 28 MHz + * 2 42 MHz + * 3 48 MHz + * 2.7V to 3.63V 0 24 MHz + * 1 48 MHz + */ + +#if 0 /* REVISIT -- should not be necessary */ +# define BOARD_FLASH_WAITSTATES 1 +#else +# define BOARD_FLASH_WAITSTATES 2 +#endif + +/* SERCOM definitions *******************************************************/ + +/* This is the source clock generator for the GCLK_SERCOM_SLOW clock that is + * common to all SERCOM modules. + */ + +#define BOARD_SERCOM05_SLOW_GCLKGEN 0 + +/* SERCOM5 USART used to Serial Console + * + * PIN PORT SERCOM FUNCTION + * --- ------------------ ----------- + * 7 PB08 SERCOM4 PAD0 USART TXD + * 8 PB09 SERCOM4 PAD1 USART RXD + */ + +#define BOARD_SERCOM4_GCLKGEN 0 +#define BOARD_SERCOM4_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN +#define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0_1) +#define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3 /* USART 4 TXD */ +#define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_3 /* USART 4 RXD */ +#define BOARD_SERCOM4_PINMAP_PAD2 0 +#define BOARD_SERCOM4_PINMAP_PAD3 0 + +#define BOARD_SERCOM4_FREQUENCY BOARD_GCLK0_FREQUENCY + +/* USB definitions **********************************************************/ + +/* This is the source clock generator for the GCLK_USB clock + */ + +#define BOARD_USB_GCLKGEN 0 +#define BOARD_USB_FREQUENCY BOARD_GCLK0_FREQUENCY + +/* default USB Pad calibration (not used yet by USB driver) */ + +#define BOARD_USB_PADCAL_P 29 +#define BOARD_USB_PADCAL_N 5 +#define BOARD_USB_PADCAL_TRIM 3 + +/* LED definitions **********************************************************/ + +/* There are 2 LEDs on board the Adafruit Circuit Express board in addition + * to the neopixel LEDs. + * The power ON LED which is connected to the 3.3V rail. + * D13 which is an active high user status LED. + * + * This user LED is controlled by PA17. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_STATUS_LED 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_STATUS LED_BIT (1 << BOARD_STATUS_LED) + +/* When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + * control the LED as defined below. Thus if the LED is statically on, NuttX + * has successfully booted and is, apparently, running normally. + * If the LED is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 /* STATUS LED=OFF */ +#define LED_HEAPALLOCATE 0 /* STATUS LED=OFF */ +#define LED_IRQSENABLED 0 /* STATUS LED=OFF */ +#define LED_STACKCREATED 1 /* STATUS LED=ON */ +#define LED_INIRQ 2 /* STATUS LED=no change */ +#define LED_SIGNAL 2 /* STATUS LED=no change */ +#define LED_ASSERTION 2 /* STATUS LED=no change */ +#define LED_PANIC 3 /* STATUS LED=flashing */ + +/* Button definitions *******************************************************/ + +/* Mechanical buttons: + * + * The Adafruit Circuit Express contains 2 mechanical buttons and a switch. + */ + +#define NUM_BUTTONS 3 + +#endif /* __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_INCLUDE_BOARD_H */ diff --git a/boards/arm/samd2l2/circuit-express/scripts/Make.defs b/boards/arm/samd2l2/circuit-express/scripts/Make.defs new file mode 100644 index 00000000000..9315c22eb8c --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/scripts/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/samd2l2/circuit-express/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif diff --git a/boards/arm/samd2l2/circuit-express/scripts/flash.ld b/boards/arm/samd2l2/circuit-express/scripts/flash.ld new file mode 100644 index 00000000000..04c873df597 --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/scripts/flash.ld @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/samd2l2/circuit-express/scripts/flash.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The ATSAMD21G18A has 256KB of FLASH beginning at address 0x0000:0000 and + * 32KB of SRAM beginning at address 0x2000:0000 + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } >flash + + .ARM.exidx : { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >flash + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/samd2l2/circuit-express/src/Makefile b/boards/arm/samd2l2/circuit-express/src/Makefile new file mode 100644 index 00000000000..e210f706aea --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/src/Makefile @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/samd2l2/circuit-express/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = sam_boot.c sam_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += sam_autoleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += sam_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += sam_appinit.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += sam_usb.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/samd2l2/circuit-express/src/circuit_express.h b/boards/arm/samd2l2/circuit-express/src/circuit_express.h new file mode 100644 index 00000000000..6967e179b97 --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/src/circuit_express.h @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/samd2l2/circuit-express/src/circuit_express.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_SRC_CIRCUIT_EXPRESS_H +#define __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_SRC_CIRCUIT_EXPRESS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include + +#include "sam_config.h" +#include "sam_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDs: + * There is a LED on board the Circuit Express board. + * + * This LED is controlled by PA17 and the LED can be activated by driving + * PA17 to High. + * + * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + * control the LED as follows: + * + * SYMBOL Meaning LED + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt N/C + * LED_SIGNAL In a signal handler N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +#define PORT_STATUS_LED (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \ + PORTA | PORT_PIN17) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int sam_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_SRC_CIRCUIT_EXPRESS_H */ diff --git a/boards/arm/samd2l2/circuit-express/src/sam_appinit.c b/boards/arm/samd2l2/circuit-express/src/sam_appinit.c new file mode 100644 index 00000000000..7730356ffa7 --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/src/sam_appinit.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/samd2l2/circuit-express/src/sam_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "sam_config.h" +#include "circuit_express.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + return OK; +} diff --git a/boards/arm/samd2l2/circuit-express/src/sam_autoleds.c b/boards/arm/samd2l2/circuit-express/src/sam_autoleds.c new file mode 100644 index 00000000000..fede758bdfe --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/src/sam_autoleds.c @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/samd2l2/circuit-express/src/sam_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* There is a LED on board the Circuit Express board. + * + * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + * control the LED as follows: + * + * SYMBOL Meaning LED + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt** N/C + * LED_SIGNAL In a signal handler*** N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "sam_port.h" +#include "circuit_express.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + sam_configport(PORT_STATUS_LED); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case 0: /* LED_STARTED: NuttX has been started STATUS LED=OFF + * LED_HEAPALLOCATE: Heap has been allocated STATUS LED=OFF + * LED_IRQSENABLED: Interrupts enabled STATUS LED=OFF + */ + + break; /* Leave ledstate == true to turn OFF */ + + default: + case 2: /* LED_INIRQ: In an interrupt STATUS LED=N/C + * LED_SIGNAL: In a signal handler STATUS LED=N/C + * LED_ASSERTION: An assertion failed STATUS LED=N/C + */ + + return; /* Return to leave STATUS LED unchanged */ + + case 3: /* LED_PANIC: The system has crashed STATUS LED=FLASH */ + case 1: /* LED_STACKCREATED: Idle stack created STATUS LED=ON */ + sam_portwrite(PORT_STATUS_LED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + /* These should not happen and are ignored */ + + default: + case 0: /* LED_STARTED: NuttX has been started STATUS LED=OFF + * LED_HEAPALLOCATE: Heap has been allocated STATUS LED=OFF + * LED_IRQSENABLED: Interrupts enabled STATUS LED=OFF + */ + + case 1: /* LED_STACKCREATED: Idle stack created STATUS LED=ON */ + + /* These result in no-change */ + + case 2: /* LED_INIRQ: In an interrupt STATUS LED=N/C + * LED_SIGNAL: In a signal handler STATUS LED=N/C + * LED_ASSERTION: An assertion failed STATUS LED=N/C + */ + + return; /* Return to leave STATUS LED unchanged */ + + /* Turn STATUS LED off set driving the output high */ + + case 3: /* LED_PANIC: The system has crashed STATUS LED=FLASH */ + sam_portwrite(PORT_STATUS_LED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/samd2l2/circuit-express/src/sam_boot.c b/boards/arm/samd2l2/circuit-express/src/sam_boot.c new file mode 100644 index 00000000000..e45589e432d --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/src/sam_boot.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/samd2l2/circuit-express/src/sam_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "sam_config.h" +#include "circuit_express.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_boardinitialize + * + * Description: + * All SAMD21 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void sam_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + (void)sam_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/samd2l2/circuit-express/src/sam_bringup.c b/boards/arm/samd2l2/circuit-express/src/sam_bringup.c new file mode 100644 index 00000000000..7e281a986f6 --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/src/sam_bringup.c @@ -0,0 +1,60 @@ +/**************************************************************************** + * boards/arm/samd2l2/circuit-express/src/sam_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "sam_config.h" +#include "circuit_express.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int sam_bringup(void) +{ + int ret = OK; + + return ret; +} diff --git a/boards/arm/samd2l2/circuit-express/src/sam_usb.c b/boards/arm/samd2l2/circuit-express/src/sam_usb.c new file mode 100644 index 00000000000..eed0eca887b --- /dev/null +++ b/boards/arm/samd2l2/circuit-express/src/sam_usb.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/samd2l2/circuit-express/src/sam_usb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "debug.h" +#include "chip.h" +#include "sam_port.h" +#include "saml_periphclks.h" +#include "circuit_express.h" + +#if defined(CONFIG_SAMD2L2_USB) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_usbinitialize + * + * Description: + * Called from sam_boot very early in initialization to setup + * USB-related GPIO pins for the Circuit Express board. + * + * USB Ports + * The SAML21 features USB device and host: + * + * + ****************************************************************************/ + +void weak_function sam_usbinitialize(void) +{ +} + +/**************************************************************************** + * Name: sam_usbsuspend + * + * Description: + * Board logic must provide the sam_usbsuspend logic if the USBDEV driver + * is used. + * This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void sam_usb_suspend(FAR struct usbdev_s *dev, bool resume) +{ + uinfo("board: resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_SAMDL_USB */ diff --git a/boards/arm/samd2l2/samd20-xplained/configs/nsh/defconfig b/boards/arm/samd2l2/samd20-xplained/configs/nsh/defconfig index 0aa8638b11a..ccd51028734 100644 --- a/boards/arm/samd2l2/samd20-xplained/configs/nsh/defconfig +++ b/boards/arm/samd2l2/samd20-xplained/configs/nsh/defconfig @@ -38,7 +38,6 @@ CONFIG_DEFAULT_SMALL=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_DEFAULT=1536 diff --git a/boards/arm/samd2l2/samd20-xplained/scripts/Make.defs b/boards/arm/samd2l2/samd20-xplained/scripts/Make.defs index 0eb235c05fb..bdb95d1af23 100644 --- a/boards/arm/samd2l2/samd20-xplained/scripts/Make.defs +++ b/boards/arm/samd2l2/samd20-xplained/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/samd2l2/samd20-xplained/src/sam_autoleds.c b/boards/arm/samd2l2/samd20-xplained/src/sam_autoleds.c index e2b05f09387..279f4de5d62 100644 --- a/boards/arm/samd2l2/samd20-xplained/src/sam_autoleds.c +++ b/boards/arm/samd2l2/samd20-xplained/src/sam_autoleds.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samd2l2/samd21-xplained/configs/nsh/defconfig b/boards/arm/samd2l2/samd21-xplained/configs/nsh/defconfig index b8e347252b6..32bc756f0ad 100644 --- a/boards/arm/samd2l2/samd21-xplained/configs/nsh/defconfig +++ b/boards/arm/samd2l2/samd21-xplained/configs/nsh/defconfig @@ -39,7 +39,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_DEFAULT=1536 diff --git a/boards/arm/samd2l2/samd21-xplained/scripts/Make.defs b/boards/arm/samd2l2/samd21-xplained/scripts/Make.defs index 32a222c4462..362cab6f470 100644 --- a/boards/arm/samd2l2/samd21-xplained/scripts/Make.defs +++ b/boards/arm/samd2l2/samd21-xplained/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/samd2l2/samd21-xplained/src/sam_autoleds.c b/boards/arm/samd2l2/samd21-xplained/src/sam_autoleds.c index 7ec2cf0a705..061a8c64a1d 100644 --- a/boards/arm/samd2l2/samd21-xplained/src/sam_autoleds.c +++ b/boards/arm/samd2l2/samd21-xplained/src/sam_autoleds.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samd2l2/saml21-xplained/configs/nsh/defconfig b/boards/arm/samd2l2/saml21-xplained/configs/nsh/defconfig index 9be44bca9d8..ef66e1e1a2c 100644 --- a/boards/arm/samd2l2/saml21-xplained/configs/nsh/defconfig +++ b/boards/arm/samd2l2/saml21-xplained/configs/nsh/defconfig @@ -39,7 +39,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_DEFAULT=1536 diff --git a/boards/arm/samd2l2/saml21-xplained/scripts/Make.defs b/boards/arm/samd2l2/saml21-xplained/scripts/Make.defs index ec264391532..a096d31545e 100644 --- a/boards/arm/samd2l2/saml21-xplained/scripts/Make.defs +++ b/boards/arm/samd2l2/saml21-xplained/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/samd2l2/saml21-xplained/src/sam_autoleds.c b/boards/arm/samd2l2/saml21-xplained/src/sam_autoleds.c index 6d14a5cd364..d291b9ad6af 100644 --- a/boards/arm/samd2l2/saml21-xplained/src/sam_autoleds.c +++ b/boards/arm/samd2l2/saml21-xplained/src/sam_autoleds.c @@ -53,6 +53,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samd5e5/metro-m4/configs/nsh/defconfig b/boards/arm/samd5e5/metro-m4/configs/nsh/defconfig index 12eb6a3279a..2ca5ab6adbc 100644 --- a/boards/arm/samd5e5/metro-m4/configs/nsh/defconfig +++ b/boards/arm/samd5e5/metro-m4/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_BUILTIN=y CONFIG_DISABLE_ENVIRON=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/samd5e5/metro-m4/scripts/Make.defs b/boards/arm/samd5e5/metro-m4/scripts/Make.defs index b5bdfb3adaf..5b553c1f2d8 100644 --- a/boards/arm/samd5e5/metro-m4/scripts/Make.defs +++ b/boards/arm/samd5e5/metro-m4/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/samd5e5/metro-m4/src/sam_autoleds.c b/boards/arm/samd5e5/metro-m4/src/sam_autoleds.c index 768433fceca..4650403cfe4 100644 --- a/boards/arm/samd5e5/metro-m4/src/sam_autoleds.c +++ b/boards/arm/samd5e5/metro-m4/src/sam_autoleds.c @@ -59,6 +59,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samd5e5/metro-m4/src/sam_automount.c b/boards/arm/samd5e5/metro-m4/src/sam_automount.c index 8347e7d8583..3e9ebabca2d 100644 --- a/boards/arm/samd5e5/metro-m4/src/sam_automount.c +++ b/boards/arm/samd5e5/metro-m4/src/sam_automount.c @@ -28,6 +28,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/samd5e5/metro-m4/src/sam_userleds.c b/boards/arm/samd5e5/metro-m4/src/sam_userleds.c index 9f468566cab..6b6e1241d68 100644 --- a/boards/arm/samd5e5/metro-m4/src/sam_userleds.c +++ b/boards/arm/samd5e5/metro-m4/src/sam_userleds.c @@ -40,6 +40,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samd5e5/same54-xplained-pro/configs/nsh/defconfig b/boards/arm/samd5e5/same54-xplained-pro/configs/nsh/defconfig index 761f4e7bd62..559072374f8 100644 --- a/boards/arm/samd5e5/same54-xplained-pro/configs/nsh/defconfig +++ b/boards/arm/samd5e5/same54-xplained-pro/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_BUILTIN=y CONFIG_DISABLE_ENVIRON=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs b/boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs index 08dbd390f0f..0f7ff5de832 100644 --- a/boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs +++ b/boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/samd5e5/same54-xplained-pro/src/sam_autoleds.c b/boards/arm/samd5e5/same54-xplained-pro/src/sam_autoleds.c index 9101a3f4589..2a1f94738b4 100644 --- a/boards/arm/samd5e5/same54-xplained-pro/src/sam_autoleds.c +++ b/boards/arm/samd5e5/same54-xplained-pro/src/sam_autoleds.c @@ -56,6 +56,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samd5e5/same54-xplained-pro/src/sam_userleds.c b/boards/arm/samd5e5/same54-xplained-pro/src/sam_userleds.c index 9c78f777120..8cc99843cad 100644 --- a/boards/arm/samd5e5/same54-xplained-pro/src/sam_userleds.c +++ b/boards/arm/samd5e5/same54-xplained-pro/src/sam_userleds.c @@ -38,6 +38,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samv7/same70-xplained/configs/mrf24j40-starhub/defconfig b/boards/arm/samv7/same70-xplained/configs/mrf24j40-starhub/defconfig index 13d6e05b8bc..437a5d0644e 100644 --- a/boards/arm/samv7/same70-xplained/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/mrf24j40-starhub/defconfig @@ -52,7 +52,6 @@ CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIB_HOSTNAME="MRF24J40-Hub" CONFIG_MAC802154_NTXDESC=32 -CONFIG_MAX_TASKS=16 CONFIG_MTD=y CONFIG_MTD_AT24XX=y CONFIG_MTD_AT25=y diff --git a/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig b/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig index 4b9477949df..ed49a970e7f 100644 --- a/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig @@ -41,7 +41,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_I2CTOOL_MAXBUS=0 CONFIG_IOB_NBUFFERS=24 CONFIG_LIB_HOSTNAME="SAME70-Xplained" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MTD=y diff --git a/boards/arm/samv7/same70-xplained/configs/nsh/defconfig b/boards/arm/samv7/same70-xplained/configs/nsh/defconfig index aed26edc851..9c0c439e862 100644 --- a/boards/arm/samv7/same70-xplained/configs/nsh/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/nsh/defconfig @@ -39,7 +39,6 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_I2CTOOL_MAXBUS=0 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MTD=y diff --git a/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig b/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig index df2f9c627e8..d778b58456f 100644 --- a/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig @@ -42,7 +42,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C_DRIVER=y CONFIG_IOB_NBUFFERS=24 CONFIG_LIB_HOSTNAME="SAME70-Xplained" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=2 @@ -62,7 +61,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ETH_PKTSIZE=870 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/samv7/same70-xplained/kernel/Makefile b/boards/arm/samv7/same70-xplained/kernel/Makefile index d7fe60f775c..bf7b56012b4 100644 --- a/boards/arm/samv7/same70-xplained/kernel/Makefile +++ b/boards/arm/samv7/same70-xplained/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/samv7/same70-xplained/kernel/sam_userspace.c b/boards/arm/samv7/same70-xplained/kernel/sam_userspace.c index e77b2525c16..2cd40031bc2 100644 --- a/boards/arm/samv7/same70-xplained/kernel/sam_userspace.c +++ b/boards/arm/samv7/same70-xplained/kernel/sam_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/samv7/same70-xplained/scripts/Make.defs b/boards/arm/samv7/same70-xplained/scripts/Make.defs index 25a2d9b11c0..565fd44e036 100644 --- a/boards/arm/samv7/same70-xplained/scripts/Make.defs +++ b/boards/arm/samv7/same70-xplained/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/samv7/same70-xplained/src/sam_autoleds.c b/boards/arm/samv7/same70-xplained/src/sam_autoleds.c index 42cce6ebc65..c22330222cb 100644 --- a/boards/arm/samv7/same70-xplained/src/sam_autoleds.c +++ b/boards/arm/samv7/same70-xplained/src/sam_autoleds.c @@ -52,6 +52,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samv7/same70-xplained/src/sam_automount.c b/boards/arm/samv7/same70-xplained/src/sam_automount.c index a20c1448bba..8ce6d585cba 100644 --- a/boards/arm/samv7/same70-xplained/src/sam_automount.c +++ b/boards/arm/samv7/same70-xplained/src/sam_automount.c @@ -28,6 +28,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/samv7/same70-xplained/src/sam_spi.c b/boards/arm/samv7/same70-xplained/src/sam_spi.c index da44ec84bff..24e1557f100 100644 --- a/boards/arm/samv7/same70-xplained/src/sam_spi.c +++ b/boards/arm/samv7/same70-xplained/src/sam_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samv7/samv71-xult/configs/knsh/Make.defs b/boards/arm/samv7/samv71-xult/configs/knsh/Make.defs index 22a2082cfaa..5e73b00c3ac 100644 --- a/boards/arm/samv7/samv71-xult/configs/knsh/Make.defs +++ b/boards/arm/samv7/samv71-xult/configs/knsh/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/samv7/samv71-xult/configs/knsh/defconfig b/boards/arm/samv7/samv71-xult/configs/knsh/defconfig index a5d351f018a..ef32493fb88 100644 --- a/boards/arm/samv7/samv71-xult/configs/knsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/knsh/defconfig @@ -41,7 +41,6 @@ CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_I2CTOOL_MAXBUS=0 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MTD=y @@ -80,6 +79,6 @@ CONFIG_START_YEAR=2015 CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_RAMTEST=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_UART3_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/samv7/samv71-xult/configs/module/defconfig b/boards/arm/samv7/samv71-xult/configs/module/defconfig index 5381087fe10..38fe8b4cf20 100644 --- a/boards/arm/samv7/samv71-xult/configs/module/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/module/defconfig @@ -26,6 +26,7 @@ CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_ICACHE=y CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=51262 CONFIG_BUILTIN=y CONFIG_EXAMPLES_MODULE=y @@ -35,7 +36,6 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_MODULE=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig b/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig index 5a61629559f..cd6b6d8beb0 100644 --- a/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig @@ -52,7 +52,6 @@ CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIB_HOSTNAME="MRF24J40-Hub" CONFIG_MAC802154_NTXDESC=32 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MTD=y diff --git a/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig b/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig index bccfd3b6a61..e5c0fdda937 100644 --- a/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig @@ -46,7 +46,6 @@ CONFIG_I2CTOOL_MAXBUS=0 CONFIG_INPUT=y CONFIG_INPUT_MXT=y CONFIG_LCD=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig b/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig index d8032aeb4e6..242a7cfff92 100644 --- a/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig @@ -41,7 +41,6 @@ CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_I2CTOOL_MAXBUS=0 CONFIG_LIB_HOSTNAME="SAMV71-XULT" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MTD=y diff --git a/boards/arm/samv7/samv71-xult/configs/nsh/defconfig b/boards/arm/samv7/samv71-xult/configs/nsh/defconfig index 5ea7fb9534b..7d5eb70973b 100644 --- a/boards/arm/samv7/samv71-xult/configs/nsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/nsh/defconfig @@ -40,7 +40,6 @@ CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_I2CTOOL_MAXBUS=0 CONFIG_I2C_RESET=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MTD=y diff --git a/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig b/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig index 7054ce27897..7e7f2665df1 100644 --- a/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig @@ -49,7 +49,6 @@ CONFIG_LCD=y CONFIG_LCD_NOGETRUN=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/samv7/samv71-xult/configs/vnc/defconfig b/boards/arm/samv7/samv71-xult/configs/vnc/defconfig index ac75a9637f9..f12f45b5fe1 100644 --- a/boards/arm/samv7/samv71-xult/configs/vnc/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/vnc/defconfig @@ -47,7 +47,6 @@ CONFIG_I2C_DRIVER=y CONFIG_IOB_NBUFFERS=72 CONFIG_IOB_THROTTLE=32 CONFIG_LIB_HOSTNAME="SAMV71-XULT" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig b/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig index b77110dd858..15561864901 100644 --- a/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig @@ -49,7 +49,6 @@ CONFIG_IOB_THROTTLE=32 CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y CONFIG_LIB_HOSTNAME="SAMV71-XULT" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/samv7/samv71-xult/kernel/Makefile b/boards/arm/samv7/samv71-xult/kernel/Makefile index bda98a6124c..cde1a5cdc56 100644 --- a/boards/arm/samv7/samv71-xult/kernel/Makefile +++ b/boards/arm/samv7/samv71-xult/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/samv7/samv71-xult/kernel/sam_userspace.c b/boards/arm/samv7/samv71-xult/kernel/sam_userspace.c index a63cc7c4c4a..01be17d1fc1 100644 --- a/boards/arm/samv7/samv71-xult/kernel/sam_userspace.c +++ b/boards/arm/samv7/samv71-xult/kernel/sam_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/samv7/samv71-xult/scripts/Make.defs b/boards/arm/samv7/samv71-xult/scripts/Make.defs index 681df9192f7..5a47a196347 100644 --- a/boards/arm/samv7/samv71-xult/scripts/Make.defs +++ b/boards/arm/samv7/samv71-xult/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/samv7/samv71-xult/src/Makefile b/boards/arm/samv7/samv71-xult/src/Makefile index 5ffc1e3fd1c..3099fb59b38 100644 --- a/boards/arm/samv7/samv71-xult/src/Makefile +++ b/boards/arm/samv7/samv71-xult/src/Makefile @@ -110,4 +110,8 @@ ifeq ($(CONFIG_IEEE802154_MRF24J40),y) CSRCS += sam_mrf24j40.c endif +ifeq ($(CONFIG_LCD_ST7789),y) +CSRCS += sam_st7789.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/samv7/samv71-xult/src/sam_autoleds.c b/boards/arm/samv7/samv71-xult/src/sam_autoleds.c index 6fd53a81c3b..e7df25b426e 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_autoleds.c +++ b/boards/arm/samv7/samv71-xult/src/sam_autoleds.c @@ -68,6 +68,7 @@ #include #include +#include #include #include diff --git a/boards/arm/samv7/samv71-xult/src/sam_automount.c b/boards/arm/samv7/samv71-xult/src/sam_automount.c index ef7066bd5c7..c6893cb127c 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_automount.c +++ b/boards/arm/samv7/samv71-xult/src/sam_automount.c @@ -28,6 +28,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/samv7/samv71-xult/src/sam_composite.c b/boards/arm/samv7/samv71-xult/src/sam_composite.c index 3be101fff43..42aba3cd3ee 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_composite.c +++ b/boards/arm/samv7/samv71-xult/src/sam_composite.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include "samv71-xult.h" diff --git a/boards/arm/samv7/samv71-xult/src/sam_ili9488.c b/boards/arm/samv7/samv71-xult/src/sam_ili9488.c index eccbecb4dfc..b8ab93a0f56 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_ili9488.c +++ b/boards/arm/samv7/samv71-xult/src/sam_ili9488.c @@ -125,6 +125,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/samv7/samv71-xult/src/sam_spi.c b/boards/arm/samv7/samv71-xult/src/sam_spi.c index fdda3f0a3a2..150cbe431ab 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_spi.c +++ b/boards/arm/samv7/samv71-xult/src/sam_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -73,6 +74,14 @@ void sam_spidev_initialize(void) sam_configgpio(CLICK_MB2_CS); #endif + +#ifdef CONFIG_LCD_ST7789 + /* Enable CS and CMD/DATA for LCD */ + + sam_configgpio(SPI0_NPCS1); + sam_configgpio(GPIO_LCD_CD); +#endif + #endif /* CONFIG_SAMV7_SPI0_MASTER */ #ifdef CONFIG_SAMV7_SPI0_SLAVE @@ -167,6 +176,12 @@ void sam_spi0select(uint32_t devid, bool selected) break; #endif +#ifdef CONFIG_LCD_ST7789 + case SPIDEV_DISPLAY(0): + sam_gpiowrite(SPI0_NPCS1, !selected); + break; +#endif + default: break; } @@ -209,4 +224,45 @@ uint8_t sam_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) } #endif +/**************************************************************************** + * Name: sam_spi[n]cmddata + * + * Description: + * Some SPI devices require an additional control to determine if the SPI + * data being sent is a command or is data. If CONFIG_SPI_CMDDATA then + * this function will be called to different be command and data transfers. + * + * This is often needed, for example, by LCD drivers. Some LCD hardware + * may be configured to use 9-bit data transfers with the 9th bit + * indicating command or data. That same hardware may be configurable, + * instead, to use 8-bit data but to require an additional, board- + * specific GPIO control to distinguish command and data. This function + * would be needed in that latter case. + * + * Input Parameters: + * dev - SPI device info + * devid - Identifies the (logical) device + * + * Returned Value: + * Zero on success; a negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_SAMV7_SPI0_MASTER +int sam_spi0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + if (devid == SPIDEV_DISPLAY(0)) + { + sam_gpiowrite(GPIO_LCD_CD, !cmd); + return OK; + } + else + { + return -ENODEV; + } +} +#endif /* CONFIG_SAMV7_SPI0_MASTER */ +#endif /* CONFIG_SPI_CMDDATA */ + #endif /* CONFIG_SAMV7_SPI */ diff --git a/boards/arm/samv7/samv71-xult/src/sam_st7789.c b/boards/arm/samv7/samv71-xult/src/sam_st7789.c new file mode 100644 index 00000000000..f1430a840ca --- /dev/null +++ b/boards/arm/samv7/samv71-xult/src/sam_st7789.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/samv7/samv71-xult/src/sam_st7789.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "sam_gpio.h" +#include "sam_spi.h" +#include "samv71-xult.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 0 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct spi_dev_s *g_spidev; +static struct lcd_dev_s *g_lcd = NULL; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, but + * with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + sam_configgpio(GPIO_LCD_RST); + + g_spidev = sam_spibus_initialize(LCD_SPI_PORTNO); + if (!g_spidev) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return -ENODEV; + } + + sam_gpiowrite(GPIO_LCD_RST, 0); + up_mdelay(1); + sam_gpiowrite(GPIO_LCD_RST, 1); + up_mdelay(120); + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. This + * allows support for multiple LCD devices. + * + ****************************************************************************/ + +FAR struct lcd_dev_s *board_lcd_getdev(int devno) +{ + g_lcd = st7789_lcdinitialize(g_spidev); + if (!g_lcd) + { + lcderr("ERROR: Failed to bind SPI port 4 to LCD %d\n", devno); + } + else + { + lcdinfo("SPI port 4 bound to LCD %d\n", devno); + return g_lcd; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Turn the display off */ + + g_lcd->setpower(g_lcd, 0); +} diff --git a/boards/arm/samv7/samv71-xult/src/samv71-xult.h b/boards/arm/samv7/samv71-xult/src/samv71-xult.h index 767dc69b25f..343f0068d46 100644 --- a/boards/arm/samv7/samv71-xult/src/samv71-xult.h +++ b/boards/arm/samv7/samv71-xult/src/samv71-xult.h @@ -621,6 +621,17 @@ #define EDBG_CSNO SPI0_CS2 +/* LCD display (over SPI) */ + +#define GPIO_LCD_CD (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \ + GPIO_PORT_PIOB | GPIO_PIN2) + +#define GPIO_LCD_RST (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \ + GPIO_PORT_PIOB | GPIO_PIN3) + +#define SPI0_NPCS1 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \ + GPIO_PORT_PIOD | GPIO_PIN25) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/boards/arm/stm32/axoloti/scripts/Make.defs b/boards/arm/stm32/axoloti/scripts/Make.defs index 98ef55119f7..34acc9f56b6 100644 --- a/boards/arm/stm32/axoloti/scripts/Make.defs +++ b/boards/arm/stm32/axoloti/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/stm32/b-g431b-esc1/Kconfig b/boards/arm/stm32/b-g431b-esc1/Kconfig index ef2d7cf720a..54c75faa436 100644 --- a/boards/arm/stm32/b-g431b-esc1/Kconfig +++ b/boards/arm/stm32/b-g431b-esc1/Kconfig @@ -5,4 +5,16 @@ if ARCH_BOARD_B_G431B_ESC1 +if STM32_FOC + +config BOARD_STM32_BG431BESC1_FOC_VBUS + bool "B-G431B-ESC1 board VBUS sense" + default n + +config BOARD_STM32_BG431BESC1_FOC_POT + bool "B-G431B-ESC1 board POT support" + default n + +endif # STM32_FOC + endif # ARCH_BOARD_B_G431B_ESC1 diff --git a/boards/arm/stm32/b-g431b-esc1/README.txt b/boards/arm/stm32/b-g431b-esc1/README.txt index 7567661b9ea..4b846366bc1 100644 --- a/boards/arm/stm32/b-g431b-esc1/README.txt +++ b/boards/arm/stm32/b-g431b-esc1/README.txt @@ -18,3 +18,44 @@ Configuration Sub-directories --- Configures the NuttShell (nsh) located at apps/examples/nsh. The Configuration enables the serial interfaces on USART2. + + foc_f32 and foc_b16: + --------------------- + FOC examples based on hardware on board. + + Pin configuration: + + Board Function Chip Function Chip Pin Number + -------------- -------------- --------------- + Phase U high TIM1_CH1 PA8 + Phase U low TIM1_CH1N PC13 + Phase V high TIM1_CH2 PA9 + Phase V low TIM1_CH2N PA12 + Phase W high TIM1_CH3 PA10 + Phase W low TIM1_CH3N PB15 + Current U + OPAMP1_VINP PA1 + Current U - OPAMP1_VINM PA3 + Current V + OPAMP2_VINP PA7 + Current V - OPAMP2_VINM PA5 + Current W + OPAMP3_VINP PB0 + Current W - OPAMP3_VINM PB2 + Temperature PB14 + VBUS ADC1_IN1 PA0 + POT ADC1_IN11 PB12 + LED GPIO_PC6 PC6 + ENCO_A/HALL_H1 PB6 + ENCO_B/HALL_H2 PB7 + ENCO_Z/HALL_H3 PB8 + BUTTON GPIO_PC10 PC10 + PWM PA15 + + Current shunt resistance = 0.003 + PGA gain = 16 + Current sense gain = -9.14 (inverted current) + Vbus sense gain = 18k/(18k+169k) = 0.0962 + Vbus min = ? + Vbus max = 25V + Iout max = 40A peak + + IPHASE_RATIO = 1/(R_shunt*gain) = -36.47 + VBUS_RATIO = 1/VBUS_gain = 10.4 diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig new file mode 100644 index 00000000000..0fa92c97ff6 --- /dev/null +++ b/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y +CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_IPHASE_ADC=-2939 +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 +CONFIG_EXAMPLES_FOC_VEL_ADC=y +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_SHUNTS=2 +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig new file mode 100644 index 00000000000..d5485b97c80 --- /dev/null +++ b/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y +CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_IPHASE_ADC=-2939 +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 +CONFIG_EXAMPLES_FOC_VEL_ADC=y +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_SHUNTS=2 +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig index 075b7b456d7..2bcb8c93542 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/b-g431b-esc1/include/board.h b/boards/arm/stm32/b-g431b-esc1/include/board.h index 6a09afebd03..67946a45992 100644 --- a/boards/arm/stm32/b-g431b-esc1/include/board.h +++ b/boards/arm/stm32/b-g431b-esc1/include/board.h @@ -120,6 +120,45 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK #define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) + /* LED definitions **********************************************************/ /* The B-G431B-ESC1 has four user LEDs. @@ -184,4 +223,21 @@ /* Pin Multiplexing Disambiguation ******************************************/ +/* TIM1 configuration *******************************************************/ + +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1NOUT_4 /* TIM1 CH1N - PC13 - U low */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2NOUT_1 /* TIM1 CH2N - PA12 - V low */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3NOUT_3 /* TIM1 CH3N - PB15 - W low */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ + +/* USART2 */ + +#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ +#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ + #endif /* __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs b/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs index 0b32117ba42..db3f58d5c1e 100644 --- a/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs +++ b/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs @@ -57,8 +57,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) @@ -69,7 +69,7 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif # Provide map file needed by the "Memory Allocation" view in Eclipse: -LDFLAGS += -Map=$(TOPDIR)/NuttX.map --gc-sections +LDFLAGS += -Wl,-Map=$(TOPDIR)/NuttX.map -Wl,--gc-sections # Embed absolute path to source file in debug information so that Eclipse # source level debugging won't get confused. See: diff --git a/boards/arm/stm32/b-g431b-esc1/src/Make.defs b/boards/arm/stm32/b-g431b-esc1/src/Make.defs index 6326d8f1de9..c1a08b29ef9 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/Make.defs +++ b/boards/arm/stm32/b-g431b-esc1/src/Make.defs @@ -21,7 +21,7 @@ include $(TOPDIR)/Make.defs ASRCS = -CSRCS = stm32_boot.c +CSRCS = stm32_boot.c stm32_bringup.c ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c @@ -29,10 +29,18 @@ else CSRCS += stm32_userleds.c endif +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif +ifeq ($(CONFIG_STM32_FOC),y) +CSRCS += stm32_foc.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h b/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h index 8de7a38cebc..be372df84da 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h +++ b/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h @@ -57,6 +57,19 @@ #define LED_DRIVER_PATH "/dev/userleds" +/* Button definitions *******************************************************/ + +/* The B-G431B-ESC supports one buttons controllabe by software: + * + * B1 USER: user button connected to the I/O PC10. + */ + +#define MIN_IRQBUTTON BUTTON_USER +#define MAX_IRQBUTTON BUTTON_USER +#define NUM_IRQBUTTONS 1 + +#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN10) + /**************************************************************************** * Public Data ****************************************************************************/ @@ -65,4 +78,48 @@ * Public Function Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_LIB_BOARDCTL=y: + * If CONFIG_NSH_ARCHINITIALIZE=y: + * Called from the NSH library (or other application) + * Otherwise, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int stm32_bringup(void); + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Initialize FOC peripheral for the board. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FOC +int stm32_foc_setup(void); +#endif + #endif /* __BOARDS_ARM_STM32_B_G431B_ESC1_SRC_B_G431B_ESC1_H */ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_appinit.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_appinit.c index ae5cc933007..8ab4db95847 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_appinit.c +++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_appinit.c @@ -1,20 +1,20 @@ /**************************************************************************** * boards/arm/stm32/b-g431b-esc1/src/stm32_appinit.c * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -24,11 +24,7 @@ #include -#include -#include - #include -#include #include "b-g431b-esc1.h" @@ -36,10 +32,8 @@ * Pre-processor Definitions ****************************************************************************/ -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 +#ifndef OK +# define OK 0 #endif /**************************************************************************** @@ -60,9 +54,9 @@ * meaning to NuttX; the meaning of the argument is a contract * between the board-specific initialization logic and the * matching application logic. The value could be such things as a - * mode enumeration value, a set of DIP switch settings, a pointer - * to configuration data read from a file or serial FLASH, or - * whatever you would like to do with it. Every implementation + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation * should accept zero/NULL as a default configuration. * * Returned Value: @@ -73,19 +67,13 @@ int board_app_initialize(uintptr_t arg) { - int ret; +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ -#if defined(HAVE_LEDS) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - - UNUSED(ret); return OK; +#else + /* Perform board-specific initialization */ + + return stm32_bringup(); +#endif } diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c index cad23b878de..a354311a31b 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c +++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c @@ -1,20 +1,20 @@ /**************************************************************************** * boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -62,9 +62,32 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_ARCH_LEDS) /* Configure on-board LEDs if LED support has been selected. */ +#ifdef CONFIG_ARCH_LEDS board_autoled_initialize(); #endif } + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c new file mode 100644 index 00000000000..edd66adcf88 --- /dev/null +++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#if defined(HAVE_LEDS) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device - must be before ADC setup */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c new file mode 100644 index 00000000000..b3ebf9a58aa --- /dev/null +++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "b-g431b-esc1.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c new file mode 100644 index 00000000000..4d1c8bd5157 --- /dev/null +++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c @@ -0,0 +1,601 @@ +/**************************************************************************** + * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "hardware/stm32g4xxxx_opamp.h" + +#include "stm32_foc.h" + +#include "arm_arch.h" + +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* We don't use phase 2 feedback as it is no connected to ADC1 */ + +#if CONFIG_MOTOR_FOC_SHUNTS != 2 +# error Only 2-shunts configuration is supported +#endif + +/* Configuration specific for L6387ED: + * 1. PWM channels must have positive polarity + * 2. PWM complementary channels must have positive polarity + */ + +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY +# error +#endif + +#if CONFIG_STM32_TIM1_CH1POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH2POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH3POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH1NPOL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH2NPOL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH3NPOL != 0 +# error +#endif + +/* SYSCFG must be enabled for OPAMP */ + +#ifndef CONFIG_STM32_SYSCFG +# error +#endif + +/* Aux ADC needs DMA enabled and workaround for G4 ADC CHAN0 enabled */ + +#ifdef CONFIG_ADC +# ifndef CONFIG_STM32_ADC1_DMA +# error +# endif +# ifndef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# error +# endif +#endif + +/* REVISIT: */ + +#define PWM_DEADTIME (20) +#define PWM_DEADTIME_NS (500) + +/* Devpath for FOC driver */ + +#define FOC_DEVPATH "/dev/foc0" + +/* Board parameters: + * Current shunt resistance = 0.003 + * PGA gain = 16 + * Current sense gain = -9.14 (inverted current) + * Vbus sense gain = 0.0962 + * Vbus min = 7V + * Vbus max = 25V (6S LiPo battery pack) + * Iout max = 40A peak + * IPHASE_RATIO = 1/(R_shunt*gain) = -36.47 + * ADC_REF_VOLTAGE = 3.3 + * ADC_VAL_MAX = 4095 + * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX + * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = -0.02939 + * VBUS_RATIO = 1/VBUS_gain = 10.4 + */ + +/* OPAMP gain */ + +#define CURRENT_PGA_GAIN 16 + +/* Center-aligned PWM duty cycle limits */ + +#define MAX_DUTY_B16 ftob16(0.95f) + +/* ADC sample time */ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_2p5 +#define VBUS_SAMPLE_TIME ADC_SMPR_640p5 +#define POT_SAMPLE_TIME ADC_SMPR_640p5 + +/* ADC1 channels used in this example */ + +#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS +# define BG431BESC1_FOC_VBUS 1 +#else +# define BG431BESC1_FOC_VBUS 0 +#endif + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT +# define BG431BESC1_FOC_POT 1 +#else +# define BG431BESC1_FOC_POT 0 +#endif + +#define ADC1_REGULAR (BG431BESC1_FOC_VBUS + BG431BESC1_FOC_POT) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +/* Check ADC1 configuration */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# if ADC1_INJECTED != (CONFIG_STM32_ADC1_INJECTED_CHAN - 1) +# error +# endif +#else +# if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +# endif +#endif + +#if CONFIG_STM32_ADC1_RESOLUTION != 0 +# error +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int board_foc_setup(FAR struct foc_dev_s *dev); +static int board_foc_shutdown(FAR struct foc_dev_s *dev); +static int board_foc_calibration(FAR struct foc_dev_s *dev, bool state); +static int board_foc_fault_clear(FAR struct foc_dev_s *dev); +static int board_foc_pwm_start(FAR struct foc_dev_s *dev, bool state); +static int board_foc_current_get(FAR struct foc_dev_s *dev, + FAR int16_t *curr_raw, + FAR foc_current_t *curr); +#ifdef CONFIG_MOTOR_FOC_TRACE +static int board_foc_trace_init(FAR struct foc_dev_s *dev); +static void board_foc_trace(FAR struct foc_dev_s *dev, int type, bool state); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* OPAMP confuguration: + * - connected with ADC through output pin (OPAINTOEN=0) + * - Current U+ - OPAMP1_VINP0 (PA1) + * - Current U- - OPAMP1_VINP0 (PA3) + * - Current V+ - OPAMP2_VINP0 (PA7) + * - Current V- - OPAMP2_VINP0 (PA5) + * - Current W+ - OPAMP3_VINP0 (PB0) + * - Current W- - OPAMP3_VINP0 (PB2) + * + * ADC configuration: + * - Current Phase V -> ADC1 INJ1 -> ADC1_IN3 (OPAMP1_VOUT/PA2) + * - Current Phase U -> Not used, no ADC1 connection + * - Current Phase W -> ADC1 INJ2 -> ADC1_IN12 (OPAMP3_VOUT/PB12) + * optional: + * - VBUS -> ADC1 REG -> ADC1_IN1 (PA0) + * - POT -> ADC1 REG -> ADC1_IN11 (PB12) + * + * TIM1 PWM configuration: + * - Phase U high -> TIM1_CH1 (PA8) + * - Phase U low -> TIM1_CH1N (PC13) + * - Phase V high -> TIM1_CH2 (PA9) + * - Phase V low -> TIM1_CH2N (PA12) + * - Phase W high -> TIM1_CH3 (PA10) + * - Phase W low -> TIM1_CH3N (PB15) + */ + +static uint8_t g_adc1_chan[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + 1, /* ADC1 REG - VBUS */ +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + 11, /* ADC1 REG - POT */ +#endif + 3, /* ADC1 INJ1 - PHASE 1 */ + 12, /* ADC1 INJ2 - PHASE 3 */ +}; + +static uint32_t g_adc1_pins[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + GPIO_ADC1_IN1, +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + GPIO_ADC1_IN11, +#endif + GPIO_ADC1_IN3, + GPIO_ADC1_IN12, +}; + +/* ADC1 sample time configuration */ + +static adc_channel_t g_adc1_stime[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + { + .channel = 1, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + { + .channel = 11, + .sample_time = POT_SAMPLE_TIME + }, +#endif + { + .channel = 3, + .sample_time = CURRENT_SAMPLE_TIME + }, + { + .channel = 12, + .sample_time = CURRENT_SAMPLE_TIME + }, +}; + +/* Board specific ADC configuration for FOC */ + +static struct stm32_foc_adc_s g_adc_cfg = +{ + .chan = g_adc1_chan, + .pins = g_adc1_pins, + .stime = g_adc1_stime, + .nchan = ADC1_NCHANNELS, + .regch = ADC1_REGULAR, + .intf = 1 +}; + +/* Board specific ops */ + +static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = +{ + .setup = board_foc_setup, + .shutdown = board_foc_shutdown, + .calibration = board_foc_calibration, + .fault_clear = board_foc_fault_clear, + .pwm_start = board_foc_pwm_start, + .current_get = board_foc_current_get, +#ifdef CONFIG_MOTOR_FOC_TRACE + .trace_init = board_foc_trace_init, + .trace = board_foc_trace +#endif +}; + +/* Board specific data */ + +static struct stm32_foc_board_data_s g_stm32_foc_board_data = +{ + .adc_cfg = &g_adc_cfg, + .duty_max = (MAX_DUTY_B16), + .pwm_dt = (PWM_DEADTIME), + .pwm_dt_ns = (PWM_DEADTIME_NS) +}; + +/* Board specific configuration */ + +static struct stm32_foc_board_s g_stm32_foc_board = +{ + .data = &g_stm32_foc_board_data, + .ops = &g_stm32_foc_board_ops, +}; + +/* Global pointer to the upper FOC driver */ + +static FAR struct foc_dev_s *g_foc_dev = NULL; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_foc_setup + ****************************************************************************/ + +static int board_foc_setup(FAR struct foc_dev_s *dev) +{ + uint32_t regval = 0; + + DEBUGASSERT(dev); + + UNUSED(dev); + + /* OPAMP1/2/3 pins: + * OPAMP1_VINM - PA3 (VINM0) + * OPAMP1_VINP - PA1 (VINP0) + * OPAMP2_VINM - PA5 (VINM0) + * OPAMP2_VINP - PA7 (VINP0) + * OPAMP3_VINM - PB2 (VINM0) + * OPAMP3_VINP - PB0 (VINP0) + */ + + /* Configure GPIO */ + + stm32_configgpio(GPIO_OPAMP1_VINM0); + stm32_configgpio(GPIO_OPAMP1_VINP0); + stm32_configgpio(GPIO_OPAMP1_VOUT); + stm32_configgpio(GPIO_OPAMP2_VINM0); + stm32_configgpio(GPIO_OPAMP2_VINP0); + stm32_configgpio(GPIO_OPAMP2_VOUT); + stm32_configgpio(GPIO_OPAMP3_VINM0); + stm32_configgpio(GPIO_OPAMP3_VINP0); + stm32_configgpio(GPIO_OPAMP3_VOUT); + + /* Configure OPAMP inputs */ + + regval += (OPAMP_CSR_VPSEL_VINP0 | OPAMP_CSR_VMSEL_PGA); + + /* PGA mode, non-inverting configuration with external bias on VINM0 */ + +#if CURRENT_PGA_GAIN == 16 + regval += ((0b01011 << OPAMP_CSR_PGAGAIN_SHIFT) & OPAMP_CSR_PGAGAIN_MASK); +#else +# error Not supported +#endif + + /* Enable high-speed mode */ + + regval += OPAMP_CSR_OPAHSM; + + /* Write configuration */ + + putreg32(regval, STM32_OPAMP1_CSR); + putreg32(regval, STM32_OPAMP2_CSR); + putreg32(regval, STM32_OPAMP3_CSR); + + /* Enable OPAMPs in separate write */ + + regval += OPAMP_CSR_OPAMPEN; + + putreg32(regval, STM32_OPAMP1_CSR); + putreg32(regval, STM32_OPAMP2_CSR); + putreg32(regval, STM32_OPAMP3_CSR); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_shutdown + ****************************************************************************/ + +static int board_foc_shutdown(FAR struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_calibration + ****************************************************************************/ + +static int board_foc_calibration(FAR struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_fault_clear + ****************************************************************************/ + +static int board_foc_fault_clear(FAR struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_pwm_start + ****************************************************************************/ + +static int board_foc_pwm_start(FAR struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_current_get + ****************************************************************************/ + +static int board_foc_current_get(FAR struct foc_dev_s *dev, + FAR int16_t *curr_raw, + FAR foc_current_t *curr) +{ + DEBUGASSERT(dev); + DEBUGASSERT(curr_raw); + DEBUGASSERT(curr); + + /* Get currents */ + + curr[0] = curr_raw[0]; + curr[2] = curr_raw[1]; + + /* Phase 2 reconstruction */ + + curr[1] = -(curr_raw[0] + curr_raw[1]); + + return OK; +} + +#ifdef CONFIG_MOTOR_FOC_TRACE +/**************************************************************************** + * Name: board_foc_trace_init + ****************************************************************************/ + +static int board_foc_trace_init(FAR struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + /* Not supported */ + + return -1; +} + +/**************************************************************************** + * Name: board_foc_trace + ****************************************************************************/ + +static void board_foc_trace(FAR struct foc_dev_s *dev, int type, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Initialize FOC driver. + * + * This function should be call by board_app_initialize(). + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + FAR struct foc_dev_s *foc = NULL; + int ret = OK; + + /* Initialize only once */ + + if (g_foc_dev == NULL) + { + /* Initialize arch specific FOC lower-half */ + + foc = stm32_foc_initialize(0, &g_stm32_foc_board); + if (foc == NULL) + { + ret = -errno; + mtrerr("Failed to initialize STM32 FOC: %d\n", ret); + goto errout; + } + + DEBUGASSERT(foc->lower); + + /* Register FOC device */ + + ret = foc_register(FOC_DEVPATH, foc); + if (ret < 0) + { + mtrerr("Failed to register FOC device: %d\n", ret); + goto errout; + } + + /* Store pointer to driver */ + + g_foc_dev = foc; + } + +errout: + return ret; +} + +#ifdef CONFIG_ADC +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + FAR struct adc_dev_s *adc = NULL; + int ret = OK; + static bool initialized = false; + + /* Initialize only once */ + + if (initialized == false) + { + if (g_foc_dev == NULL) + { + mtrerr("Failed to get g_foc_dev device\n"); + ret = -EACCES; + goto errout; + } + + /* Register regular channel ADC */ + + adc = stm32_foc_adcget(g_foc_dev); + if (adc == NULL) + { + mtrerr("Failed to get ADC device: %d\n", ret); + goto errout; + } + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + mtrerr("adc_register failed: %d\n", ret); + goto errout; + } + + initialized = true; + } + +errout: + return ret; +} +#endif diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig index 6fedb59ae94..7cd5712fcaf 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig +++ b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs b/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs index 1302883a9c9..588bd53a96c 100644 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs +++ b/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs @@ -57,8 +57,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) @@ -69,7 +69,7 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif # Provide map file needed by the "Memory Allocation" view in Eclipse: -LDFLAGS += -Map=$(TOPDIR)/NuttX.map --gc-sections +LDFLAGS += -Wl,-Map=$(TOPDIR)/NuttX.map -Wl,--gc-sections # Embed absolute path to source file in debug information so that Eclipse # source level debugging won't get confused. See: diff --git a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig index 4bf0db30277..c9a79b9793e 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig @@ -23,7 +23,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_DISABLE_DD=y CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_IFUPDOWN=y @@ -52,7 +51,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=y CONFIG_STM32_PWR=y CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=32 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig index 6e140c17cd0..42e82568859 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig @@ -61,7 +61,6 @@ CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIB_HOSTNAME="MRF24J40" CONFIG_MAC802154_NTXDESC=32 -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig index 424f4635e5c..74ab61bd9c5 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig @@ -28,7 +28,6 @@ CONFIG_IEEE802154_MAC=y CONFIG_IEEE802154_MACDEV=y CONFIG_IEEE802154_MRF24J40=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_GET=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig index 15def9b1975..ef42c6541b4 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig @@ -44,7 +44,6 @@ CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIB_HOSTNAME="MRF24J40" CONFIG_MAC802154_NTXDESC=32 -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig index 8ceb1d136e5..9d6fe69db28 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig @@ -61,7 +61,6 @@ CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIB_HOSTNAME="MRF24J40" CONFIG_MAC802154_NTXDESC=32 -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig index 290b1caccc7..98afb731254 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig index ce7dceb668f..3664b547e47 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig @@ -30,7 +30,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_GET=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig index 0189677914f..bd412c45253 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig @@ -58,7 +58,6 @@ CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIB_HOSTNAME="XBee" -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/stm32/clicker2-stm32/kernel/Makefile b/boards/arm/stm32/clicker2-stm32/kernel/Makefile index ef7dcf7e1cc..f9c5313e99e 100644 --- a/boards/arm/stm32/clicker2-stm32/kernel/Makefile +++ b/boards/arm/stm32/clicker2-stm32/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c b/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c index 791543da8db..2a2521c68ac 100644 --- a/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c +++ b/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32/clicker2-stm32/scripts/Make.defs b/boards/arm/stm32/clicker2-stm32/scripts/Make.defs index 902686362b2..9abdaa040e3 100644 --- a/boards/arm/stm32/clicker2-stm32/scripts/Make.defs +++ b/boards/arm/stm32/clicker2-stm32/scripts/Make.defs @@ -56,8 +56,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c b/boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c index ba9cf752da1..4f709b266bd 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c @@ -96,11 +96,12 @@ int board_app_initialize(uintptr_t arg) nxsig_usleep(CONFIG_CLICKER2_STM32_SYSLOG_FILE_DELAY * 1000); - ret = syslog_file_channel(CONFIG_CLICKER2_STM32_SYSLOG_FILE_PATH); - if (ret < 0) + FAR struct syslog_channel_s *channel; + channel = syslog_file_channel(CONFIG_CLICKER2_STM32_SYSLOG_FILE_PATH); + if (channel == NULL) { - syslog(LOG_ERR, "ERROR: syslog_file_channel() failed: %d\n", ret); - return ret; + syslog(LOG_ERR, "ERROR: syslog_file_channel() failed\n"); + return -EINVAL; } #endif diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c b/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c index 4e2202efb40..fa72cc9682f 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c @@ -45,6 +45,7 @@ # define CONFIG_DEBUG_FS 1 #endif +#include #include #include diff --git a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig b/boards/arm/stm32/cloudctrl/configs/nsh/defconfig index 0324f04dd64..a1c42670d65 100644 --- a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig +++ b/boards/arm/stm32/cloudctrl/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_FS_FAT=y CONFIG_HAVE_CXX=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_NET=y diff --git a/boards/arm/stm32/cloudctrl/scripts/Make.defs b/boards/arm/stm32/cloudctrl/scripts/Make.defs index 29b9b3b86a6..ef7539b2880 100644 --- a/boards/arm/stm32/cloudctrl/scripts/Make.defs +++ b/boards/arm/stm32/cloudctrl/scripts/Make.defs @@ -57,8 +57,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-eabi-) diff --git a/boards/arm/stm32/common/src/stm32_bmp180.c b/boards/arm/stm32/common/src/stm32_bmp180.c index 84b625ca58e..7725f504b04 100644 --- a/boards/arm/stm32/common/src/stm32_bmp180.c +++ b/boards/arm/stm32/common/src/stm32_bmp180.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "stm32_i2c.h" /**************************************************************************** diff --git a/boards/arm/stm32/common/src/stm32_max6675.c b/boards/arm/stm32/common/src/stm32_max6675.c index fe3987902ac..d290d508595 100644 --- a/boards/arm/stm32/common/src/stm32_max6675.c +++ b/boards/arm/stm32/common/src/stm32_max6675.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "stm32_spi.h" #ifdef CONFIG_SENSORS_MAX6675 diff --git a/boards/arm/stm32/common/src/stm32_xen1210.c b/boards/arm/stm32/common/src/stm32_xen1210.c index 7843fec7f1a..4eaf24a8dd2 100644 --- a/boards/arm/stm32/common/src/stm32_xen1210.c +++ b/boards/arm/stm32/common/src/stm32_xen1210.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/common/src/stm32_zerocross.c b/boards/arm/stm32/common/src/stm32_zerocross.c index 1785aff470b..59bbe6e2235 100644 --- a/boards/arm/stm32/common/src/stm32_zerocross.c +++ b/boards/arm/stm32/common/src/stm32_zerocross.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/emw3162/Kconfig b/boards/arm/stm32/emw3162/Kconfig new file mode 100644 index 00000000000..a8e91b19d30 --- /dev/null +++ b/boards/arm/stm32/emw3162/Kconfig @@ -0,0 +1,12 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_EMW3162 + +config EMW3162_WLAN + bool "Enable WLAN chip support" + depends on IEEE80211_BROADCOM_FULLMAC_SDIO + +endif diff --git a/boards/arm/stm32/emw3162/README.txt b/boards/arm/stm32/emw3162/README.txt new file mode 100644 index 00000000000..d76fa8d1514 --- /dev/null +++ b/boards/arm/stm32/emw3162/README.txt @@ -0,0 +1,82 @@ +README +====== + + EMW3162 board (https://www.waveshare.com/EMW3162.htm) features the + STM32F205RG MCU and Broadcom BCM43362KUBG Wi-Fi chip. + The STM32F205RG is a 120 MHz Cortex-M3 operation with 1Mbit Flash + memory and 128kbytes. + +Contents +======== + + - Configuring NuttX for the EMW3162 board + - Configuring NuttX to use your Wireless Router (aka Access Point) + - Programming Flash + - NSH via telnet + - Serial console configuration + +Configuring NuttX for the EMW3162 board +======================================= + + $ cd nuttx + $ make apps_distclean + $ make distclean + $ ./tools/configure.sh emw3162:wlan + +Configuring NuttX to use your Wireless Router (aka Access Point) +================================================================ + + $ make menuconfig + + Browse the menus this way: + + Application Configuration ---> + NSH Library ---> + Networking Configuration ---> + WAPI Configuration ---> + (myApSSID) SSID + (mySSIDpassphrase) Passprhase + + Replace the SSID from myApSSID with your wireless router name and + the Passprhase with your WiFi password. + + Exit and save. + + Finally just compile NuttX: + + $ make + +Programming Flash +================= + + Flash memory can be programmed by stlink toolset + (https://github.com/stlink-org/stlink) and ST-LINK V2 programmer + (via SWD interface) as follows: + + $ sudo st-flash write nuttx.bin 0x8000000 + +NSH via telnet +============== + + After you successfully downloaded nuttx.bin, reset the board and it + automatically connects to the corresponding wifi AP. You may login + your router to see its IP address. Assume that it's 192.168.1.111 + + Open a terminal on your computer and telnet your EMW3162 board: + + $ telnet 192.168.1.111 + Trying 192.168.1.111... + Connected to 192.168.1.111. + Escape character is '^]' + + NuttShell (NSH) NuttX-10.1.0-RC1 + nsh> + +Serial console configuration +============================ + + Connect a USB/Serial 3.3V dongle to GND, TXD and RXD pins of EMW3162 board. + Then use some serial console client (minicom, picocom, teraterm, etc) confi- + gured to 115200 8n1 without software or hardware flow control. + + Reset the board and you should see NuttX starting in the serial. diff --git a/boards/arm/stm32/emw3162/configs/nsh/defconfig b/boards/arm/stm32/emw3162/configs/nsh/defconfig new file mode 100644 index 00000000000..7adefa0e14a --- /dev/null +++ b/boards/arm/stm32/emw3162/configs/nsh/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="emw3162" +CONFIG_ARCH_BOARD_EMW3162=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/emw3162/configs/wlan/defconfig b/boards/arm/stm32/emw3162/configs/wlan/defconfig new file mode 100644 index 00000000000..fe1189ad052 --- /dev/null +++ b/boards/arm/stm32/emw3162/configs/wlan/defconfig @@ -0,0 +1,85 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_IEEE80211_BROADCOM_FWFILES is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="emw3162" +CONFIG_ARCH_BOARD_EMW3162=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EMW3162_WLAN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE80211_BROADCOM_BCM43362=y +CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEVICES=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=800 +CONFIG_NET_GUARDSIZE=32 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_PKT=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32/emw3162/include/board.h b/boards/arm/stm32/emw3162/include/board.h new file mode 100644 index 00000000000..cfddfd9a329 --- /dev/null +++ b/boards/arm/stm32/emw3162/include/board.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include "stm32_rcc.h" +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The EMW3162 board features a single 26MHz crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration + * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) + * PLLM : 26 (STM32_PLLCFG_PLLM) + * PLLN : 240 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 5 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG HS : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 26MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 26000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (26,000,000 / 26) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ---------------------------- ------ + * SYMBOL Meaning LED + * ------------------- ---------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* MCU is is sleep mode Not used */ + +/* Thus if LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* Alternate function pin selections ****************************************/ + +/* UART1 */ + +#ifdef CONFIG_STM32_USART1 +# define GPIO_USART1_RX GPIO_USART1_RX_1 +# define GPIO_USART1_TX GPIO_USART1_TX_1 +#endif + +/* SDIO definitions *********************************************************/ + +/* Note that slower clocking is required when DMA is disabled in order + * to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. + * + * These values have not been tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +#endif /* __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/emw3162/scripts/Make.defs b/boards/arm/stm32/emw3162/scripts/Make.defs new file mode 100644 index 00000000000..718757550a6 --- /dev/null +++ b/boards/arm/stm32/emw3162/scripts/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32/emw3162/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif diff --git a/boards/arm/stm32/emw3162/scripts/ld.script b/boards/arm/stm32/emw3162/scripts/ld.script new file mode 100644 index 00000000000..eb3611a6f1d --- /dev/null +++ b/boards/arm/stm32/emw3162/scripts/ld.script @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F205RG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 112Kb of SRAM in main SRAM1 and 16 Kb in auxiliary SRAM2. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + + . = ALIGN(0x4); + wlan_firmware_image_location = .; + *(.wlan_firmware_image .wlan_firmware_image.*) + wlan_firmware_image_end = .; + . = ALIGN(0x4); + wlan_nvram_image_location = .; + *(.wlan_nvram_image .wlan_nvram_image.*) + wlan_nvram_image_end = .; + + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/emw3162/src/Make.defs b/boards/arm/stm32/emw3162/src/Make.defs new file mode 100644 index 00000000000..9fa6e5d517e --- /dev/null +++ b/boards/arm/stm32/emw3162/src/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32/emw3162/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_EMW3162_WLAN),y) +CSRCS += stm32_wlan.c +CSRCS += stm32_wlan_firmware.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/emw3162/src/emw3162.h b/boards/arm/stm32/emw3162/src/emw3162.h new file mode 100644 index 00000000000..d9189cf551e --- /dev/null +++ b/boards/arm/stm32/emw3162/src/emw3162.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/src/emw3162.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_EMW3162_SRC_EMW3162_H +#define __BOARDS_ARM_STM32_EMW3162_SRC_EMW3162_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDs */ + +#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0) + +#define GPIO_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) + +/* WLAN chip */ + +#define SDIO_WLAN0_SLOTNO 0 /* EMW3162 board has only one sdio device */ +#define SDIO_WLAN0_MINOR 0 /* Register "wlan0" device */ + +#define GPIO_WLAN0_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_WLAN0_PWRDN (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN1) + +#define GPIO_WLAN0_32K_CLK (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN8) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Called either by board_initialize() if CONFIG_BOARD_LATE_INITIALIZE or + * by board_app_initialize if CONFIG_LIB_BOARDCTL is selected. This + * function initializes and configures all on-board features appropriate + * for the selected configuration. + * + ****************************************************************************/ + +#if defined(CONFIG_LIB_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) +int stm32_bringup(void); +#endif + +/**************************************************************************** + * Name: emw3162_wlan_initialize + * + * Description: + * Initialize wlan hardware and driver for EMW3162 board. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_EMW3162_WLAN +int emw3162_wlan_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32_EMW3162_SRC_EMW3162_H */ diff --git a/boards/arm/stm32/emw3162/src/stm32_appinit.c b/boards/arm/stm32/emw3162/src/stm32_appinit.c new file mode 100644 index 00000000000..1b49e154f1c --- /dev/null +++ b/boards/arm/stm32/emw3162/src/stm32_appinit.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/src/stm32_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "emw3162.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return stm32_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/boards/arm/stm32/emw3162/src/stm32_autoleds.c b/boards/arm/stm32/emw3162/src/stm32_autoleds.c new file mode 100644 index 00000000000..e331446c0fc --- /dev/null +++ b/boards/arm/stm32/emw3162/src/stm32_autoleds.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/src/stm32_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* LEDs + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ----------------------- ------ + * SYMBOL Meaning LED + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt N/C + * LED_SIGNAL In a signal handler N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus is LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "emw3162.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure EMW3162 LED gpio as output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1 || led == 3) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 3) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/emw3162/src/stm32_boot.c b/boards/arm/stm32/emw3162/src/stm32_boot.c new file mode 100644 index 00000000000..b1a0462c3cf --- /dev/null +++ b/boards/arm/stm32/emw3162/src/stm32_boot.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/src/stm32_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm_arch.h" +#include "emw3162.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_intitialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + stm32_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32/emw3162/src/stm32_bringup.c b/boards/arm/stm32/emw3162/src/stm32_bringup.c new file mode 100644 index 00000000000..eead0c2cdd5 --- /dev/null +++ b/boards/arm/stm32/emw3162/src/stm32_bringup.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/src/stm32_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "emw3162.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Called either by board_initialize() if CONFIG_BOARD_LATE_INITIALIZE or + * by board_app_initialize if CONFIG_LIB_BOARDCTL is selected. + * This function initializes and configures all on-board features + * appropriate for the selected configuration. + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +#ifdef CONFIG_USERLED_LOWER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable USER LED support for some other purpose */ + + board_userled_initialize(); +#endif /* CONFIG_USERLED_LOWER */ +#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ + +#ifdef CONFIG_EMW3162_WLAN + /* Initialize wlan driver and hardware */ + + ret = emw3162_wlan_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32/emw3162/src/stm32_userleds.c b/boards/arm/stm32/emw3162/src/stm32_userleds.c new file mode 100644 index 00000000000..c159a4ae8e6 --- /dev/null +++ b/boards/arm/stm32/emw3162/src/stm32_userleds.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/src/stm32_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include "emw3162.h" + +#include "stm32_gpio.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure EMW3162 LED gpio as output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/emw3162/src/stm32_wlan.c b/boards/arm/stm32/emw3162/src/stm32_wlan.c new file mode 100644 index 00000000000..15c2abeb972 --- /dev/null +++ b/boards/arm/stm32/emw3162/src/stm32_wlan.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/stm32/emw3162/src/stm32_wlan.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "stm32_gpio.h" +#include "stm32_sdio.h" + +#include "emw3162.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bcmf_board_reset + ****************************************************************************/ + +void bcmf_board_reset(int minor, bool reset) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); +} + +/**************************************************************************** + * Name: bcmf_board_power + ****************************************************************************/ + +void bcmf_board_power(int minor, bool power) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + stm32_gpiowrite(GPIO_WLAN0_PWRDN, !power); +} + +/**************************************************************************** + * Name: bcmf_board_initialize + ****************************************************************************/ + +void bcmf_board_initialize(int minor) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure MCO1 output to drive EXT_SLEEP_CLK input pin of BCM43362 */ + + stm32_configgpio(GPIO_MCO1); + stm32_mco1config(RCC_CFGR_MCO1_LSE, RCC_CFGR_MCO1PRE_NONE); + + /* Configure PowerDown pin */ + + stm32_configgpio(GPIO_WLAN0_PWRDN); + + /* Shutdown wlan chip */ + + bcmf_board_power(minor, false); + + /* Configure reset pin */ + + stm32_configgpio(GPIO_WLAN0_RESET); + + /* Put wlan chip in reset state */ + + bcmf_board_reset(minor, true); +} + +/**************************************************************************** + * Name: bcmf_board_setup_oob_irq + ****************************************************************************/ + +void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure SDIO card in-band interrupt callback */ + + if (g_sdio_dev != NULL) + { + sdio_set_sdio_card_isr(g_sdio_dev, func, arg); + } +} + +/**************************************************************************** + * Name: emw3162_wlan_initialize + ****************************************************************************/ + +int emw3162_wlan_initialize() +{ + int ret; + + /* Initialize sdio interface */ + + wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); + + if (!g_sdio_dev) + { + wlerr("ERROR: Failed to initialize SDIO with slot %d\n", + SDIO_WLAN0_SLOTNO); + return ERROR; + } + + /* Bind the SDIO interface to the bcmf driver */ + + ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); + + if (ret != OK) + { + wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); + + /* FIXME deinitialize sdio device */ + + return ERROR; + } + + return OK; +} diff --git a/boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c b/boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c new file mode 120000 index 00000000000..2d4fef1596f --- /dev/null +++ b/boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c @@ -0,0 +1 @@ +../../photon/src/stm32_wlan_firmware.c \ No newline at end of file diff --git a/boards/arm/stm32/et-stm32-stamp/Kconfig b/boards/arm/stm32/et-stm32-stamp/Kconfig new file mode 100644 index 00000000000..8a0658e8099 --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/Kconfig @@ -0,0 +1,26 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ET_STM32_STAMP + +choice + prompt "Select board type" + default ET_STM32_STAMP if ARCH_CHIP_STM32F103RE + ---help--- + Select the board hosting the architecture. You must first select the + exact MCU part number, then the boards supporting that part will + be available for selection. Use ARCH_BOARD_CUSTOM to create a new + board configuration. + +config ET_STM32_STAMP + bool "ET-STM32 Stamp" + depends on ARCH_CHIP_STM32F103RE + ---help--- + This version is the standard ET-STM32 Stamp board from Futurlec, with + the STM32F103RET6 microcontroller. + +endchoice + +endif diff --git a/boards/arm/stm32/et-stm32-stamp/README.txt b/boards/arm/stm32/et-stm32-stamp/README.txt new file mode 100644 index 00000000000..777bfab5ff1 --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/README.txt @@ -0,0 +1,120 @@ +README +====== + +This README discusses issues/thoughts unique to NuttX configuration(s) for the +ET-STM32 Stamp board from Futurlec (https://www.futurlec.com/ET-STM32_Stamp.shtml). + +Microprocessor: 32-bit ARM Cortex M3 at 72MHz STM32F103RET6 +Memory: 512 KB Flash and 64 KB SRAM +I/O Pins Out: 48 +ADCs: 16 (at 12-bit resolution) +DACs: 2 (at 12-bit resolution) +Peripherals: RTC, 4 timers, 2 I2Cs, 3 SPI ports, 1 on-board UART (upto 5 channels) +Other: Sleep, stop, and standby modes; serial wire debug and JTAG interfaces + +Please see link below for board specific details: + + https://www.futurlec.com/ET-STM32_Stamp_Technical.shtml + +This configuration supports the ET-STM32 Stamp module. + +Contents +======== + + - Development Environment + - Flashing/Programming + - Configurations + +Development Environment +======================= + + Either Linux (recommended), Mac or Cygwin on Windows can be used for the development + environment. The source has been built only using the GNU (Cortex M) toolchain. + Other toolchains will likely cause problems. + + WSL (Windows Subsystem for Linux) was used to develop, compile and test the NuttX + build for the ET-STM32 Stamp platform. + +Flashing/Programming +==================== + +Prerequisites: + + 1. The ET-STM32 Stamp module from Futurlec. + + 2. An RS232 connection cable such as the one in this link: (Part code: RS232CONN): + https://www.futurlec.com/DevBoardAccessories.shtml + + It has a 4-pin connection header on one end and an RS-232 (DB9) female connector on + the other. The 4-pin connector can be directly plugged onto the Stamp module. + + 3. An RS232 to USB converter cable. Ensure that a suitable driver is installed for + the converter cable. When the cable is plugged in (for example), my PC lists the + assigned port with this name: "USB-SERIAL CH340 (COM2)". + + Assuming Windows 10, navigate to: This PC -> Manage -> Device Manager -> Ports. + + 4. ST's Flash loader demonstrator tool. You can download it from here: + https://www.st.com/en/development-tools/flasher-stm32.html + +To install the NuttX firmware (nuttx.bin) on the ET-STM32 Stamp: + + 1. First, power the Stamp module with a 3.3 VDC power supply. I made my own + Stamp module fixture using a 3.3 VDC switching regulator, a prototype PCB card + and some solder. + + 2. Insert the RS232CONN into the 4-pin on-board header. The other end should be + connected to the USB port of the PC using the RS232-USB converter. + + 3. Set the BOOT1 jumper on your board to the ISP position. + + 4. Press the BOOT0 switch. The green "BOOT0=1" LED should light up. + + 5. Reset the board by pressing on the RESET button. + + 6. Using the ST Flash loader demonstrator to download the NuttX binary image. + + 7. Wait until programming is completed and press "Finish". Toggle the + BOOT0 switch again. Reset the board. + +You will now be presented with the NuttShell (NSH). Enjoy. + +Configurations +============== + + Information Common to All Configurations + ---------------------------------------- + The ET-STM32 Stamp configuration is maintained in a sub-directory and can be + selected as follow: + + tools/configure.sh et-stm32-stamp: + + Before building, make sure the PATH environment variable includes the + correct path to the directory than holds your toolchain binaries. + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + + make + + The that is provided above as an argument to the tools/configure.sh + must be in one of the following. + + NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + Configuration Sub-directories + ----------------------------- + + nsh: + + This configuration directory provide the basic NuttShell (NSH). + A serial console is provided on USART1. diff --git a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig b/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig new file mode 100644 index 00000000000..129a40b8ab7 --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig @@ -0,0 +1,37 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="et-stm32-stamp" +CONFIG_ARCH_BOARD_ET_STM32_STAMP=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RE=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_LIB_RAND_ORDER=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NSH_LINELEN=80 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/et-stm32-stamp/include/board.h b/boards/arm/stm32/et-stm32-stamp/include/board.h new file mode 100644 index 00000000000..d475bd9b776 --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/include/board.h @@ -0,0 +1,149 @@ +/**************************************************************************** + * boards/arm/stm32/et-stm32-stamp/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif +#include "stm32_rcc.h" +#include "stm32_sdio.h" +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multipler is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The ET-STM32 Stamp doesn't have an on-board LED. These innocent macros + * can still be here. + */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +#endif /* __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs b/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs new file mode 100644 index 00000000000..2938181310f --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32/et-stm32-stamp/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION += -g +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif diff --git a/boards/arm/stm32/et-stm32-stamp/scripts/ld.script b/boards/arm/stm32/et-stm32-stamp/scripts/ld.script new file mode 100644 index 00000000000..b0b307a478e --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/scripts/ld.script @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/stm32/et-stm32-stamp/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* The STM32F103RE has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103RET6 has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/et-stm32-stamp/src/Make.defs b/boards/arm/stm32/et-stm32-stamp/src/Make.defs new file mode 100644 index 00000000000..11ef7edce3f --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32/et-stm32-stamp/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +endif + +ifeq ($(CONFIG_INPUT),y) +endif + +ifeq ($(CONFIG_USBMSC),y) +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h b/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h new file mode 100644 index 00000000000..60a96085952 --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_ET_STM32_STAMP_SRC_ET_STM32_STAMP_H +#define __BOARDS_ARM_STM32_ET_STM32_STAMP_SRC_ET_STM32_STAMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The ET-STM32 Stamp target doesn't have any configurable LEDs OR buttons. + */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32_ET_STM32_STAMP_SRC_ET_STM32_STAMP_H */ diff --git a/boards/arm/stm32/et-stm32-stamp/src/stm32_appinit.c b/boards/arm/stm32/et-stm32-stamp/src/stm32_appinit.c new file mode 100644 index 00000000000..9d9be7e3bee --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/src/stm32_appinit.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/arm/stm32/et-stm32-stamp/src/stm32_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "et-stm32-stamp.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + return OK; +} diff --git a/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c b/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c new file mode 100644 index 00000000000..089c5428f81 --- /dev/null +++ b/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c @@ -0,0 +1,61 @@ +/**************************************************************************** + * boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_arch.h" +#include "et-stm32-stamp.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Empty for now. */ +} diff --git a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig b/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig index e96227532f9..a3e2a2a802b 100644 --- a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig +++ b/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_I2CTOOL_MAXBUS=2 CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2C_POLLED=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_NET=y diff --git a/boards/arm/stm32/fire-stm32v2/scripts/Make.defs b/boards/arm/stm32/fire-stm32v2/scripts/Make.defs index c1da9cf8689..6f5df787e31 100644 --- a/boards/arm/stm32/fire-stm32v2/scripts/Make.defs +++ b/boards/arm/stm32/fire-stm32v2/scripts/Make.defs @@ -57,8 +57,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_appinit.c b/boards/arm/stm32/fire-stm32v2/src/stm32_appinit.c index 12d61b6e79c..c1f5f8c7d3d 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_appinit.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_appinit.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c b/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c index 84bd62075ed..ebff7d851ea 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c @@ -41,6 +41,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig index 1eb6316461d..04fbb89337a 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_BINFMT_DISABLE=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_FAT_LCNAMES=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig index 3518cf35e62..13ce4e702de 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig @@ -41,7 +41,6 @@ CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_MAXPOWER=100 CONFIG_LCD_SSD1289=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig index 9c9884596f5..937006154fe 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig index 555096824c4..5877a9788d9 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig @@ -23,7 +23,6 @@ CONFIG_CDCACM=y CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_MAX_TASKS=16 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=49152 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig index 6cf7722bad6..7e8dddd4bc3 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig @@ -16,7 +16,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_DISABLE_MOUNTPOINT=y CONFIG_EXAMPLES_USBSERIAL=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_PL2303=y CONFIG_PL2303_PRODUCTSTR="USBdev Serial" CONFIG_PL2303_RXBUFSIZE=512 diff --git a/boards/arm/stm32/hymini-stm32v/scripts/Make.defs b/boards/arm/stm32/hymini-stm32v/scripts/Make.defs index 8543560e5da..5891cd9ab01 100644 --- a/boards/arm/stm32/hymini-stm32v/scripts/Make.defs +++ b/boards/arm/stm32/hymini-stm32v/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c b/boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c index 4ddc445277f..f8137ccf29f 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c index 250c48749ac..9baeedc7bee 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c @@ -1,38 +1,20 @@ /**************************************************************************** * boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c * - * Copyright (C) 2009, 2011, 2013, 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Laurent Latil - * C. Faure 2013-05-15 - * - Adapted initialization from SSD1289 to r61505u + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -46,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c index 08192ea40c5..e69ee5a1adc 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/maple/configs/nsh/defconfig b/boards/arm/stm32/maple/configs/nsh/defconfig index 2a4c65debef..9614151486e 100644 --- a/boards/arm/stm32/maple/configs/nsh/defconfig +++ b/boards/arm/stm32/maple/configs/nsh/defconfig @@ -32,7 +32,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_LIB_RAND_ORDER=2 -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_LINELEN=80 diff --git a/boards/arm/stm32/maple/configs/nx/defconfig b/boards/arm/stm32/maple/configs/nx/defconfig index ce0098220b1..232ac0cae78 100644 --- a/boards/arm/stm32/maple/configs/nx/defconfig +++ b/boards/arm/stm32/maple/configs/nx/defconfig @@ -45,7 +45,6 @@ CONFIG_I2C=y CONFIG_LCD=y CONFIG_LCD_SHARP_MEMLCD=y CONFIG_LIB_RAND_ORDER=2 -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/maple/configs/usbnsh/defconfig b/boards/arm/stm32/maple/configs/usbnsh/defconfig index 4913c91dfe6..1a2c5455dde 100644 --- a/boards/arm/stm32/maple/configs/usbnsh/defconfig +++ b/boards/arm/stm32/maple/configs/usbnsh/defconfig @@ -38,7 +38,6 @@ CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_DEFAULT_SMALL=y CONFIG_I2C=y CONFIG_LIB_RAND_ORDER=2 -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_LINELEN=80 diff --git a/boards/arm/stm32/maple/scripts/Make.defs b/boards/arm/stm32/maple/scripts/Make.defs index 79d0f5cfd5a..6a729569cba 100644 --- a/boards/arm/stm32/maple/scripts/Make.defs +++ b/boards/arm/stm32/maple/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/maple/src/stm32_lcd.c b/boards/arm/stm32/maple/src/stm32_lcd.c index 09a0568fe02..77d2b62d27a 100644 --- a/boards/arm/stm32/maple/src/stm32_lcd.c +++ b/boards/arm/stm32/maple/src/stm32_lcd.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig index 21b33f6239e..93757747e80 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig @@ -55,7 +55,6 @@ CONFIG_LIBC_STRERROR=y CONFIG_M25P_MANUFACTURER=0x1C CONFIG_M25P_MEMORY_TYPE=0x31 CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MAX_TASKS=16 CONFIG_MIKROE_FLASH=y CONFIG_MIKROE_FLASH_PART=y CONFIG_MMCSD=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig index c23192d832e..ef14ecee1e9 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig @@ -39,7 +39,6 @@ CONFIG_LIBC_STRERROR=y CONFIG_M25P_MANUFACTURER=0x1C CONFIG_M25P_MEMORY_TYPE=0x31 CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MAX_TASKS=16 CONFIG_MIKROE_FLASH=y CONFIG_MIKROE_FLASH_PART=y CONFIG_MIKROE_FLASH_PART_LIST="256,768" @@ -82,7 +81,7 @@ CONFIG_STM32_USART2=y CONFIG_SYSLOG_CHAR=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=11 CONFIG_TESTING_OSTEST=y CONFIG_USBDEV=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig index 1ca8f8760e5..3b58971bede 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig @@ -34,7 +34,6 @@ CONFIG_LIBC_STRERROR=y CONFIG_M25P_MANUFACTURER=0x1C CONFIG_M25P_MEMORY_TYPE=0x31 CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MAX_TASKS=16 CONFIG_MIKROE_FLASH=y CONFIG_MIKROE_FLASH_PART=y CONFIG_MIKROE_FLASH_PART_LIST="256,768" diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig index 71e627e2aff..880ef9c2485 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig @@ -34,7 +34,6 @@ CONFIG_LCD=y CONFIG_LCD_MIO283QT2=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig index 1780e46e8af..df19c1d3768 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig @@ -39,7 +39,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_MIO283QT2=y CONFIG_LCD_NOGETRUN=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig index 4e22eac03f2..5d2725eae85 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig @@ -33,7 +33,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_MIO283QT2=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig index 08032fc5e9e..f7c687d5ab4 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig @@ -38,7 +38,6 @@ CONFIG_LIBC_STRERROR=y CONFIG_M25P_MANUFACTURER=0x1C CONFIG_M25P_MEMORY_TYPE=0x31 CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MAX_TASKS=16 CONFIG_MIKROE_FLASH=y CONFIG_MIKROE_FLASH_PART=y CONFIG_MIKROE_FLASH_PART_LIST="256,768" diff --git a/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile b/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile index 56e6186f62a..3c7023fc753 100644 --- a/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile +++ b/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c b/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c index fb63a4ae224..25af38e677b 100644 --- a/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c +++ b/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs b/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs index 9a24c87487f..ce284c2048b 100644 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs +++ b/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c index 9457436b82f..08adedea8cc 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c index a375793b671..2eacc2b1aa3 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c index e3ebebeee9e..4e27c971e0b 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c index 43698435572..1f90ce0fa1c 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig index 546735f077d..ea556b80efb 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig @@ -23,7 +23,6 @@ CONFIG_DEFAULT_SMALL=y CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_GROUPSIZE=3 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig index b8cdc0b2cbb..0736262e7a5 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig @@ -49,7 +49,6 @@ CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=4 CONFIG_MOTOR=y CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_TRACE=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig index e9b9bc5e08f..fe522db373d 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig @@ -18,7 +18,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_SMALL=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig index 333ce3f0000..386847b2549 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig @@ -19,7 +19,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_SMALL=y CONFIG_EXAMPLES_PWM=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs b/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs index 7dfe3feadd8..4a8950ebae3 100644 --- a/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c index b90774d06c7..254c921ccab 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c +++ b/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c @@ -69,7 +69,7 @@ * Private Data ****************************************************************************/ -/* FOC ADC configration: +/* FOC ADC configuration: * - Current Phase V -> ADC1 INJ1 -> ADC1_IN0 (PA0) * - Current Phase U -> ADC1 INJ2 -> ADC1_IN11 (PC1) * - Current Phase W -> ADC1 INJ3 -> ADC1_I10 (PC0) diff --git a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig index cf2031cfd69..eaa303daee2 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig @@ -23,7 +23,6 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_GROUPSIZE=3 CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig index 471d2717451..2ddb9e0dddf 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_EXAMPLES_HELLO=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig index 5948d373fb7..4d9b6476327 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig @@ -19,7 +19,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_EXAMPLES_PWM=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs index 36f3ef1c73b..7ec4ad364c8 100644 --- a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig index c97ba4d74d7..6c1664d949e 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig @@ -27,7 +27,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NUCLEOF302R8_HIGHPRI=y CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=512 diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig index f388242ed93..f95cfe96686 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig @@ -50,7 +50,6 @@ CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=4 CONFIG_MOTOR=y CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_TRACE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig index c513b9f6d72..73d603e8d08 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig @@ -50,7 +50,6 @@ CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=4 CONFIG_MOTOR=y CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_TRACE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig index 5de0caa1d83..49ee3ea88e3 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig @@ -28,7 +28,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_FDCLONE_STDIO=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_BASENAME=y diff --git a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs index e23b0d0b070..97e2ba09d6c 100644 --- a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c index f86d07ee996..3ee22a4927a 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c +++ b/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c @@ -67,7 +67,7 @@ * Private Data ****************************************************************************/ -/* FOC ADC configration: +/* FOC ADC configuration: * - Current Phase V -> ADC1 INJ1 -> ADC1_IN1 (PA0) * - Current Phase U -> ADC1 INJ2 -> ADC1_IN7 (PC1) * - Current Phase W -> ADC1 INJ3 -> ADC1_IN6 (PC0) diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c index 95838ac86d2..a8e4e182910 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c +++ b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig index 2bbda686062..352cd7868fe 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig @@ -23,7 +23,6 @@ CONFIG_EXAMPLES_ADC_GROUPSIZE=3 CONFIG_EXAMPLES_ADC_SWTRIG=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig b/boards/arm/stm32/nucleo-f303re/configs/can/defconfig index cf6cdbd5b62..be0f65e9d4e 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/can/defconfig @@ -21,7 +21,6 @@ CONFIG_EXAMPLES_CAN=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65536 diff --git a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig b/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig index 69d91f9e480..ff141fe99a8 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig @@ -19,7 +19,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_EXAMPLES_HELLO=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65536 diff --git a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig index c1bb3515668..9b3b6f29a06 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig @@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_DEBUG_SYMBOLS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65536 diff --git a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig index 4bfbaa2f17a..053635dd2f2 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig @@ -25,7 +25,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_SSD1351=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig index fb32a909e53..c952d8a70d0 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig @@ -19,7 +19,6 @@ CONFIG_BUILTIN=y CONFIG_EXAMPLES_PWM=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig b/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig index 3b98d6a029f..9d818b7e7e8 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig @@ -23,7 +23,6 @@ CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65536 diff --git a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs b/boards/arm/stm32/nucleo-f303re/scripts/Make.defs index b5081e1218a..6997cbb7079 100644 --- a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f303re/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig index e6ca4213883..e955449b987 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig @@ -25,7 +25,6 @@ CONFIG_EXAMPLES_ADC_GROUPSIZE=3 CONFIG_EXAMPLES_ADC_SWTRIG=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig index 17013f8e2fb..13a2a14d60d 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_EXAMPLES_HELLO=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig index 5d9764a6b63..51131d96ca1 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig @@ -29,7 +29,6 @@ CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=255 CONFIG_LCD_SH1106_OLED_132=y CONFIG_LCD_SSD1306_I2C=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs b/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs index 4cbd1a33097..96ad28cbc1f 100644 --- a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig index 68ba58f9381..a7f3919e8c3 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig @@ -30,7 +30,6 @@ CONFIG_EXAMPLES_ADC_GROUPSIZE=3 CONFIG_EXAMPLES_ADC_SWTRIG=y CONFIG_FDCLONE_STDIO=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig index 55c4857e952..175823c11e0 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig @@ -27,7 +27,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NUCLEOF334R8_HIGHPRI=y CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=512 diff --git a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig index f424eed13c1..2eba7b472a3 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig @@ -28,7 +28,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_FDCLONE_STDIO=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_BASENAME=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig index 1a25c1e0c23..bb5371d613c 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig @@ -27,7 +27,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NUCLEOF334R8_SPWM=y CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=3 diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig index b14553cbc40..32a1ad309a7 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig @@ -29,7 +29,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NUCLEOF334R8_SPWM=y CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=4 diff --git a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs index 6d6488f2855..ab27c9a1f96 100644 --- a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c index 37430be327c..a46742ade50 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c +++ b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c index b3af2a5a11d..f6711bb35e1 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c +++ b/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig index e937108f0cc..f375e6652b3 100644 --- a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig @@ -28,7 +28,6 @@ CONFIG_EXAMPLES_HELLO=y CONFIG_HAVE_CXX=y CONFIG_HEAP_COLORATION=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs b/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs index d764fe3c93d..340bef14efa 100644 --- a/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c index d8b6d20cc6f..6d076381347 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c +++ b/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig index 396c6a21336..a3ad59c3b71 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig @@ -33,7 +33,6 @@ CONFIG_DEBUG_HARDFAULT_ALERT=y CONFIG_HAVE_CXX=y CONFIG_I2C=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs index e040434722a..451a58039b0 100644 --- a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs @@ -45,15 +45,15 @@ ARCHWARNINGSXX = -Wall -Wshadow -Wundef ARCHDEFINES = ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 -CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h b/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h index fe4157812fe..fb0bb1f4ea3 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h +++ b/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h @@ -84,13 +84,10 @@ /* USB OTG FS * - * PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED) * PC0 OTG_FS_PowerSwitchOn * PD5 OTG_FS_Overcurrent */ -#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ - GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) #define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) diff --git a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig index e52b9ccc784..2bbee3003e9 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig +++ b/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_TMPFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig index a5656072955..9c17dff0242 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 CONFIG_HEAP2_SIZE=8388608 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs b/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs index 9620711ef90..c914082a4e1 100644 --- a/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c index fb14e793984..505361716b9 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c +++ b/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/stm32/nucleo-f446re/README.txt b/boards/arm/stm32/nucleo-f446re/README.txt index 8fd031d455a..e4fe895dd73 100644 --- a/boards/arm/stm32/nucleo-f446re/README.txt +++ b/boards/arm/stm32/nucleo-f446re/README.txt @@ -559,20 +559,23 @@ Configurations Functionality of CAN driver can be tested by calling application "can" in NuttShell. This application sends 100 messages over CAN 1. - lcd: + dac: ---- - This is basically an nsh configuration (see above) with added support - of ILI9225 176x220 TFT display and test framebuffer application. + This is an nsh configuration (see above) with added support + for digital analog converter driver. - Display connection is set to SPI 3 and pinout is following: + Functionality of DAC driver can be tested by calling application + "dac" in NuttShell. GPIO_DAC1_OUT1 pin is set on PA_4. - CS D8 - RST D6 - RS D7 - SDA D4 - CLK D3 + gpio: + ----- + This is an nsh configuration (see above) with added support for GPIO + driver and GPIO test application "gpio". Three pins are configured for + testing purposes: - Framebuffer application can be started from terminal by typing "fb". + PA_7 - GPIO_INPUT + PB_6 - GPIO_OUTPUT + PC_7 - GPIO_INPUT_INTERRUPT ihm08m1_f32 and ihm08m1_b16: ---------------------------- @@ -637,3 +640,24 @@ Configurations VBUS_RATIO = 1/VBUS_gain = 19.152 For now only 3-shunt resistors configuration is supported. + + lcd: + ---- + This is basically an nsh configuration (see above) with added support + of ILI9225 176x220 TFT display and test framebuffer application. + + Display connection is set to SPI 3 and pinout is following: + + CS D8 + RST D6 + RS D7 + SDA D4 + CLK D3 + + Framebuffer application can be started from terminal by typing "fb". + + pwm: + ---- + This is an nsh configuration (see above) with added capability of pulse width + modulation. PWM output is on Timer 3 channel 1, which is pin PA_6 (D12) on + Nucleo board. Example program can be stared by "pwm" command. diff --git a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig index 70dc8c67251..527504af09a 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig @@ -32,7 +32,6 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig b/boards/arm/stm32/nucleo-f446re/configs/can/defconfig index 4f31ee24b7e..e96098ef48b 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/can/defconfig @@ -30,7 +30,6 @@ CONFIG_EXAMPLES_CAN_WRITE=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig b/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig new file mode 100644 index 00000000000..2967087204e --- /dev/null +++ b/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DAC=y +CONFIG_EXAMPLES_DAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig b/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig new file mode 100644 index 00000000000..59aba725824 --- /dev/null +++ b/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEV_GPIO=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig index a42cad77deb..69f1837fb0b 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig @@ -49,7 +49,6 @@ CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOR=y CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_TRACE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig index fddb077432f..45e17403832 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig @@ -49,7 +49,6 @@ CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOR=y CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_TRACE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig index 1c79e8172e3..c3bdd6a040d 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig @@ -33,7 +33,6 @@ CONFIG_LCD=y CONFIG_LCD_FRAMEBUFFER=y CONFIG_LCD_ILI9225=y CONFIG_LCD_PORTRAIT=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig index 3fcb0761538..5907c0d71ec 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig new file mode 100644 index 00000000000..983d665a3c4 --- /dev/null +++ b/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm2" +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/nucleo-f446re/include/board.h b/boards/arm/stm32/nucleo-f446re/include/board.h index f7d9a69bf34..d5b48be1c75 100644 --- a/boards/arm/stm32/nucleo-f446re/include/board.h +++ b/boards/arm/stm32/nucleo-f446re/include/board.h @@ -380,6 +380,9 @@ #define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP) #define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP) +/* TIM3 configuration *******************************************************/ +#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_1 + #ifdef CONFIG_BOARD_STM32_IHM08M1 /* Configuration specific to the X-NUCLEO-IHM08M1 expansion board with diff --git a/boards/arm/stm32/nucleo-f446re/scripts/Make.defs b/boards/arm/stm32/nucleo-f446re/scripts/Make.defs index bcfcc2a5b12..9f4d96d0894 100644 --- a/boards/arm/stm32/nucleo-f446re/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f446re/scripts/Make.defs @@ -63,8 +63,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f446re/src/Make.defs b/boards/arm/stm32/nucleo-f446re/src/Make.defs index 34acbcb5f1a..7e8267c02bd 100644 --- a/boards/arm/stm32/nucleo-f446re/src/Make.defs +++ b/boards/arm/stm32/nucleo-f446re/src/Make.defs @@ -49,6 +49,18 @@ ifeq ($(CONFIG_CAN),y) CSRCS += stm32_can.c endif +ifeq ($(CONFIG_STM32_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif diff --git a/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h b/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h index cd15cae311e..f503727d02f 100644 --- a/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h +++ b/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h @@ -192,6 +192,19 @@ #define GPIO_BUTTON_G \ (GPIO_INPUT | GPIO_PULLUP |GPIO_EXTI | GPIO_PORTC | GPIO_PIN7) +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +#define GPIO_IN1 (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \ + GPIO_PORTA | GPIO_PIN7) +#define GPIO_OUT1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6) +#define GPIO_INT1 (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \ + GPIO_PORTC | GPIO_PIN7) + /* Itead Joystick Signal interpretation: * * --------- ----------------------- --------------------------- @@ -330,4 +343,52 @@ int board_ajoy_initialize(void); int stm32_foc_setup(void); #endif +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + * Return Value: + * OK on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + * Return Value: + * OK on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int stm32_gpio_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC0 of the microcontroller. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_DAC) +int stm32_dac_setup(void); +#endif + #endif /* __BOARDS_ARM_STM32_NUCLEO_F401RE_SRC_NUCLEO_F446RE_H */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c index 672e54a03b1..261c98a5375 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c index e0684fc425e..118429ee1ed 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c @@ -159,7 +159,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER /* Initialize and register the qencoder driver */ - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F401RE_QETIMER); + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F446RE_QETIMER); if (ret != OK) { syslog(LOG_ERR, @@ -182,5 +182,35 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Initialize GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); + } +#endif + return ret; } diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c b/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c new file mode 100644 index 00000000000..13de8efe5a0 --- /dev/null +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-f446re/src/stm32_dac.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "stm32_dac.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_DAC + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_DAC1CH1 +static struct dac_dev_s *g_dac1; +#endif + +#ifdef CONFIG_STM32_DAC1CH2 +static struct dac_dev_s *g_dac2; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_dac_setup(void) +{ + int ret; +#ifdef CONFIG_STM32_DAC1CH1 + g_dac1 = stm32_dacinitialize(1); + if (g_dac1 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac0" */ + + ret = dac_register("/dev/dac0", g_dac1); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } + +#endif +#ifdef CONFIG_STM32_DAC1CH2 + g_dac2 = stm32_dacinitialize(2); + if (g_dac2 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac1" */ + + ret = dac_register("/dev/dac1", g_dac2); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} + +#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c b/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c new file mode 100644 index 00000000000..800ffee061f --- /dev/null +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c @@ -0,0 +1,341 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "nucleo-f446re.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value); +#endif +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpout_write(FAR struct gpio_dev_s *dev, bool value); +#endif +#if BOARD_NGPIOINT > 0 +static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpint_attach(FAR struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; +#endif + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(FAR struct gpio_dev_s *dev, bool value) +{ + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(FAR struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable) +{ + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c new file mode 100644 index 00000000000..ee2c0de44ef --- /dev/null +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_arch.h" +#include "stm32_pwm.h" +#include "nucleo-f446re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + * Return Value: + * OK on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef CONFIG_PWM + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + +#if defined(CONFIG_STM32_TIM1_PWM) + pwm = stm32_pwminitialize(1); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM2_PWM) + pwm = stm32_pwminitialize(2); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM3_PWM) + pwm = stm32_pwminitialize(3); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM4_PWM) + pwm = stm32_pwminitialize(4); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c index efdebf8eff3..c425c4af1c5 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f4x1re/configs/f401-nsh/defconfig b/boards/arm/stm32/nucleo-f4x1re/configs/f401-nsh/defconfig index 2054fd42a66..870eef778aa 100644 --- a/boards/arm/stm32/nucleo-f4x1re/configs/f401-nsh/defconfig +++ b/boards/arm/stm32/nucleo-f4x1re/configs/f401-nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/nucleo-f4x1re/configs/f411-mcp2515-extid/defconfig b/boards/arm/stm32/nucleo-f4x1re/configs/f411-mcp2515-extid/defconfig index d8f18467816..1e673bf9aa0 100644 --- a/boards/arm/stm32/nucleo-f4x1re/configs/f411-mcp2515-extid/defconfig +++ b/boards/arm/stm32/nucleo-f4x1re/configs/f411-mcp2515-extid/defconfig @@ -32,7 +32,6 @@ CONFIG_EXAMPLES_CAN_NMSGS=1 CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MCP2515_PHASESEG1=3 CONFIG_MCP2515_PROPSEG=1 CONFIG_MCP2515_SPI_SCK_FREQUENCY=500000 diff --git a/boards/arm/stm32/nucleo-f4x1re/configs/f411-nsh/defconfig b/boards/arm/stm32/nucleo-f4x1re/configs/f411-nsh/defconfig index a0f415f9397..d7b38b269ab 100644 --- a/boards/arm/stm32/nucleo-f4x1re/configs/f411-nsh/defconfig +++ b/boards/arm/stm32/nucleo-f4x1re/configs/f411-nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/nucleo-f4x1re/scripts/Make.defs b/boards/arm/stm32/nucleo-f4x1re/scripts/Make.defs index be1f975d100..8979b5b617e 100644 --- a/boards/arm/stm32/nucleo-f4x1re/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-f4x1re/scripts/Make.defs @@ -69,8 +69,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c index 5da929ca79b..f1a9258ff9e 100644 --- a/boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c +++ b/boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f4x1re/src/stm32_mcp2515.c b/boards/arm/stm32/nucleo-f4x1re/src/stm32_mcp2515.c index c5f6c3fc4c7..51bb9a805c8 100644 --- a/boards/arm/stm32/nucleo-f4x1re/src/stm32_mcp2515.c +++ b/boards/arm/stm32/nucleo-f4x1re/src/stm32_mcp2515.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f4x1re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f4x1re/src/stm32_userleds.c index 0007a56e3a9..89caf861cf4 100644 --- a/boards/arm/stm32/nucleo-f4x1re/src/stm32_userleds.c +++ b/boards/arm/stm32/nucleo-f4x1re/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-g431kb/Kconfig b/boards/arm/stm32/nucleo-g431kb/Kconfig new file mode 100755 index 00000000000..cbd7b6a1ef4 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NUCLEO_G431KB + +endif # ARCH_BOARD_NUCLEO_G431KB diff --git a/boards/arm/stm32/nucleo-g431kb/README.txt b/boards/arm/stm32/nucleo-g431kb/README.txt new file mode 100755 index 00000000000..f8ede7ef9f2 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/README.txt @@ -0,0 +1,13 @@ +README +====== + +The Nucleo-G431KB is a member of the Nucleo-32 board family. The Nucleo-32 +is a standard board for use with several STM32 parts in the UFQFPN32 package. + +STATUS +====== + + 2021-06-11: The basic NSH configuration is now functional. + +Configurations +============== \ No newline at end of file diff --git a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig new file mode 100644 index 00000000000..5ac495da0f1 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_COMP=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2021 +CONFIG_STM32_COMP2=y +CONFIG_STM32_COMP2_HYST=3 +CONFIG_STM32_COMP2_OUT=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig new file mode 100644 index 00000000000..c82df4cd5d4 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=1024 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig new file mode 100644 index 00000000000..083f88a2e41 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=14 +CONFIG_START_YEAR=2021 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/nucleo-g431kb/include/board.h b/boards/arm/stm32/nucleo-g431kb/include/board.h new file mode 100755 index 00000000000..3798e597edc --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/include/board.h @@ -0,0 +1,256 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Nucleo-G431KB supports four ways to configure high-speed clock + * + * - HSI configuration (default): 16 MHz high-speed internal RC oscillator. + * - HSE bypass configuration (from ST-LINK): The input clock is the + * ST-LINK MCO output. The frequency is fixed to 25 MHz, and connected + * to the PF0-OSC_IN of the STM32G4 microcontroller. + * - HSE bypass configuration (from ARDUINO D7): The clock is coming from + * an external oscillator through the pin PF0 (ARDUINO D7 pin 10 of the + * CN4 connector). + * - HSE oscillator configuration: The clock is provided by an external + * 24MHz crystal (X2) available in the PCB. + */ + +#define STM32_BOARD_XTAL 24000000ul /* 24MHz */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The Nucleo-G431KB board has only one user LED, LD2. LD2 is a green LED + * connected to the following STM32G4 pins + * - PB8 (default) + * - PB3 + * It is also connected to Arduino signal D13. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control this LED in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED2 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo-G431KB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is is sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo G431KB don't have buttons that are controllable by software: + * + * B1 RESET: push button connected to NRST is used to RESET the + * STM32G431KB. + */ + +/* Alternate function pin selections ****************************************/ + +/* USART2 (STLINK Virtual COM Port) */ + +#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ +#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 /* PA8 */ + +/* Comparators configuration ************************************************/ + +#define GPIO_COMP2_OUT GPIO_COMP2_OUT_3 /* PA12 */ +#define GPIO_COMP2_INP GPIO_COMP2_INP_2 /* PA7 */ +#define GPIO_COMP2_INM GPIO_COMP2_INM_2 /* PA5 check solder bridge SB2 */ + +/* DMA channels *************************************************************/ + +/* USART2 */ + +#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ +#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs b/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs new file mode 100755 index 00000000000..096438e2dd0 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs @@ -0,0 +1,77 @@ +############################################################################ +# boards/arm/stm32/nucleo-g431kb/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + # Windows-native toolchains + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin -funwind-tables +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -funwind-tables +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -ffunction-sections -fdata-sections -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -ffunction-sections -fdata-sections -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +# Provide map file needed by the "Memory Allocation" view in Eclipse: +LDFLAGS += -Wl,-Map=$(TOPDIR)/NuttX.map -Wl,--gc-sections + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g431kb/scripts/ld.script b/boards/arm/stm32/nucleo-g431kb/scripts/ld.script new file mode 100755 index 00000000000..df8fda891d2 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/scripts/ld.script @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G431KB has 128 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G431KB has a total of 32 KiB of SRAM in three separate areas: + * + * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. + * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. + * + * CCM SRAM (Routine Booster): + * + * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff + * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-g431kb/src/.gitignore b/boards/arm/stm32/nucleo-g431kb/src/.gitignore new file mode 100755 index 00000000000..726d936e1e3 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/arm/stm32/nucleo-g431kb/src/Make.defs b/boards/arm/stm32/nucleo-g431kb/src/Make.defs new file mode 100755 index 00000000000..fce06a22325 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32/nucleo-g431kb/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + +ifeq ($(CONFIG_STM32_COMP),y) +CSRCS += stm32_comp.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h b/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h new file mode 100755 index 00000000000..609d10c5a6e --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_G431KB_SRC_NUCLEO_G431KB_H +#define __BOARDS_ARM_STM32_NUCLEO_G431KB_SRC_NUCLEO_G431KB_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ + +/* The Nucleo G431KB board has four LEDs. Three of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V3. + * LD3 OC: indicates that the board power consumption on USB ST-LINK + * exceeds 500mA. + * LD4 PWR: green LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32G431KB. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) + +#define LED_DRIVER_PATH "/dev/userleds" + +/* PWM */ + +#define NUCLEOG431KB_PWM_TIMER 1 +#define NUCLEOG431KB_PWM_PATH "/dev/pwm0" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_LIB_BOARDCTL=y: + * If CONFIG_NSH_ARCHINITIALIZE=y: + * Called from the NSH library (or other application) + * Otherwise, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int stm32_bringup(void); + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP peripheral for the board. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_COMP +int stm32_comp_setup(void); +#endif + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G431KB_SRC_NUCLEO_G431KB_H */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_appinit.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_appinit.c new file mode 100755 index 00000000000..a6b55c62401 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/stm32_appinit.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/src/stm32_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a pointer + * to configuration data read from a file or serial FLASH, or + * whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return stm32_bringup(); +#endif +} diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c new file mode 100755 index 00000000000..2634defa322 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g431kb.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c new file mode 100755 index 00000000000..71882d802f2 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c new file mode 100755 index 00000000000..fa504d7c271 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_COMP + /* Initialize and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c new file mode 100644 index 00000000000..6a074bda61a --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c @@ -0,0 +1,146 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_STM32_COMP) && (defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4)) + +#ifdef CONFIG_STM32_COMP1 +# if defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP2 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP3 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP4 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) +# error "Currently only one COMP device supported" +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP + * + ****************************************************************************/ + +int stm32_comp_setup(void) +{ + static bool initialized = false; + struct comp_dev_s *comp = NULL; + int ret = OK; + + if (!initialized) + { + /* Get the comparator interface */ + +#ifdef CONFIG_STM32_COMP1 + comp = stm32_compinitialize(1); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 1); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP2 + comp = stm32_compinitialize(2); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 2); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP3 + comp = stm32_compinitialize(3); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 3); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + comp = stm32_compinitialize(4); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 4); + return -ENODEV; + } +#endif + +#ifdef CONFIG_COMP + + /* Register the comparator character driver at /dev/comp0 */ + + ret = comp_register("/dev/comp0", comp); + if (ret < 0) + { + aerr("ERROR: comp_register failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return ret; +} + +#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || + * CONFIG_STM32_COMP2 || + * CONFIG_STM32_COMP3 || + * CONFIG_STM32_COMP4) */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c new file mode 100644 index 00000000000..d6ee92126d8 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_arch.h" +#include "stm32_pwm.h" +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOG431KB_PWM_TIMER); + if (!pwm) + { + tmrerr("Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register(NUCLEOG431KB_PWM_PATH, pwm); + if (ret < 0) + { + tmrerr("pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c new file mode 100755 index 00000000000..0a3e7b6da3a --- /dev/null +++ b/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-g431kb.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig index 4bb376c6888..627d6d44d00 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig @@ -30,7 +30,6 @@ CONFIG_EXAMPLES_ADC_GROUPSIZE=3 CONFIG_EXAMPLES_ADC_SWTRIG=y CONFIG_FDCLONE_STDIO=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig index e69c79c9a74..e2ed3e6dcb9 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig @@ -50,7 +50,6 @@ CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=4 CONFIG_MOTOR=y CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_TRACE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig index 49584d6fadb..f9a1ee69d3e 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig @@ -50,7 +50,6 @@ CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=4 CONFIG_MOTOR=y CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_TRACE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig index f5e9e2a3be1..f8de54bfb6f 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig index cf1607ddca6..2d2f4a05a27 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig @@ -19,7 +19,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_SMALL=y CONFIG_EXAMPLES_PWM=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs b/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs index 827bf5d67de..1f5f74a091c 100644 --- a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs @@ -57,8 +57,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) @@ -69,7 +69,7 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif # Provide map file needed by the "Memory Allocation" view in Eclipse: -LDFLAGS += -Map=$(TOPDIR)/NuttX.map --gc-sections +LDFLAGS += -Wl,-Map=$(TOPDIR)/NuttX.map -Wl,--gc-sections # Embed absolute path to source file in debug information so that Eclipse # source level debugging won't get confused. See: diff --git a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig index 9555afb4249..e74d7183879 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig +++ b/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig @@ -37,7 +37,6 @@ CONFIG_LCD_ILI9341=y CONFIG_LCD_ILI9341_IFACE0=y CONFIG_LCD_ILI9341_IFACE0_PORTRAIT=y CONFIG_LCD_PORTRAIT=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig index 73480b199dc..02ed002cc9f 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y CONFIG_EXAMPLES_HELLO=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=64 diff --git a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs b/boards/arm/stm32/nucleo-l152re/scripts/Make.defs index a10de05ddad..13877afe17e 100644 --- a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs +++ b/boards/arm/stm32/nucleo-l152re/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig index 4f45c173b0c..bb61609c8b1 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig @@ -29,7 +29,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig index 21006c66b7d..37459989271 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig index bbb7f340149..d39cbb2ef59 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig @@ -27,7 +27,6 @@ CONFIG_EXAMPLES_DISCOVER_NOMAC=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NET_ARP_IPIN=y @@ -35,7 +34,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig index 069c6ffe877..1972c5ab2fd 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig @@ -30,7 +30,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig index f4c4de8f39e..49ed4a1f689 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig @@ -52,7 +52,6 @@ CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_MAC802154_NTXDESC=32 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDEVICES=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig index e8d5b35b416..bbe5e744ef2 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig @@ -38,7 +38,6 @@ CONFIG_IEEE802154_MAC=y CONFIG_IEEE802154_MACDEV=y CONFIG_IEEE802154_MRF24J40=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig index e8bbfe85e8e..223ccd7d624 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig @@ -23,7 +23,6 @@ CONFIG_ETH0_PHY_LAN8720=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y @@ -38,7 +37,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig index 844ad17cb91..2e18a93db3e 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig index dae10e9f0b8..8b257ac9969 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig @@ -29,7 +29,6 @@ CONFIG_EXAMPLES_TELNETD_NOMAC=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y @@ -41,7 +40,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig index e466d51c333..9fa791eb763 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig @@ -28,7 +28,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig index e096190afac..43169da6076 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig index b627c079991..49c58975bae 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig @@ -25,7 +25,6 @@ CONFIG_EXAMPLES_WEBSERVER_DRIPADDR=0xc0a80101 CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y @@ -37,7 +36,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs index 77cdc871aaf..a6917305860 100644 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs +++ b/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs @@ -57,8 +57,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c index 99fe8ee47c8..68cf2bc5107 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c index 9665ff7605a..c7b0b02dea3 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c @@ -1,37 +1,20 @@ /**************************************************************************** * boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c * - * Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Laurent Latil - * Modify by: Acutronics Robotics (Juan Flores) + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig index f87669d9304..40456fe3c95 100644 --- a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig @@ -35,7 +35,6 @@ CONFIG_EXAMPLES_CAN=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_GET=y diff --git a/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs index 9cdf37e8b52..68976ae39f0 100644 --- a/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs +++ b/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig index 1b25093a01e..319cf8de6cf 100644 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig index 9cf01ef1048..7797176bb96 100644 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig +++ b/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig @@ -24,7 +24,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_FS_PROCFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs index 1e3ba2434ec..c7984ae4d53 100644 --- a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs +++ b/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig index 4ac073d8dc4..f38bd8c663b 100644 --- a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_BUILTIN=y CONFIG_CAN=y CONFIG_ETH0_PHY_KS8721=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MTD=y CONFIG_NET=y diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs index e5fb9d12e71..ab51a5a1aca 100644 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs +++ b/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c b/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c index 984b21720eb..71c548a7938 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c +++ b/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig index 77ba4ce495c..09002e71667 100644 --- a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_EXAMPLES_ADC_GROUPSIZE=1 CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y @@ -38,7 +37,6 @@ CONFIG_NETINIT_IPADDR=0xa0000002 CONFIG_NETINIT_NOMAC=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y diff --git a/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs index ab10eb13fbb..aee38d5ecb2 100644 --- a/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs +++ b/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig index 3d5b9c894d6..7fa3daacd01 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig @@ -30,7 +30,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig index 1d45d7174e3..4474938eda3 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig index f74dbb99713..e82f3bc8742 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_GET=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs index 90a9a9a4855..359645cc2aa 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs +++ b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs @@ -53,8 +53,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF kernel module definitions diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig index 50a19392cee..1b471ddd451 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_ARM_MPU=y CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILD_PROTECTED=y @@ -30,8 +31,8 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_HAVE_CXX=y CONFIG_INTELHEX_BINARY=y +CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_MM_KERNEL_HEAPSIZE=16384 CONFIG_MM_REGIONS=2 CONFIG_NUTTX_USERSPACE=0x08020000 @@ -54,7 +55,7 @@ CONFIG_STM32_SDIO=y CONFIG_STM32_USART3=y CONFIG_STM32_USBHOST=y CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USBHOST_ISOC_DISABLE=y CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs index 8a2df2be91d..0fc037c1ad9 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs +++ b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs @@ -53,8 +53,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF kernel module definitions diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig index ecc3d29d339..953a8225ee1 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_ARM_MPU=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILD_PROTECTED=y @@ -29,7 +30,6 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MM_KERNEL_HEAPSIZE=16384 CONFIG_MM_REGIONS=2 CONFIG_MODULE=y @@ -51,7 +51,7 @@ CONFIG_STM32_PWR=y CONFIG_STM32_USART3=y CONFIG_STM32_USBHOST=y CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USBHOST_ISOC_DISABLE=y CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs index 9efb144d759..9ad76c27d4a 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs +++ b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig index 928051f05f4..f7b04216a97 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig @@ -23,7 +23,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MM_KERNEL_HEAPSIZE=16384 CONFIG_NSH_DISABLE_DD=y CONFIG_NSH_DISABLE_GET=y @@ -52,7 +51,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=y CONFIG_STM32_PWR=y CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=32 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig index 4238f1ab480..783971988ad 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_EXAMPLES_MODULE=y @@ -25,7 +26,6 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_MODULE=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig index cef93e2cfa4..982d83186be 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HTS221_DEBUG=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_IPv4ADDR=0xc0a80101 @@ -40,7 +39,6 @@ CONFIG_NETUTILS_MQTTC=y CONFIG_NETUTILS_TELNETD=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig index 4c1b64d48ad..418d3f33ab7 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig index 0b2b1b3f766..200a65270e6 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig @@ -28,7 +28,6 @@ CONFIG_I2C_POLLED=y CONFIG_I2C_RESET=y CONFIG_I2S=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile b/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile index 71cdc0af22f..5cc2fa19947 100644 --- a/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile +++ b/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c b/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c index a6d3a3f4aa0..efe32d85082 100644 --- a/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c +++ b/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs index 3eb16dc804f..33ea5f26a73 100644 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs +++ b/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c index 72fd762260d..0a8472cdee4 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c +++ b/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig b/boards/arm/stm32/olimexino-stm32/configs/can/defconfig index bf612b88d45..fbca71c9bdf 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/can/defconfig @@ -53,7 +53,6 @@ CONFIG_I2C_RESET=y CONFIG_IDLETHREAD_STACKSIZE=300 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_SENDFILE_BUFSIZE=0 -CONFIG_MAX_TASKS=16 CONFIG_MM_SMALL=y CONFIG_NAME_MAX=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 diff --git a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig b/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig index e0e252e5dc3..dfc6fa095a7 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig @@ -71,7 +71,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=300 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_SENDFILE_BUFSIZE=0 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_SMALL=y CONFIG_NAME_MAX=8 diff --git a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig index 4692b7868c7..a6ec6581750 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig @@ -59,7 +59,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=300 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_SENDFILE_BUFSIZE=0 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_SMALL=y CONFIG_NAME_MAX=8 diff --git a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig index ebe4b26328a..dfa98145278 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig @@ -36,7 +36,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=300 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_SENDFILE_BUFSIZE=0 -CONFIG_MAX_TASKS=4 CONFIG_MM_SMALL=y CONFIG_NAME_MAX=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 diff --git a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig b/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig index 09e085c0c34..e4f31f1fef8 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig @@ -37,7 +37,6 @@ CONFIG_IDLETHREAD_STACKSIZE=300 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_SENDFILE_BUFSIZE=0 -CONFIG_MAX_TASKS=4 CONFIG_MM_SMALL=y CONFIG_NAME_MAX=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 diff --git a/boards/arm/stm32/olimexino-stm32/scripts/Make.defs b/boards/arm/stm32/olimexino-stm32/scripts/Make.defs index 9aa827c7ae4..5071e35d4dc 100644 --- a/boards/arm/stm32/olimexino-stm32/scripts/Make.defs +++ b/boards/arm/stm32/olimexino-stm32/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c b/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c index fba5b4a93de..0412a6d321d 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c +++ b/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c @@ -25,7 +25,8 @@ #include #include -#include +#include +#include #include #include diff --git a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig index 550bf2748f9..b0b109be7a9 100644 --- a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig +++ b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig @@ -53,7 +53,6 @@ CONFIG_IOB_NBUFFERS=24 CONFIG_IOB_NCHAINS=8 CONFIG_LIB_HOSTNAME="omnibusf4" CONFIG_M25P_SPIFREQUENCY=75000000 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_IOB=y CONFIG_MM_REGIONS=2 diff --git a/boards/arm/stm32/omnibusf4/kernel/Makefile b/boards/arm/stm32/omnibusf4/kernel/Makefile index df064e27a3f..70a10c5219c 100644 --- a/boards/arm/stm32/omnibusf4/kernel/Makefile +++ b/boards/arm/stm32/omnibusf4/kernel/Makefile @@ -63,7 +63,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c b/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c index a3ffc8d7459..08c02ae1a8e 100644 --- a/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c +++ b/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c @@ -112,9 +112,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32/omnibusf4/scripts/Make.defs b/boards/arm/stm32/omnibusf4/scripts/Make.defs index 0f38726532e..1e3863a6cea 100644 --- a/boards/arm/stm32/omnibusf4/scripts/Make.defs +++ b/boards/arm/stm32/omnibusf4/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/stm32/photon/configs/adb/defconfig b/boards/arm/stm32/photon/configs/adb/defconfig index 86527bc06da..b0d1074f2b6 100644 --- a/boards/arm/stm32/photon/configs/adb/defconfig +++ b/boards/arm/stm32/photon/configs/adb/defconfig @@ -42,7 +42,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBUV=y CONFIG_LIBUV_PIPE=y CONFIG_LIBUV_STREAM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/photon/configs/nsh/defconfig b/boards/arm/stm32/photon/configs/nsh/defconfig index 1a2428e5e5a..71562c45902 100644 --- a/boards/arm/stm32/photon/configs/nsh/defconfig +++ b/boards/arm/stm32/photon/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/photon/configs/rgbled/defconfig b/boards/arm/stm32/photon/configs/rgbled/defconfig index db7ac09a1cf..138c5a1f6e0 100644 --- a/boards/arm/stm32/photon/configs/rgbled/defconfig +++ b/boards/arm/stm32/photon/configs/rgbled/defconfig @@ -27,7 +27,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/photon/configs/usbnsh/defconfig b/boards/arm/stm32/photon/configs/usbnsh/defconfig index bb5351ffa77..674243f4427 100644 --- a/boards/arm/stm32/photon/configs/usbnsh/defconfig +++ b/boards/arm/stm32/photon/configs/usbnsh/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/photon/configs/wlan/defconfig b/boards/arm/stm32/photon/configs/wlan/defconfig index 3b90e0abaad..3a346d4b628 100644 --- a/boards/arm/stm32/photon/configs/wlan/defconfig +++ b/boards/arm/stm32/photon/configs/wlan/defconfig @@ -35,7 +35,6 @@ CONFIG_IEEE80211_BROADCOM_BCM43362=y CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=2 @@ -54,7 +53,6 @@ CONFIG_NET_GUARDSIZE=32 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_PKT=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/photon/scripts/Make.defs b/boards/arm/stm32/photon/scripts/Make.defs index 8e9e2d33441..f2b75ee8d82 100644 --- a/boards/arm/stm32/photon/scripts/Make.defs +++ b/boards/arm/stm32/photon/scripts/Make.defs @@ -60,8 +60,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/shenzhou/configs/nsh/defconfig b/boards/arm/stm32/shenzhou/configs/nsh/defconfig index 4da0bdafca9..8aabfe0a976 100644 --- a/boards/arm/stm32/shenzhou/configs/nsh/defconfig +++ b/boards/arm/stm32/shenzhou/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_HAVE_CXX=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_NET=y diff --git a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig b/boards/arm/stm32/shenzhou/configs/nxwm/defconfig index f9d30a4eab5..daeea066f75 100644 --- a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig +++ b/boards/arm/stm32/shenzhou/configs/nxwm/defconfig @@ -35,7 +35,6 @@ CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y CONFIG_LCD_SSD1289=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig b/boards/arm/stm32/shenzhou/configs/thttpd/defconfig index dabe049064f..cf26dced9ea 100644 --- a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig +++ b/boards/arm/stm32/shenzhou/configs/thttpd/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_NXFFS=y CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MTD=y CONFIG_MTD_W25=y CONFIG_NET=y diff --git a/boards/arm/stm32/shenzhou/scripts/Make.defs b/boards/arm/stm32/shenzhou/scripts/Make.defs index 67d3c091a84..f07339c780b 100644 --- a/boards/arm/stm32/shenzhou/scripts/Make.defs +++ b/boards/arm/stm32/shenzhou/scripts/Make.defs @@ -60,9 +60,9 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -#NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections +#NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c b/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c index bdc0f2db74a..5a5038699f9 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c +++ b/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c @@ -121,6 +121,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c b/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c index 3e2accf363c..a11eea65269 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c +++ b/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig b/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig index 54bded96fc7..623213128af 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig @@ -28,7 +28,6 @@ CONFIG_COMPOSITE_VENDORID=0x03eb CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig index 5f9d3b21115..f35b88497eb 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_FAT_LCNAMES=y CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MTD=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig index 189bb1ce2b4..e861d410e8b 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig @@ -53,7 +53,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y CONFIG_LCD_RPORTRAIT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig index 94e4bd723ce..a9b2ad1431d 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig @@ -37,7 +37,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y CONFIG_LCD_RPORTRAIT=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig index ade9d66f6c2..e6f7a6ffba9 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig @@ -26,7 +26,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig index fc888a0255f..1b9ebac3204 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig @@ -48,7 +48,6 @@ CONFIG_LCD_MAXCONTRAST=100 CONFIG_LCD_MAXPOWER=100 CONFIG_LCD_NOGETRUN=y CONFIG_LCD_RPORTRAIT=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig index 2e230a378fc..fa8bf046ee7 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig @@ -18,7 +18,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig index df0b7be0d87..de20f94af44 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig @@ -19,7 +19,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_EXAMPLES_USBSERIAL=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_PL2303=y CONFIG_PL2303_PRODUCTSTR="USBdev Serial" CONFIG_PL2303_RXBUFSIZE=512 diff --git a/boards/arm/stm32/stm3210e-eval/scripts/Make.defs b/boards/arm/stm32/stm3210e-eval/scripts/Make.defs index 6d6f1b0f748..da523dd7bf2 100644 --- a/boards/arm/stm32/stm3210e-eval/scripts/Make.defs +++ b/boards/arm/stm32/stm3210e-eval/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c b/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c index 3f9d3e7dc2f..ac137847f55 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c b/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c index 667ead198a5..01db1258ff6 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c b/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c index b5fbdc859b6..7d8865f8347 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c index bfcead134cb..d8997589e99 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c @@ -67,6 +67,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig index f1f8cc6de6e..beca4805ee9 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_DHCPD=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig index e9c3454ecab..a4e33772c87 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NET_ICMP=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig index d00332fc9ad..52322f10a2a 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_I2C_POLLED=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MTD=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig index a76f4648d07..4e0114709f9 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig @@ -32,7 +32,6 @@ CONFIG_I2CTOOL_DEFFREQ=100000 CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2C_POLLED=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig index 704237d4802..0dadc7cc911 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig @@ -36,7 +36,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MQ_MAXMSGSIZE=64 diff --git a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig index 012e1672707..2226a5ab7c3 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs b/boards/arm/stm32/stm3220g-eval/scripts/Make.defs index 1d10042cd1a..c9999b8e7af 100644 --- a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs +++ b/boards/arm/stm32/stm3220g-eval/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_appinit.c b/boards/arm/stm32/stm3220g-eval/src/stm32_appinit.c index e00b4b2c5c6..77a27737b04 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_appinit.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_appinit.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c index 0bde4497b16..c67a1a8ae61 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c b/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c index ff53b5f66ac..8be1876d298 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig index 5dc7600b1ea..8f524878795 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_DHCPD=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig b/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig index 70128776311..ce3483a133c 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_I2C_POLLED=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 @@ -37,7 +36,6 @@ CONFIG_NET_ETH_PKTSIZE=650 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig b/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig index a59251256d3..a20ddb7ad84 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig @@ -33,7 +33,6 @@ CONFIG_LCD=y CONFIG_LCD_FRAMEBUFFER=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs b/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs index e50b256f048..4f994ebeaab 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs +++ b/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig index 8e33f7a80f6..ed933046e01 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig @@ -38,7 +38,6 @@ CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_USRWORK=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NUTTX_USERSPACE=0x08040000 @@ -93,7 +92,7 @@ CONFIG_STMPE811_THRESHX=39 CONFIG_STMPE811_THRESHY=51 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_READLINE=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_RXBUFSIZE=128 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig index 0fa84e5492e..becb46abf35 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig index 6dc099800b5..ba7a3bdc7dc 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_I2CTOOL_DEFFREQ=100000 CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2C_POLLED=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig index bfce92b2fa1..d152d25d5a0 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig @@ -33,7 +33,6 @@ CONFIG_I2CTOOL_DEFFREQ=100000 CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2C_POLLED=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig index 9dad057f650..894ab6aaae4 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig @@ -37,7 +37,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NET=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig index 62fcfe50d04..62d728c2864 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig @@ -35,7 +35,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NET=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig index d8cf5465e5b..d40c0c47c98 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig @@ -28,7 +28,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig b/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig index 86808120176..e1f6550f1cc 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig @@ -28,7 +28,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_I2C_POLLED=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MTD=y CONFIG_NET=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig b/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig index e6b11a01faa..baa7f4b7fc0 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_I2C_POLLED=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 @@ -36,7 +35,6 @@ CONFIG_NET_ETH_PKTSIZE=650 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y diff --git a/boards/arm/stm32/stm3240g-eval/kernel/Makefile b/boards/arm/stm32/stm3240g-eval/kernel/Makefile index 7d92f1b5f2c..1169b47f922 100644 --- a/boards/arm/stm32/stm3240g-eval/kernel/Makefile +++ b/boards/arm/stm32/stm3240g-eval/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c b/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c index 2faeb54bdd1..4eafb03e4ec 100644 --- a/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c +++ b/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c @@ -94,9 +94,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs b/boards/arm/stm32/stm3240g-eval/scripts/Make.defs index c9861aa029d..153e4ae3e2d 100644 --- a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs +++ b/boards/arm/stm32/stm3240g-eval/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c b/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c index aea590f3d17..68a5336027d 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c index 3a81f7ef5b4..f736928c37c 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c b/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c index 534e3ccfa09..4cfe65980fc 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig index 7143e7119d9..28952194f60 100644 --- a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EXAMPLES_NRF24L01TERM=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig index 93f4f0e7af1..84d92c231c7 100644 --- a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig @@ -34,7 +34,6 @@ CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_DEFAULT_SMALL=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_LINELEN=80 diff --git a/boards/arm/stm32/stm32_tiny/scripts/Make.defs b/boards/arm/stm32/stm32_tiny/scripts/Make.defs index f97f56c6e4d..3613a6f3023 100644 --- a/boards/arm/stm32/stm32_tiny/scripts/Make.defs +++ b/boards/arm/stm32/stm32_tiny/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig index 3dc8b3f99a0..52104755f8b 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig @@ -38,7 +38,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig index 4a2f4ad68cc..849a002f61b 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig @@ -39,7 +39,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR_SHORT=y CONFIG_LIB_HOSTNAME="butterfly2" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NET=y CONFIG_NETINIT_DRIPADDR=0x0a010101 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig index db9215dfb49..5a2dc95c497 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig @@ -36,7 +36,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig index 3dc8b3f99a0..52104755f8b 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig @@ -38,7 +38,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32butterfly2/include/board.h b/boards/arm/stm32/stm32butterfly2/include/board.h index 00759016a47..00b5082a43a 100644 --- a/boards/arm/stm32/stm32butterfly2/include/board.h +++ b/boards/arm/stm32/stm32butterfly2/include/board.h @@ -1,35 +1,20 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/include/board.h * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32butterfly2/scripts/Make.defs b/boards/arm/stm32/stm32butterfly2/scripts/Make.defs index 546ef49aad3..9adc068dbf3 100644 --- a/boards/arm/stm32/stm32butterfly2/scripts/Make.defs +++ b/boards/arm/stm32/stm32butterfly2/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32butterfly2/src/Make.defs b/boards/arm/stm32/stm32butterfly2/src/Make.defs index 645616df6a7..a4cbc04832a 100644 --- a/boards/arm/stm32/stm32butterfly2/src/Make.defs +++ b/boards/arm/stm32/stm32butterfly2/src/Make.defs @@ -1,35 +1,21 @@ ############################################################################ # boards/arm/stm32/stm32butterfly2/src/Make.defs # -# Copyright (C) 2016 Michał Łyszczek. All rights reserved. -# Author: Michał Łyszczek +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: +# http://www.apache.org/licenses/LICENSE-2.0 # -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. # -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. ############################################################################ include $(TOPDIR)/Make.defs diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c b/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c index 0d5f2e75fef..0fd6097f93c 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_adc.c * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c b/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c index 52c8c9b6c17..01fd4510885 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_boot.c * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h b/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h index 9f45d638d04..0842271a164 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ #ifndef __BOARDS_ARM_STM32_STM32_BUTTERFLY2_SRC_STM32_BUTTERFLY2_H diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c b/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c index e5686dba607..3e334832d10 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c b/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c index 2ededd42b40..eeb147a8363 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_leds.c * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c b/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c index 8fe7960f191..365d747e923 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c * - * Copyright (C) 2016-2017 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c b/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c index 2386fd4cc40..ba0df5c3415 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_spi.c * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c index adc55f7f225..d340313943f 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_usb.c * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c index 694436377f7..2e2e82ab0a1 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c index a957402891a..ef584b216f8 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c @@ -1,35 +1,21 @@ /**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c * - * Copyright (C) 2016 Michał Łyszczek. All rights reserved. - * Author: Michał Łyszczek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig index 3d945ceedc1..9a0269352c8 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig @@ -41,7 +41,6 @@ CONFIG_FS_PROCFS_EXCLUDE_MOUNTS=y CONFIG_LIBUV=y CONFIG_LIBUV_PIPE=y CONFIG_LIBUV_STREAM=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFCONFIG=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig index 355bc520cf8..d1c8cac5f35 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig @@ -30,7 +30,6 @@ CONFIG_DEFAULT_SMALL=y CONFIG_EXAMPLES_APDS9960=y CONFIG_I2C_DRIVER=y CONFIG_IDLETHREAD_STACKSIZE=512 -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig index 08a6e992d4e..9cf94523351 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig @@ -30,7 +30,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_DRIVERS_AUDIO=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig index c0d09be4a54..14a7b810474 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig @@ -35,7 +35,6 @@ CONFIG_EXAMPLES_BUTTONS=y CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig index 762346b4188..0034fcb2113 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig @@ -29,7 +29,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_FDCLONE_STDIO=y -CONFIG_MAX_TASKS=4 CONFIG_MM_SMALL=y CONFIG_NSH_DISABLE_CP=y CONFIG_NSH_DISABLE_MKDIR=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig index 66e7729d889..4587193ac9c 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig @@ -34,7 +34,6 @@ CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 CONFIG_LCD=y CONFIG_LCD_ST7567=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig index 57fad5645b9..75319ac55a6 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig @@ -34,7 +34,6 @@ CONFIG_I2CTOOL_MAXBUS=1 CONFIG_I2CTOOL_MINBUS=1 CONFIG_LCD_BACKPACK=y CONFIG_LCD_LCD1602=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig index e985b7cf9e2..8fc866d60e9 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig @@ -33,7 +33,6 @@ CONFIG_CAN_TXREADY=y CONFIG_DEFAULT_SMALL=y CONFIG_EXAMPLES_CAN=y CONFIG_EXAMPLES_CAN_READ=y -CONFIG_MAX_TASKS=16 CONFIG_MCP2515_PHASESEG1=3 CONFIG_MCP2515_PROPSEG=1 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig index 3dd924144ad..0c9c6082559 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig @@ -29,7 +29,6 @@ CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EXAMPLES_NRF24L01TERM=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig index 45fd68540b8..e099101d3d3 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig index ee0ad906a94..5ca06b45ce6 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig @@ -28,7 +28,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_EXAMPLES_PWM=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig index 74335ab9002..affef8ee23b 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig @@ -30,7 +30,6 @@ CONFIG_CL_MFRC522=y CONFIG_DEFAULT_SMALL=y CONFIG_DRIVERS_CONTACTLESS=y CONFIG_EXAMPLES_RFID_READUID=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig index 2687886623a..651fe8c235d 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig @@ -28,7 +28,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_EXAMPLES_RGBLED=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig index a4e964afa9d..4fe4afc8799 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig @@ -15,14 +15,12 @@ # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_PS is not set -CONFIG_1WIRE_DS28E17=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_MKRD=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=5483 @@ -36,7 +34,6 @@ CONFIG_I2C=y CONFIG_I2C_DRIVER=y CONFIG_I2C_RESET=y CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_CP=y @@ -81,7 +78,7 @@ CONFIG_STM32_USART2=y CONFIG_STM32_USART2_1WIREDRIVER=y CONFIG_STM32_USART_SINGLEWIRE=y CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_SENSORTEST=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig index e9f73ba91c6..324e7a9ad3e 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig @@ -34,7 +34,6 @@ CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_DEFAULT_SMALL=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_LINELEN=80 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig index 317f2596950..dbeaa7f1ebb 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig @@ -30,7 +30,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_EXAMPLES_LEDS=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig index 7ede642a35c..a35cc7c4289 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig @@ -28,7 +28,6 @@ CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs b/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs index d97260e43cf..5ede0bfea49 100644 --- a/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs +++ b/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs @@ -55,11 +55,11 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 -LDFLAGS += --gc-sections +LDFLAGS += -Wl,--gc-sections ifneq ($(CROSSDEV),arm-nuttx-elf-) LDFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c index 3ecc5b08b08..ae5f15734f6 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c index f8dee31cd7d..dfdbe7f2abe 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig b/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig index e261cafbab8..969c0095ef7 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig @@ -40,7 +40,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBDSP=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig index 5242875422b..77d4c5c234a 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_FDCLONE_STDIO=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_BASENAME=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig index d4f60ee7f11..f0254d255ad 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig @@ -36,7 +36,6 @@ CONFIG_FDCLONE_STDIO=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=4 CONFIG_NAME_MAX=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs b/boards/arm/stm32/stm32f334-disco/scripts/Make.defs index 38141133bfb..1a51646f875 100644 --- a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs +++ b/boards/arm/stm32/stm32f334-disco/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig index b2a26e5f0bb..43c71583b3a 100644 --- a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig index 5e313adfac1..61982ba6f0e 100644 --- a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs b/boards/arm/stm32/stm32f3discovery/scripts/Make.defs index d1de262fa92..1a21640fcda 100644 --- a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs +++ b/boards/arm/stm32/stm32f3discovery/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig index 6af4bfa62c5..44f19e53bf7 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BOARD_LOOPSPERMSEC=8499 CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs b/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs index ada4018691f..0924ab753b3 100644 --- a/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs +++ b/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig index 61b07b7d156..019959f2d43 100644 --- a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_BOARD_LOOPSPERMSEC=8499 CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs b/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs index 8955673c0ce..e72740d0c10 100644 --- a/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs +++ b/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig index 08ab38399f1..aaa6a1e8be6 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 CONFIG_HEAP2_SIZE=8388608 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig index d827d2538ac..cb7207be4d5 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 CONFIG_HEAP2_SIZE=8388608 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MTD_CONFIG=y CONFIG_MTD_CONFIG_RAM_CONSOLIDATE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig index 7d40d3d5a53..8b8ebe9bfc9 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig @@ -32,7 +32,6 @@ CONFIG_HEAP2_SIZE=7774208 CONFIG_INPUT=y CONFIG_INPUT_STMPE811=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig index 05fff911d2c..1801a67939d 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig @@ -25,7 +25,6 @@ CONFIG_HEAP2_SIZE=8388608 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig index b78a9acdb8e..d1719628b14 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig @@ -33,7 +33,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_ILI9341=y CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig index 527079f8695..b7026e39b00 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig @@ -36,7 +36,6 @@ CONFIG_INPUT_STMPE811=y CONFIG_INTELHEX_BINARY=y CONFIG_LV_HOR_RES=240 CONFIG_LV_VER_RES=320 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig index 5e9167f39a2..01f01386e85 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 CONFIG_HEAP2_SIZE=8388608 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig index a5a4a045958..c06a87e42e0 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 CONFIG_HEAP2_SIZE=8388608 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig index edf5eb8a0e7..55330492b24 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig @@ -37,7 +37,6 @@ CONFIG_HEAP2_SIZE=8081408 CONFIG_INPUT=y CONFIG_INPUT_STMPE811=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig index 8d032fd95e4..8c51bf8d501 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 CONFIG_HEAP2_SIZE=8388608 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig index 581631291c8..0ebfee5221c 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig @@ -33,7 +33,6 @@ CONFIG_HEAP2_SIZE=8388608 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs b/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs index 080702e852f..fa03cb33635 100644 --- a/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs +++ b/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c index cbafe5653b7..31d1e1fc382 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c index 656edba9b01..3c7444e2d08 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c index 5d2bcf6ecf5..bf149612735 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig index b2fd2e9d9d0..732db60b522 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig @@ -45,7 +45,6 @@ CONFIG_LIBUV=y CONFIG_LIBUV_PIPE=y CONFIG_LIBUV_STREAM=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig b/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig index 99b1dd6d534..bf2d119c501 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig @@ -36,7 +36,6 @@ CONFIG_I2C_DRIVER=y CONFIG_I2C_POLLED=y CONFIG_I2C_RESET=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig b/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig index 174e9e209af..c337587af4b 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig @@ -27,7 +27,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/Make.defs b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/Make.defs index 2038d5efaa3..3b0d2d57cdd 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/Make.defs +++ b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig index 37ec47b4a52..456d9e64db9 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig @@ -21,7 +21,6 @@ CONFIG_HAVE_CXX=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 diff --git a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig b/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig index fde912cf91d..89da21a5449 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_CONSOLE_SYSLOG=y @@ -24,8 +25,8 @@ CONFIG_EXAMPLES_ELF=y CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_INTELHEX_BINARY=y +CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PATH_INITIAL="/mnt/romfs" CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/stm32/stm32f4discovery/configs/hciuart/defconfig b/boards/arm/stm32/stm32f4discovery/configs/hciuart/defconfig index a774de30334..baf60dd61d5 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/hciuart/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/hciuart/defconfig @@ -39,7 +39,6 @@ CONFIG_IOB_NBUFFERS=64 CONFIG_IOB_NCHAINS=16 CONFIG_IOB_THROTTLE=16 CONFIG_LIB_HOSTNAME="STM32F4-Discovery" -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig index 2c396f79800..0bffd1a4fa2 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HOSTNAME="STM32F4-Discovery" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig index 627462d8e76..1c5c3063c32 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig @@ -22,7 +22,6 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NUTTX_USERSPACE=0x08020000 CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel" @@ -39,7 +38,7 @@ CONFIG_START_YEAR=2013 CONFIG_STM32_JTAG_SW_ENABLE=y CONFIG_STM32_USART2=y CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TESTING_OSTEST=y CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3 CONFIG_TESTING_OSTEST_STACKSIZE=2048 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig index e9ba8a07426..5cb7e61d863 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig @@ -29,7 +29,6 @@ CONFIG_I2C=y CONFIG_INTELHEX_BINARY=y CONFIG_LCD_BACKPACK=y CONFIG_LCD_LCD1602=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig index 6eb7d6606c1..ae9cb5a6817 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LWL_CONSOLE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig index 4c2bc69bf85..7b7915ce090 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig index daa86a75114..cc7f4c1b658 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig @@ -52,7 +52,6 @@ CONFIG_LCD_MAX7219=y CONFIG_LCD_NOGETRUN=y CONFIG_LIBC_LONG_LONG=y CONFIG_MAX7219_NHORIZONTALBLKS=4 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig index d524c8bb3ad..ea00e7c6271 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig @@ -37,7 +37,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP_COLORATION=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_SENDFILE_BUFSIZE=1024 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_REGIONS=2 CONFIG_NETUTILS_CODECS=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig index ffc1a975656..1243b922ad6 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig @@ -31,7 +31,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MODBUS=y CONFIG_MODBUS_SLAVE=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig b/boards/arm/stm32/stm32f4discovery/configs/module/defconfig index 770a306652a..c78151462fd 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/module/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_EXAMPLES_MODULE=y @@ -25,7 +26,6 @@ CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MODULE=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig index 1fd6d5dde32..633bc623497 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HOSTNAME="STM32F4-Discovery" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig index 175dac039f7..b26ebd8797b 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig index 05c42e4244f..68768c012d0 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig @@ -36,7 +36,6 @@ CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_MAXPOWER=255 CONFIG_LCD_SSD1289=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig index 2088376887a..49ca6404820 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig b/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig index 135bd39de60..cf6c772d21d 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_CONSTRUCTORS=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_CONSOLE_SYSLOG=y CONFIG_ELF=y @@ -28,7 +29,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PATH_INITIAL="/mnt/romfs" CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig index 27c745b377d..1ae9cf895a0 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig index a11f098ea84..02ccff030d5 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig index 619d17f433d..1aa38f83d05 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig @@ -36,7 +36,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 diff --git a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig index 8011087cbc1..3a85f7fe0d9 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig @@ -23,7 +23,6 @@ CONFIG_BUILTIN=y CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig index dbe45f10200..2c12b29e4e9 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig @@ -32,7 +32,6 @@ CONFIG_LCD_FRAMEBUFFER=y CONFIG_LCD_NOGETRUN=y CONFIG_LCD_PORTRAIT=y CONFIG_LCD_ST7789=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/Make.defs b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/Make.defs index 23416fff509..94e98cb6d80 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/Make.defs +++ b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/Make.defs @@ -77,8 +77,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig index f949ee7177c..83f35795aff 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig @@ -26,7 +26,6 @@ CONFIG_LIBCXX=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LOCALTIME=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig index 19faecbd049..8f881b6f821 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig @@ -24,7 +24,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig index 78667024faf..8556157b483 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig @@ -30,7 +30,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig index a305d584ebc..b97710140f3 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig @@ -43,7 +43,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_SENDFILE_BUFSIZE=1024 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_REGIONS=2 CONFIG_NET=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/winbuild/Make.defs b/boards/arm/stm32/stm32f4discovery/configs/winbuild/Make.defs index 771ad598245..fe5eba0431e 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/winbuild/Make.defs +++ b/boards/arm/stm32/stm32f4discovery/configs/winbuild/Make.defs @@ -47,8 +47,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)\binfmt\libnxflat\gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)\binfmt\libnxflat\gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 LDFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/arm/stm32/stm32f4discovery/configs/winbuild/defconfig b/boards/arm/stm32/stm32f4discovery/configs/winbuild/defconfig index 1213b0981f8..ce69b344c52 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/winbuild/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/winbuild/defconfig @@ -20,7 +20,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_EXPERIMENTAL=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 diff --git a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig b/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig index bc201a4bc43..e841c83e847 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig @@ -24,7 +24,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32/stm32f4discovery/kernel/Makefile b/boards/arm/stm32/stm32f4discovery/kernel/Makefile index 2a43089e594..34ea2b7bd67 100644 --- a/boards/arm/stm32/stm32f4discovery/kernel/Makefile +++ b/boards/arm/stm32/stm32f4discovery/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) $(USER_LIBGCC) --end-group + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) $(USER_LIBGCC) -Wl,--end-group $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c b/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c index 1ec35a3ae71..ff60953b5f0 100644 --- a/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c +++ b/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs b/boards/arm/stm32/stm32f4discovery/scripts/Make.defs index 9920ba16783..7edfe3dee5c 100644 --- a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs +++ b/boards/arm/stm32/stm32f4discovery/scripts/Make.defs @@ -63,8 +63,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c b/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c index acd7dd7b35b..aa5a6dd2163 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c @@ -38,6 +38,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c index 750d2a97493..22e5a81233a 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig index 9ca50667357..97cc29185ec 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig +++ b/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig @@ -35,7 +35,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LIB_SLCDCODEC=y CONFIG_LWL_CONSOLE=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig index 06044111567..15ba98b0635 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_DISABLE_CD=y diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs b/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs index 08e97cf5c9d..decdc6b2675 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs +++ b/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c index 19ad107f0e3..3453915db53 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig index 9f2b6377350..e31640eb350 100644 --- a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig @@ -34,7 +34,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_SMALL=y CONFIG_IDLETHREAD_STACKSIZE=128 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs b/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs index 110b13ab11e..18e6192a1b0 100644 --- a/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs +++ b/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs @@ -67,13 +67,13 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS = -nostartfiles -nodefaultlibs + LDFLAGS += -nostartfiles -nodefaultlibs endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS = -g + LDFLAGS += -g endif diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig index d2bb66805cc..0a3469b1913 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig @@ -23,7 +23,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_FT80X=y CONFIG_LCD_FT80X_AUDIO_GPIOSHUTDOWN=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig index f3e40269b09..9a1adcc4866 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65536 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig index 6bae55158f8..599059add1e 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig @@ -23,7 +23,6 @@ CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 CONFIG_LIB_HOSTNAME="Viewtool-STM32F107" -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_NOADDR=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig index e120948b264..0baad6d7200 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_BUILTIN=y CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig index ec2dfa05f6d..f32f8cdb776 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig @@ -24,7 +24,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=50 CONFIG_IOB_NCHAINS=12 CONFIG_LIB_HOSTNAME="Viewtool-STM32F107" -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETINIT_NOMAC=y CONFIG_NETINIT_THREAD=y diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs b/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs index 79fb23fb163..ee0969983da 100644 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs +++ b/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c index b08cafd0011..f76db4d2431 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c @@ -25,7 +25,6 @@ #include #include -#include #include #include diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c index 68cd63e3d0d..b795b5fbf5f 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig index 2358e628520..47f9e0488b4 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig @@ -28,7 +28,6 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_SWTRIG=y CONFIG_EXPERIMENTAL=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig index 66dd577f820..6c423e4481b 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXPERIMENTAL=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=64 diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig index b523ce3fe92..c5e67a30aaf 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig @@ -30,7 +30,6 @@ CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=255 CONFIG_LCD_SH1106_OLED_132=y CONFIG_LCD_SSD1306_I2C=y -CONFIG_MAX_TASKS=8 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig index 12bd849a2a9..566f5fbee08 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig @@ -33,7 +33,6 @@ CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 CONFIG_LPWAN_SX127X_RFFREQ_DEFAULT=930000000 CONFIG_LPWAN_SX127X_RXSUPPORT=y CONFIG_LPWAN_SX127X_TXSUPPORT=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs index 4b47ffde49d..e061cdbd8e5 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig index 4668628411b..73887db0e79 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_BUILTIN=y CONFIG_DEFAULT_SMALL=y CONFIG_DISABLE_MQUEUE=y CONFIG_FS_PROCFS=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs index 8cb560e7f3f..75e8968195b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c index 7e78ccecd10..55ade16a619 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig index a9b2741190a..bc0add92054 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_SMALL=y CONFIG_DISABLE_MQUEUE=y CONFIG_FS_PROCFS=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig index 2107ce7c9b0..992d2e9f1c5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig @@ -32,7 +32,6 @@ CONFIG_LPWAN_SX127X_FSKOOK=y CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 CONFIG_LPWAN_SX127X_RXSUPPORT=y CONFIG_LPWAN_SX127X_TXSUPPORT=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs index b145b6bbe89..fad356d8229 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c index 488c9894af0..369a75fd3d1 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig index 59bc2488e47..ea3e44292de 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig @@ -39,7 +39,6 @@ CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=64 diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs index 00ea6daee21..a6ae9e9cb31 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs @@ -69,8 +69,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig index ed9f4b4c130..618dcaebaeb 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y CONFIG_EXAMPLES_HELLO=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=64 diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs index 3b4f10912ef..176d2e5ff61 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig index 3a22d959e2c..2476cb3f11f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXPERIMENTAL=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=64 diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig index cb5ede51e81..e8dbee6a931 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig @@ -33,7 +33,6 @@ CONFIG_LPWAN_SX127X_FSKOOK=y CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 CONFIG_LPWAN_SX127X_RXSUPPORT=y CONFIG_LPWAN_SX127X_TXSUPPORT=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs index 328e3ce21b4..54d156c960b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig index 0f64b0ea948..34886071cd6 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=2796 CONFIG_DEFAULT_SMALL=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_DISABLE_CD=y diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs index 91a246064a0..b852907637a 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig index c9afd8d97cf..c9308943eea 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=2796 CONFIG_DEFAULT_SMALL=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_DISABLE_CD=y diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs index 85a07c543a9..00c791235dd 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/nucleo-144/Kconfig b/boards/arm/stm32f7/nucleo-144/Kconfig index e0d39ab4796..81288711f6e 100644 --- a/boards/arm/stm32f7/nucleo-144/Kconfig +++ b/boards/arm/stm32f7/nucleo-144/Kconfig @@ -154,16 +154,16 @@ choice Sets SPI 1 clock mode config NUCLEO_SPI1_TEST_MODE0 - bool "CPOL=0 CHPHA=0" + bool "CPOL=0 CPHA=0" config NUCLEO_SPI1_TEST_MODE1 - bool "CPOL=0 CHPHA=1" + bool "CPOL=0 CPHA=1" config NUCLEO_SPI1_TEST_MODE2 - bool "CPOL=1 CHPHA=0" + bool "CPOL=1 CPHA=0" config NUCLEO_SPI1_TEST_MODE3 - bool "CPOL=1 CHPHA=1" + bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 1 Clock Mode" @@ -199,16 +199,16 @@ choice Sets SPI 2 clock mode config NUCLEO_SPI2_TEST_MODE0 - bool "CPOL=0 CHPHA=0" + bool "CPOL=0 CPHA=0" config NUCLEO_SPI2_TEST_MODE1 - bool "CPOL=0 CHPHA=1" + bool "CPOL=0 CPHA=1" config NUCLEO_SPI2_TEST_MODE2 - bool "CPOL=1 CHPHA=0" + bool "CPOL=1 CPHA=0" config NUCLEO_SPI2_TEST_MODE3 - bool "CPOL=1 CHPHA=1" + bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 2 Clock Mode" @@ -244,16 +244,16 @@ choice Sets SPI 3 clock mode config NUCLEO_SPI3_TEST_MODE0 - bool "CPOL=0 CHPHA=0" + bool "CPOL=0 CPHA=0" config NUCLEO_SPI3_TEST_MODE1 - bool "CPOL=0 CHPHA=1" + bool "CPOL=0 CPHA=1" config NUCLEO_SPI3_TEST_MODE2 - bool "CPOL=1 CHPHA=0" + bool "CPOL=1 CPHA=0" config NUCLEO_SPI3_TEST_MODE3 - bool "CPOL=1 CHPHA=1" + bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 3 Clock Mode" diff --git a/boards/arm/stm32f7/nucleo-144/README.txt b/boards/arm/stm32f7/nucleo-144/README.txt index 9447b2eb3e4..4ee4da3e5fa 100644 --- a/boards/arm/stm32f7/nucleo-144/README.txt +++ b/boards/arm/stm32f7/nucleo-144/README.txt @@ -573,6 +573,8 @@ f7xx-evalos: - Configures nsh with advanced features such as autocompletion. - Configures the on-board LEDs to work with the 'leds' example app. - Configures the 'helloxx' example app. + - Adds character device for i2c1 + - Tries to register mpu60x0 IMU to i2c1 NOTES: diff --git a/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/Make.defs index d25d7e1d7ed..da3ffbc30d7 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig index 846afa79638..e94e0832c26 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/Make.defs index f9dfa03dda1..530cbe52ab1 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/Make.defs @@ -68,8 +68,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig index bd9c3b3a6dd..027ee02f598 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig @@ -29,7 +29,6 @@ CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_LEDS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/Make.defs index b2c816a3d8e..6f1cd5e5aec 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig index 8b70a348d21..1fd432886ba 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/Make.defs index ce66c1d6287..53ac3ee8bcf 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig index 30db1505691..b44c5ce18af 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig @@ -44,7 +44,6 @@ CONFIG_IOEXPANDER=y CONFIG_IOEXPANDER_MULTIPIN=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MODULE=y CONFIG_MQ_MAXMSGSIZE=256 diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/Make.defs index 9420e7e9aa3..59f21f65fcb 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/Make.defs @@ -68,8 +68,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig index 34575a9ca76..5e08098720d 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig @@ -29,8 +29,8 @@ CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_LEDS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 +CONFIG_MPU60X0_I2C=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 @@ -49,14 +49,18 @@ CONFIG_SCHED_HPWORK=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y +CONFIG_SENSORS=y +CONFIG_SENSORS_MPU60X0=y CONFIG_SPI=y CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 +CONFIG_STM32F7_I2C1=y CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y CONFIG_STM32F7_USART_BREAKS=y +CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/Make.defs index bbb93e1b36c..9581bb20b16 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig index c024f2e8170..3edec3b0792 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig @@ -27,7 +27,6 @@ CONFIG_FS_TMPFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_LIB_HOSTNAME="stntest" -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/Make.defs index 345822edc6a..4449b6f0d7b 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig index 6948d4e0bcb..9cee444890f 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_appinitialize.c b/boards/arm/stm32f7/nucleo-144/src/stm32_appinitialize.c index b851b3dade6..8177e5b548b 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_appinitialize.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_appinitialize.c @@ -48,7 +48,13 @@ #include "nucleo-144.h" #include +#include +#include #include +#include + +#include "stm32_i2c.h" + #ifdef CONFIG_STM32_ROMFS #include "stm32_romfs.h" #endif @@ -97,6 +103,13 @@ int stm32f7_can_setup(void); int board_app_initialize(uintptr_t arg) { int ret; +#ifdef CONFIG_I2C + int i2c_bus; + FAR struct i2c_master_s *i2c; +#ifdef CONFIG_MPU60X0_I2C + FAR struct mpu_config_s *mpu_config; +#endif +#endif #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -220,6 +233,40 @@ int board_app_initialize(uintptr_t arg) } #endif +#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) + i2c_bus = 1; + i2c = stm32_i2cbus_initialize(i2c_bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", i2c_bus); + } + else + { +#if defined(CONFIG_SYSTEM_I2CTOOL) + ret = i2c_register(i2c, i2c_bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + i2c_bus, ret); + } +#endif + +#ifdef CONFIG_MPU60X0_I2C + mpu_config = kmm_zalloc(sizeof(struct mpu_config_s)); + if (mpu_config == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to allocate mpu60x0 driver\n"); + } + else + { + mpu_config->i2c = i2c; + mpu_config->addr = 0x68; + mpu60x0_register("/dev/imu0", mpu_config); + } +#endif + } +#endif + UNUSED(ret); return OK; } diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c index b3a16005e1c..a7d9d56c806 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/arm/stm32f7/stm32f746-ws/scripts/Make.defs b/boards/arm/stm32f7/stm32f746-ws/scripts/Make.defs index 0713bdc1213..f8297ab0764 100644 --- a/boards/arm/stm32f7/stm32f746-ws/scripts/Make.defs +++ b/boards/arm/stm32f7/stm32f746-ws/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig index 88d74d63765..36f2ed2cc3a 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig @@ -44,7 +44,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MM_REGIONS=3 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig index 24685710186..ddb403ab559 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig @@ -34,7 +34,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig index 31b198e07d4..e4d1c9ea9c2 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig @@ -42,7 +42,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LV_DPI=72 CONFIG_LV_HOR_RES=480 CONFIG_LV_VER_RES=272 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=256 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig index 917a14fd6a2..68dcd69e274 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig @@ -28,7 +28,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HOSTNAME="stntest" -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y @@ -44,7 +43,6 @@ CONFIG_NET_ETH_PKTSIZE=1500 CONFIG_NET_ICMP=y CONFIG_NET_IGMP=y CONFIG_NET_ROUTE=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig index 35655d4c616..8fb4e9dfe20 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig @@ -28,7 +28,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig index 1ad6be5c1c6..dba5fa2670d 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig @@ -42,7 +42,6 @@ CONFIG_EXAMPLES_NX_BPP=16 CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=256 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig index f31a9daa2e4..30fd1238d17 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig @@ -34,7 +34,6 @@ CONFIG_EXAMPLES_NXTERM=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=256 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/kernel/Makefile b/boards/arm/stm32f7/stm32f746g-disco/kernel/Makefile index 5eb94e7a6c8..22b31293a9f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/kernel/Makefile +++ b/boards/arm/stm32f7/stm32f746g-disco/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32f7/stm32f746g-disco/kernel/stm32_userspace.c b/boards/arm/stm32f7/stm32f746g-disco/kernel/stm32_userspace.c index 6061bb2b3f2..0ee9fa14958 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/kernel/stm32_userspace.c +++ b/boards/arm/stm32f7/stm32f746g-disco/kernel/stm32_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/scripts/Make.defs b/boards/arm/stm32f7/stm32f746g-disco/scripts/Make.defs index f1c39ad1435..e2c47c6fa9c 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/scripts/Make.defs +++ b/boards/arm/stm32f7/stm32f746g-disco/scripts/Make.defs @@ -62,8 +62,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c index 51b40f3628b..ef22bf2a830 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig index dde49ba1d5d..2bd7b12cc65 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig @@ -28,7 +28,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIB_HOSTNAME="stntest" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SDIO=y CONFIG_MM_REGIONS=3 @@ -40,7 +39,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ETH_PKTSIZE=1500 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig index 59aaf52b176..5b728fb21db 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/kernel/Makefile b/boards/arm/stm32f7/stm32f769i-disco/kernel/Makefile index e9cf736612c..acf53454f96 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/kernel/Makefile +++ b/boards/arm/stm32f7/stm32f769i-disco/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32f7/stm32f769i-disco/kernel/stm32_userspace.c b/boards/arm/stm32f7/stm32f769i-disco/kernel/stm32_userspace.c index 4a66cd7dd34..f85466e5b5f 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/kernel/stm32_userspace.c +++ b/boards/arm/stm32f7/stm32f769i-disco/kernel/stm32_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/scripts/Make.defs b/boards/arm/stm32f7/stm32f769i-disco/scripts/Make.defs index d5e4dab3d85..637b949dcb6 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/scripts/Make.defs +++ b/boards/arm/stm32f7/stm32f769i-disco/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig index 2d9fb756d66..3bd0b062df9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig @@ -21,6 +21,7 @@ CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_DTCM=y CONFIG_ARMV7M_ICACHE=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y @@ -33,7 +34,6 @@ CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig index dab850096b6..55ff795368e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig index 15e20f6058d..d13df8a4e4f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig index f15b84985fa..ab89b178aa9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig @@ -38,7 +38,6 @@ CONFIG_LCD=y CONFIG_LCD_MAXCONTRAST=255 CONFIG_LCD_SH1106_OLED_132=y CONFIG_LCD_SSD1306_I2C=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_MQ_MAXMSGSIZE=128 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig index 406b5485a3e..e7fa2bd6103 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig @@ -28,7 +28,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig index 05c61255fb7..ac686c2246b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig @@ -26,7 +26,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/kernel/Makefile b/boards/arm/stm32h7/nucleo-h743zi/kernel/Makefile index b85631e8e63..7da93a8df4d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/kernel/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32h7/nucleo-h743zi/kernel/stm32_userspace.c b/boards/arm/stm32h7/nucleo-h743zi/kernel/stm32_userspace.c index d696786e400..54fb39e0510 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/kernel/stm32_userspace.c +++ b/boards/arm/stm32h7/nucleo-h743zi/kernel/stm32_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/scripts/Make.defs b/boards/arm/stm32h7/nucleo-h743zi/scripts/Make.defs index 0593c6b13ca..daa1c36bb09 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/scripts/Make.defs +++ b/boards/arm/stm32h7/nucleo-h743zi/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/stm32h7/nucleo-h743zi2/README.txt b/boards/arm/stm32h7/nucleo-h743zi2/README.txt index b1f62aeb90b..1336feb78f5 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/README.txt +++ b/boards/arm/stm32h7/nucleo-h743zi2/README.txt @@ -78,7 +78,7 @@ Configurations jumbo: - This configuration enables many Apache Nuttx features. This is + This configuration enables many Apache NuttX features. This is mostly to help provide additional code coverage in CI, but also allows for a users to see a wide range of features that are supported by the OS. diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig index c32feb62eb7..521043d6b68 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig @@ -47,7 +47,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_MTD=y CONFIG_NET=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig new file mode 100644 index 00000000000..652e6945e33 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h743zi2" +CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743ZI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8742A=y +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=4 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_ETHMAC=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_PHYSR=31 +CONFIG_STM32H7_PHYSR_100FD=0x0018 +CONFIG_STM32H7_PHYSR_100HD=0x0008 +CONFIG_STM32H7_PHYSR_10FD=0x0014 +CONFIG_STM32H7_PHYSR_10HD=0x0004 +CONFIG_STM32H7_PHYSR_ALTCONFIG=y +CONFIG_STM32H7_PHYSR_ALTMODE=0x001c +CONFIG_STM32H7_USART3=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST=y +CONFIG_USBHOST_MSC=y +CONFIG_USBHOST_MSC_NOTIFIER=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig index 79914b08fcc..6bb5a1c9225 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32h7/nucleo-h743zi2/scripts/Make.defs b/boards/arm/stm32h7/nucleo-h743zi2/scripts/Make.defs index 1447dae7994..6de57694348 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/scripts/Make.defs +++ b/boards/arm/stm32h7/nucleo-h743zi2/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h index 55c22ca13d1..28ea554d8f3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h @@ -78,13 +78,13 @@ #define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN0) #define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ - GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7) + GPIO_OUTPUT_CLEAR | GPIO_PORTE | GPIO_PIN1) #define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN14) -#define GPIO_LED_GREEN GPIO_LD1 -#define GPIO_LED_BLUE GPIO_LD2 -#define GPIO_LED_RED GPIO_LD3 +#define GPIO_LED_GREEN GPIO_LD1 +#define GPIO_LED_ORANGE GPIO_LD2 +#define GPIO_LED_RED GPIO_LD3 #define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_autoleds.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_autoleds.c index 4105716060e..db26e84ef56 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_autoleds.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_autoleds.c @@ -50,7 +50,7 @@ static const uint32_t g_ledmap[BOARD_NLEDS] = { GPIO_LED_GREEN, - GPIO_LED_BLUE, + GPIO_LED_ORANGE, GPIO_LED_RED, }; diff --git a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig index 3ba35b44594..db0bc24d97b 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32h7/stm32h747i-disco/kernel/Makefile b/boards/arm/stm32h7/stm32h747i-disco/kernel/Makefile index 8cb2c383c40..8d011961fce 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/kernel/Makefile +++ b/boards/arm/stm32h7/stm32h747i-disco/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32h7/stm32h747i-disco/kernel/stm32_userspace.c b/boards/arm/stm32h7/stm32h747i-disco/kernel/stm32_userspace.c index 84079d23ed0..4dfafe8a421 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/kernel/stm32_userspace.c +++ b/boards/arm/stm32h7/stm32h747i-disco/kernel/stm32_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/scripts/Make.defs b/boards/arm/stm32h7/stm32h747i-disco/scripts/Make.defs index 2791e997f79..6121c6ea86f 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/scripts/Make.defs +++ b/boards/arm/stm32h7/stm32h747i-disco/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig index 6564e642e9e..dc33986e6be 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MTD_SMART_SECTOR_SIZE=512 CONFIG_MX25RXX_SECTOR512=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig index 2ff1211ff52..b477cb7641b 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig @@ -46,7 +46,6 @@ CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIBM=y CONFIG_LIB_HOSTNAME="B-L475E-IOT01A" -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig index 423eabba917..68521c80c47 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig @@ -35,7 +35,6 @@ CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIBM=y CONFIG_LIB_HOSTNAME="B-L475E-IOT01A" -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig index 160122f4a39..217a3c76c29 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig @@ -47,7 +47,6 @@ CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 CONFIG_LIBM=y CONFIG_LIB_HOSTNAME="B-L475E-IOT01A" -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index 2d26e27ac01..16e90adf880 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -284,7 +284,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ @@ -387,7 +386,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ @@ -467,7 +465,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/scripts/Make.defs b/boards/arm/stm32l4/b-l475e-iot01a/scripts/Make.defs index e746d71b9d7..84455abc747 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/scripts/Make.defs +++ b/boards/arm/stm32l4/b-l475e-iot01a/scripts/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c index 1a1de91186d..bea6bd1a328 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c @@ -59,6 +59,7 @@ int stm32l4_timer_driver_setup(void) if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM1 at /dev/timer0: %d\n", + ret); } #endif @@ -121,6 +122,7 @@ int stm32l4_timer_driver_setup(void) if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM8 at /dev/timer7: %d\n", + ret); } #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig index 2ba40e74033..b12c62e8c31 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig @@ -27,7 +27,6 @@ CONFIG_EXAMPLES_RANDOM=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig index c9e677d5c7f..fb55a2b3fdc 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NUCLEOL432KC_SPWM=y CONFIG_NUCLEOL432KC_SPWM_PWM_FREQ=200000 diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h index abc3b803e72..61baeee94b4 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h @@ -278,7 +278,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ @@ -376,7 +375,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ @@ -471,7 +469,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/scripts/Make.defs b/boards/arm/stm32l4/nucleo-l432kc/scripts/Make.defs index 6f267488202..e0d87d5584e 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/scripts/Make.defs +++ b/boards/arm/stm32l4/nucleo-l432kc/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_appinit.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_appinit.c index 7824d500455..c8e9ec3e48e 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_appinit.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_appinit.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index 1c9f2a9ef77..b7115db8d46 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c index 939df213a9f..7499dfba104 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c index 40f8c34f9e7..8652db1057d 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig index bd13279628c..962ca2f5a35 100644 --- a/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig @@ -35,7 +35,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_I2C_RESET=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h index 7babdcfaf7b..66a373ca19a 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h @@ -274,7 +274,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ @@ -373,7 +372,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ @@ -457,7 +455,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ diff --git a/boards/arm/stm32l4/nucleo-l452re/scripts/Make.defs b/boards/arm/stm32l4/nucleo-l452re/scripts/Make.defs index 206e1bbdd7c..7da0792d894 100644 --- a/boards/arm/stm32l4/nucleo-l452re/scripts/Make.defs +++ b/boards/arm/stm32l4/nucleo-l452re/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c index 40f4dbe7314..5aad15ec623 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig index 04c222dcb61..5734ae6789a 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig @@ -27,7 +27,6 @@ CONFIG_EXAMPLES_RANDOM=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig b/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig index 2168b3373cd..9241a5f24df 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig +++ b/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig @@ -31,7 +31,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_FRAMEBUFFER=y CONFIG_LCD_PCD8544=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h index 4f5ec43f465..0525d598bb0 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h @@ -279,7 +279,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ @@ -378,7 +377,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ @@ -461,7 +459,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/scripts/Make.defs b/boards/arm/stm32l4/nucleo-l476rg/scripts/Make.defs index e196a82774b..f181c7b7d9d 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/scripts/Make.defs +++ b/boards/arm/stm32l4/nucleo-l476rg/scripts/Make.defs @@ -60,8 +60,8 @@ ifeq ($(CONFIG_LIBCXX),y) endif endif -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c index af6dafec821..7f222d4ab09 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c index 7478af2d806..968fc280d36 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c index 03d89550b03..5761d57d4f2 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig index e5e05702c8c..26a52ca4045 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig @@ -36,7 +36,6 @@ CONFIG_I2C=y CONFIG_I2CTOOL_MAXBUS=4 CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2C_RESET=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 675efe017a9..271c7693f99 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -148,7 +148,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ @@ -259,7 +258,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ @@ -371,7 +369,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/scripts/Make.defs b/boards/arm/stm32l4/nucleo-l496zg/scripts/Make.defs index a4819506cbd..ec5751b7b43 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/scripts/Make.defs +++ b/boards/arm/stm32l4/nucleo-l496zg/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig index a5cdffcf561..bdd91bec6a7 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_TMPFS=y CONFIG_HAVE_CXX=y CONFIG_INTELHEX_BINARY=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h index 586168d0a9e..ef0beb7c88e 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h @@ -146,7 +146,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ @@ -235,7 +234,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ diff --git a/boards/arm/stm32l4/stm32l476-mdk/scripts/Make.defs b/boards/arm/stm32l4/stm32l476-mdk/scripts/Make.defs index b985a297971..83d78bd35c1 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/scripts/Make.defs +++ b/boards/arm/stm32l4/stm32l476-mdk/scripts/Make.defs @@ -66,8 +66,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/Make.defs b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/Make.defs index a3a3fa42022..db5e4fa6a1f 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/Make.defs +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) @@ -65,6 +65,6 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) LDFLAGS += -g endif -#LDFLAGS += -Map=$(TOPDIR)/nuttx.map +#LDFLAGS += -Wl,-Map=$(TOPDIR)/nuttx.map #CFLAGS += -Wa,-adhln #CXXFLAGS += -Wa,-adhln diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig index 37d88e2ec8e..ea933aacddf 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig @@ -33,7 +33,6 @@ CONFIG_FS_TMPFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MTD=y CONFIG_MTD_N25QXXX=y CONFIG_MTD_PARTITION=y @@ -69,7 +68,7 @@ CONFIG_STM32L4_RTC=y CONFIG_STM32L4_SAI1PLL=y CONFIG_STM32L4_USART2=y CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig index 61a8b415b6a..015f0860eb0 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig @@ -35,7 +35,6 @@ CONFIG_FS_TMPFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MTD=y CONFIG_MTD_N25QXXX=y CONFIG_MTD_PARTITION=y diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h index a4aee34f5a5..60e2d6071ee 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h @@ -155,7 +155,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ @@ -248,7 +247,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ @@ -328,7 +326,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/kernel/Makefile b/boards/arm/stm32l4/stm32l476vg-disco/kernel/Makefile index 2623a08194a..9bd0e230766 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/kernel/Makefile +++ b/boards/arm/stm32l4/stm32l476vg-disco/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32l4/stm32l476vg-disco/kernel/stm32l4_userspace.c b/boards/arm/stm32l4/stm32l476vg-disco/kernel/stm32l4_userspace.c index f274947f035..548d619a623 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/kernel/stm32l4_userspace.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/kernel/stm32l4_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/scripts/Make.defs b/boards/arm/stm32l4/stm32l476vg-disco/scripts/Make.defs index 7e47218b2cf..f50da8bdf34 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/scripts/Make.defs +++ b/boards/arm/stm32l4/stm32l476vg-disco/scripts/Make.defs @@ -66,8 +66,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) @@ -77,6 +77,6 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) LDFLAGS += -g endif -LDFLAGS += -Map=$(TOPDIR)/nuttx.map +LDFLAGS += -Wl,-Map=$(TOPDIR)/nuttx.map #CFLAGS += -Wa,-adhln #CXXFLAGS += -Wa,-adhln diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_appinit.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_appinit.c index 2c1d0c63bee..e6b14ba9a19 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_appinit.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_appinit.c @@ -26,7 +26,6 @@ #include #include -#include #include #include #include diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c index 91161e397d1..06dd46c41d8 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/Make.defs b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/Make.defs index a949456700e..30110850908 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/Make.defs +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) @@ -65,6 +65,6 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) LDFLAGS += -g endif -#LDFLAGS += -Map=$(TOPDIR)/nuttx.map +#LDFLAGS += -Wl,-Map=$(TOPDIR)/nuttx.map #CFLAGS += -Wa,-adhln #CXXFLAGS += -Wa,-adhln diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig index dfea95c178f..b2a72d658de 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig @@ -36,7 +36,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_I2C_DRIVER=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MTD=y CONFIG_MTD_PARTITION=y @@ -73,7 +72,7 @@ CONFIG_STM32L4_SRAM2_HEAP=y CONFIG_STM32L4_UART4=y CONFIG_STM32L4_USART2=y CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=2000000 CONFIG_UART4_RXBUFSIZE=512 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig index d3713217bb5..957305c25f9 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig @@ -37,7 +37,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_I2C_DRIVER=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MTD=y CONFIG_MTD_PARTITION=y diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index 41b308dcb89..6168f3d3d33 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -165,7 +165,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/1 (120 MHz) */ @@ -276,7 +275,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ @@ -374,7 +372,6 @@ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY -#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/kernel/Makefile b/boards/arm/stm32l4/stm32l4r9ai-disco/kernel/Makefile index 78bf862f4e6..53828d0792c 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/kernel/Makefile +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) -Wl,--end-group $(USER_LIBGCC) $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/kernel/stm32l4_userspace.c b/boards/arm/stm32l4/stm32l4r9ai-disco/kernel/stm32l4_userspace.c index 802c1a37051..ae474c689f4 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/kernel/stm32l4_userspace.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/kernel/stm32l4_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/scripts/Make.defs b/boards/arm/stm32l4/stm32l4r9ai-disco/scripts/Make.defs index aa788d94333..3f4bf432cec 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/scripts/Make.defs +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/scripts/Make.defs @@ -66,8 +66,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) @@ -77,6 +77,6 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) LDFLAGS += -g endif -LDFLAGS += -Map=$(TOPDIR)/nuttx.map +LDFLAGS += -Wl,-Map=$(TOPDIR)/nuttx.map #CFLAGS += -Wa,-adhln #CXXFLAGS += -Wa,-adhln diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_appinit.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_appinit.c index 9dcabb6c014..9455a1c230d 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_appinit.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_appinit.c @@ -26,7 +26,6 @@ #include #include -#include #include #include #include diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c index 70e3754e8eb..0d8c4422b1a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig b/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig index f5db81706bd..933ecbdefea 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig +++ b/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig @@ -37,7 +37,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 84a11ab26e4..31e0a23e7c3 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -120,7 +120,6 @@ #define STM32L5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY -#define STM32L5_BOARD_HCLK STM32L5_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* Configure the APB1 prescaler */ diff --git a/boards/arm/stm32l5/nucleo-l552ze/scripts/Make.defs b/boards/arm/stm32l5/nucleo-l552ze/scripts/Make.defs index d7317b6b042..e157cdcf325 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/scripts/Make.defs +++ b/boards/arm/stm32l5/nucleo-l552ze/scripts/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig b/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig index 8d41541716f..2b12b7cf6f4 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig +++ b/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index a6c30036696..20e3c369bbf 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -72,7 +72,6 @@ #define STM32L5_SYSCLK_FREQUENCY 110000000ul #define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY -#define STM32L5_BOARD_HCLK STM32L5_HCLK_FREQUENCY #define STM32L5_PCLK1_FREQUENCY STM32L5_HCLK_FREQUENCY #define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) diff --git a/boards/arm/stm32l5/stm32l562e-dk/scripts/Make.defs b/boards/arm/stm32l5/stm32l562e-dk/scripts/Make.defs index a3afb351417..4adf73c6aa8 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/scripts/Make.defs +++ b/boards/arm/stm32l5/stm32l562e-dk/scripts/Make.defs @@ -54,8 +54,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/str71x/olimex-strp711/configs/nettest/defconfig b/boards/arm/str71x/olimex-strp711/configs/nettest/defconfig index 7e0f57442ec..e4a699d9f5a 100644 --- a/boards/arm/str71x/olimex-strp711/configs/nettest/defconfig +++ b/boards/arm/str71x/olimex-strp711/configs/nettest/defconfig @@ -22,7 +22,6 @@ CONFIG_ENC28J60=y CONFIG_EXAMPLES_NETTEST=y CONFIG_EXAMPLES_NETTEST_NOMAC=y CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/arm/str71x/olimex-strp711/configs/nsh/defconfig b/boards/arm/str71x/olimex-strp711/configs/nsh/defconfig index 6789aa53d30..07829d1c5f7 100644 --- a/boards/arm/str71x/olimex-strp711/configs/nsh/defconfig +++ b/boards/arm/str71x/olimex-strp711/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=1431 CONFIG_FS_FAT=y CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/str71x/olimex-strp711/scripts/Make.defs b/boards/arm/str71x/olimex-strp711/scripts/Make.defs index 4bec904ef8c..d4eb365dcea 100644 --- a/boards/arm/str71x/olimex-strp711/scripts/Make.defs +++ b/boards/arm/str71x/olimex-strp711/scripts/Make.defs @@ -74,10 +74,10 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld \ - -no-check-sections + -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/tiva/dk-tm4c129x/configs/ipv6/defconfig b/boards/arm/tiva/dk-tm4c129x/configs/ipv6/defconfig index 98cfb379f21..d9b7cfcc5c2 100644 --- a/boards/arm/tiva/dk-tm4c129x/configs/ipv6/defconfig +++ b/boards/arm/tiva/dk-tm4c129x/configs/ipv6/defconfig @@ -27,7 +27,6 @@ CONFIG_I2CTOOL_MAXBUS=6 CONFIG_I2CTOOL_MINBUS=6 CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETINIT_IPv6NETMASK_8=0xff80 CONFIG_NETINIT_MONITOR=y diff --git a/boards/arm/tiva/dk-tm4c129x/configs/nsh/defconfig b/boards/arm/tiva/dk-tm4c129x/configs/nsh/defconfig index a5e61d64125..387b8b1ccbb 100644 --- a/boards/arm/tiva/dk-tm4c129x/configs/nsh/defconfig +++ b/boards/arm/tiva/dk-tm4c129x/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_I2CTOOL_MAXBUS=6 CONFIG_I2CTOOL_MINBUS=6 CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_NOADDR=y diff --git a/boards/arm/tiva/dk-tm4c129x/scripts/Make.defs b/boards/arm/tiva/dk-tm4c129x/scripts/Make.defs index e8d64f0a212..f837ea27f3d 100644 --- a/boards/arm/tiva/dk-tm4c129x/scripts/Make.defs +++ b/boards/arm/tiva/dk-tm4c129x/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/tiva/eagle100/configs/httpd/defconfig b/boards/arm/tiva/eagle100/configs/httpd/defconfig index 0a46a7cff8f..bfff3a38622 100644 --- a/boards/arm/tiva/eagle100/configs/httpd/defconfig +++ b/boards/arm/tiva/eagle100/configs/httpd/defconfig @@ -20,7 +20,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_EXAMPLES_WEBSERVER=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NETUTILS_WEBSERVER=y diff --git a/boards/arm/tiva/eagle100/configs/nettest/defconfig b/boards/arm/tiva/eagle100/configs/nettest/defconfig index 8475a0d1508..3b6dd9c6b12 100644 --- a/boards/arm/tiva/eagle100/configs/nettest/defconfig +++ b/boards/arm/tiva/eagle100/configs/nettest/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_NETTEST=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NET_ICMP=y diff --git a/boards/arm/tiva/eagle100/configs/nsh/defconfig b/boards/arm/tiva/eagle100/configs/nsh/defconfig index bd8783a38df..0e20a2adae9 100644 --- a/boards/arm/tiva/eagle100/configs/nsh/defconfig +++ b/boards/arm/tiva/eagle100/configs/nsh/defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_NET=y diff --git a/boards/arm/tiva/eagle100/configs/nxflat/defconfig b/boards/arm/tiva/eagle100/configs/nxflat/defconfig index 469b748b7d4..c1680d81fe3 100644 --- a/boards/arm/tiva/eagle100/configs/nxflat/defconfig +++ b/boards/arm/tiva/eagle100/configs/nxflat/defconfig @@ -13,13 +13,14 @@ CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_CONSOLE_SYSLOG=y CONFIG_DISABLE_ENVIRON=y CONFIG_EXAMPLES_NXFLAT=y CONFIG_FS_ROMFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 +CONFIG_LIBM=y +CONFIG_LIB_BOARDCTL=y CONFIG_NXFLAT=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65536 diff --git a/boards/arm/tiva/eagle100/configs/thttpd/defconfig b/boards/arm/tiva/eagle100/configs/thttpd/defconfig index a3965c26b23..0de428ba959 100644 --- a/boards/arm/tiva/eagle100/configs/thttpd/defconfig +++ b/boards/arm/tiva/eagle100/configs/thttpd/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_THTTPD=y CONFIG_FS_ROMFS=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NETUTILS_THTTPD=y diff --git a/boards/arm/tiva/eagle100/scripts/Make.defs b/boards/arm/tiva/eagle100/scripts/Make.defs index 2125ba5c5d5..893c5e51fdb 100644 --- a/boards/arm/tiva/eagle100/scripts/Make.defs +++ b/boards/arm/tiva/eagle100/scripts/Make.defs @@ -52,8 +52,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ MKNXFLAT = mknxflat LDNXFLAT = ldnxflat -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT),y) diff --git a/boards/arm/tiva/eagle100/src/lm_appinit.c b/boards/arm/tiva/eagle100/src/lm_appinit.c index 8a028bd9323..a28766c6d64 100644 --- a/boards/arm/tiva/eagle100/src/lm_appinit.c +++ b/boards/arm/tiva/eagle100/src/lm_appinit.c @@ -108,7 +108,9 @@ int board_app_initialize(uintptr_t arg) { FAR struct spi_dev_s *spi; +#if defined (CONFIG_MMCSD) && defined (CONFIG_MMCSD_SPI) int ret; +#endif /* Get the SPI port */ @@ -126,6 +128,7 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_INFO, "Successfully initialized SPI port %d\n", CONFIG_NSH_MMCSDSPIPORTNO); +#if defined (CONFIG_MMCSD) && defined (CONFIG_MMCSD_SPI) /* Bind the SPI port to the slot */ syslog(LOG_INFO, "Binding SPI port %d to MMC/SD slot %d\n", @@ -143,5 +146,7 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_INFO, "Successfully bound SPI port %d to MMC/SD slot %d\n", CONFIG_NSH_MMCSDSPIPORTNO, CONFIG_NSH_MMCSDSLOTNO); +#endif + return OK; } diff --git a/boards/arm/tiva/ekk-lm3s9b96/configs/nsh/defconfig b/boards/arm/tiva/ekk-lm3s9b96/configs/nsh/defconfig index e9f00df15c9..f8372afd2f5 100644 --- a/boards/arm/tiva/ekk-lm3s9b96/configs/nsh/defconfig +++ b/boards/arm/tiva/ekk-lm3s9b96/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_NSLOTS=0 CONFIG_NET=y diff --git a/boards/arm/tiva/ekk-lm3s9b96/scripts/Make.defs b/boards/arm/tiva/ekk-lm3s9b96/scripts/Make.defs index 97470b3b787..d060cf72296 100644 --- a/boards/arm/tiva/ekk-lm3s9b96/scripts/Make.defs +++ b/boards/arm/tiva/ekk-lm3s9b96/scripts/Make.defs @@ -65,8 +65,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/tiva/launchxl-cc1310/configs/nsh/defconfig b/boards/arm/tiva/launchxl-cc1310/configs/nsh/defconfig index c2c092e9f51..64ee7e8ee06 100644 --- a/boards/arm/tiva/launchxl-cc1310/configs/nsh/defconfig +++ b/boards/arm/tiva/launchxl-cc1310/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_BUILTIN=y CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/tiva/launchxl-cc1310/scripts/Make.defs b/boards/arm/tiva/launchxl-cc1310/scripts/Make.defs index 875a4de1d9b..89f590bb3ed 100644 --- a/boards/arm/tiva/launchxl-cc1310/scripts/Make.defs +++ b/boards/arm/tiva/launchxl-cc1310/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/tiva/launchxl-cc1312r1/configs/nsh/defconfig b/boards/arm/tiva/launchxl-cc1312r1/configs/nsh/defconfig index db53e95f525..5d687112c10 100644 --- a/boards/arm/tiva/launchxl-cc1312r1/configs/nsh/defconfig +++ b/boards/arm/tiva/launchxl-cc1312r1/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_BUILTIN=y CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/tiva/launchxl-cc1312r1/scripts/Make.defs b/boards/arm/tiva/launchxl-cc1312r1/scripts/Make.defs index 4f458036f4b..6fef940f9b6 100644 --- a/boards/arm/tiva/launchxl-cc1312r1/scripts/Make.defs +++ b/boards/arm/tiva/launchxl-cc1312r1/scripts/Make.defs @@ -55,8 +55,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/tiva/lm3s6432-s2e/configs/nsh/defconfig b/boards/arm/tiva/lm3s6432-s2e/configs/nsh/defconfig index e7836ac4345..8a5f2046356 100644 --- a/boards/arm/tiva/lm3s6432-s2e/configs/nsh/defconfig +++ b/boards/arm/tiva/lm3s6432-s2e/configs/nsh/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=4531 -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 diff --git a/boards/arm/tiva/lm3s6432-s2e/scripts/Make.defs b/boards/arm/tiva/lm3s6432-s2e/scripts/Make.defs index c9df8a5fdc2..0b32bbe683d 100644 --- a/boards/arm/tiva/lm3s6432-s2e/scripts/Make.defs +++ b/boards/arm/tiva/lm3s6432-s2e/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/tiva/lm3s6965-ek/configs/discover/defconfig b/boards/arm/tiva/lm3s6965-ek/configs/discover/defconfig index 1f402b9d1c4..636a7dd5b22 100644 --- a/boards/arm/tiva/lm3s6965-ek/configs/discover/defconfig +++ b/boards/arm/tiva/lm3s6965-ek/configs/discover/defconfig @@ -21,7 +21,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_NET=y diff --git a/boards/arm/tiva/lm3s6965-ek/configs/nsh/defconfig b/boards/arm/tiva/lm3s6965-ek/configs/nsh/defconfig index e647bce7048..d59563010c7 100644 --- a/boards/arm/tiva/lm3s6965-ek/configs/nsh/defconfig +++ b/boards/arm/tiva/lm3s6965-ek/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_NET=y diff --git a/boards/arm/tiva/lm3s6965-ek/configs/nx/defconfig b/boards/arm/tiva/lm3s6965-ek/configs/nx/defconfig index ed754c6d1cb..ac598e6362b 100644 --- a/boards/arm/tiva/lm3s6965-ek/configs/nx/defconfig +++ b/boards/arm/tiva/lm3s6965-ek/configs/nx/defconfig @@ -31,7 +31,6 @@ CONFIG_EXAMPLES_NX_FONTCOLOR=0x00 CONFIG_EXAMPLES_NX_TBCOLOR=0x08 CONFIG_LCD=y CONFIG_LCD_P14201=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y diff --git a/boards/arm/tiva/lm3s6965-ek/configs/qemu-flat/defconfig b/boards/arm/tiva/lm3s6965-ek/configs/qemu-flat/defconfig index 5ad9f94af9a..2386efe1a1c 100644 --- a/boards/arm/tiva/lm3s6965-ek/configs/qemu-flat/defconfig +++ b/boards/arm/tiva/lm3s6965-ek/configs/qemu-flat/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_SEMIHOSTING_HOSTFS=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_BUILTIN=y CONFIG_CLOCK_MONOTONIC=y @@ -42,7 +43,6 @@ CONFIG_FS_TMPFS=y CONFIG_HOST_MACOS=y CONFIG_LIBC_DLFCN=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_NET=y diff --git a/boards/arm/tiva/lm3s6965-ek/configs/qemu-nxflat/defconfig b/boards/arm/tiva/lm3s6965-ek/configs/qemu-nxflat/defconfig new file mode 100644 index 00000000000..acfcacebb98 --- /dev/null +++ b/boards/arm/tiva/lm3s6965-ek/configs/qemu-nxflat/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_NSH_DISABLE_DATE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="lm3s6965-ek" +CONFIG_ARCH_BOARD_LM3S6965EK=y +CONFIG_ARCH_CHIP="tiva" +CONFIG_ARCH_CHIP_LM3S6965=y +CONFIG_ARCH_CHIP_LM3S=y +CONFIG_ARCH_CHIP_LM=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=4531 +CONFIG_CLOCK_MONOTONIC=y +CONFIG_EXAMPLES_NXFLAT=y +CONFIG_FS_ROMFS=y +CONFIG_LIBM=y +CONFIG_LIB_BOARDCTL=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_NAMESIZE=64 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETDB_MAX_IPADDR=2 +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_NETCAT=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=8 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NXFLAT=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SIG_DEFAULT=y +CONFIG_SIG_PIPE=11 +CONFIG_SPI=y +CONFIG_START_DAY=8 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2010 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TIVA_ETHERNET=y +CONFIG_TIVA_GPIOA_IRQS=y +CONFIG_TIVA_GPIOB_IRQS=y +CONFIG_TIVA_GPIOC_IRQS=y +CONFIG_TIVA_GPIOD_IRQS=y +CONFIG_TIVA_GPIOE_IRQS=y +CONFIG_TIVA_GPIOF_IRQS=y +CONFIG_TIVA_GPIOG_IRQS=y +CONFIG_TIVA_SSI0=y +CONFIG_TIVA_UART0=y +CONFIG_TIVA_WITH_QEMU=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nxflat_main" diff --git a/boards/arm/tiva/lm3s6965-ek/configs/qemu-protected/defconfig b/boards/arm/tiva/lm3s6965-ek/configs/qemu-protected/defconfig index 2e3799581eb..65759f21126 100644 --- a/boards/arm/tiva/lm3s6965-ek/configs/qemu-protected/defconfig +++ b/boards/arm/tiva/lm3s6965-ek/configs/qemu-protected/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y CONFIG_ARM_SEMIHOSTING_HOSTFS=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_BUILD_PROTECTED=y CONFIG_BUILTIN=y @@ -44,7 +45,6 @@ CONFIG_FS_TMPFS=y CONFIG_HOST_MACOS=y CONFIG_LIBC_DLFCN=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MODULE=y @@ -97,7 +97,7 @@ CONFIG_SYSTEM_NETDB=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NTPC=y CONFIG_SYSTEM_PING=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=0 CONFIG_TIVA_ETHERNET=y CONFIG_TIVA_GPIOA_IRQS=y diff --git a/boards/arm/tiva/lm3s6965-ek/configs/tcpecho/defconfig b/boards/arm/tiva/lm3s6965-ek/configs/tcpecho/defconfig index 7d4ebcaafdb..698ce69b535 100644 --- a/boards/arm/tiva/lm3s6965-ek/configs/tcpecho/defconfig +++ b/boards/arm/tiva/lm3s6965-ek/configs/tcpecho/defconfig @@ -20,7 +20,6 @@ CONFIG_EXAMPLES_TCPECHO_DRIPADDR=0xc0a80201 CONFIG_EXAMPLES_TCPECHO_IPADDR=0xc0a80232 CONFIG_EXAMPLES_TCPECHO_NOMAC=y CONFIG_FS_FAT=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 diff --git a/boards/arm/tiva/lm3s6965-ek/kernel/Makefile b/boards/arm/tiva/lm3s6965-ek/kernel/Makefile index bd4707beab3..9dd99a131c9 100644 --- a/boards/arm/tiva/lm3s6965-ek/kernel/Makefile +++ b/boards/arm/tiva/lm3s6965-ek/kernel/Makefile @@ -46,7 +46,7 @@ else USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" endif -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT) -nostartfiles -nodefaultlibs USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" @@ -67,7 +67,7 @@ $(COBJS): %$(OBJEXT): %.c # Create the nuttx_user.elf file containing all of the user-mode code nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) $(USER_LIBGCC) --end-group + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) -Wl,--start-group $(USER_LDLIBS) $(USER_LIBGCC) -Wl,--end-group $(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf @echo "LD: nuttx_user.elf" diff --git a/boards/arm/tiva/lm3s6965-ek/kernel/lm_userspace.c b/boards/arm/tiva/lm3s6965-ek/kernel/lm_userspace.c index 6873dc10bdb..1e6ae7bced8 100644 --- a/boards/arm/tiva/lm3s6965-ek/kernel/lm_userspace.c +++ b/boards/arm/tiva/lm3s6965-ek/kernel/lm_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/arm/tiva/lm3s6965-ek/scripts/Make.defs b/boards/arm/tiva/lm3s6965-ek/scripts/Make.defs index d303b665a81..6476976672a 100644 --- a/boards/arm/tiva/lm3s6965-ek/scripts/Make.defs +++ b/boards/arm/tiva/lm3s6965-ek/scripts/Make.defs @@ -41,6 +41,17 @@ ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef ARCHWARNINGSXX = -Wall -Wshadow -Wundef ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 +ifeq ($(CONFIG_NXFLAT),y) + # mpic-data-is-text-relative flag first time appeared in GCC source code tree on 2016-Jul-12 + # and it was included in GCC 4.9.4 release on 2016-Aug-03. + ARCHCC_HAS_PIC_DATA_IS_TEXT_RELATIVE_FLAG = ${shell $(CC) --target-help 2>&1 | grep -c "mpic-data-is-text-relative"} + + # Turn off -mpic-data-is-text-relative flag to access bss via the GOT + # (https://cwiki.apache.org/confluence/pages/viewpage.action?pageId=139630111) + ifneq ($(ARCHCC_HAS_PIC_DATA_IS_TEXT_RELATIVE_FLAG),0) + ARCHPICFLAGS += -mno-pic-data-is-text-relative + endif +endif CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) @@ -49,8 +60,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/tiva/lm3s8962-ek/configs/nsh/defconfig b/boards/arm/tiva/lm3s8962-ek/configs/nsh/defconfig index a3c4b70e65b..a35541cfc30 100644 --- a/boards/arm/tiva/lm3s8962-ek/configs/nsh/defconfig +++ b/boards/arm/tiva/lm3s8962-ek/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_NET=y diff --git a/boards/arm/tiva/lm3s8962-ek/configs/nx/defconfig b/boards/arm/tiva/lm3s8962-ek/configs/nx/defconfig index 9ffb503128c..861f9cd5837 100644 --- a/boards/arm/tiva/lm3s8962-ek/configs/nx/defconfig +++ b/boards/arm/tiva/lm3s8962-ek/configs/nx/defconfig @@ -31,7 +31,6 @@ CONFIG_EXAMPLES_NX_TBCOLOR=8 CONFIG_HOST_WINDOWS=y CONFIG_LCD=y CONFIG_LCD_P14201=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y diff --git a/boards/arm/tiva/lm3s8962-ek/scripts/Make.defs b/boards/arm/tiva/lm3s8962-ek/scripts/Make.defs index 4b74d7ecaa7..d9dd80fac86 100644 --- a/boards/arm/tiva/lm3s8962-ek/scripts/Make.defs +++ b/boards/arm/tiva/lm3s8962-ek/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/tiva/lm4f120-launchpad/configs/nsh/defconfig b/boards/arm/tiva/lm4f120-launchpad/configs/nsh/defconfig index ac18caa8766..0e5e9b1bd21 100644 --- a/boards/arm/tiva/lm4f120-launchpad/configs/nsh/defconfig +++ b/boards/arm/tiva/lm4f120-launchpad/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_BUILTIN=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/arm/tiva/lm4f120-launchpad/scripts/Make.defs b/boards/arm/tiva/lm4f120-launchpad/scripts/Make.defs index 124ca03a0fe..e505e25a269 100644 --- a/boards/arm/tiva/lm4f120-launchpad/scripts/Make.defs +++ b/boards/arm/tiva/lm4f120-launchpad/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/tiva/tm4c123g-launchpad/configs/mcp2515/defconfig b/boards/arm/tiva/tm4c123g-launchpad/configs/mcp2515/defconfig index 46fc7679cac..28dd06d50bf 100644 --- a/boards/arm/tiva/tm4c123g-launchpad/configs/mcp2515/defconfig +++ b/boards/arm/tiva/tm4c123g-launchpad/configs/mcp2515/defconfig @@ -26,7 +26,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_EXAMPLES_CAN=y CONFIG_EXAMPLES_CAN_READ=y -CONFIG_MAX_TASKS=16 CONFIG_MCP2515_PHASESEG1=3 CONFIG_MCP2515_PROPSEG=1 CONFIG_MCP2515_SPI_SCK_FREQUENCY=4000000 diff --git a/boards/arm/tiva/tm4c123g-launchpad/configs/nsh/defconfig b/boards/arm/tiva/tm4c123g-launchpad/configs/nsh/defconfig index ea055f38d37..5c70046a6bf 100644 --- a/boards/arm/tiva/tm4c123g-launchpad/configs/nsh/defconfig +++ b/boards/arm/tiva/tm4c123g-launchpad/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=4531 CONFIG_BUILTIN=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/tiva/tm4c123g-launchpad/scripts/Make.defs b/boards/arm/tiva/tm4c123g-launchpad/scripts/Make.defs index 7148c1ab7bb..48f8b9fb232 100644 --- a/boards/arm/tiva/tm4c123g-launchpad/scripts/Make.defs +++ b/boards/arm/tiva/tm4c123g-launchpad/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/tiva/tm4c123g-launchpad/src/tm4c_mcp2515.c b/boards/arm/tiva/tm4c123g-launchpad/src/tm4c_mcp2515.c index d3fa7ead224..4737b8f2726 100644 --- a/boards/arm/tiva/tm4c123g-launchpad/src/tm4c_mcp2515.c +++ b/boards/arm/tiva/tm4c123g-launchpad/src/tm4c_mcp2515.c @@ -40,6 +40,7 @@ #include +#include #include #include diff --git a/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6/defconfig b/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6/defconfig index 53be6bd98c2..70dafb67c6a 100644 --- a/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6/defconfig +++ b/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6/defconfig @@ -26,7 +26,6 @@ CONFIG_I2CTOOL_MAXBUS=6 CONFIG_I2CTOOL_MINBUS=6 CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETINIT_IPv6NETMASK_4=0x0000 CONFIG_NETINIT_IPv6NETMASK_8=0xff80 diff --git a/boards/arm/tiva/tm4c1294-launchpad/configs/nsh/defconfig b/boards/arm/tiva/tm4c1294-launchpad/configs/nsh/defconfig index 369e0c0a8ea..6ee1e6c9555 100644 --- a/boards/arm/tiva/tm4c1294-launchpad/configs/nsh/defconfig +++ b/boards/arm/tiva/tm4c1294-launchpad/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_I2CTOOL_MAXBUS=6 CONFIG_I2CTOOL_MINBUS=6 CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_NOADDR=y diff --git a/boards/arm/tiva/tm4c1294-launchpad/scripts/Make.defs b/boards/arm/tiva/tm4c1294-launchpad/scripts/Make.defs index 61e8166566b..7cce314351c 100644 --- a/boards/arm/tiva/tm4c1294-launchpad/scripts/Make.defs +++ b/boards/arm/tiva/tm4c1294-launchpad/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),arm-nuttx-elf-) diff --git a/boards/arm/tms570/launchxl-tms57004/configs/nsh/defconfig b/boards/arm/tms570/launchxl-tms57004/configs/nsh/defconfig index c2203aee971..a68161f0d28 100644 --- a/boards/arm/tms570/launchxl-tms57004/configs/nsh/defconfig +++ b/boards/arm/tms570/launchxl-tms57004/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_I2C=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/tms570/launchxl-tms57004/scripts/Make.defs b/boards/arm/tms570/launchxl-tms57004/scripts/Make.defs index 31b0b1a2c4d..cf4a015d46c 100644 --- a/boards/arm/tms570/launchxl-tms57004/scripts/Make.defs +++ b/boards/arm/tms570/launchxl-tms57004/scripts/Make.defs @@ -54,8 +54,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/tms570/tms570ls31x-usb-kit/configs/nsh/defconfig b/boards/arm/tms570/tms570ls31x-usb-kit/configs/nsh/defconfig index e5236bb8370..ce9fc20de7f 100644 --- a/boards/arm/tms570/tms570ls31x-usb-kit/configs/nsh/defconfig +++ b/boards/arm/tms570/tms570ls31x-usb-kit/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_I2C=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/tms570/tms570ls31x-usb-kit/scripts/Make.defs b/boards/arm/tms570/tms570ls31x-usb-kit/scripts/Make.defs index 720af2c83ac..81ede1c4ae5 100644 --- a/boards/arm/tms570/tms570ls31x-usb-kit/scripts/Make.defs +++ b/boards/arm/tms570/tms570ls31x-usb-kit/scripts/Make.defs @@ -54,8 +54,8 @@ AFLAGS := $(CFLAGS) -D__ASSEMBLY__ # NXFLAT module definitions -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # ELF module definitions diff --git a/boards/arm/xmc4/xmc4500-relax/configs/nsh/defconfig b/boards/arm/xmc4/xmc4500-relax/configs/nsh/defconfig index d42b5c11fab..02a8ce3849c 100644 --- a/boards/arm/xmc4/xmc4500-relax/configs/nsh/defconfig +++ b/boards/arm/xmc4/xmc4500-relax/configs/nsh/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_I2CTOOL_MAXBUS=0 CONFIG_I2C_RESET=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MTD=y diff --git a/boards/arm/xmc4/xmc4500-relax/scripts/Make.defs b/boards/arm/xmc4/xmc4500-relax/scripts/Make.defs index 639585d2fc2..db2fe44b3ee 100644 --- a/boards/arm/xmc4/xmc4500-relax/scripts/Make.defs +++ b/boards/arm/xmc4/xmc4500-relax/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/arm/xmc4/xmc4700-relax/configs/nsh/defconfig b/boards/arm/xmc4/xmc4700-relax/configs/nsh/defconfig index 94fa0bdc39e..fc441a4eec7 100644 --- a/boards/arm/xmc4/xmc4700-relax/configs/nsh/defconfig +++ b/boards/arm/xmc4/xmc4700-relax/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=8000 CONFIG_BUILTIN=y CONFIG_DEBUG_NOOPT=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/xmc4/xmc4700-relax/scripts/Make.defs b/boards/arm/xmc4/xmc4700-relax/scripts/Make.defs index 6d2614d3046..236ce39e4b9 100644 --- a/boards/arm/xmc4/xmc4700-relax/scripts/Make.defs +++ b/boards/arm/xmc4/xmc4700-relax/scripts/Make.defs @@ -51,8 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 # Loadable module definitions diff --git a/boards/avr/at32uc3/avr32dev1/configs/nsh/defconfig b/boards/avr/at32uc3/avr32dev1/configs/nsh/defconfig index 2380c2d85e7..c3668f2a7c5 100644 --- a/boards/avr/at32uc3/avr32dev1/configs/nsh/defconfig +++ b/boards/avr/at32uc3/avr32dev1/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_ENDIAN_BIG=y CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y diff --git a/boards/avr/at32uc3/avr32dev1/configs/ostest/defconfig b/boards/avr/at32uc3/avr32dev1/configs/ostest/defconfig index 2764db4ec0a..62f78fde7aa 100644 --- a/boards/avr/at32uc3/avr32dev1/configs/ostest/defconfig +++ b/boards/avr/at32uc3/avr32dev1/configs/ostest/defconfig @@ -26,7 +26,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_ENDIAN_BIG=y CONFIG_HOST_WINDOWS=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x00000000 diff --git a/boards/avr/at32uc3/avr32dev1/include/board.h b/boards/avr/at32uc3/avr32dev1/include/board.h index 11723677e2b..89862b3adea 100644 --- a/boards/avr/at32uc3/avr32dev1/include/board.h +++ b/boards/avr/at32uc3/avr32dev1/include/board.h @@ -123,7 +123,7 @@ /* Pin muliplexing selecion *************************************************/ -#define PINMUX_USART1_RXD PINMUX_USART1_RXD_1 +#define PINMUX_USART1_RXD PINMUX_USART1_RXD_2 #define PINMUX_USART1_TXD PINMUX_USART1_TXD_1 /* LED definitions **********************************************************/ diff --git a/boards/avr/at32uc3/avr32dev1/src/Makefile b/boards/avr/at32uc3/avr32dev1/src/Makefile index b042283c046..898afb25e7c 100644 --- a/boards/avr/at32uc3/avr32dev1/src/Makefile +++ b/boards/avr/at32uc3/avr32dev1/src/Makefile @@ -27,5 +27,7 @@ endif ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += avr32_buttons.c endif +CSRCS += avr32_appinit.c +CSRCS += avr32_bringup.c include $(TOPDIR)/boards/Board.mk diff --git a/boards/avr/at32uc3/avr32dev1/src/avr32_appinit.c b/boards/avr/at32uc3/avr32dev1/src/avr32_appinit.c new file mode 100644 index 00000000000..e12a504afc9 --- /dev/null +++ b/boards/avr/at32uc3/avr32dev1/src/avr32_appinit.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/avr/at32uc3/avr32dev1/src/avr32_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "avr32dev1.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return avr32_bringup(); +#else + return OK; +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ +} diff --git a/boards/avr/at32uc3/avr32dev1/src/avr32_bringup.c b/boards/avr/at32uc3/avr32dev1/src/avr32_bringup.c new file mode 100644 index 00000000000..b0d87009694 --- /dev/null +++ b/boards/avr/at32uc3/avr32dev1/src/avr32_bringup.c @@ -0,0 +1,57 @@ +/**************************************************************************** + * boards/avr/at32uc3/avr32dev1/src/avr32_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: avr32_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int avr32_bringup(void) +{ + int ret = OK; + + #warning "Not Implemented" + + return ret; +} diff --git a/boards/avr/at90usb/micropendous3/configs/hello/defconfig b/boards/avr/at90usb/micropendous3/configs/hello/defconfig index 2f0ea2c4e89..19f9c05e2b3 100644 --- a/boards/avr/at90usb/micropendous3/configs/hello/defconfig +++ b/boards/avr/at90usb/micropendous3/configs/hello/defconfig @@ -24,7 +24,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_IDLETHREAD_STACKSIZE=512 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/avr/at90usb/micropendous3/scripts/Make.defs b/boards/avr/at90usb/micropendous3/scripts/Make.defs index 06bf0f83284..5a36b8a272d 100644 --- a/boards/avr/at90usb/micropendous3/scripts/Make.defs +++ b/boards/avr/at90usb/micropendous3/scripts/Make.defs @@ -47,6 +47,6 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/avr/at90usb/teensy-2.0/configs/hello/defconfig b/boards/avr/at90usb/teensy-2.0/configs/hello/defconfig index 0b2e790d1ff..aab3024df5d 100644 --- a/boards/avr/at90usb/teensy-2.0/configs/hello/defconfig +++ b/boards/avr/at90usb/teensy-2.0/configs/hello/defconfig @@ -24,7 +24,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_IDLETHREAD_STACKSIZE=512 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/avr/at90usb/teensy-2.0/configs/nsh/defconfig b/boards/avr/at90usb/teensy-2.0/configs/nsh/defconfig index 0c0cf9a8576..27c94c55aa6 100644 --- a/boards/avr/at90usb/teensy-2.0/configs/nsh/defconfig +++ b/boards/avr/at90usb/teensy-2.0/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y CONFIG_IDLETHREAD_STACKSIZE=512 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/avr/at90usb/teensy-2.0/configs/usbmsc/defconfig b/boards/avr/at90usb/teensy-2.0/configs/usbmsc/defconfig index 3b49fb2c816..d047ad94f41 100644 --- a/boards/avr/at90usb/teensy-2.0/configs/usbmsc/defconfig +++ b/boards/avr/at90usb/teensy-2.0/configs/usbmsc/defconfig @@ -25,7 +25,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_IDLETHREAD_STACKSIZE=512 CONFIG_INTELHEX_BINARY=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=8 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 diff --git a/boards/avr/at90usb/teensy-2.0/scripts/Make.defs b/boards/avr/at90usb/teensy-2.0/scripts/Make.defs index 7effe7e80fd..eb0c6edc721 100644 --- a/boards/avr/at90usb/teensy-2.0/scripts/Make.defs +++ b/boards/avr/at90usb/teensy-2.0/scripts/Make.defs @@ -49,6 +49,6 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/avr/atmega/amber/configs/hello/defconfig b/boards/avr/atmega/amber/configs/hello/defconfig index 3d6793cf300..e012e2b1e5b 100644 --- a/boards/avr/atmega/amber/configs/hello/defconfig +++ b/boards/avr/atmega/amber/configs/hello/defconfig @@ -24,7 +24,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_IDLETHREAD_STACKSIZE=512 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/avr/atmega/amber/scripts/Make.defs b/boards/avr/atmega/amber/scripts/Make.defs index aaf6a7b5ea9..7b18f826936 100644 --- a/boards/avr/atmega/amber/scripts/Make.defs +++ b/boards/avr/atmega/amber/scripts/Make.defs @@ -47,6 +47,6 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/avr/atmega/arduino-mega2560/configs/hello/defconfig b/boards/avr/atmega/arduino-mega2560/configs/hello/defconfig index eebada1e120..230cf63cec0 100644 --- a/boards/avr/atmega/arduino-mega2560/configs/hello/defconfig +++ b/boards/avr/atmega/arduino-mega2560/configs/hello/defconfig @@ -26,7 +26,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_IDLETHREAD_STACKSIZE=128 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/avr/atmega/arduino-mega2560/configs/nsh/defconfig b/boards/avr/atmega/arduino-mega2560/configs/nsh/defconfig index d6c4bc090c3..a25ecf76828 100644 --- a/boards/avr/atmega/arduino-mega2560/configs/nsh/defconfig +++ b/boards/avr/atmega/arduino-mega2560/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y CONFIG_IDLETHREAD_STACKSIZE=128 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 CONFIG_NUNGET_CHARS=0 CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=512 diff --git a/boards/avr/atmega/arduino-mega2560/scripts/Make.defs b/boards/avr/atmega/arduino-mega2560/scripts/Make.defs index 522a033267a..be673e2f376 100644 --- a/boards/avr/atmega/arduino-mega2560/scripts/Make.defs +++ b/boards/avr/atmega/arduino-mega2560/scripts/Make.defs @@ -49,8 +49,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 EXEEXT = .elf diff --git a/boards/avr/atmega/moteino-mega/configs/hello/defconfig b/boards/avr/atmega/moteino-mega/configs/hello/defconfig index d7af2c5375a..3fe8c8fda30 100644 --- a/boards/avr/atmega/moteino-mega/configs/hello/defconfig +++ b/boards/avr/atmega/moteino-mega/configs/hello/defconfig @@ -24,7 +24,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_IDLETHREAD_STACKSIZE=512 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=4 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/avr/atmega/moteino-mega/configs/nsh/defconfig b/boards/avr/atmega/moteino-mega/configs/nsh/defconfig index 85b844e090d..05b3192e9f5 100644 --- a/boards/avr/atmega/moteino-mega/configs/nsh/defconfig +++ b/boards/avr/atmega/moteino-mega/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y CONFIG_IDLETHREAD_STACKSIZE=512 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/avr/atmega/moteino-mega/scripts/Make.defs b/boards/avr/atmega/moteino-mega/scripts/Make.defs index 4fc13f4f40e..e8581469926 100644 --- a/boards/avr/atmega/moteino-mega/scripts/Make.defs +++ b/boards/avr/atmega/moteino-mega/scripts/Make.defs @@ -47,6 +47,6 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/boardctl.c b/boards/boardctl.c index 538d29d2cfa..3a7443cb5d7 100644 --- a/boards/boardctl.c +++ b/boards/boardctl.c @@ -418,6 +418,24 @@ int boardctl(unsigned int cmd, uintptr_t arg) break; #endif +#ifdef CONFIG_BOARDCTL_UNIQUEKEY + /* CMD: BOARDIOC_UNIQUEKEY + * DESCRIPTION: Return a unique KEY associated with the board (such + * as a trusted key or a private identity). + * ARG: A writable array of size + * CONFIG_BOARDCTL_UNIQUEKEY_SIZE in which to receive + * the board unique KEY. + * DEPENDENCIES: Board logic must provide the board_uniquekey() + * interface. + */ + + case BOARDIOC_UNIQUEKEY: + { + ret = board_uniquekey((FAR uint8_t *)arg); + } + break; +#endif + #ifdef CONFIG_BOARDCTL_MKRD /* CMD: BOARDIOC_MKRD * DESCRIPTION: Create a RAM disk diff --git a/boards/hc/m9s12/demo9s12ne64/configs/ostest/defconfig b/boards/hc/m9s12/demo9s12ne64/configs/ostest/defconfig index 83c0282bdf4..785e945dc2b 100644 --- a/boards/hc/m9s12/demo9s12ne64/configs/ostest/defconfig +++ b/boards/hc/m9s12/demo9s12ne64/configs/ostest/defconfig @@ -25,7 +25,6 @@ CONFIG_HCS12_NONBANKED=y CONFIG_HCS12_SCI0=y CONFIG_HCS12_SERIALMON=y CONFIG_IDLETHREAD_STACKSIZE=256 -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=3 CONFIG_NUNGET_CHARS=0 diff --git a/boards/hc/m9s12/demo9s12ne64/scripts/Make.defs b/boards/hc/m9s12/demo9s12ne64/scripts/Make.defs index d215cc3b88b..30991396e54 100644 --- a/boards/hc/m9s12/demo9s12ne64/scripts/Make.defs +++ b/boards/hc/m9s12/demo9s12ne64/scripts/Make.defs @@ -67,8 +67,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 LDFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/hc/m9s12/ne64badge/configs/ostest/defconfig b/boards/hc/m9s12/ne64badge/configs/ostest/defconfig index 6846916041b..ae15d38949f 100644 --- a/boards/hc/m9s12/ne64badge/configs/ostest/defconfig +++ b/boards/hc/m9s12/ne64badge/configs/ostest/defconfig @@ -24,7 +24,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_HCS12_NONBANKED=y CONFIG_HCS12_SCI0=y CONFIG_IDLETHREAD_STACKSIZE=256 -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=3 CONFIG_NUNGET_CHARS=0 diff --git a/boards/hc/m9s12/ne64badge/scripts/Make.defs b/boards/hc/m9s12/ne64badge/scripts/Make.defs index 5b8569a839b..368e6f505a5 100644 --- a/boards/hc/m9s12/ne64badge/scripts/Make.defs +++ b/boards/hc/m9s12/ne64badge/scripts/Make.defs @@ -67,8 +67,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 LDFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/hc/m9s12/ne64badge/src/m9s12_leds.c b/boards/hc/m9s12/ne64badge/src/m9s12_leds.c index 4fa7f58ba3f..721ef090be9 100644 --- a/boards/hc/m9s12/ne64badge/src/m9s12_leds.c +++ b/boards/hc/m9s12/ne64badge/src/m9s12_leds.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/boards/mips/pic32mx/mirtoo/configs/nsh/defconfig b/boards/mips/pic32mx/mirtoo/configs/nsh/defconfig index 502e8f9b962..09a433f9b10 100644 --- a/boards/mips/pic32mx/mirtoo/configs/nsh/defconfig +++ b/boards/mips/pic32mx/mirtoo/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_PIC32MX_DEBUGGER=1 CONFIG_PIC32MX_ICESEL=2 CONFIG_PIC32MX_OSCOUT=1 diff --git a/boards/mips/pic32mx/mirtoo/configs/nxffs/defconfig b/boards/mips/pic32mx/mirtoo/configs/nxffs/defconfig index 12d9017a50a..88e7ad35740 100644 --- a/boards/mips/pic32mx/mirtoo/configs/nxffs/defconfig +++ b/boards/mips/pic32mx/mirtoo/configs/nxffs/defconfig @@ -28,7 +28,6 @@ CONFIG_FS_NXFFS=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MIPS32_TOOLCHAIN_PINGUINOW=y CONFIG_MTD=y CONFIG_MTD_SST25=y diff --git a/boards/mips/pic32mx/mirtoo/src/pic32_appinit.c b/boards/mips/pic32mx/mirtoo/src/pic32_appinit.c index b927fba194e..54c7dabca82 100644 --- a/boards/mips/pic32mx/mirtoo/src/pic32_appinit.c +++ b/boards/mips/pic32mx/mirtoo/src/pic32_appinit.c @@ -26,8 +26,8 @@ #include #include +#include #include -#include #include #include diff --git a/boards/mips/pic32mx/pic32mx-starterkit/configs/nsh/defconfig b/boards/mips/pic32mx/pic32mx-starterkit/configs/nsh/defconfig index e8774df0ca3..aaa2e69d561 100644 --- a/boards/mips/pic32mx/pic32mx-starterkit/configs/nsh/defconfig +++ b/boards/mips/pic32mx/pic32mx-starterkit/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MTD=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/mips/pic32mx/pic32mx-starterkit/configs/nsh2/defconfig b/boards/mips/pic32mx/pic32mx-starterkit/configs/nsh2/defconfig index b9d2b46b3c0..9deda0790fb 100644 --- a/boards/mips/pic32mx/pic32mx-starterkit/configs/nsh2/defconfig +++ b/boards/mips/pic32mx/pic32mx-starterkit/configs/nsh2/defconfig @@ -29,7 +29,6 @@ CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MTD=y CONFIG_NET=y diff --git a/boards/mips/pic32mx/pic32mx7mmb/configs/nsh/defconfig b/boards/mips/pic32mx/pic32mx7mmb/configs/nsh/defconfig index f5df7f5c2a3..0af7e9e8105 100644 --- a/boards/mips/pic32mx/pic32mx7mmb/configs/nsh/defconfig +++ b/boards/mips/pic32mx/pic32mx7mmb/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MIPS32_TOOLCHAIN_PINGUINOW=y CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=12500000 diff --git a/boards/mips/pic32mx/pic32mx7mmb/src/pic32_mio283qt2.c b/boards/mips/pic32mx/pic32mx7mmb/src/pic32_mio283qt2.c index 5ec2e006e45..f521a291cea 100644 --- a/boards/mips/pic32mx/pic32mx7mmb/src/pic32_mio283qt2.c +++ b/boards/mips/pic32mx/pic32mx7mmb/src/pic32_mio283qt2.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include diff --git a/boards/mips/pic32mx/sure-pic32mx/configs/nsh/defconfig b/boards/mips/pic32mx/sure-pic32mx/configs/nsh/defconfig index 964d0c56453..9c37b031623 100644 --- a/boards/mips/pic32mx/sure-pic32mx/configs/nsh/defconfig +++ b/boards/mips/pic32mx/sure-pic32mx/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_BUILTIN=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/mips/pic32mx/sure-pic32mx/configs/usbnsh/defconfig b/boards/mips/pic32mx/sure-pic32mx/configs/usbnsh/defconfig index 0d14af9593e..ed2e76d0f62 100644 --- a/boards/mips/pic32mx/sure-pic32mx/configs/usbnsh/defconfig +++ b/boards/mips/pic32mx/sure-pic32mx/configs/usbnsh/defconfig @@ -28,7 +28,6 @@ CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/mips/pic32mx/sure-pic32mx/src/pic32mx_lcd1602.c b/boards/mips/pic32mx/sure-pic32mx/src/pic32mx_lcd1602.c index d5fa0823ebc..a1ccf416630 100644 --- a/boards/mips/pic32mx/sure-pic32mx/src/pic32mx_lcd1602.c +++ b/boards/mips/pic32mx/sure-pic32mx/src/pic32mx_lcd1602.c @@ -63,6 +63,7 @@ #include #include #include +#include #include #include diff --git a/boards/mips/pic32mx/ubw32/configs/nsh/defconfig b/boards/mips/pic32mx/ubw32/configs/nsh/defconfig index 6685257e131..4791ba62270 100644 --- a/boards/mips/pic32mx/ubw32/configs/nsh/defconfig +++ b/boards/mips/pic32mx/ubw32/configs/nsh/defconfig @@ -27,7 +27,6 @@ CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/mips/pic32mz/flipnclick-pic32mz/configs/nsh/defconfig b/boards/mips/pic32mz/flipnclick-pic32mz/configs/nsh/defconfig index 33a0b2f1926..4f042f3ace0 100644 --- a/boards/mips/pic32mz/flipnclick-pic32mz/configs/nsh/defconfig +++ b/boards/mips/pic32mz/flipnclick-pic32mz/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MIPS32_TOOLCHAIN_PINGUINOW=y CONFIG_MIPS_MICROMIPS=y CONFIG_MMCSD=y diff --git a/boards/mips/pic32mz/flipnclick-pic32mz/configs/nxlines/defconfig b/boards/mips/pic32mz/flipnclick-pic32mz/configs/nxlines/defconfig index ab84184a0e1..e1a741ca7c9 100644 --- a/boards/mips/pic32mz/flipnclick-pic32mz/configs/nxlines/defconfig +++ b/boards/mips/pic32mz/flipnclick-pic32mz/configs/nxlines/defconfig @@ -30,7 +30,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_HILETGO=y CONFIG_LCD_MAXCONTRAST=255 -CONFIG_MAX_TASKS=16 CONFIG_MIPS32_TOOLCHAIN_PINGUINOW=y CONFIG_MIPS_MICROMIPS=y CONFIG_MMCSD=y diff --git a/boards/mips/pic32mz/pic32mz-starterkit/configs/nsh/defconfig b/boards/mips/pic32mz/pic32mz-starterkit/configs/nsh/defconfig index db416ec655e..05d077f5aa0 100644 --- a/boards/mips/pic32mz/pic32mz-starterkit/configs/nsh/defconfig +++ b/boards/mips/pic32mz/pic32mz-starterkit/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MIPS32_TOOLCHAIN_PINGUINOW=y CONFIG_MIPS_MICROMIPS=y CONFIG_MMCSD=y diff --git a/boards/misoc/lm32/misoc/configs/hello/defconfig b/boards/misoc/lm32/misoc/configs/hello/defconfig index 10a39a8adb3..ff96e5cf269 100644 --- a/boards/misoc/lm32/misoc/configs/hello/defconfig +++ b/boards/misoc/lm32/misoc/configs/hello/defconfig @@ -36,7 +36,6 @@ CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IOB_NBUFFERS=24 CONFIG_LIB_HOSTNAME="nuttx" -CONFIG_MAX_TASKS=16 CONFIG_MISOC_ETHERNET=y CONFIG_MISOC_UART1=y CONFIG_NET=y diff --git a/boards/misoc/lm32/misoc/configs/nsh/defconfig b/boards/misoc/lm32/misoc/configs/nsh/defconfig index 722ab9252b9..d910755f8da 100644 --- a/boards/misoc/lm32/misoc/configs/nsh/defconfig +++ b/boards/misoc/lm32/misoc/configs/nsh/defconfig @@ -52,7 +52,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXPERIMENTAL=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=4 CONFIG_MISOC_UART1=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/misoc/lm32/misoc/scripts/Make.defs b/boards/misoc/lm32/misoc/scripts/Make.defs index 39525408cd6..87fe4a89f35 100644 --- a/boards/misoc/lm32/misoc/scripts/Make.defs +++ b/boards/misoc/lm32/misoc/scripts/Make.defs @@ -71,6 +71,6 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/or1k/mor1kx/or1k/configs/nsh/defconfig b/boards/or1k/mor1kx/or1k/configs/nsh/defconfig index edf38f800af..5a48b14914b 100644 --- a/boards/or1k/mor1kx/or1k/configs/nsh/defconfig +++ b/boards/or1k/mor1kx/or1k/configs/nsh/defconfig @@ -68,7 +68,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/or1k/mor1kx/or1k/scripts/Make.defs b/boards/or1k/mor1kx/or1k/scripts/Make.defs index bc34cf58f75..23c15c15881 100644 --- a/boards/or1k/mor1kx/or1k/scripts/Make.defs +++ b/boards/or1k/mor1kx/or1k/scripts/Make.defs @@ -66,8 +66,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS := $(CFLAGS) -D__ASSEMBLY__ -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections LDNXFLATFLAGS = -e main -s 2048 ifneq ($(CROSSDEV),or1k-nuttx-elf-) diff --git a/boards/renesas/m16c/skp16c26/README.txt b/boards/renesas/m16c/skp16c26/README.txt index b30b3d407ba..99cbb7fd149 100644 --- a/boards/renesas/m16c/skp16c26/README.txt +++ b/boards/renesas/m16c/skp16c26/README.txt @@ -27,7 +27,7 @@ boards/renesas/m16c/skp16c26/README.txt c:\Hew3\Tools\KPIT Cummins\GNUM16CM32C-ELF\v0901\m32c-elf\bin\m32c-elf-ld.exe: BFD (GNU Binutils) 2.19-GNUM16CM32C_v0901 assertion fail /home/kpit/fsfsrc/binutils-2.19/bfd/elf32-m32c.c:482 -It is possible that this error messasge my be telling me -- a very roundabout way -- +It is possible that this error message may be telling me -- a very roundabout way -- that I have exceeded the FLASH region, but I think that unlikely (it is difficult to know if the link does not complete gracefully). diff --git a/boards/renesas/m16c/skp16c26/configs/ostest/defconfig b/boards/renesas/m16c/skp16c26/configs/ostest/defconfig index 17863733e1c..fb1af80d58a 100644 --- a/boards/renesas/m16c/skp16c26/configs/ostest/defconfig +++ b/boards/renesas/m16c/skp16c26/configs/ostest/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_ENDIAN_BIG=y CONFIG_IDLETHREAD_STACKSIZE=256 -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig b/boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig index bd5eb440dcd..5bc89e81211 100644 --- a/boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig +++ b/boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig @@ -24,7 +24,6 @@ CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y CONFIG_EXAMPLES_SERIALRX_PRIORITY=75 CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NET=y CONFIG_NETDEV_PHY_IOCTL=y diff --git a/boards/renesas/rx65n/rx65n-grrose/configs/netnsh/defconfig b/boards/renesas/rx65n/rx65n-grrose/configs/netnsh/defconfig index fb8f9a76aff..7eba4b11085 100644 --- a/boards/renesas/rx65n/rx65n-grrose/configs/netnsh/defconfig +++ b/boards/renesas/rx65n/rx65n-grrose/configs/netnsh/defconfig @@ -22,7 +22,6 @@ CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y CONFIG_EXAMPLES_SERIALRX_PRIORITY=75 CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/renesas/rx65n/rx65n-grrose/configs/nsh/defconfig b/boards/renesas/rx65n/rx65n-grrose/configs/nsh/defconfig index ce9f3e59a72..66f483875c0 100644 --- a/boards/renesas/rx65n/rx65n-grrose/configs/nsh/defconfig +++ b/boards/renesas/rx65n/rx65n-grrose/configs/nsh/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15001 CONFIG_BUILTIN=y CONFIG_DEBUG_FEATURES=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c index 2749e2fe874..5794c871945 100644 --- a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c +++ b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c index 31153f7baa7..298e8f1e336 100644 --- a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c +++ b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/configs/netnsh/defconfig b/boards/renesas/rx65n/rx65n-rsk1mb/configs/netnsh/defconfig index 8504743fc68..f99b3f5f900 100644 --- a/boards/renesas/rx65n/rx65n-rsk1mb/configs/netnsh/defconfig +++ b/boards/renesas/rx65n/rx65n-rsk1mb/configs/netnsh/defconfig @@ -18,7 +18,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_ETH0_PHY_KSZ8081=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/configs/nsh/defconfig b/boards/renesas/rx65n/rx65n-rsk1mb/configs/nsh/defconfig index ee25eea81ec..5ffcbd91e6b 100644 --- a/boards/renesas/rx65n/rx65n-rsk1mb/configs/nsh/defconfig +++ b/boards/renesas/rx65n/rx65n-rsk1mb/configs/nsh/defconfig @@ -17,7 +17,6 @@ CONFIG_ARCH_RENESAS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BUILTIN=y CONFIG_DEBUG_FEATURES=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig b/boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig index 03472a0a198..9cbfa63acc9 100644 --- a/boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig +++ b/boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig @@ -24,7 +24,6 @@ CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y CONFIG_EXAMPLES_SERIALRX_PRIORITY=75 CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NET=y CONFIG_NETDEV_PHY_IOCTL=y diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/configs/netnsh/defconfig b/boards/renesas/rx65n/rx65n-rsk2mb/configs/netnsh/defconfig index 31abe5021cd..d02780a9cc1 100644 --- a/boards/renesas/rx65n/rx65n-rsk2mb/configs/netnsh/defconfig +++ b/boards/renesas/rx65n/rx65n-rsk2mb/configs/netnsh/defconfig @@ -22,7 +22,6 @@ CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y CONFIG_EXAMPLES_SERIALRX_PRIORITY=75 CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/configs/nsh/defconfig b/boards/renesas/rx65n/rx65n-rsk2mb/configs/nsh/defconfig index 1b5eb838034..e6f524e1808 100644 --- a/boards/renesas/rx65n/rx65n-rsk2mb/configs/nsh/defconfig +++ b/boards/renesas/rx65n/rx65n-rsk2mb/configs/nsh/defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15001 CONFIG_BUILTIN=y CONFIG_DEBUG_FEATURES=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c index b1987e069e5..e5a33f0c6f8 100644 --- a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c +++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c index 04a8ab3e783..d50cf108dde 100644 --- a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c +++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/boards/renesas/rx65n/rx65n/configs/nsh/defconfig b/boards/renesas/rx65n/rx65n/configs/nsh/defconfig index bc322f8ffd3..03e93b6f31b 100644 --- a/boards/renesas/rx65n/rx65n/configs/nsh/defconfig +++ b/boards/renesas/rx65n/rx65n/configs/nsh/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BUILTIN=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/renesas/sh1/us7032evb1/configs/nsh/defconfig b/boards/renesas/sh1/us7032evb1/configs/nsh/defconfig index 9fe80133645..f4478656406 100644 --- a/boards/renesas/sh1/us7032evb1/configs/nsh/defconfig +++ b/boards/renesas/sh1/us7032evb1/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_PTHREAD=y CONFIG_ENDIAN_BIG=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 diff --git a/boards/renesas/sh1/us7032evb1/configs/ostest/defconfig b/boards/renesas/sh1/us7032evb1/configs/ostest/defconfig index 2085e898d72..7e8defbfd35 100644 --- a/boards/renesas/sh1/us7032evb1/configs/ostest/defconfig +++ b/boards/renesas/sh1/us7032evb1/configs/ostest/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_PTHREAD=y CONFIG_ENDIAN_BIG=y -CONFIG_MAX_TASKS=8 CONFIG_MOTOROLA_SREC=y CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/risc-v/bl602/bl602evb/configs/ble/defconfig b/boards/risc-v/bl602/bl602evb/configs/ble/defconfig index 66e9dc490a5..838e7c9ef48 100644 --- a/boards/risc-v/bl602/bl602evb/configs/ble/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/ble/defconfig @@ -29,6 +29,7 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_SMALL=y CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EXAMPLES_DHCPD=y @@ -43,7 +44,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=1024 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y @@ -58,7 +58,6 @@ CONFIG_NET_ARP_SEND=y CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_DELAYED_ACK=y CONFIG_NET_TCP_KEEPALIVE=y @@ -100,10 +99,12 @@ CONFIG_TASK_NAME_SIZE=12 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=8192 CONFIG_TESTING_MM=y CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_FPUSIZE=132 CONFIG_UART0_BAUD=2000000 CONFIG_UART0_RXBUFSIZE=128 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART0_TXBUFSIZE=128 +CONFIG_UART_BTH4=y CONFIG_USERMAIN_STACKSIZE=8192 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WIRELESS_WAPI=y diff --git a/boards/risc-v/bl602/bl602evb/configs/elf/defconfig b/boards/risc-v/bl602/bl602evb/configs/elf/defconfig index 6fe7075215c..849f97205a0 100644 --- a/boards/risc-v/bl602/bl602evb/configs/elf/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/elf/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BL602_HAVE_UART0=y CONFIG_BL602_TIMER0=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=10000 CONFIG_BUILTIN=y CONFIG_DEBUG_FEATURES=y @@ -39,7 +40,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/fpu/defconfig b/boards/risc-v/bl602/bl602evb/configs/fpu/defconfig index 07e32247b2b..3c952bc4d0c 100644 --- a/boards/risc-v/bl602/bl602evb/configs/fpu/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/fpu/defconfig @@ -35,7 +35,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/gpio/defconfig b/boards/risc-v/bl602/bl602evb/configs/gpio/defconfig index 9ea5929f8c6..3eed8c5bcfc 100644 --- a/boards/risc-v/bl602/bl602evb/configs/gpio/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/gpio/defconfig @@ -37,7 +37,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/i2c/defconfig b/boards/risc-v/bl602/bl602evb/configs/i2c/defconfig index 340afb633d5..6e079fb31af 100644 --- a/boards/risc-v/bl602/bl602evb/configs/i2c/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/i2c/defconfig @@ -37,7 +37,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig b/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig index d2a8e7e4909..277bf21856f 100644 --- a/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig @@ -35,7 +35,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/spi/defconfig b/boards/risc-v/bl602/bl602evb/configs/spi/defconfig index 60d181ab56f..175a44d7b4f 100644 --- a/boards/risc-v/bl602/bl602evb/configs/spi/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/spi/defconfig @@ -36,7 +36,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/spiflash/defconfig b/boards/risc-v/bl602/bl602evb/configs/spiflash/defconfig index 4ea53dfb70e..8c413a3ff9b 100644 --- a/boards/risc-v/bl602/bl602evb/configs/spiflash/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/spiflash/defconfig @@ -37,7 +37,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/timer/defconfig b/boards/risc-v/bl602/bl602evb/configs/timer/defconfig index 3910f841811..15cc7db663a 100644 --- a/boards/risc-v/bl602/bl602evb/configs/timer/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/timer/defconfig @@ -38,7 +38,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/bl602/bl602evb/configs/wifi/defconfig b/boards/risc-v/bl602/bl602evb/configs/wifi/defconfig index 18740991a7b..6ee05c2c10c 100644 --- a/boards/risc-v/bl602/bl602evb/configs/wifi/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/wifi/defconfig @@ -60,7 +60,6 @@ CONFIG_LIBC_LOCALTIME=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MEMCPY_VIK=y CONFIG_MEMSET_OPTSPEED=y CONFIG_MM_REGIONS=2 @@ -81,7 +80,6 @@ CONFIG_NET_ARP_SEND=y CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_KEEPALIVE=y CONFIG_NET_TCP_NOTIFIER=y diff --git a/boards/risc-v/bl602/bl602evb/scripts/ld.script b/boards/risc-v/bl602/bl602evb/scripts/ld.script index 74ed85d9ef3..da48feb555a 100644 --- a/boards/risc-v/bl602/bl602evb/scripts/ld.script +++ b/boards/risc-v/bl602/bl602evb/scripts/ld.script @@ -3,6 +3,10 @@ OUTPUT_ARCH( "riscv" ) ENTRY( bl602_start ) __EM_SIZE = DEFINED(ble_controller_init) ? 8K : 0K; +__RFTLV_SIZE_OFFSET = 1K; +__RFTLV_SIZE_HOLE = 2K; +__RFTLV_HEAD1_H = (0x46524C42); /* BLRF */ +__RFTLV_HEAD1_L = (0x41524150); /* PAPA */ MEMORY { @@ -23,6 +27,17 @@ SECTIONS KEEP (*(SORT_NONE(.init))) } > flash + /* value for rftlv */ + + .rftlv.tool : + { + . = ORIGIN(flash) + __RFTLV_SIZE_OFFSET; + PROVIDE( _ld_symbol_rftlv_address = . ); + LONG(__RFTLV_HEAD1_H); + LONG(__RFTLV_HEAD1_L); + . = ORIGIN(flash) + __RFTLV_SIZE_OFFSET + __RFTLV_SIZE_HOLE; + } > flash + .text : { PROVIDE(_stext = .); diff --git a/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c b/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c index 80dfbf9b451..981308fa54f 100644 --- a/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c +++ b/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -46,6 +47,7 @@ #include #include #include +#include #if defined(CONFIG_BL602_SPIFLASH) #include @@ -68,36 +70,20 @@ * Private Function Prototypes ****************************************************************************/ -#if defined(CONFIG_BL602_BLE_CONTROLLER) -static void bl602_net_poll_work(FAR void *arg); -static void ble_hci_rx_poll_expiry(wdparm_t arg); -#endif - /**************************************************************************** * Private Data ****************************************************************************/ -#if defined(CONFIG_BL602_BLE_CONTROLLER) -/* BLE HCI timer */ - -static struct wdog_s g_ble_hci_rx_poll; - -/* For deferring poll work to the work queue */ - -static struct work_s g_ble_hci_rx_work; -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ #if defined(CONFIG_BL602_WIRELESS) -extern int bl602_net_initialize(int intf); +extern int bl602_net_initialize(void); #endif #if defined(CONFIG_BL602_BLE_CONTROLLER) extern void bl602_hci_uart_init(uint8_t uartid); -extern int ble_hci_do_rx(void); #endif /**************************************************************************** @@ -272,16 +258,38 @@ int bl602_bringup(void) #ifdef CONFIG_BL602_WIRELESS bl602_set_em_sel(BL602_GLB_EM_8KB); - bl602_net_initialize(0); + bl602_net_initialize(); +#endif + +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the BL602 lower-half RTC driver */ + + FAR struct rtc_lowerhalf_s *lower; + + lower = bl602_rtc_lowerhalf_initialize(); + if (!lower) + { + syslog(LOG_ERR, + "ERROR: Failed to instantiate the RTC lower-half driver\n"); + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind/register the RTC driver: %d\n", + ret); + } + } #endif #if defined(CONFIG_BL602_BLE_CONTROLLER) bl602_hci_uart_init(0); - - /* 50ms interval */ - - wd_start(&g_ble_hci_rx_poll, - 1 * CLOCKS_PER_SEC / 20, ble_hci_rx_poll_expiry, (wdparm_t)NULL); #endif /* CONFIG_BL602_BLE_CONTROLLER */ #ifdef CONFIG_FS_ROMFS @@ -312,29 +320,3 @@ int bl602_bringup(void) return ret; } - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if defined(CONFIG_BL602_BLE_CONTROLLER) -static void bl602_net_poll_work(FAR void *arg) -{ - ble_hci_do_rx(); - - /* 50ms interval */ - - wd_start(&g_ble_hci_rx_poll, - 1 * CLOCKS_PER_SEC / 20, ble_hci_rx_poll_expiry, (wdparm_t)NULL); -} - -static void ble_hci_rx_poll_expiry(wdparm_t arg) -{ - UNUSED(arg); - - if (work_available(&g_ble_hci_rx_work)) - { - work_queue(LPWORK, &g_ble_hci_rx_work, bl602_net_poll_work, NULL, 0); - } -} -#endif diff --git a/boards/risc-v/c906/smartl-c906/configs/elf/defconfig b/boards/risc-v/c906/smartl-c906/configs/elf/defconfig index 806ea25d82b..eb63e400669 100644 --- a/boards/risc-v/c906/smartl-c906/configs/elf/defconfig +++ b/boards/risc-v/c906/smartl-c906/configs/elf/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_CHIP_C906=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=46000 CONFIG_BUILTIN=y CONFIG_C906_ENABLE_DPFPU=y @@ -33,7 +34,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/risc-v/c906/smartl-c906/configs/fpu/defconfig b/boards/risc-v/c906/smartl-c906/configs/fpu/defconfig index e5ac51a98cb..5f0eb114382 100644 --- a/boards/risc-v/c906/smartl-c906/configs/fpu/defconfig +++ b/boards/risc-v/c906/smartl-c906/configs/fpu/defconfig @@ -29,7 +29,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/risc-v/c906/smartl-c906/configs/knsh/defconfig b/boards/risc-v/c906/smartl-c906/configs/knsh/defconfig index c22533fc903..0a3e1fa41f2 100644 --- a/boards/risc-v/c906/smartl-c906/configs/knsh/defconfig +++ b/boards/risc-v/c906/smartl-c906/configs/knsh/defconfig @@ -30,7 +30,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_MM_KERNEL_HEAPSIZE=524288 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y @@ -57,7 +56,7 @@ CONFIG_START_DAY=7 CONFIG_START_MONTH=3 CONFIG_START_YEAR=2021 CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=20 CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y diff --git a/boards/risc-v/c906/smartl-c906/configs/module/defconfig b/boards/risc-v/c906/smartl-c906/configs/module/defconfig index 14a14a4ca8f..7eec8f3f367 100644 --- a/boards/risc-v/c906/smartl-c906/configs/module/defconfig +++ b/boards/risc-v/c906/smartl-c906/configs/module/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_CHIP_C906=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=46000 CONFIG_BUILTIN=y CONFIG_C906_ENABLE_DPFPU=y @@ -33,7 +34,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_MODULE=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/c906/smartl-c906/configs/nsh/defconfig b/boards/risc-v/c906/smartl-c906/configs/nsh/defconfig index cec4d3d2413..5e5c0782c51 100644 --- a/boards/risc-v/c906/smartl-c906/configs/nsh/defconfig +++ b/boards/risc-v/c906/smartl-c906/configs/nsh/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/risc-v/c906/smartl-c906/configs/sotest/defconfig b/boards/risc-v/c906/smartl-c906/configs/sotest/defconfig index 5b14a3300f6..7eb2c465954 100644 --- a/boards/risc-v/c906/smartl-c906/configs/sotest/defconfig +++ b/boards/risc-v/c906/smartl-c906/configs/sotest/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_CHIP_C906=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=46000 CONFIG_BUILTIN=y CONFIG_C906_ENABLE_DPFPU=y @@ -34,7 +35,6 @@ CONFIG_LIBC_DLFCN=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/risc-v/c906/smartl-c906/kernel/c906_userspace.c b/boards/risc-v/c906/smartl-c906/kernel/c906_userspace.c index 1f5a2f34aad..9f24ab1a9d7 100644 --- a/boards/risc-v/c906/smartl-c906/kernel/c906_userspace.c +++ b/boards/risc-v/c906/smartl-c906/kernel/c906_userspace.c @@ -99,9 +99,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/risc-v/c906/smartl-c906/src/c906_bringup.c b/boards/risc-v/c906/smartl-c906/src/c906_bringup.c index 71cf487f714..2231938fb0c 100644 --- a/boards/risc-v/c906/smartl-c906/src/c906_bringup.c +++ b/boards/risc-v/c906/smartl-c906/src/c906_bringup.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/Kconfig b/boards/risc-v/esp32c3/esp32c3-devkit/Kconfig index 6259575c555..afe5a2a433a 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/Kconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/Kconfig @@ -5,6 +5,38 @@ if ARCH_BOARD_ESP32C3_DEVKIT +if PM + +config PM_ALARM_SEC + int "PM_STANDBY delay (seconds)" + default 15 + depends on PM + ---help--- + Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. + +config PM_ALARM_NSEC + int "PM_STANDBY delay (nanoseconds)" + default 0 + depends on PM + ---help--- + Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. + +config PM_SLEEP_WAKEUP_SEC + int "PM_SLEEP delay (seconds)" + default 20 + depends on PM + ---help--- + Number of seconds to wait in PM_SLEEP. + +config PM_SLEEP_WAKEUP_NSEC + int "PM_SLEEP delay (nanoseconds)" + default 0 + depends on PM + ---help--- + Number of additional nanoseconds to wait in PM_SLEEP. + +endif # PM + config ESP32C3_DEVKIT_RUN_IRAM bool "Run from IRAM" default n @@ -33,4 +65,25 @@ choice endchoice +config ESP32C3_SPIFLASH_FS_MOUNT_PT + string "File-system Mount Point" + depends on ESP32C3_SPIFLASH_LITTLEFS + default "/data" + +config ESP32C3_SPIFLASH_ENCRYPTION_TEST + bool "SPI Flash encryption test" + default n + depends on ESP32C3_SPIFLASH + select DEBUG_ASSERTIONS + ---help--- + Enable SPI Flash encryption test. This option will also select + DEBUG_ASSERTIONS to enable kernel assert macro. + +config ESP32C3_SPIFLASH_TEST_ADDRESS + hex "SPI Flash test address" + default 0x180000 + depends on ESP32C3_SPIFLASH_ENCRYPTION_TEST + ---help--- + SPI Flash encryption test read/write address. + endif # ARCH_BOARD_ESP32C3_DEVKIT diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/README.txt b/boards/risc-v/esp32c3/esp32c3-devkit/README.txt deleted file mode 100644 index 1e6c8c8bdf5..00000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/README.txt +++ /dev/null @@ -1,147 +0,0 @@ -README for the Espressif ESP32-C3 DevKit -======================================= - - The ESP32-C3 DevKit is an entry-level development board equipped with either - an ESP32-C3-WROOM-02 or an ESP32-C3-MINI-1. - ESP32-C3-WROOM-02 and ESP32-C3-MINI-1 are SoMs based on the RISC-V ESP32-C3 CPU. - - Most of the I/O pins are broken out to the pin headers on both sides for easy - interfacing. Developers can either connect peripherals with jumper wires or - mount ESP32-C3 DevKit on a breadboard. - -ESP32-C3 Features -================= - The ESP32-C3 is an ultra-low-power and highly integrated SoC with a RISC-V - core and supports 2.4 GHz Wi-Fi and Bluetooth Low Energy. - - * Address Space - - 800 KB of internal memory address space accessed from the instruction bus - - 560 KB of internal memory address space accessed from the data bus - - 1016 KB of peripheral address space - - 8 MB of external memory virtual address space accessed from the instruction bus - - 8 MB of external memory virtual address space accessed from the data bus - - 480 KB of internal DMA address space - * Internal Memory - - 384 KB ROM - - 400 KB SRAM (16 KB can be configured as Cache) - - 8 KB of SRAM in RTC - * External Memory - - Up to 16 MB of external flash - * Peripherals - - 35 peripherals - * GDMA - - 7 modules are capable of DMA operations. - -ESP32-C3 Toolchain -================== - -The configurations provided are using a generic RISC-V toolchain to build ESP32-C3 projects. -It can be downloaded from: https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz - -Second stage bootloader and partition table -=========================================== - -The NuttX port for now relies on IDF's second stage bootloader to carry on some hardware -initializations. The binaries for the bootloader and the partition table can be found in -this repository: https://github.com/espressif/esp-nuttx-bootloader -That repository contains a dummy IDF project that's used to build the bootloader and -partition table, these are then presented as Github assets and can be downloaded -from: https://github.com/espressif/esp-nuttx-bootloader/releases -Download bootloader-esp32c3.bin and partition-table-esp32c3.bin and place them -in a folder, the path to this folder will be used later to program them. This -can be: "../esp-bins" - -Buttons and LEDs -================ - - Buttons - ------- - There are two buttons labeled Boot and RST. The RST button is not available - to software. It pulls the chip enable line that doubles as a reset line. - - The BOOT button is connected to IO9. On reset it is used as a strapping - pin to determine whether the chip boots normally or into the serial - bootloader. After reset, however, the BOOT button can be used for software - input. - - LEDs - ---- - There is one on-board LED that indicates the presence of power. - Another WS2812 LED is connected to GPIO8 and is available for software. - -Configurations -============== - - nsh - --- - - Basic configuration to run the NuttShell (nsh). - - gpio - ____ - - This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and - GPIO9 as an interrupt pin. - - At the nsh, we can turn the outputs on and off with the following: - nsh> gpio -o 1 /dev/gpout0 - nsh> gpio -o 1 /dev/gpout1 - - nsh> gpio -o 0 /dev/gpout0 - nsh> gpio -o 0 /dev/gpout1 - - We can use the interrupt pin to send a signal when the interrupt fires: - nsh> gpio -w 14 /dev/gpint2 - - The pin is configured as a rising edge interrupt, so after issuing the - above command, connect it to 3.3V. - - watchdog - -------- - - This configuration tests the watchdog timers. It includes the 2 MWDTS, - adds driver support, registers the WDTs as devices and includes the watchdog - example application. - - To test it, just run the following command: - - `nsh> wdog -i /dev/watchdogX` - - Where X ix the watchdog instance. - - watcher - ------- - - This configuration tests the watchdog timers in the capture mode. - It includes the 2 MWDTS, adds driver support, registers the WDTs as devices - and includes the watcher and watched example applications. - - To test it, just run the following command: - - ``` - nsh> watcher - nsh> watched - ``` - -Building and flashing -===================== - -First make sure that `esptool.py` is installed. This tool is used to convert -the ELF to a compatible ESP32 image and to flash the image into the board. -It can be installed with: `pip install esptool`. - -Configure the NUttX project: `./tools/configure.sh esp32c3-devkit:nsh` -If the project isn't clean, please run `make distclean` before configure.sh or -run configure.sh with -E option. -Run `make` to build the project. Note that the conversion mentioned above is -included in the build process. -The esptool.py command to flash all the binaries is `esptool.py --chip esp32c3 ---port /dev/ttyUSBXX --baud 921600 write_flash 0x0 bootloader.bin 0x8000 partition-table.bin 0x10000 nuttx.bin` -However, this is also included in the build process and we can use build and flash with: -`make download ESPTOOL_PORT=/dev/ttyUSBXX ESPTOOL_BINDIR=../esp-bins` -The "../esp-bins" path is the path to the folder containing the bootloader and the -partition table for the ESP32-C3 as explained above. -Note that this step is required only one time. Once the bootloader and partition -table are flashed, we don't need to flash them again. So subsequent builds -would just require: `make download ESPTOOL_PORT=/dev/ttyUSBXX` - diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig new file mode 100644 index 00000000000..fccb5b07206 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_ADC1=y +CONFIG_ESP32C3_ADC1_CHANNEL0=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=1 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/aes/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/aes/defconfig new file mode 100644 index 00000000000..ec0efd3582b --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/aes/defconfig @@ -0,0 +1,45 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_AES_ACCELERATOR=y +CONFIG_ESP32C3_AES_ACCELERATOR_TEST=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="esp32c3_aes_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/autopm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/autopm/defconfig new file mode 100644 index 00000000000..588fbc6fd9d --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/autopm/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32C3_AUTO_SLEEP=y +CONFIG_ESP32C3_WIFI=y +CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_NAME_MAX=48 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RAW_BINARY=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig new file mode 100644 index 00000000000..fb1bb178e80 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BTSAK=y +CONFIG_BUILTIN=y +CONFIG_DRIVERS_BLUETOOTH=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32C3_BLE=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_NAME_MAX=48 +CONFIG_NET_BLUETOOTH=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_SPINLOCK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WIRELESS=y +CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig index beecb824154..54bd3756cce 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig @@ -27,7 +27,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/dma/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/dma/defconfig new file mode 100644 index 00000000000..b43efaa3bb1 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/dma/defconfig @@ -0,0 +1,31 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_ESP32C3_DMA=y +CONFIG_ESP32C3_DMA_M2M_TEST=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="esp32c3_dma_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig new file mode 100644 index 00000000000..5301b4d11e4 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_EFUSE=y +CONFIG_ESP32C3_EFUSE=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/elf/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/elf/defconfig new file mode 100644 index 00000000000..78af327e199 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/elf/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=8192 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_USE_TEXT_HEAP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_STACKSIZE=8192 +CONFIG_EXECFUNCS_HAVE_SYMTAB=y +CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=8192 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=20 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2020 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=8192 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USERMAIN_STACKSIZE=8192 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig index e70b12cf75a..61adaf4cf21 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/module/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/module/defconfig new file mode 100644 index 00000000000..3aa26282964 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/module/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MODULE=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig index c9f134381e5..c89a3613823 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/oneshot/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/oneshot/defconfig index f8a0d84d421..afbb72f34c3 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/oneshot/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/oneshot/defconfig @@ -31,7 +31,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig index 5bb112d0940..6def6a02e77 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig @@ -25,7 +25,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig new file mode 100644 index 00000000000..4ad4a9828a2 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PM=y +CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=y +CONFIG_PM_GOVERNOR_GREEDY=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig new file mode 100644 index 00000000000..d45bc387680 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_LEDC=y +CONFIG_ESP32C3_LEDC_TIM0=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig index 988a7b59a07..339bc0b7c3d 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig new file mode 100644 index 00000000000..25de5922c35 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_ROMFS=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_ARCHROMFS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_ROMFSDEVNO=6 +CONFIG_NSH_ROMFSETC=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rsa/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rsa/defconfig new file mode 100644 index 00000000000..d234f2db181 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rsa/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_BIGNUM_ACCELERATOR=y +CONFIG_ESP32C3_BIGNUM_ACCELERATOR_TEST=y +CONFIG_ESP32C3_RSA_ACCELERATOR=y +CONFIG_ESP32C3_RSA_ACCELERATOR_TEST=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USERMAIN_STACKSIZE=4096 +CONFIG_USER_ENTRYPOINT="esp32c3_rsa_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig new file mode 100644 index 00000000000..f5be78b297a --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_RT_TIMER=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_RTC_NALARMS=2 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sha/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sha/defconfig new file mode 100644 index 00000000000..30b2bc37785 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sha/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_SHA_ACCELERATOR=y +CONFIG_ESP32C3_SHA_ACCELERATOR_TEST=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="esp32c3_sha_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sotest/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sotest/defconfig new file mode 100644 index 00000000000..baa25fb6414 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sotest/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_OS_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_SOTEST=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_DLFCN=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig index 5386f3efefe..23546b3deac 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig @@ -29,7 +29,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_MTD_SMART=y CONFIG_NAME_MAX=48 CONFIG_NSH_ARCHINIT=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig index 942e6734163..dc4cb5efb69 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig @@ -30,9 +30,9 @@ CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32C3_MTD_OFFSET=0x110000 CONFIG_ESP32C3_MTD_SIZE=0xf0000 CONFIG_ESP32C3_SPIFLASH=y +CONFIG_ESP32C3_WIFI=y CONFIG_ESP32C3_WIFI_SAVE_PARAM=y CONFIG_ESP32C3_WIFI_STATION_SOFTAP_COEXISTENCE=y -CONFIG_ESP32C3_WIRELESS=y CONFIG_EXAMPLES_DHCPD=y CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y @@ -42,7 +42,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_LATEINIT=y @@ -53,7 +52,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ETH_PKTSIZE=1514 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig new file mode 100644 index 00000000000..9a2f44b6e91 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_TICKLESS=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/timer/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/timer/defconfig index 6d624c910fc..ac20f19cdd6 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/timer/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/timer/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/uid/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/uid/defconfig new file mode 100644 index 00000000000..caea36c8291 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/uid/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_UNIQUEID=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/wapi/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/wapi/defconfig index 3fb338c699a..acff4338fdd 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/wapi/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/wapi/defconfig @@ -21,7 +21,7 @@ CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32C3_WIRELESS=y +CONFIG_ESP32C3_WIFI=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y @@ -37,7 +37,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ETH_PKTSIZE=1514 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig index 38972552e94..69007d611f4 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig index a15584f0a03..ab4ab67cc2b 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig @@ -30,7 +30,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/include/nsh_romfsimg.h b/boards/risc-v/esp32c3/esp32c3-devkit/include/nsh_romfsimg.h new file mode 100644 index 00000000000..6b293e9f3b5 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/include/nsh_romfsimg.h @@ -0,0 +1,25 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-devkit/include/nsh_romfsimg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_NSH_ROMFSIMG_H +#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_NSH_ROMFSIMG_H +extern const unsigned char romfs_img[]; +extern const unsigned int romfs_img_len; +#endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs index dac80a8cd8c..a40663c3f66 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs +++ b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs @@ -60,6 +60,29 @@ NXFLATLDFLAGS1 = -r -d -warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections LDNXFLATFLAGS = -e main -s 2048 +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) + +LDMODULEFLAGS = -melf32lriscv -r -e module_initialize +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -fno-common +CXXELFFLAGS = $(CXXFLAGS) -fno-common + +LDELFFLAGS = -melf32lriscv -r -e main +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld}" +else + LDELFFLAGS += -T $(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld +endif + LDFLAGS += -nostartfiles -nodefaultlibs ifeq ($(CONFIG_CYGWIN_WINTOOL),y) diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.ld b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.ld index fa3b073743a..fddd0dd3019 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.ld +++ b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.ld @@ -223,7 +223,7 @@ SECTIONS { . = ALIGN(4); *(.rtc.literal .rtc.text) - } >rtc_iram_seg + } >rtc_seg /* This section is required to skip rtc.text area because the text and * data segments reflect the same address space on different buses. @@ -232,7 +232,14 @@ SECTIONS .rtc.dummy : { . = SIZEOF(.rtc.text); - } >rtc_iram_seg + } >rtc_seg + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_seg /* RTC data section holds RTC wake stub data/rodata. */ @@ -240,6 +247,11 @@ SECTIONS { *(.rtc.data) *(.rtc.rodata) - } >rtc_iram_seg + + /* Whatever is left from the RTC memory is used as a special heap. */ + + _srtcheap = ABSOLUTE(.); + + } >rtc_seg } diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.template.ld b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.template.ld index 4b8a5c3c87a..5923840f626 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.template.ld +++ b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.template.ld @@ -66,7 +66,7 @@ MEMORY * constraint that (paddr % 64KB == vaddr % 64KB). */ - iram0_2_seg (RX) : org = 0x42000020, len = 0x8000000 - 0x20 + irom0_0_seg (RX) : org = 0x42000020, len = 0x8000000 - 0x20 /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */ @@ -76,10 +76,9 @@ MEMORY drom0_0_seg (R) : org = 0x3c000020, len = 0x8000000 - 0x20 - /* RTC fast memory (executable). Persists over deep sleep. */ - - rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 + /* RTC fast memory. Persists over deep sleep. */ + rtc_seg(RWX) : org = 0x50000000, len = 0x2000 } #if CONFIG_ESP32C3_DEVKIT_RUN_IRAM @@ -87,6 +86,9 @@ MEMORY REGION_ALIAS("default_code_seg", iram0_0_seg); #else REGION_ALIAS("default_rodata_seg", drom0_0_seg); - REGION_ALIAS("default_code_seg", iram0_2_seg); + REGION_ALIAS("default_code_seg", irom0_0_seg); #endif /* CONFIG_ESP32C3_DEVKIT_RUN_IRAM */ +/* Mark the end of the RTC heap (top of the RTC region) */ + +_ertcheap = 0x50001fff; diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_rom.ld b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_rom.ld index c4cc218cf2e..f282eef8bff 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_rom.ld +++ b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_rom.ld @@ -296,7 +296,7 @@ PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004c4 ); PROVIDE( ROM_Boot_Cache_Init = 0x400004c8 ); PROVIDE( Cache_Invalidate_ICache_Items = 0x400004cc ); PROVIDE( Cache_Op_Addr = 0x400004d0 ); -PROVIDE( Cache_Invalidate_Addr = 0x400004d4 ); +PROVIDE( cache_invalidate_addr = 0x400004d4 ); PROVIDE( Cache_Invalidate_ICache_All = 0x400004d8 ); PROVIDE( Cache_Mask_All = 0x400004dc ); PROVIDE( Cache_UnMask_Dram0 = 0x400004e0 ); @@ -316,8 +316,8 @@ PROVIDE( Cache_Lock_Addr = 0x40000514 ); PROVIDE( Cache_Unlock_Addr = 0x40000518 ); PROVIDE( Cache_Disable_ICache = 0x4000051c ); PROVIDE( Cache_Enable_ICache = 0x40000520 ); -PROVIDE( Cache_Suspend_ICache = 0x40000524 ); -PROVIDE( Cache_Resume_ICache = 0x40000528 ); +PROVIDE( cache_suspend_icache = 0x40000524 ); +PROVIDE( cache_resume_icache = 0x40000528 ); PROVIDE( Cache_Freeze_ICache_Enable = 0x4000052c ); PROVIDE( Cache_Freeze_ICache_Disable = 0x40000530 ); PROVIDE( Cache_Pms_Lock = 0x40000534 ); @@ -1815,9 +1815,9 @@ rom_get_i2c_read_mask = 0x40001948; rom_get_pwctrl_correct = 0x4000194c; rom_get_rf_gain_qdb = 0x40001950; rom_i2c_readreg = 0x40001954; -rom_i2c_readreg_Mask = 0x40001958; +rom_i2c_readreg_mask = 0x40001958; rom_i2c_writereg = 0x4000195c; -rom_i2c_writereg_Mask = 0x40001960; +rom_i2c_writereg_mask = 0x40001960; rom_index_to_txbbgain = 0x40001964; rom_iq_est_disable = 0x40001968; rom_iq_est_enable = 0x4000196c; diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/.gitignore b/boards/risc-v/esp32c3/esp32c3-devkit/src/.gitignore new file mode 100644 index 00000000000..1baf09ba3ae --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/.gitignore @@ -0,0 +1 @@ +/etctmp* diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile b/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile index f91d70996d3..661da923f46 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile @@ -50,6 +50,10 @@ ifeq ($(CONFIG_SPI_DRIVER),y) CSRCS += esp32c3_board_spidev.c endif +ifeq ($(CONFIG_SPI_SLAVE_DRIVER),y) +CSRCS += esp32c3_board_spislavedev.c +endif + ifeq ($(CONFIG_I2C_DRIVER),y) CSRCS += esp32c3_i2c.c endif @@ -66,6 +70,29 @@ ifeq ($(CONFIG_ONESHOT),y) CSRCS += esp32c3_oneshot.c endif +ifeq ($(CONFIG_PWM),y) +CSRCS += esp32c3_ledc.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += esp32c3_adc.c +endif + +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) +CSRCS += esp32c3_ioctl.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += esp32c3_uid.c +endif + +ifeq ($(CONFIG_NSH_ROMFSETC),y) +ifneq ($(CONFIG_NSH_CUSTOMROMFS),y) + RCSRCS = etc/init.d/rcS + RCRAWS = etc/group etc/passwd +endif +endif + SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32c3.template.ld SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32c3_out.ld diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/README.txt b/boards/risc-v/esp32c3/esp32c3-devkit/src/README.txt new file mode 100644 index 00000000000..209f760b46a --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/README.txt @@ -0,0 +1,120 @@ +README +====== + + Overview + -------- + This directory contains logic to support a custom ROMFS start-up script. + This startup script is used by by the NSH when it starts provided that + CONFIG_NSH_ARCHROMFS=y. The script provides a ROMFS volume that will be + mounted at /etc and will look like this at run-time: + + NuttShell (NSH) NuttX-10.1.0-RC1 + MOTD: username=admin password=Administrator + nsh> ls -Rl /etc + /etc: + dr-xr-xr-x 0 . + -r--r--r-- 20 group + dr-xr-xr-x 0 init.d/ + -r--r--r-- 35 passwd + /etc/init.d: + dr-xr-xr-x 0 .. + -r--r--r-- 110 rcS + nsh> + + /etc/init.d/rcS is the start-up script; /etc/passwd is a the password + file. It supports a single user: + + USERNAME: admin + PASSWORD: Administrator + + nsh> cat /etc/passwd + admin:8Tv+Hbmr3pLddSjtzL0kwC:0:0:/ + + The encrypted passwords in the provided passwd file are only valid if the + TEA key is set to: 012345678 9abcdef0 012345678 9abcdef0. Changes to either + the key or the password word will require regeneration of the nsh_romfimg.h + header file. + + The format of the password file is: + + user:x:uid:gid:home + + Where: + user: User name + x: Encrypted password + uid: User ID (0 for now) + gid: Group ID (0 for now) + home: Login directory (/ for now) + + /etc/group is a group file. It is not currently used. + + nsh> cat /etc/group + root:*:0:root,admin + + The format of the group file is: + + group:x:gid:users + + Where: + group: The group name + x: Group password + gid: Group ID + users: A comma separated list of members of the group + + Updating the ROMFS File System + ------------------------------ + The content on the nsh_romfsimg.h header file is generated from a sample + directory structure. You can directly modify files under etc/ folder, + The build system will regenerate nsh_romfsimg.h automatically. + + See the esp32c3-devkit/nsh configuration for an example of the use of this file + system. + + Replacing the Password File + --------------------------- + The esp32c3-devkit/nsh configuration can also be used to create a new password file. + First, make these configuration changes: + + 1. Disable logins + + - CONFIG_NSH_CONSOLE_LOGIN=y + + # CONFIG_NSH_CONSOLE_LOGIN is not set + # CONFIG_NSH_TELNET_LOGIN is not set + + 2. Move the password file to a write-able file system: + + - CONFIG_FSUTILS_PASSWD_PATH="/etc/passwd" + + CONFIG_FSUTILS_PASSWD_PATH="/tmp/passwd" + + 3. make the password file modifiable + + - CONFIG_FSUTILS_PASSWD_READONLY=y + # CONFIG_FSUTILS_PASSWD_READONLY is not set + + Now rebuild the simulation. No login should be required to enter the + shell and you should find the 'useradd', 'userdel', and 'passwd' commands + available in the help summary, provided that they are enabled. Make + certain that the 'useradd' command is not disabled: + + # CONFIG_NSH_DISABLE_USERADD is not set + + Use the NSH 'useradd' command to add new uses with new user passwords like: + + nsh> useradd + + Do this as many times as you would like. Each time that you do this a new + entry with an encrypted password will be added to the passwd file at + /tmp/passwd. You can see the passwd file like: + + nsh> cat /tmp/passwd + + When you are finished, you can simply copy the /tmp/passwd content from the + 'cat' command and paste it into an editor. Make sure to remove any + carriage returns that may have ended up on the file if you are using + Windows. + + Then recreate the nsh_romfsimg.h file as described above. In step 2, + simply replace the old /etc/passwd file with the one in your editor. + When you are finished, the new passwd file will be in the ROMFS file + system at the path /etc/passwd. When you restore the original NSH + sim configuration, these are the passwords that will be used. diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h index c55776badf1..de523f7679d 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h @@ -114,6 +114,25 @@ int board_wdt_init(void); int board_spidev_initialize(int bus); #endif +/**************************************************************************** + * Name: board_spislavedev_initialize + * + * Description: + * Initialize SPI Slave driver and register the /dev/spislv device. + * + * Input Parameters: + * bus - The SPI bus number, used to build the device path as /dev/spislvN + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_SLAVE +int board_spislavedev_initialize(int bus); +#endif + /**************************************************************************** * Name: board_i2c_init * @@ -181,5 +200,51 @@ int board_bmp180_initialize(int devno, int busno); int esp32c3_spiflash_init(void); #endif +/**************************************************************************** + * Name: esp32c3_spiflash_encrypt_test + * + * Description: + * Test ESP32-C3 SPI Flash driver read/write with encryption. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPIFLASH_ENCRYPTION_TEST +void esp32c3_spiflash_encrypt_test(void); +#endif + +/**************************************************************************** + * Name: esp32c3_ledc_setup + * + * Description: + * Initialize LEDC PWM and register the PWM device. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_LEDC +int esp32c3_pwm_setup(void); +#endif + +/**************************************************************************** + * Name: board_adc_init + * + * Description: + * Configure the ADC driver. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ADC +int board_adc_init(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_SRC_ESP32C3_DEVKIT_H */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_adc.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_adc.c new file mode 100644 index 00000000000..710e0b1e03a --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_adc.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_adc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp32c3_adc.h" + +#include "esp32c3-devkit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_adc_init + * + * Description: + * Configure the ADC driver. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_adc_init(void) +{ + int ret; + struct adc_dev_s *adc; + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL0 + adc = esp32c3_adc_init(0); + if (!adc) + { + syslog(LOG_ERR, "ERROR: Failed to get ADC channel 0 dev\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: adc_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL1 + adc = esp32c3_adc_init(1); + if (!adc) + { + syslog(LOG_ERR, "ERROR: Failed to get ADC channel 1 dev\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: adc_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL2 + adc = esp32c3_adc_init(2); + if (!adc) + { + syslog(LOG_ERR, "ERROR: Failed to get ADC channel 2 dev\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc2" */ + + ret = adc_register("/dev/adc2", adc); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: adc_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL3 + adc = esp32c3_adc_init(3); + if (!adc) + { + syslog(LOG_ERR, "ERROR: Failed to get ADC channel 3 dev\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc3" */ + + ret = adc_register("/dev/adc3", adc); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: adc_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESP32C3_ADC1_CHANNEL4 + adc = esp32c3_adc_init(4); + if (!adc) + { + syslog(LOG_ERR, "ERROR: Failed to get ADC channel 4 dev\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc4" */ + + ret = adc_register("/dev/adc4", adc); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: adc_register failed: %d\n", ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bmp180.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bmp180.c index 5343f91ff58..b8532b96c17 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bmp180.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bmp180.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_board_spislavedev.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_board_spislavedev.c new file mode 100644 index 00000000000..69bf48e60ce --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_board_spislavedev.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_board_spislavedev.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "esp32c3_spi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spislavedev_initialize + * + * Description: + * Initialize SPI Slave driver and register the /dev/spislv device. + * + * Input Parameters: + * bus - The SPI bus number, used to build the device path as /dev/spislvN + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_spislavedev_initialize(int bus) +{ + int ret; + + FAR struct spi_slave_ctrlr_s *ctrlr; + + spiinfo("Initializing /dev/spislv%d...\n", bus); + + /* Initialize SPI Slave controller device */ + + ctrlr = esp32c3_spislave_ctrlr_initialize(bus); + if (ctrlr == NULL) + { + spierr("Failed to initialize SPI%d as slave.\n", bus); + return -ENODEV; + } + + ret = spi_slave_register(ctrlr, bus); + if (ret < 0) + { + spierr("Failed to register /dev/spislv%d: %d\n", bus, ret); + + esp32c3_spislave_ctrlr_uninitialize(ctrlr); + } + + return ret; +} diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c index e97f7024e5d..d008b76b116 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c @@ -22,6 +22,8 @@ * Included Files ****************************************************************************/ +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c index e914603dbd8..320753fdca9 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c @@ -42,14 +42,35 @@ #include "esp32c3_partition.h" #include "esp32c3-devkit.h" -#ifdef CONFIG_SPI_DRIVER +#ifdef CONFIG_SPI # include "esp32c3_spi.h" #endif +#ifdef CONFIG_ESP32C3_RT_TIMER +# include "esp32c3_rt_timer.h" +#endif + #ifdef CONFIG_TIMER # include "esp32c3_tim_lowerhalf.h" #endif +#include "esp32c3_rtc.h" +#ifdef CONFIG_ESP32C3_EFUSE +# include "esp32c3_efuse.h" +#endif + +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR +# include "esp32c3_sha.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include "esp32c3_rtc_lowerhalf.h" +#endif + +#ifdef CONFIG_ESP32C3_BLE +# include "esp32c3_ble.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -116,6 +137,23 @@ int esp32c3_bringup(void) { int ret; +#if defined(CONFIG_ESP32C3_EFUSE) + ret = esp32c3_efuse_initialize("/dev/efuse"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to init EFUSE: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR + ret = esp32c3_sha_init(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize SHA: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -138,6 +176,11 @@ int esp32c3_bringup(void) #endif #ifdef CONFIG_ESP32C3_SPIFLASH + +# ifdef CONFIG_ESP32C3_SPIFLASH_ENCRYPTION_TEST + esp32c3_spiflash_encrypt_test(); +# endif + ret = esp32c3_spiflash_init(); if (ret) { @@ -174,6 +217,15 @@ int esp32c3_bringup(void) } #endif +#if defined(CONFIG_SPI_SLAVE_DRIVER) && defined(CONFIG_ESP32C3_SPI2) + ret = board_spislavedev_initialize(ESP32C3_SPI2); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SPI%d Slave driver: %d\n", + ESP32C3_SPI2, ret); + } +#endif + #if defined(CONFIG_I2C_DRIVER) /* Configure I2C peripheral interfaces */ @@ -250,8 +302,37 @@ int esp32c3_bringup(void) #endif /* CONFIG_ONESHOT */ +#ifdef CONFIG_ESP32C3_RT_TIMER + ret = esp32c3_rt_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); + return ret; + } +#endif + #ifdef CONFIG_ESP32C3_WIRELESS +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + ret = esp32c3_wifi_bt_coexist_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize Wi-Fi and BT coexist\n"); + return ret; + } +#endif + +#ifdef CONFIG_ESP32C3_BLE + ret = esp32c3_ble_initialize(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize BLE\n"); + return ret; + } +#endif + +#ifdef CONFIG_ESP32C3_WIFI + #ifdef CONFIG_ESP32C3_WIFI_SAVE_PARAM ret = esp32c3_init_wifi_storage(); if (ret) @@ -281,6 +362,36 @@ int esp32c3_bringup(void) #endif #endif +#endif + +#endif /* CONFIG_ESP32C3_WIRELESS */ + +#ifdef CONFIG_ESP32C3_LEDC + ret = esp32c3_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp32c3_pwm_setup() failed: %d\n", ret); + } +#endif /* CONFIG_ESP32C3_LEDC */ + +#ifdef CONFIG_ESP32C3_ADC + ret = board_adc_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: board_adc_init() failed: %d\n", ret); + return ret; + } +#endif /* CONFIG_ESP32C3_ADC */ + +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the ESP32-C3 RTC driver */ + + ret = esp32c3_rtc_driverinit(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); + } #endif /* If we got here then perhaps not all initialization was successful, but diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ioctl.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ioctl.c new file mode 100644 index 00000000000..54579a8c3a7 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ioctl.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ioctl.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#ifdef CONFIG_BOARDCTL_IOCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ioctl + * + * Description: + * The "landing site" for much of the boardctl() interface. Generic board- + * control functions invoked via ioctl() get routed through here. + * + * Since we don't do anything unusual at the moment, this function + * accomplishes nothing except avoid a missing-function linker error if + * CONFIG_BOARDCTL_IOCTL is selected. + * + * Input Parameters: + * cmd - IOCTL command being requested. + * arg - Arguments for the IOCTL. + * + * Returned Value: + * we don't yet support any boardctl IOCTLs. This function always returns + * -ENOTTY which is the standard IOCTL return value when a command is not + * supported + * + ****************************************************************************/ + +int board_ioctl(unsigned int cmd, uintptr_t arg) +{ + switch (cmd) + { + default: + return -ENOTTY; + } + + return OK; +} + +#endif /* CONFIG_BOARDCTL_IOCTL */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c new file mode 100644 index 00000000000..5771aeb85f6 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "esp32c3_ledc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_pwm_setup + * + * Description: + * Initialize LEDC PWM and register the PWM device. + * + ****************************************************************************/ + +int esp32c3_pwm_setup(void) +{ + int ret; + struct pwm_lowerhalf_s *pwm; + +#ifdef CONFIG_ESP32C3_LEDC_TIM0 + pwm = esp32c3_ledc_init(0); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 0 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESP32C3_LEDC_TIM1 + pwm = esp32c3_ledc_init(1); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 1 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm1" */ + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESP32C3_LEDC_TIM2 + pwm = esp32c3_ledc_init(2); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 2 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm2" */ + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + + return OK; +} + diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_spiflash.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_spiflash.c index ea7f1df324a..e88e99d7b98 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_spiflash.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_spiflash.c @@ -26,9 +26,11 @@ #include +#include "inttypes.h" #include #include #include +#include #include #include @@ -40,6 +42,14 @@ #include "esp32c3_spiflash.h" #include "esp32c3-devkit.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_MTD_PATH "/dev/esp32c3flash" + +#define ESP32C3_FS_MOUNT_PT CONFIG_ESP32C3_SPIFLASH_FS_MOUNT_PT + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -87,6 +97,27 @@ int esp32c3_spiflash_init(void) return ret; } +#elif defined (CONFIG_ESP32C3_SPIFLASH_LITTLEFS) + ret = register_mtddriver(ESP32C3_MTD_PATH, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Register MTD failed: %d\n", ret); + return ret; + } + + ret = mount(ESP32C3_MTD_PATH, ESP32C3_FS_MOUNT_PT, + "littlefs", 0, NULL); + if (ret < 0) + { + ret = mount(ESP32C3_MTD_PATH, ESP32C3_FS_MOUNT_PT, + "littlefs", 0, "forceformat"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", + errno); + return ret; + } + } #else ret = register_mtddriver("/dev/esp32c3flash", mtd, 0755, NULL); if (ret < 0) @@ -126,8 +157,8 @@ void esp32c3_spiflash_encrypt_test(void) uint32_t erase_nblocks; uint32_t rw_block; uint32_t rw_nblocks; - struct mtd_dev_s *mtd = esp32c3_spiflash_get_mtd(); - struct mtd_dev_s *enc_mtd = esp32c3_spiflash_encrypt_get_mtd(); + struct mtd_dev_s *mtd = esp32c3_spiflash_mtd(); + struct mtd_dev_s *enc_mtd = esp32c3_spiflash_encrypt_mtd(); const uint32_t address = CONFIG_ESP32C3_SPIFLASH_TEST_ADDRESS; const uint32_t size = 4096; @@ -142,14 +173,14 @@ void esp32c3_spiflash_encrypt_test(void) wbuf = kmm_malloc(size); if (!wbuf) { - ferr("ERROR: Failed to alloc %d heap\n", size); + ferr("ERROR: Failed to alloc %" PRIu32 " heap\n", size); DEBUGASSERT(0); } rbuf = kmm_malloc(size); if (!rbuf) { - ferr("ERROR: Failed to alloc %d heap\n", size); + ferr("ERROR: Failed to alloc %" PRIu32 " heap\n", size); DEBUGASSERT(0); } diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_uid.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_uid.c new file mode 100644 index 00000000000..f01bed46c01 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_uid.c @@ -0,0 +1,49 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_uid.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "esp32c3_uid.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + esp32c3_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/group b/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/group new file mode 100644 index 00000000000..1eca6970c9d --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/group @@ -0,0 +1 @@ +root:*:0:root,admin diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rcS b/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rcS new file mode 100644 index 00000000000..964d268c678 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rcS @@ -0,0 +1,36 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rcS + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +#define CONCAT_(x, y) x##y +#define CONCAT(x, y) CONCAT_(x, y) + +#ifdef CONFIG_NSH_ROMFSETC +#ifdef CONFIG_FS_FAT + +/* Create a RAMDISK and mount it at /tmp */ + +mkrd -m CONFIG_NSH_FATDEVNO -s CONFIG_NSH_FATSECTSIZE CONFIG_NSH_FATNSECTORS +mkfatfs CONCAT(/dev/ram, CONFIG_NSH_FATDEVNO) +mount -t vfat CONCAT(/dev/ram, CONFIG_NSH_FATDEVNO) CONFIG_NSH_FATMOUNTPT + +#endif /* CONFIG_FS_FAT */ +#endif /* CONFIG_NSH_ROMFSETC */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/passwd b/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/passwd new file mode 100644 index 00000000000..d93ef03bb1a --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/passwd @@ -0,0 +1 @@ +admin:8Tv+Hbmr3pLddSjtzL0kwC:0:0:/ diff --git a/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig index 07f3f1a88e0..f41ec840fe3 100644 --- a/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig +++ b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig @@ -43,7 +43,6 @@ CONFIG_INPUT_BUTTONS_NPOLLWAITERS=1 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_MM_SMALL=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y diff --git a/boards/risc-v/fe310/hifive1-revb/src/fe310_bringup.c b/boards/risc-v/fe310/hifive1-revb/src/fe310_bringup.c index 27e3e88b639..02cd3a2699a 100644 --- a/boards/risc-v/fe310/hifive1-revb/src/fe310_bringup.c +++ b/boards/risc-v/fe310/hifive1-revb/src/fe310_bringup.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/risc-v/fe310/hifive1-revb/src/fe310_buttons.c b/boards/risc-v/fe310/hifive1-revb/src/fe310_buttons.c index 6a0e8c90e9d..3993bc0b462 100644 --- a/boards/risc-v/fe310/hifive1-revb/src/fe310_buttons.c +++ b/boards/risc-v/fe310/hifive1-revb/src/fe310_buttons.c @@ -28,7 +28,8 @@ #include #include -#include +#include +#include #include #include "fe310_gpio.h" diff --git a/boards/risc-v/k210/maix-bit/README-qemu.txt b/boards/risc-v/k210/maix-bit/README-qemu.txt index 11ab5cc2ee8..c160ae2c631 100644 --- a/boards/risc-v/k210/maix-bit/README-qemu.txt +++ b/boards/risc-v/k210/maix-bit/README-qemu.txt @@ -21,7 +21,6 @@ +CONFIG_K210_WITH_QEMU=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y - CONFIG_MAX_TASKS=64 4. Configure and build NuttX diff --git a/boards/risc-v/k210/maix-bit/README.txt b/boards/risc-v/k210/maix-bit/README.txt index e9b43d9cb8f..8b158da36c1 100644 --- a/boards/risc-v/k210/maix-bit/README.txt +++ b/boards/risc-v/k210/maix-bit/README.txt @@ -1,6 +1,7 @@ 1. Download and install toolchain and openocd-k210 $ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz + $ export PATH=$PATH:/$TOOL_CHAIN_PATH/bin 2. Build openocd-k210 @@ -11,8 +12,8 @@ 3. Configure and build NuttX $ mkdir ./nuttx; cd ./nuttx - $ git clone https://github.com/apache/incubator-nuttx.git - $ git clone https://github.com/apache/incubator-nuttx-apps.git + $ git clone https://github.com/apache/incubator-nuttx.git nuttx + $ git clone https://github.com/apache/incubator-nuttx-apps.git apps $ cd nuttx $ make distclean $ ./tools/configure.sh maix-bit:nsh diff --git a/boards/risc-v/k210/maix-bit/configs/elf/defconfig b/boards/risc-v/k210/maix-bit/configs/elf/defconfig index 206dd57adee..b49295ade27 100644 --- a/boards/risc-v/k210/maix-bit/configs/elf/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/elf/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=46000 CONFIG_BUILTIN=y CONFIG_DEBUG_FULLOPT=y @@ -32,7 +33,6 @@ CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_PATH_INITIAL="/mnt/romfs" CONFIG_PIPES=y CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=3072 diff --git a/boards/risc-v/k210/maix-bit/configs/knsh/defconfig b/boards/risc-v/k210/maix-bit/configs/knsh/defconfig index bf09a7db53d..c560913f1b3 100644 --- a/boards/risc-v/k210/maix-bit/configs/knsh/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/knsh/defconfig @@ -27,7 +27,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_MM_KERNEL_HEAPSIZE=524288 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y @@ -46,7 +45,7 @@ CONFIG_START_DAY=12 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2020 CONFIG_SYSTEM_NSH=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=20 CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y diff --git a/boards/risc-v/k210/maix-bit/configs/knsh_smp/defconfig b/boards/risc-v/k210/maix-bit/configs/knsh_smp/defconfig index 67debe2592c..11d4a845d4d 100644 --- a/boards/risc-v/k210/maix-bit/configs/knsh_smp/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/knsh_smp/defconfig @@ -27,7 +27,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_MM_KERNEL_HEAPSIZE=524288 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y @@ -51,7 +50,7 @@ CONFIG_START_YEAR=2021 CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TASKSET=y -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=20 CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y diff --git a/boards/risc-v/k210/maix-bit/configs/kostest/defconfig b/boards/risc-v/k210/maix-bit/configs/kostest/defconfig index f120882b494..b2aa9099439 100644 --- a/boards/risc-v/k210/maix-bit/configs/kostest/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/kostest/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_MM_KERNEL_HEAPSIZE=524288 CONFIG_NUTTX_USERSPACE=0x80100000 CONFIG_PASS1_BUILDIR="boards/risc-v/k210/maix-bit/kernel" @@ -42,7 +41,7 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=14 CONFIG_START_MONTH=2 CONFIG_START_YEAR=2020 -CONFIG_SYS_RESERVED=8 +CONFIG_SYS_RESERVED=9 CONFIG_TASK_NAME_SIZE=20 CONFIG_TESTING_OSTEST=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/k210/maix-bit/configs/module/defconfig b/boards/risc-v/k210/maix-bit/configs/module/defconfig index 624b79a1f3f..3f19329e1e4 100644 --- a/boards/risc-v/k210/maix-bit/configs/module/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/module/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=46000 CONFIG_BUILTIN=y CONFIG_DEBUG_FULLOPT=y @@ -33,7 +34,6 @@ CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_MODULE=y CONFIG_PATH_INITIAL="/mnt/romfs" CONFIG_PIPES=y diff --git a/boards/risc-v/k210/maix-bit/configs/nsh/defconfig b/boards/risc-v/k210/maix-bit/configs/nsh/defconfig index e5f8b97daa0..081a0d800c0 100644 --- a/boards/risc-v/k210/maix-bit/configs/nsh/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/nsh/defconfig @@ -27,7 +27,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/risc-v/k210/maix-bit/configs/posix_spawn/defconfig b/boards/risc-v/k210/maix-bit/configs/posix_spawn/defconfig index 2d5c6d574d2..ebea6b48e75 100644 --- a/boards/risc-v/k210/maix-bit/configs/posix_spawn/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/posix_spawn/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=46000 CONFIG_BUILTIN=y CONFIG_DEBUG_FULLOPT=y @@ -31,7 +32,6 @@ CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y CONFIG_LIB_BOARDCTL=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_PATH_INITIAL="/mnt/romfs" CONFIG_PIPES=y CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 diff --git a/boards/risc-v/k210/maix-bit/configs/smp/defconfig b/boards/risc-v/k210/maix-bit/configs/smp/defconfig index 13320973e53..674bba8aa53 100644 --- a/boards/risc-v/k210/maix-bit/configs/smp/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/smp/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/risc-v/k210/maix-bit/configs/smp2/defconfig b/boards/risc-v/k210/maix-bit/configs/smp2/defconfig index 74897d1d3d9..2d198857c4a 100644 --- a/boards/risc-v/k210/maix-bit/configs/smp2/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/smp2/defconfig @@ -29,7 +29,6 @@ CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y diff --git a/boards/risc-v/k210/maix-bit/kernel/k210_userspace.c b/boards/risc-v/k210/maix-bit/kernel/k210_userspace.c index 09335202b36..f7ff8e5dfd6 100644 --- a/boards/risc-v/k210/maix-bit/kernel/k210_userspace.c +++ b/boards/risc-v/k210/maix-bit/kernel/k210_userspace.c @@ -95,9 +95,6 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) = /* Task/thread startup routines */ .task_startup = nxtask_startup, -#ifndef CONFIG_DISABLE_PTHREAD - .pthread_startup = pthread_startup, -#endif /* Signal handler trampoline */ diff --git a/boards/risc-v/k210/maix-bit/src/k210_bringup.c b/boards/risc-v/k210/maix-bit/src/k210_bringup.c index 3145a00e55f..2dc3d09c7b6 100644 --- a/boards/risc-v/k210/maix-bit/src/k210_bringup.c +++ b/boards/risc-v/k210/maix-bit/src/k210_bringup.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/risc-v/litex/arty_a7/configs/nsh/defconfig b/boards/risc-v/litex/arty_a7/configs/nsh/defconfig index 26d03ea8c96..25454763637 100644 --- a/boards/risc-v/litex/arty_a7/configs/nsh/defconfig +++ b/boards/risc-v/litex/arty_a7/configs/nsh/defconfig @@ -32,7 +32,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/risc-v/litex/arty_a7/src/litex_bringup.c b/boards/risc-v/litex/arty_a7/src/litex_bringup.c index a8abf06c484..a1f8b1ab942 100644 --- a/boards/risc-v/litex/arty_a7/src/litex_bringup.c +++ b/boards/risc-v/litex/arty_a7/src/litex_bringup.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/risc-v/mpfs/icicle/Kconfig b/boards/risc-v/mpfs/icicle/Kconfig new file mode 100755 index 00000000000..6dba7cd4c95 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_ICICLE_MPFS + +endif diff --git a/boards/risc-v/mpfs/icicle/configs/nsh/defconfig b/boards/risc-v/mpfs/icicle/configs/nsh/defconfig new file mode 100644 index 00000000000..87dfc3387cb --- /dev/null +++ b/boards/risc-v/mpfs/icicle/configs/nsh/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="icicle" +CONFIG_ARCH_BOARD_ICICLE_MPFS=y +CONFIG_ARCH_CHIP="mpfs" +CONFIG_ARCH_CHIP_MPFS=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=54000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WARN=y +CONFIG_DEV_ZERO=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIB_HOSTNAME="icicle" +CONFIG_MEMSET_64BIT=y +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MPFS_ENABLE_DPFPU=y +CONFIG_MPFS_UART1=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_LINELEN=160 +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=1048576 +CONFIG_RAM_START=0x80200000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_NPOLLWAITERS=2 +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2021 +CONFIG_SYSLOG_COLOR_OUTPUT=y +CONFIG_SYSTEM_CLE_CMD_HISTORY=y +CONFIG_SYSTEM_COLOR_CLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TIME64=y +CONFIG_TASK_NAME_SIZE=20 +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_FPUSIZE=264 +CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USERMAIN_STACKSIZE=3072 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/mpfs/icicle/include/board.h b/boards/risc-v/mpfs/icicle/include/board.h new file mode 100755 index 00000000000..680915d27e7 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/include/board.h @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ICICLE_MPFS_INCLUDE_BOARD_H +#define __BOARDS_RISCV_ICICLE_MPFS_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include "mpfs_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking TODO: */ + +#define MPFS_MSS_EXT_SGMII_REF_CLK (125000000UL) +#define MPFS_MSS_COREPLEX_CPU_CLK (600000000UL) +#define MPFS_MSS_SYSTEM_CLK (600000000UL) +#define MPFS_MSS_RTC_TOGGLE_CLK (1000000UL) +#define MPFS_MSS_AXI_CLK (300000000UL) +#define MPFS_MSS_APB_AHB_CLK (150000000UL) + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +#define BOARD_LED_ORANGE1 BOARD_LED1 +#define BOARD_LED_ORANGE2 BOARD_LED2 +#define BOARD_LED_RED1 BOARD_LED3 +#define BOARD_LED_RED2 BOARD_LED4 + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED3 + LED1 */ +#define LED_SIGNAL 5 /* LED3 + LED2 */ +#define LED_ASSERTION 6 /* LED3 + LED2 + LED1 */ +#define LED_PANIC 7 /* LED4 */ + +/* Button definitions *******************************************************/ + +/* The Icicle supports 3 buttons: */ + +#define BUTTON_USER1 0 +#define BUTTON_USER2 1 +#define BUTTON_USER3 2 +#define NUM_BUTTONS 3 +#define BUTTON_USER1_BIT (1 << BUTTON_USER1) +#define BUTTON_USER2_BIT (1 << BUTTON_USER2) +#define BUTTON_USER3_BIT (1 << BUTTON_USER3) + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_boardinitialize + ****************************************************************************/ + +void mpfs_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ICICLE_MPFS_INCLUDE_BOARD_H */ diff --git a/boards/risc-v/mpfs/icicle/kernel/Makefile b/boards/risc-v/mpfs/icicle/kernel/Makefile new file mode 100755 index 00000000000..919e2d9965c --- /dev/null +++ b/boards/risc-v/mpfs/icicle/kernel/Makefile @@ -0,0 +1,107 @@ +############################################################################ +# boards/risc-v/mpfs/icicle//kernel/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_USER_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_USER_ENTRYPOINT)) + +# The memory layout + +MEM_LAYOUT = memory.ld + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + # Windows-native toolchains + USER_LIBPATHS = ${shell for path in $(USERLIBS); do dir=`dirname $(TOPDIR)$(DELIM)$$path`;echo "-L\"`cygpath -w $$dir`\"";done} + USER_LDSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(MEM_LAYOUT)}" + USER_LDSCRIPT += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld}" + USER_HEXFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.hex}" + USER_SRECFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.srec}" + USER_BINFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.bin}" +else + # Linux/Cygwin-native toolchain + USER_LIBPATHS = $(addprefix -L$(TOPDIR)$(DELIM),$(dir $(USERLIBS))) + USER_LDSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(MEM_LAYOUT) + USER_LDSCRIPT += -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld + USER_HEXFILE += "$(TOPDIR)$(DELIM)nuttx_user.hex" + USER_SRECFILE += "$(TOPDIR)$(DELIM)nuttx_user.srec" + USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" +endif + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = mpfs_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) -n nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/risc-v/mpfs/icicle/kernel/mpfs_userspace.c b/boards/risc-v/mpfs/icicle/kernel/mpfs_userspace.c new file mode 100755 index 00000000000..6fda7b7c8fb --- /dev/null +++ b/boards/risc-v/mpfs/icicle/kernel/mpfs_userspace.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/kernel/mpfs_userspace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x00001000 +# error "CONFIG_NUTTX_USERSPACE must match the value in memory.ld" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. + * They are not actual uint32_t storage locations! + * They are only used meaningfully in the following way: + * + * - The linker script defines, for example, the symbol_sdata. + * - The declaration extern uint32_t _sdata; makes C happy. C will believe + * that the value _sdata is the address of a uint32_t variable _data + * (it is not!). + * - We can recover the linker value then by simply taking the address of + * of _data. like: uint32_t *pdata = &_sdata; + */ + +extern uint32_t _stext; /* Start of .text */ +extern uint32_t _etext; /* End_1 of .text + .rodata */ +extern const uint32_t _eronly; /* End+1 of read only section */ +extern uint32_t _sdata; /* Start of .data */ +extern uint32_t _edata; /* End+1 of .data */ +extern uint32_t _sbss; /* Start of .bss */ +extern uint32_t _ebss; /* End+1 of .bss */ + +extern uintptr_t *__ld_usram_end; /* End+1 of user ram section */ + +/* This is the user space entry point */ + +int CONFIG_USER_ENTRYPOINT(int argc, char *argv[]); + +const struct userspace_s userspace __attribute__ ((section (".userspace"))) = +{ + /* General memory map */ + + .us_entrypoint = (main_t)CONFIG_USER_ENTRYPOINT, + .us_textstart = (uintptr_t)&_stext, + .us_textend = (uintptr_t)&_etext, + .us_datasource = (uintptr_t)&_eronly, + .us_datastart = (uintptr_t)&_sdata, + .us_dataend = (uintptr_t)&_edata, + .us_bssstart = (uintptr_t)&_sbss, + .us_bssend = (uintptr_t)&_ebss, + + .us_heapend = (uintptr_t)&__ld_usram_end, + + /* Memory manager heap structure */ + + .us_heap = &g_mmheap, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, +#ifndef CONFIG_DISABLE_PTHREAD + .pthread_startup = pthread_startup, +#endif + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIB_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/risc-v/mpfs/icicle/scripts/Make.defs b/boards/risc-v/mpfs/icicle/scripts/Make.defs new file mode 100755 index 00000000000..bdf6da11a5d --- /dev/null +++ b/boards/risc-v/mpfs/icicle/scripts/Make.defs @@ -0,0 +1,98 @@ +############################################################################ +# boards/risc-v/mpfs/icicle/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/risc-v/src/rv64gc/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g + ASARCHCPUFLAGS += -Wa,-g +endif + +MAXOPTIMIZATION = -Os + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce +endif + +# The following options are for the toolchain from T-HEAD. +# For more info ahout the T-HEAD ISA extensions, please refer to the MPFS user guide. +# ARCHCPUFLAGS = -march=rv64gcxthead -mabi=lp64d -mcmodel=medany +# TODO: We are not going to enable this at this time for the CI compatiblity. + +ifeq ($(CONFIG_ARCH_HAVE_DPFPU),y) + ARCHCPUFLAGS = -march=rv64gc -mabi=lp64d -mcmodel=medany +else + ARCHCPUFLAGS = -march=rv64imac -mabi=lp64 -mcmodel=medany +endif + +ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fno-omit-frame-pointer +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS) + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -fno-common +CXXELFFLAGS = $(CXXFLAGS) -fno-common + +LDELFFLAGS = -r -e main +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}" +else + LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld +endif + +# File extensions + +LDFLAGS += --gc-sections -melf64lriscv diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/gnu-elf.ld b/boards/risc-v/mpfs/icicle/scripts/gnu-elf.ld old mode 100644 new mode 100755 similarity index 97% rename from boards/xtensa/esp32/esp32-devkitc/scripts/gnu-elf.ld rename to boards/risc-v/mpfs/icicle/scripts/gnu-elf.ld index 6430b5de0c9..b513bc6063d --- a/boards/xtensa/esp32/esp32-devkitc/scripts/gnu-elf.ld +++ b/boards/risc-v/mpfs/icicle/scripts/gnu-elf.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/xtensa/esp32/esp32-devkitc/scripts/gnu-elf.ld + * boards/risc-v/mpfs/icicle/scripts/gnu-elf.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -75,7 +75,7 @@ SECTIONS _sctors = . ; *(.ctors) /* Old ABI: Unallocated */ *(.init_array) /* New ABI: Allocated */ - _ectors = . ; + _edtors = . ; } .dtors : diff --git a/boards/risc-v/mpfs/icicle/scripts/hss-nuttx.yml b/boards/risc-v/mpfs/icicle/scripts/hss-nuttx.yml new file mode 100644 index 00000000000..05b4214a024 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/scripts/hss-nuttx.yml @@ -0,0 +1,12 @@ +# HSS Payload Generator + +# First, we can optionally set a name for our image, otherwise one will be created dynamically +set-name: 'PolarFire-SoC-HSS::nuttx' + +# Next, we'll define the entry point addresses for each hart, as follows: +hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80000000', u54_3: '0x80000000', u54_4: '0x80000000'} + +# +payloads: + nuttx.bin: {exec-addr: '0x80000000', owner-hart: u54_1, priv-mode: prv_m} + diff --git a/boards/risc-v/mpfs/icicle/scripts/ld.script b/boards/risc-v/mpfs/icicle/scripts/ld.script new file mode 100755 index 00000000000..4fa073525af --- /dev/null +++ b/boards/risc-v/mpfs/icicle/scripts/ld.script @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + progmem (rx) : ORIGIN = 0x80000000, LENGTH = 2M /* w/ cache */ + sram (rwx) : ORIGIN = 0x80200000, LENGTH = 1M /* w/ cache */ +} + +OUTPUT_ARCH("riscv") + +ENTRY(_stext) +EXTERN(_vectors) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.* .srodata .srodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progmem + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > progmem + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > progmem + + PROVIDE(__global_pointer$ = _sdata + ((_edata - _sdata) / 2)); + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + . = ALIGN(32); + _default_stack_limit = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/mpfs/icicle/scripts/memory.ld b/boards/risc-v/mpfs/icicle/scripts/memory.ld new file mode 100755 index 00000000000..3b38cc4bbc3 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/scripts/memory.ld @@ -0,0 +1,35 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/scripts/memory.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Reg Access Start addr End addr Size + * QEMU CPU w/ cache 0x00000000 - 0x003fffff : 4MB + * QEMU CPU w/o cache 0x1f000000 - 0x1f01ffff : 128KB + */ + +MEMORY +{ + kflash (rx) : ORIGIN = 0x80000000, LENGTH = 256K /* w/ cache */ + uflash (rx) : ORIGIN = 0x80040000, LENGTH = 256K /* w/ cache */ + xflash (rx) : ORIGIN = 0x80080000, LENGTH = 256K /* w/o cache */ + + ksram (rwx) : ORIGIN = 0x800C0000, LENGTH = 256K /* w/ cache */ + usram (rwx) : ORIGIN = 0x80100000, LENGTH = 256K /* w/ cache */ + xsram (rwx) : ORIGIN = 0x80140000, LENGTH = 256K /* w/o cache */ +} diff --git a/boards/risc-v/mpfs/icicle/scripts/user-space.ld b/boards/risc-v/mpfs/icicle/scripts/user-space.ld new file mode 100755 index 00000000000..0e1204971cf --- /dev/null +++ b/boards/risc-v/mpfs/icicle/scripts/user-space.ld @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/scripts/user-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH("riscv") + +SECTIONS +{ + /* section info */ + + __ld_uflash_start = ORIGIN(uflash); + __ld_uflash_end = ORIGIN(uflash)+ LENGTH(uflash); + __ld_uflash_size = LENGTH(uflash); + + __ld_usram_start = ORIGIN(usram); + __ld_usram_end = ORIGIN(usram)+ LENGTH(usram); + __ld_usram_size = LENGTH(usram); + + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > uflash + + __exidx_start = ABSOLUTE(.); + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/mpfs/icicle/src/Makefile b/boards/risc-v/mpfs/icicle/src/Makefile new file mode 100755 index 00000000000..fc6753297b8 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/Makefile @@ -0,0 +1,45 @@ +############################################################################ +# boards/risc-v/mpfs/icicle/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = mpfs_bringup.c mpfs_boot.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += mpfs_appinit.c +endif + +ifeq ($(CONFIG_I2C),y) +CSRCS += mpfs_i2c.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += mpfs_autoleds.c +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CSRCS += mpfs_ostest.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += mpfs_board_spi.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/risc-v/mpfs/icicle/src/mpfs_appinit.c b/boards/risc-v/mpfs/icicle/src/mpfs_appinit.c new file mode 100755 index 00000000000..c4a28c00be7 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/mpfs_appinit.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/src/mpfs_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "mpfs.h" +#include "mpfsicicle.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return mpfs_bringup(); +#endif +} diff --git a/boards/risc-v/mpfs/icicle/src/mpfs_autoleds.c b/boards/risc-v/mpfs/icicle/src/mpfs_autoleds.c new file mode 100755 index 00000000000..5bc8b3b5442 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/mpfs_autoleds.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/src/mpfs_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include "mpfsicicle.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + * + * Description: + * Init the LEDs. + * + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + mpfs_configgpio(ICICLE_GPIO_LED1); + mpfs_configgpio(ICICLE_GPIO_LED2); + mpfs_configgpio(ICICLE_GPIO_LED3); + mpfs_configgpio(ICICLE_GPIO_LED4); + mpfs_gpiowrite(ICICLE_GPIO_LED1, false); + mpfs_gpiowrite(ICICLE_GPIO_LED2, false); + mpfs_gpiowrite(ICICLE_GPIO_LED3, false); + mpfs_gpiowrite(ICICLE_GPIO_LED4, false); +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turn on the LED specificed. + * + * Input Parameters: + * led - The LED which is under this control + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case LED_STARTED: + mpfs_gpiowrite(ICICLE_GPIO_LED1, true); + mpfs_gpiowrite(ICICLE_GPIO_LED2, false); + mpfs_gpiowrite(ICICLE_GPIO_LED3, false); + mpfs_gpiowrite(ICICLE_GPIO_LED4, false); + break; + case LED_HEAPALLOCATE: + mpfs_gpiowrite(ICICLE_GPIO_LED2, true); + break; + case LED_IRQSENABLED: + mpfs_gpiowrite(ICICLE_GPIO_LED1, true); + mpfs_gpiowrite(ICICLE_GPIO_LED2, true); + break; + case LED_STACKCREATED: + mpfs_gpiowrite(ICICLE_GPIO_LED3, true); + mpfs_gpiowrite(ICICLE_GPIO_LED1, false); + mpfs_gpiowrite(ICICLE_GPIO_LED2, false); + break; + case LED_INIRQ: + mpfs_gpiowrite(ICICLE_GPIO_LED1, true); + mpfs_gpiowrite(ICICLE_GPIO_LED2, false); + mpfs_gpiowrite(ICICLE_GPIO_LED3, false); + break; + case LED_SIGNAL: + mpfs_gpiowrite(ICICLE_GPIO_LED3, true); + mpfs_gpiowrite(ICICLE_GPIO_LED1, false); + mpfs_gpiowrite(ICICLE_GPIO_LED2, false); + break; + case LED_ASSERTION: + mpfs_gpiowrite(ICICLE_GPIO_LED3, true); + mpfs_gpiowrite(ICICLE_GPIO_LED2, true); + mpfs_gpiowrite(ICICLE_GPIO_LED1, true); + break; + case LED_PANIC: + mpfs_gpiowrite(ICICLE_GPIO_LED4, true); + break; + + default: + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turn off the LED specificed. + * + * Input Parameters: + * led - The LED which is under this control + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_INIRQ: + mpfs_gpiowrite(ICICLE_GPIO_LED1, false); + break; + case LED_SIGNAL: + mpfs_gpiowrite(ICICLE_GPIO_LED3, false); + break; + case LED_ASSERTION: + mpfs_gpiowrite(ICICLE_GPIO_LED3, false); + mpfs_gpiowrite(ICICLE_GPIO_LED2, false); + mpfs_gpiowrite(ICICLE_GPIO_LED1, false); + break; + case LED_PANIC: + mpfs_gpiowrite(ICICLE_GPIO_LED4, false); + break; + + default: + break; + } +} diff --git a/boards/risc-v/mpfs/icicle/src/mpfs_board_spi.c b/boards/risc-v/mpfs/icicle/src/mpfs_board_spi.c new file mode 100644 index 00000000000..85f955214e7 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/mpfs_board_spi.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/src/mpfs_board_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "mpfs_spi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spi_initialize + * + * Description: + * Initialize and register SPI driver for the defined SPI ports. + * + ****************************************************************************/ + +int mpfs_board_spi_init(void) +{ + int ret = OK; +#if defined(CONFIG_MPFS_SPI0) || defined(CONFIG_MPFS_SPI1) + struct spi_dev_s *spi; +#ifdef CONFIG_SPI_DRIVER + int port = 0; +#endif /* CONFIG_SPI_DRIVER */ +#endif + + /* Initialize SPI device */ + +#ifdef CONFIG_MPFS_SPI0 + spi = mpfs_spibus_initialize(0); + if (spi == NULL) + { + spierr("Failed to initialize SPI0\n"); + return -ENODEV; + } + +#ifdef CONFIG_SPI_DRIVER + ret = spi_register(spi, port++); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to register /dev/spi0: %d\n", ret); + + mpfs_spibus_uninitialize(spi); + } +#endif /* CONFIG_SPI_DRIVER */ +#endif /* CONFIG_MPFS_SPI0 */ + +#ifdef CONFIG_MPFS_SPI1 + spi = mpfs_spibus_initialize(1); + if (spi == NULL) + { + spierr("Failed to initialize SPI1\n"); + return -ENODEV; + } + +#ifdef CONFIG_SPI_DRIVER + ret = spi_register(spi, port); + if (ret < 0) + { + spierr("Failed to register /dev/spi%d: %d\n", port, ret); + + mpfs_spibus_uninitialize(spi); + } + +#endif /* CONFIG_SPI_DRIVER */ +#endif /* CONFIG_MPFS_SPI1 */ + return ret; +} diff --git a/boards/risc-v/mpfs/icicle/src/mpfs_boot.c b/boards/risc-v/mpfs/icicle/src/mpfs_boot.c new file mode 100755 index 00000000000..183ee9591aa --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/mpfs_boot.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/src/mpfs_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_boardinitialize + * + * Description: + * All mpfs architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void mpfs_boardinitialize(void) +{ + board_autoled_initialize(); +} diff --git a/boards/risc-v/mpfs/icicle/src/mpfs_bringup.c b/boards/risc-v/mpfs/icicle/src/mpfs_bringup.c new file mode 100755 index 00000000000..983ba9489e3 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/mpfs_bringup.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/src/mpfs_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "mpfsicicle.h" +#include "mpfs.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_bringup + ****************************************************************************/ + +int mpfs_bringup(void) +{ + int ret = OK; + +#if defined(CONFIG_I2C_DRIVER) + /* Configure I2C peripheral interfaces */ + + ret = mpfs_board_i2c_init(); + + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize I2C driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", "/proc", ret); + } +#endif + +#if defined(CONFIG_MPFS_SPI0) || defined(CONFIG_MPFS_SPI1) + /* Configure SPI peripheral interfaces */ + + ret = mpfs_board_spi_init(); + + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SPI driver: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/risc-v/mpfs/icicle/src/mpfs_i2c.c b/boards/risc-v/mpfs/icicle/src/mpfs_i2c.c new file mode 100644 index 00000000000..f08b50fa42c --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/mpfs_i2c.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/src/mpfs_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "mpfs_i2c.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_i2c_init + * + * Description: + * Configure the I2C driver. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int mpfs_board_i2c_init(void) +{ + int ret = OK; + +#if defined(CONFIG_MPFS_I2C0) || defined(CONFIG_MPFS_I2C1) +#ifdef CONFIG_I2C_DRIVER + int bus = 0; +#endif + FAR struct i2c_master_s *i2c; +#endif + +#ifdef CONFIG_MPFS_I2C0 + i2c = mpfs_i2cbus_initialize(0); + + if (i2c == NULL) + { + i2cerr("ERROR: Failed to init I2C0 interface\n"); + return -ENODEV; + } + +#ifdef CONFIG_I2C_DRIVER + ret = i2c_register(i2c, bus++); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C0 driver: %d\n", ret); + mpfs_i2cbus_uninitialize(i2c); + return ret; + } +#endif +#endif + +#ifdef CONFIG_MPFS_I2C1 + i2c = mpfs_i2cbus_initialize(1); + + if (i2c == NULL) + { + i2cerr("ERROR: Failed to init I2C1 interface\n"); + return -ENODEV; + } + +#ifdef CONFIG_I2C_DRIVER + ret = i2c_register(i2c, bus); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C1 driver: %d\n", ret); + mpfs_i2cbus_uninitialize(i2c); + return ret; + } +#endif +#endif + + return ret; +} diff --git a/boards/risc-v/mpfs/icicle/src/mpfs_ostest.c b/boards/risc-v/mpfs/icicle/src/mpfs_ostest.c new file mode 100755 index 00000000000..715ccc6504c --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/mpfs_ostest.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/src/mpfs_ostest.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#undef HAVE_FPU +#if defined(CONFIG_ARCH_FPU) && \ + !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \ + defined(CONFIG_TESTING_OSTEST_FPUSIZE) && \ + defined(CONFIG_SCHED_WAITPID) +# define HAVE_FPU 1 +#endif + +#ifdef HAVE_FPU + +#if CONFIG_TESTING_OSTEST_FPUSIZE != (8 * FPU_XCPT_REGS) +# error "CONFIG_TESTING_OSTEST_FPUSIZE has the wrong size" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint64_t g_saveregs[XCPTCONTEXT_REGS]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* Given an array of size CONFIG_TESTING_OSTEST_FPUSIZE, this function will + * return the current FPU registers. + */ + +void arch_getfpu(FAR uint32_t *fpusave) +{ + irqstate_t flags; + + /* Take a snapshot of the thread context right now */ + + flags = enter_critical_section(); + riscv_saveusercontext(g_saveregs); + + /* Return only the floating register values */ + + memcpy(fpusave, &g_saveregs[INT_XCPT_REGS], (8 * FPU_XCPT_REGS)); + leave_critical_section(flags); +} + +/* Given two arrays of size CONFIG_TESTING_OSTEST_FPUSIZE this function + * will compare them and return true if they are identical. + */ + +bool arch_cmpfpu(FAR const uint32_t *fpusave1, FAR const uint32_t *fpusave2) +{ + return memcmp(fpusave1, fpusave2, (8 * FPU_XCPT_REGS)) == 0; +} + +#endif /* HAVE_FPU */ diff --git a/boards/risc-v/mpfs/icicle/src/mpfsicicle.h b/boards/risc-v/mpfs/icicle/src/mpfsicicle.h new file mode 100755 index 00000000000..2d00e3acb63 --- /dev/null +++ b/boards/risc-v/mpfs/icicle/src/mpfsicicle.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * boards/risc-v/mpfs/icicle/src/mpfsicicle.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ICICLE_MPFS_SRC_MPFSICICLE_H +#define __BOARDS_RISCV_ICICLE_MPFS_SRC_MPFSICICLE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#define ICICLE_GPIO_LED1 (GPIO_BANK2 | GPIO_PIN19 | GPIO_OUTPUT) +#define ICICLE_GPIO_LED2 (GPIO_BANK2 | GPIO_PIN18 | GPIO_OUTPUT) +#define ICICLE_GPIO_LED3 (GPIO_BANK2 | GPIO_PIN17 | GPIO_OUTPUT) +#define ICICLE_GPIO_LED4 (GPIO_BANK2 | GPIO_PIN16 | GPIO_OUTPUT) + +/* note: button1 don't have gpio. Only irq */ + +#define ICICLE_GPIO_BUTTON2 (GPIO_BANK2 | GPIO_PIN30 | GPIO_INPUT | \ + GPIO_IRQ_ENABLE | GPIO_IRQ_EDGE_POS) +#define ICICLE_GPIO_BUTTON2_ALT (GPIO_BANK2 | GPIO_PIN26 | GPIO_OUTPUT) +#define ICICLE_GPIO_BUTTON3 (GPIO_BANK2 | GPIO_PIN31 | GPIO_INPUT | \ + GPIO_IRQ_ENABLE | GPIO_IRQ_EDGE_POS) +#define ICICLE_GPIO_BUTTON3_ALT (GPIO_BANK2 | GPIO_PIN27 | GPIO_OUTPUT) + +int mpfs_bringup(void); +int mpfs_board_spi_init(void); +int mpfs_board_i2c_init(void); + +#endif /* __BOARDS_RISCV_ICICLE_MPFS_SRC_MPFSICICLE_H */ diff --git a/boards/risc-v/rv32m1/rv32m1-vega/Kconfig b/boards/risc-v/rv32m1/rv32m1-vega/Kconfig new file mode 100644 index 00000000000..6f86982c469 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/Kconfig @@ -0,0 +1,15 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_RV32M1_VEGA + +config RV32M1_OPENISA_TOOLCHAIN + bool "Utilize OPEN ISA Toolchain" + default n + select ARCH_RISCV_INTXCPT_EXTENSIONS + ---help--- + With OPEN ISA Toolchain, RV32M1 RISC-V Core Capability can be exploited. + +endif diff --git a/boards/risc-v/rv32m1/rv32m1-vega/README.txt b/boards/risc-v/rv32m1/rv32m1-vega/README.txt new file mode 100644 index 00000000000..abf7f86c2c5 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/README.txt @@ -0,0 +1,242 @@ +README +====== + +This README discusses issues unique to NuttX configurations for the +OPEN ISA RV32M1-VEGA development board featuring the RV32M1 MCU. The +RV32M1 is a heterogeneous soc including an ARM Cortex-M4 CPU, an ARM +Cortex-M0+ CPU, a RISC-V RI5CY CPU, and a RISC-V ZERO_RISCY CPU. the +SOC integrates 1.25 MB flash, 384 KB SRAM, and varieties of peripherals. +The RV32M1-VEGA board features: + + - On-board OpenSDA Debug Adapter, + - USB Device Port, + - FXOS8700CQ Digital Combo Sensor: 3D Accelerometer + 3D Magnetometer, + - Wirless Abilities: BLE, Generic FSK, and IEEE Std.802.15.4(Thread), + - ONE user RGB LED, + - Four user push-buttons, + - 4 MB external SPI Flash, + - Micro-SD Card Slot on the backside, + - Arduino R3 Compatible IO Header. + +Refer to https://open-isa.org for further information about this board. + +Currently NuttX is ported to RV32M1 RI5CY only. RI5CY is RV32IMC RISC-V CPU +with PULP extensions features: + - Post-Incrementing load and stores, + - Multiply-Accumulate extenstions, + - ALU extensions, + - Hardware Loops. + +Contents +======== + + - LEDs + - UARTs + - Buttons + - ITCM + - TSTMR + +LEDs +==== + +The RV32M1-VEGA board has ONE user RGB LED; Only the red part led is used to +indicate an interrupt request is being serviced. + + SYMBOL Meaning RED* GREEN BLUE + ------------------- ----------------------- ------- ------- ----- + LED_STARTED NuttX has been started OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF OFF + LED_IRQSENABLED Interrupts enabled OFF OFF OFF + LED_STACKCREATED Idle stack created OFF OFF OFF + LED_INIRQ In an interrupt** OFF OFF OFF + LED_SIGNAL In a signal handler*** OFF OFF OFF + LED_ASSERTION An assertion failed OFF OFF OFF + LED_PANIC The system has crashed OFF OFF OFF + LED_CPU Interrupt service ON OFF OFF + +UARTs +==== + +LPUART PINS +--------------- + +LPUART0 + RX PC7, PB25, PA2 + TX PC8, PB26, PA3 +LPUART1 + RX PB2, PC29, PA2, PA25 + TX PB3, PC30, PA3, PA26 +LPUART2 + RX PB11, PB18, PB1 + TX PB12, PB19, PB0 +LPUART3 + RX PB28, PE8, PE29 + TX PB29, PE9, PE30 + +Default LPUART Configuration +-------------------------------- + +LPUART0 is enabled in most configurations (see */defconfig). RX and TX are +configured on pins PC7 and PC8, respectively (see include/board.h). These +two above pins are connected to onboard Debug Adpater which provides a USB- +TTL serial channel. + +Buttons +==== + +Four tactile buttons are populated on RV32M1-VEGA Board. + +Buttons PINS Assignment +--------------- +NAME PIN EXTERNAL-PULLUP +SW2 PA0 YES +SW3 PE8 NO +SW4 PE9 NO +SW5 PE12 NO + +All these buttons can be used as interrupt and wake up sources while SW2 can +be an alternative NMI Source. + +ITCM +==== + +A 64KB ITCM is coupled with M4 Cores, RI5CY CPU or ARM Cortex-M4 CPU. If the +ITCM is selected, Critical Codes including but not limited to Exception Vectors, +Interrupt Service Routines will be placed in ITCM. + +TSTMR +==== + +TSTMR Module is embedded in RV32M1 to provide system time stamp. It runs off 1MHz +with a 56-bit counter, and can be adopted to get more accurate delay counting. If +the Module is selected, a hardware delay method will replace mdealy and udelay, +the built-in software delay methods. + +TOOLCHAIN +======== + +It is preferable to use OPEN ISA gcc Toolchain to exploit RV32M1 RI5CY capabi- +lities, though the generic GNU RVG Toolchain can generate binary codes running +on RV32M1 RI5CY without any problems. To switch generic GNU RVG Toolchain to +OPEN ISA Toolchain, the following option must be selected: + +Board Selection ---> + [*] Utilize OPEN ISA Toolchain + +Make sure OPEN ISA Toolchain have been installed and be found in PATH. + +ARCHCPUFLAGS +==== + +RI5CY Core supports hardware loop with 6 hardware loop registers assistance, +these registers could be overwritten when contexts switch. If codes are generated +by OPEN ISA Toolchain and CONFIG_ARCH_RISCV_INTXCPT_EXTREGS is not less than 6, +the RI5CY specific architecture flag will be passed to gcc compiler. In that case, +the 6 hardware loop registers must be saved and restored in interrupt routines with +the general purpose registers. + +You will see the following lines in Make.defs file: + + ARCHCPURV32IM = -march=rv32imc -mabi=ilp32 + + ifeq ($(CONFIG_RV32M1_OPENISA_TOOLCHAIN),y) + ifdef CONFIG_ARCH_RISCV_INTXCPT_EXTREGS + ifeq ($(filter 0 1 2 3 4 5 , $(CONFIG_ARCH_RISCV_INTXCPT_EXTREGS)),) + ARCHCPURV32IM = -march=rv32imcxpulpv2 + endif + endif + endif + + ARCHCPUFLAGS = $(ARCHCPURV32IM) + + + +CONFIG_ARCH_RISV_INTXCPT_EXTREGS could be configured in the following menu: + +System Type ---> + [*] RISC-V Integer Context Extensions + (6) Number of Extral RISC-V Integer Context Registers + + +Program & Debug +======== + +Program +==== + +To program RV32M1, openocd from OPEN ISA and an external jtag adapter are pre- +requisite. There are 2 tested jtag adapters: Segger Jlink EDU mini and SiPEED +USB Jtag Adapter. The Segger Jlink EDU mini can connect J55 header on RV32M1-VEGA +board directly while SiPEED USB Jtag Adpater has to co-operate with an Adapter +board to setup wires connection. +Compared to Segger Jlink EDU Mini Adapter, SiPEED USB Jtag Adpater is cheaper but +not inferior. + +With SiPEED USB Jtag Adapter, some patches must be applied to rv32m1_ri5cy.cfg: + +--- a/rv32m1_ri5cy.cfg ++++ b/rv32m1_ri5cy.cfg +@@ -2,7 +2,11 @@ set _WORKAREASIZE 0x2000 + + adapter_khz 1000 + +-interface jlink ++interface ftdi ++ftdi_vid_pid 0x0403 0x6010 ++ftdi_layout_init 0x0508 0x0f1b ++ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100 ++ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400 + transport select jtag + + set _WORKAREASIZE 0x1000 + +------------------------------ +Make sure that RV32M1 boots RI5CY, and you do this ONLY ONCE. Refer to RV32M1-VEGA +quick start guide for more details. + +Note: + +OPEN ISA Toolchain, rv32m1_ri5cy.cfg contained in RV32M1 SDK, and RV32M1-VEGA +quick start guide could be found in the following link: +https://open-isa.org/downloads/ + +Debug +==== + +riscv64-unknonw-elf-gdb can not debug RV32M1 RISC-V Cores currently. GDB from +OPEN ISA Toolchain seems the only option and even can debug elf files generated +by risc64-unknown-elf-* tools. + +Configuration Sub-directories +======== + +NuttX of all configurations in rv32m1-vega/configs can be compiled by +the generic GNU RVG Toolchain and OPEN ISA Toolchain. + +buttons +==== + This configuration is a variant of the NSH configuration used for + demonstrating the four buttons on RV32M1-VEGA board. + Example usage of buttons: + + a. Start the buttons daemon: + nsh> buttons + + b. Press and release SW2, SW3, SW4, SW5 freely, the button pressed + and released messages will display correspondingly. + +nsh +==== + This configuration is basic. getprime is included in this configuration to + determine performance of RV32M1 RI5CY Core. + +nsh-itcm +==== + This configuration is a variant of the NSH configuration used for + demonstrating ITCM. When ITCM is selected, RI5CY Exception Vectors and + Interrupt Service Routines are placed in ITCM. Performance can be calculated + by getprime, and you might find it deteriorated a litte ironically. The drawback + may be caused by long jump frequently between ITCM and flash. Besides, an instr- + uction cache is enabled always after RI5CY resets, and amelioration could not be + achieved with even ITCM enabled. + What if codes fullfill the 64KB ITCM ? diff --git a/boards/risc-v/rv32m1/rv32m1-vega/configs/buttons/defconfig b/boards/risc-v/rv32m1/rv32m1-vega/configs/buttons/defconfig new file mode 100644 index 00000000000..35d6573d5ab --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/configs/buttons/defconfig @@ -0,0 +1,78 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="rv32m1-vega" +CONFIG_ARCH_BOARD_RV32M1_VEGA=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="rv32m1" +CONFIG_ARCH_CHIP_RV32M1=y +CONFIG_ARCH_CHIP_RV32M1_RI5CY=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEV_ZERO=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW2" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LPUART0_SERIAL_CONSOLE=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RV32IM_HW_MULDIV=y +CONFIG_RV32M1_LPUART0=y +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_TESTING_GETPRIME=y +CONFIG_USEC_PER_TICK=1000 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/rv32m1/rv32m1-vega/configs/nsh-itcm/defconfig b/boards/risc-v/rv32m1/rv32m1-vega/configs/nsh-itcm/defconfig new file mode 100644 index 00000000000..0ec05b2b628 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/configs/nsh-itcm/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="rv32m1-vega" +CONFIG_ARCH_BOARD_RV32M1_VEGA=y +CONFIG_ARCH_CHIP="rv32m1" +CONFIG_ARCH_CHIP_RV32M1=y +CONFIG_ARCH_CHIP_RV32M1_RI5CY=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEV_ZERO=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LPUART0_SERIAL_CONSOLE=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RV32IM_HW_MULDIV=y +CONFIG_RV32M1_ITCM=y +CONFIG_RV32M1_LPUART0=y +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_TESTING_GETPRIME=y +CONFIG_USEC_PER_TICK=1000 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/rv32m1/rv32m1-vega/configs/nsh/defconfig b/boards/risc-v/rv32m1/rv32m1-vega/configs/nsh/defconfig new file mode 100644 index 00000000000..431f5214bd5 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/configs/nsh/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="rv32m1-vega" +CONFIG_ARCH_BOARD_RV32M1_VEGA=y +CONFIG_ARCH_CHIP="rv32m1" +CONFIG_ARCH_CHIP_RV32M1=y +CONFIG_ARCH_CHIP_RV32M1_RI5CY=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEV_ZERO=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LPUART0_SERIAL_CONSOLE=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RV32IM_HW_MULDIV=y +CONFIG_RV32M1_LPUART0=y +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_TESTING_GETPRIME=y +CONFIG_USEC_PER_TICK=1000 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/rv32m1/rv32m1-vega/include/board.h b/boards/risc-v/rv32m1/rv32m1-vega/include/board.h new file mode 100644 index 00000000000..7e3fdff8d36 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/include/board.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_RV32M1_RV32M1_VEGA_INCLUDE_BOARD_H +#define __BOARDS_RISCV_RV32M1_RV32M1_VEGA_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LED_STARTED 0 /* N/A */ +#define LED_HEAPALLOCATE 1 /* N/A */ +#define LED_IRQSENABLED 2 /* N/A */ +#define LED_STACKCREATED 3 /* N/A */ +#define LED_INIRQ 4 /* N/A */ +#define LED_SIGNAL 5 /* N/A */ +#define LED_ASSERTION 6 /* N/A */ +#define LED_PANIC 7 /* N/A */ +#define LED_CPU 8 /* LED */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#define GPIO_LPUART0_RX GPIO_LPUART0_RX_1 /* PC7 */ +#define GPIO_LPUART0_TX GPIO_LPUART0_TX_1 /* PC8 */ + +#define GPIO_LPUART1_RX GPIO_LPUART1_RX_4 /* PA25 */ +#define GPIO_LPUART1_TX GPIO_LPUART1_TX_4 /* PA26 */ + +#define GPIO_LPUART2_RX GPIO_LPUART2_RX_1 /* PB11 */ +#define GPIO_LPUART2_TX GPIO_LPUART2_TX_1 /* PB12 */ + +#define GPIO_LPUART3_RX GPIO_LPUART3_RX_2 /* PE8 */ +#define GPIO_LPUART3_TX GPIO_LPUART3_TX_3 /* PE30 */ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_boardinitialize + ****************************************************************************/ + +void rv32m1_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISC-V_RV32M1_RV32M1_VEGA_INCLUDE_BOARD_H */ diff --git a/boards/risc-v/rv32m1/rv32m1-vega/scripts/Make.defs b/boards/risc-v/rv32m1/rv32m1-vega/scripts/Make.defs new file mode 100644 index 00000000000..9c211dd7679 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/scripts/Make.defs @@ -0,0 +1,80 @@ +############################################################################ +# boards/risc-v/rv32m1/rv32m1-vega/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs + +ifeq ($(CONFIG_RV32M1_OPENISA_TOOLCHAIN),y) + CROSSDEV = riscv32-unknown-elf- +endif + +ifeq ($(CONFIG_RV32M1_ITCM),y) + LDSCRIPT = ld-itcm.script +else + LDSCRIPT = ld.script +endif + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g + ASARCHCPUFLAGS += -Wa,-g +endif + +MAXOPTIMIZATION = -Os + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCPURV32IM = -march=rv32imc -mabi=ilp32 + +ifeq ($(CONFIG_RV32M1_OPENISA_TOOLCHAIN),y) + ifdef CONFIG_ARCH_RISCV_INTXCPT_EXTREGS + ifeq ($(filter 0 1 2 3 4 5 , $(CONFIG_ARCH_RISCV_INTXCPT_EXTREGS)),) + ARCHCPURV32IM = -march=rv32imcxpulpv2 + endif + endif +endif + +ARCHCPUFLAGS = $(ARCHCPURV32IM) +ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS) + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +LDFLAGS += --gc-sections -melf32lriscv diff --git a/boards/risc-v/rv32m1/rv32m1-vega/scripts/ld-itcm.script b/boards/risc-v/rv32m1/rv32m1-vega/scripts/ld-itcm.script new file mode 100644 index 00000000000..34b6bf0fff5 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/scripts/ld-itcm.script @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/scripts/ld-itcm.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x000FFF00 + vector(rx) : ORIGIN = 0x000FFF00, LENGTH = 256 + itcm (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +OUTPUT_ARCH("riscv") + +ENTRY(_stext) +EXTERN(_vectors) +SECTIONS +{ + .boot : { + _sboot = ABSOLUTE(.); + KEEP(*(.boot)) + _eboot = ABSOLUTE(.); + } > vector + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + .ialign : { + . = ALIGN(4); + _slitcm = ABSOLUTE(.); + } > flash + + .itcm : { + . = ALIGN(4); + _sitcm = ABSOLUTE(.); + _svitcm = ABSOLUTE(.); + _svector = .; + KEEP(*(.vectors)) + _evector = .; + *(.itcm .itcm.*) + . = ALIGN(4); + _evitcm = ABSOLUTE(.); + _suvitcm = ABSOLUTE(.); + *(.uitcm .uitcm.*) + _euvitcm = ABSOLUTE(.); + _eitcm = ORIGIN(itcm) + LENGTH(itcm); + } > itcm AT > flash + + .dalign : { + . = ALIGN(4); + _eronly = ABSOLUTE(.); + } > flash + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/rv32m1/rv32m1-vega/scripts/ld.script b/boards/risc-v/rv32m1/rv32m1-vega/scripts/ld.script new file mode 100644 index 00000000000..8298410d28e --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/scripts/ld.script @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x000FFF00 + vector(rx) : ORIGIN = 0x000FFF00, LENGTH = 256 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +OUTPUT_ARCH("riscv") + +ENTRY(_stext) +EXTERN(_vectors) +SECTIONS +{ + .vectors : ALIGN(4) { + _svector = .; + KEEP(*(.vectors)) + _evector = .; + } > vector + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/rv32m1/rv32m1-vega/src/Makefile b/boards/risc-v/rv32m1/rv32m1-vega/src/Makefile new file mode 100644 index 00000000000..426d902ed59 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/src/Makefile @@ -0,0 +1,37 @@ +############################################################################ +# boards/risc-v/rv32m1/rv32m1-vega/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = rv32m1_bringup.c rv32m1_boot.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += rv32m1_appinit.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += rv32m1_autoleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += rv32m1_buttons.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1-vega.h b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1-vega.h new file mode 100644 index 00000000000..c74d582c300 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1-vega.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1-vega.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_RV32M1_RV32M1_VEGA_SRC_RV32M1_VEGA_H +#define __BOARDS_RISCV_RV32M1_RV32M1_VEGA_SRC_RV32M1_VEGA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* BUTTONs */ + +#define BOARD_NBUTTON 4 + +#define BUTTON_SW2 (GPIO_INPUT|GPIO_INT_EDGE|GPIO_FLOAT |\ + GPIO_PORTA|GPIO_PIN0) + +#define BUTTON_SW3 (GPIO_INPUT|GPIO_INT_EDGE|GPIO_PULLUP|\ + GPIO_PORTE|GPIO_PIN8) + +#define BUTTON_SW4 (GPIO_INPUT|GPIO_INT_EDGE|GPIO_PULLUP|\ + GPIO_PORTE|GPIO_PIN9) + +#define BUTTON_SW5 (GPIO_INPUT|GPIO_INT_EDGE|GPIO_PULLUP|\ + GPIO_PORTE|GPIO_PIN12) + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture specific initialization + * + ****************************************************************************/ + +int rv32m1_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_RV32M1_RV32M1_VEGA_SRC_RV32M1_VEGA_H */ diff --git a/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_appinit.c b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_appinit.c new file mode 100644 index 00000000000..21e41299dd9 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_appinit.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "rv32m1.h" +#include "rv32m1-vega.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return rv32m1_bringup(); +#endif +} diff --git a/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_autoleds.c b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_autoleds.c new file mode 100644 index 00000000000..d5048817aaf --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_autoleds.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "rv32m1_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIO_LED (GPIO_OUTPUT|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN24) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + rv32m1_gpio_config(GPIO_LED); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (LED_CPU == led) + { + rv32m1_gpio_write(GPIO_LED, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (LED_CPU == led) + { + rv32m1_gpio_write(GPIO_LED, false); + } +} diff --git a/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_boot.c b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_boot.c new file mode 100644 index 00000000000..52e8a944319 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_boot.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_boardinitialize + * + * Description: + * All RV32M1 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void rv32m1_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} diff --git a/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_bringup.c b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_bringup.c new file mode 100644 index 00000000000..6af10072c07 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_bringup.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "rv32m1.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rv32m1_bringup + ****************************************************************************/ + +int rv32m1_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + "/proc", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", + ret); + } +#endif + + return ret; +} diff --git a/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_buttons.c b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_buttons.c new file mode 100644 index 00000000000..542b3ea1973 --- /dev/null +++ b/boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_buttons.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/risc-v/rv32m1/rv32m1-vega/src/rv32m1_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include + +#include "rv32m1_gpio.h" +#include "rv32m1.h" +#include "rv32m1-vega.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_buttons[BOARD_NBUTTON] = +{ + BUTTON_SW2, + BUTTON_SW3, + BUTTON_SW4, + BUTTON_SW5 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + for (i = 0; i < BOARD_NBUTTON; ++i) + { + rv32m1_gpio_config(g_buttons[i]); + } + + return BOARD_NBUTTON; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i = 0; + + for (i = 0; i < BOARD_NBUTTON; ++i) + { + /* Low value means that the button is pressed */ + + if (!rv32m1_gpio_read(g_buttons[i])) + { + ret |= 1 << i; + } + } + + return ret; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + int ret = -EINVAL; + + if (id < 0 || id >= BOARD_NBUTTON) + { + return -EINVAL; + } + + if (NULL != irqhandler) + { + /* Attach the new button handler. */ + + ret = rv32m1_gpio_irqattach(g_buttons[id], irqhandler, arg); + + /* Then make sure that interrupts are enabled on the pin */ + + rv32m1_gpio_irqenable(g_buttons[id]); + } + else + { + rv32m1_gpio_irqdisable(g_buttons[id]); + ret = 0; + } + + return ret; +} +#endif diff --git a/boards/sim/sim/sim/Kconfig b/boards/sim/sim/sim/Kconfig index 020de199f7a..4a138b09ee6 100644 --- a/boards/sim/sim/sim/Kconfig +++ b/boards/sim/sim/sim/Kconfig @@ -12,6 +12,7 @@ config EXAMPLES_TOUCHSCREEN_BGCOLOR config SIM_RPTUN_MASTER bool "Remote Processor Tunneling Role" + default n depends on RPTUN if SIM_TOUCHSCREEN diff --git a/boards/sim/sim/sim/configs/alsa/defconfig b/boards/sim/sim/sim/configs/alsa/defconfig index 4d39f374dca..7ab6550db5b 100644 --- a/boards/sim/sim/sim/configs/alsa/defconfig +++ b/boards/sim/sim/sim/configs/alsa/defconfig @@ -33,7 +33,6 @@ CONFIG_FS_ROMFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y @@ -55,5 +54,4 @@ CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NXLOOPER=y CONFIG_SYSTEM_NXPLAYER=y CONFIG_SYSTEM_NXRECORDER=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/asan/defconfig b/boards/sim/sim/sim/configs/asan/defconfig new file mode 100644 index 00000000000..f656a298656 --- /dev/null +++ b/boards/sim/sim/sim/configs/asan/defconfig @@ -0,0 +1,32 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="sim" +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_CHIP="sim" +CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_BINFS=y +CONFIG_FS_PROCFS=y +CONFIG_MM_CUSTOMIZE_MANAGER=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIM_SANITIZE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/bas/defconfig b/boards/sim/sim/sim/configs/bas/defconfig index 6fed61d9ea6..a9f92fcdcf8 100644 --- a/boards/sim/sim/sim/configs/bas/defconfig +++ b/boards/sim/sim/sim/configs/bas/defconfig @@ -25,7 +25,6 @@ CONFIG_INTERPRETERS_BAS=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FATDEVNO=2 @@ -41,5 +40,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/bastest/defconfig b/boards/sim/sim/sim/configs/bastest/defconfig new file mode 100644 index 00000000000..4fd991384dc --- /dev/null +++ b/boards/sim/sim/sim/configs/bastest/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="sim" +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_CHIP="sim" +CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_BASTEST=y +CONFIG_EXAMPLES_BASTEST_DEVMINOR=6 +CONFIG_EXAMPLES_BASTEST_DEVPATH="/dev/ram6" +CONFIG_EXAMPLES_HELLO=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FSUTILS_PASSWD=y +CONFIG_FSUTILS_PASSWD_READONLY=y +CONFIG_FS_BINFS=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_INTERPRETERS_BAS=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_LIB_ENVPATH=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_ARCHROMFS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CONSOLE_LOGIN=y +CONFIG_NSH_FATDEVNO=2 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" +CONFIG_NSH_READLINE=y +CONFIG_NSH_ROMFSDEVNO=1 +CONFIG_NSH_ROMFSETC=y +CONFIG_PATH_INITIAL="/bin" +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2008 +CONFIG_SYSTEM_NSH=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/bluetooth/defconfig b/boards/sim/sim/sim/configs/bluetooth/defconfig index 7974ba24bde..947b1badf43 100644 --- a/boards/sim/sim/sim/configs/bluetooth/defconfig +++ b/boards/sim/sim/sim/configs/bluetooth/defconfig @@ -37,7 +37,6 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_HOSTNAME="NuttX-SIM" -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y @@ -64,7 +63,6 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_DAY=3 CONFIG_START_MONTH=4 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WIRELESS=y CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/sim/sim/sim/configs/bthcisock/defconfig b/boards/sim/sim/sim/configs/bthcisock/defconfig index bb2ac21b384..7c22ea74968 100644 --- a/boards/sim/sim/sim/configs/bthcisock/defconfig +++ b/boards/sim/sim/sim/configs/bthcisock/defconfig @@ -38,7 +38,6 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_HOSTNAME="NuttX-SIM" -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y @@ -66,7 +65,6 @@ CONFIG_SIM_HCISOCKET=y CONFIG_START_DAY=3 CONFIG_START_MONTH=4 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WIRELESS=y CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/sim/sim/sim/configs/btuart/defconfig b/boards/sim/sim/sim/configs/btuart/defconfig index aecc21d845a..6e5ceba7c97 100644 --- a/boards/sim/sim/sim/configs/btuart/defconfig +++ b/boards/sim/sim/sim/configs/btuart/defconfig @@ -39,7 +39,6 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_HOSTNAME="NuttX-SIM" -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y @@ -68,7 +67,6 @@ CONFIG_START_DAY=3 CONFIG_START_MONTH=4 CONFIG_SYSTEM_NSH=y CONFIG_UART_BTH4=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WIRELESS=y CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/sim/sim/sim/configs/configdata/defconfig b/boards/sim/sim/sim/configs/configdata/defconfig index 0b634e1443a..a06ffd17300 100644 --- a/boards/sim/sim/sim/configs/configdata/defconfig +++ b/boards/sim/sim/sim/configs/configdata/defconfig @@ -21,7 +21,6 @@ CONFIG_FS_FAT=y CONFIG_FS_NXFFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIB_RAND_ORDER=3 -CONFIG_MAX_TASKS=64 CONFIG_MTD=y CONFIG_MTD_BYTE_WRITE=y CONFIG_MTD_CONFIG=y @@ -34,5 +33,4 @@ CONFIG_START_DAY=4 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2013 CONFIG_TESTING_NXFFS=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="configdata_main" diff --git a/boards/sim/sim/sim/configs/cxxtest/defconfig b/boards/sim/sim/sim/configs/cxxtest/defconfig index a286b7f719f..ea3d8ef40dc 100644 --- a/boards/sim/sim/sim/configs/cxxtest/defconfig +++ b/boards/sim/sim/sim/configs/cxxtest/defconfig @@ -15,7 +15,6 @@ CONFIG_BOARD_LOOPSPERMSEC=100 CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBM=y -CONFIG_MAX_TASKS=64 CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_START=0x00000000 CONFIG_SCHED_ONEXIT=y @@ -26,5 +25,4 @@ CONFIG_START_MONTH=2 CONFIG_START_YEAR=2007 CONFIG_TESTING_CXXTEST=y CONFIG_UCLIBCXX=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="cxxtest_main" diff --git a/boards/sim/sim/sim/configs/duktape/defconfig b/boards/sim/sim/sim/configs/duktape/defconfig index 3033ad8e218..56ce97bc286 100644 --- a/boards/sim/sim/sim/configs/duktape/defconfig +++ b/boards/sim/sim/sim/configs/duktape/defconfig @@ -34,7 +34,6 @@ CONFIG_INTERPRETERS_DUKTAPE_STACKSIZE=32768 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y @@ -56,5 +55,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/elf/defconfig b/boards/sim/sim/sim/configs/elf/defconfig new file mode 100644 index 00000000000..9b201f7f51b --- /dev/null +++ b/boards/sim/sim/sim/configs/elf/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="sim" +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_CHIP="sim" +CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_ELF=y +CONFIG_EXAMPLES_ELF_DEVMINOR=6 +CONFIG_EXAMPLES_ELF_DEVPATH="/dev/ram6" +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXECFUNCS_HAVE_SYMTAB=y +CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FSUTILS_PASSWD=y +CONFIG_FSUTILS_PASSWD_READONLY=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_LIBC_STRERROR=y +CONFIG_LIB_ENVPATH=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" +CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/bin" +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SIM_M32=y +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2008 +CONFIG_SYSTEM_NSH=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/fb/defconfig b/boards/sim/sim/sim/configs/fb/defconfig index 1c708cc5342..1460cfa0d88 100644 --- a/boards/sim/sim/sim/configs/fb/defconfig +++ b/boards/sim/sim/sim/configs/fb/defconfig @@ -18,11 +18,9 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DRIVERS_VIDEO=y CONFIG_EXAMPLES_FB=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=16 CONFIG_SDCLONE_DISABLE=y CONFIG_START_DAY=28 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2008 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="fb_main" CONFIG_VIDEO_FB=y diff --git a/boards/sim/sim/sim/configs/foc/defconfig b/boards/sim/sim/sim/configs/foc/defconfig index 7cd0364afd6..4c02a6d8447 100644 --- a/boards/sim/sim/sim/configs/foc/defconfig +++ b/boards/sim/sim/sim/configs/foc/defconfig @@ -60,7 +60,6 @@ CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_MOTOR=y CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_INST=4 @@ -88,5 +87,4 @@ CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSLOG_CONSOLE=y CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/ipforward/defconfig b/boards/sim/sim/sim/configs/ipforward/defconfig index f4462c90c40..efa4bd16232 100644 --- a/boards/sim/sim/sim/configs/ipforward/defconfig +++ b/boards/sim/sim/sim/configs/ipforward/defconfig @@ -33,7 +33,6 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_HOSTNAME="IP-Forward" -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NET_IPFORWARD=y @@ -66,5 +65,4 @@ CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y CONFIG_TUN_NINTERFACES=2 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/libcxxtest/defconfig b/boards/sim/sim/sim/configs/libcxxtest/defconfig index 74c295a6271..169288dd758 100644 --- a/boards/sim/sim/sim/configs/libcxxtest/defconfig +++ b/boards/sim/sim/sim/configs/libcxxtest/defconfig @@ -29,7 +29,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEBUG_WARN=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y -CONFIG_DHCPC_RENEW_STACKSIZE=4096 CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_NETTEST=y @@ -40,17 +39,14 @@ CONFIG_FS_HOSTFS=y CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y -CONFIG_HOST_MACOS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_IOB_NOTIFIER=y CONFIG_LIBCXX=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_MM_FILL_ALLOCATIONS=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_IFINDEX=y CONFIG_NETDEV_PHY_IOCTL=y CONFIG_NETDOWN_NOTIFIER=y CONFIG_NETINIT_DHCPC=y @@ -66,7 +62,6 @@ CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y CONFIG_NET_LOCAL=y CONFIG_NET_PROMISCUOUS=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_NOTIFIER=y @@ -87,7 +82,6 @@ CONFIG_RTC_ARCH=y CONFIG_RTC_DATETIME=y CONFIG_RTC_DRIVER=y CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_LPWORKSTACKSIZE=4096 CONFIG_SCHED_ONEXIT=y CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y @@ -97,9 +91,6 @@ CONFIG_STDIO_DISABLE_BUFFERING=y CONFIG_SYSLOG_CONSOLE=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NSH_STACKSIZE=4096 CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_PING_STACKSIZE=4096 CONFIG_TESTING_CXXTEST=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/linuxi2c/defconfig b/boards/sim/sim/sim/configs/linuxi2c/defconfig index e0e6708d4c2..fca047b98b1 100644 --- a/boards/sim/sim/sim/configs/linuxi2c/defconfig +++ b/boards/sim/sim/sim/configs/linuxi2c/defconfig @@ -23,7 +23,6 @@ CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y @@ -38,5 +37,4 @@ CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/lvgl/defconfig b/boards/sim/sim/sim/configs/lvgl/defconfig index ea9c906ef40..b860855ad22 100644 --- a/boards/sim/sim/sim/configs/lvgl/defconfig +++ b/boards/sim/sim/sim/configs/lvgl/defconfig @@ -32,7 +32,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_LV_COLOR_DEPTH=32 CONFIG_LV_HOR_RES=640 CONFIG_LV_VER_RES=480 -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NXFONTS_DISABLE_16BPP=y @@ -54,6 +53,5 @@ CONFIG_START_DAY=28 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=16384 CONFIG_USER_ENTRYPOINT="lvgldemo_main" CONFIG_VIDEO_FB=y diff --git a/boards/sim/sim/sim/configs/minibasic/defconfig b/boards/sim/sim/sim/configs/minibasic/defconfig index f870c196021..80f43b5bf0f 100644 --- a/boards/sim/sim/sim/configs/minibasic/defconfig +++ b/boards/sim/sim/sim/configs/minibasic/defconfig @@ -32,7 +32,6 @@ CONFIG_INTERPRETER_MINIBASIC_TESTSCRIPT=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBM=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y @@ -51,5 +50,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/module/defconfig b/boards/sim/sim/sim/configs/module/defconfig index 60eca11a696..60e7f27eff9 100644 --- a/boards/sim/sim/sim/configs/module/defconfig +++ b/boards/sim/sim/sim/configs/module/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y CONFIG_BINFMT_DISABLE=y CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y @@ -25,11 +26,10 @@ CONFIG_EXAMPLES_MODULE_DEVPATH="/dev/ram4" CONFIG_FSUTILS_PASSWD=y CONFIG_FSUTILS_PASSWD_READONLY=y CONFIG_FS_ROMFS=y -CONFIG_HOST_MACOS=y CONFIG_IOB_NOTIFIER=y CONFIG_LIBC_DLFCN=y +CONFIG_LIBC_STRERROR=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_MM_FILL_ALLOCATIONS=y CONFIG_NAME_MAX=64 CONFIG_NET=y @@ -49,7 +49,6 @@ CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y CONFIG_NET_LOCAL=y CONFIG_NET_PROMISCUOUS=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_NOTIFIER=y diff --git a/boards/sim/sim/sim/configs/module32/defconfig b/boards/sim/sim/sim/configs/module32/defconfig index 3d6d7cdb4f8..797486dd62f 100644 --- a/boards/sim/sim/sim/configs/module32/defconfig +++ b/boards/sim/sim/sim/configs/module32/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y CONFIG_BINFMT_DISABLE=y CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y @@ -25,16 +26,14 @@ CONFIG_EXAMPLES_MODULE_DEVPATH="/dev/ram4" CONFIG_FSUTILS_PASSWD=y CONFIG_FSUTILS_PASSWD_READONLY=y CONFIG_FS_ROMFS=y -CONFIG_HOST_MACOS=y CONFIG_IOB_NOTIFIER=y CONFIG_LIBC_DLFCN=y +CONFIG_LIBC_STRERROR=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_MM_FILL_ALLOCATIONS=y CONFIG_NAME_MAX=64 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_IFINDEX=y CONFIG_NETDEV_PHY_IOCTL=y CONFIG_NETDOWN_NOTIFIER=y CONFIG_NET_ARP_SEND=y @@ -49,7 +48,6 @@ CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y CONFIG_NET_LOCAL=y CONFIG_NET_PROMISCUOUS=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_NOTIFIER=y diff --git a/boards/sim/sim/sim/configs/mount/defconfig b/boards/sim/sim/sim/configs/mount/defconfig index 917fb2329f4..f3ecd15ab32 100644 --- a/boards/sim/sim/sim/configs/mount/defconfig +++ b/boards/sim/sim/sim/configs/mount/defconfig @@ -16,9 +16,7 @@ CONFIG_EXAMPLES_MOUNT_BLOCKDEVICE=y CONFIG_EXAMPLES_MOUNT_DEVNAME="/dev/ram0" CONFIG_FS_FAT=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=64 CONFIG_SDCLONE_DISABLE=y CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="mount_main" diff --git a/boards/sim/sim/sim/configs/mtdpart/defconfig b/boards/sim/sim/sim/configs/mtdpart/defconfig index 1a7f588f900..32e3ea18a72 100644 --- a/boards/sim/sim/sim/configs/mtdpart/defconfig +++ b/boards/sim/sim/sim/configs/mtdpart/defconfig @@ -18,7 +18,6 @@ CONFIG_EXAMPLES_MTDPART=y CONFIG_FS_FAT=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIB_RAND_ORDER=3 -CONFIG_MAX_TASKS=64 CONFIG_MTD=y CONFIG_MTD_PARTITION=y CONFIG_RAMMTD=y @@ -27,5 +26,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_DAY=29 CONFIG_START_MONTH=4 CONFIG_START_YEAR=2011 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="mtdpart_main" diff --git a/boards/sim/sim/sim/configs/mtdrwb/defconfig b/boards/sim/sim/sim/configs/mtdrwb/defconfig index b81bb16ad33..7b3ca81c640 100644 --- a/boards/sim/sim/sim/configs/mtdrwb/defconfig +++ b/boards/sim/sim/sim/configs/mtdrwb/defconfig @@ -19,7 +19,6 @@ CONFIG_EXAMPLES_MTDRWB=y CONFIG_FS_FAT=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIB_RAND_ORDER=3 -CONFIG_MAX_TASKS=64 CONFIG_MTD=y CONFIG_MTD_PARTITION=y CONFIG_MTD_READAHEAD=y @@ -32,5 +31,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_DAY=29 CONFIG_START_MONTH=4 CONFIG_START_YEAR=2011 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="mtdrwb_main" diff --git a/boards/sim/sim/sim/configs/nettest/defconfig b/boards/sim/sim/sim/configs/nettest/defconfig index 087641f65d1..ff4c0cb15d1 100644 --- a/boards/sim/sim/sim/configs/nettest/defconfig +++ b/boards/sim/sim/sim/configs/nettest/defconfig @@ -15,7 +15,6 @@ CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80001 CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80080 CONFIG_FS_FAT=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETUTILS_NETLIB=y @@ -29,5 +28,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_DAY=16 CONFIG_START_MONTH=8 CONFIG_START_YEAR=2008 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nettest_main" diff --git a/boards/sim/sim/sim/configs/nimble/defconfig b/boards/sim/sim/sim/configs/nimble/defconfig index 19d822376f7..f8e17c036d6 100644 --- a/boards/sim/sim/sim/configs/nimble/defconfig +++ b/boards/sim/sim/sim/configs/nimble/defconfig @@ -39,7 +39,6 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_HOSTNAME="NuttX-SIM" -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NETDEV_LATEINIT=y @@ -73,7 +72,6 @@ CONFIG_SIM_HCISOCKET=y CONFIG_START_DAY=3 CONFIG_START_MONTH=4 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WIRELESS=y CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/sim/sim/sim/configs/note/defconfig b/boards/sim/sim/sim/configs/note/defconfig new file mode 100644 index 00000000000..feae620c587 --- /dev/null +++ b/boards/sim/sim/sim/configs/note/defconfig @@ -0,0 +1,37 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="sim" +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_CHIP="sim" +CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVER_NOTE=y +CONFIG_DRIVER_NOTELOG=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_BINFS=y +CONFIG_FS_PROCFS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_CSECTION=y +CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y +CONFIG_SCHED_INSTRUMENTATION_PREEMPTION=y +CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS=y +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SYSTEM_NSH=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/nsh/defconfig b/boards/sim/sim/sim/configs/nsh/defconfig index 24d2c7839b9..f2ec75f111a 100644 --- a/boards/sim/sim/sim/configs/nsh/defconfig +++ b/boards/sim/sim/sim/configs/nsh/defconfig @@ -31,7 +31,6 @@ CONFIG_FS_ROMFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y @@ -53,5 +52,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/nsh2/defconfig b/boards/sim/sim/sim/configs/nsh2/defconfig index ab84ab46bf8..6de1dd3509e 100644 --- a/boards/sim/sim/sim/configs/nsh2/defconfig +++ b/boards/sim/sim/sim/configs/nsh2/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_INPUT=y -CONFIG_MAX_TASKS=64 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y @@ -55,6 +54,5 @@ CONFIG_START_DAY=6 CONFIG_START_MONTH=10 CONFIG_START_YEAR=2011 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_VIDEO_FB=y diff --git a/boards/sim/sim/sim/configs/nshcromfs/defconfig b/boards/sim/sim/sim/configs/nshcromfs/defconfig index d373d9c7ac8..9bb2df9b8e3 100644 --- a/boards/sim/sim/sim/configs/nshcromfs/defconfig +++ b/boards/sim/sim/sim/configs/nshcromfs/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILE_APPS=y @@ -48,5 +47,4 @@ CONFIG_START_YEAR=2008 CONFIG_SYSTEM_LZF=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SYSTEM=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/nx/defconfig b/boards/sim/sim/sim/configs/nx/defconfig index a8994a8e375..c6d48cebb92 100644 --- a/boards/sim/sim/sim/configs/nx/defconfig +++ b/boards/sim/sim/sim/configs/nx/defconfig @@ -19,7 +19,6 @@ CONFIG_DRIVERS_VIDEO=y CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX_BPP=8 CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y @@ -30,6 +29,5 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_DAY=28 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2008 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nx_main" CONFIG_VIDEO_FB=y diff --git a/boards/sim/sim/sim/configs/nx11/defconfig b/boards/sim/sim/sim/configs/nx11/defconfig index 6199703ee26..e7a7f6675d4 100644 --- a/boards/sim/sim/sim/configs/nx11/defconfig +++ b/boards/sim/sim/sim/configs/nx11/defconfig @@ -18,7 +18,6 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DRIVERS_VIDEO=y CONFIG_EXAMPLES_NX=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y @@ -31,6 +30,5 @@ CONFIG_SIM_X11FB=y CONFIG_START_DAY=28 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2008 -CONFIG_USERMAIN_STACKSIZE=16384 CONFIG_USER_ENTRYPOINT="nx_main" CONFIG_VIDEO_FB=y diff --git a/boards/sim/sim/sim/configs/nxffs/defconfig b/boards/sim/sim/sim/configs/nxffs/defconfig index 25febf33995..3944a3873b6 100644 --- a/boards/sim/sim/sim/configs/nxffs/defconfig +++ b/boards/sim/sim/sim/configs/nxffs/defconfig @@ -18,7 +18,6 @@ CONFIG_FS_FAT=y CONFIG_FS_NXFFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIB_RAND_ORDER=3 -CONFIG_MAX_TASKS=64 CONFIG_MTD=y CONFIG_NXFFS_SCAN_VOLUME=y CONFIG_RAMMTD=y @@ -28,5 +27,4 @@ CONFIG_START_DAY=29 CONFIG_START_MONTH=4 CONFIG_START_YEAR=2011 CONFIG_TESTING_NXFFS=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nxffs_main" diff --git a/boards/sim/sim/sim/configs/nxlines/defconfig b/boards/sim/sim/sim/configs/nxlines/defconfig index 7dac1054a35..990ca6110ad 100644 --- a/boards/sim/sim/sim/configs/nxlines/defconfig +++ b/boards/sim/sim/sim/configs/nxlines/defconfig @@ -31,7 +31,6 @@ CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=8192 -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FATDEVNO=2 @@ -55,6 +54,5 @@ CONFIG_SIM_FBBPP=32 CONFIG_SIM_X11FB=y CONFIG_START_MONTH=5 CONFIG_START_YEAR=2012 -CONFIG_USERMAIN_STACKSIZE=16384 CONFIG_USER_ENTRYPOINT="nxlines_main" CONFIG_VIDEO_FB=y diff --git a/boards/sim/sim/sim/configs/nxwm/defconfig b/boards/sim/sim/sim/configs/nxwm/defconfig index 9663a12e207..cf8fe0a3293 100644 --- a/boards/sim/sim/sim/configs/nxwm/defconfig +++ b/boards/sim/sim/sim/configs/nxwm/defconfig @@ -23,7 +23,6 @@ CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=8192 -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_LIBRARY=y diff --git a/boards/sim/sim/sim/configs/ostest/defconfig b/boards/sim/sim/sim/configs/ostest/defconfig index 3a67b244bd2..7cc4399c054 100644 --- a/boards/sim/sim/sim/configs/ostest/defconfig +++ b/boards/sim/sim/sim/configs/ostest/defconfig @@ -17,7 +17,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_FS_NAMED_SEMAPHORES=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=64 CONFIG_PTHREAD_CLEANUP=y CONFIG_PTHREAD_CLEANUP_STACKSIZE=3 CONFIG_PTHREAD_MUTEX_TYPES=y @@ -31,5 +30,4 @@ CONFIG_START_YEAR=2007 CONFIG_TESTING_OSTEST=y CONFIG_TESTING_OSTEST_LOOPS=100 CONFIG_TESTING_OSTEST_POWEROFF=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="ostest_main" diff --git a/boards/sim/sim/sim/configs/pf_ieee802154/defconfig b/boards/sim/sim/sim/configs/pf_ieee802154/defconfig index fc362a01ca9..22e89b9e611 100644 --- a/boards/sim/sim/sim/configs/pf_ieee802154/defconfig +++ b/boards/sim/sim/sim/configs/pf_ieee802154/defconfig @@ -35,7 +35,6 @@ CONFIG_IEEE802154_LOOPBACK=y CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=48 CONFIG_LIB_HOSTNAME="SAMV71-XULT" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MTD=y @@ -62,7 +61,6 @@ CONFIG_RAM_SIZE=393216 CONFIG_RAM_START=0x20400000 CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKSTACKSIZE=4096 CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y CONFIG_STANDARD_SERIAL=y @@ -70,7 +68,6 @@ CONFIG_START_DAY=10 CONFIG_START_MONTH=3 CONFIG_START_YEAR=2014 CONFIG_SYSTEM_NSH=y -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WIRELESS=y CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/sim/sim/sim/configs/pktradio/defconfig b/boards/sim/sim/sim/configs/pktradio/defconfig index 60a872fbe14..71ac6f6a37b 100644 --- a/boards/sim/sim/sim/configs/pktradio/defconfig +++ b/boards/sim/sim/sim/configs/pktradio/defconfig @@ -26,14 +26,12 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_DAEMON_STACKSIZE=4096 CONFIG_EXAMPLES_NETTEST_LOOPBACK=y CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x00a9 CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_NETTEST_STACKSIZE1=4096 CONFIG_EXAMPLES_UDPBLASTER=y CONFIG_EXAMPLES_UDPBLASTER_HOSTIPv6_1=0xfe80 CONFIG_EXAMPLES_UDPBLASTER_HOSTIPv6_6=0x00ff @@ -52,7 +50,6 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=48 CONFIG_LIB_HOSTNAME="SAMV71-XULT" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MTD=y @@ -69,7 +66,6 @@ CONFIG_NETINIT_NOMAC=y CONFIG_NET_6LOWPAN=y CONFIG_NET_BROADCAST=y CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y @@ -88,7 +84,6 @@ CONFIG_RAM_SIZE=393216 CONFIG_RAM_START=0x20400000 CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKSTACKSIZE=4096 CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y CONFIG_STANDARD_SERIAL=y @@ -96,7 +91,6 @@ CONFIG_START_DAY=10 CONFIG_START_MONTH=3 CONFIG_START_YEAR=2014 CONFIG_SYSTEM_NSH=y -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WIRELESS=y CONFIG_WIRELESS_PKTRADIO=y diff --git a/boards/sim/sim/sim/configs/posix_spawn/defconfig b/boards/sim/sim/sim/configs/posix_spawn/defconfig new file mode 100644 index 00000000000..bdaa0236835 --- /dev/null +++ b/boards/sim/sim/sim/configs/posix_spawn/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="sim" +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_CHIP="sim" +CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_POSIXSPAWN=y +CONFIG_EXAMPLES_POSIXSPAWN_DEVMINOR=8 +CONFIG_EXAMPLES_POSIXSPAWN_DEVPATH="/dev/ram8" +CONFIG_EXECFUNCS_HAVE_SYMTAB=y +CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FSUTILS_PASSWD=y +CONFIG_FSUTILS_PASSWD_READONLY=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIB_ENVPATH=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" +CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/mnt/romfs" +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SIM_M32=y +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2008 +CONFIG_SYSTEM_NSH=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/rc/defconfig b/boards/sim/sim/sim/configs/rc/defconfig index af2dfedd397..df465c7e1ce 100644 --- a/boards/sim/sim/sim/configs/rc/defconfig +++ b/boards/sim/sim/sim/configs/rc/defconfig @@ -28,7 +28,6 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILE_APPS=y @@ -45,5 +44,4 @@ CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y CONFIG_TESTING_IRTEST=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/romfs/defconfig b/boards/sim/sim/sim/configs/romfs/defconfig new file mode 100644 index 00000000000..05221993668 --- /dev/null +++ b/boards/sim/sim/sim/configs/romfs/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="sim" +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_CHIP="sim" +CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_ROMFS=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FSUTILS_PASSWD=y +CONFIG_FSUTILS_PASSWD_READONLY=y +CONFIG_FS_BINFS=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIB_ENVPATH=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_ARCHROMFS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CONSOLE_LOGIN=y +CONFIG_NSH_FATDEVNO=2 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" +CONFIG_NSH_READLINE=y +CONFIG_NSH_ROMFSDEVNO=6 +CONFIG_NSH_ROMFSETC=y +CONFIG_PATH_INITIAL="/bin" +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2008 +CONFIG_SYSTEM_NSH=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/rpproxy/defconfig b/boards/sim/sim/sim/configs/rpproxy/defconfig index fb491ab34f6..8c861aa0c8a 100644 --- a/boards/sim/sim/sim/configs/rpproxy/defconfig +++ b/boards/sim/sim/sim/configs/rpproxy/defconfig @@ -5,7 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # -# CONFIG_SIM_NETDEV is not set +# CONFIG_NET_ETHERNET is not set CONFIG_ARCH="sim" CONFIG_ARCH_BOARD="sim" CONFIG_ARCH_BOARD_SIM=y @@ -13,29 +13,22 @@ CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y CONFIG_BOARDCTL_POWEROFF=y CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_EXAMPLES_RPMSGSOCKET=y CONFIG_FS_HOSTFS=y CONFIG_FS_HOSTFS_RPMSG=y CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_FS_UNIONFS=y -CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIB_HOSTNAME="proxy" CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=176 CONFIG_NETDB_DNSCLIENT_RECV_TIMEOUT=3 CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x771d1d1d -CONFIG_NETDEV_IFINDEX=y CONFIG_NETUTILS_USRSOCK_RPMSG=y CONFIG_NET_ICMP_NO_STACK=y CONFIG_NET_RPMSG=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP_NO_STACK=y CONFIG_NET_UDP_NO_STACK=y CONFIG_NET_USRSOCK=y @@ -43,12 +36,9 @@ CONFIG_NET_USRSOCK_OTHER=y CONFIG_NET_USRSOCK_TCP=y CONFIG_NET_USRSOCK_UDP=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_UNAME=y CONFIG_NSH_PROMPT_STRING="proxy> " CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_OPENAMP=y CONFIG_READLINE_CMD_HISTORY=y CONFIG_READLINE_TABCOMPLETION=y @@ -63,11 +53,9 @@ CONFIG_RTC_RPMSG_SERVER_NAME="server" CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y +CONFIG_SIG_DEFAULT=y CONFIG_SIM_M32=y -CONFIG_STACK_COLORATION=y CONFIG_SYSLOG_PREFIX=y CONFIG_SYSLOG_PREFIX_STRING="proxy: " CONFIG_SYSLOG_RPMSG=y @@ -76,11 +64,4 @@ CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y -CONFIG_TTY_SIGINT=y -CONFIG_TTY_SIGINT_CHAR=0x04 -CONFIG_UORB=y -CONFIG_UORB_LISTENER=y -CONFIG_UORB_RPMSG_COMMUNICATOR=y -CONFIG_UORB_TESTS=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/rpserver/defconfig b/boards/sim/sim/sim/configs/rpserver/defconfig index 81459bca5d5..2c30410d2cf 100644 --- a/boards/sim/sim/sim/configs/rpserver/defconfig +++ b/boards/sim/sim/sim/configs/rpserver/defconfig @@ -12,17 +12,13 @@ CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y CONFIG_BOARDCTL_POWEROFF=y CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_EXAMPLES_RPMSGSOCKET=y CONFIG_FS_HOSTFS=y CONFIG_FS_HOSTFS_RPMSG_SERVER=y CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIB_HOSTNAME="server" CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y @@ -41,21 +37,16 @@ CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y CONFIG_NET_LOOPBACK=y CONFIG_NET_RPMSG=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y -CONFIG_NET_UDP_BINDTODEVICE=y CONFIG_NET_UDP_WRITE_BUFFERS=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_UNAME=y CONFIG_NSH_PROMPT_STRING="server> " CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_OPENAMP=y CONFIG_READLINE_CMD_HISTORY=y CONFIG_READLINE_TABCOMPLETION=y @@ -70,16 +61,10 @@ CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS_WTGAHRS2=y -CONFIG_SENSOR_MANAGER=y CONFIG_SIG_DEFAULT=y CONFIG_SIM_M32=y CONFIG_SIM_NET_BRIDGE=y CONFIG_SIM_RPTUN_MASTER=y -CONFIG_SIM_UART0_NAME="/dev/ttySensor" -CONFIG_SIM_UART_NUMBER=1 -CONFIG_SIM_WTGAHRS2_UARTN=0 -CONFIG_STACK_COLORATION=y CONFIG_SYSLOG_PREFIX=y CONFIG_SYSLOG_PREFIX_STRING="server: " CONFIG_SYSLOG_RPMSG_SERVER=y @@ -89,10 +74,5 @@ CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_CUTERM_DEFAULT_DEVICE="/dev/ttyproxy" CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y -CONFIG_TESTING_SENSORTEST=y CONFIG_TTY_SIGINT=y -CONFIG_UORB_LISTENER=y -CONFIG_UORB_RPMSG_COMMUNICATOR=y -CONFIG_UORB_TESTS=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/sensor/defconfig b/boards/sim/sim/sim/configs/sensor/defconfig index 5b20b3cc8a1..05fb1b2b5ee 100644 --- a/boards/sim/sim/sim/configs/sensor/defconfig +++ b/boards/sim/sim/sim/configs/sensor/defconfig @@ -29,7 +29,6 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILE_APPS=y @@ -51,5 +50,4 @@ CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y CONFIG_TESTING_SENSORTEST=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/sixlowpan/defconfig b/boards/sim/sim/sim/configs/sixlowpan/defconfig index 5cdaab2ce92..8e41279bd95 100644 --- a/boards/sim/sim/sim/configs/sixlowpan/defconfig +++ b/boards/sim/sim/sim/configs/sixlowpan/defconfig @@ -26,14 +26,12 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_DAEMON_STACKSIZE=4096 CONFIG_EXAMPLES_NETTEST_LOOPBACK=y CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0xcda9 CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_NETTEST_STACKSIZE1=4096 CONFIG_EXAMPLES_UDPBLASTER=y CONFIG_EXAMPLES_UDPBLASTER_HOSTIPv6_1=0xfe80 CONFIG_EXAMPLES_UDPBLASTER_HOSTIPv6_6=0x00ff @@ -53,7 +51,6 @@ CONFIG_IEEE802154_LOOPBACK=y CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=48 CONFIG_LIB_HOSTNAME="SAMV71-XULT" -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MTD=y @@ -70,7 +67,6 @@ CONFIG_NETINIT_NOMAC=y CONFIG_NET_6LOWPAN=y CONFIG_NET_BROADCAST=y CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y @@ -88,7 +84,6 @@ CONFIG_RAM_SIZE=393216 CONFIG_RAM_START=0x20400000 CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKSTACKSIZE=4096 CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y CONFIG_STANDARD_SERIAL=y @@ -96,7 +91,6 @@ CONFIG_START_DAY=10 CONFIG_START_MONTH=3 CONFIG_START_YEAR=2014 CONFIG_SYSTEM_NSH=y -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WIRELESS=y CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/sim/sim/sim/configs/sotest/defconfig b/boards/sim/sim/sim/configs/sotest/defconfig index b048653ce60..5eb28f1625c 100644 --- a/boards/sim/sim/sim/configs/sotest/defconfig +++ b/boards/sim/sim/sim/configs/sotest/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y CONFIG_BINFMT_DISABLE=y CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y @@ -25,16 +26,14 @@ CONFIG_EXAMPLES_SOTEST_DEVPATH="/dev/ram3" CONFIG_FSUTILS_PASSWD=y CONFIG_FSUTILS_PASSWD_READONLY=y CONFIG_FS_ROMFS=y -CONFIG_HOST_MACOS=y CONFIG_IOB_NOTIFIER=y CONFIG_LIBC_DLFCN=y +CONFIG_LIBC_STRERROR=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_MM_FILL_ALLOCATIONS=y CONFIG_NAME_MAX=64 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_IFINDEX=y CONFIG_NETDEV_PHY_IOCTL=y CONFIG_NETDOWN_NOTIFIER=y CONFIG_NET_ARP_SEND=y @@ -49,7 +48,6 @@ CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y CONFIG_NET_LOCAL=y CONFIG_NET_PROMISCUOUS=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_NOTIFIER=y diff --git a/boards/sim/sim/sim/configs/sotest32/defconfig b/boards/sim/sim/sim/configs/sotest32/defconfig index 9cbccccfdee..b4eaf3e6df6 100644 --- a/boards/sim/sim/sim/configs/sotest32/defconfig +++ b/boards/sim/sim/sim/configs/sotest32/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y CONFIG_BINFMT_DISABLE=y CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y @@ -25,16 +26,14 @@ CONFIG_EXAMPLES_SOTEST_DEVPATH="/dev/ram3" CONFIG_FSUTILS_PASSWD=y CONFIG_FSUTILS_PASSWD_READONLY=y CONFIG_FS_ROMFS=y -CONFIG_HOST_MACOS=y CONFIG_IOB_NOTIFIER=y CONFIG_LIBC_DLFCN=y +CONFIG_LIBC_STRERROR=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_MM_FILL_ALLOCATIONS=y CONFIG_NAME_MAX=64 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_IFINDEX=y CONFIG_NETDEV_PHY_IOCTL=y CONFIG_NETDOWN_NOTIFIER=y CONFIG_NET_ARP_SEND=y @@ -49,7 +48,6 @@ CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y CONFIG_NET_LOCAL=y CONFIG_NET_PROMISCUOUS=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_NOTIFIER=y diff --git a/boards/sim/sim/sim/configs/spiffs/defconfig b/boards/sim/sim/sim/configs/spiffs/defconfig index 4820a720436..bcaf85f159d 100644 --- a/boards/sim/sim/sim/configs/spiffs/defconfig +++ b/boards/sim/sim/sim/configs/spiffs/defconfig @@ -20,7 +20,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_FS_SPIFFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIB_RAND_ORDER=3 -CONFIG_MAX_TASKS=64 CONFIG_MTD=y CONFIG_RAMMTD=y CONFIG_RAMMTD_FLASHSIM=y @@ -31,5 +30,4 @@ CONFIG_START_MONTH=9 CONFIG_TESTING_FSTEST=y CONFIG_TESTING_FSTEST_MOUNTPT="/mnt/spiffs" CONFIG_TESTING_FSTEST_NLOOPS=10 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="fstest_main" diff --git a/boards/sim/sim/sim/configs/tcpblaster/defconfig b/boards/sim/sim/sim/configs/tcpblaster/defconfig index f82b754c048..6ace500bc86 100644 --- a/boards/sim/sim/sim/configs/tcpblaster/defconfig +++ b/boards/sim/sim/sim/configs/tcpblaster/defconfig @@ -39,7 +39,6 @@ CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_LOCALE=y CONFIG_LIBC_LOCALTIME=y CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MTD=y @@ -78,13 +77,11 @@ CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_TUN=y CONFIG_NET_TUN_PKTSIZE=1500 CONFIG_NET_UDP=y -CONFIG_NET_UDP_BINDTODEVICE=y CONFIG_NET_UDP_WRITE_BUFFERS=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=4096 CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 CONFIG_PREALLOC_TIMERS=4 CONFIG_PSEUDOFS_SOFTLINKS=y @@ -109,14 +106,11 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NSH_STACKSIZE=4096 CONFIG_SYSTEM_NTPC=y CONFIG_SYSTEM_PING6=y CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_PING_STACKSIZE=4096 CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_SYSTEM_TELNET_CLIENT_STACKSIZE=4096 CONFIG_SYSTEM_TIME64=y CONFIG_TASK_NAME_SIZE=32 CONFIG_TELNET_CHARACTER_MODE=y @@ -124,5 +118,4 @@ CONFIG_TELNET_TXBUFFER_SIZE=64 CONFIG_TTY_SIGINT=y CONFIG_TTY_SIGINT_CHAR=0x3 CONFIG_TTY_SIGTSTP=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/tcploop/defconfig b/boards/sim/sim/sim/configs/tcploop/defconfig index b57a714744b..ff23abcec01 100644 --- a/boards/sim/sim/sim/configs/tcploop/defconfig +++ b/boards/sim/sim/sim/configs/tcploop/defconfig @@ -34,7 +34,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y CONFIG_LIB_HOSTNAME="IP-Forward" -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NET_IPv6=y diff --git a/boards/sim/sim/sim/configs/touchscreen/defconfig b/boards/sim/sim/sim/configs/touchscreen/defconfig index 24e04eeb3d1..ca3eaa441d3 100644 --- a/boards/sim/sim/sim/configs/touchscreen/defconfig +++ b/boards/sim/sim/sim/configs/touchscreen/defconfig @@ -22,7 +22,6 @@ CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_INPUT=y CONFIG_LIB_BOARDCTL=y -CONFIG_MAX_TASKS=16 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y @@ -38,6 +37,5 @@ CONFIG_SIM_X11FB=y CONFIG_START_DAY=28 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2008 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="tc_main" CONFIG_VIDEO_FB=y diff --git a/boards/sim/sim/sim/configs/udgram/defconfig b/boards/sim/sim/sim/configs/udgram/defconfig index 400a8fbc615..b487e149576 100644 --- a/boards/sim/sim/sim/configs/udgram/defconfig +++ b/boards/sim/sim/sim/configs/udgram/defconfig @@ -30,7 +30,6 @@ CONFIG_FS_ROMFS=y CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NET_LOCAL=y diff --git a/boards/sim/sim/sim/configs/unionfs/defconfig b/boards/sim/sim/sim/configs/unionfs/defconfig index 6bf932b87a0..287a21af19e 100644 --- a/boards/sim/sim/sim/configs/unionfs/defconfig +++ b/boards/sim/sim/sim/configs/unionfs/defconfig @@ -26,8 +26,8 @@ CONFIG_FS_ROMFS=y CONFIG_FS_UNIONFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_STRERROR=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FATDEVNO=2 @@ -43,5 +43,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/userfs/defconfig b/boards/sim/sim/sim/configs/userfs/defconfig index a0b5bd8fe99..910ffd036fa 100644 --- a/boards/sim/sim/sim/configs/userfs/defconfig +++ b/boards/sim/sim/sim/configs/userfs/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_USERFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NET_LOCAL=y diff --git a/boards/sim/sim/sim/configs/ustream/defconfig b/boards/sim/sim/sim/configs/ustream/defconfig index ba882678b50..92d0e9ee5ab 100644 --- a/boards/sim/sim/sim/configs/ustream/defconfig +++ b/boards/sim/sim/sim/configs/ustream/defconfig @@ -30,7 +30,6 @@ CONFIG_FS_ROMFS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_NET=y CONFIG_NETDEVICES=y CONFIG_NET_LOCAL=y @@ -49,5 +48,4 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_NSH=y -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/configs/vpnkit/defconfig b/boards/sim/sim/sim/configs/vpnkit/defconfig index b9f76fd0460..be6bef90c9f 100644 --- a/boards/sim/sim/sim/configs/vpnkit/defconfig +++ b/boards/sim/sim/sim/configs/vpnkit/defconfig @@ -28,7 +28,6 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEBUG_WARN=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y -CONFIG_DHCPC_RENEW_STACKSIZE=4096 CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_NETTEST=y CONFIG_FSUTILS_PASSWD=y @@ -41,11 +40,9 @@ CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_IOB_NOTIFIER=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIB_ENVPATH=y -CONFIG_MAX_TASKS=64 CONFIG_MM_FILL_ALLOCATIONS=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_IFINDEX=y CONFIG_NETDEV_PHY_IOCTL=y CONFIG_NETDOWN_NOTIFIER=y CONFIG_NETINIT_DHCPC=y @@ -61,7 +58,6 @@ CONFIG_NET_ICMPv6_SOCKET=y CONFIG_NET_IPv6=y CONFIG_NET_LOCAL=y CONFIG_NET_PROMISCUOUS=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_TCP_NOTIFIER=y @@ -82,7 +78,6 @@ CONFIG_RTC_ARCH=y CONFIG_RTC_DATETIME=y CONFIG_RTC_DRIVER=y CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_LPWORKSTACKSIZE=4096 CONFIG_SCHED_ONEXIT=y CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y @@ -93,8 +88,5 @@ CONFIG_STDIO_DISABLE_BUFFERING=y CONFIG_SYSLOG_CONSOLE=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NSH_STACKSIZE=4096 CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_PING_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/scripts/Make.defs b/boards/sim/sim/sim/scripts/Make.defs index e69ae6a9cdb..def290af598 100644 --- a/boards/sim/sim/sim/scripts/Make.defs +++ b/boards/sim/sim/sim/scripts/Make.defs @@ -83,7 +83,7 @@ endif CC = $(CROSSDEV)cc CXX = $(CROSSDEV)c++ CPP = $(CROSSDEV)cc -E -P -x c -LD = $(CROSSDEV)ld +LD = $(CROSSDEV)cc ifeq ($(CONFIG_HOST_MACOS),y) STRIP = $(CROSSDEV)strip AR = $(TOPDIR)/tools/macar-rcs.sh @@ -96,26 +96,27 @@ OBJCOPY = $(CROSSDEV)objcopy OBJDUMP = $(CROSSDEV)objdump # Note: -fshort-wchar for the case where NuttX and the host OS have -# differnt wchar_t. On Nuttx, it's uint16_t. On macOS, it's 32-bit. +# different wchar_t. On NuttX, it's uint16_t. On macOS, it's 32-bit. CFLAGS := $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe \ -fshort-wchar CXXFLAGS := $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \ $(ARCHCPUFLAGSXX) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe \ - -fshort-wchar -std=c++17 + -fshort-wchar CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) \ -fshort-wchar AFLAGS := $(CFLAGS) -D__ASSEMBLY__ ifeq ($(CONFIG_LIBCXX),y) - # Why c++14? + # Why c++17? # * libcxx seems to require c++11. # * The compiler defaults varies: # clang/macOS (from xcode): 199711L # gcc/ubuntu: 201402L # * There is a precedent to use c++14. # (boards/arm/stm32l4/nucleo-l476rg/scripts/Make.defs) - CXXFLAGS += -std=c++14 + # * libs/libxx/libcxx/src/barrier.cpp depends on aligned new + CXXFLAGS += -std=c++17 ifeq ($(CONFIG_HOST_MACOS),y) # macOS uses libc++abi @@ -183,11 +184,11 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif ifeq ($(CONFIG_SIM_M32),y) - LDLINKFLAGS += -melf_i386 + LDLINKFLAGS += -Wl,-melf_i386 CCLINKFLAGS += -m32 LDFLAGS += -m32 - LDMODULEFLAGS += -melf_i386 - LDELFFLAGS += -melf_i386 + LDMODULEFLAGS += -Wl,-melf_i386 + LDELFFLAGS += -Wl,-melf_i386 HOSTLDFLAGS += -m32 endif @@ -198,3 +199,5 @@ endif HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(EXTRAFLAGS) -pipe + +LDLINKFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/sim/sim/sim/src/Makefile b/boards/sim/sim/sim/src/Makefile index 7eb90210408..598b8af0a6f 100644 --- a/boards/sim/sim/sim/src/Makefile +++ b/boards/sim/sim/sim/src/Makefile @@ -62,9 +62,6 @@ ifeq ($(CONFIG_NSH_ROMFSETC),y) ifneq ($(CONFIG_NSH_CUSTOMROMFS),y) RCSRCS = etc/init.d/rcS RCRAWS = etc/group etc/passwd - RCRAWS += etc/ssl/curl/cacert.pem - RCRAWS += etc/init.d/bt_did.conf - RCRAWS += etc/init.d/bt_stack.conf endif endif diff --git a/boards/sim/sim/sim/src/csv/accel.csv b/boards/sim/sim/sim/src/csv/accel.csv deleted file mode 100644 index a3baad30ea2..00000000000 --- a/boards/sim/sim/sim/src/csv/accel.csv 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--1.9295919,0.8104877,5.0660086 --2.0028956,0.48917282,5.2223897 --1.9686873,0.1727449,5.2956934 --1.7451108,-0.022731803,5.239494 --1.4616696,-0.072822705,5.0195827 --1.3908092,0.09699768,4.6652813 --1.6021684,0.2924744,4.2291236 --1.9552482,0.3633347,3.7990744 --2.1079643,0.28147882,3.3934603 --1.9796828,0.15319723,2.979294 --1.7157893,0.11532362,2.528476 --1.5068735,0.13731475,2.12164 --1.4201307,0.15441896,1.7514561 --1.3590443,0.13731475,1.3983762 --1.328501,0.083558664,1.0733962 --1.3077316,0.034689482,0.78018117 --1.2148802,0.010254892,0.53339183 --1.003521,0.0126983505,0.32325435 --0.7274101,0.027359102,0.1143386 --0.46473825,0.11043671,-0.14466804 --0.21550544,0.226501,-0.45132214 --0.037132937,0.2924744,-0.82028437 -0.03006218,0.36944336,-1.2368941 -0.07770963,0.4708469,-1.6950427 -0.23653446,0.556368,-2.1483045 -0.5260843,0.6040154,-2.601566 -0.8681686,0.5991285,-3.043832 -1.2053658,0.569807,-3.5374107 -1.4790332,0.51605093,-4.030989 -1.7417051,0.4256429,-4.451264 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--3.7346191,5.0598145,-10.598572 --1.9214478,5.286377,-11.00238 --3.2392578,5.8344727,-10.489502 --2.858429,6.133545,-10.443298 --1.4187622,5.8901367,-10.600525 --0.86694336,4.900879,-11.028748 --0.86694336,4.900879,-11.028748 --1.2221375,4.070801,-9.569885 --1.2221375,4.070801,-9.569885 --2.5496826,4.666504,-10.623047 --2.2645264,3.991455,-10.23114 --2.9169312,4.0307617,-10.240173 --1.3965149,5.510498,-8.761902 --2.5800476,5.761963,-9.384216 -0.22808838,3.505127,-9.767761 --1.0704651,3.147705,-11.413025 --2.31958,5.6132812,-10.340637 --1.5202637,5.215332,-9.430847 --1.4893188,4.522705,-7.946228 --1.5154114,5.1914062,-8.647827 --0.6098633,4.904297,-11.65155 --1.3699646,4.7043457,-8.8637085 --2.2702942,4.290039,-9.407349 --2.6003723,6.132324,-10.909546 --2.6864014,4.840332,-10.761108 --2.5573425,5.244873,-8.34906 --1.269043,5.2470703,-10.993347 --1.5584717,6.0788574,-11.208313 --0.7470093,5.4853516,-9.222717 --2.5534973,4.9558105,-9.486023 --1.7730408,4.7851562,-10.748474 --1.0979309,4.22876,-9.704285 -0.57373047,4.9230957,-9.265808 --1.5096436,4.8928223,-9.471619 --2.8086853,4.6726074,-10.313416 --2.0378418,5.090088,-9.615051 --2.7216492,5.9594727,-10.305298 --1.9253235,5.30542,-11.628845 --2.1640015,4.9416504,-9.793884 --1.4100342,5.847168,-9.190979 --1.0767212,3.5839844,-9.785767 --1.7643127,4.7421875,-9.338989 --1.25354,4.900635,-10.251038 --2.133545,4.116455,-9.269287 --2.8125,4.961914,-9.176453 --0.7489624,5.494873,-9.53595 --2.149475,4.6000977,-9.208191 --1.5096436,4.8928223,-9.471619 --2.040741,5.104492,-10.0849 --1.3680115,4.694824,-8.550537 --1.5222168,5.2248535,-9.74408 --0.5242615,6.333252,-10.996521 --2.1533813,4.6191406,-9.834595 --1.2389832,4.8293457,-7.9019165 --2.2765198,4.726074,-7.7800903 --1.1669617,6.324951,-9.439514 --1.769165,4.7661133,-10.122009 --2.7167969,5.935547,-9.522278 --1.2269897,4.0944824,-10.352966 --2.8096008,4.94751,-8.706604 --1.5584717,6.0788574,-11.208313 --2.9343567,4.3864746,-11.295654 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-1.5914001,54.441162,-19.615662 --0.7177124,53.307617,-20.280823 --1.801117,54.645996,-19.662537 diff --git a/boards/sim/sim/sim/src/etc/init.d/bt_did.conf b/boards/sim/sim/sim/src/etc/init.d/bt_did.conf deleted file mode 100644 index da9cf6bdbe4..00000000000 --- a/boards/sim/sim/sim/src/etc/init.d/bt_did.conf +++ /dev/null @@ -1,6 +0,0 @@ -[DID1] -primaryRecord = true -productId = 0x1200 -version = 0x1436 -[DID2] -[DID3] diff --git a/boards/sim/sim/sim/src/etc/init.d/bt_stack.conf b/boards/sim/sim/sim/src/etc/init.d/bt_stack.conf deleted file mode 100644 index 5b4d907b8d6..00000000000 --- a/boards/sim/sim/sim/src/etc/init.d/bt_stack.conf +++ /dev/null @@ -1,20 +0,0 @@ -TraceConf=true -TRC_BTM=2 -TRC_HCI=2 -TRC_L2CAP=2 -TRC_RFCOMM=2 -TRC_OBEX=2 -TRC_AVCT=2 -TRC_AVDT=2 -TRC_AVRC=2 -TRC_AVDT_SCB=2 -TRC_AVDT_CCB=2 -TRC_A2D=2 -TRC_SDP=2 -TRC_SMP=2 -TRC_BTAPP=2 -TRC_BTIF=2 -TRC_BNEP=2 -TRC_PAN=2 -TRC_HID_HOST=2 -TRC_HID_DEV=2 diff --git a/boards/sim/sim/sim/src/etc/init.d/rcS b/boards/sim/sim/sim/src/etc/init.d/rcS index d7de084dbda..29ae0dd696c 100644 --- a/boards/sim/sim/sim/src/etc/init.d/rcS +++ b/boards/sim/sim/sim/src/etc/init.d/rcS @@ -20,17 +20,10 @@ #include -set +e - #define CONCAT_(x, y) x##y #define CONCAT(x, y) CONCAT_(x, y) #ifdef CONFIG_NSH_ROMFSETC - -#ifndef CONFIG_NSH_DISABLE_UNAME -uname -a > /dev/syslog -#endif /* CONFIG_NSH_DISABLE_UNAME */ - #ifdef CONFIG_FS_FAT /* Create a RAMDISK and mount it at /tmp */ @@ -40,73 +33,4 @@ mkfatfs CONCAT(/dev/ram, CONFIG_NSH_FATDEVNO) mount -t vfat CONCAT(/dev/ram, CONFIG_NSH_FATDEVNO) CONFIG_NSH_FATMOUNTPT #endif /* CONFIG_FS_FAT */ - -#ifdef CONFIG_FS_HOSTFS - -#ifdef CONFIG_FS_HOSTFS_RPMSG -mount -t hostfs -o fs=/system /system -mount -t hostfs -o fs=/data /data - - #if defined (CONFIG_NSH_PROC_MOUNTPOINT) && defined (CONFIG_FS_UNIONFS) - umount CONFIG_NSH_PROC_MOUNTPOINT - mount -t procfs /proc1 - mount -t hostfs -o fs=/proc/net /net2 - mount -t unionfs -o fspath1=/proc1,fspath2=/net2,prefix2=net CONFIG_NSH_PROC_MOUNTPOINT - #endif - -#else -mount -t hostfs -o fs=../apps /system -mount -t hostfs -o fs=. /data -#endif - -#ifdef CONFIG_TESTING_TESTRUNNER - -testrunner >/system/testing/testrunner.log & - -#endif /* CONFIG_TESTING_TESTRUNNER */ - -#endif /* CONFIG_FS_HOSTFS */ - #endif /* CONFIG_NSH_ROMFSETC */ - -#ifdef CONFIG_KVDB -#ifndef KVDB_REMOTE_SERVER - -kvdbd & -usleep 10 - -#endif /* !CONFIG_REMOTE_SERVER */ -#endif /* CONFIG_KVDB */ - -#ifdef CONFIG_UORB - -uorb start & - -#endif /* CONFIG_UORB */ - -#ifdef CONFIG_LIB_FLUORIDE -fluorided & -bta bdname -bta scan 2 -#endif /* CONFIG_LIB_FLUORIDE */ - -#ifdef CONFIG_BT -zblue - -#ifdef CONFIG_BT_TESTER -bttester -#endif /* CONFIG_BT_TESTER */ - -#endif /* CONFIG_BT */ - -#ifdef CONFIG_SENSOR_MANAGER - -sensor & - -#endif /* CONFIG_SENSOR_MANAGER */ - -#if defined (CONFIG_NET_USRSOCK) - usrsock server & -#elif defined (CONFIG_NETUTILS_USRSOCK_RPMSG) - usrsock & -#endif diff --git a/boards/sim/sim/sim/src/etc/ssl/curl/cacert.pem b/boards/sim/sim/sim/src/etc/ssl/curl/cacert.pem deleted file mode 100644 index 651694e8a3a..00000000000 --- a/boards/sim/sim/sim/src/etc/ssl/curl/cacert.pem +++ /dev/null @@ -1,3466 +0,0 @@ -## -## Bundle of CA Root Certificates -## -## Certificate data from Mozilla as of: Wed Jan 1 04:12:10 2020 GMT -## -## This is a bundle of X.509 certificates of public Certificate Authorities -## (CA). These were automatically extracted from Mozilla's root certificates -## file (certdata.txt). This file can be found in the mozilla source tree: -## https://hg.mozilla.org/releases/mozilla-release/raw-file/default/security/nss/lib/ckfw/builtins/certdata.txt -## -## It contains the certificates in PEM format and therefore -## can be directly used with curl / libcurl / php_curl, or with -## an Apache+mod_ssl webserver for SSL client authentication. -## Just configure this file as the SSLCACertificateFile. -## -## Conversion done with mk-ca-bundle.pl version 1.27. -## SHA256: f3bdcd74612952da8476a9d4147f50b29ad0710b7dd95b4c8690500209986d70 -## - - -GlobalSign Root CA -================== ------BEGIN CERTIFICATE----- -MIIDdTCCAl2gAwIBAgILBAAAAAABFUtaw5QwDQYJKoZIhvcNAQEFBQAwVzELMAkGA1UEBhMCQkUx -GTAXBgNVBAoTEEdsb2JhbFNpZ24gbnYtc2ExEDAOBgNVBAsTB1Jvb3QgQ0ExGzAZBgNVBAMTEkds -b2JhbFNpZ24gUm9vdCBDQTAeFw05ODA5MDExMjAwMDBaFw0yODAxMjgxMjAwMDBaMFcxCzAJBgNV -BAYTAkJFMRkwFwYDVQQKExBHbG9iYWxTaWduIG52LXNhMRAwDgYDVQQLEwdSb290IENBMRswGQYD -VQQDExJHbG9iYWxTaWduIFJvb3QgQ0EwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDa -DuaZjc6j40+Kfvvxi4Mla+pIH/EqsLmVEQS98GPR4mdmzxzdzxtIK+6NiY6arymAZavpxy0Sy6sc -THAHoT0KMM0VjU/43dSMUBUc71DuxC73/OlS8pF94G3VNTCOXkNz8kHp1Wrjsok6Vjk4bwY8iGlb -Kk3Fp1S4bInMm/k8yuX9ifUSPJJ4ltbcdG6TRGHRjcdGsnUOhugZitVtbNV4FpWi6cgKOOvyJBNP -c1STE4U6G7weNLWLBYy5d4ux2x8gkasJU26Qzns3dLlwR5EiUWMWea6xrkEmCMgZK9FGqkjWZCrX -gzT/LCrBbBlDSgeF59N89iFo7+ryUp9/k5DPAgMBAAGjQjBAMA4GA1UdDwEB/wQEAwIBBjAPBgNV -HRMBAf8EBTADAQH/MB0GA1UdDgQWBBRge2YaRQ2XyolQL30EzTSo//z9SzANBgkqhkiG9w0BAQUF -AAOCAQEA1nPnfE920I2/7LqivjTFKDK1fPxsnCwrvQmeU79rXqoRSLblCKOzyj1hTdNGCbM+w6Dj -Y1Ub8rrvrTnhQ7k4o+YviiY776BQVvnGCv04zcQLcFGUl5gE38NflNUVyRRBnMRddWQVDf9VMOyG -j/8N7yy5Y0b2qvzfvGn9LhJIZJrglfCm7ymPAbEVtQwdpf5pLGkkeB6zpxxxYu7KyJesF12KwvhH -hm4qxFYxldBniYUr+WymXUadDKqC5JlR3XC321Y9YeRq4VzW9v493kHMB65jUr9TU/Qr6cf9tveC -X4XSQRjbgbMEHMUfpIBvFSDJ3gyICh3WZlXi/EjJKSZp4A== ------END CERTIFICATE----- - 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-DigiCert Global Root CA -======================= ------BEGIN CERTIFICATE----- -MIIDrzCCApegAwIBAgIQCDvgVpBCRrGhdWrJWZHHSjANBgkqhkiG9w0BAQUFADBhMQswCQYDVQQG -EwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3d3cuZGlnaWNlcnQuY29tMSAw -HgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBDQTAeFw0wNjExMTAwMDAwMDBaFw0zMTExMTAw -MDAwMDBaMGExCzAJBgNVBAYTAlVTMRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3 -dy5kaWdpY2VydC5jb20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IENBMIIBIjANBgkq -hkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA4jvhEXLeqKTTo1eqUKKPC3eQyaKl7hLOllsBCSDMAZOn -TjC3U/dDxGkAV53ijSLdhwZAAIEJzs4bg7/fzTtxRuLWZscFs3YnFo97nh6Vfe63SKMI2tavegw5 -BmV/Sl0fvBf4q77uKNd0f3p4mVmFaG5cIzJLv07A6Fpt43C/dxC//AH2hdmoRBBYMql1GNXRor5H -4idq9Joz+EkIYIvUX7Q6hL+hqkpMfT7PT19sdl6gSzeRntwi5m3OFBqOasv+zbMUZBfHWymeMr/y -7vrTC0LUq7dBMtoM1O/4gdW7jVg/tRvoSSiicNoxBN33shbyTApOB6jtSj1etX+jkMOvJwIDAQAB -o2MwYTAOBgNVHQ8BAf8EBAMCAYYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUA95QNVbRTLtm -8KPiGxvDl7I90VUwHwYDVR0jBBgwFoAUA95QNVbRTLtm8KPiGxvDl7I90VUwDQYJKoZIhvcNAQEF -BQADggEBAMucN6pIExIK+t1EnE9SsPTfrgT1eXkIoyQY/EsrhMAtudXH/vTBH1jLuG2cenTnmCmr -EbXjcKChzUyImZOMkXDiqw8cvpOp/2PV5Adg06O/nVsJ8dWO41P0jmP6P6fbtGbfYmbW0W5BjfIt -tep3Sp+dWOIrWcBAI+0tKIJFPnlUkiaY4IBIqDfv8NZ5YBberOgOzW6sRBc4L0na4UU+Krk2U886 -UAb3LujEV0lsYSEY1QSteDwsOoBrp+uvFRTp2InBuThs4pFsiv9kuXclVzDAGySj4dzp30d8tbQk -CAUw7C29C79Fv1C5qfPrmAESrciIxpg0X40KPMbp1ZWVbd4= ------END CERTIFICATE----- - -DigiCert High Assurance EV Root CA -================================== ------BEGIN CERTIFICATE----- -MIIDxTCCAq2gAwIBAgIQAqxcJmoLQJuPC3nyrkYldzANBgkqhkiG9w0BAQUFADBsMQswCQYDVQQG -EwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3d3cuZGlnaWNlcnQuY29tMSsw -KQYDVQQDEyJEaWdpQ2VydCBIaWdoIEFzc3VyYW5jZSBFViBSb290IENBMB4XDTA2MTExMDAwMDAw -MFoXDTMxMTExMDAwMDAwMFowbDELMAkGA1UEBhMCVVMxFTATBgNVBAoTDERpZ2lDZXJ0IEluYzEZ -MBcGA1UECxMQd3d3LmRpZ2ljZXJ0LmNvbTErMCkGA1UEAxMiRGlnaUNlcnQgSGlnaCBBc3N1cmFu -Y2UgRVYgUm9vdCBDQTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAMbM5XPm+9S75S0t -Mqbf5YE/yc0lSbZxKsPVlDRnogocsF9ppkCxxLeyj9CYpKlBWTrT3JTWPNt0OKRKzE0lgvdKpVMS -OO7zSW1xkX5jtqumX8OkhPhPYlG++MXs2ziS4wblCJEMxChBVfvLWokVfnHoNb9Ncgk9vjo4UFt3 -MRuNs8ckRZqnrG0AFFoEt7oT61EKmEFBIk5lYYeBQVCmeVyJ3hlKV9Uu5l0cUyx+mM0aBhakaHPQ -NAQTXKFx01p8VdteZOE3hzBWBOURtCmAEvF5OYiiAhF8J2a3iLd48soKqDirCmTCv2ZdlYTBoSUe -h10aUAsgEsxBu24LUTi4S8sCAwEAAaNjMGEwDgYDVR0PAQH/BAQDAgGGMA8GA1UdEwEB/wQFMAMB -Af8wHQYDVR0OBBYEFLE+w2kD+L9HAdSYJhoIAu9jZCvDMB8GA1UdIwQYMBaAFLE+w2kD+L9HAdSY -JhoIAu9jZCvDMA0GCSqGSIb3DQEBBQUAA4IBAQAcGgaX3NecnzyIZgYIVyHbIUf4KmeqvxgydkAQ -V8GK83rZEWWONfqe/EW1ntlMMUu4kehDLI6zeM7b41N5cdblIZQB2lWHmiRk9opmzN6cN82oNLFp -myPInngiK3BD41VHMWEZ71jFhS9OMPagMRYjyOfiZRYzy78aG6A9+MpeizGLYAiJLQwGXFK3xPkK -mNEVX58Svnw2Yzi9RKR/5CYrCsSXaQ3pjOLAEFe4yHYSkVXySGnYvCoCWw9E1CAx2/S6cCZdkGCe -vEsXCS+0yx5DaMkHJ8HSXPfqIbloEpw8nL+e/IBcm2PN7EeqJSdnoDfzAIJ9VNep+OkuE6N36B9K ------END CERTIFICATE----- - -DST Root CA X3 -============== ------BEGIN CERTIFICATE----- -MIIDSjCCAjKgAwIBAgIQRK+wgNajJ7qJMDmGLvhAazANBgkqhkiG9w0BAQUFADA/MSQwIgYDVQQK -ExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMTDkRTVCBSb290IENBIFgzMB4X -DTAwMDkzMDIxMTIxOVoXDTIxMDkzMDE0MDExNVowPzEkMCIGA1UEChMbRGlnaXRhbCBTaWduYXR1 -cmUgVHJ1c3QgQ28uMRcwFQYDVQQDEw5EU1QgUm9vdCBDQSBYMzCCASIwDQYJKoZIhvcNAQEBBQAD -ggEPADCCAQoCggEBAN+v6ZdQCINXtMxiZfaQguzH0yxrMMpb7NnDfcdAwRgUi+DoM3ZJKuM/IUmT -rE4Orz5Iy2Xu/NMhD2XSKtkyj4zl93ewEnu1lcCJo6m67XMuegwGMoOifooUMM0RoOEqOLl5CjH9 -UL2AZd+3UWODyOKIYepLYYHsUmu5ouJLGiifSKOeDNoJjj4XLh7dIN9bxiqKqy69cK3FCxolkHRy -xXtqqzTWMIn/5WgTe1QLyNau7Fqckh49ZLOMxt+/yUFw7BZy1SbsOFU5Q9D8/RhcQPGX69Wam40d -utolucbY38EVAjqr2m7xPi71XAicPNaDaeQQmxkqtilX4+U9m5/wAl0CAwEAAaNCMEAwDwYDVR0T -AQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFMSnsaR7LHH62+FLkHX/xBVghYkQ -MA0GCSqGSIb3DQEBBQUAA4IBAQCjGiybFwBcqR7uKGY3Or+Dxz9LwwmglSBd49lZRNI+DT69ikug -dB/OEIKcdBodfpga3csTS7MgROSR6cz8faXbauX+5v3gTt23ADq1cEmv8uXrAvHRAosZy5Q6XkjE -GB5YGV8eAlrwDPGxrancWYaLbumR9YbK+rlmM6pZW87ipxZzR8srzJmwN0jP41ZL9c8PDHIyh8bw -RLtTcm1D9SZImlJnt1ir/md2cXjbDaJWFBM5JDGFoqgCWjBH4d1QB7wCCZAA62RjYJsWvIjJEubS -fZGL+T0yjWW06XyxV3bqxbYoOb8VZRzI9neWagqNdwvYkQsEjgfbKbYK7p2CNTUQ ------END CERTIFICATE----- - -SwissSign Gold CA - G2 -====================== ------BEGIN CERTIFICATE----- -MIIFujCCA6KgAwIBAgIJALtAHEP1Xk+wMA0GCSqGSIb3DQEBBQUAMEUxCzAJBgNVBAYTAkNIMRUw -EwYDVQQKEwxTd2lzc1NpZ24gQUcxHzAdBgNVBAMTFlN3aXNzU2lnbiBHb2xkIENBIC0gRzIwHhcN -MDYxMDI1MDgzMDM1WhcNMzYxMDI1MDgzMDM1WjBFMQswCQYDVQQGEwJDSDEVMBMGA1UEChMMU3dp -c3NTaWduIEFHMR8wHQYDVQQDExZTd2lzc1NpZ24gR29sZCBDQSAtIEcyMIICIjANBgkqhkiG9w0B -AQEFAAOCAg8AMIICCgKCAgEAr+TufoskDhJuqVAtFkQ7kpJcyrhdhJJCEyq8ZVeCQD5XJM1QiyUq -t2/876LQwB8CJEoTlo8jE+YoWACjR8cGp4QjK7u9lit/VcyLwVcfDmJlD909Vopz2q5+bbqBHH5C -jCA12UNNhPqE21Is8w4ndwtrvxEvcnifLtg+5hg3Wipy+dpikJKVyh+c6bM8K8vzARO/Ws/BtQpg -vd21mWRTuKCWs2/iJneRjOBiEAKfNA+k1ZIzUd6+jbqEemA8atufK+ze3gE/bk3lUIbLtK/tREDF -ylqM2tIrfKjuvqblCqoOpd8FUrdVxyJdMmqXl2MT28nbeTZ7hTpKxVKJ+STnnXepgv9VHKVxaSvR -AiTysybUa9oEVeXBCsdtMDeQKuSeFDNeFhdVxVu1yzSJkvGdJo+hB9TGsnhQ2wwMC3wLjEHXuend -jIj3o02yMszYF9rNt85mndT9Xv+9lz4pded+p2JYryU0pUHHPbwNUMoDAw8IWh+Vc3hiv69yFGkO -peUDDniOJihC8AcLYiAQZzlG+qkDzAQ4embvIIO1jEpWjpEA/I5cgt6IoMPiaG59je883WX0XaxR -7ySArqpWl2/5rX3aYT+YdzylkbYcjCbaZaIJbcHiVOO5ykxMgI93e2CaHt+28kgeDrpOVG2Y4OGi -GqJ3UM/EY5LsRxmd6+ZrzsECAwEAAaOBrDCBqTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUw -AwEB/zAdBgNVHQ4EFgQUWyV7lqRlUX64OfPAeGZe6Drn8O4wHwYDVR0jBBgwFoAUWyV7lqRlUX64 -OfPAeGZe6Drn8O4wRgYDVR0gBD8wPTA7BglghXQBWQECAQEwLjAsBggrBgEFBQcCARYgaHR0cDov -L3JlcG9zaXRvcnkuc3dpc3NzaWduLmNvbS8wDQYJKoZIhvcNAQEFBQADggIBACe645R88a7A3hfm -5djV9VSwg/S7zV4Fe0+fdWavPOhWfvxyeDgD2StiGwC5+OlgzczOUYrHUDFu4Up+GC9pWbY9ZIEr -44OE5iKHjn3g7gKZYbge9LgriBIWhMIxkziWMaa5O1M/wySTVltpkuzFwbs4AOPsF6m43Md8AYOf -Mke6UiI0HTJ6CVanfCU2qT1L2sCCbwq7EsiHSycR+R4tx5M/nttfJmtS2S6K8RTGRI0Vqbe/vd6m -Gu6uLftIdxf+u+yvGPUqUfA5hJeVbG4bwyvEdGB5JbAKJ9/fXtI5z0V9QkvfsywexcZdylU6oJxp -mo/a77KwPJ+HbBIrZXAVUjEaJM9vMSNQH4xPjyPDdEFjHFWoFN0+4FFQz/EbMFYOkrCChdiDyyJk -vC24JdVUorgG6q2SpCSgwYa1ShNqR88uC1aVVMvOmttqtKay20EIhid392qgQmwLOM7XdVAyksLf -KzAiSNDVQTglXaTpXZ/GlHXQRf0wl0OPkKsKx4ZzYEppLd6leNcG2mqeSz53OiATIgHQv2ieY2Br -NU0LbbqhPcCT4H8js1WtciVORvnSFu+wZMEBnunKoGqYDs/YYPIvSbjkQuE4NRb0yG5P94FW6Lqj -viOvrv1vA+ACOzB2+httQc8Bsem4yWb02ybzOqR08kkkW8mw0FfB+j564ZfJ ------END CERTIFICATE----- - -SwissSign Silver CA - G2 -======================== ------BEGIN CERTIFICATE----- -MIIFvTCCA6WgAwIBAgIITxvUL1S7L0swDQYJKoZIhvcNAQEFBQAwRzELMAkGA1UEBhMCQ0gxFTAT -BgNVBAoTDFN3aXNzU2lnbiBBRzEhMB8GA1UEAxMYU3dpc3NTaWduIFNpbHZlciBDQSAtIEcyMB4X -DTA2MTAyNTA4MzI0NloXDTM2MTAyNTA4MzI0NlowRzELMAkGA1UEBhMCQ0gxFTATBgNVBAoTDFN3 -aXNzU2lnbiBBRzEhMB8GA1UEAxMYU3dpc3NTaWduIFNpbHZlciBDQSAtIEcyMIICIjANBgkqhkiG -9w0BAQEFAAOCAg8AMIICCgKCAgEAxPGHf9N4Mfc4yfjDmUO8x/e8N+dOcbpLj6VzHVxumK4DV644 -N0MvFz0fyM5oEMF4rhkDKxD6LHmD9ui5aLlV8gREpzn5/ASLHvGiTSf5YXu6t+WiE7brYT7QbNHm -+/pe7R20nqA1W6GSy/BJkv6FCgU+5tkL4k+73JU3/JHpMjUi0R86TieFnbAVlDLaYQ1HTWBCrpJH -6INaUFjpiou5XaHc3ZlKHzZnu0jkg7Y360g6rw9njxcH6ATK72oxh9TAtvmUcXtnZLi2kUpCe2Uu -MGoM9ZDulebyzYLs2aFK7PayS+VFheZteJMELpyCbTapxDFkH4aDCyr0NQp4yVXPQbBH6TCfmb5h -qAaEuSh6XzjZG6k4sIN/c8HDO0gqgg8hm7jMqDXDhBuDsz6+pJVpATqJAHgE2cn0mRmrVn5bi4Y5 -FZGkECwJMoBgs5PAKrYYC51+jUnyEEp/+dVGLxmSo5mnJqy7jDzmDrxHB9xzUfFwZC8I+bRHHTBs -ROopN4WSaGa8gzj+ezku01DwH/teYLappvonQfGbGHLy9YR0SslnxFSuSGTfjNFusB3hB48IHpmc -celM2KX3RxIfdNFRnobzwqIjQAtz20um53MGjMGg6cFZrEb65i/4z3GcRm25xBWNOHkDRUjvxF3X -CO6HOSKGsg0PWEP3calILv3q1h8CAwEAAaOBrDCBqTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/ -BAUwAwEB/zAdBgNVHQ4EFgQUF6DNweRBtjpbO8tFnb0cwpj6hlgwHwYDVR0jBBgwFoAUF6DNweRB -tjpbO8tFnb0cwpj6hlgwRgYDVR0gBD8wPTA7BglghXQBWQEDAQEwLjAsBggrBgEFBQcCARYgaHR0 -cDovL3JlcG9zaXRvcnkuc3dpc3NzaWduLmNvbS8wDQYJKoZIhvcNAQEFBQADggIBAHPGgeAn0i0P -4JUw4ppBf1AsX19iYamGamkYDHRJ1l2E6kFSGG9YrVBWIGrGvShpWJHckRE1qTodvBqlYJ7YH39F -kWnZfrt4csEGDyrOj4VwYaygzQu4OSlWhDJOhrs9xCrZ1x9y7v5RoSJBsXECYxqCsGKrXlcSH9/L -3XWgwF15kIwb4FDm3jH+mHtwX6WQ2K34ArZv02DdQEsixT2tOnqfGhpHkXkzuoLcMmkDlm4fS/Bx -/uNncqCxv1yL5PqZIseEuRuNI5c/7SXgz2W79WEE790eslpBIlqhn10s6FvJbakMDHiqYMZWjwFa -DGi8aRl5xB9+lwW/xekkUV7U1UtT7dkjWjYDZaPBA61BMPNGG4WQr2W11bHkFlt4dR2Xem1ZqSqP -e97Dh4kQmUlzeMg9vVE1dCrV8X5pGyq7O70luJpaPXJhkGaH7gzWTdQRdAtq/gsD/KNVV4n+Ssuu -WxcFyPKNIzFTONItaj+CuY0IavdeQXRuwxF+B6wpYJE/OMpXEA29MC/HpeZBoNquBYeaoKRlbEwJ -DIm6uNO5wJOKMPqN5ZprFQFOZ6raYlY+hAhm0sQ2fac+EPyI4NSA5QC9qvNOBqN6avlicuMJT+ub -DgEj8Z+7fNzcbBGXJbLytGMU0gYqZ4yD9c7qB9iaah7s5Aq7KkzrCWA5zspi2C5u ------END CERTIFICATE----- - -GeoTrust Primary Certification Authority -======================================== ------BEGIN CERTIFICATE----- -MIIDfDCCAmSgAwIBAgIQGKy1av1pthU6Y2yv2vrEoTANBgkqhkiG9w0BAQUFADBYMQswCQYDVQQG -EwJVUzEWMBQGA1UEChMNR2VvVHJ1c3QgSW5jLjExMC8GA1UEAxMoR2VvVHJ1c3QgUHJpbWFyeSBD -ZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNjExMjcwMDAwMDBaFw0zNjA3MTYyMzU5NTlaMFgx -CzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1HZW9UcnVzdCBJbmMuMTEwLwYDVQQDEyhHZW9UcnVzdCBQ -cmltYXJ5IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIB -CgKCAQEAvrgVe//UfH1nrYNke8hCUy3f9oQIIGHWAVlqnEQRr+92/ZV+zmEwu3qDXwK9AWbK7hWN -b6EwnL2hhZ6UOvNWiAAxz9juapYC2e0DjPt1befquFUWBRaa9OBesYjAZIVcFU2Ix7e64HXprQU9 -nceJSOC7KMgD4TCTZF5SwFlwIjVXiIrxlQqD17wxcwE07e9GceBrAqg1cmuXm2bgyxx5X9gaBGge -RwLmnWDiNpcB3841kt++Z8dtd1k7j53WkBWUvEI0EME5+bEnPn7WinXFsq+W06Lem+SYvn3h6YGt -tm/81w7a4DSwDRp35+MImO9Y+pyEtzavwt+s0vQQBnBxNQIDAQABo0IwQDAPBgNVHRMBAf8EBTAD -AQH/MA4GA1UdDwEB/wQEAwIBBjAdBgNVHQ4EFgQULNVQQZcVi/CPNmFbSvtr2ZnJM5IwDQYJKoZI -hvcNAQEFBQADggEBAFpwfyzdtzRP9YZRqSa+S7iq8XEN3GHHoOo0Hnp3DwQ16CePbJC/kRYkRj5K -Ts4rFtULUh38H2eiAkUxT87z+gOneZ1TatnaYzr4gNfTmeGl4b7UVXGYNTq+k+qurUKykG/g/CFN -NWMziUnWm07Kx+dOCQD32sfvmWKZd7aVIl6KoKv0uHiYyjgZmclynnjNS6yvGaBzEi38wkG6gZHa -Floxt/m0cYASSJlyc1pZU8FjUjPtp8nSOQJw+uCxQmYpqptR7TBUIhRf2asdweSU8Pj1K/fqynhG -1riR/aYNKxoUAT6A8EKglQdebc3MS6RFjasS6LPeWuWgfOgPIh1a6Vk= ------END CERTIFICATE----- - -thawte Primary Root CA -====================== ------BEGIN CERTIFICATE----- -MIIEIDCCAwigAwIBAgIQNE7VVyDV7exJ9C/ON9srbTANBgkqhkiG9w0BAQUFADCBqTELMAkGA1UE -BhMCVVMxFTATBgNVBAoTDHRoYXd0ZSwgSW5jLjEoMCYGA1UECxMfQ2VydGlmaWNhdGlvbiBTZXJ2 -aWNlcyBEaXZpc2lvbjE4MDYGA1UECxMvKGMpIDIwMDYgdGhhd3RlLCBJbmMuIC0gRm9yIGF1dGhv -cml6ZWQgdXNlIG9ubHkxHzAdBgNVBAMTFnRoYXd0ZSBQcmltYXJ5IFJvb3QgQ0EwHhcNMDYxMTE3 -MDAwMDAwWhcNMzYwNzE2MjM1OTU5WjCBqTELMAkGA1UEBhMCVVMxFTATBgNVBAoTDHRoYXd0ZSwg -SW5jLjEoMCYGA1UECxMfQ2VydGlmaWNhdGlvbiBTZXJ2aWNlcyBEaXZpc2lvbjE4MDYGA1UECxMv -KGMpIDIwMDYgdGhhd3RlLCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxHzAdBgNVBAMT -FnRoYXd0ZSBQcmltYXJ5IFJvb3QgQ0EwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCs -oPD7gFnUnMekz52hWXMJEEUMDSxuaPFsW0hoSVk3/AszGcJ3f8wQLZU0HObrTQmnHNK4yZc2AreJ -1CRfBsDMRJSUjQJib+ta3RGNKJpchJAQeg29dGYvajig4tVUROsdB58Hum/u6f1OCyn1PoSgAfGc -q/gcfomk6KHYcWUNo1F77rzSImANuVud37r8UVsLr5iy6S7pBOhih94ryNdOwUxkHt3Ph1i6Sk/K -aAcdHJ1KxtUvkcx8cXIcxcBn6zL9yZJclNqFwJu/U30rCfSMnZEfl2pSy94JNqR32HuHUETVPm4p -afs5SSYeCaWAe0At6+gnhcn+Yf1+5nyXHdWdAgMBAAGjQjBAMA8GA1UdEwEB/wQFMAMBAf8wDgYD -VR0PAQH/BAQDAgEGMB0GA1UdDgQWBBR7W0XPr87Lev0xkhpqtvNG61dIUDANBgkqhkiG9w0BAQUF -AAOCAQEAeRHAS7ORtvzw6WfUDW5FvlXok9LOAz/t2iWwHVfLHjp2oEzsUHboZHIMpKnxuIvW1oeE -uzLlQRHAd9mzYJ3rG9XRbkREqaYB7FViHXe4XI5ISXycO1cRrK1zN44veFyQaEfZYGDm/Ac9IiAX -xPcW6cTYcvnIc3zfFi8VqT79aie2oetaupgf1eNNZAqdE8hhuvU5HIe6uL17In/2/qxAeeWsEG89 -jxt5dovEN7MhGITlNgDrYyCZuen+MwS7QcjBAvlEYyCegc5C09Y/LHbTY5xZ3Y+m4Q6gLkH3LpVH -z7z9M/P2C2F+fpErgUfCJzDupxBdN49cOSvkBPB7jVaMaA== ------END CERTIFICATE----- - -VeriSign Class 3 Public Primary Certification Authority - G5 -============================================================ ------BEGIN CERTIFICATE----- -MIIE0zCCA7ugAwIBAgIQGNrRniZ96LtKIVjNzGs7SjANBgkqhkiG9w0BAQUFADCByjELMAkGA1UE -BhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZWZXJpU2lnbiBUcnVzdCBO -ZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNiBWZXJpU2lnbiwgSW5jLiAtIEZvciBhdXRob3JpemVk -IHVzZSBvbmx5MUUwQwYDVQQDEzxWZXJpU2lnbiBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5IENlcnRp -ZmljYXRpb24gQXV0aG9yaXR5IC0gRzUwHhcNMDYxMTA4MDAwMDAwWhcNMzYwNzE2MjM1OTU5WjCB -yjELMAkGA1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZWZXJpU2ln -biBUcnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNiBWZXJpU2lnbiwgSW5jLiAtIEZvciBh -dXRob3JpemVkIHVzZSBvbmx5MUUwQwYDVQQDEzxWZXJpU2lnbiBDbGFzcyAzIFB1YmxpYyBQcmlt -YXJ5IENlcnRpZmljYXRpb24gQXV0aG9yaXR5IC0gRzUwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAw -ggEKAoIBAQCvJAgIKXo1nmAMqudLO07cfLw8RRy7K+D+KQL5VwijZIUVJ/XxrcgxiV0i6CqqpkKz -j/i5Vbext0uz/o9+B1fs70PbZmIVYc9gDaTY3vjgw2IIPVQT60nKWVSFJuUrjxuf6/WhkcIzSdhD -Y2pSS9KP6HBRTdGJaXvHcPaz3BJ023tdS1bTlr8Vd6Gw9KIl8q8ckmcY5fQGBO+QueQA5N06tRn/ -Arr0PO7gi+s3i+z016zy9vA9r911kTMZHRxAy3QkGSGT2RT+rCpSx4/VBEnkjWNHiDxpg8v+R70r -fk/Fla4OndTRQ8Bnc+MUCH7lP59zuDMKz10/NIeWiu5T6CUVAgMBAAGjgbIwga8wDwYDVR0TAQH/ -BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwbQYIKwYBBQUHAQwEYTBfoV2gWzBZMFcwVRYJaW1hZ2Uv -Z2lmMCEwHzAHBgUrDgMCGgQUj+XTGoasjY5rw8+AatRIGCx7GS4wJRYjaHR0cDovL2xvZ28udmVy -aXNpZ24uY29tL3ZzbG9nby5naWYwHQYDVR0OBBYEFH/TZafC3ey78DAJ80M5+gKvMzEzMA0GCSqG -SIb3DQEBBQUAA4IBAQCTJEowX2LP2BqYLz3q3JktvXf2pXkiOOzEp6B4Eq1iDkVwZMXnl2YtmAl+ -X6/WzChl8gGqCBpH3vn5fJJaCGkgDdk+bW48DW7Y5gaRQBi5+MHt39tBquCWIMnNZBU4gcmU7qKE -KQsTb47bDN0lAtukixlE0kF6BWlKWE9gyn6CagsCqiUXObXbf+eEZSqVir2G3l6BFoMtEMze/aiC -Km0oHw0LxOXnGiYZ4fQRbxC1lfznQgUy286dUV4otp6F01vvpX1FQHKOtw5rDgb7MzVIcbidJ4vE -ZV8NhnacRHr2lVz2XTIIM6RUthg/aFzyQkqFOFSDX9HoLPKsEdao7WNq ------END CERTIFICATE----- - -SecureTrust CA -============== ------BEGIN CERTIFICATE----- -MIIDuDCCAqCgAwIBAgIQDPCOXAgWpa1Cf/DrJxhZ0DANBgkqhkiG9w0BAQUFADBIMQswCQYDVQQG -EwJVUzEgMB4GA1UEChMXU2VjdXJlVHJ1c3QgQ29ycG9yYXRpb24xFzAVBgNVBAMTDlNlY3VyZVRy -dXN0IENBMB4XDTA2MTEwNzE5MzExOFoXDTI5MTIzMTE5NDA1NVowSDELMAkGA1UEBhMCVVMxIDAe -BgNVBAoTF1NlY3VyZVRydXN0IENvcnBvcmF0aW9uMRcwFQYDVQQDEw5TZWN1cmVUcnVzdCBDQTCC -ASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKukgeWVzfX2FI7CT8rU4niVWJxB4Q2ZQCQX -OZEzZum+4YOvYlyJ0fwkW2Gz4BERQRwdbvC4u/jep4G6pkjGnx29vo6pQT64lO0pGtSO0gMdA+9t -DWccV9cGrcrI9f4Or2YlSASWC12juhbDCE/RRvgUXPLIXgGZbf2IzIaowW8xQmxSPmjL8xk037uH -GFaAJsTQ3MBv396gwpEWoGQRS0S8Hvbn+mPeZqx2pHGj7DaUaHp3pLHnDi+BeuK1cobvomuL8A/b -01k/unK8RCSc43Oz969XL0Imnal0ugBS8kvNU3xHCzaFDmapCJcWNFfBZveA4+1wVMeT4C4oFVmH -ursCAwEAAaOBnTCBmjATBgkrBgEEAYI3FAIEBh4EAEMAQTALBgNVHQ8EBAMCAYYwDwYDVR0TAQH/ -BAUwAwEB/zAdBgNVHQ4EFgQUQjK2FvoE/f5dS3rD/fdMQB1aQ68wNAYDVR0fBC0wKzApoCegJYYj -aHR0cDovL2NybC5zZWN1cmV0cnVzdC5jb20vU1RDQS5jcmwwEAYJKwYBBAGCNxUBBAMCAQAwDQYJ -KoZIhvcNAQEFBQADggEBADDtT0rhWDpSclu1pqNlGKa7UTt36Z3q059c4EVlew3KW+JwULKUBRSu -SceNQQcSc5R+DCMh/bwQf2AQWnL1mA6s7Ll/3XpvXdMc9P+IBWlCqQVxyLesJugutIxq/3HcuLHf -mbx8IVQr5Fiiu1cprp6poxkmD5kuCLDv/WnPmRoJjeOnnyvJNjR7JLN4TJUXpAYmHrZkUjZfYGfZ -nMUFdAvnZyPSCPyI6a6Lf+Ew9Dd+/cYy2i2eRDAwbO4H3tI0/NL/QPZL9GZGBlSm8jIKYyYwa5vR -3ItHuuG51WLQoqD0ZwV4KWMabwTW+MZMo5qxN7SN5ShLHZ4swrhovO0C7jE= ------END CERTIFICATE----- - -Secure Global CA -================ ------BEGIN CERTIFICATE----- -MIIDvDCCAqSgAwIBAgIQB1YipOjUiolN9BPI8PjqpTANBgkqhkiG9w0BAQUFADBKMQswCQYDVQQG -EwJVUzEgMB4GA1UEChMXU2VjdXJlVHJ1c3QgQ29ycG9yYXRpb24xGTAXBgNVBAMTEFNlY3VyZSBH -bG9iYWwgQ0EwHhcNMDYxMTA3MTk0MjI4WhcNMjkxMjMxMTk1MjA2WjBKMQswCQYDVQQGEwJVUzEg -MB4GA1UEChMXU2VjdXJlVHJ1c3QgQ29ycG9yYXRpb24xGTAXBgNVBAMTEFNlY3VyZSBHbG9iYWwg -Q0EwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCvNS7YrGxVaQZx5RNoJLNP2MwhR/jx -YDiJiQPpvepeRlMJ3Fz1Wuj3RSoC6zFh1ykzTM7HfAo3fg+6MpjhHZevj8fcyTiW89sa/FHtaMbQ -bqR8JNGuQsiWUGMu4P51/pinX0kuleM5M2SOHqRfkNJnPLLZ/kG5VacJjnIFHovdRIWCQtBJwB1g -8NEXLJXr9qXBkqPFwqcIYA1gBBCWeZ4WNOaptvolRTnIHmX5k/Wq8VLcmZg9pYYaDDUz+kulBAYV -HDGA76oYa8J719rO+TMg1fW9ajMtgQT7sFzUnKPiXB3jqUJ1XnvUd+85VLrJChgbEplJL4hL/VBi -0XPnj3pDAgMBAAGjgZ0wgZowEwYJKwYBBAGCNxQCBAYeBABDAEEwCwYDVR0PBAQDAgGGMA8GA1Ud -EwEB/wQFMAMBAf8wHQYDVR0OBBYEFK9EBMJBfkiD2045AuzshHrmzsmkMDQGA1UdHwQtMCswKaAn -oCWGI2h0dHA6Ly9jcmwuc2VjdXJldHJ1c3QuY29tL1NHQ0EuY3JsMBAGCSsGAQQBgjcVAQQDAgEA -MA0GCSqGSIb3DQEBBQUAA4IBAQBjGghAfaReUw132HquHw0LURYD7xh8yOOvaliTFGCRsoTciE6+ -OYo68+aCiV0BN7OrJKQVDpI1WkpEXk5X+nXOH0jOZvQ8QCaSmGwb7iRGDBezUqXbpZGRzzfTb+cn -CDpOGR86p1hcF895P4vkp9MmI50mD1hp/Ed+stCNi5O/KU9DaXR2Z0vPB4zmAve14bRDtUstFJ/5 -3CYNv6ZHdAbYiNE6KTCEztI5gGIbqMdXSbxqVVFnFUq+NQfk1XWYN3kwFNspnWzFacxHVaIw98xc -f8LDmBxrThaA63p4ZUWiABqvDA1VZDRIuJK58bRQKfJPIx/abKwfROHdI3hRW8cW ------END CERTIFICATE----- - -COMODO Certification Authority -============================== ------BEGIN CERTIFICATE----- -MIIEHTCCAwWgAwIBAgIQToEtioJl4AsC7j41AkblPTANBgkqhkiG9w0BAQUFADCBgTELMAkGA1UE -BhMCR0IxGzAZBgNVBAgTEkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UEBxMHU2FsZm9yZDEaMBgG -A1UEChMRQ09NT0RPIENBIExpbWl0ZWQxJzAlBgNVBAMTHkNPTU9ETyBDZXJ0aWZpY2F0aW9uIEF1 -dGhvcml0eTAeFw0wNjEyMDEwMDAwMDBaFw0yOTEyMzEyMzU5NTlaMIGBMQswCQYDVQQGEwJHQjEb -MBkGA1UECBMSR3JlYXRlciBNYW5jaGVzdGVyMRAwDgYDVQQHEwdTYWxmb3JkMRowGAYDVQQKExFD -T01PRE8gQ0EgTGltaXRlZDEnMCUGA1UEAxMeQ09NT0RPIENlcnRpZmljYXRpb24gQXV0aG9yaXR5 -MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA0ECLi3LjkRv3UcEbVASY06m/weaKXTuH -+7uIzg3jLz8GlvCiKVCZrts7oVewdFFxze1CkU1B/qnI2GqGd0S7WWaXUF601CxwRM/aN5VCaTww -xHGzUvAhTaHYujl8HJ6jJJ3ygxaYqhZ8Q5sVW7euNJH+1GImGEaaP+vB+fGQV+useg2L23IwambV -4EajcNxo2f8ESIl33rXp+2dtQem8Ob0y2WIC8bGoPW43nOIv4tOiJovGuFVDiOEjPqXSJDlqR6sA -1KGzqSX+DT+nHbrTUcELpNqsOO9VUCQFZUaTNE8tja3G1CEZ0o7KBWFxB3NH5YoZEr0ETc5OnKVI -rLsm9wIDAQABo4GOMIGLMB0GA1UdDgQWBBQLWOWLxkwVN6RAqTCpIb5HNlpW/zAOBgNVHQ8BAf8E -BAMCAQYwDwYDVR0TAQH/BAUwAwEB/zBJBgNVHR8EQjBAMD6gPKA6hjhodHRwOi8vY3JsLmNvbW9k -b2NhLmNvbS9DT01PRE9DZXJ0aWZpY2F0aW9uQXV0aG9yaXR5LmNybDANBgkqhkiG9w0BAQUFAAOC -AQEAPpiem/Yb6dc5t3iuHXIYSdOH5EOC6z/JqvWote9VfCFSZfnVDeFs9D6Mk3ORLgLETgdxb8CP -OGEIqB6BCsAvIC9Bi5HcSEW88cbeunZrM8gALTFGTO3nnc+IlP8zwFboJIYmuNg4ON8qa90SzMc/ -RxdMosIGlgnW2/4/PEZB31jiVg88O8EckzXZOFKs7sjsLjBOlDW0JB9LeGna8gI4zJVSk/BwJVmc -IGfE7vmLV2H0knZ9P4SNVbfo5azV8fUZVqZa+5Acr5Pr5RzUZ5ddBA6+C4OmF4O5MBKgxTMVBbkN -+8cFduPYSo38NBejxiEovjBFMR7HeL5YYTisO+IBZQ== ------END CERTIFICATE----- - -Network Solutions Certificate Authority -======================================= ------BEGIN CERTIFICATE----- -MIID5jCCAs6gAwIBAgIQV8szb8JcFuZHFhfjkDFo4DANBgkqhkiG9w0BAQUFADBiMQswCQYDVQQG -EwJVUzEhMB8GA1UEChMYTmV0d29yayBTb2x1dGlvbnMgTC5MLkMuMTAwLgYDVQQDEydOZXR3b3Jr -IFNvbHV0aW9ucyBDZXJ0aWZpY2F0ZSBBdXRob3JpdHkwHhcNMDYxMjAxMDAwMDAwWhcNMjkxMjMx -MjM1OTU5WjBiMQswCQYDVQQGEwJVUzEhMB8GA1UEChMYTmV0d29yayBTb2x1dGlvbnMgTC5MLkMu -MTAwLgYDVQQDEydOZXR3b3JrIFNvbHV0aW9ucyBDZXJ0aWZpY2F0ZSBBdXRob3JpdHkwggEiMA0G -CSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDkvH6SMG3G2I4rC7xGzuAnlt7e+foS0zwzc7MEL7xx -jOWftiJgPl9dzgn/ggwbmlFQGiaJ3dVhXRncEg8tCqJDXRfQNJIg6nPPOCwGJgl6cvf6UDL4wpPT -aaIjzkGxzOTVHzbRijr4jGPiFFlp7Q3Tf2vouAPlT2rlmGNpSAW+Lv8ztumXWWn4Zxmuk2GWRBXT -crA/vGp97Eh/jcOrqnErU2lBUzS1sLnFBgrEsEX1QV1uiUV7PTsmjHTC5dLRfbIR1PtYMiKagMnc -/Qzpf14Dl847ABSHJ3A4qY5usyd2mFHgBeMhqxrVhSI8KbWaFsWAqPS7azCPL0YCorEMIuDTAgMB -AAGjgZcwgZQwHQYDVR0OBBYEFCEwyfsA106Y2oeqKtCnLrFAMadMMA4GA1UdDwEB/wQEAwIBBjAP -BgNVHRMBAf8EBTADAQH/MFIGA1UdHwRLMEkwR6BFoEOGQWh0dHA6Ly9jcmwubmV0c29sc3NsLmNv -bS9OZXR3b3JrU29sdXRpb25zQ2VydGlmaWNhdGVBdXRob3JpdHkuY3JsMA0GCSqGSIb3DQEBBQUA -A4IBAQC7rkvnt1frf6ott3NHhWrB5KUd5Oc86fRZZXe1eltajSU24HqXLjjAV2CDmAaDn7l2em5Q -4LqILPxFzBiwmZVRDuwduIj/h1AcgsLj4DKAv6ALR8jDMe+ZZzKATxcheQxpXN5eNK4CtSbqUN9/ -GGUsyfJj4akH/nxxH2szJGoeBfcFaMBqEssuXmHLrijTfsK0ZpEmXzwuJF/LWA/rKOyvEZbz3Htv -wKeI8lN3s2Berq4o2jUsbzRF0ybh3uxbTydrFny9RAQYgrOJeRcQcT16ohZO9QHNpGxlaKFJdlxD -ydi8NmdspZS11My5vWo1ViHe2MPr+8ukYEywVaCge1ey ------END CERTIFICATE----- - -COMODO ECC Certification Authority -================================== ------BEGIN CERTIFICATE----- -MIICiTCCAg+gAwIBAgIQH0evqmIAcFBUTAGem2OZKjAKBggqhkjOPQQDAzCBhTELMAkGA1UEBhMC -R0IxGzAZBgNVBAgTEkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UEBxMHU2FsZm9yZDEaMBgGA1UE -ChMRQ09NT0RPIENBIExpbWl0ZWQxKzApBgNVBAMTIkNPTU9ETyBFQ0MgQ2VydGlmaWNhdGlvbiBB -dXRob3JpdHkwHhcNMDgwMzA2MDAwMDAwWhcNMzgwMTE4MjM1OTU5WjCBhTELMAkGA1UEBhMCR0Ix -GzAZBgNVBAgTEkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UEBxMHU2FsZm9yZDEaMBgGA1UEChMR -Q09NT0RPIENBIExpbWl0ZWQxKzApBgNVBAMTIkNPTU9ETyBFQ0MgQ2VydGlmaWNhdGlvbiBBdXRo -b3JpdHkwdjAQBgcqhkjOPQIBBgUrgQQAIgNiAAQDR3svdcmCFYX7deSRFtSrYpn1PlILBs5BAH+X -4QokPB0BBO490o0JlwzgdeT6+3eKKvUDYEs2ixYjFq0JcfRK9ChQtP6IHG4/bC8vCVlbpVsLM5ni -wz2J+Wos77LTBumjQjBAMB0GA1UdDgQWBBR1cacZSBm8nZ3qQUfflMRId5nTeTAOBgNVHQ8BAf8E -BAMCAQYwDwYDVR0TAQH/BAUwAwEB/zAKBggqhkjOPQQDAwNoADBlAjEA7wNbeqy3eApyt4jf/7VG -FAkK+qDmfQjGGoe9GKhzvSbKYAydzpmfz1wPMOG+FDHqAjAU9JM8SaczepBGR7NjfRObTrdvGDeA -U/7dIOA1mjbRxwG55tzd8/8dLDoWV9mSOdY= ------END CERTIFICATE----- - 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-Certigna -======== ------BEGIN CERTIFICATE----- -MIIDqDCCApCgAwIBAgIJAP7c4wEPyUj/MA0GCSqGSIb3DQEBBQUAMDQxCzAJBgNVBAYTAkZSMRIw -EAYDVQQKDAlEaGlteW90aXMxETAPBgNVBAMMCENlcnRpZ25hMB4XDTA3MDYyOTE1MTMwNVoXDTI3 -MDYyOTE1MTMwNVowNDELMAkGA1UEBhMCRlIxEjAQBgNVBAoMCURoaW15b3RpczERMA8GA1UEAwwI -Q2VydGlnbmEwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDIaPHJ1tazNHUmgh7stL7q -XOEm7RFHYeGifBZ4QCHkYJ5ayGPhxLGWkv8YbWkj4Sti993iNi+RB7lIzw7sebYs5zRLcAglozyH -GxnygQcPOJAZ0xH+hrTy0V4eHpbNgGzOOzGTtvKg0KmVEn2lmsxryIRWijOp5yIVUxbwzBfsV1/p -ogqYCd7jX5xv3EjjhQsVWqa6n6xI4wmy9/Qy3l40vhx4XUJbzg4ij02Q130yGLMLLGq/jj8UEYkg -DncUtT2UCIf3JR7VsmAA7G8qKCVuKj4YYxclPz5EIBb2JsglrgVKtOdjLPOMFlN+XPsRGgjBRmKf -Irjxwo1p3Po6WAbfAgMBAAGjgbwwgbkwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUGu3+QTmQ -tCRZvgHyUtVF9lo53BEwZAYDVR0jBF0wW4AUGu3+QTmQtCRZvgHyUtVF9lo53BGhOKQ2MDQxCzAJ -BgNVBAYTAkZSMRIwEAYDVQQKDAlEaGlteW90aXMxETAPBgNVBAMMCENlcnRpZ25hggkA/tzjAQ/J -SP8wDgYDVR0PAQH/BAQDAgEGMBEGCWCGSAGG+EIBAQQEAwIABzANBgkqhkiG9w0BAQUFAAOCAQEA -hQMeknH2Qq/ho2Ge6/PAD/Kl1NqV5ta+aDY9fm4fTIrv0Q8hbV6lUmPOEvjvKtpv6zf+EwLHyzs+ -ImvaYS5/1HI93TDhHkxAGYwP15zRgzB7mFncfca5DClMoTOi62c6ZYTTluLtdkVwj7Ur3vkj1klu -PBS1xp81HlDQwY9qcEQCYsuuHWhBp6pX6FOqB9IG9tUUBguRA3UsbHK1YZWaDYu5Def131TN3ubY -1gkIl2PlwS6wt0QmwCbAr1UwnjvVNioZBPRcHv/PLLf/0P2HQBHVESO7SMAhqaQoLf0V+LBOK/Qw -WyH8EZE0vkHve52Xdf+XlcCWWC/qu0bXu+TZLg== ------END CERTIFICATE----- - -Cybertrust Global Root -====================== ------BEGIN CERTIFICATE----- -MIIDoTCCAomgAwIBAgILBAAAAAABD4WqLUgwDQYJKoZIhvcNAQEFBQAwOzEYMBYGA1UEChMPQ3li -ZXJ0cnVzdCwgSW5jMR8wHQYDVQQDExZDeWJlcnRydXN0IEdsb2JhbCBSb290MB4XDTA2MTIxNTA4 -MDAwMFoXDTIxMTIxNTA4MDAwMFowOzEYMBYGA1UEChMPQ3liZXJ0cnVzdCwgSW5jMR8wHQYDVQQD -ExZDeWJlcnRydXN0IEdsb2JhbCBSb290MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA -+Mi8vRRQZhP/8NN57CPytxrHjoXxEnOmGaoQ25yiZXRadz5RfVb23CO21O1fWLE3TdVJDm71aofW -0ozSJ8bi/zafmGWgE07GKmSb1ZASzxQG9Dvj1Ci+6A74q05IlG2OlTEQXO2iLb3VOm2yHLtgwEZL -AfVJrn5GitB0jaEMAs7u/OePuGtm839EAL9mJRQr3RAwHQeWP032a7iPt3sMpTjr3kfb1V05/Iin -89cqdPHoWqI7n1C6poxFNcJQZZXcY4Lv3b93TZxiyWNzFtApD0mpSPCzqrdsxacwOUBdrsTiXSZT -8M4cIwhhqJQZugRiQOwfOHB3EgZxpzAYXSUnpQIDAQABo4GlMIGiMA4GA1UdDwEB/wQEAwIBBjAP -BgNVHRMBAf8EBTADAQH/MB0GA1UdDgQWBBS2CHsNesysIEyGVjJez6tuhS1wVzA/BgNVHR8EODA2 -MDSgMqAwhi5odHRwOi8vd3d3Mi5wdWJsaWMtdHJ1c3QuY29tL2NybC9jdC9jdHJvb3QuY3JsMB8G -A1UdIwQYMBaAFLYIew16zKwgTIZWMl7Pq26FLXBXMA0GCSqGSIb3DQEBBQUAA4IBAQBW7wojoFRO -lZfJ+InaRcHUowAl9B8Tq7ejhVhpwjCt2BWKLePJzYFa+HMjWqd8BfP9IjsO0QbE2zZMcwSO5bAi -5MXzLqXZI+O4Tkogp24CJJ8iYGd7ix1yCcUxXOl5n4BHPa2hCwcUPUf/A2kaDAtE52Mlp3+yybh2 -hO0j9n0Hq0V+09+zv+mKts2oomcrUtW3ZfA5TGOgkXmTUg9U3YO7n9GPp1Nzw8v/MOx8BLjYRB+T -X3EJIrduPuocA06dGiBh+4E37F78CkWr1+cXVdCg6mCbpvbjjFspwgZgFJ0tl0ypkxWdYcQBX0jW -WL1WMRJOEcgh4LMRkWXbtKaIOM5V ------END CERTIFICATE----- - -ePKI Root Certification Authority -================================= ------BEGIN CERTIFICATE----- -MIIFsDCCA5igAwIBAgIQFci9ZUdcr7iXAF7kBtK8nTANBgkqhkiG9w0BAQUFADBeMQswCQYDVQQG -EwJUVzEjMCEGA1UECgwaQ2h1bmdod2EgVGVsZWNvbSBDby4sIEx0ZC4xKjAoBgNVBAsMIWVQS0kg -Um9vdCBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNDEyMjAwMjMxMjdaFw0zNDEyMjAwMjMx -MjdaMF4xCzAJBgNVBAYTAlRXMSMwIQYDVQQKDBpDaHVuZ2h3YSBUZWxlY29tIENvLiwgTHRkLjEq -MCgGA1UECwwhZVBLSSBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MIICIjANBgkqhkiG9w0B -AQEFAAOCAg8AMIICCgKCAgEA4SUP7o3biDN1Z82tH306Tm2d0y8U82N0ywEhajfqhFAHSyZbCUNs -IZ5qyNUD9WBpj8zwIuQf5/dqIjG3LBXy4P4AakP/h2XGtRrBp0xtInAhijHyl3SJCRImHJ7K2RKi -lTza6We/CKBk49ZCt0Xvl/T29de1ShUCWH2YWEtgvM3XDZoTM1PRYfl61dd4s5oz9wCGzh1NlDiv -qOx4UXCKXBCDUSH3ET00hl7lSM2XgYI1TBnsZfZrxQWh7kcT1rMhJ5QQCtkkO7q+RBNGMD+XPNjX -12ruOzjjK9SXDrkb5wdJfzcq+Xd4z1TtW0ado4AOkUPB1ltfFLqfpo0kR0BZv3I4sjZsN/+Z0V0O -WQqraffAsgRFelQArr5T9rXn4fg8ozHSqf4hUmTFpmfwdQcGlBSBVcYn5AGPF8Fqcde+S/uUWH1+ -ETOxQvdibBjWzwloPn9s9h6PYq2lY9sJpx8iQkEeb5mKPtf5P0B6ebClAZLSnT0IFaUQAS2zMnao -lQ2zepr7BxB4EW/hj8e6DyUadCrlHJhBmd8hh+iVBmoKs2pHdmX2Os+PYhcZewoozRrSgx4hxyy/ -vv9haLdnG7t4TY3OZ+XkwY63I2binZB1NJipNiuKmpS5nezMirH4JYlcWrYvjB9teSSnUmjDhDXi -Zo1jDiVN1Rmy5nk3pyKdVDECAwEAAaNqMGgwHQYDVR0OBBYEFB4M97Zn8uGSJglFwFU5Lnc/Qkqi -MAwGA1UdEwQFMAMBAf8wOQYEZyoHAAQxMC8wLQIBADAJBgUrDgMCGgUAMAcGBWcqAwAABBRFsMLH -ClZ87lt4DJX5GFPBphzYEDANBgkqhkiG9w0BAQUFAAOCAgEACbODU1kBPpVJufGBuvl2ICO1J2B0 -1GqZNF5sAFPZn/KmsSQHRGoqxqWOeBLoR9lYGxMqXnmbnwoqZ6YlPwZpVnPDimZI+ymBV3QGypzq -KOg4ZyYr8dW1P2WT+DZdjo2NQCCHGervJ8A9tDkPJXtoUHRVnAxZfVo9QZQlUgjgRywVMRnVvwdV -xrsStZf0X4OFunHB2WyBEXYKCrC/gpf36j36+uwtqSiUO1bd0lEursC9CBWMd1I0ltabrNMdjmEP -NXubrjlpC2JgQCA2j6/7Nu4tCEoduL+bXPjqpRugc6bY+G7gMwRfaKonh+3ZwZCc7b3jajWvY9+r -GNm65ulK6lCKD2GTHuItGeIwlDWSXQ62B68ZgI9HkFFLLk3dheLSClIKF5r8GrBQAuUBo2M3IUxE -xJtRmREOc5wGj1QupyheRDmHVi03vYVElOEMSyycw5KFNGHLD7ibSkNS/jQ6fbjpKdx2qcgw+BRx -gMYeNkh0IkFch4LoGHGLQYlE535YW6i4jRPpp2zDR+2zGp1iro2C6pSe3VkQw63d4k3jMdXH7Ojy -sP6SHhYKGvzZ8/gntsm+HbRsZJB/9OTEW9c3rkIO3aQab3yIVMUWbuF6aC74Or8NpDyJO3inTmOD -BCEIZ43ygknQW/2xzQ+DhNQ+IIX3Sj0rnP0qCglN6oH4EZw= ------END CERTIFICATE----- - -certSIGN ROOT CA -================ ------BEGIN CERTIFICATE----- -MIIDODCCAiCgAwIBAgIGIAYFFnACMA0GCSqGSIb3DQEBBQUAMDsxCzAJBgNVBAYTAlJPMREwDwYD -VQQKEwhjZXJ0U0lHTjEZMBcGA1UECxMQY2VydFNJR04gUk9PVCBDQTAeFw0wNjA3MDQxNzIwMDRa -Fw0zMTA3MDQxNzIwMDRaMDsxCzAJBgNVBAYTAlJPMREwDwYDVQQKEwhjZXJ0U0lHTjEZMBcGA1UE -CxMQY2VydFNJR04gUk9PVCBDQTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALczuX7I -JUqOtdu0KBuqV5Do0SLTZLrTk+jUrIZhQGpgV2hUhE28alQCBf/fm5oqrl0Hj0rDKH/v+yv6efHH -rfAQUySQi2bJqIirr1qjAOm+ukbuW3N7LBeCgV5iLKECZbO9xSsAfsT8AzNXDe3i+s5dRdY4zTW2 -ssHQnIFKquSyAVwdj1+ZxLGt24gh65AIgoDzMKND5pCCrlUoSe1b16kQOA7+j0xbm0bqQfWwCHTD -0IgztnzXdN/chNFDDnU5oSVAKOp4yw4sLjmdjItuFhwvJoIQ4uNllAoEwF73XVv4EOLQunpL+943 -AAAaWyjj0pxzPjKHmKHJUS/X3qwzs08CAwEAAaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8B -Af8EBAMCAcYwHQYDVR0OBBYEFOCMm9slSbPxfIbWskKHC9BroNnkMA0GCSqGSIb3DQEBBQUAA4IB -AQA+0hyJLjX8+HXd5n9liPRyTMks1zJO890ZeUe9jjtbkw9QSSQTaxQGcu8J06Gh40CEyecYMnQ8 -SG4Pn0vU9x7Tk4ZkVJdjclDVVc/6IJMCopvDI5NOFlV2oHB5bc0hH88vLbwZ44gx+FkagQnIl6Z0 -x2DEW8xXjrJ1/RsCCdtZb3KTafcxQdaIOL+Hsr0Wefmq5L6IJd1hJyMctTEHBDa0GpC9oHRxUIlt -vBTjD4au8as+x6AJzKNI0eDbZOeStc+vckNwi/nDhDwTqn6Sm1dTk/pwwpEOMfmbZ13pljheX7Nz -TogVZ96edhBiIL5VaZVDADlN9u6wWk5JRFRYX0KD ------END CERTIFICATE----- - -GeoTrust Primary Certification Authority - G3 -============================================= ------BEGIN CERTIFICATE----- -MIID/jCCAuagAwIBAgIQFaxulBmyeUtB9iepwxgPHzANBgkqhkiG9w0BAQsFADCBmDELMAkGA1UE -BhMCVVMxFjAUBgNVBAoTDUdlb1RydXN0IEluYy4xOTA3BgNVBAsTMChjKSAyMDA4IEdlb1RydXN0 -IEluYy4gLSBGb3IgYXV0aG9yaXplZCB1c2Ugb25seTE2MDQGA1UEAxMtR2VvVHJ1c3QgUHJpbWFy -eSBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eSAtIEczMB4XDTA4MDQwMjAwMDAwMFoXDTM3MTIwMTIz -NTk1OVowgZgxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1HZW9UcnVzdCBJbmMuMTkwNwYDVQQLEzAo -YykgMjAwOCBHZW9UcnVzdCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxNjA0BgNVBAMT -LUdlb1RydXN0IFByaW1hcnkgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgLSBHMzCCASIwDQYJKoZI -hvcNAQEBBQADggEPADCCAQoCggEBANziXmJYHTNXOTIz+uvLh4yn1ErdBojqZI4xmKU4kB6Yzy5j -K/BGvESyiaHAKAxJcCGVn2TAppMSAmUmhsalifD614SgcK9PGpc/BkTVyetyEH3kMSj7HGHmKAdE -c5IiaacDiGydY8hS2pgn5whMcD60yRLBxWeDXTPzAxHsatBT4tG6NmCUgLthY2xbF37fQJQeqw3C -IShwiP/WJmxsYAQlTlV+fe+/lEjetx3dcI0FX4ilm/LC7urRQEFtYjgdVgbFA0dRIBn8exALDmKu -dlW/X3e+PkkBUz2YJQN2JFodtNuJ6nnltrM7P7pMKEF/BqxqjsHQ9gUdfeZChuOl1UcCAwEAAaNC -MEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFMR5yo6hTgMdHNxr -2zFblD4/MH8tMA0GCSqGSIb3DQEBCwUAA4IBAQAtxRPPVoB7eni9n64smefv2t+UXglpp+duaIy9 -cr5HqQ6XErhK8WTTOd8lNNTBzU6B8A8ExCSzNJbGpqow32hhc9f5joWJ7w5elShKKiePEI4ufIbE -Ap7aDHdlDkQNkv39sxY2+hENHYwOB4lqKVb3cvTdFZx3NWZXqxNT2I7BQMXXExZacse3aQHEerGD -AWh9jUGhlBjBJVz88P6DAod8DQ3PLghcSkANPuyBYeYk28rgDi0Hsj5W3I31QYUHSJsMC8tJP33s -t/3LjWeJGqvtux6jAAgIFyqCXDFdRootD4abdNlF+9RAsXqqaC2Gspki4cErx5z481+oghLrGREt ------END CERTIFICATE----- - -thawte Primary Root CA - G2 -=========================== ------BEGIN CERTIFICATE----- -MIICiDCCAg2gAwIBAgIQNfwmXNmET8k9Jj1Xm67XVjAKBggqhkjOPQQDAzCBhDELMAkGA1UEBhMC -VVMxFTATBgNVBAoTDHRoYXd0ZSwgSW5jLjE4MDYGA1UECxMvKGMpIDIwMDcgdGhhd3RlLCBJbmMu -IC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxJDAiBgNVBAMTG3RoYXd0ZSBQcmltYXJ5IFJvb3Qg -Q0EgLSBHMjAeFw0wNzExMDUwMDAwMDBaFw0zODAxMTgyMzU5NTlaMIGEMQswCQYDVQQGEwJVUzEV -MBMGA1UEChMMdGhhd3RlLCBJbmMuMTgwNgYDVQQLEy8oYykgMjAwNyB0aGF3dGUsIEluYy4gLSBG -b3IgYXV0aG9yaXplZCB1c2Ugb25seTEkMCIGA1UEAxMbdGhhd3RlIFByaW1hcnkgUm9vdCBDQSAt -IEcyMHYwEAYHKoZIzj0CAQYFK4EEACIDYgAEotWcgnuVnfFSeIf+iha/BebfowJPDQfGAFG6DAJS -LSKkQjnE/o/qycG+1E3/n3qe4rF8mq2nhglzh9HnmuN6papu+7qzcMBniKI11KOasf2twu8x+qi5 -8/sIxpHR+ymVo0IwQDAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIBBjAdBgNVHQ4EFgQU -mtgAMADna3+FGO6Lts6KDPgR4bswCgYIKoZIzj0EAwMDaQAwZgIxAN344FdHW6fmCsO99YCKlzUN -G4k8VIZ3KMqh9HneteY4sPBlcIx/AlTCv//YoT7ZzwIxAMSNlPzcU9LcnXgWHxUzI1NS41oxXZ3K -rr0TKUQNJ1uo52icEvdYPy5yAlejj6EULg== ------END CERTIFICATE----- - -thawte Primary Root CA - G3 -=========================== ------BEGIN CERTIFICATE----- -MIIEKjCCAxKgAwIBAgIQYAGXt0an6rS0mtZLL/eQ+zANBgkqhkiG9w0BAQsFADCBrjELMAkGA1UE -BhMCVVMxFTATBgNVBAoTDHRoYXd0ZSwgSW5jLjEoMCYGA1UECxMfQ2VydGlmaWNhdGlvbiBTZXJ2 -aWNlcyBEaXZpc2lvbjE4MDYGA1UECxMvKGMpIDIwMDggdGhhd3RlLCBJbmMuIC0gRm9yIGF1dGhv -cml6ZWQgdXNlIG9ubHkxJDAiBgNVBAMTG3RoYXd0ZSBQcmltYXJ5IFJvb3QgQ0EgLSBHMzAeFw0w -ODA0MDIwMDAwMDBaFw0zNzEyMDEyMzU5NTlaMIGuMQswCQYDVQQGEwJVUzEVMBMGA1UEChMMdGhh -d3RlLCBJbmMuMSgwJgYDVQQLEx9DZXJ0aWZpY2F0aW9uIFNlcnZpY2VzIERpdmlzaW9uMTgwNgYD -VQQLEy8oYykgMjAwOCB0aGF3dGUsIEluYy4gLSBGb3IgYXV0aG9yaXplZCB1c2Ugb25seTEkMCIG -A1UEAxMbdGhhd3RlIFByaW1hcnkgUm9vdCBDQSAtIEczMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8A -MIIBCgKCAQEAsr8nLPvb2FvdeHsbnndmgcs+vHyu86YnmjSjaDFxODNi5PNxZnmxqWWjpYvVj2At -P0LMqmsywCPLLEHd5N/8YZzic7IilRFDGF/Eth9XbAoFWCLINkw6fKXRz4aviKdEAhN0cXMKQlkC -+BsUa0Lfb1+6a4KinVvnSr0eAXLbS3ToO39/fR8EtCab4LRarEc9VbjXsCZSKAExQGbY2SS99irY -7CFJXJv2eul/VTV+lmuNk5Mny5K76qxAwJ/C+IDPXfRa3M50hqY+bAtTyr2SzhkGcuYMXDhpxwTW -vGzOW/b3aJzcJRVIiKHpqfiYnODz1TEoYRFsZ5aNOZnLwkUkOQIDAQABo0IwQDAPBgNVHRMBAf8E -BTADAQH/MA4GA1UdDwEB/wQEAwIBBjAdBgNVHQ4EFgQUrWyqlGCc7eT/+j4KdCtjA/e2Wb8wDQYJ -KoZIhvcNAQELBQADggEBABpA2JVlrAmSicY59BDlqQ5mU1143vokkbvnRFHfxhY0Cu9qRFHqKweK -A3rD6z8KLFIWoCtDuSWQP3CpMyVtRRooOyfPqsMpQhvfO0zAMzRbQYi/aytlryjvsvXDqmbOe1bu -t8jLZ8HJnBoYuMTDSQPxYA5QzUbF83d597YV4Djbxy8ooAw/dyZ02SUS2jHaGh7cKUGRIjxpp7sC -8rZcJwOJ9Abqm+RyguOhCcHpABnTPtRwa7pxpqpYrvS76Wy274fMm7v/OeZWYdMKp8RcTGB7BXcm -er/YB1IsYvdwY9k5vG8cwnncdimvzsUsZAReiDZuMdRAGmI0Nj81Aa6sY6A= ------END CERTIFICATE----- - -GeoTrust Primary Certification Authority - G2 -============================================= ------BEGIN CERTIFICATE----- -MIICrjCCAjWgAwIBAgIQPLL0SAoA4v7rJDteYD7DazAKBggqhkjOPQQDAzCBmDELMAkGA1UEBhMC -VVMxFjAUBgNVBAoTDUdlb1RydXN0IEluYy4xOTA3BgNVBAsTMChjKSAyMDA3IEdlb1RydXN0IElu -Yy4gLSBGb3IgYXV0aG9yaXplZCB1c2Ugb25seTE2MDQGA1UEAxMtR2VvVHJ1c3QgUHJpbWFyeSBD -ZXJ0aWZpY2F0aW9uIEF1dGhvcml0eSAtIEcyMB4XDTA3MTEwNTAwMDAwMFoXDTM4MDExODIzNTk1 -OVowgZgxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1HZW9UcnVzdCBJbmMuMTkwNwYDVQQLEzAoYykg -MjAwNyBHZW9UcnVzdCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxNjA0BgNVBAMTLUdl -b1RydXN0IFByaW1hcnkgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgLSBHMjB2MBAGByqGSM49AgEG -BSuBBAAiA2IABBWx6P0DFUPlrOuHNxFi79KDNlJ9RVcLSo17VDs6bl8VAsBQps8lL33KSLjHUGMc -KiEIfJo22Av+0SbFWDEwKCXzXV2juLaltJLtbCyf691DiaI8S0iRHVDsJt/WYC69IaNCMEAwDwYD -VR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFBVfNVdRVfslsq0DafwBo/q+ -EVXVMAoGCCqGSM49BAMDA2cAMGQCMGSWWaboCd6LuvpaiIjwH5HTRqjySkwCY/tsXzjbLkGTqQ7m -ndwxHLKgpxgceeHHNgIwOlavmnRs9vuD4DPTCF+hnMJbn0bWtsuRBmOiBuczrD6ogRLQy7rQkgu2 -npaqBA+K ------END CERTIFICATE----- - -VeriSign Universal Root Certification Authority -=============================================== ------BEGIN CERTIFICATE----- -MIIEuTCCA6GgAwIBAgIQQBrEZCGzEyEDDrvkEhrFHTANBgkqhkiG9w0BAQsFADCBvTELMAkGA1UE -BhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZWZXJpU2lnbiBUcnVzdCBO -ZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwOCBWZXJpU2lnbiwgSW5jLiAtIEZvciBhdXRob3JpemVk -IHVzZSBvbmx5MTgwNgYDVQQDEy9WZXJpU2lnbiBVbml2ZXJzYWwgUm9vdCBDZXJ0aWZpY2F0aW9u -IEF1dGhvcml0eTAeFw0wODA0MDIwMDAwMDBaFw0zNzEyMDEyMzU5NTlaMIG9MQswCQYDVQQGEwJV -UzEXMBUGA1UEChMOVmVyaVNpZ24sIEluYy4xHzAdBgNVBAsTFlZlcmlTaWduIFRydXN0IE5ldHdv -cmsxOjA4BgNVBAsTMShjKSAyMDA4IFZlcmlTaWduLCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNl -IG9ubHkxODA2BgNVBAMTL1ZlcmlTaWduIFVuaXZlcnNhbCBSb290IENlcnRpZmljYXRpb24gQXV0 -aG9yaXR5MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAx2E3XrEBNNti1xWb/1hajCMj -1mCOkdeQmIN65lgZOIzF9uVkhbSicfvtvbnazU0AtMgtc6XHaXGVHzk8skQHnOgO+k1KxCHfKWGP -MiJhgsWHH26MfF8WIFFE0XBPV+rjHOPMee5Y2A7Cs0WTwCznmhcrewA3ekEzeOEz4vMQGn+HLL72 -9fdC4uW/h2KJXwBL38Xd5HVEMkE6HnFuacsLdUYI0crSK5XQz/u5QGtkjFdN/BMReYTtXlT2NJ8I -AfMQJQYXStrxHXpma5hgZqTZ79IugvHw7wnqRMkVauIDbjPTrJ9VAMf2CGqUuV/c4DPxhGD5WycR -tPwW8rtWaoAljQIDAQABo4GyMIGvMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEGMG0G -CCsGAQUFBwEMBGEwX6FdoFswWTBXMFUWCWltYWdlL2dpZjAhMB8wBwYFKw4DAhoEFI/l0xqGrI2O -a8PPgGrUSBgsexkuMCUWI2h0dHA6Ly9sb2dvLnZlcmlzaWduLmNvbS92c2xvZ28uZ2lmMB0GA1Ud -DgQWBBS2d/ppSEefUxLVwuoHMnYH0ZcHGTANBgkqhkiG9w0BAQsFAAOCAQEASvj4sAPmLGd75JR3 -Y8xuTPl9Dg3cyLk1uXBPY/ok+myDjEedO2Pzmvl2MpWRsXe8rJq+seQxIcaBlVZaDrHC1LGmWazx -Y8u4TB1ZkErvkBYoH1quEPuBUDgMbMzxPcP1Y+Oz4yHJJDnp/RVmRvQbEdBNc6N9Rvk97ahfYtTx -P/jgdFcrGJ2BtMQo2pSXpXDrrB2+BxHw1dvd5Yzw1TKwg+ZX4o+/vqGqvz0dtdQ46tewXDpPaj+P -wGZsY6rp2aQW9IHRlRQOfc2VNNnSj3BzgXucfr2YYdhFh5iQxeuGMMY1v/D/w1WIg0vvBZIGcfK4 -mJO37M2CYfE45k+XmCpajQ== ------END CERTIFICATE----- - -VeriSign Class 3 Public Primary Certification Authority - G4 -============================================================ ------BEGIN CERTIFICATE----- -MIIDhDCCAwqgAwIBAgIQL4D+I4wOIg9IZxIokYesszAKBggqhkjOPQQDAzCByjELMAkGA1UEBhMC -VVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZWZXJpU2lnbiBUcnVzdCBOZXR3 -b3JrMTowOAYDVQQLEzEoYykgMjAwNyBWZXJpU2lnbiwgSW5jLiAtIEZvciBhdXRob3JpemVkIHVz -ZSBvbmx5MUUwQwYDVQQDEzxWZXJpU2lnbiBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5IENlcnRpZmlj -YXRpb24gQXV0aG9yaXR5IC0gRzQwHhcNMDcxMTA1MDAwMDAwWhcNMzgwMTE4MjM1OTU5WjCByjEL -MAkGA1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZWZXJpU2lnbiBU -cnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNyBWZXJpU2lnbiwgSW5jLiAtIEZvciBhdXRo -b3JpemVkIHVzZSBvbmx5MUUwQwYDVQQDEzxWZXJpU2lnbiBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5 -IENlcnRpZmljYXRpb24gQXV0aG9yaXR5IC0gRzQwdjAQBgcqhkjOPQIBBgUrgQQAIgNiAASnVnp8 -Utpkmw4tXNherJI9/gHmGUo9FANL+mAnINmDiWn6VMaaGF5VKmTeBvaNSjutEDxlPZCIBIngMGGz -rl0Bp3vefLK+ymVhAIau2o970ImtTR1ZmkGxvEeA3J5iw/mjgbIwga8wDwYDVR0TAQH/BAUwAwEB -/zAOBgNVHQ8BAf8EBAMCAQYwbQYIKwYBBQUHAQwEYTBfoV2gWzBZMFcwVRYJaW1hZ2UvZ2lmMCEw -HzAHBgUrDgMCGgQUj+XTGoasjY5rw8+AatRIGCx7GS4wJRYjaHR0cDovL2xvZ28udmVyaXNpZ24u -Y29tL3ZzbG9nby5naWYwHQYDVR0OBBYEFLMWkf3upm7ktS5Jj4d4gYDs5bG1MAoGCCqGSM49BAMD -A2gAMGUCMGYhDBgmYFo4e1ZC4Kf8NoRRkSAsdk1DPcQdhCPQrNZ8NQbOzWm9kA3bbEhCHQ6qQgIx -AJw9SDkjOVgaFRJZap7v1VmyHVIsmXHNxynfGyphe3HR3vPA5Q06Sqotp9iGKt0uEA== ------END CERTIFICATE----- - -NetLock Arany (Class Gold) Főtanúsítvány -======================================== ------BEGIN CERTIFICATE----- -MIIEFTCCAv2gAwIBAgIGSUEs5AAQMA0GCSqGSIb3DQEBCwUAMIGnMQswCQYDVQQGEwJIVTERMA8G -A1UEBwwIQnVkYXBlc3QxFTATBgNVBAoMDE5ldExvY2sgS2Z0LjE3MDUGA1UECwwuVGFuw7pzw610 -dsOhbnlraWFkw7NrIChDZXJ0aWZpY2F0aW9uIFNlcnZpY2VzKTE1MDMGA1UEAwwsTmV0TG9jayBB -cmFueSAoQ2xhc3MgR29sZCkgRsWRdGFuw7pzw610dsOhbnkwHhcNMDgxMjExMTUwODIxWhcNMjgx -MjA2MTUwODIxWjCBpzELMAkGA1UEBhMCSFUxETAPBgNVBAcMCEJ1ZGFwZXN0MRUwEwYDVQQKDAxO -ZXRMb2NrIEtmdC4xNzA1BgNVBAsMLlRhbsO6c8OtdHbDoW55a2lhZMOzayAoQ2VydGlmaWNhdGlv -biBTZXJ2aWNlcykxNTAzBgNVBAMMLE5ldExvY2sgQXJhbnkgKENsYXNzIEdvbGQpIEbFkXRhbsO6 -c8OtdHbDoW55MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAxCRec75LbRTDofTjl5Bu -0jBFHjzuZ9lk4BqKf8owyoPjIMHj9DrTlF8afFttvzBPhCf2nx9JvMaZCpDyD/V/Q4Q3Y1GLeqVw -/HpYzY6b7cNGbIRwXdrzAZAj/E4wqX7hJ2Pn7WQ8oLjJM2P+FpD/sLj916jAwJRDC7bVWaaeVtAk -H3B5r9s5VA1lddkVQZQBr17s9o3x/61k/iCa11zr/qYfCGSji3ZVrR47KGAuhyXoqq8fxmRGILdw -fzzeSNuWU7c5d+Qa4scWhHaXWy+7GRWF+GmF9ZmnqfI0p6m2pgP8b4Y9VHx2BJtr+UBdADTHLpl1 -neWIA6pN+APSQnbAGwIDAKiLo0UwQzASBgNVHRMBAf8ECDAGAQH/AgEEMA4GA1UdDwEB/wQEAwIB -BjAdBgNVHQ4EFgQUzPpnk/C2uNClwB7zU/2MU9+D15YwDQYJKoZIhvcNAQELBQADggEBAKt/7hwW -qZw8UQCgwBEIBaeZ5m8BiFRhbvG5GK1Krf6BQCOUL/t1fC8oS2IkgYIL9WHxHG64YTjrgfpioTta -YtOUZcTh5m2C+C8lcLIhJsFyUR+MLMOEkMNaj7rP9KdlpeuY0fsFskZ1FSNqb4VjMIDw1Z4fKRzC -bLBQWV2QWzuoDTDPv31/zvGdg73JRm4gpvlhUbohL3u+pRVjodSVh/GeufOJ8z2FuLjbvrW5Kfna -NwUASZQDhETnv0Mxz3WLJdH0pmT1kvarBes96aULNmLazAZfNou2XjG4Kvte9nHfRCaexOYNkbQu -dZWAUWpLMKawYqGT8ZvYzsRjdT9ZR7E= ------END CERTIFICATE----- - -Staat der Nederlanden Root CA - G2 -================================== ------BEGIN CERTIFICATE----- -MIIFyjCCA7KgAwIBAgIEAJiWjDANBgkqhkiG9w0BAQsFADBaMQswCQYDVQQGEwJOTDEeMBwGA1UE -CgwVU3RhYXQgZGVyIE5lZGVybGFuZGVuMSswKQYDVQQDDCJTdGFhdCBkZXIgTmVkZXJsYW5kZW4g -Um9vdCBDQSAtIEcyMB4XDTA4MDMyNjExMTgxN1oXDTIwMDMyNTExMDMxMFowWjELMAkGA1UEBhMC -TkwxHjAcBgNVBAoMFVN0YWF0IGRlciBOZWRlcmxhbmRlbjErMCkGA1UEAwwiU3RhYXQgZGVyIE5l -ZGVybGFuZGVuIFJvb3QgQ0EgLSBHMjCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAMVZ -5291qj5LnLW4rJ4L5PnZyqtdj7U5EILXr1HgO+EASGrP2uEGQxGZqhQlEq0i6ABtQ8SpuOUfiUtn -vWFI7/3S4GCI5bkYYCjDdyutsDeqN95kWSpGV+RLufg3fNU254DBtvPUZ5uW6M7XxgpT0GtJlvOj -CwV3SPcl5XCsMBQgJeN/dVrlSPhOewMHBPqCYYdu8DvEpMfQ9XQ+pV0aCPKbJdL2rAQmPlU6Yiil -e7Iwr/g3wtG61jj99O9JMDeZJiFIhQGp5Rbn3JBV3w/oOM2ZNyFPXfUib2rFEhZgF1XyZWampzCR -OME4HYYEhLoaJXhena/MUGDWE4dS7WMfbWV9whUYdMrhfmQpjHLYFhN9C0lK8SgbIHRrxT3dsKpI -CT0ugpTNGmXZK4iambwYfp/ufWZ8Pr2UuIHOzZgweMFvZ9C+X+Bo7d7iscksWXiSqt8rYGPy5V65 -48r6f1CGPqI0GAwJaCgRHOThuVw+R7oyPxjMW4T182t0xHJ04eOLoEq9jWYv6q012iDTiIJh8BIi -trzQ1aTsr1SIJSQ8p22xcik/Plemf1WvbibG/ufMQFxRRIEKeN5KzlW/HdXZt1bv8Hb/C3m1r737 -qWmRRpdogBQ2HbN/uymYNqUg+oJgYjOk7Na6B6duxc8UpufWkjTYgfX8HV2qXB72o007uPc5AgMB -AAGjgZcwgZQwDwYDVR0TAQH/BAUwAwEB/zBSBgNVHSAESzBJMEcGBFUdIAAwPzA9BggrBgEFBQcC -ARYxaHR0cDovL3d3dy5wa2lvdmVyaGVpZC5ubC9wb2xpY2llcy9yb290LXBvbGljeS1HMjAOBgNV -HQ8BAf8EBAMCAQYwHQYDVR0OBBYEFJFoMocVHYnitfGsNig0jQt8YojrMA0GCSqGSIb3DQEBCwUA -A4ICAQCoQUpnKpKBglBu4dfYszk78wIVCVBR7y29JHuIhjv5tLySCZa59sCrI2AGeYwRTlHSeYAz -+51IvuxBQ4EffkdAHOV6CMqqi3WtFMTC6GY8ggen5ieCWxjmD27ZUD6KQhgpxrRW/FYQoAUXvQwj -f/ST7ZwaUb7dRUG/kSS0H4zpX897IZmflZ85OkYcbPnNe5yQzSipx6lVu6xiNGI1E0sUOlWDuYaN -kqbG9AclVMwWVxJKgnjIFNkXgiYtXSAfea7+1HAWFpWD2DU5/1JddRwWxRNVz0fMdWVSSt7wsKfk -CpYL+63C4iWEst3kvX5ZbJvw8NjnyvLplzh+ib7M+zkXYT9y2zqR2GUBGR2tUKRXCnxLvJxxcypF -URmFzI79R6d0lR2o0a9OF7FpJsKqeFdbxU2n5Z4FF5TKsl+gSRiNNOkmbEgeqmiSBeGCc1qb3Adb -CG19ndeNIdn8FCCqwkXfP+cAslHkwvgFuXkajDTznlvkN1trSt8sV4pAWja63XVECDdCcAz+3F4h -oKOKwJCcaNpQ5kUQR3i2TtJlycM33+FCY7BXN0Ute4qcvwXqZVUz9zkQxSgqIXobisQk+T8VyJoV -IPVVYpbtbZNQvOSqeK3Zywplh6ZmwcSBo3c6WB4L7oOLnR7SUqTMHW+wmG2UMbX4cQrcufx9MmDm -66+KAQ== ------END CERTIFICATE----- - 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-SSL.com Root Certification Authority RSA -======================================== ------BEGIN CERTIFICATE----- -MIIF3TCCA8WgAwIBAgIIeyyb0xaAMpkwDQYJKoZIhvcNAQELBQAwfDELMAkGA1UEBhMCVVMxDjAM -BgNVBAgMBVRleGFzMRAwDgYDVQQHDAdIb3VzdG9uMRgwFgYDVQQKDA9TU0wgQ29ycG9yYXRpb24x -MTAvBgNVBAMMKFNTTC5jb20gUm9vdCBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eSBSU0EwHhcNMTYw -MjEyMTczOTM5WhcNNDEwMjEyMTczOTM5WjB8MQswCQYDVQQGEwJVUzEOMAwGA1UECAwFVGV4YXMx -EDAOBgNVBAcMB0hvdXN0b24xGDAWBgNVBAoMD1NTTCBDb3Jwb3JhdGlvbjExMC8GA1UEAwwoU1NM -LmNvbSBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5IFJTQTCCAiIwDQYJKoZIhvcNAQEBBQAD -ggIPADCCAgoCggIBAPkP3aMrfcvQKv7sZ4Wm5y4bunfh4/WvpOz6Sl2RxFdHaxh3a3by/ZPkPQ/C -Fp4LZsNWlJ4Xg4XOVu/yFv0AYvUiCVToZRdOQbngT0aXqhvIuG5iXmmxX9sqAn78bMrzQdjt0Oj8 -P2FI7bADFB0QDksZ4LtO7IZl/zbzXmcCC52GVWH9ejjt/uIZALdvoVBidXQ8oPrIJZK0bnoix/ge -oeOy3ZExqysdBP+lSgQ36YWkMyv94tZVNHwZpEpox7Ko07fKoZOI68GXvIz5HdkihCR0xwQ9aqkp -k8zruFvh/l8lqjRYyMEjVJ0bmBHDOJx+PYZspQ9AhnwC9FwCTyjLrnGfDzrIM/4RJTXq/LrFYD3Z -fBjVsqnTdXgDciLKOsMf7yzlLqn6niy2UUb9rwPW6mBo6oUWNmuF6R7As93EJNyAKoFBbZQ+yODJ -gUEAnl6/f8UImKIYLEJAs/lvOCdLToD0PYFH4Ih86hzOtXVcUS4cK38acijnALXRdMbX5J+tB5O2 -UzU1/Dfkw/ZdFr4hc96SCvigY2q8lpJqPvi8ZVWb3vUNiSYE/CUapiVpy8JtynziWV+XrOvvLsi8 -1xtZPCvM8hnIk2snYxnP/Okm+Mpxm3+T/jRnhE6Z6/yzeAkzcLpmpnbtG3PrGqUNxCITIJRWCk4s -bE6x/c+cCbqiM+2HAgMBAAGjYzBhMB0GA1UdDgQWBBTdBAkHovV6fVJTEpKV7jiAJQ2mWTAPBgNV -HRMBAf8EBTADAQH/MB8GA1UdIwQYMBaAFN0ECQei9Xp9UlMSkpXuOIAlDaZZMA4GA1UdDwEB/wQE -AwIBhjANBgkqhkiG9w0BAQsFAAOCAgEAIBgRlCn7Jp0cHh5wYfGVcpNxJK1ok1iOMq8bs3AD/CUr -dIWQPXhq9LmLpZc7tRiRux6n+UBbkflVma8eEdBcHadm47GUBwwyOabqG7B52B2ccETjit3E+ZUf -ijhDPwGFpUenPUayvOUiaPd7nNgsPgohyC0zrL/FgZkxdMF1ccW+sfAjRfSda/wZY52jvATGGAsl -u1OJD7OAUN5F7kR/q5R4ZJjT9ijdh9hwZXT7DrkT66cPYakylszeu+1jTBi7qUD3oFRuIIhxdRjq -erQ0cuAjJ3dctpDqhiVAq+8zD8ufgr6iIPv2tS0a5sKFsXQP+8hlAqRSAUfdSSLBv9jra6x+3uxj -MxW3IwiPxg+NQVrdjsW5j+VFP3jbutIbQLH+cU0/4IGiul607BXgk90IH37hVZkLId6Tngr75qNJ -vTYw/ud3sqB1l7UtgYgXZSD32pAAn8lSzDLKNXz1PQ/YK9f1JmzJBjSWFupwWRoyeXkLtoh/D1JI -Pb9s2KJELtFOt3JY04kTlf5Eq/jXixtunLwsoFvVagCvXzfh1foQC5ichucmj87w7G6KVwuA406y -wKBjYZC6VWg3dGq2ktufoYYitmUnDuy2n0Jg5GfCtdpBC8TTi2EbvPofkSvXRAdeuims2cXp71NI -WuuA8ShYIc2wBlX7Jz9TkHCpBB5XJ7k= ------END CERTIFICATE----- - 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-SSL.com EV Root Certification Authority RSA R2 -============================================== ------BEGIN CERTIFICATE----- -MIIF6zCCA9OgAwIBAgIIVrYpzTS8ePYwDQYJKoZIhvcNAQELBQAwgYIxCzAJBgNVBAYTAlVTMQ4w -DAYDVQQIDAVUZXhhczEQMA4GA1UEBwwHSG91c3RvbjEYMBYGA1UECgwPU1NMIENvcnBvcmF0aW9u -MTcwNQYDVQQDDC5TU0wuY29tIEVWIFJvb3QgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgUlNBIFIy -MB4XDTE3MDUzMTE4MTQzN1oXDTQyMDUzMDE4MTQzN1owgYIxCzAJBgNVBAYTAlVTMQ4wDAYDVQQI -DAVUZXhhczEQMA4GA1UEBwwHSG91c3RvbjEYMBYGA1UECgwPU1NMIENvcnBvcmF0aW9uMTcwNQYD -VQQDDC5TU0wuY29tIEVWIFJvb3QgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgUlNBIFIyMIICIjAN -BgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAjzZlQOHWTcDXtOlG2mvqM0fNTPl9fb69LT3w23jh -hqXZuglXaO1XPqDQCEGD5yhBJB/jchXQARr7XnAjssufOePPxU7Gkm0mxnu7s9onnQqG6YE3Bf7w -cXHswxzpY6IXFJ3vG2fThVUCAtZJycxa4bH3bzKfydQ7iEGonL3Lq9ttewkfokxykNorCPzPPFTO -Zw+oz12WGQvE43LrrdF9HSfvkusQv1vrO6/PgN3B0pYEW3p+pKk8OHakYo6gOV7qd89dAFmPZiw+ -B6KjBSYRaZfqhbcPlgtLyEDhULouisv3D5oi53+aNxPN8k0TayHRwMwi8qFG9kRpnMphNQcAb9Zh -CBHqurj26bNg5U257J8UZslXWNvNh2n4ioYSA0e/ZhN2rHd9NCSFg83XqpyQGp8hLH94t2S42Oim -9HizVcuE0jLEeK6jj2HdzghTreyI/BXkmg3mnxp3zkyPuBQVPWKchjgGAGYS5Fl2WlPAApiiECto -RHuOec4zSnaqW4EWG7WK2NAAe15itAnWhmMOpgWVSbooi4iTsjQc2KRVbrcc0N6ZVTsj9CLg+Slm -JuwgUHfbSguPvuUCYHBBXtSuUDkiFCbLsjtzdFVHB3mBOagwE0TlBIqulhMlQg+5U8Sb/M3kHN48 -+qvWBkofZ6aYMBzdLNvcGJVXZsb/XItW9XcCAwEAAaNjMGEwDwYDVR0TAQH/BAUwAwEB/zAfBgNV -HSMEGDAWgBT5YLvU49U09rj1BoAlp3PbRmmonjAdBgNVHQ4EFgQU+WC71OPVNPa49QaAJadz20Zp -qJ4wDgYDVR0PAQH/BAQDAgGGMA0GCSqGSIb3DQEBCwUAA4ICAQBWs47LCp1Jjr+kxJG7ZhcFUZh1 -++VQLHqe8RT6q9OKPv+RKY9ji9i0qVQBDb6Thi/5Sm3HXvVX+cpVHBK+Rw82xd9qt9t1wkclf7nx -Y/hoLVUE0fKNsKTPvDxeH3jnpaAgcLAExbf3cqfeIg29MyVGjGSSJuM+LmOW2puMPfgYCdcDzH2G -guDKBAdRUNf/ktUM79qGn5nX67evaOI5JpS6aLe/g9Pqemc9YmeuJeVy6OLk7K4S9ksrPJ/psEDz -OFSz/bdoyNrGj1E8svuR3Bznm53htw1yj+KkxKl4+esUrMZDBcJlOSgYAsOCsp0FvmXtll9ldDz7 -CTUue5wT/RsPXcdtgTpWD8w74a8CLyKsRspGPKAcTNZEtF4uXBVmCeEmKf7GUmG6sXP/wwyc5Wxq -lD8UykAWlYTzWamsX0xhk23RO8yilQwipmdnRC652dKKQbNmC1r7fSOl8hqw/96bg5Qu0T/fkreR -rwU7ZcegbLHNYhLDkBvjJc40vG93drEQw/cFGsDWr3RiSBd3kmmQYRzelYB0VI8YHMPzA9C/pEN1 -hlMYegouCRw2n5H9gooiS9EOUCXdywMMF8mDAAhONU2Ki+3wApRmLER/y5UnlhetCTCstnEXbosX -9hwJ1C07mKVx01QT2WDz9UtmT/rx7iASjbSsV7FFY6GsdqnC+w== ------END CERTIFICATE----- - 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-emSign ECC Root CA - C3 -======================= ------BEGIN CERTIFICATE----- -MIICKzCCAbGgAwIBAgIKe3G2gla4EnycqDAKBggqhkjOPQQDAzBaMQswCQYDVQQGEwJVUzETMBEG -A1UECxMKZW1TaWduIFBLSTEUMBIGA1UEChMLZU11ZGhyYSBJbmMxIDAeBgNVBAMTF2VtU2lnbiBF -Q0MgUm9vdCBDQSAtIEMzMB4XDTE4MDIxODE4MzAwMFoXDTQzMDIxODE4MzAwMFowWjELMAkGA1UE -BhMCVVMxEzARBgNVBAsTCmVtU2lnbiBQS0kxFDASBgNVBAoTC2VNdWRocmEgSW5jMSAwHgYDVQQD -ExdlbVNpZ24gRUNDIFJvb3QgQ0EgLSBDMzB2MBAGByqGSM49AgEGBSuBBAAiA2IABP2lYa57JhAd -6bciMK4G9IGzsUJxlTm801Ljr6/58pc1kjZGDoeVjbk5Wum739D+yAdBPLtVb4OjavtisIGJAnB9 -SMVK4+kiVCJNk7tCDK93nCOmfddhEc5lx/h//vXyqaNCMEAwHQYDVR0OBBYEFPtaSNCAIEDyqOkA -B2kZd6fmw/TPMA4GA1UdDwEB/wQEAwIBBjAPBgNVHRMBAf8EBTADAQH/MAoGCCqGSM49BAMDA2gA -MGUCMQC02C8Cif22TGK6Q04ThHK1rt0c3ta13FaPWEBaLd4gTCKDypOofu4SQMfWh0/434UCMBwU -ZOR8loMRnLDRWmFLpg9J0wD8ofzkpf9/rdcw0Md3f76BB1UwUCAU9Vc4CqgxUQ== ------END CERTIFICATE----- - -Hongkong Post Root CA 3 -======================= ------BEGIN CERTIFICATE----- -MIIFzzCCA7egAwIBAgIUCBZfikyl7ADJk0DfxMauI7gcWqQwDQYJKoZIhvcNAQELBQAwbzELMAkG -A1UEBhMCSEsxEjAQBgNVBAgTCUhvbmcgS29uZzESMBAGA1UEBxMJSG9uZyBLb25nMRYwFAYDVQQK -Ew1Ib25na29uZyBQb3N0MSAwHgYDVQQDExdIb25na29uZyBQb3N0IFJvb3QgQ0EgMzAeFw0xNzA2 -MDMwMjI5NDZaFw00MjA2MDMwMjI5NDZaMG8xCzAJBgNVBAYTAkhLMRIwEAYDVQQIEwlIb25nIEtv -bmcxEjAQBgNVBAcTCUhvbmcgS29uZzEWMBQGA1UEChMNSG9uZ2tvbmcgUG9zdDEgMB4GA1UEAxMX -SG9uZ2tvbmcgUG9zdCBSb290IENBIDMwggIiMA0GCSqGSIb3DQEBAQUAA4ICDwAwggIKAoICAQCz -iNfqzg8gTr7m1gNt7ln8wlffKWihgw4+aMdoWJwcYEuJQwy51BWy7sFOdem1p+/l6TWZ5Mwc50tf -jTMwIDNT2aa71T4Tjukfh0mtUC1Qyhi+AViiE3CWu4mIVoBc+L0sPOFMV4i707mV78vH9toxdCim -5lSJ9UExyuUmGs2C4HDaOym71QP1mbpV9WTRYA6ziUm4ii8F0oRFKHyPaFASePwLtVPLwpgchKOe -sL4jpNrcyCse2m5FHomY2vkALgbpDDtw1VAliJnLzXNg99X/NWfFobxeq81KuEXryGgeDQ0URhLj -0mRiikKYvLTGCAj4/ahMZJx2Ab0vqWwzD9g/KLg8aQFChn5pwckGyuV6RmXpwtZQQS4/t+TtbNe/ -JgERohYpSms0BpDsE9K2+2p20jzt8NYt3eEV7KObLyzJPivkaTv/ciWxNoZbx39ri1UbSsUgYT2u -y1DhCDq+sI9jQVMwCFk8mB13umOResoQUGC/8Ne8lYePl8X+l2oBlKN8W4UdKjk60FSh0Tlxnf0h -+bV78OLgAo9uliQlLKAeLKjEiafv7ZkGL7YKTE/bosw3Gq9HhS2KX8Q0NEwA/RiTZxPRN+ZItIsG -xVd7GYYKecsAyVKvQv83j+GjHno9UKtjBucVtT+2RTeUN7F+8kjDf8V1/peNRY8apxpyKBpADwID -AQABo2MwYTAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIBBjAfBgNVHSMEGDAWgBQXnc0e -i9Y5K3DTXNSguB+wAPzFYTAdBgNVHQ4EFgQUF53NHovWOStw01zUoLgfsAD8xWEwDQYJKoZIhvcN -AQELBQADggIBAFbVe27mIgHSQpsY1Q7XZiNc4/6gx5LS6ZStS6LG7BJ8dNVI0lkUmcDrudHr9Egw -W62nV3OZqdPlt9EuWSRY3GguLmLYauRwCy0gUCCkMpXRAJi70/33MvJJrsZ64Ee+bs7Lo3I6LWld -y8joRTnU+kLBEUx3XZL7av9YROXrgZ6voJmtvqkBZss4HTzfQx/0TW60uhdG/H39h4F5ag0zD/ov -+BS5gLNdTaqX4fnkGMX41TiMJjz98iji7lpJiCzfeT2OnpA8vUFKOt1b9pq0zj8lMH8yfaIDlNDc -eqFS3m6TjRgm/VWsvY+b0s+v54Ysyx8Jb6NvqYTUc79NoXQbTiNg8swOqn+knEwlqLJmOzj/2ZQw -9nKEvmhVEA/GcywWaZMH/rFF7buiVWqw2rVKAiUnhde3t4ZEFolsgCs+l6mc1X5VTMbeRRAc6uk7 -nwNT7u56AQIWeNTowr5GdogTPyK7SBIdUgC0An4hGh6cJfTzPV4e0hz5sy229zdcxsshTrD3mUcY -hcErulWuBurQB7Lcq9CClnXO0lD+mefPL5/ndtFhKvshuzHQqp9HpLIiyhY6UFfEW0NnxWViA0kB -60PZ2Pierc+xYw5F9KBaLJstxabArahH9CdMOA0uG0k7UvToiIMrVCjU8jVStDKDYmlkDJGcn5fq -dBb9HxEGmpv0 ------END CERTIFICATE----- - -Entrust Root Certification Authority - G4 -========================================= ------BEGIN CERTIFICATE----- -MIIGSzCCBDOgAwIBAgIRANm1Q3+vqTkPAAAAAFVlrVgwDQYJKoZIhvcNAQELBQAwgb4xCzAJBgNV -BAYTAlVTMRYwFAYDVQQKEw1FbnRydXN0LCBJbmMuMSgwJgYDVQQLEx9TZWUgd3d3LmVudHJ1c3Qu -bmV0L2xlZ2FsLXRlcm1zMTkwNwYDVQQLEzAoYykgMjAxNSBFbnRydXN0LCBJbmMuIC0gZm9yIGF1 -dGhvcml6ZWQgdXNlIG9ubHkxMjAwBgNVBAMTKUVudHJ1c3QgUm9vdCBDZXJ0aWZpY2F0aW9uIEF1 -dGhvcml0eSAtIEc0MB4XDTE1MDUyNzExMTExNloXDTM3MTIyNzExNDExNlowgb4xCzAJBgNVBAYT -AlVTMRYwFAYDVQQKEw1FbnRydXN0LCBJbmMuMSgwJgYDVQQLEx9TZWUgd3d3LmVudHJ1c3QubmV0 -L2xlZ2FsLXRlcm1zMTkwNwYDVQQLEzAoYykgMjAxNSBFbnRydXN0LCBJbmMuIC0gZm9yIGF1dGhv -cml6ZWQgdXNlIG9ubHkxMjAwBgNVBAMTKUVudHJ1c3QgUm9vdCBDZXJ0aWZpY2F0aW9uIEF1dGhv -cml0eSAtIEc0MIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAsewsQu7i0TD/pZJH4i3D -umSXbcr3DbVZwbPLqGgZ2K+EbTBwXX7zLtJTmeH+H17ZSK9dE43b/2MzTdMAArzE+NEGCJR5WIoV -3imz/f3ET+iq4qA7ec2/a0My3dl0ELn39GjUu9CH1apLiipvKgS1sqbHoHrmSKvS0VnM1n4j5pds -8ELl3FFLFUHtSUrJ3hCX1nbB76W1NhSXNdh4IjVS70O92yfbYVaCNNzLiGAMC1rlLAHGVK/XqsEQ -e9IFWrhAnoanw5CGAlZSCXqc0ieCU0plUmr1POeo8pyvi73TDtTUXm6Hnmo9RR3RXRv06QqsYJn7 -ibT/mCzPfB3pAqoEmh643IhuJbNsZvc8kPNXwbMv9W3y+8qh+CmdRouzavbmZwe+LGcKKh9asj5X -xNMhIWNlUpEbsZmOeX7m640A2Vqq6nPopIICR5b+W45UYaPrL0swsIsjdXJ8ITzI9vF01Bx7owVV -7rtNOzK+mndmnqxpkCIHH2E6lr7lmk/MBTwoWdPBDFSoWWG9yHJM6Nyfh3+9nEg2XpWjDrk4JFX8 -dWbrAuMINClKxuMrLzOg2qOGpRKX/YAr2hRC45K9PvJdXmd0LhyIRyk0X+IyqJwlN4y6mACXi0mW -Hv0liqzc2thddG5msP9E36EYxr5ILzeUePiVSj9/E15dWf10hkNjc0kCAwEAAaNCMEAwDwYDVR0T -AQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFJ84xFYjwznooHFs6FRM5Og6sb9n -MA0GCSqGSIb3DQEBCwUAA4ICAQAS5UKme4sPDORGpbZgQIeMJX6tuGguW8ZAdjwD+MlZ9POrYs4Q -jbRaZIxowLByQzTSGwv2LFPSypBLhmb8qoMi9IsabyZIrHZ3CL/FmFz0Jomee8O5ZDIBf9PD3Vht -7LGrhFV0d4QEJ1JrhkzO3bll/9bGXp+aEJlLdWr+aumXIOTkdnrG0CSqkM0gkLpHZPt/B7NTeLUK -YvJzQ85BK4FqLoUWlFPUa19yIqtRLULVAJyZv967lDtX/Zr1hstWO1uIAeV8KEsD+UmDfLJ/fOPt -jqF/YFOOVZ1QNBIPt5d7bIdKROf1beyAN/BYGW5KaHbwH5Lk6rWS02FREAutp9lfx1/cH6NcjKF+ -m7ee01ZvZl4HliDtC3T7Zk6LERXpgUl+b7DUUH8i119lAg2m9IUe2K4GS0qn0jFmwvjO5QimpAKW -RGhXxNUzzxkvFMSUHHuk2fCfDrGA4tGeEWSpiBE6doLlYsKA2KSD7ZPvfC+QsDJMlhVoSFLUmQjA -JOgc47OlIQ6SwJAfzyBfyjs4x7dtOvPmRLgOMWuIjnDrnBdSqEGULoe256YSxXXfW8AKbnuk5F6G -+TaU33fD6Q3AOfF5u0aOq0NZJ7cguyPpVkAh7DE9ZapD8j3fcEThuk0mEDuYn/PIjhs4ViFqUZPT -kcpG2om3PVODLAgfi49T3f+sHw== ------END CERTIFICATE----- diff --git a/boards/sim/sim/sim/src/sim_bringup.c b/boards/sim/sim/sim/src/sim_bringup.c index 58286367304..232354bfb9e 100644 --- a/boards/sim/sim/sim/src/sim_bringup.c +++ b/boards/sim/sim/sim/src/sim_bringup.c @@ -47,10 +47,10 @@ #include #include #include +#include #include #include #include -#include #include #ifdef CONFIG_LCD_DEV @@ -369,17 +369,6 @@ int sim_bringup(void) } #endif -#ifdef CONFIG_BLUETOOTH_UART_BRIDGE - /* Register the Bluetooth BT/BLE dual mode bridge driver */ - - ret = bt_uart_bridge_register("/dev/ttyHCI0", - "/dev/ttyBT", "/dev/ttyBLE"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: bt_uart_bridge_register() failed: %d\n", ret); - } -#endif - #ifdef CONFIG_SIM_I2CBUS /* Initialize the i2c master bus device */ diff --git a/boards/sim/sim/sim/src/sim_foc.c b/boards/sim/sim/sim/src/sim_foc.c index 9f97bda3bab..74f113f5184 100644 --- a/boards/sim/sim/sim/src/sim_foc.c +++ b/boards/sim/sim/sim/src/sim_foc.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/boards/x86/qemu/qemu-i486/configs/nsh/defconfig b/boards/x86/qemu/qemu-i486/configs/nsh/defconfig index 9d313855766..68bec834ebc 100644 --- a/boards/x86/qemu/qemu-i486/configs/nsh/defconfig +++ b/boards/x86/qemu/qemu-i486/configs/nsh/defconfig @@ -32,7 +32,6 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y diff --git a/boards/x86/qemu/qemu-i486/configs/ostest/defconfig b/boards/x86/qemu/qemu-i486/configs/ostest/defconfig index 231614342e2..a343dffc325 100644 --- a/boards/x86/qemu/qemu-i486/configs/ostest/defconfig +++ b/boards/x86/qemu/qemu-i486/configs/ostest/defconfig @@ -18,7 +18,6 @@ CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_CONSOLE_SYSLOG=y CONFIG_FS_FAT=y CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_MAX_TASKS=64 CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=1048576 CONFIG_RAM_START=0x00100000 diff --git a/boards/x86/qemu/qemu-i486/src/qemu_appinit.c b/boards/x86/qemu/qemu-i486/src/qemu_appinit.c index 9990950caa1..578e5846c63 100644 --- a/boards/x86/qemu/qemu-i486/src/qemu_appinit.c +++ b/boards/x86/qemu/qemu-i486/src/qemu_appinit.c @@ -27,6 +27,7 @@ #include #include +#include #include "up_internal.h" diff --git a/boards/x86_64/intel64/qemu-intel64/configs/nsh/defconfig b/boards/x86_64/intel64/qemu-intel64/configs/nsh/defconfig index 30a7572cc09..5ef4f1fede7 100644 --- a/boards/x86_64/intel64/qemu-intel64/configs/nsh/defconfig +++ b/boards/x86_64/intel64/qemu-intel64/configs/nsh/defconfig @@ -31,7 +31,6 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=4194304 CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=4194304 CONFIG_LIBM=y -CONFIG_MAX_TASKS=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFCONFIG=y diff --git a/boards/x86_64/intel64/qemu-intel64/configs/ostest/defconfig b/boards/x86_64/intel64/qemu-intel64/configs/ostest/defconfig index 2c56c97efd2..cb98932e790 100644 --- a/boards/x86_64/intel64/qemu-intel64/configs/ostest/defconfig +++ b/boards/x86_64/intel64/qemu-intel64/configs/ostest/defconfig @@ -27,7 +27,6 @@ CONFIG_CLOCK_MONOTONIC=y CONFIG_CONSOLE_SYSLOG=y CONFIG_IDLETHREAD_STACKSIZE=4194304 CONFIG_LIBM=y -CONFIG_MAX_TASKS=64 CONFIG_PREALLOC_CHILDSTATUS=16 CONFIG_PRIORITY_INHERITANCE=y CONFIG_PTHREAD_MUTEX_TYPES=y diff --git a/boards/x86_64/intel64/qemu-intel64/src/qemu_bringup.c b/boards/x86_64/intel64/qemu-intel64/src/qemu_bringup.c index 23433e02612..7cd5d551372 100644 --- a/boards/x86_64/intel64/qemu-intel64/src/qemu_bringup.c +++ b/boards/x86_64/intel64/qemu-intel64/src/qemu_bringup.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include diff --git a/boards/xtensa/esp32/common/include/esp32_ht16k33.h b/boards/xtensa/esp32/common/include/esp32_ht16k33.h new file mode 100644 index 00000000000..9464ecc8938 --- /dev/null +++ b/boards/xtensa/esp32/common/include/esp32_ht16k33.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/xtensa/esp32/common/include/esp32_ht16k33.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_BOARD_HT16K33_H +#define __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_BOARD_HT16K33_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ht16k33_initialize + * + * Description: + * Initialize and register the HT16K32 LED Display. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/slcdN + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_ht16k33_initialize(int devno, int busno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_BOARD_HT16K33_H */ diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32_rom.ld b/boards/xtensa/esp32/common/scripts/esp32_rom.ld similarity index 100% rename from boards/xtensa/esp32/esp32-devkitc/scripts/esp32_rom.ld rename to boards/xtensa/esp32/common/scripts/esp32_rom.ld diff --git a/boards/xtensa/esp32/common/src/Make.defs b/boards/xtensa/esp32/common/src/Make.defs index 25041197910..928dbe0960f 100644 --- a/boards/xtensa/esp32/common/src/Make.defs +++ b/boards/xtensa/esp32/common/src/Make.defs @@ -42,6 +42,10 @@ ifeq ($(CONFIG_SENSORS_BMP180),y) CSRCS += esp32_bmp180.c endif +ifeq ($(CONFIG_LCD_HT16K33),y) + CSRCS += esp32_ht16k33.c +endif + ifeq ($(CONFIG_CAN_MCP2515),y) CSRCS += esp32_mcp2515.c endif diff --git a/boards/xtensa/esp32/common/src/esp32_bmp180.c b/boards/xtensa/esp32/common/src/esp32_bmp180.c index 37c690798a7..6cf195ab83b 100644 --- a/boards/xtensa/esp32/common/src/esp32_bmp180.c +++ b/boards/xtensa/esp32/common/src/esp32_bmp180.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/libs/libc/pthread/pthread_startup.c b/boards/xtensa/esp32/common/src/esp32_ht16k33.c similarity index 71% rename from libs/libc/pthread/pthread_startup.c rename to boards/xtensa/esp32/common/src/esp32_ht16k33.c index 53be0326092..34170a3cac4 100644 --- a/libs/libc/pthread/pthread_startup.c +++ b/boards/xtensa/esp32/common/src/esp32_ht16k33.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libs/libc/pthread/pthread_startup.c + * boards/xtensa/esp32/common/src/esp32_ht16k33.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -24,23 +24,26 @@ #include -#include -#include +#include +#include -#include +#include +#include -#if !defined(CONFIG_BUILD_FLAT) && !defined(__KERNEL__) +#include "esp32_board_i2c.h" +#include "esp32_i2c.h" +#include "esp32_ht16k33.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /**************************************************************************** - * Private Type Declarations + * Private Types ****************************************************************************/ /**************************************************************************** - * Public Data + * Private Function Prototypes ****************************************************************************/ /**************************************************************************** @@ -48,7 +51,7 @@ ****************************************************************************/ /**************************************************************************** - * Private Function Prototypes + * Public Data ****************************************************************************/ /**************************************************************************** @@ -60,34 +63,47 @@ ****************************************************************************/ /**************************************************************************** - * Name: pthread_startup + * Name: board_ht16k33_initialize * * Description: - * This function is the user-space, pthread startup function. It is called - * from up_pthread_start() in user-mode. + * Initialize and register the BMP180 Pressure Sensor driver. * * Input Parameters: - * entrypt - The user-space address of the pthread entry point - * arg - Standard argument for the pthread entry point + * devno - The device number, used to build the device path as /dev/pressN + * busno - The I2C bus number * * Returned Value: - * None. This function does not return. + * Zero (OK) on success; a negated errno value on failure. * ****************************************************************************/ -void pthread_startup(pthread_startroutine_t entrypt, pthread_addr_t arg) +int board_ht16k33_initialize(int devno, int busno) { - pthread_addr_t exit_status; + struct i2c_master_s *i2c; + int ret; - DEBUGASSERT(entrypt); + sninfo("Initializing HT16K33!\n"); - /* Pass control to the thread entry point. */ + /* Initialize I2C Bus */ - exit_status = entrypt(arg); + i2c = esp32_i2cbus_initialize(busno); - /* The pthread has returned */ + if (i2c) + { + /* Register the HT16K33 Driver at the specified location. */ - pthread_exit(exit_status); + ret = ht16k33_register(devno, i2c); + if (ret < 0) + { + lcderr("ERROR: ht16k33_register(%d) failed: %d\n", devno, ret); + return ret; + } + } + else + { + ret = -ENODEV; + } + + return ret; } -#endif /* !CONFIG_BUILD_FLAT && !__KERNEL__ */ diff --git a/boards/xtensa/esp32/common/src/esp32_mcp2515.c b/boards/xtensa/esp32/common/src/esp32_mcp2515.c index d7055bbda16..5f5d06c0299 100644 --- a/boards/xtensa/esp32/common/src/esp32_mcp2515.c +++ b/boards/xtensa/esp32/common/src/esp32_mcp2515.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/aes/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/aes/defconfig index a1fed199ce7..19d81b1b2c7 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/aes/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/aes/defconfig @@ -34,7 +34,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/autopm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/autopm/defconfig new file mode 100644 index 00000000000..867be758c43 --- /dev/null +++ b/boards/xtensa/esp32/esp32-devkitc/configs/autopm/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-devkitc" +CONFIG_ARCH_BOARD_ESP32_DEVKITC=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32_AUTO_SLEEP=y +CONFIG_ESP32_MTD_SIZE=0x80000 +CONFIG_ESP32_SPIFLASH=y +CONFIG_ESP32_UART0=y +CONFIG_ESP32_WIFI_SAVE_PARAM=y +CONFIG_ESP32_WIRELESS=y +CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y +CONFIG_FS_PROCFS=y +CONFIG_FS_SPIFFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_MM_REGIONS=3 +CONFIG_NAME_MAX=48 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SIG_DEFAULT=y +CONFIG_SPIFFS_NAME_MAX=48 +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig index 37bcef8a4d6..a8e31091c8b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig @@ -32,7 +32,6 @@ CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig new file mode 100644 index 00000000000..73183fe5aa0 --- /dev/null +++ b/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-devkitc" +CONFIG_ARCH_BOARD_ESP32_DEVKITC=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_USE_TEXT_HEAP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ELF=y +CONFIG_ESP32_IRAM_HEAP=y +CONFIG_ESP32_UART0=y +CONFIG_EXAMPLES_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXECFUNCS_HAVE_SYMTAB=y +CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig index 1162b6dc020..8ba0cbc813a 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig index 9894a0d4b89..4bcd7b9155a 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mmcsdspi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mmcsdspi/defconfig index e703f4005ae..f258664ca25 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mmcsdspi/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mmcsdspi/defconfig @@ -34,7 +34,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=4000000 CONFIG_MM_REGIONS=3 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig index e43aae77c99..2f6a8555ccd 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEBUG_ASSERTIONS=y @@ -29,6 +30,7 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEBUG_WARN=y +CONFIG_ESP32_IRAM_HEAP=y CONFIG_ESP32_UART0=y CONFIG_EXAMPLES_MODULE=y CONFIG_EXPERIMENTAL=y @@ -36,10 +38,8 @@ CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_MACOS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MODULE=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig index f6707896c64..9056169e5db 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig @@ -35,7 +35,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 CONFIG_IOB_THROTTLE=0 CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 CONFIG_NETDB_DNSCLIENT=y @@ -48,7 +47,6 @@ CONFIG_NETUTILS_MQTTC=y CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_NOTIFIER=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/netnsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/netnsh/defconfig index 3d2826667fa..c00eff379cb 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/netnsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/netnsh/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig index 90a518a0c82..c567711436d 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig index 742d40cc7de..5e4e71eda07 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig @@ -33,7 +33,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig index a1f967043e7..ebe92afbe43 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig index c1fe3cbd72c..578d60c04ee 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig index d2dad9dedd4..ec4331f4343 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig @@ -32,7 +32,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=36 CONFIG_IOB_NCHAINS=36 CONFIG_IOB_THROTTLE=8 -CONFIG_MAX_TASKS=16 CONFIG_MM_IOB=y CONFIG_MM_REGIONS=4 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig index b1d01e14753..2197d38a916 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig new file mode 100644 index 00000000000..de8277eb9ee --- /dev/null +++ b/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-devkitc" +CONFIG_ARCH_BOARD_ESP32_DEVKITC=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32_RT_TIMER=y +CONFIG_ESP32_UART0=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_RTC_NALARMS=2 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/smp/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/smp/defconfig index d3cf21c1e98..9f0fddf116d 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/smp/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/smp/defconfig @@ -15,10 +15,13 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y CONFIG_ESP32_UART0=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y @@ -26,7 +29,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=4 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y @@ -43,6 +45,7 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_SMP=y CONFIG_SMP_NCPUS=2 CONFIG_SPI=y +CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig index 3c462782966..5835d568f13 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_OS_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEBUG_ASSERTIONS=y @@ -30,6 +31,7 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEBUG_WARN=y +CONFIG_ESP32_IRAM_HEAP=y CONFIG_ESP32_UART0=y CONFIG_EXAMPLES_SOTEST=y CONFIG_EXPERIMENTAL=y @@ -37,11 +39,9 @@ CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_MACOS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_DLFCN=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig index 076140e01da..c62111c5b3a 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MTD_SMART=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/sta_softap/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/sta_softap/defconfig index 7d62d88257a..7a8cb6eb83c 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/sta_softap/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/sta_softap/defconfig @@ -42,7 +42,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_LATEINIT=y @@ -53,7 +52,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ETH_PKTSIZE=1514 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig new file mode 100644 index 00000000000..263313331db --- /dev/null +++ b/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-devkitc" +CONFIG_ARCH_BOARD_ESP32_DEVKITC=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32_TICKLESS=y +CONFIG_ESP32_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig index 2d17e0356c5..96cd5623d24 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig @@ -30,7 +30,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wapi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wapi/defconfig index 6ce95a34bbd..dd903a985e5 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wapi/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wapi/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y +CONFIG_DEV_URANDOM=y CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32_MTD_SIZE=0x80000 @@ -33,23 +34,25 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_NAMESIZE=64 CONFIG_NETDEV_LATEINIT=y CONFIG_NETDEV_PHY_IOCTL=y CONFIG_NETDEV_WIRELESS_IOCTL=y CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1518 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 +CONFIG_NSH_LINELEN=300 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_MUTEX_TYPES=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wapi_smp/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wapi_smp/defconfig index bd1d34cfef3..ed3e4a301fb 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wapi_smp/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wapi_smp/defconfig @@ -52,7 +52,6 @@ CONFIG_NET_BROADCAST=y CONFIG_NET_ETH_PKTSIZE=1514 CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_STATISTICS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig index 82ad1176082..98d901b8de5 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig index dbe61857a17..99999b00b03 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig @@ -29,7 +29,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/Make.defs b/boards/xtensa/esp32/esp32-devkitc/scripts/Make.defs index 873156f9ad3..bf8cc21f100 100644 --- a/boards/xtensa/esp32/esp32-devkitc/scripts/Make.defs +++ b/boards/xtensa/esp32/esp32-devkitc/scripts/Make.defs @@ -24,22 +24,15 @@ include $(TOPDIR)/tools/esp32/Config.mk include $(TOPDIR)/arch/xtensa/src/lx6/Toolchain.defs LDSCRIPT1 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_out.ld -LDSCRIPT3 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_rom.ld -LDSCRIPT4 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_peripherals.ld - -ifeq ($(CONFIG_ESP32_RUN_IRAM),y) - LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_iram.ld -else - LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_flash.ld -endif +LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32.ld +LDSCRIPT3 = $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32_rom.ld ifeq ($(CONFIG_CYGWIN_WINTOOL),y) ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}" ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}" ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}" - ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}" else - ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4) + ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) @@ -91,9 +84,9 @@ CXXELFFLAGS = $(CXXFLAGS) -mtext-section-literals LDELFFLAGS = -r -e main ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}" + LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld}" else - LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld + LDELFFLAGS += -T $(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld endif LDFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32-ft232h.cfg b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32-ft232h.cfg deleted file mode 100644 index 52402c61bad..00000000000 --- a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32-ft232h.cfg +++ /dev/null @@ -1,6 +0,0 @@ -source [find interface/ftdi/um232h.cfg] -transport select jtag -adapter_khz 2000 -set ESP32_FLASH_VOLTAGE 3.3 -set ESP32_RTOS none -source [find target/esp32.cfg] diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.cfg b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.cfg deleted file mode 100644 index a9f94d37dc8..00000000000 --- a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.cfg +++ /dev/null @@ -1,49 +0,0 @@ -# -# Example configuration file to hook up an ESP32 module or board to a JTAG -# adapter. Please modify this file to your local setup. -# -# - - -# Include the configuration for the JTAG adapter. We use the Tian TUMPA here. -# If you have a different interface, please edit this to include the -# configuration file of yours. -# source [find interface/ftdi/olimex-arm-usb-ocd.cfg] - -# The ESP32 only supports JTAG. -transport select jtag - -# The speed of the JTAG interface, in KHz. If you get DSR/DIR errors (and they -# do not relate to OpenOCD trying to read from a memory range without physical -# memory being present there), you can try lowering this. -adapter_khz 200 - -# With no variables set, openocd will configure JTAG for the two cores of the ESP32 and -# will do automatic RTOS detection. This can be be adjusted by uncommenting any of the -# following lines: - -# Only configure the PRO CPU -#set ESP32_ONLYCPU 1 -# Only configure the APP CPU -#set ESP32_ONLYCPU 2 -# Disable RTOS support -set ESP32_RTOS none -# Force RTOS to be FreeRTOS -#set ESP32_RTOS FreeRTOS - -#Source the ESP32 configuration file -source [find target/esp32.cfg] - - -# The TDI pin of ESP32 is also a bootstrap pin that selects the voltage the SPI flash -# chip runs at. When a hard reset happens (e.g. because someone switches the board off -# and on) the ESP32 will use the current TDI value as the bootstrap value because the -# JTAG adapter overrides the pull-up or pull-down resistor that is supposed to do the -# bootstrapping. These lines basically set the idle value of the TDO line to a -# specified value, therefore reducing the chance of a bad bootup due to a bad flash -# voltage greatly. - -# Enable this for 1.8V SPI flash -# esp108 flashbootstrap 1.8 -# Enable this for 3.3V SPI flash -esp108 flashbootstrap 3.3 diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32_flash.ld b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.ld similarity index 94% rename from boards/xtensa/esp32/esp32-devkitc/scripts/esp32_flash.ld rename to boards/xtensa/esp32/esp32-devkitc/scripts/esp32.ld index b9a6f621658..8a5c13afdd2 100644 --- a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32_flash.ld +++ b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/xtensa/esp32/esp32-devkitc/scripts/esp32_flash.ld + * boards/xtensa/esp32/esp32-devkitc/scripts/esp32.ld ****************************************************************************/ /* Default entry point: */ @@ -63,10 +63,10 @@ SECTIONS *(.phyiram .phyiram.*) _iram_text_end = ABSOLUTE(.); - /* Module text area starts at the end of iram0_0_seg */ + /* IRAM heap starts at the end of iram0_0_seg */ . = ALIGN (4); - _smodtext = ABSOLUTE(.); + _siramheap = ABSOLUTE(.); } > iram0_0_seg /* Shared RAM */ @@ -190,7 +190,7 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - } >drom0_0_seg + } >default_rodata_seg .flash.text : { @@ -203,7 +203,7 @@ SECTIONS *(.gnu.version) _text_end = ABSOLUTE(.); _etext = .; - } >iram0_2_seg + } >default_code_seg .rtc.text : { @@ -215,5 +215,10 @@ SECTIONS { *(.rtc.data) *(.rtc.rodata) + + /* Whatever is left from the RTC memory is used as a special heap. */ + + . = ALIGN (4); + _srtcheap = ABSOLUTE(.); } > rtc_slow_seg } diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld index 22d8226865d..ac974b379c6 100644 --- a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld +++ b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld @@ -28,17 +28,16 @@ MEMORY iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 - /* Even though the segment name is iram, it is actually mapped to flash. + /* Flash mapped instruction data. * - * NOTE: (0x20 offset above is a convenience for the app binary image - * generation. + * The 0x20 offset is a convenience for the app binary image generation. * Flash cache has 64KB pages. The .bin file which is flashed to the chip * has a 0x18 byte file header, and each segment has a 0x08 byte segment * header. Setting this offset makes it simple to meet the flash cache MMU's * constraint that (paddr % 64KB == vaddr % 64KB).) */ - iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20 + irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20 /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. * Enabling Bluetooth & Trace Memory features in menuconfig will decrease @@ -74,10 +73,22 @@ MEMORY extmem_seg(RWX) : org = 0x3f800000, len = 0x400000 } +#if CONFIG_ESP32_DEVKIT_RUN_IRAM + REGION_ALIAS("default_rodata_seg", dram0_0_seg); + REGION_ALIAS("default_code_seg", iram0_0_seg); +#else + REGION_ALIAS("default_rodata_seg", drom0_0_seg); + REGION_ALIAS("default_code_seg", irom0_0_seg); +#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */ + /* Heap ends at top of dram0_0_seg */ _eheap = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; -/* Module text area ends at top of dram0_0_seg */ +/* IRAM heap ends at top of dram0_0_seg */ -_emodtext = 0x400a0000; +_eiramheap = 0x400a0000; + +/* Mark the end of the RTC heap (top of the RTC region) */ + +_ertcheap = 0x50001fff; diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32_peripherals.ld b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32_peripherals.ld deleted file mode 100644 index 46101b26cfd..00000000000 --- a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32_peripherals.ld +++ /dev/null @@ -1,24 +0,0 @@ -/**************************************************************************** - * boards/xtensa/esp32/esp32-devkitc/scripts/esp32_peripherals.ld - ****************************************************************************/ - -PROVIDE ( UART0 = 0x3ff40000 ); -PROVIDE ( SPI1 = 0x3ff42000 ); -PROVIDE ( SPI0 = 0x3ff43000 ); -PROVIDE ( GPIO = 0x3ff44000 ); -PROVIDE ( SIGMADELTA = 0x3ff44f00 ); -PROVIDE ( UHCI1 = 0x3ff4C000 ); -PROVIDE ( I2S0 = 0x3ff4F000 ); -PROVIDE ( UART1 = 0x3ff50000 ); -PROVIDE ( I2C0 = 0x3ff53000 ); -PROVIDE ( UHCI0 = 0x3ff54000 ); -PROVIDE ( RMT = 0x3ff56000 ); -PROVIDE ( PCNT = 0x3ff57000 ); -PROVIDE ( LEDC = 0x3ff59000 ); -PROVIDE ( TIMERG0 = 0x3ff5F000 ); -PROVIDE ( TIMERG1 = 0x3ff60000 ); -PROVIDE ( SPI2 = 0x3ff64000 ); -PROVIDE ( SPI3 = 0x3ff65000 ); -PROVIDE ( I2C1 = 0x3ff67000 ); -PROVIDE ( I2S1 = 0x3ff6D000 ); -PROVIDE ( UART2 = 0x3ff6E000 ); diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c index 21dc6668778..ca844a6c3ab 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c @@ -74,14 +74,26 @@ # include "esp32_bmp180.h" #endif +#ifdef CONFIG_LCD_HT16K33 +# include "esp32_ht16k33.h" +#endif + #ifdef CONFIG_ESP32_AES_ACCELERATOR # include "esp32_aes.h" #endif +#ifdef CONFIG_ESP32_RT_TIMER +# include "esp32_rt_timer.h" +#endif + #ifdef CONFIG_INPUT_BUTTONS # include #endif +#ifdef CONFIG_RTC_DRIVER +# include "esp32_rtc_lowerhalf.h" +#endif + #include "esp32-devkitc.h" /**************************************************************************** @@ -186,6 +198,14 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESP32_RT_TIMER + ret = esp32_rt_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); + } +#endif + #ifdef CONFIG_ESP32_WIRELESS ret = board_wlan_init(); if (ret < 0) @@ -337,6 +357,18 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_LCD_HT16K33 + /* Try to register HT16K33 in the I2C0 */ + + ret = board_ht16k33_initialize(0, 0); + + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize HT16K33 driver: %d\n", ret); + return ret; + } +#endif + #ifdef CONFIG_INPUT_BUTTONS /* Register the BUTTON driver */ @@ -347,6 +379,17 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the ESP32 RTC driver */ + + ret = esp32_rtc_driverinit(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_buttons.c index fa7b21ed20c..6d4ee4553cb 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_buttons.c @@ -24,10 +24,11 @@ #include +#include +#include #include #include #include -#include #include #include diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c index 3f85f655802..8b2cd41c42f 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c @@ -25,9 +25,9 @@ #include #include -#include #include #include +#include #include #include diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_spiflash.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_spiflash.c index a9deca2c9c6..2ccba641ead 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_spiflash.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_spiflash.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/autopm/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/autopm/defconfig new file mode 100644 index 00000000000..6d770f63750 --- /dev/null +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/autopm/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-ethernet-kit" +CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32_AUTO_SLEEP=y +CONFIG_ESP32_MTD_SIZE=0x80000 +CONFIG_ESP32_SPIFLASH=y +CONFIG_ESP32_UART0=y +CONFIG_ESP32_WIFI_SAVE_PARAM=y +CONFIG_ESP32_WIRELESS=y +CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y +CONFIG_FS_PROCFS=y +CONFIG_FS_SPIFFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_MM_REGIONS=3 +CONFIG_NAME_MAX=48 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SIG_DEFAULT=y +CONFIG_SPIFFS_NAME_MAX=48 +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig index f92bd2f75f6..e0cfcb2cf12 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig @@ -31,7 +31,6 @@ CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig index 9170ab87c4e..8953a8d0da3 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808 diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig index 01f9a76e274..5095ef85f93 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig @@ -24,7 +24,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig index 64f635506bd..e2aa263fc85 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig new file mode 100644 index 00000000000..8d82c4c67cd --- /dev/null +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-ethernet-kit" +CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32_RT_TIMER=y +CONFIG_ESP32_UART0=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_RTC_NALARMS=2 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/tickless/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/tickless/defconfig new file mode 100644 index 00000000000..7fd258b05be --- /dev/null +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/tickless/defconfig @@ -0,0 +1,45 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-ethernet-kit" +CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32_TICKLESS=y +CONFIG_ESP32_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/wapi/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/wapi/defconfig index 06ecfd3568a..e32bf6818d9 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/wapi/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/wapi/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 CONFIG_NETDB_DNSCLIENT=y @@ -42,7 +41,6 @@ CONFIG_NETDEV_WIRELESS_IOCTL=y CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/Make.defs b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/Make.defs index 1b4e115248a..f858a6a4101 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/Make.defs +++ b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/Make.defs @@ -24,22 +24,15 @@ include $(TOPDIR)/tools/esp32/Config.mk include $(TOPDIR)/arch/xtensa/src/lx6/Toolchain.defs LDSCRIPT1 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_out.ld -LDSCRIPT3 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_rom.ld -LDSCRIPT4 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_peripherals.ld - -ifeq ($(CONFIG_ESP32_RUN_IRAM),y) - LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_iram.ld -else - LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_flash.ld -endif +LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32.ld +LDSCRIPT3 = $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32_rom.ld ifeq ($(CONFIG_CYGWIN_WINTOOL),y) ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}" ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}" ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}" - ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}" else - ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4) + ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) @@ -91,9 +84,9 @@ CXXELFFLAGS = $(CXXFLAGS) -mtext-section-literals LDELFFLAGS = -r -e main ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}" + LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld}" else - LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld + LDELFFLAGS += -T $(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld endif LDFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_flash.ld b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.ld similarity index 94% rename from boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_flash.ld rename to boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.ld index ac02d69dc42..4667cbb9c80 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_flash.ld +++ b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_flash.ld + * boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.ld ****************************************************************************/ /* Default entry point: */ @@ -66,10 +66,10 @@ SECTIONS *(.phyiram .phyiram.*) _iram_text_end = ABSOLUTE(.); - /* Module text area starts at the end of iram0_0_seg */ + /* IRAM heap starts at the end of iram0_0_seg */ . = ALIGN (4); - _smodtext = ABSOLUTE(.); + _siramheap = ABSOLUTE(.); } > iram0_0_seg /* Shared RAM */ @@ -192,7 +192,7 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - } >drom0_0_seg + } >default_rodata_seg .flash.text : { @@ -205,7 +205,7 @@ SECTIONS *(.gnu.version) _text_end = ABSOLUTE(.); _etext = .; - } >iram0_2_seg + } >default_code_seg .rtc.text : { @@ -217,5 +217,10 @@ SECTIONS { *(.rtc.data) *(.rtc.rodata) + + /* Whatever is left from the RTC memory is used as a special heap. */ + + . = ALIGN (4); + _srtcheap = ABSOLUTE(.); } > rtc_slow_seg } diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld index 63024c07baf..fa3459a0fb6 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld +++ b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld @@ -28,17 +28,16 @@ MEMORY iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 - /* Even though the segment name is iram, it is actually mapped to flash. + /* Flash mapped instruction data. * - * NOTE: (0x20 offset above is a convenience for the app binary image - * generation. + * The 0x20 offset is a convenience for the app binary image generation. * Flash cache has 64KB pages. The .bin file which is flashed to the chip * has a 0x18 byte file header, and each segment has a 0x08 byte segment * header. Setting this offset makes it simple to meet the flash cache MMU's * constraint that (paddr % 64KB == vaddr % 64KB).) */ - iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20 + irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20 /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. * Enabling Bluetooth & Trace Memory features in menuconfig will decrease @@ -74,10 +73,22 @@ MEMORY extmem_seg(RWX) : org = 0x3f800000, len = 0x400000 } +#if CONFIG_ESP32_DEVKIT_RUN_IRAM + REGION_ALIAS("default_rodata_seg", dram0_0_seg); + REGION_ALIAS("default_code_seg", iram0_0_seg); +#else + REGION_ALIAS("default_rodata_seg", drom0_0_seg); + REGION_ALIAS("default_code_seg", irom0_0_seg); +#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */ + /* Heap ends at top of dram0_0_seg */ _eheap = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; -/* Module text area ends at top of dram0_0_seg */ +/* IRAM heap ends at top of dram0_0_seg */ -_emodtext = 0x400a0000; +_eiramheap = 0x400a0000; + +/* Mark the end of the RTC heap (top of the RTC region) */ + +_ertcheap = 0x50001fff; diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_peripherals.ld b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_peripherals.ld deleted file mode 100644 index 2f3262e667f..00000000000 --- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_peripherals.ld +++ /dev/null @@ -1,24 +0,0 @@ -/**************************************************************************** - * boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_peripherals.ld - ****************************************************************************/ - -PROVIDE ( UART0 = 0x3ff40000 ); -PROVIDE ( SPI1 = 0x3ff42000 ); -PROVIDE ( SPI0 = 0x3ff43000 ); -PROVIDE ( GPIO = 0x3ff44000 ); -PROVIDE ( SIGMADELTA = 0x3ff44f00 ); -PROVIDE ( UHCI1 = 0x3ff4C000 ); -PROVIDE ( I2S0 = 0x3ff4F000 ); -PROVIDE ( UART1 = 0x3ff50000 ); -PROVIDE ( I2C0 = 0x3ff53000 ); -PROVIDE ( UHCI0 = 0x3ff54000 ); -PROVIDE ( RMT = 0x3ff56000 ); -PROVIDE ( PCNT = 0x3ff57000 ); -PROVIDE ( LEDC = 0x3ff59000 ); -PROVIDE ( TIMERG0 = 0x3ff5F000 ); -PROVIDE ( TIMERG1 = 0x3ff60000 ); -PROVIDE ( SPI2 = 0x3ff64000 ); -PROVIDE ( SPI3 = 0x3ff65000 ); -PROVIDE ( I2C1 = 0x3ff67000 ); -PROVIDE ( I2S1 = 0x3ff6D000 ); -PROVIDE ( UART2 = 0x3ff6E000 ); diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_rom.ld b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_rom.ld deleted file mode 100644 index 6088eeb708a..00000000000 --- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_rom.ld +++ /dev/null @@ -1,1858 +0,0 @@ -/* -ESP32 ROM address table -Generated for ROM with MD5sum: -ab8282ae908fe9e7a63fb2a4ac2df013 ../../rom_image/prorom.elf -*/ - -PROVIDE ( abort = 0x4000bba4 ); -PROVIDE ( abs = 0x40056340 ); -PROVIDE ( __absvdi2 = 0x4006387c ); -PROVIDE ( __absvsi2 = 0x40063868 ); -PROVIDE ( Add2SelfBigHex256 = 0x40015b7c ); -PROVIDE ( AddBigHex256 = 0x40015b28 ); -PROVIDE ( AddBigHexModP256 = 0x40015c98 ); -PROVIDE ( __adddf3 = 0x40002590 ); -PROVIDE ( AddP256 = 0x40015c74 ); -PROVIDE ( AddPdiv2_256 = 0x40015ce0 ); -PROVIDE ( __addsf3 = 0x400020e8 ); -PROVIDE ( __addvdi3 = 0x40002cbc ); -PROVIDE ( __addvsi3 = 0x40002c98 ); -PROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c ); -PROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 ); -PROVIDE ( aes_unwrap = 0x4005ccf0 ); -PROVIDE ( app_gpio_arg = 0x3ffe003c ); -PROVIDE ( app_gpio_handler = 0x3ffe0040 ); -PROVIDE ( __ascii_wctomb = 0x40058ef0 ); -PROVIDE ( asctime = 0x40059588 ); -PROVIDE ( asctime_r = 0x40000ec8 ); -PROVIDE ( __ashldi3 = 0x4000c818 ); -PROVIDE ( __ashrdi3 = 0x4000c830 ); -PROVIDE ( asiprintf = 0x40056d9c ); -PROVIDE ( _asiprintf_r = 0x40056d4c ); -PROVIDE ( asniprintf = 0x40056cd8 ); -PROVIDE ( _asniprintf_r = 0x40056c64 ); -PROVIDE ( asnprintf = 0x40056cd8 ); -PROVIDE ( _asnprintf_r = 0x40056c64 ); -PROVIDE ( asprintf = 0x40056d9c ); -PROVIDE ( _asprintf_r = 0x40056d4c ); -PROVIDE ( atoi = 0x400566c4 ); -PROVIDE ( _atoi_r = 0x400566d4 ); -PROVIDE ( atol = 0x400566ec ); -PROVIDE ( _atol_r = 0x400566fc ); -PROVIDE ( base64_decode = 0x4005ced8 ); -PROVIDE ( base64_encode = 0x4005cdbc ); -PROVIDE ( BasePoint_x_256 = 0x3ff97488 ); -PROVIDE ( BasePoint_y_256 = 0x3ff97468 ); -PROVIDE ( bigHexInversion256 = 0x400168f0 ); -PROVIDE ( bigHexP256 = 0x3ff973bc ); -PROVIDE ( __bswapdi2 = 0x400649c4 ); -PROVIDE ( __bswapsi2 = 0x4006499c ); -PROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c ); -PROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 ); -PROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 ); -PROVIDE ( btdm_r_data_init = 0x4001002c ); -PROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 ); -PROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 ); -PROVIDE ( btdm_r_ip_func_p_set = 0x40019afc ); -PROVIDE ( btdm_r_modules_func_p_get = 0x4005427c ); -PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 ); -PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 ); -PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 ); -PROVIDE ( bzero = 0x4000c1f4 ); -PROVIDE ( cache_flash_mmu_set = 0x400095e0 ); -PROVIDE ( cache_flush = 0x40009a14 ); -PROVIDE ( cache_read_disable = 0x40009ab8 ); -PROVIDE ( cache_read_enable = 0x40009a84 ); -PROVIDE ( cache_read_init = 0x40009950 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( calc_rtc_memory_crc = 0x40008170 ); -PROVIDE ( calloc = 0x4000bee4 ); -PROVIDE ( _calloc_r = 0x4000bbf8 ); -PROVIDE ( check_pos = 0x400068b8 ); -PROVIDE ( _cleanup = 0x40001df8 ); -PROVIDE ( _cleanup_r = 0x40001d48 ); -PROVIDE ( __clear_cache = 0x40063860 ); -PROVIDE ( close = 0x40001778 ); -PROVIDE ( _close_r = 0x4000bd3c ); -PROVIDE ( __clrsbdi2 = 0x40064a38 ); -PROVIDE ( __clrsbsi2 = 0x40064a20 ); -PROVIDE ( __clzdi2 = 0x4000ca50 ); -PROVIDE ( __clzsi2 = 0x4000c7e8 ); -PROVIDE ( __cmpdi2 = 0x40063820 ); -PROVIDE ( co_default_bdaddr = 0x3ffae704 ); -PROVIDE ( co_null_bdaddr = 0x3ffb80e0 ); -PROVIDE ( co_sca2ppm = 0x3ff971e8 ); -PROVIDE ( crc16_be = 0x4005d09c ); -PROVIDE ( crc16_le = 0x4005d05c ); -PROVIDE ( crc32_be = 0x4005d024 ); -PROVIDE ( crc32_le = 0x4005cfec ); -PROVIDE ( crc8_be = 0x4005d114 ); -PROVIDE ( crc8_le = 0x4005d0e0 ); -PROVIDE ( creat = 0x40000e8c ); -PROVIDE ( ctime = 0x400595b0 ); -PROVIDE ( ctime_r = 0x400595c4 ); -PROVIDE ( _ctype_ = 0x3ff96354 ); -PROVIDE ( __ctype_ptr__ = 0x3ff96350 ); -PROVIDE ( __ctzdi2 = 0x4000ca64 ); -PROVIDE ( __ctzsi2 = 0x4000c7f0 ); -PROVIDE ( _data_end = 0x4000d5c8 ); -PROVIDE ( _data_end_btdm_rom = 0x4000d4f8 ); -PROVIDE ( _data_start = 0x4000d4f8 ); -PROVIDE ( _data_start_btdm_rom = 0x4000d4f4 ); -PROVIDE ( _data_start_btdm = 0x3ffae6e0); -PROVIDE ( _data_end_btdm = 0x3ffaff10); -PROVIDE ( _sbss_btdm = 0x3ffb8000); -PROVIDE ( _ebss_btdm = 0x3ffbff70); -PROVIDE ( _daylight = 0x3ffae0a4 ); -PROVIDE ( dbg_default_handler = 0x3ff97218 ); -PROVIDE ( dbg_state = 0x3ffb8d5d ); -PROVIDE ( DebugE256PublicKey_x = 0x3ff97428 ); -PROVIDE ( DebugE256PublicKey_y = 0x3ff97408 ); -PROVIDE ( DebugE256SecretKey = 0x3ff973e8 ); -PROVIDE ( _DebugExceptionVector = 0x40000280 ); -PROVIDE ( debug_timer = 0x3ffe042c ); -PROVIDE ( debug_timerfn = 0x3ffe0430 ); -PROVIDE ( dh_group14_generator = 0x3ff9ac60 ); -PROVIDE ( dh_group14_prime = 0x3ff9ab60 ); -PROVIDE ( dh_group15_generator = 0x3ff9ab5f ); -PROVIDE ( dh_group15_prime = 0x3ff9a9df ); -PROVIDE ( dh_group16_generator = 0x3ff9a9de ); -PROVIDE ( dh_group16_prime = 0x3ff9a7de ); -PROVIDE ( dh_group17_generator = 0x3ff9a7dd ); -PROVIDE ( dh_group17_prime = 0x3ff9a4dd ); -PROVIDE ( dh_group18_generator = 0x3ff9a4dc ); -PROVIDE ( dh_group18_prime = 0x3ff9a0dc ); -PROVIDE ( dh_group1_generator = 0x3ff9ae03 ); -PROVIDE ( dh_group1_prime = 0x3ff9ada3 ); -PROVIDE ( dh_group2_generator = 0x3ff9ada2 ); -PROVIDE ( dh_group2_prime = 0x3ff9ad22 ); -PROVIDE ( dh_group5_generator = 0x3ff9ad21 ); -PROVIDE ( dh_group5_prime = 0x3ff9ac61 ); -PROVIDE ( div = 0x40056348 ); -PROVIDE ( __divdc3 = 0x40064460 ); -PROVIDE ( __divdf3 = 0x40002954 ); -PROVIDE ( __divdi3 = 0x4000ca84 ); -PROVIDE ( __divsc3 = 0x40064200 ); -PROVIDE ( __divsf3 = 0x4000234c ); -PROVIDE ( __divsi3 = 0x4000c7b8 ); -PROVIDE ( _DoubleExceptionVector = 0x400003c0 ); -PROVIDE ( dummy_len_plus = 0x3ffae290 ); -PROVIDE ( __dummy_lock = 0x4000c728 ); -PROVIDE ( __dummy_lock_try = 0x4000c730 ); -PROVIDE ( ecc_env = 0x3ffb8d60 ); -PROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 ); -PROVIDE ( em_buf_env = 0x3ffb8d74 ); -PROVIDE ( environ = 0x3ffae0b4 ); -PROVIDE ( __env_lock = 0x40001fd4 ); -PROVIDE ( __env_unlock = 0x40001fe0 ); -PROVIDE ( __eqdf2 = 0x400636a8 ); -PROVIDE ( __eqsf2 = 0x40063374 ); -PROVIDE ( esp_crc8 = 0x4005d144 ); -PROVIDE ( _etext = 0x4000d66c ); -PROVIDE ( ets_aes_crypt = 0x4005c9b8 ); -PROVIDE ( ets_aes_disable = 0x4005c8f8 ); -PROVIDE ( ets_aes_enable = 0x4005c8cc ); -PROVIDE ( ets_aes_set_endian = 0x4005c928 ); -PROVIDE ( ets_aes_setkey_dec = 0x4005c994 ); -PROVIDE ( ets_aes_setkey_enc = 0x4005c97c ); -PROVIDE ( ets_bigint_disable = 0x4005c4e0 ); -PROVIDE ( ets_bigint_enable = 0x4005c498 ); -PROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 ); -PROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 ); -PROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 ); -PROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c ); -PROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 ); -PROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc ); -PROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 ); -PROVIDE ( ets_bigint_mult_prepare = 0x4005c630 ); -PROVIDE ( ets_bigint_wait_finish = 0x4005c520 ); -PROVIDE ( ets_delay_us = 0x40008534 ); -PROVIDE ( ets_efuse_get_8M_clock = 0x40008710 ); -PROVIDE ( ets_efuse_get_spiconfig = 0x40008658 ); -PROVIDE ( ets_efuse_program_op = 0x40008628 ); -PROVIDE ( ets_efuse_read_op = 0x40008600 ); -PROVIDE ( ets_get_cpu_frequency = 0x4000855c ); -PROVIDE ( ets_get_detected_xtal_freq = 0x40008588 ); -PROVIDE ( ets_get_xtal_scale = 0x4000856c ); -PROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 ); -PROVIDE ( ets_install_putc1 = 0x40007d18 ); -PROVIDE ( ets_install_putc2 = 0x40007d38 ); -PROVIDE ( ets_install_uart_printf = 0x40007d28 ); -PROVIDE ( ets_intr_count = 0x3ffe03fc ); -PROVIDE ( ets_intr_lock = 0x400067b0 ); -PROVIDE ( ets_intr_unlock = 0x400067c4 ); -PROVIDE ( ets_isr_attach = 0x400067ec ); -PROVIDE ( ets_isr_mask = 0x400067fc ); -PROVIDE ( ets_isr_unmask = 0x40006808 ); -PROVIDE ( ets_post = 0x4000673c ); -PROVIDE ( ets_printf = 0x40007d54 ); -PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 ); -PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 ); -PROVIDE ( ets_readySet_ = 0x3ffe01f0 ); -PROVIDE ( ets_run = 0x400066bc ); -PROVIDE ( ets_secure_boot_check = 0x4005cb40 ); -PROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 ); -PROVIDE ( ets_secure_boot_check_start = 0x4005cbcc ); -PROVIDE ( ets_secure_boot_finish = 0x4005ca84 ); -PROVIDE ( ets_secure_boot_hash = 0x4005cad4 ); -PROVIDE ( ets_secure_boot_obtain = 0x4005cb14 ); -PROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 ); -PROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 ); -PROVIDE ( ets_secure_boot_start = 0x4005ca34 ); -PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c ); -PROVIDE ( ets_set_idle_cb = 0x40006674 ); -PROVIDE ( ets_set_startup_callback = 0x4000688c ); -PROVIDE ( ets_set_user_start = 0x4000687c ); -PROVIDE ( ets_sha_disable = 0x4005c0a8 ); -PROVIDE ( ets_sha_enable = 0x4005c07c ); -PROVIDE ( ets_sha_finish = 0x4005c104 ); -PROVIDE ( ets_sha_init = 0x4005c0d4 ); -PROVIDE ( ets_sha_update = 0x4005c2a0 ); -PROVIDE ( ets_startup_callback = 0x3ffe0404 ); -PROVIDE ( ets_task = 0x40006688 ); -PROVIDE ( ets_timer_arm = 0x40008368 ); -PROVIDE ( ets_timer_arm_us = 0x400083ac ); -PROVIDE ( ets_timer_disarm = 0x400083ec ); -PROVIDE ( ets_timer_done = 0x40008428 ); -PROVIDE ( ets_timer_handler_isr = 0x40008454 ); -PROVIDE ( ets_timer_init = 0x400084e8 ); -PROVIDE ( ets_timer_setfn = 0x40008350 ); -PROVIDE ( ets_unpack_flash_code = 0x40007018 ); -PROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c ); -PROVIDE ( ets_update_cpu_frequency = 0x40008550 ); -PROVIDE ( ets_waiti0 = 0x400067d8 ); -PROVIDE ( exc_cause_table = 0x3ff991d0 ); -PROVIDE ( _exit_r = 0x4000bd28 ); -PROVIDE ( __extendsfdf2 = 0x40002c34 ); -PROVIDE ( fclose = 0x400020ac ); -PROVIDE ( _fclose_r = 0x40001fec ); -PROVIDE ( fflush = 0x40059394 ); -PROVIDE ( _fflush_r = 0x40059320 ); -PROVIDE ( __ffsdi2 = 0x4000ca2c ); -PROVIDE ( __ffssi2 = 0x4000c804 ); -PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 ); -PROVIDE ( FilePacketSendReqMsgProc = 0x40008860 ); -PROVIDE ( _findenv_r = 0x40001f44 ); -PROVIDE ( fiprintf = 0x40056efc ); -PROVIDE ( _fiprintf_r = 0x40056ed8 ); -PROVIDE ( fiscanf = 0x40058884 ); -PROVIDE ( _fiscanf_r = 0x400588b4 ); -PROVIDE ( __fixdfdi = 0x40002ac4 ); -PROVIDE ( __fixdfsi = 0x40002a78 ); -PROVIDE ( __fixsfdi = 0x4000244c ); -PROVIDE ( __fixsfsi = 0x4000240c ); -PROVIDE ( __fixunsdfsi = 0x40002b30 ); -PROVIDE ( __fixunssfdi = 0x40002504 ); -PROVIDE ( __fixunssfsi = 0x400024ac ); -PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 ); -PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c ); -PROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 ); -PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 ); -PROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec ); -PROVIDE ( __floatdidf = 0x4000c988 ); -PROVIDE ( __floatdisf = 0x4000c8c0 ); -PROVIDE ( __floatsidf = 0x4000c944 ); -PROVIDE ( __floatsisf = 0x4000c870 ); -PROVIDE ( __floatundidf = 0x4000c978 ); -PROVIDE ( __floatundisf = 0x4000c8b0 ); -PROVIDE ( __floatunsidf = 0x4000c938 ); -PROVIDE ( __floatunsisf = 0x4000c864 ); -PROVIDE ( __fp_lock_all = 0x40001f1c ); -PROVIDE ( fprintf = 0x40056efc ); -PROVIDE ( _fprintf_r = 0x40056ed8 ); -PROVIDE ( __fp_unlock_all = 0x40001f30 ); -PROVIDE ( fputwc = 0x40058ea8 ); -PROVIDE ( __fputwc = 0x40058da0 ); -PROVIDE ( _fputwc_r = 0x40058e4c ); -PROVIDE ( free = 0x4000beb8 ); -PROVIDE ( _free_r = 0x4000bbcc ); -PROVIDE ( fscanf = 0x40058884 ); -PROVIDE ( _fscanf_r = 0x400588b4 ); -PROVIDE ( _fstat_r = 0x4000bccc ); -PROVIDE ( _fwalk = 0x4000c738 ); -PROVIDE ( _fwalk_reent = 0x4000c770 ); -PROVIDE ( __gcc_bcmp = 0x40064a70 ); -PROVIDE ( __gedf2 = 0x40063768 ); -PROVIDE ( _GeneralException = 0x40000e14 ); -PROVIDE ( __gesf2 = 0x4006340c ); -PROVIDE ( __get_current_time_locale = 0x40001834 ); -PROVIDE ( _getenv_r = 0x40001fbc ); -PROVIDE ( _getpid_r = 0x4000bcfc ); -PROVIDE ( __getreent = 0x4000be8c ); -PROVIDE ( _gettimeofday_r = 0x4000bc58 ); -PROVIDE ( __gettzinfo = 0x40001fcc ); -PROVIDE ( GetUartDevice = 0x40009598 ); -PROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 ); -PROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 ); -PROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c ); -PROVIDE ( _global_impure_ptr = 0x3ffae0b0 ); -PROVIDE ( gmtime = 0x40059848 ); -PROVIDE ( gmtime_r = 0x40059868 ); -PROVIDE ( g_phyFuns_instance = 0x3ffae0c4 ); -PROVIDE ( gpio_init = 0x40009c20 ); -PROVIDE ( gpio_input_get = 0x40009b88 ); -PROVIDE ( gpio_input_get_high = 0x40009b9c ); -PROVIDE ( gpio_intr_ack = 0x40009dd4 ); -PROVIDE ( gpio_intr_ack_high = 0x40009e1c ); -PROVIDE ( gpio_intr_handler_register = 0x40009e6c ); -PROVIDE ( gpio_intr_pending = 0x40009cec ); -PROVIDE ( gpio_intr_pending_high = 0x40009cf8 ); -PROVIDE ( gpio_matrix_in = 0x40009edc ); -PROVIDE ( gpio_matrix_out = 0x40009f0c ); -PROVIDE ( gpio_output_set = 0x40009b24 ); -PROVIDE ( gpio_output_set_high = 0x40009b5c ); -PROVIDE ( gpio_pad_hold = 0x4000a734 ); -PROVIDE ( gpio_pad_pulldown = 0x4000a348 ); -PROVIDE ( gpio_pad_pullup = 0x4000a22c ); -PROVIDE ( gpio_pad_select_gpio = 0x40009fdc ); -PROVIDE ( gpio_pad_set_drv = 0x4000a11c ); -PROVIDE ( gpio_pad_unhold = 0x4000a484 ); -PROVIDE ( gpio_pending_mask = 0x3ffe0038 ); -PROVIDE ( gpio_pending_mask_high = 0x3ffe0044 ); -PROVIDE ( gpio_pin_intr_state_set = 0x40009d04 ); -PROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 ); -PROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c ); -PROVIDE ( gpio_register_get = 0x40009cbc ); -PROVIDE ( gpio_register_set = 0x40009bbc ); -PROVIDE ( __gtdf2 = 0x400636dc ); -PROVIDE ( __gtsf2 = 0x400633a0 ); -PROVIDE ( gTxMsg = 0x3ffe0050 ); -PROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 ); -PROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 ); -PROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c ); -PROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 ); -PROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 ); -PROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c ); -PROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 ); -PROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 ); -PROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 ); -PROVIDE ( hci_command_handler = 0x4004c928 ); -PROVIDE ( hci_env = 0x3ffb9350 ); -PROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c ); -PROVIDE ( hci_evt_desc_tab = 0x3ff9751c ); -PROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 ); -PROVIDE ( hci_fc_env = 0x3ffb9340 ); -PROVIDE ( hmac_md5 = 0x4005d264 ); -PROVIDE ( hmac_md5_vector = 0x4005d17c ); -PROVIDE ( hmac_sha1 = 0x40060acc ); -PROVIDE ( hmac_sha1_vector = 0x400609e4 ); -PROVIDE ( hmac_sha256 = 0x40060d58 ); -PROVIDE ( hmac_sha256_vector = 0x40060c84 ); -PROVIDE ( intr_matrix_set = 0x4000681c ); -PROVIDE ( iprintf = 0x40056978 ); -PROVIDE ( _iprintf_r = 0x40056944 ); -PROVIDE ( isalnum = 0x40000f04 ); -PROVIDE ( isalpha = 0x40000f18 ); -PROVIDE ( isascii = 0x4000c20c ); -PROVIDE ( _isatty_r = 0x40000ea0 ); -PROVIDE ( isblank = 0x40000f2c ); -PROVIDE ( iscanf = 0x40058760 ); -PROVIDE ( _iscanf_r = 0x4005879c ); -PROVIDE ( iscntrl = 0x40000f50 ); -PROVIDE ( isdigit = 0x40000f64 ); -PROVIDE ( isgraph = 0x40000f94 ); -PROVIDE ( islower = 0x40000f78 ); -PROVIDE ( isprint = 0x40000fa8 ); -PROVIDE ( ispunct = 0x40000fc0 ); -PROVIDE ( isspace = 0x40000fd4 ); -PROVIDE ( isupper = 0x40000fe8 ); -PROVIDE ( itoa = 0x400566b4 ); -PROVIDE ( __itoa = 0x40056678 ); -PROVIDE ( jd_decomp = 0x400613e8 ); -PROVIDE ( jd_prepare = 0x40060fa8 ); -PROVIDE ( ke_env = 0x3ffb93cc ); -PROVIDE ( _KernelExceptionVector = 0x40000300 ); -PROVIDE ( _kill_r = 0x4000bd10 ); -PROVIDE ( labs = 0x40056370 ); -PROVIDE ( lb_default_handler = 0x3ff982b8 ); -PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 ); -PROVIDE ( lb_env = 0x3ffb9424 ); -PROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c ); -PROVIDE ( lb_state = 0x3ffb94e8 ); -PROVIDE ( lc_default_handler = 0x3ff98648 ); -PROVIDE ( lc_default_state_tab_p_get = 0x4002f494 ); -PROVIDE ( lc_env = 0x3ffb94ec ); -PROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 ); -PROVIDE ( lc_state = 0x3ffb9508 ); -PROVIDE ( ld_acl_br_sizes = 0x3ff98a2a ); -PROVIDE ( ld_acl_br_types = 0x3ff98a36 ); -PROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 ); -PROVIDE ( ld_acl_edr_types = 0x3ff98a22 ); -PROVIDE ( ld_env = 0x3ffb9510 ); -PROVIDE ( ldiv = 0x40056378 ); -PROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c ); -PROVIDE ( ld_sched_params = 0x3ffb96c0 ); -PROVIDE ( ld_sync_train_channels = 0x3ff98a3c ); -PROVIDE ( __ledf2 = 0x40063704 ); -PROVIDE ( __lesf2 = 0x400633c0 ); -PROVIDE ( _xtensa_level2_from = 0x40000954 ); -PROVIDE ( _xtensa_level2_vector = 0x40000180 ); -PROVIDE ( _xtensa_level3_from = 0x40000a28 ); -PROVIDE ( _xtensa_level3_vector = 0x400001c0 ); -PROVIDE ( _xtensa_level4_from = 0x40000af8 ); -PROVIDE ( _xtensa_level4_vector = 0x40000200 ); -PROVIDE ( _xtensa_level5_from = 0x40000c68 ); -PROVIDE ( _xtensa_level5_vector = 0x40000240 ); -PROVIDE ( _LevelOneInterrupt = 0x40000835 ); -PROVIDE ( _link_r = 0x4000bc9c ); -PROVIDE ( llc_default_handler = 0x3ff98b3c ); -PROVIDE ( llc_default_state_tab_p_get = 0x40046058 ); -PROVIDE ( llc_env = 0x3ffb96d0 ); -PROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 ); -PROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 ); -PROVIDE ( llc_hci_command_handler = 0x40042360 ); -PROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 ); -PROVIDE ( llc_state = 0x3ffb96f8 ); -PROVIDE ( lldesc_build_chain = 0x4000a850 ); -PROVIDE ( lldesc_num2link = 0x4000a948 ); -PROVIDE ( lldesc_set_owner = 0x4000a974 ); -PROVIDE ( lld_evt_env = 0x3ffb9704 ); -PROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 ); -PROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 ); -PROVIDE ( LLM_AA_CT1 = 0x3ff98d8a ); -PROVIDE ( LLM_AA_CT2 = 0x3ff98d88 ); -PROVIDE ( llm_default_handler = 0x3ff98d80 ); -PROVIDE ( llm_default_state_tab_p_get = 0x4004e718 ); -PROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 ); -PROVIDE ( llm_le_env = 0x3ffb976c ); -PROVIDE ( llm_local_cmds = 0x3ff98d38 ); -PROVIDE ( llm_local_data_len_values = 0x3ff98d1c ); -PROVIDE ( llm_local_le_feats = 0x3ff98d30 ); -PROVIDE ( llm_local_le_states = 0x3ff98d28 ); -PROVIDE ( llm_state = 0x3ffb985c ); -PROVIDE ( lm_default_handler = 0x3ff990e0 ); -PROVIDE ( lm_default_state_tab_p_get = 0x40054268 ); -PROVIDE ( lm_env = 0x3ffb9860 ); -PROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c ); -PROVIDE ( lm_local_supp_feats = 0x3ff990ee ); -PROVIDE ( lm_n_page_tab = 0x3ff990e8 ); -PROVIDE ( lmp_desc_tab = 0x3ff96e6c ); -PROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c ); -PROVIDE ( lm_state = 0x3ffb9a1c ); -PROVIDE ( __locale_charset = 0x40059540 ); -PROVIDE ( __locale_cjk_lang = 0x40059558 ); -PROVIDE ( localeconv = 0x4005957c ); -PROVIDE ( _localeconv_r = 0x40059560 ); -PROVIDE ( __locale_mb_cur_max = 0x40059548 ); -PROVIDE ( __locale_msgcharset = 0x40059550 ); -PROVIDE ( localtime = 0x400595dc ); -PROVIDE ( localtime_r = 0x400595fc ); -PROVIDE ( _lock_acquire = 0x4000be14 ); -PROVIDE ( _lock_acquire_recursive = 0x4000be28 ); -PROVIDE ( _lock_close = 0x4000bdec ); -PROVIDE ( _lock_close_recursive = 0x4000be00 ); -PROVIDE ( _lock_init = 0x4000bdc4 ); -PROVIDE ( _lock_init_recursive = 0x4000bdd8 ); -PROVIDE ( _lock_release = 0x4000be64 ); -PROVIDE ( _lock_release_recursive = 0x4000be78 ); -PROVIDE ( _lock_try_acquire = 0x4000be3c ); -PROVIDE ( _lock_try_acquire_recursive = 0x4000be50 ); -PROVIDE ( longjmp = 0x400562cc ); -PROVIDE ( _lseek_r = 0x4000bd8c ); -PROVIDE ( __lshrdi3 = 0x4000c84c ); -PROVIDE ( __ltdf2 = 0x40063790 ); -PROVIDE ( __ltsf2 = 0x4006342c ); -PROVIDE ( malloc = 0x4000bea0 ); -PROVIDE ( _malloc_r = 0x4000bbb4 ); -PROVIDE ( maxSecretKey_256 = 0x3ff97448 ); -PROVIDE ( __mb_cur_max = 0x3ff96530 ); -PROVIDE ( MD5Final = 0x4005db1c ); -PROVIDE ( MD5Init = 0x4005da7c ); -PROVIDE ( MD5Update = 0x4005da9c ); -PROVIDE ( md5_vector = 0x4005db80 ); -PROVIDE ( memccpy = 0x4000c220 ); -PROVIDE ( memchr = 0x4000c244 ); -PROVIDE ( memcmp = 0x4000c260 ); -PROVIDE ( memcpy = 0x4000c2c8 ); -PROVIDE ( MemDwnLdStartMsgProc = 0x40008948 ); -PROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc ); -PROVIDE ( memmove = 0x4000c3c0 ); -PROVIDE ( MemPacketSendReqMsgProc = 0x40008978 ); -PROVIDE ( memrchr = 0x4000c400 ); -PROVIDE ( memset = 0x4000c44c ); -PROVIDE ( mktime = 0x4005a5e8 ); -PROVIDE ( mmu_init = 0x400095a4 ); -PROVIDE ( __moddi3 = 0x4000cd4c ); -PROVIDE ( __modsi3 = 0x4000c7c0 ); -PROVIDE ( __month_lengths = 0x3ff9609c ); -PROVIDE ( __muldc3 = 0x40063bf4 ); -PROVIDE ( __muldf3 = 0x4006358c ); -PROVIDE ( __muldi3 = 0x4000c9fc ); -PROVIDE ( __mulsc3 = 0x40063934 ); -PROVIDE ( __mulsf3 = 0x400632c8 ); -PROVIDE ( __mulsi3 = 0x4000c7b0 ); -PROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 ); -PROVIDE ( MultiplyBigHexModP256 = 0x400160b8 ); -PROVIDE ( MultiplyByU32ModP256 = 0x40015fdc ); -PROVIDE ( multofup = 0x4000ab8c ); -PROVIDE ( __mulvdi3 = 0x40002d78 ); -PROVIDE ( __mulvsi3 = 0x40002d60 ); -PROVIDE ( mz_adler32 = 0x4005edbc ); -PROVIDE ( mz_crc32 = 0x4005ee88 ); -PROVIDE ( mz_free = 0x4005eed4 ); -PROVIDE ( __nedf2 = 0x400636a8 ); -PROVIDE ( __negdf2 = 0x400634a0 ); -PROVIDE ( __negdi2 = 0x4000ca14 ); -PROVIDE ( __negsf2 = 0x400020c0 ); -PROVIDE ( __negvdi2 = 0x40002e98 ); -PROVIDE ( __negvsi2 = 0x40002e78 ); -PROVIDE ( __nesf2 = 0x40063374 ); -PROVIDE ( _NMIExceptionVector = 0x400002c0 ); -PROVIDE ( notEqual256 = 0x40015b04 ); -PROVIDE ( __nsau_data = 0x3ff96544 ); -PROVIDE ( one_bits = 0x3ff971f8 ); -PROVIDE ( open = 0x4000178c ); -PROVIDE ( _open_r = 0x4000bd54 ); -PROVIDE ( __paritysi2 = 0x40002f3c ); -PROVIDE ( pbkdf2_sha1 = 0x40060ba4 ); -PROVIDE ( phy_get_romfuncs = 0x40004100 ); -PROVIDE ( __popcountdi2 = 0x40002ef8 ); -PROVIDE ( __popcountsi2 = 0x40002ed0 ); -PROVIDE ( __popcount_tab = 0x3ff96544 ); -PROVIDE ( __powidf2 = 0x400638d4 ); -PROVIDE ( __powisf2 = 0x4006389c ); -PROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 ); -PROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c ); -PROVIDE ( printf = 0x40056978 ); -PROVIDE ( _printf_common = 0x40057338 ); -PROVIDE ( _printf_float = 0x4000befc ); -PROVIDE ( _printf_i = 0x40057404 ); -PROVIDE ( _printf_r = 0x40056944 ); -PROVIDE ( qsort = 0x40056424 ); -PROVIDE ( _raise_r = 0x4000bc70 ); -PROVIDE ( rand = 0x40001058 ); -PROVIDE ( rand_r = 0x400010d4 ); -PROVIDE ( r_btdm_option_data = 0x3ffae6e0 ); -PROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 ); -PROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 ); -PROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 ); -PROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 ); -PROVIDE ( r_bt_util_buf_init = 0x400100e4 ); -PROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 ); -PROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec ); -PROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 ); -PROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 ); -PROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 ); -PROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c ); -PROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec ); -PROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 ); -PROVIDE ( rc4_skip = 0x40060928 ); -PROVIDE ( r_co_bdaddr_compare = 0x40014324 ); -PROVIDE ( r_co_bytes_to_string = 0x400142e4 ); -PROVIDE ( r_co_list_check_size_available = 0x400142c4 ); -PROVIDE ( r_co_list_extract = 0x4001404c ); -PROVIDE ( r_co_list_extract_after = 0x40014118 ); -PROVIDE ( r_co_list_find = 0x4001419c ); -PROVIDE ( r_co_list_init = 0x40013f14 ); -PROVIDE ( r_co_list_insert_after = 0x40014254 ); -PROVIDE ( r_co_list_insert_before = 0x40014200 ); -PROVIDE ( r_co_list_merge = 0x400141bc ); -PROVIDE ( r_co_list_pool_init = 0x40013f30 ); -PROVIDE ( r_co_list_pop_front = 0x40014028 ); -PROVIDE ( r_co_list_push_back = 0x40013fb8 ); -PROVIDE ( r_co_list_push_front = 0x40013ff4 ); -PROVIDE ( r_co_list_size = 0x400142ac ); -PROVIDE ( r_co_nb_good_channels = 0x40014360 ); -PROVIDE ( r_co_slot_to_duration = 0x40014348 ); -PROVIDE ( RcvMsg = 0x4000954c ); -PROVIDE ( r_dbg_init = 0x40014394 ); -PROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 ); -PROVIDE ( r_dbg_swdiag_init = 0x40014470 ); -PROVIDE ( r_dbg_swdiag_read = 0x400144a4 ); -PROVIDE ( r_dbg_swdiag_write = 0x400144d0 ); -PROVIDE ( r_E1 = 0x400108e8 ); -PROVIDE ( r_E21 = 0x40010968 ); -PROVIDE ( r_E22 = 0x400109b4 ); -PROVIDE ( r_E3 = 0x40010a58 ); -PROVIDE ( r_ea_alarm_clear = 0x40015ab4 ); -PROVIDE ( r_ea_alarm_set = 0x40015a10 ); -PROVIDE ( read = 0x400017dc ); -PROVIDE ( _read_r = 0x4000bda8 ); -PROVIDE ( r_ea_elt_cancel = 0x400150d0 ); -PROVIDE ( r_ea_elt_create = 0x40015264 ); -PROVIDE ( r_ea_elt_insert = 0x400152a8 ); -PROVIDE ( r_ea_elt_remove = 0x400154f0 ); -PROVIDE ( r_ea_finetimer_isr = 0x400155d4 ); -PROVIDE ( r_ea_init = 0x40015228 ); -PROVIDE ( r_ea_interval_create = 0x4001555c ); -PROVIDE ( r_ea_interval_delete = 0x400155a8 ); -PROVIDE ( r_ea_interval_duration_req = 0x4001597c ); -PROVIDE ( r_ea_interval_insert = 0x4001557c ); -PROVIDE ( r_ea_interval_remove = 0x40015590 ); -PROVIDE ( realloc = 0x4000becc ); -PROVIDE ( _realloc_r = 0x4000bbe0 ); -PROVIDE ( r_ea_offset_req = 0x40015748 ); -PROVIDE ( r_ea_sleep_check = 0x40015928 ); -PROVIDE ( r_ea_sw_isr = 0x40015724 ); -PROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 ); -PROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 ); -PROVIDE ( r_ecc_abort_key256_generation = 0x40017070 ); -PROVIDE ( r_ecc_generate_key256 = 0x40016e00 ); -PROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 ); -PROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 ); -PROVIDE ( r_ecc_get_debug_Keys = 0x40017224 ); -PROVIDE ( r_ecc_init = 0x40016dbc ); -PROVIDE ( RecvBuff = 0x3ffe009c ); -PROVIDE ( recv_packet = 0x40009424 ); -PROVIDE ( r_em_buf_init = 0x4001729c ); -PROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 ); -PROVIDE ( r_em_buf_rx_free = 0x400173c4 ); -PROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 ); -PROVIDE ( r_em_buf_tx_free = 0x4001741c ); -PROVIDE ( _rename_r = 0x4000bc28 ); -PROVIDE ( _ResetHandler = 0x40000450 ); -PROVIDE ( _ResetVector = 0x40000400 ); -PROVIDE ( r_F1_256 = 0x400133e4 ); -PROVIDE ( r_F2_256 = 0x40013568 ); -PROVIDE ( r_F3_256 = 0x40013664 ); -PROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c ); -PROVIDE ( r_G_256 = 0x40013470 ); -PROVIDE ( r_H3 = 0x40013760 ); -PROVIDE ( r_H4 = 0x40013830 ); -PROVIDE ( r_h4tl_init = 0x40017878 ); -PROVIDE ( r_h4tl_start = 0x40017924 ); -PROVIDE ( r_h4tl_stop = 0x40017934 ); -PROVIDE ( r_h4tl_write = 0x400178d0 ); -PROVIDE ( r_H5 = 0x400138dc ); -PROVIDE ( r_hashConcat = 0x40013a38 ); -PROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c ); -PROVIDE ( r_hci_acl_tx_data_received = 0x40019654 ); -PROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 ); -PROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac ); -PROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c ); -PROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 ); -PROVIDE ( r_hci_cmd_received = 0x400192f8 ); -PROVIDE ( r_hci_evt_filter_add = 0x40018a64 ); -PROVIDE ( r_hci_evt_mask_set = 0x400189e4 ); -PROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 ); -PROVIDE ( r_hci_fc_acl_en = 0x400179d8 ); -PROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c ); -PROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 ); -PROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 ); -PROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c ); -PROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 ); -PROVIDE ( r_hci_fc_init = 0x40017974 ); -PROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 ); -PROVIDE ( r_hci_fc_sync_en = 0x40017a30 ); -PROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 ); -PROVIDE ( r_hci_init = 0x40018538 ); -PROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 ); -PROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 ); -PROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 ); -PROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 ); -PROVIDE ( r_hci_reset = 0x4001856c ); -PROVIDE ( r_hci_send_2_host = 0x400185bc ); -PROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 ); -PROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 ); -PROVIDE ( r_hci_tl_init = 0x40019290 ); -PROVIDE ( r_hci_tl_send = 0x40019228 ); -PROVIDE ( r_hci_util_pack = 0x40019874 ); -PROVIDE ( r_hci_util_unpack = 0x40019998 ); -PROVIDE ( r_hci_voice_settings_get = 0x40018bdc ); -PROVIDE ( r_hci_voice_settings_set = 0x40018be8 ); -PROVIDE ( r_HMAC = 0x40013968 ); -PROVIDE ( r_import_rf_phy_func = 0x3ffb8354 ); -PROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 ); -PROVIDE ( r_ip_funcs = 0x3ffae710 ); -PROVIDE ( r_ip_funcs_p = 0x3ffae70c ); -PROVIDE ( r_ke_check_malloc = 0x40019de0 ); -PROVIDE ( r_ke_event_callback_set = 0x40019ba8 ); -PROVIDE ( r_ke_event_clear = 0x40019c2c ); -PROVIDE ( r_ke_event_flush = 0x40019ccc ); -PROVIDE ( r_ke_event_get = 0x40019c78 ); -PROVIDE ( r_ke_event_get_all = 0x40019cc0 ); -PROVIDE ( r_ke_event_init = 0x40019b90 ); -PROVIDE ( r_ke_event_schedule = 0x40019cdc ); -PROVIDE ( r_ke_event_set = 0x40019be0 ); -PROVIDE ( r_ke_flush = 0x4001a374 ); -PROVIDE ( r_ke_free = 0x4001a014 ); -PROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 ); -PROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 ); -PROVIDE ( r_ke_init = 0x4001a318 ); -PROVIDE ( r_ke_is_free = 0x4001a184 ); -PROVIDE ( r_ke_malloc = 0x40019eb4 ); -PROVIDE ( r_ke_mem_init = 0x40019d3c ); -PROVIDE ( r_ke_mem_is_empty = 0x40019d8c ); -PROVIDE ( r_ke_msg_alloc = 0x4001a1e0 ); -PROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 ); -PROVIDE ( r_ke_msg_discard = 0x4001a850 ); -PROVIDE ( r_ke_msg_forward = 0x4001a290 ); -PROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac ); -PROVIDE ( r_ke_msg_free = 0x4001a2cc ); -PROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 ); -PROVIDE ( r_ke_msg_save = 0x4001a858 ); -PROVIDE ( r_ke_msg_send = 0x4001a234 ); -PROVIDE ( r_ke_msg_send_basic = 0x4001a26c ); -PROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec ); -PROVIDE ( r_ke_queue_extract = 0x40055fd0 ); -PROVIDE ( r_ke_queue_insert = 0x40056020 ); -PROVIDE ( r_ke_sleep_check = 0x4001a3d8 ); -PROVIDE ( r_ke_state_get = 0x4001a7d8 ); -PROVIDE ( r_ke_state_set = 0x4001a6fc ); -PROVIDE ( r_ke_stats_get = 0x4001a3f0 ); -PROVIDE ( r_ke_task_check = 0x4001a8a4 ); -PROVIDE ( r_ke_task_create = 0x4001a674 ); -PROVIDE ( r_ke_task_delete = 0x4001a6c0 ); -PROVIDE ( r_ke_task_init = 0x4001a650 ); -PROVIDE ( r_ke_task_msg_flush = 0x4001a860 ); -PROVIDE ( r_ke_timer_active = 0x4001ac08 ); -PROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 ); -PROVIDE ( r_ke_timer_clear = 0x4001ab90 ); -PROVIDE ( r_ke_timer_init = 0x4001aa9c ); -PROVIDE ( r_ke_timer_set = 0x4001aac0 ); -PROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 ); -PROVIDE ( r_KPrimC = 0x40010ad4 ); -PROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 ); -PROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 ); -PROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 ); -PROVIDE ( r_lb_init = 0x4001acd4 ); -PROVIDE ( r_lb_mst_key = 0x4001afc0 ); -PROVIDE ( r_lb_mst_key_cmp = 0x4001af74 ); -PROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 ); -PROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 ); -PROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c ); -PROVIDE ( r_lb_reset = 0x4001ad38 ); -PROVIDE ( r_lb_send_lmp = 0x4001adbc ); -PROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c ); -PROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 ); -PROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 ); -PROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 ); -PROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c ); -PROVIDE ( r_lc_afh_set = 0x4001cc74 ); -PROVIDE ( r_lc_afh_start = 0x4001d240 ); -PROVIDE ( r_lc_auth_cmp = 0x4001cd54 ); -PROVIDE ( r_lc_calc_link_key = 0x4001ce7c ); -PROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 ); -PROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc ); -PROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac ); -PROVIDE ( r_lc_chk_to = 0x4001d2a8 ); -PROVIDE ( r_lc_cmd_stat_send = 0x4001c914 ); -PROVIDE ( r_lc_comb_key_svr = 0x4001d30c ); -PROVIDE ( r_lc_con_cmp = 0x4001d44c ); -PROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc ); -PROVIDE ( r_lc_conn_seq_done = 0x40021334 ); -PROVIDE ( r_lc_detach = 0x4002037c ); -PROVIDE ( r_lc_dhkey = 0x4001d564 ); -PROVIDE ( r_lc_enc_cmp = 0x4001d8bc ); -PROVIDE ( r_lc_enc_key_refresh = 0x4001d720 ); -PROVIDE ( r_lc_end_chk_colli = 0x4001d858 ); -PROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 ); -PROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 ); -PROVIDE ( r_lc_epr_change_lk = 0x4001db38 ); -PROVIDE ( r_lc_epr_cmp = 0x4001da88 ); -PROVIDE ( r_lc_epr_resp = 0x4001e0b4 ); -PROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 ); -PROVIDE ( r_lc_ext_feat = 0x40020d6c ); -PROVIDE ( r_lc_feat = 0x40020984 ); -PROVIDE ( r_lc_hl_connect = 0x400209e8 ); -PROVIDE ( r_lc_init = 0x4001c948 ); -PROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 ); -PROVIDE ( r_lc_initiator_epr = 0x4001e064 ); -PROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 ); -PROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 ); -PROVIDE ( r_lc_key_exch_end = 0x4001e140 ); -PROVIDE ( r_lc_legacy_pair = 0x4001e1c0 ); -PROVIDE ( r_lc_local_switch = 0x4001e22c ); -PROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 ); -PROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 ); -PROVIDE ( r_lc_loc_auth = 0x40020ecc ); -PROVIDE ( r_lc_locepr_lkref = 0x4001d648 ); -PROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 ); -PROVIDE ( r_lc_loc_sniff = 0x40020a6c ); -PROVIDE ( r_lc_max_slot_mgt = 0x4001e410 ); -PROVIDE ( r_lc_mst_key = 0x4001e7c0 ); -PROVIDE ( r_lc_mst_qos_done = 0x4001ea80 ); -PROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 ); -PROVIDE ( r_lc_mutual_auth_end = 0x4001e670 ); -PROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 ); -PROVIDE ( r_lc_packet_type = 0x40021038 ); -PROVIDE ( r_lc_pair = 0x40020ddc ); -PROVIDE ( r_lc_pairing_cont = 0x4001eafc ); -PROVIDE ( r_lc_passkey_comm = 0x4001ed20 ); -PROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 ); -PROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec ); -PROVIDE ( r_lc_ptt = 0x4001ee2c ); -PROVIDE ( r_lc_ptt_cmp = 0x4001eeec ); -PROVIDE ( r_lc_qos_setup = 0x4001ef50 ); -PROVIDE ( r_lc_rd_rem_name = 0x4001efd0 ); -PROVIDE ( r_lc_release = 0x4001f8a8 ); -PROVIDE ( r_lc_rem_enc = 0x4001f124 ); -PROVIDE ( r_lc_rem_name_cont = 0x4001f290 ); -PROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 ); -PROVIDE ( r_lc_rem_sniff = 0x40020ca4 ); -PROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 ); -PROVIDE ( r_lc_rem_switch = 0x4001f070 ); -PROVIDE ( r_lc_rem_trans_mode = 0x4001f314 ); -PROVIDE ( r_lc_rem_unsniff = 0x400207a0 ); -PROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c ); -PROVIDE ( r_lc_reset = 0x4001c99c ); -PROVIDE ( r_lc_resp_auth = 0x4001f518 ); -PROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 ); -PROVIDE ( r_lc_resp_num_comp = 0x40020074 ); -PROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 ); -PROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c ); -PROVIDE ( r_lc_resp_pair = 0x400208a4 ); -PROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 ); -PROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c ); -PROVIDE ( r_lc_restart_enc = 0x4001f8ec ); -PROVIDE ( r_lc_restart_enc_cont = 0x4001f940 ); -PROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 ); -PROVIDE ( r_lc_restore_to = 0x4001f9e0 ); -PROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 ); -PROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 ); -PROVIDE ( r_lc_rsw_done = 0x4001db94 ); -PROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 ); -PROVIDE ( r_lc_sco_detach = 0x40021e40 ); -PROVIDE ( r_lc_sco_host_accept = 0x40022118 ); -PROVIDE ( r_lc_sco_host_reject = 0x400222b8 ); -PROVIDE ( r_lc_sco_host_request = 0x40021f4c ); -PROVIDE ( r_lc_sco_host_request_disc = 0x4002235c ); -PROVIDE ( r_lc_sco_init = 0x40021dc8 ); -PROVIDE ( r_lc_sco_peer_accept = 0x40022780 ); -PROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 ); -PROVIDE ( r_lc_sco_peer_reject = 0x40022824 ); -PROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c ); -PROVIDE ( r_lc_sco_peer_request = 0x4002240c ); -PROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec ); -PROVIDE ( r_lc_sco_release = 0x40021eec ); -PROVIDE ( r_lc_sco_reset = 0x40021dfc ); -PROVIDE ( r_lc_sco_timeout = 0x40022bd4 ); -PROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec ); -PROVIDE ( r_lc_semi_key_cmp = 0x40020294 ); -PROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c ); -PROVIDE ( r_lc_send_enc_mode = 0x40020220 ); -PROVIDE ( r_lc_send_lmp = 0x4001c1a8 ); -PROVIDE ( r_lc_send_pdu_acc = 0x4001c21c ); -PROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 ); -PROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 ); -PROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 ); -PROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c ); -PROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 ); -PROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 ); -PROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 ); -PROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 ); -PROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 ); -PROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 ); -PROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 ); -PROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec ); -PROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 ); -PROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 ); -PROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c ); -PROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c ); -PROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 ); -PROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec ); -PROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c ); -PROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 ); -PROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 ); -PROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 ); -PROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 ); -PROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 ); -PROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c ); -PROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 ); -PROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 ); -PROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 ); -PROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 ); -PROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 ); -PROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 ); -PROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 ); -PROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 ); -PROVIDE ( r_lc_send_pdu_sres = 0x4001c548 ); -PROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc ); -PROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 ); -PROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 ); -PROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 ); -PROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc ); -PROVIDE ( r_lc_sniff_init = 0x40022cac ); -PROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 ); -PROVIDE ( r_lc_sniff_reset = 0x40022cc8 ); -PROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 ); -PROVIDE ( r_lc_sniff_sub_mode = 0x400204fc ); -PROVIDE ( r_lc_sp_end = 0x400213a8 ); -PROVIDE ( r_lc_sp_fail = 0x40020470 ); -PROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc ); -PROVIDE ( r_lc_ssr_nego = 0x4002125c ); -PROVIDE ( r_lc_start = 0x4001ca28 ); -PROVIDE ( r_lc_start_enc = 0x4001fb28 ); -PROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c ); -PROVIDE ( r_lc_start_key_exch = 0x4001fe10 ); -PROVIDE ( r_lc_start_lmp_to = 0x4001fae8 ); -PROVIDE ( r_lc_start_oob = 0x4001fffc ); -PROVIDE ( r_lc_start_passkey = 0x4001feac ); -PROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 ); -PROVIDE ( r_lc_stop_afh_report = 0x40020184 ); -PROVIDE ( r_lc_stop_enc = 0x40020110 ); -PROVIDE ( r_lc_switch_cmp = 0x40020448 ); -PROVIDE ( r_lc_unit_key_svr = 0x400206d8 ); -PROVIDE ( r_lc_unsniff = 0x40020c50 ); -PROVIDE ( r_lc_unsniff_cmp = 0x40020810 ); -PROVIDE ( r_lc_unsniff_cont = 0x40020750 ); -PROVIDE ( r_lc_upd_to = 0x4002065c ); -PROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 ); -PROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac ); -PROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 ); -PROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c ); -PROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 ); -PROVIDE ( r_lc_version = 0x40020a30 ); -PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 ); -PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 ); -PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 ); -PROVIDE ( r_ld_acl_afh_set = 0x40036b60 ); -PROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 ); -PROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 ); -PROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 ); -PROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 ); -PROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 ); -PROVIDE ( r_ld_acl_clk_set = 0x40036950 ); -PROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 ); -PROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 ); -PROVIDE ( r_ld_acl_data_flush = 0x400357bc ); -PROVIDE ( r_ld_acl_data_tx = 0x4003544c ); -PROVIDE ( r_ld_acl_edr_set = 0x4003678c ); -PROVIDE ( r_ld_acl_enc_key_load = 0x40036404 ); -PROVIDE ( r_ld_acl_flow_off = 0x40035400 ); -PROVIDE ( r_ld_acl_flow_on = 0x4003541c ); -PROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c ); -PROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 ); -PROVIDE ( r_ld_acl_init = 0x40034d08 ); -PROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 ); -PROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 ); -PROVIDE ( r_ld_acl_lsto_get = 0x400366b4 ); -PROVIDE ( r_ld_acl_lsto_set = 0x400366f8 ); -PROVIDE ( r_ld_acl_reset = 0x40034d24 ); -PROVIDE ( r_ld_acl_role_get = 0x40036b30 ); -PROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 ); -PROVIDE ( r_ld_acl_rsw_req = 0x40035e74 ); -PROVIDE ( r_ld_acl_rx_enc = 0x40036344 ); -PROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 ); -PROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 ); -PROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c ); -PROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 ); -PROVIDE ( r_ld_acl_sniff = 0x4003617c ); -PROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 ); -PROVIDE ( r_ld_acl_ssr_set = 0x40036274 ); -PROVIDE ( r_ld_acl_start = 0x40034ddc ); -PROVIDE ( r_ld_acl_stop = 0x4003532c ); -PROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 ); -PROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c ); -PROVIDE ( r_ld_acl_t_poll_get = 0x40036024 ); -PROVIDE ( r_ld_acl_t_poll_set = 0x40036068 ); -PROVIDE ( r_ld_acl_tx_enc = 0x400362f8 ); -PROVIDE ( r_ld_acl_unsniff = 0x400361e0 ); -PROVIDE ( r_ld_active_check = 0x4003cac4 ); -PROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec ); -PROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c ); -PROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 ); -PROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc ); -PROVIDE ( r_ld_bcst_acl_start = 0x4003882c ); -PROVIDE ( r_ld_bcst_afh_update = 0x40038f3c ); -PROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c ); -PROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 ); -PROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 ); -PROVIDE ( r_ld_bd_addr_get = 0x4003ca20 ); -PROVIDE ( r_ld_channel_assess = 0x4003c184 ); -PROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 ); -PROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 ); -PROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 ); -PROVIDE ( r_ld_csb_rx_init = 0x40039690 ); -PROVIDE ( r_ld_csb_rx_reset = 0x4003969c ); -PROVIDE ( r_ld_csb_rx_start = 0x4003972c ); -PROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 ); -PROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc ); -PROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c ); -PROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 ); -PROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 ); -PROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 ); -PROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 ); -PROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 ); -PROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 ); -PROVIDE ( r_ld_fm_frame_isr = 0x4003a82c ); -PROVIDE ( r_ld_fm_init = 0x4003a760 ); -PROVIDE ( r_ld_fm_prog_check = 0x4003ab28 ); -PROVIDE ( r_ld_fm_prog_disable = 0x4003a984 ); -PROVIDE ( r_ld_fm_prog_enable = 0x4003a944 ); -PROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 ); -PROVIDE ( r_ld_fm_reset = 0x4003a794 ); -PROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 ); -PROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 ); -PROVIDE ( r_ld_init = 0x4003c294 ); -PROVIDE ( r_ld_inq_init = 0x4003b15c ); -PROVIDE ( r_ld_inq_reset = 0x4003b168 ); -PROVIDE ( r_ld_inq_start = 0x4003b1f0 ); -PROVIDE ( r_ld_inq_stop = 0x4003b4f0 ); -PROVIDE ( r_ld_iscan_eir_get = 0x4003c118 ); -PROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 ); -PROVIDE ( r_ld_iscan_init = 0x4003b9f0 ); -PROVIDE ( r_ld_iscan_reset = 0x4003ba14 ); -PROVIDE ( r_ld_iscan_restart = 0x4003ba44 ); -PROVIDE ( r_ld_iscan_start = 0x4003bb28 ); -PROVIDE ( r_ld_iscan_stop = 0x4003bf1c ); -PROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 ); -PROVIDE ( r_ld_page_init = 0x4003d808 ); -PROVIDE ( r_ld_page_reset = 0x4003d814 ); -PROVIDE ( r_ld_page_start = 0x4003d848 ); -PROVIDE ( r_ld_page_stop = 0x4003da54 ); -PROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 ); -PROVIDE ( r_ld_pca_init = 0x4003deb4 ); -PROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac ); -PROVIDE ( r_ld_pca_local_config = 0x4003df6c ); -PROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 ); -PROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 ); -PROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 ); -PROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 ); -PROVIDE ( r_ld_pca_reset = 0x4003df0c ); -PROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 ); -PROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 ); -PROVIDE ( r_ld_pscan_init = 0x4003f474 ); -PROVIDE ( r_ld_pscan_reset = 0x4003f498 ); -PROVIDE ( r_ld_pscan_restart = 0x4003f4b8 ); -PROVIDE ( r_ld_pscan_start = 0x4003f514 ); -PROVIDE ( r_ld_pscan_stop = 0x4003f618 ); -PROVIDE ( r_ld_read_clock = 0x4003c9e4 ); -PROVIDE ( r_ld_reset = 0x4003c714 ); -PROVIDE ( r_ld_sched_acl_add = 0x4003f978 ); -PROVIDE ( r_ld_sched_acl_remove = 0x4003f99c ); -PROVIDE ( r_ld_sched_compute = 0x4003f6f8 ); -PROVIDE ( r_ld_sched_init = 0x4003f7ac ); -PROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 ); -PROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 ); -PROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 ); -PROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 ); -PROVIDE ( r_ld_sched_page_add = 0x4003f910 ); -PROVIDE ( r_ld_sched_page_remove = 0x4003f938 ); -PROVIDE ( r_ld_sched_pscan_add = 0x4003f828 ); -PROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 ); -PROVIDE ( r_ld_sched_reset = 0x4003f7d4 ); -PROVIDE ( r_ld_sched_sco_add = 0x4003fa4c ); -PROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c ); -PROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 ); -PROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c ); -PROVIDE ( r_ld_sched_sscan_add = 0x4003f868 ); -PROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 ); -PROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 ); -PROVIDE ( r_ld_sco_data_tx = 0x40037ee8 ); -PROVIDE ( r_ld_sco_start = 0x40037110 ); -PROVIDE ( r_ld_sco_stop = 0x40037c40 ); -PROVIDE ( r_ld_sco_update = 0x40037a74 ); -PROVIDE ( r_ld_sscan_activated = 0x4004031c ); -PROVIDE ( r_ld_sscan_init = 0x400402f0 ); -PROVIDE ( r_ld_sscan_reset = 0x400402fc ); -PROVIDE ( r_ld_sscan_start = 0x40040384 ); -PROVIDE ( r_ld_strain_init = 0x400409f4 ); -PROVIDE ( r_ld_strain_reset = 0x40040a00 ); -PROVIDE ( r_ld_strain_start = 0x40040a8c ); -PROVIDE ( r_ld_strain_stop = 0x40040df0 ); -PROVIDE ( r_ld_timing_accuracy_get = 0x4003caac ); -PROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c ); -PROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 ); -PROVIDE ( r_ld_util_bch_create = 0x40040fcc ); -PROVIDE ( r_ld_util_fhs_pk = 0x400411c8 ); -PROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 ); -PROVIDE ( r_ld_util_stp_pk = 0x400413f4 ); -PROVIDE ( r_ld_util_stp_unpk = 0x40041324 ); -PROVIDE ( r_ld_version_get = 0x4003ca6c ); -PROVIDE ( r_ld_wlcoex_set = 0x4003caf8 ); -PROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 ); -PROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c ); -PROVIDE ( r_llc_ch_assess_local = 0x40041494 ); -PROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 ); -PROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 ); -PROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac ); -PROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 ); -PROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c ); -PROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 ); -PROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c ); -PROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 ); -PROVIDE ( r_llc_con_update_complete_send = 0x40044d68 ); -PROVIDE ( r_llc_con_update_finished = 0x4004518c ); -PROVIDE ( r_llc_con_update_ind = 0x40045038 ); -PROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 ); -PROVIDE ( r_llc_end_evt_defer = 0x40046330 ); -PROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c ); -PROVIDE ( r_llc_init = 0x40044778 ); -PROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 ); -PROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 ); -PROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc ); -PROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 ); -PROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 ); -PROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 ); -PROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 ); -PROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 ); -PROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 ); -PROVIDE ( r_llc_llcp_get_autorize = 0x4004475c ); -PROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 ); -PROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac ); -PROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 ); -PROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 ); -PROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c ); -PROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 ); -PROVIDE ( r_llc_llcp_recv_handler = 0x40044678 ); -PROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c ); -PROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c ); -PROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 ); -PROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 ); -PROVIDE ( r_llc_llcp_tester_send = 0x400445e4 ); -PROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 ); -PROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c ); -PROVIDE ( r_llc_lsto_con_update = 0x40045098 ); -PROVIDE ( r_llc_ltk_req_send = 0x40044dc0 ); -PROVIDE ( r_llc_map_update_finished = 0x40045260 ); -PROVIDE ( r_llc_map_update_ind = 0x400450f0 ); -PROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc ); -PROVIDE ( r_llc_pdu_defer = 0x40046528 ); -PROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac ); -PROVIDE ( r_llc_reset = 0x400447b8 ); -PROVIDE ( r_llc_start = 0x400447f4 ); -PROVIDE ( r_llc_stop = 0x400449ac ); -PROVIDE ( r_llc_util_bw_mgt = 0x4004629c ); -PROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 ); -PROVIDE ( r_llc_util_dicon_procedure = 0x40046130 ); -PROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 ); -PROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 ); -PROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 ); -PROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 ); -PROVIDE ( r_llc_util_update_channel_map = 0x400461ac ); -PROVIDE ( r_llc_version_rd_event_send = 0x40044e60 ); -PROVIDE ( r_lld_adv_start = 0x40048b38 ); -PROVIDE ( r_lld_adv_stop = 0x40048ea0 ); -PROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 ); -PROVIDE ( r_lld_con_param_req = 0x40049f0c ); -PROVIDE ( r_lld_con_param_rsp = 0x40049e00 ); -PROVIDE ( r_lld_con_start = 0x400491f8 ); -PROVIDE ( r_lld_con_stop = 0x40049fdc ); -PROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc ); -PROVIDE ( r_lld_con_update_ind = 0x4004a30c ); -PROVIDE ( r_lld_con_update_req = 0x40049b60 ); -PROVIDE ( r_lld_core_reset = 0x40048a9c ); -PROVIDE ( r_lld_crypt_isr = 0x4004a324 ); -PROVIDE ( r_lld_evt_adv_create = 0x400481f4 ); -PROVIDE ( r_lld_evt_canceled = 0x400485c8 ); -PROVIDE ( r_lld_evt_channel_next = 0x40046aac ); -PROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc ); -PROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 ); -PROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c ); -PROVIDE ( r_lld_evt_drift_compute = 0x40047670 ); -PROVIDE ( r_lld_evt_elt_delete = 0x40047538 ); -PROVIDE ( r_lld_evt_elt_insert = 0x400474c8 ); -PROVIDE ( r_lld_evt_end = 0x400483e8 ); -PROVIDE ( r_lld_evt_end_isr = 0x4004862c ); -PROVIDE ( r_lld_evt_init = 0x40046b3c ); -PROVIDE ( r_lld_evt_init_evt = 0x40046cd0 ); -PROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 ); -PROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 ); -PROVIDE ( r_lld_evt_prevent_stop = 0x40047adc ); -PROVIDE ( r_lld_evt_restart = 0x40046d50 ); -PROVIDE ( r_lld_evt_rx = 0x40048578 ); -PROVIDE ( r_lld_evt_rx_isr = 0x40048678 ); -PROVIDE ( r_lld_evt_scan_create = 0x40047ae8 ); -PROVIDE ( r_lld_evt_schedule = 0x40047908 ); -PROVIDE ( r_lld_evt_schedule_next = 0x400477dc ); -PROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 ); -PROVIDE ( r_lld_evt_slave_update = 0x40048138 ); -PROVIDE ( r_lld_evt_update_create = 0x40047cd8 ); -PROVIDE ( r_lld_get_mode = 0x40049ff8 ); -PROVIDE ( r_lld_init = 0x4004873c ); -PROVIDE ( r_lld_move_to_master = 0x400499e0 ); -PROVIDE ( r_lld_move_to_slave = 0x4004a024 ); -PROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 ); -PROVIDE ( r_lld_pdu_check = 0x4004ac34 ); -PROVIDE ( r_lld_pdu_data_send = 0x4004b018 ); -PROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc ); -PROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 ); -PROVIDE ( r_lld_pdu_send_packet = 0x4004b774 ); -PROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 ); -PROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 ); -PROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 ); -PROVIDE ( r_lld_pdu_tx_push = 0x4004b080 ); -PROVIDE ( r_lld_ral_renew_req = 0x4004a73c ); -/**************************************************************************** - * boards/xtensa/elf32-core/scripts/esp32_rom.ld - ****************************************************************************/ - -PROVIDE ( r_lld_scan_start = 0x40048ee0 ); -PROVIDE ( r_lld_scan_stop = 0x40049190 ); -PROVIDE ( r_lld_test_mode_rx = 0x4004a540 ); -PROVIDE ( r_lld_test_mode_tx = 0x4004a350 ); -PROVIDE ( r_lld_test_stop = 0x4004a710 ); -PROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc ); -PROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c ); -PROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 ); -PROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 ); -PROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 ); -PROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 ); -PROVIDE ( r_lld_util_flush_list = 0x4004bbd8 ); -PROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 ); -PROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac ); -PROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 ); -PROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 ); -PROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 ); -PROVIDE ( r_lld_util_instant_get = 0x4004b890 ); -PROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc ); -PROVIDE ( r_lld_util_priority_set = 0x4004bd10 ); -PROVIDE ( r_lld_util_priority_update = 0x4004bd78 ); -PROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 ); -PROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 ); -PROVIDE ( r_lld_wlcoex_set = 0x4004bd98 ); -PROVIDE ( r_llm_ble_ready = 0x4004cc34 ); -PROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 ); -PROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 ); -PROVIDE ( r_llm_con_req_ind = 0x4004cc54 ); -PROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 ); -PROVIDE ( r_llm_create_con = 0x4004de78 ); -PROVIDE ( r_llm_encryption_done = 0x4004dff8 ); -PROVIDE ( r_llm_encryption_start = 0x4004e128 ); -PROVIDE ( r_llm_end_evt_defer = 0x4004eb6c ); -PROVIDE ( r_llm_init = 0x4004c9f8 ); -PROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 ); -PROVIDE ( r_llm_pdu_defer = 0x4004ec48 ); -PROVIDE ( r_llm_ral_clear = 0x4004e1fc ); -PROVIDE ( r_llm_ral_dev_add = 0x4004e23c ); -PROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc ); -PROVIDE ( r_llm_ral_get_rpa = 0x4004e400 ); -PROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 ); -PROVIDE ( r_llm_ral_update = 0x4004e4f8 ); -PROVIDE ( r_llm_set_adv_data = 0x4004d960 ); -PROVIDE ( r_llm_set_adv_en = 0x4004d7ec ); -PROVIDE ( r_llm_set_adv_param = 0x4004d5f4 ); -PROVIDE ( r_llm_set_scan_en = 0x4004db64 ); -PROVIDE ( r_llm_set_scan_param = 0x4004dac8 ); -PROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 ); -PROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 ); -PROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc ); -PROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc ); -PROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 ); -PROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 ); -PROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 ); -PROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 ); -PROVIDE ( r_llm_util_bl_add = 0x4004e9ac ); -PROVIDE ( r_llm_util_bl_check = 0x4004e930 ); -PROVIDE ( r_llm_util_bl_rem = 0x4004ea70 ); -PROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 ); -PROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 ); -PROVIDE ( r_llm_util_check_map_validity = 0x4004e800 ); -PROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 ); -PROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 ); -PROVIDE ( r_llm_util_set_public_addr = 0x4004e89c ); -PROVIDE ( r_llm_wl_clr = 0x4004dc54 ); -PROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 ); -PROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 ); -PROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc ); -PROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 ); -PROVIDE ( r_lm_acl_disc = 0x4004f148 ); -PROVIDE ( r_LM_AddSniff = 0x40022d20 ); -PROVIDE ( r_lm_add_sync = 0x40051358 ); -PROVIDE ( r_lm_afh_activate_timer = 0x4004f444 ); -PROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 ); -PROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 ); -PROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c ); -PROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 ); -PROVIDE ( r_lm_check_active_sync = 0x40051334 ); -PROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c ); -PROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 ); -PROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c ); -PROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 ); -PROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 ); -PROVIDE ( r_LM_ComputePacketType = 0x4002f554 ); -PROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac ); -PROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 ); -PROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 ); -PROVIDE ( r_lm_dhkey_calc_init = 0x40013234 ); -PROVIDE ( r_lm_dhkey_compare = 0x400132d8 ); -PROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec ); -PROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 ); -PROVIDE ( r_lm_f1 = 0x40012bb8 ); -PROVIDE ( r_lm_f2 = 0x40012cfc ); -PROVIDE ( r_lm_f3 = 0x40013050 ); -PROVIDE ( r_lm_g = 0x40012f90 ); -PROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c ); -PROVIDE ( r_lm_get_auth_en = 0x4004f1ac ); -PROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c ); -PROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 ); -PROVIDE ( r_LM_GetFeature = 0x4002f924 ); -PROVIDE ( r_LM_GetLinkTimeout = 0x400233ec ); -PROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 ); -PROVIDE ( r_lm_get_loopback_mode = 0x4004f248 ); -PROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c ); -PROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 ); -PROVIDE ( r_LM_GetMasterKey = 0x4001b260 ); -PROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 ); -PROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 ); -PROVIDE ( r_lm_get_nb_acl = 0x4004ef9c ); -PROVIDE ( r_lm_get_nb_sync_link = 0x4005179c ); -PROVIDE ( r_lm_get_nonce = 0x400131c4 ); -PROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 ); -PROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 ); -PROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 ); -PROVIDE ( r_LM_GetPINType = 0x4004f1e8 ); -PROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 ); -PROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 ); -PROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 ); -PROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 ); -PROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 ); -PROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 ); -PROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c ); -PROVIDE ( r_lm_get_sp_en = 0x4004f1c0 ); -PROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 ); -PROVIDE ( r_lm_get_synchdl = 0x4005175c ); -PROVIDE ( r_lm_get_sync_param = 0x400503b4 ); -PROVIDE ( r_lm_init = 0x4004ed34 ); -PROVIDE ( r_lm_init_sync = 0x400512d8 ); -PROVIDE ( r_lm_is_acl_con = 0x4004f47c ); -PROVIDE ( r_lm_is_acl_con_role = 0x4004f49c ); -PROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 ); -PROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 ); -PROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 ); -PROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 ); -PROVIDE ( r_lm_look_for_sync = 0x40051774 ); -PROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c ); -PROVIDE ( r_lm_lt_addr_free = 0x4004ef74 ); -PROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 ); -PROVIDE ( r_LM_MakeCof = 0x4002f84c ); -PROVIDE ( r_LM_MakeRandVec = 0x400112d8 ); -PROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 ); -PROVIDE ( r_LM_MaxSlot = 0x4002f694 ); -PROVIDE ( r_lm_modif_sync = 0x40051578 ); -PROVIDE ( r_lm_n_is_zero = 0x40012170 ); -PROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 ); -PROVIDE ( r_lm_oob_f1 = 0x40012e54 ); -PROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 ); -PROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 ); -PROVIDE ( r_lmp_pack = 0x4001135c ); -PROVIDE ( r_lmp_unpack = 0x4001149c ); -PROVIDE ( r_lm_read_features = 0x4004f0d8 ); -PROVIDE ( r_LM_RemoveSniff = 0x40023124 ); -PROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 ); -PROVIDE ( r_lm_remove_sync = 0x400517c8 ); -PROVIDE ( r_lm_reset_sync = 0x40051304 ); -PROVIDE ( r_lm_role_switch_finished = 0x4004f028 ); -PROVIDE ( r_lm_role_switch_start = 0x4004efe0 ); -PROVIDE ( r_lm_sco_nego_end = 0x40051828 ); -PROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 ); -PROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 ); -PROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc ); -PROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 ); -PROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 ); -PROVIDE ( r_lm_sp_n_one = 0x400123a4 ); -PROVIDE ( r_lm_sp_p192_add = 0x40012828 ); -PROVIDE ( r_lm_sp_p192_dbl = 0x4001268c ); -PROVIDE ( r_lm_sp_p192_invert = 0x40012b6c ); -PROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 ); -PROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 ); -PROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 ); -PROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 ); -PROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 ); -PROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 ); -PROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 ); -PROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 ); -PROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 ); -PROVIDE ( r_modules_funcs = 0x3ffafd6c ); -PROVIDE ( r_modules_funcs_p = 0x3ffafd68 ); -PROVIDE ( r_nvds_del = 0x400544c4 ); -PROVIDE ( r_nvds_get = 0x40054488 ); -PROVIDE ( r_nvds_init = 0x40054410 ); -PROVIDE ( r_nvds_lock = 0x400544fc ); -PROVIDE ( r_nvds_put = 0x40054534 ); -PROVIDE ( rom_abs_temp = 0x400054f0 ); -PROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c ); -PROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac ); -PROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 ); -PROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 ); -PROVIDE ( rom_bb_wdg_test_en = 0x40003b70 ); -PROVIDE ( rom_cbw2040_cfg = 0x400040b0 ); -PROVIDE ( rom_check_noise_floor = 0x40003c78 ); -PROVIDE ( rom_chip_i2c_readReg = 0x40004110 ); -PROVIDE ( rom_chip_i2c_writeReg = 0x40004168 ); -PROVIDE ( rom_chip_v7_bt_init = 0x40004d8c ); -PROVIDE ( rom_chip_v7_rx_init = 0x40004cec ); -PROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 ); -PROVIDE ( rom_chip_v7_tx_init = 0x40004d18 ); -PROVIDE ( rom_clk_force_on_vit = 0x40003710 ); -PROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 ); -PROVIDE ( rom_dc_iq_est = 0x400055c8 ); -PROVIDE ( rom_disable_agc = 0x40002fa4 ); -PROVIDE ( rom_enable_agc = 0x40002fcc ); -PROVIDE ( rom_en_pwdet = 0x4000506c ); -PROVIDE ( rom_gen_rx_gain_table = 0x40003e3c ); -PROVIDE ( rom_get_data_sat = 0x4000312c ); -PROVIDE ( rom_get_fm_sar_dout = 0x40005204 ); -PROVIDE ( rom_get_power_db = 0x40005fc8 ); -PROVIDE ( rom_get_pwctrl_correct = 0x400065d4 ); -PROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc ); -PROVIDE ( rom_get_rf_gain_qdb = 0x40006290 ); -PROVIDE ( rom_get_sar_dout = 0x40006564 ); -PROVIDE ( rom_i2c_readreg = 0x40004148 ); -PROVIDE ( rom_i2c_readreg_Mask = 0x400041c0 ); -PROVIDE ( rom_i2c_writereg = 0x400041a4 ); -PROVIDE ( rom_i2c_writereg_Mask = 0x400041fc ); -PROVIDE ( rom_index_to_txbbgain = 0x40004df8 ); -PROVIDE ( rom_iq_est_disable = 0x40005590 ); -PROVIDE ( rom_iq_est_enable = 0x40005514 ); -PROVIDE ( rom_linear_to_db = 0x40005f64 ); -PROVIDE ( rom_loopback_mode_en = 0x400030f8 ); -PROVIDE ( rom_main = 0x400076c4 ); -PROVIDE ( rom_meas_tone_pwr_db = 0x40006004 ); -PROVIDE ( rom_mhz2ieee = 0x4000404c ); -PROVIDE ( rom_noise_floor_auto_set = 0x40003bdc ); -PROVIDE ( rom_pbus_debugmode = 0x40004458 ); -PROVIDE ( rom_pbus_force_mode = 0x40004270 ); -PROVIDE ( rom_pbus_force_test = 0x400043c0 ); -PROVIDE ( rom_pbus_rd = 0x40004414 ); -PROVIDE ( rom_pbus_rd_addr = 0x40004334 ); -PROVIDE ( rom_pbus_rd_shift = 0x40004374 ); -PROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 ); -PROVIDE ( rom_pbus_set_dco = 0x40004638 ); -PROVIDE ( rom_pbus_set_rxgain = 0x40004480 ); -PROVIDE ( rom_pbus_workmode = 0x4000446c ); -PROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 ); -PROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c ); -PROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 ); -PROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 ); -PROVIDE ( rom_phy_disable_agc = 0x40002f6c ); -PROVIDE ( rom_phy_disable_cca = 0x40003000 ); -PROVIDE ( rom_phy_enable_agc = 0x40002f88 ); -PROVIDE ( rom_phy_enable_cca = 0x4000302c ); -PROVIDE ( rom_phy_freq_correct = 0x40004b44 ); -PROVIDE ( rom_phyFuns = 0x3ffae0c0 ); -PROVIDE ( rom_phy_get_noisefloor = 0x40003c2c ); -PROVIDE ( rom_phy_get_vdd33 = 0x4000642c ); -PROVIDE ( rom_pow_usr = 0x40003044 ); -PROVIDE ( rom_read_sar_dout = 0x400051c0 ); -PROVIDE ( rom_restart_cal = 0x400046e0 ); -PROVIDE ( rom_rfcal_pwrctrl = 0x40006058 ); -PROVIDE ( rom_rfcal_rxiq = 0x40005b4c ); -PROVIDE ( rom_rfcal_txcap = 0x40005dec ); -PROVIDE ( rom_rfpll_reset = 0x40004680 ); -PROVIDE ( rom_rfpll_set_freq = 0x400047f8 ); -PROVIDE ( rom_rtc_mem_backup = 0x40003db4 ); -PROVIDE ( rom_rtc_mem_recovery = 0x40003df4 ); -PROVIDE ( rom_rx_gain_force = 0x4000351c ); -PROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 ); -PROVIDE ( rom_rxiq_get_mis = 0x400058e4 ); -PROVIDE ( rom_rxiq_set_reg = 0x40005a00 ); -PROVIDE ( rom_set_cal_rxdc = 0x400030b8 ); -PROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 ); -PROVIDE ( rom_set_channel_freq = 0x40004880 ); -PROVIDE ( rom_set_loopback_gain = 0x40003060 ); -PROVIDE ( rom_set_noise_floor = 0x40003d48 ); -PROVIDE ( rom_set_pbus_mem = 0x400031a4 ); -PROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 ); -PROVIDE ( rom_set_rxclk_en = 0x40003594 ); -PROVIDE ( rom_set_txcap_reg = 0x40005d50 ); -PROVIDE ( rom_set_txclk_en = 0x40003564 ); -PROVIDE ( rom_spur_coef_cfg = 0x40003ac8 ); -PROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 ); -PROVIDE ( rom_start_tx_tone = 0x400036b4 ); -PROVIDE ( rom_start_tx_tone_step = 0x400035d0 ); -PROVIDE ( rom_stop_tx_tone = 0x40003f98 ); -PROVIDE ( _rom_store = 0x4000d66c ); -PROVIDE ( _rom_store_table = 0x4000d4f8 ); -PROVIDE ( rom_target_power_add_backoff = 0x40006268 ); -PROVIDE ( rom_tx_atten_set_interp = 0x400061cc ); -PROVIDE ( rom_txbbgain_to_index = 0x40004dc0 ); -PROVIDE ( rom_txcal_work_mode = 0x4000510c ); -PROVIDE ( rom_txdc_cal_init = 0x40004e10 ); -PROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 ); -PROVIDE ( rom_txiq_cover = 0x4000538c ); -PROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc ); -PROVIDE ( rom_txiq_set_reg = 0x40005154 ); -PROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c ); -PROVIDE ( rom_txtone_linear_pwr = 0x40005290 ); -PROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 ); -PROVIDE ( rom_write_gain_mem = 0x4000348c ); -PROVIDE ( rom_write_rfpll_sdm = 0x40004740 ); -PROVIDE ( roundup2 = 0x4000ab7c ); -PROVIDE ( r_plf_funcs_p = 0x3ffb8360 ); -PROVIDE ( r_rf_rw_bt_init = 0x40054868 ); -PROVIDE ( r_rf_rw_init = 0x40054b0c ); -PROVIDE ( r_rf_rw_le_init = 0x400549d0 ); -PROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c ); -PROVIDE ( r_rwble_init = 0x40054bf4 ); -PROVIDE ( r_rwble_isr = 0x40054e08 ); -PROVIDE ( r_rwble_reset = 0x40054ce8 ); -PROVIDE ( r_rwble_sleep_check = 0x40054d78 ); -PROVIDE ( r_rwble_version = 0x40054dac ); -PROVIDE ( r_rwbt_init = 0x40055160 ); -PROVIDE ( r_rwbt_isr = 0x40055248 ); -PROVIDE ( r_rwbt_reset = 0x400551bc ); -PROVIDE ( r_rwbt_sleep_check = 0x4005577c ); -PROVIDE ( r_rwbt_sleep_enter = 0x400557a4 ); -PROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc ); -PROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc ); -PROVIDE ( r_rwbt_version = 0x4005520c ); -PROVIDE ( r_rwip_assert_err = 0x40055f88 ); -PROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc ); -PROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c ); -PROVIDE ( r_rwip_init = 0x4005595c ); -PROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 ); -PROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 ); -PROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 ); -PROVIDE ( r_rwip_reset = 0x40055ab8 ); -PROVIDE ( r_rwip_schedule = 0x40055b38 ); -PROVIDE ( r_rwip_sleep = 0x40055b5c ); -PROVIDE ( r_rwip_sleep_enable = 0x40055f30 ); -PROVIDE ( r_rwip_version = 0x40055b20 ); -PROVIDE ( r_rwip_wakeup = 0x40055dc4 ); -PROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c ); -PROVIDE ( r_rwip_wakeup_end = 0x40055e18 ); -PROVIDE ( r_rwip_wlcoex_set = 0x40055f60 ); -PROVIDE ( r_SHA_256 = 0x40013a90 ); -PROVIDE ( rtc_boot_control = 0x4000821c ); -PROVIDE ( rtc_get_reset_reason = 0x400081d4 ); -PROVIDE ( rtc_get_wakeup_cause = 0x400081f4 ); -PROVIDE ( rtc_select_apb_bridge = 0x40008288 ); -PROVIDE ( rwip_coex_cfg = 0x3ff9914c ); -PROVIDE ( rwip_priority = 0x3ff99159 ); -PROVIDE ( rwip_rf = 0x3ffbdb28 ); -PROVIDE ( rwip_rf_p_get = 0x400558f4 ); -PROVIDE ( r_XorKey = 0x400112c0 ); -PROVIDE ( sbrk = 0x400017f4 ); -PROVIDE ( _sbrk_r = 0x4000bce4 ); -PROVIDE ( scanf = 0x40058760 ); -PROVIDE ( _scanf_chars = 0x40058384 ); -PROVIDE ( _scanf_float = 0x4000bf18 ); -PROVIDE ( _scanf_i = 0x4005845c ); -PROVIDE ( _scanf_r = 0x4005879c ); -PROVIDE ( __sccl = 0x4000c498 ); -PROVIDE ( __sclose = 0x400011b8 ); -PROVIDE ( SelectSpiFunction = 0x40061f84 ); -PROVIDE ( SelectSpiQIO = 0x40061ddc ); -PROVIDE ( SendMsg = 0x40009384 ); -PROVIDE ( send_packet = 0x40009340 ); -PROVIDE ( __seofread = 0x40001148 ); -PROVIDE ( setjmp = 0x40056268 ); -PROVIDE ( setlocale = 0x40059568 ); -PROVIDE ( _setlocale_r = 0x4005950c ); -PROVIDE ( set_rtc_memory_crc = 0x40008208 ); -PROVIDE ( SetSpiDrvs = 0x40061e78 ); -PROVIDE ( __sf_fake_stderr = 0x3ff96458 ); -PROVIDE ( __sf_fake_stdin = 0x3ff96498 ); -PROVIDE ( __sf_fake_stdout = 0x3ff96478 ); -PROVIDE ( __sflush_r = 0x400591e0 ); -PROVIDE ( __sfmoreglue = 0x40001dc8 ); -PROVIDE ( __sfp = 0x40001e90 ); -PROVIDE ( __sfp_lock_acquire = 0x40001e08 ); -PROVIDE ( __sfp_lock_release = 0x40001e14 ); -PROVIDE ( __sfputs_r = 0x40057790 ); -PROVIDE ( __sfvwrite_r = 0x4005893c ); -PROVIDE ( sha1_prf = 0x40060ae8 ); -PROVIDE ( sha1_vector = 0x40060b64 ); -PROVIDE ( sha256_prf = 0x40060d70 ); -PROVIDE ( sha256_vector = 0x40060e08 ); -PROVIDE ( sha_blk_bits = 0x3ff99290 ); -PROVIDE ( sha_blk_bits_bytes = 0x3ff99288 ); -PROVIDE ( sha_blk_hash_bytes = 0x3ff9928c ); -PROVIDE ( sig_matrix = 0x3ffae293 ); -PROVIDE ( __sinit = 0x40001e38 ); -PROVIDE ( __sinit_lock_acquire = 0x40001e20 ); -PROVIDE ( __sinit_lock_release = 0x40001e2c ); -PROVIDE ( sip_after_tx_complete = 0x4000b358 ); -PROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c ); -PROVIDE ( sip_get_ptr = 0x4000b34c ); -PROVIDE ( sip_get_state = 0x4000ae2c ); -PROVIDE ( sip_init_attach = 0x4000ae58 ); -PROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 ); -PROVIDE ( sip_install_rx_data_cb = 0x4000ae20 ); -PROVIDE ( sip_is_active = 0x4000b3c0 ); -PROVIDE ( sip_post_init = 0x4000aed8 ); -PROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc ); -PROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c ); -PROVIDE ( siprintf = 0x40056c08 ); -PROVIDE ( _siprintf_r = 0x40056bbc ); -PROVIDE ( sip_send = 0x4000af54 ); -PROVIDE ( sip_to_host_chain_append = 0x4000aef8 ); -PROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 ); -PROVIDE ( siscanf = 0x400587d0 ); -PROVIDE ( _siscanf_r = 0x40058830 ); -PROVIDE ( slc_add_credits = 0x4000baf4 ); -PROVIDE ( slc_enable = 0x4000b64c ); -PROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 ); -PROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 ); -PROVIDE ( slc_has_pkt_to_host = 0x4000b5fc ); -PROVIDE ( slc_init_attach = 0x4000b918 ); -PROVIDE ( slc_init_credit = 0x4000badc ); -PROVIDE ( slc_reattach = 0x4000b62c ); -PROVIDE ( slc_send_to_host_chain = 0x4000b6a0 ); -PROVIDE ( slc_set_host_io_max_window = 0x4000b89c ); -PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 ); -PROVIDE ( __smakebuf_r = 0x40059108 ); -PROVIDE ( sniprintf = 0x40056b4c ); -PROVIDE ( _sniprintf_r = 0x40056ae4 ); -PROVIDE ( snprintf = 0x40056b4c ); -PROVIDE ( _snprintf_r = 0x40056ae4 ); -PROVIDE ( software_reset = 0x4000824c ); -PROVIDE ( software_reset_cpu = 0x40008264 ); -PROVIDE ( specialModP256 = 0x4001600c ); -PROVIDE ( spi_cache_sram_init = 0x400626e4 ); -PROVIDE ( SPIClkConfig = 0x40062bc8 ); -PROVIDE ( SPI_Common_Command = 0x4006246c ); -PROVIDE ( spi_dummy_len_fix = 0x40061d90 ); -PROVIDE ( SPI_Encrypt_Write = 0x40062e78 ); -PROVIDE ( SPIEraseArea = 0x400631ac ); -PROVIDE ( SPIEraseBlock = 0x40062c4c ); -PROVIDE ( SPIEraseChip = 0x40062c14 ); -PROVIDE ( SPIEraseSector = 0x40062ccc ); -PROVIDE ( spi_flash_attach = 0x40062a6c ); -PROVIDE ( SPILock = 0x400628f0 ); -PROVIDE ( SPIMasterReadModeCnfig = 0x40062b64 ); -PROVIDE ( spi_modes = 0x3ff99270 ); -PROVIDE ( SPIParamCfg = 0x40063238 ); -PROVIDE ( SPI_Prepare_Encrypt_Data = 0x40062e1c ); -PROVIDE ( SPIRead = 0x40062ed8 ); -PROVIDE ( SPIReadModeCnfig = 0x40062944 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_read_status = 0x4006226c ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_read_status_high = 0x40062448 ); -PROVIDE ( SPIUnlock = 0x400628b0 ); -PROVIDE ( SPI_user_command_read = 0x400621b0 ); -PROVIDE ( spi_w25q16 = 0x3ffae270 ); -PROVIDE ( SPIWrite = 0x40062d50 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_write_enable = 0x40062320 ); -PROVIDE ( SPI_Write_Encrypt_Disable = 0x40062e60 ); -PROVIDE ( SPI_Write_Encrypt_Enable = 0x40062df4 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_write_status = 0x400622f0 ); -PROVIDE ( sprintf = 0x40056c08 ); -PROVIDE ( _sprintf_r = 0x40056bbc ); -PROVIDE ( __sprint_r = 0x400577e4 ); -PROVIDE ( srand = 0x40001004 ); -PROVIDE ( __sread = 0x40001118 ); -PROVIDE ( __srefill_r = 0x400593d4 ); -PROVIDE ( sscanf = 0x400587d0 ); -PROVIDE ( _sscanf_r = 0x40058830 ); -PROVIDE ( __sseek = 0x40001184 ); -PROVIDE ( __ssprint_r = 0x40056ff8 ); -PROVIDE ( __ssputs_r = 0x40056f2c ); -PROVIDE ( __ssrefill_r = 0x40057fec ); -PROVIDE ( __ssvfiscanf_r = 0x4005802c ); -PROVIDE ( __ssvfscanf_r = 0x4005802c ); -PROVIDE ( __stack = 0x3ffe3f20 ); -PROVIDE ( __stack_app = 0x3ffe7e30 ); -PROVIDE ( _stack_sentry = 0x3ffe1320 ); -PROVIDE ( _stack_sentry_app = 0x3ffe5230 ); -PROVIDE ( _start = 0x40000704 ); -PROVIDE ( start_tb_console = 0x4005a980 ); -PROVIDE ( _stat_r = 0x4000bcb4 ); -PROVIDE ( _stext = 0x40000560 ); -PROVIDE ( strcasecmp = 0x400011cc ); -PROVIDE ( strcasestr = 0x40001210 ); -PROVIDE ( strcat = 0x4000c518 ); -PROVIDE ( strchr = 0x4000c53c ); -PROVIDE ( strcmp = 0x40001274 ); -PROVIDE ( strcoll = 0x40001398 ); -PROVIDE ( strcpy = 0x400013ac ); -PROVIDE ( strcspn = 0x4000c558 ); -PROVIDE ( strdup = 0x4000143c ); -PROVIDE ( _strdup_r = 0x40001450 ); -PROVIDE ( strftime = 0x40059ab4 ); -PROVIDE ( strlcat = 0x40001470 ); -PROVIDE ( strlcpy = 0x4000c584 ); -PROVIDE ( strlen = 0x400014c0 ); -PROVIDE ( strlwr = 0x40001524 ); -PROVIDE ( strncasecmp = 0x40001550 ); -PROVIDE ( strncat = 0x4000c5c4 ); -PROVIDE ( strncmp = 0x4000c5f4 ); -PROVIDE ( strncpy = 0x400015d4 ); -PROVIDE ( strndup = 0x400016b0 ); -PROVIDE ( _strndup_r = 0x400016c4 ); -PROVIDE ( strnlen = 0x4000c628 ); -PROVIDE ( strrchr = 0x40001708 ); -PROVIDE ( strsep = 0x40001734 ); -PROVIDE ( strspn = 0x4000c648 ); -PROVIDE ( strstr = 0x4000c674 ); -PROVIDE ( __strtok_r = 0x4000c6a8 ); -PROVIDE ( strtok_r = 0x4000c70c ); -PROVIDE ( strtol = 0x4005681c ); -PROVIDE ( _strtol_r = 0x40056714 ); -PROVIDE ( strtoul = 0x4005692c ); -PROVIDE ( _strtoul_r = 0x40056834 ); -PROVIDE ( strupr = 0x4000174c ); -PROVIDE ( __subdf3 = 0x400026e4 ); -PROVIDE ( __submore = 0x40058f3c ); -PROVIDE ( __subsf3 = 0x400021d0 ); -PROVIDE ( SubtractBigHex256 = 0x40015bcc ); -PROVIDE ( SubtractBigHexMod256 = 0x40015e8c ); -PROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c ); -PROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 ); -PROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 ); -PROVIDE ( __subvdi3 = 0x40002d20 ); -PROVIDE ( __subvsi3 = 0x40002cf8 ); -PROVIDE ( _sungetc_r = 0x40057f6c ); -PROVIDE ( _svfiprintf_r = 0x40057100 ); -PROVIDE ( __svfiscanf_r = 0x40057b08 ); -PROVIDE ( _svfprintf_r = 0x40057100 ); -PROVIDE ( __svfscanf = 0x40057f04 ); -PROVIDE ( __svfscanf_r = 0x40057b08 ); -PROVIDE ( __swbuf = 0x40058cb4 ); -PROVIDE ( __swbuf_r = 0x40058bec ); -PROVIDE ( __swrite = 0x40001150 ); -PROVIDE ( __swsetup_r = 0x40058cc8 ); -PROVIDE ( sw_to_hw = 0x3ffb8d40 ); -PROVIDE ( _SyscallException = 0x400007cf ); -PROVIDE ( syscall_table_ptr_app = 0x3ffae020 ); -PROVIDE ( syscall_table_ptr_pro = 0x3ffae024 ); -PROVIDE ( _system_r = 0x4000bc10 ); -PROVIDE ( tdefl_compress = 0x400600bc ); -PROVIDE ( tdefl_compress_buffer = 0x400607f4 ); -PROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 ); -PROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 ); -PROVIDE ( tdefl_get_adler32 = 0x400608d8 ); -PROVIDE ( tdefl_get_prev_return_status = 0x400608d0 ); -PROVIDE ( tdefl_init = 0x40060810 ); -PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c ); -PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 ); -PROVIDE ( time = 0x40001844 ); -PROVIDE ( __time_load_locale = 0x4000183c ); -PROVIDE ( times = 0x40001808 ); -PROVIDE ( _times_r = 0x4000bc40 ); -PROVIDE ( _timezone = 0x3ffae0a0 ); -PROVIDE ( tinfl_decompress = 0x4005ef30 ); -PROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 ); -PROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 ); -PROVIDE ( toascii = 0x4000c720 ); -PROVIDE ( tolower = 0x40001868 ); -PROVIDE ( toupper = 0x40001884 ); -PROVIDE ( __truncdfsf2 = 0x40002b90 ); -PROVIDE ( __tzcalc_limits = 0x400018a0 ); -PROVIDE ( __tz_lock = 0x40001a04 ); -PROVIDE ( _tzname = 0x3ffae030 ); -PROVIDE ( tzset = 0x40001a1c ); -PROVIDE ( _tzset_r = 0x40001a28 ); -PROVIDE ( __tz_unlock = 0x40001a10 ); -PROVIDE ( uartAttach = 0x40008fd0 ); -PROVIDE ( uart_baudrate_detect = 0x40009034 ); -PROVIDE ( uart_buff_switch = 0x400093c0 ); -PROVIDE ( UartConnCheck = 0x40008738 ); -PROVIDE ( UartConnectProc = 0x40008a04 ); -PROVIDE ( UartDev = 0x3ffe019c ); -PROVIDE ( uart_div_modify = 0x400090cc ); -PROVIDE ( UartDwnLdProc = 0x40008ce8 ); -PROVIDE ( UartGetCmdLn = 0x40009564 ); -PROVIDE ( Uart_Init = 0x40009120 ); -PROVIDE ( UartRegReadProc = 0x40008a58 ); -PROVIDE ( UartRegWriteProc = 0x40008a14 ); -PROVIDE ( uart_rx_intr_handler = 0x40008f4c ); -PROVIDE ( uart_rx_one_char = 0x400092d0 ); -PROVIDE ( uart_rx_one_char_block = 0x400092a4 ); -PROVIDE ( uart_rx_readbuff = 0x40009394 ); -PROVIDE ( UartRxString = 0x400092fc ); -PROVIDE ( UartSetBaudProc = 0x40008aac ); -PROVIDE ( UartSpiAttachProc = 0x40008a6c ); -PROVIDE ( UartSpiReadProc = 0x40008a80 ); -PROVIDE ( uart_tx_flush = 0x40009258 ); -PROVIDE ( uart_tx_one_char = 0x40009200 ); -PROVIDE ( uart_tx_one_char2 = 0x4000922c ); -PROVIDE ( uart_tx_switch = 0x40009028 ); -PROVIDE ( uart_tx_wait_idle = 0x40009278 ); -PROVIDE ( __ucmpdi2 = 0x40063840 ); -PROVIDE ( __udivdi3 = 0x4000cff8 ); -PROVIDE ( __udivmoddi4 = 0x40064ab0 ); -PROVIDE ( __udivsi3 = 0x4000c7c8 ); -PROVIDE ( __udiv_w_sdiv = 0x40064aa8 ); -PROVIDE ( __umoddi3 = 0x4000d280 ); -PROVIDE ( __umodsi3 = 0x4000c7d0 ); -PROVIDE ( __umulsidi3 = 0x4000c7d8 ); -PROVIDE ( ungetc = 0x400590f4 ); -PROVIDE ( _ungetc_r = 0x40058fa0 ); -PROVIDE ( _unlink_r = 0x4000bc84 ); -PROVIDE ( __unorddf2 = 0x400637f4 ); -PROVIDE ( __unordsf2 = 0x40063478 ); -PROVIDE ( user_code_start = 0x3ffe0400 ); -PROVIDE ( _UserExceptionVector = 0x40000340 ); -PROVIDE ( utoa = 0x40056258 ); -PROVIDE ( __utoa = 0x400561f0 ); -PROVIDE ( vasiprintf = 0x40056eb8 ); -PROVIDE ( _vasiprintf_r = 0x40056e80 ); -PROVIDE ( vasniprintf = 0x40056e58 ); -PROVIDE ( _vasniprintf_r = 0x40056df8 ); -PROVIDE ( vasnprintf = 0x40056e58 ); -PROVIDE ( _vasnprintf_r = 0x40056df8 ); -PROVIDE ( vasprintf = 0x40056eb8 ); -PROVIDE ( _vasprintf_r = 0x40056e80 ); -PROVIDE ( VerifyFlashMd5Proc = 0x40008c44 ); -PROVIDE ( veryBigHexP256 = 0x3ff9736c ); -PROVIDE ( vfiprintf = 0x40057ae8 ); -PROVIDE ( _vfiprintf_r = 0x40057850 ); -PROVIDE ( vfiscanf = 0x40057eb8 ); -PROVIDE ( _vfiscanf_r = 0x40057f24 ); -PROVIDE ( vfprintf = 0x40057ae8 ); -PROVIDE ( _vfprintf_r = 0x40057850 ); -PROVIDE ( vfscanf = 0x40057eb8 ); -PROVIDE ( _vfscanf_r = 0x40057f24 ); -PROVIDE ( viprintf = 0x400569b4 ); -PROVIDE ( _viprintf_r = 0x400569e4 ); -PROVIDE ( viscanf = 0x40058698 ); -PROVIDE ( _viscanf_r = 0x400586c8 ); -PROVIDE ( vprintf = 0x400569b4 ); -PROVIDE ( _vprintf_r = 0x400569e4 ); -PROVIDE ( vscanf = 0x40058698 ); -PROVIDE ( _vscanf_r = 0x400586c8 ); -PROVIDE ( vsiprintf = 0x40056ac4 ); -PROVIDE ( _vsiprintf_r = 0x40056a90 ); -PROVIDE ( vsiscanf = 0x40058740 ); -PROVIDE ( _vsiscanf_r = 0x400586f8 ); -PROVIDE ( vsniprintf = 0x40056a68 ); -PROVIDE ( _vsniprintf_r = 0x40056a14 ); -PROVIDE ( vsnprintf = 0x40056a68 ); -PROVIDE ( _vsnprintf_r = 0x40056a14 ); -PROVIDE ( vsprintf = 0x40056ac4 ); -PROVIDE ( _vsprintf_r = 0x40056a90 ); -PROVIDE ( vsscanf = 0x40058740 ); -PROVIDE ( _vsscanf_r = 0x400586f8 ); -PROVIDE ( wcrtomb = 0x40058920 ); -PROVIDE ( _wcrtomb_r = 0x400588d8 ); -PROVIDE ( __wctomb = 0x3ff96540 ); -PROVIDE ( _wctomb_r = 0x40058f14 ); -PROVIDE ( _WindowOverflow12 = 0x40000100 ); -PROVIDE ( _WindowOverflow4 = 0x40000000 ); -PROVIDE ( _WindowOverflow8 = 0x40000080 ); -PROVIDE ( _WindowUnderflow12 = 0x40000140 ); -PROVIDE ( _WindowUnderflow4 = 0x40000040 ); -PROVIDE ( _WindowUnderflow8 = 0x400000c0 ); -PROVIDE ( write = 0x4000181c ); -PROVIDE ( _write_r = 0x4000bd70 ); -PROVIDE ( xthal_bcopy = 0x4000c098 ); -PROVIDE ( xthal_copy123 = 0x4000c124 ); -PROVIDE ( xthal_get_ccompare = 0x4000c078 ); -PROVIDE ( xthal_get_ccount = 0x4000c050 ); -PROVIDE ( xthal_get_interrupt = 0x4000c1e4 ); -PROVIDE ( xthal_get_intread = 0x4000c1e4 ); -PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 ); -PROVIDE ( xthal_memcpy = 0x4000c0bc ); -PROVIDE ( xthal_set_ccompare = 0x4000c058 ); -PROVIDE ( xthal_set_intclear = 0x4000c1ec ); -PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 ); -PROVIDE ( _xtos_alloca_handler = 0x40000010 ); -PROVIDE ( _xtos_cause3_handler = 0x40000dd8 ); -PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 ); -PROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 ); -PROVIDE ( _xtos_enabled = 0x3ffe0650 ); -PROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 ); -PROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 ); -PROVIDE ( _xtos_interrupt_table = 0x3ffe0658 ); -PROVIDE ( _xtos_ints_off = 0x4000bfac ); -PROVIDE ( _xtos_ints_on = 0x4000bf88 ); -PROVIDE ( _xtos_intstruct = 0x3ffe0650 ); -PROVIDE ( _xtos_l1int_handler = 0x40000814 ); -PROVIDE ( _xtos_p_none = 0x4000bfd4 ); -PROVIDE ( _xtos_restore_intlevel = 0x40000928 ); -PROVIDE ( _xtos_return_from_exc = 0x4000c034 ); -PROVIDE ( _xtos_set_exception_handler = 0x4000074c ); -PROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 ); -PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 ); -PROVIDE ( _xtos_set_intlevel = 0x4000bfdc ); -PROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 ); -PROVIDE ( _xtos_set_vpri = 0x40000934 ); -PROVIDE ( _xtos_syscall_handler = 0x40000790 ); -PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); -PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); -PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); -PROVIDE ( g_rom_flashchip = 0x3ffae270 ); -PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 ); -PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 ); -PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 ); -PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 ); -PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c ); - -PROVIDE ( esp_rom_printf = ets_printf ); -PROVIDE ( esp_rom_delay_us = ets_delay_us ); diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/gnu-elf.ld b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/gnu-elf.ld deleted file mode 100644 index 5a0c67948c6..00000000000 --- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/gnu-elf.ld +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/xtensa/esp32/esp32-ethernet-kit/scripts/gnu-elf.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -SECTIONS -{ - .text 0x00000000 : - { - _stext = . ; - *(.text) - *(.text.*) - *(.gnu.warning) - *(.stub) - *(.glue_7) - *(.glue_7t) - *(.jcr) - - /* C++ support: The .init and .fini sections contain specific logic - * to manage static constructors and destructors. - */ - - *(.gnu.linkonce.t.*) - *(.init) /* Old ABI */ - *(.fini) /* Old ABI */ - _etext = . ; - } - - .rodata : - { - _srodata = . ; - *(.rodata) - *(.rodata1) - *(.rodata.*) - *(.gnu.linkonce.r*) - _erodata = . ; - } - - .data : - { - _sdata = . ; - *(.data) - *(.data1) - *(.data.*) - *(.gnu.linkonce.d*) - . = ALIGN(4); - _edata = . ; - } - - /* C++ support. For each global and static local C++ object, - * GCC creates a small subroutine to construct the object. Pointers - * to these routines (not the routines themselves) are stored as - * simple, linear arrays in the .ctors section of the object file. - * Similarly, pointers to global/static destructor routines are - * stored in .dtors. - */ - - .ctors : - { - _sctors = . ; - *(.ctors) /* Old ABI: Unallocated */ - *(.init_array) /* New ABI: Allocated */ - _ectors = . ; - } - - .dtors : - { - _sdtors = . ; - *(.dtors) /* Old ABI: Unallocated */ - *(.fini_array) /* New ABI: Allocated */ - _edtors = . ; - } - - .bss : - { - _sbss = . ; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.b*) - *(COMMON) - _ebss = . ; - } - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_bringup.c index 726cefc1146..e1875b5e41c 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_bringup.c @@ -58,6 +58,10 @@ # include "esp32_board_wdt.h" #endif +#ifdef CONFIG_ESP32_RT_TIMER +# include "esp32_rt_timer.h" +#endif + #ifdef CONFIG_ESP32_WIRELESS # include "esp32_board_wlan.h" #endif @@ -66,6 +70,10 @@ # include #endif +#ifdef CONFIG_RTC_DRIVER +# include "esp32_rtc_lowerhalf.h" +#endif + #include "esp32-ethernet-kit.h" /**************************************************************************** @@ -153,6 +161,14 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESP32_RT_TIMER + ret = esp32_rt_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); + } +#endif + #ifdef CONFIG_ESP32_WIRELESS ret = board_wlan_init(); if (ret < 0) @@ -259,6 +275,17 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the ESP32 RTC driver */ + + ret = esp32_rtc_driverinit(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_buttons.c index 5840c74e1df..c0ebf1902e2 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_buttons.c @@ -24,10 +24,11 @@ #include +#include +#include #include #include #include -#include #include #include diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_spiflash.c b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_spiflash.c index d21109d3a4a..9a0d3b9a043 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_spiflash.c +++ b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_spiflash.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/autopm/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/autopm/defconfig new file mode 100644 index 00000000000..bddb794e0db --- /dev/null +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/autopm/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-wrover-kit" +CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32_AUTO_SLEEP=y +CONFIG_ESP32_MTD_SIZE=0x80000 +CONFIG_ESP32_SPIFLASH=y +CONFIG_ESP32_UART0=y +CONFIG_ESP32_WIFI_SAVE_PARAM=y +CONFIG_ESP32_WIRELESS=y +CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y +CONFIG_FS_PROCFS=y +CONFIG_FS_SPIFFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_MM_REGIONS=3 +CONFIG_NAME_MAX=48 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SIG_DEFAULT=y +CONFIG_SPIFFS_NAME_MAX=48 +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig index 27ac7897883..b2b2ada6051 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig @@ -27,7 +27,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig index 6b7d0fbaf97..5ed4e692d59 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig @@ -32,7 +32,6 @@ CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig index 864183b3f90..ba4f1dfa39e 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig @@ -28,7 +28,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig index 6b88b9df2a6..69214bc785b 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig @@ -26,7 +26,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig index 0e544e0ff9e..6fd81faec75 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig @@ -41,7 +41,6 @@ CONFIG_LCD_ILI9341=y CONFIG_LCD_ILI9341_IFACE0=y CONFIG_LV_COLOR_16_SWAP=y CONFIG_LV_DPI=125 -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig index 8fc6809731b..da04fb06785 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig index 9fb1fde3312..8ca1bb8ff52 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig @@ -44,7 +44,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_ILI9341=y CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig index 30c827b369c..193ea9f2545 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig @@ -32,7 +32,6 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig new file mode 100644 index 00000000000..c69edd81ed5 --- /dev/null +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-wrover-kit" +CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32_RT_TIMER=y +CONFIG_ESP32_UART0=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_RTC_NALARMS=2 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/tickless/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/tickless/defconfig new file mode 100644 index 00000000000..4c6b6773dcc --- /dev/null +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/tickless/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-wrover-kit" +CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32_TICKLESS=y +CONFIG_ESP32_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/wapi/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/wapi/defconfig index f412669f2b5..50b443149da 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/wapi/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/wapi/defconfig @@ -33,7 +33,6 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MAX_TASKS=16 CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 CONFIG_NETDB_DNSCLIENT=y @@ -43,7 +42,6 @@ CONFIG_NETDEV_WIRELESS_IOCTL=y CONFIG_NET_BROADCAST=y CONFIG_NET_ICMP=y CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOCKOPTS=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/Make.defs b/boards/xtensa/esp32/esp32-wrover-kit/scripts/Make.defs index 4c02ca2f3e1..761605dec4b 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/Make.defs +++ b/boards/xtensa/esp32/esp32-wrover-kit/scripts/Make.defs @@ -24,22 +24,15 @@ include $(TOPDIR)/tools/esp32/Config.mk include $(TOPDIR)/arch/xtensa/src/lx6/Toolchain.defs LDSCRIPT1 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_out.ld -LDSCRIPT3 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_rom.ld -LDSCRIPT4 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_peripherals.ld - -ifeq ($(CONFIG_ESP32_RUN_IRAM),y) - LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_iram.ld -else - LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32_flash.ld -endif +LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32.ld +LDSCRIPT3 = $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32_rom.ld ifeq ($(CONFIG_CYGWIN_WINTOOL),y) ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}" ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}" ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}" - ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}" else - ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4) + ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) endif ifeq ($(CONFIG_DEBUG_SYMBOLS),y) @@ -91,9 +84,9 @@ CXXELFFLAGS = $(CXXFLAGS) -mtext-section-literals LDELFFLAGS = -r -e main ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}" + LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld}" else - LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld + LDELFFLAGS += -T $(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld endif LDFLAGS += -nostartfiles -nodefaultlibs diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_flash.ld b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.ld similarity index 94% rename from boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_flash.ld rename to boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.ld index 16a9c106ce0..705815bf3e1 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_flash.ld +++ b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_flash.ld + * boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.ld ****************************************************************************/ /* Default entry point: */ @@ -66,10 +66,10 @@ SECTIONS *(.phyiram .phyiram.*) _iram_text_end = ABSOLUTE(.); - /* Module text area starts at the end of iram0_0_seg */ + /* iram heap starts at the end of iram0_0_seg */ . = ALIGN (4); - _smodtext = ABSOLUTE(.); + _siramheap = ABSOLUTE(.); } > iram0_0_seg /* Shared RAM */ @@ -192,7 +192,7 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - } >drom0_0_seg + } >default_rodata_seg .flash.text : { @@ -205,7 +205,7 @@ SECTIONS *(.gnu.version) _text_end = ABSOLUTE(.); _etext = .; - } >iram0_2_seg + } >default_code_seg .rtc.text : { @@ -217,5 +217,10 @@ SECTIONS { *(.rtc.data) *(.rtc.rodata) + + /* Whatever is left from the RTC memory is used as a special heap. */ + + . = ALIGN (4); + _srtcheap = ABSOLUTE(.); } > rtc_slow_seg } diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld index f5ea00b00cb..8e5d98c6918 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld +++ b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld @@ -28,17 +28,16 @@ MEMORY iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 - /* Even though the segment name is iram, it is actually mapped to flash. + /* Flash mapped instruction data. * - * NOTE: (0x20 offset above is a convenience for the app binary image - * generation. + * The 0x20 offset is a convenience for the app binary image generation. * Flash cache has 64KB pages. The .bin file which is flashed to the chip * has a 0x18 byte file header, and each segment has a 0x08 byte segment * header. Setting this offset makes it simple to meet the flash cache MMU's * constraint that (paddr % 64KB == vaddr % 64KB).) */ - iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20 + irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20 /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. * Enabling Bluetooth & Trace Memory features in menuconfig will decrease @@ -74,10 +73,22 @@ MEMORY extmem_seg(RWX) : org = 0x3f800000, len = 0x400000 } +#if CONFIG_ESP32_DEVKIT_RUN_IRAM + REGION_ALIAS("default_rodata_seg", dram0_0_seg); + REGION_ALIAS("default_code_seg", iram0_0_seg); +#else + REGION_ALIAS("default_rodata_seg", drom0_0_seg); + REGION_ALIAS("default_code_seg", irom0_0_seg); +#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */ + /* Heap ends at top of dram0_0_seg */ _eheap = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; -/* Module text area ends at top of dram0_0_seg */ +/* IRAM heap ends at top of dram0_0_seg */ -_emodtext = 0x400a0000; +_eiramheap = 0x400a0000; + +/* Mark the end of the RTC heap (top of the RTC region) */ + +_ertcheap = 0x50001fff; diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_iram.ld b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_iram.ld deleted file mode 100644 index 27b6042e207..00000000000 --- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_iram.ld +++ /dev/null @@ -1,196 +0,0 @@ -/**************************************************************************** - * boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_iram.ld - ****************************************************************************/ - -/* Default entry point: */ - -ENTRY(__start); - -SECTIONS -{ - /* Send .iram0 code to iram */ - - .iram0.vectors : - { - /* Vectors go to IRAM */ - - _init_start = ABSOLUTE(.); - - /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ - - . = 0x0; - KEEP (*(.window_vectors.text)); - . = 0x180; - KEEP (*(.xtensa_level2_vector.text)); - . = 0x1c0; - KEEP (*(.xtensa_level3_vector.text)); - . = 0x200; - KEEP (*(.xtensa_level4_vector.text)); - . = 0x240; - KEEP (*(.xtensa_level5_vector.text)); - . = 0x280; - KEEP (*(.debug_exception_vector.text)); - . = 0x2c0; - KEEP (*(.nmi_vector.text)); - . = 0x300; - KEEP (*(.kernel_exception_vector.text)); - . = 0x340; - KEEP (*(.user_exception_vector.text)); - . = 0x3c0; - KEEP (*(.double_exception_vector.text)); - . = 0x400; - *(.*_vector.literal) - - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - _init_end = ABSOLUTE(.); - } > iram0_0_seg - - .iram0.text : - { - /* Code marked as running out of IRAM */ - - _iram_text_start = ABSOLUTE(.); - *(.iram1 .iram1.*) - *libphy.a:(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) - *libpp.a:(.literal .text .literal.* .text.*) - *libhal.a:(.literal .text .literal.* .text.*) - _iram_text_end = ABSOLUTE(.); - - _stext = .; - _text_start = ABSOLUTE(.); - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - - /* Module text area starts at the end of iram0_0_seg */ - - . = ALIGN (4); - _smodtext = ABSOLUTE(.); - } > iram0_0_seg - - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - /* .bss initialized on power-up */ - - . = ALIGN (8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - KEEP (*(.bss)) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } >dram0_0_seg - - .noinit (NOLOAD): - { - /* This section contains data that is not initialized during load, - * or during the application's initialization sequence. - */ - - *(.noinit) - } >dram0_0_seg - - .dram0.data : - { - /* .data initialized on power-up in ROMed configurations. */ - - _sdata = ABSOLUTE(.); - KEEP (*(.data)) - KEEP (*(.data.*)) - KEEP (*(.gnu.linkonce.d.*)) - KEEP (*(.data1)) - KEEP (*(.sdata)) - KEEP (*(.sdata.*)) - KEEP (*(.gnu.linkonce.s.*)) - KEEP (*(.sdata2)) - KEEP (*(.sdata2.*)) - KEEP (*(.gnu.linkonce.s2.*)) - KEEP (*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - _edata = ABSOLUTE(.); - - _srodata = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - *(.eh_frame) - - . = (. + 3) & ~ 3; - - /* C++ constructor and destructor tables, properly ordered: */ - - _sinit = ABSOLUTE(.); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - _einit = ABSOLUTE(.); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - - /* C++ exception handlers table: */ - - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - _erodata = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - - /* Heap starts at the end of .data */ - - _sheap = ABSOLUTE(.); - } >dram0_0_seg - - .rtc.text : - { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - } >rtc_iram_seg - - .rtc.data : - { - *(.rtc.data) - *(.rtc.rodata) - } > rtc_slow_seg -} diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_peripherals.ld b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_peripherals.ld deleted file mode 100644 index af55704d82f..00000000000 --- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_peripherals.ld +++ /dev/null @@ -1,24 +0,0 @@ -/**************************************************************************** - * boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_peripherals.ld - ****************************************************************************/ - -PROVIDE ( UART0 = 0x3ff40000 ); -PROVIDE ( SPI1 = 0x3ff42000 ); -PROVIDE ( SPI0 = 0x3ff43000 ); -PROVIDE ( GPIO = 0x3ff44000 ); -PROVIDE ( SIGMADELTA = 0x3ff44f00 ); -PROVIDE ( UHCI1 = 0x3ff4C000 ); -PROVIDE ( I2S0 = 0x3ff4F000 ); -PROVIDE ( UART1 = 0x3ff50000 ); -PROVIDE ( I2C0 = 0x3ff53000 ); -PROVIDE ( UHCI0 = 0x3ff54000 ); -PROVIDE ( RMT = 0x3ff56000 ); -PROVIDE ( PCNT = 0x3ff57000 ); -PROVIDE ( LEDC = 0x3ff59000 ); -PROVIDE ( TIMERG0 = 0x3ff5F000 ); -PROVIDE ( TIMERG1 = 0x3ff60000 ); -PROVIDE ( SPI2 = 0x3ff64000 ); -PROVIDE ( SPI3 = 0x3ff65000 ); -PROVIDE ( I2C1 = 0x3ff67000 ); -PROVIDE ( I2S1 = 0x3ff6D000 ); -PROVIDE ( UART2 = 0x3ff6E000 ); diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_rom.ld b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_rom.ld deleted file mode 100644 index 6088eeb708a..00000000000 --- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32_rom.ld +++ /dev/null @@ -1,1858 +0,0 @@ -/* -ESP32 ROM address table -Generated for ROM with MD5sum: -ab8282ae908fe9e7a63fb2a4ac2df013 ../../rom_image/prorom.elf -*/ - -PROVIDE ( abort = 0x4000bba4 ); -PROVIDE ( abs = 0x40056340 ); -PROVIDE ( __absvdi2 = 0x4006387c ); -PROVIDE ( __absvsi2 = 0x40063868 ); -PROVIDE ( Add2SelfBigHex256 = 0x40015b7c ); -PROVIDE ( AddBigHex256 = 0x40015b28 ); -PROVIDE ( AddBigHexModP256 = 0x40015c98 ); -PROVIDE ( __adddf3 = 0x40002590 ); -PROVIDE ( AddP256 = 0x40015c74 ); -PROVIDE ( AddPdiv2_256 = 0x40015ce0 ); -PROVIDE ( __addsf3 = 0x400020e8 ); -PROVIDE ( __addvdi3 = 0x40002cbc ); -PROVIDE ( __addvsi3 = 0x40002c98 ); -PROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c ); -PROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 ); -PROVIDE ( aes_unwrap = 0x4005ccf0 ); -PROVIDE ( app_gpio_arg = 0x3ffe003c ); -PROVIDE ( app_gpio_handler = 0x3ffe0040 ); -PROVIDE ( __ascii_wctomb = 0x40058ef0 ); -PROVIDE ( asctime = 0x40059588 ); -PROVIDE ( asctime_r = 0x40000ec8 ); -PROVIDE ( __ashldi3 = 0x4000c818 ); -PROVIDE ( __ashrdi3 = 0x4000c830 ); -PROVIDE ( asiprintf = 0x40056d9c ); -PROVIDE ( _asiprintf_r = 0x40056d4c ); -PROVIDE ( asniprintf = 0x40056cd8 ); -PROVIDE ( _asniprintf_r = 0x40056c64 ); -PROVIDE ( asnprintf = 0x40056cd8 ); -PROVIDE ( _asnprintf_r = 0x40056c64 ); -PROVIDE ( asprintf = 0x40056d9c ); -PROVIDE ( _asprintf_r = 0x40056d4c ); -PROVIDE ( atoi = 0x400566c4 ); -PROVIDE ( _atoi_r = 0x400566d4 ); -PROVIDE ( atol = 0x400566ec ); -PROVIDE ( _atol_r = 0x400566fc ); -PROVIDE ( base64_decode = 0x4005ced8 ); -PROVIDE ( base64_encode = 0x4005cdbc ); -PROVIDE ( BasePoint_x_256 = 0x3ff97488 ); -PROVIDE ( BasePoint_y_256 = 0x3ff97468 ); -PROVIDE ( bigHexInversion256 = 0x400168f0 ); -PROVIDE ( bigHexP256 = 0x3ff973bc ); -PROVIDE ( __bswapdi2 = 0x400649c4 ); -PROVIDE ( __bswapsi2 = 0x4006499c ); -PROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c ); -PROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 ); -PROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 ); -PROVIDE ( btdm_r_data_init = 0x4001002c ); -PROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 ); -PROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 ); -PROVIDE ( btdm_r_ip_func_p_set = 0x40019afc ); -PROVIDE ( btdm_r_modules_func_p_get = 0x4005427c ); -PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 ); -PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 ); -PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 ); -PROVIDE ( bzero = 0x4000c1f4 ); -PROVIDE ( cache_flash_mmu_set = 0x400095e0 ); -PROVIDE ( cache_flush = 0x40009a14 ); -PROVIDE ( cache_read_disable = 0x40009ab8 ); -PROVIDE ( cache_read_enable = 0x40009a84 ); -PROVIDE ( cache_read_init = 0x40009950 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( calc_rtc_memory_crc = 0x40008170 ); -PROVIDE ( calloc = 0x4000bee4 ); -PROVIDE ( _calloc_r = 0x4000bbf8 ); -PROVIDE ( check_pos = 0x400068b8 ); -PROVIDE ( _cleanup = 0x40001df8 ); -PROVIDE ( _cleanup_r = 0x40001d48 ); -PROVIDE ( __clear_cache = 0x40063860 ); -PROVIDE ( close = 0x40001778 ); -PROVIDE ( _close_r = 0x4000bd3c ); -PROVIDE ( __clrsbdi2 = 0x40064a38 ); -PROVIDE ( __clrsbsi2 = 0x40064a20 ); -PROVIDE ( __clzdi2 = 0x4000ca50 ); -PROVIDE ( __clzsi2 = 0x4000c7e8 ); -PROVIDE ( __cmpdi2 = 0x40063820 ); -PROVIDE ( co_default_bdaddr = 0x3ffae704 ); -PROVIDE ( co_null_bdaddr = 0x3ffb80e0 ); -PROVIDE ( co_sca2ppm = 0x3ff971e8 ); -PROVIDE ( crc16_be = 0x4005d09c ); -PROVIDE ( crc16_le = 0x4005d05c ); -PROVIDE ( crc32_be = 0x4005d024 ); -PROVIDE ( crc32_le = 0x4005cfec ); -PROVIDE ( crc8_be = 0x4005d114 ); -PROVIDE ( crc8_le = 0x4005d0e0 ); -PROVIDE ( creat = 0x40000e8c ); -PROVIDE ( ctime = 0x400595b0 ); -PROVIDE ( ctime_r = 0x400595c4 ); -PROVIDE ( _ctype_ = 0x3ff96354 ); -PROVIDE ( __ctype_ptr__ = 0x3ff96350 ); -PROVIDE ( __ctzdi2 = 0x4000ca64 ); -PROVIDE ( __ctzsi2 = 0x4000c7f0 ); -PROVIDE ( _data_end = 0x4000d5c8 ); -PROVIDE ( _data_end_btdm_rom = 0x4000d4f8 ); -PROVIDE ( _data_start = 0x4000d4f8 ); -PROVIDE ( _data_start_btdm_rom = 0x4000d4f4 ); -PROVIDE ( _data_start_btdm = 0x3ffae6e0); -PROVIDE ( _data_end_btdm = 0x3ffaff10); -PROVIDE ( _sbss_btdm = 0x3ffb8000); -PROVIDE ( _ebss_btdm = 0x3ffbff70); -PROVIDE ( _daylight = 0x3ffae0a4 ); -PROVIDE ( dbg_default_handler = 0x3ff97218 ); -PROVIDE ( dbg_state = 0x3ffb8d5d ); -PROVIDE ( DebugE256PublicKey_x = 0x3ff97428 ); -PROVIDE ( DebugE256PublicKey_y = 0x3ff97408 ); -PROVIDE ( DebugE256SecretKey = 0x3ff973e8 ); -PROVIDE ( _DebugExceptionVector = 0x40000280 ); -PROVIDE ( debug_timer = 0x3ffe042c ); -PROVIDE ( debug_timerfn = 0x3ffe0430 ); -PROVIDE ( dh_group14_generator = 0x3ff9ac60 ); -PROVIDE ( dh_group14_prime = 0x3ff9ab60 ); -PROVIDE ( dh_group15_generator = 0x3ff9ab5f ); -PROVIDE ( dh_group15_prime = 0x3ff9a9df ); -PROVIDE ( dh_group16_generator = 0x3ff9a9de ); -PROVIDE ( dh_group16_prime = 0x3ff9a7de ); -PROVIDE ( dh_group17_generator = 0x3ff9a7dd ); -PROVIDE ( dh_group17_prime = 0x3ff9a4dd ); -PROVIDE ( dh_group18_generator = 0x3ff9a4dc ); -PROVIDE ( dh_group18_prime = 0x3ff9a0dc ); -PROVIDE ( dh_group1_generator = 0x3ff9ae03 ); -PROVIDE ( dh_group1_prime = 0x3ff9ada3 ); -PROVIDE ( dh_group2_generator = 0x3ff9ada2 ); -PROVIDE ( dh_group2_prime = 0x3ff9ad22 ); -PROVIDE ( dh_group5_generator = 0x3ff9ad21 ); -PROVIDE ( dh_group5_prime = 0x3ff9ac61 ); -PROVIDE ( div = 0x40056348 ); -PROVIDE ( __divdc3 = 0x40064460 ); -PROVIDE ( __divdf3 = 0x40002954 ); -PROVIDE ( __divdi3 = 0x4000ca84 ); -PROVIDE ( __divsc3 = 0x40064200 ); -PROVIDE ( __divsf3 = 0x4000234c ); -PROVIDE ( __divsi3 = 0x4000c7b8 ); -PROVIDE ( _DoubleExceptionVector = 0x400003c0 ); -PROVIDE ( dummy_len_plus = 0x3ffae290 ); -PROVIDE ( __dummy_lock = 0x4000c728 ); -PROVIDE ( __dummy_lock_try = 0x4000c730 ); -PROVIDE ( ecc_env = 0x3ffb8d60 ); -PROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 ); -PROVIDE ( em_buf_env = 0x3ffb8d74 ); -PROVIDE ( environ = 0x3ffae0b4 ); -PROVIDE ( __env_lock = 0x40001fd4 ); -PROVIDE ( __env_unlock = 0x40001fe0 ); -PROVIDE ( __eqdf2 = 0x400636a8 ); -PROVIDE ( __eqsf2 = 0x40063374 ); -PROVIDE ( esp_crc8 = 0x4005d144 ); -PROVIDE ( _etext = 0x4000d66c ); -PROVIDE ( ets_aes_crypt = 0x4005c9b8 ); -PROVIDE ( ets_aes_disable = 0x4005c8f8 ); -PROVIDE ( ets_aes_enable = 0x4005c8cc ); -PROVIDE ( ets_aes_set_endian = 0x4005c928 ); -PROVIDE ( ets_aes_setkey_dec = 0x4005c994 ); -PROVIDE ( ets_aes_setkey_enc = 0x4005c97c ); -PROVIDE ( ets_bigint_disable = 0x4005c4e0 ); -PROVIDE ( ets_bigint_enable = 0x4005c498 ); -PROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 ); -PROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 ); -PROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 ); -PROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c ); -PROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 ); -PROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc ); -PROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 ); -PROVIDE ( ets_bigint_mult_prepare = 0x4005c630 ); -PROVIDE ( ets_bigint_wait_finish = 0x4005c520 ); -PROVIDE ( ets_delay_us = 0x40008534 ); -PROVIDE ( ets_efuse_get_8M_clock = 0x40008710 ); -PROVIDE ( ets_efuse_get_spiconfig = 0x40008658 ); -PROVIDE ( ets_efuse_program_op = 0x40008628 ); -PROVIDE ( ets_efuse_read_op = 0x40008600 ); -PROVIDE ( ets_get_cpu_frequency = 0x4000855c ); -PROVIDE ( ets_get_detected_xtal_freq = 0x40008588 ); -PROVIDE ( ets_get_xtal_scale = 0x4000856c ); -PROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 ); -PROVIDE ( ets_install_putc1 = 0x40007d18 ); -PROVIDE ( ets_install_putc2 = 0x40007d38 ); -PROVIDE ( ets_install_uart_printf = 0x40007d28 ); -PROVIDE ( ets_intr_count = 0x3ffe03fc ); -PROVIDE ( ets_intr_lock = 0x400067b0 ); -PROVIDE ( ets_intr_unlock = 0x400067c4 ); -PROVIDE ( ets_isr_attach = 0x400067ec ); -PROVIDE ( ets_isr_mask = 0x400067fc ); -PROVIDE ( ets_isr_unmask = 0x40006808 ); -PROVIDE ( ets_post = 0x4000673c ); -PROVIDE ( ets_printf = 0x40007d54 ); -PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 ); -PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 ); -PROVIDE ( ets_readySet_ = 0x3ffe01f0 ); -PROVIDE ( ets_run = 0x400066bc ); -PROVIDE ( ets_secure_boot_check = 0x4005cb40 ); -PROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 ); -PROVIDE ( ets_secure_boot_check_start = 0x4005cbcc ); -PROVIDE ( ets_secure_boot_finish = 0x4005ca84 ); -PROVIDE ( ets_secure_boot_hash = 0x4005cad4 ); -PROVIDE ( ets_secure_boot_obtain = 0x4005cb14 ); -PROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 ); -PROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 ); -PROVIDE ( ets_secure_boot_start = 0x4005ca34 ); -PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c ); -PROVIDE ( ets_set_idle_cb = 0x40006674 ); -PROVIDE ( ets_set_startup_callback = 0x4000688c ); -PROVIDE ( ets_set_user_start = 0x4000687c ); -PROVIDE ( ets_sha_disable = 0x4005c0a8 ); -PROVIDE ( ets_sha_enable = 0x4005c07c ); -PROVIDE ( ets_sha_finish = 0x4005c104 ); -PROVIDE ( ets_sha_init = 0x4005c0d4 ); -PROVIDE ( ets_sha_update = 0x4005c2a0 ); -PROVIDE ( ets_startup_callback = 0x3ffe0404 ); -PROVIDE ( ets_task = 0x40006688 ); -PROVIDE ( ets_timer_arm = 0x40008368 ); -PROVIDE ( ets_timer_arm_us = 0x400083ac ); -PROVIDE ( ets_timer_disarm = 0x400083ec ); -PROVIDE ( ets_timer_done = 0x40008428 ); -PROVIDE ( ets_timer_handler_isr = 0x40008454 ); -PROVIDE ( ets_timer_init = 0x400084e8 ); -PROVIDE ( ets_timer_setfn = 0x40008350 ); -PROVIDE ( ets_unpack_flash_code = 0x40007018 ); -PROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c ); -PROVIDE ( ets_update_cpu_frequency = 0x40008550 ); -PROVIDE ( ets_waiti0 = 0x400067d8 ); -PROVIDE ( exc_cause_table = 0x3ff991d0 ); -PROVIDE ( _exit_r = 0x4000bd28 ); -PROVIDE ( __extendsfdf2 = 0x40002c34 ); -PROVIDE ( fclose = 0x400020ac ); -PROVIDE ( _fclose_r = 0x40001fec ); -PROVIDE ( fflush = 0x40059394 ); -PROVIDE ( _fflush_r = 0x40059320 ); -PROVIDE ( __ffsdi2 = 0x4000ca2c ); -PROVIDE ( __ffssi2 = 0x4000c804 ); -PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 ); -PROVIDE ( FilePacketSendReqMsgProc = 0x40008860 ); -PROVIDE ( _findenv_r = 0x40001f44 ); -PROVIDE ( fiprintf = 0x40056efc ); -PROVIDE ( _fiprintf_r = 0x40056ed8 ); -PROVIDE ( fiscanf = 0x40058884 ); -PROVIDE ( _fiscanf_r = 0x400588b4 ); -PROVIDE ( __fixdfdi = 0x40002ac4 ); -PROVIDE ( __fixdfsi = 0x40002a78 ); -PROVIDE ( __fixsfdi = 0x4000244c ); -PROVIDE ( __fixsfsi = 0x4000240c ); -PROVIDE ( __fixunsdfsi = 0x40002b30 ); -PROVIDE ( __fixunssfdi = 0x40002504 ); -PROVIDE ( __fixunssfsi = 0x400024ac ); -PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 ); -PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c ); -PROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 ); -PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 ); -PROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec ); -PROVIDE ( __floatdidf = 0x4000c988 ); -PROVIDE ( __floatdisf = 0x4000c8c0 ); -PROVIDE ( __floatsidf = 0x4000c944 ); -PROVIDE ( __floatsisf = 0x4000c870 ); -PROVIDE ( __floatundidf = 0x4000c978 ); -PROVIDE ( __floatundisf = 0x4000c8b0 ); -PROVIDE ( __floatunsidf = 0x4000c938 ); -PROVIDE ( __floatunsisf = 0x4000c864 ); -PROVIDE ( __fp_lock_all = 0x40001f1c ); -PROVIDE ( fprintf = 0x40056efc ); -PROVIDE ( _fprintf_r = 0x40056ed8 ); -PROVIDE ( __fp_unlock_all = 0x40001f30 ); -PROVIDE ( fputwc = 0x40058ea8 ); -PROVIDE ( __fputwc = 0x40058da0 ); -PROVIDE ( _fputwc_r = 0x40058e4c ); -PROVIDE ( free = 0x4000beb8 ); -PROVIDE ( _free_r = 0x4000bbcc ); -PROVIDE ( fscanf = 0x40058884 ); -PROVIDE ( _fscanf_r = 0x400588b4 ); -PROVIDE ( _fstat_r = 0x4000bccc ); -PROVIDE ( _fwalk = 0x4000c738 ); -PROVIDE ( _fwalk_reent = 0x4000c770 ); -PROVIDE ( __gcc_bcmp = 0x40064a70 ); -PROVIDE ( __gedf2 = 0x40063768 ); -PROVIDE ( _GeneralException = 0x40000e14 ); -PROVIDE ( __gesf2 = 0x4006340c ); -PROVIDE ( __get_current_time_locale = 0x40001834 ); -PROVIDE ( _getenv_r = 0x40001fbc ); -PROVIDE ( _getpid_r = 0x4000bcfc ); -PROVIDE ( __getreent = 0x4000be8c ); -PROVIDE ( _gettimeofday_r = 0x4000bc58 ); -PROVIDE ( __gettzinfo = 0x40001fcc ); -PROVIDE ( GetUartDevice = 0x40009598 ); -PROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 ); -PROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 ); -PROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c ); -PROVIDE ( _global_impure_ptr = 0x3ffae0b0 ); -PROVIDE ( gmtime = 0x40059848 ); -PROVIDE ( gmtime_r = 0x40059868 ); -PROVIDE ( g_phyFuns_instance = 0x3ffae0c4 ); -PROVIDE ( gpio_init = 0x40009c20 ); -PROVIDE ( gpio_input_get = 0x40009b88 ); -PROVIDE ( gpio_input_get_high = 0x40009b9c ); -PROVIDE ( gpio_intr_ack = 0x40009dd4 ); -PROVIDE ( gpio_intr_ack_high = 0x40009e1c ); -PROVIDE ( gpio_intr_handler_register = 0x40009e6c ); -PROVIDE ( gpio_intr_pending = 0x40009cec ); -PROVIDE ( gpio_intr_pending_high = 0x40009cf8 ); -PROVIDE ( gpio_matrix_in = 0x40009edc ); -PROVIDE ( gpio_matrix_out = 0x40009f0c ); -PROVIDE ( gpio_output_set = 0x40009b24 ); -PROVIDE ( gpio_output_set_high = 0x40009b5c ); -PROVIDE ( gpio_pad_hold = 0x4000a734 ); -PROVIDE ( gpio_pad_pulldown = 0x4000a348 ); -PROVIDE ( gpio_pad_pullup = 0x4000a22c ); -PROVIDE ( gpio_pad_select_gpio = 0x40009fdc ); -PROVIDE ( gpio_pad_set_drv = 0x4000a11c ); -PROVIDE ( gpio_pad_unhold = 0x4000a484 ); -PROVIDE ( gpio_pending_mask = 0x3ffe0038 ); -PROVIDE ( gpio_pending_mask_high = 0x3ffe0044 ); -PROVIDE ( gpio_pin_intr_state_set = 0x40009d04 ); -PROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 ); -PROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c ); -PROVIDE ( gpio_register_get = 0x40009cbc ); -PROVIDE ( gpio_register_set = 0x40009bbc ); -PROVIDE ( __gtdf2 = 0x400636dc ); -PROVIDE ( __gtsf2 = 0x400633a0 ); -PROVIDE ( gTxMsg = 0x3ffe0050 ); -PROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 ); -PROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 ); -PROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c ); -PROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 ); -PROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 ); -PROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c ); -PROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 ); -PROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 ); -PROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 ); -PROVIDE ( hci_command_handler = 0x4004c928 ); -PROVIDE ( hci_env = 0x3ffb9350 ); -PROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c ); -PROVIDE ( hci_evt_desc_tab = 0x3ff9751c ); -PROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 ); -PROVIDE ( hci_fc_env = 0x3ffb9340 ); -PROVIDE ( hmac_md5 = 0x4005d264 ); -PROVIDE ( hmac_md5_vector = 0x4005d17c ); -PROVIDE ( hmac_sha1 = 0x40060acc ); -PROVIDE ( hmac_sha1_vector = 0x400609e4 ); -PROVIDE ( hmac_sha256 = 0x40060d58 ); -PROVIDE ( hmac_sha256_vector = 0x40060c84 ); -PROVIDE ( intr_matrix_set = 0x4000681c ); -PROVIDE ( iprintf = 0x40056978 ); -PROVIDE ( _iprintf_r = 0x40056944 ); -PROVIDE ( isalnum = 0x40000f04 ); -PROVIDE ( isalpha = 0x40000f18 ); -PROVIDE ( isascii = 0x4000c20c ); -PROVIDE ( _isatty_r = 0x40000ea0 ); -PROVIDE ( isblank = 0x40000f2c ); -PROVIDE ( iscanf = 0x40058760 ); -PROVIDE ( _iscanf_r = 0x4005879c ); -PROVIDE ( iscntrl = 0x40000f50 ); -PROVIDE ( isdigit = 0x40000f64 ); -PROVIDE ( isgraph = 0x40000f94 ); -PROVIDE ( islower = 0x40000f78 ); -PROVIDE ( isprint = 0x40000fa8 ); -PROVIDE ( ispunct = 0x40000fc0 ); -PROVIDE ( isspace = 0x40000fd4 ); -PROVIDE ( isupper = 0x40000fe8 ); -PROVIDE ( itoa = 0x400566b4 ); -PROVIDE ( __itoa = 0x40056678 ); -PROVIDE ( jd_decomp = 0x400613e8 ); -PROVIDE ( jd_prepare = 0x40060fa8 ); -PROVIDE ( ke_env = 0x3ffb93cc ); -PROVIDE ( _KernelExceptionVector = 0x40000300 ); -PROVIDE ( _kill_r = 0x4000bd10 ); -PROVIDE ( labs = 0x40056370 ); -PROVIDE ( lb_default_handler = 0x3ff982b8 ); -PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 ); -PROVIDE ( lb_env = 0x3ffb9424 ); -PROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c ); -PROVIDE ( lb_state = 0x3ffb94e8 ); -PROVIDE ( lc_default_handler = 0x3ff98648 ); -PROVIDE ( lc_default_state_tab_p_get = 0x4002f494 ); -PROVIDE ( lc_env = 0x3ffb94ec ); -PROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 ); -PROVIDE ( lc_state = 0x3ffb9508 ); -PROVIDE ( ld_acl_br_sizes = 0x3ff98a2a ); -PROVIDE ( ld_acl_br_types = 0x3ff98a36 ); -PROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 ); -PROVIDE ( ld_acl_edr_types = 0x3ff98a22 ); -PROVIDE ( ld_env = 0x3ffb9510 ); -PROVIDE ( ldiv = 0x40056378 ); -PROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c ); -PROVIDE ( ld_sched_params = 0x3ffb96c0 ); -PROVIDE ( ld_sync_train_channels = 0x3ff98a3c ); -PROVIDE ( __ledf2 = 0x40063704 ); -PROVIDE ( __lesf2 = 0x400633c0 ); -PROVIDE ( _xtensa_level2_from = 0x40000954 ); -PROVIDE ( _xtensa_level2_vector = 0x40000180 ); -PROVIDE ( _xtensa_level3_from = 0x40000a28 ); -PROVIDE ( _xtensa_level3_vector = 0x400001c0 ); -PROVIDE ( _xtensa_level4_from = 0x40000af8 ); -PROVIDE ( _xtensa_level4_vector = 0x40000200 ); -PROVIDE ( _xtensa_level5_from = 0x40000c68 ); -PROVIDE ( _xtensa_level5_vector = 0x40000240 ); -PROVIDE ( _LevelOneInterrupt = 0x40000835 ); -PROVIDE ( _link_r = 0x4000bc9c ); -PROVIDE ( llc_default_handler = 0x3ff98b3c ); -PROVIDE ( llc_default_state_tab_p_get = 0x40046058 ); -PROVIDE ( llc_env = 0x3ffb96d0 ); -PROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 ); -PROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 ); -PROVIDE ( llc_hci_command_handler = 0x40042360 ); -PROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 ); -PROVIDE ( llc_state = 0x3ffb96f8 ); -PROVIDE ( lldesc_build_chain = 0x4000a850 ); -PROVIDE ( lldesc_num2link = 0x4000a948 ); -PROVIDE ( lldesc_set_owner = 0x4000a974 ); -PROVIDE ( lld_evt_env = 0x3ffb9704 ); -PROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 ); -PROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 ); -PROVIDE ( LLM_AA_CT1 = 0x3ff98d8a ); -PROVIDE ( LLM_AA_CT2 = 0x3ff98d88 ); -PROVIDE ( llm_default_handler = 0x3ff98d80 ); -PROVIDE ( llm_default_state_tab_p_get = 0x4004e718 ); -PROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 ); -PROVIDE ( llm_le_env = 0x3ffb976c ); -PROVIDE ( llm_local_cmds = 0x3ff98d38 ); -PROVIDE ( llm_local_data_len_values = 0x3ff98d1c ); -PROVIDE ( llm_local_le_feats = 0x3ff98d30 ); -PROVIDE ( llm_local_le_states = 0x3ff98d28 ); -PROVIDE ( llm_state = 0x3ffb985c ); -PROVIDE ( lm_default_handler = 0x3ff990e0 ); -PROVIDE ( lm_default_state_tab_p_get = 0x40054268 ); -PROVIDE ( lm_env = 0x3ffb9860 ); -PROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c ); -PROVIDE ( lm_local_supp_feats = 0x3ff990ee ); -PROVIDE ( lm_n_page_tab = 0x3ff990e8 ); -PROVIDE ( lmp_desc_tab = 0x3ff96e6c ); -PROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c ); -PROVIDE ( lm_state = 0x3ffb9a1c ); -PROVIDE ( __locale_charset = 0x40059540 ); -PROVIDE ( __locale_cjk_lang = 0x40059558 ); -PROVIDE ( localeconv = 0x4005957c ); -PROVIDE ( _localeconv_r = 0x40059560 ); -PROVIDE ( __locale_mb_cur_max = 0x40059548 ); -PROVIDE ( __locale_msgcharset = 0x40059550 ); -PROVIDE ( localtime = 0x400595dc ); -PROVIDE ( localtime_r = 0x400595fc ); -PROVIDE ( _lock_acquire = 0x4000be14 ); -PROVIDE ( _lock_acquire_recursive = 0x4000be28 ); -PROVIDE ( _lock_close = 0x4000bdec ); -PROVIDE ( _lock_close_recursive = 0x4000be00 ); -PROVIDE ( _lock_init = 0x4000bdc4 ); -PROVIDE ( _lock_init_recursive = 0x4000bdd8 ); -PROVIDE ( _lock_release = 0x4000be64 ); -PROVIDE ( _lock_release_recursive = 0x4000be78 ); -PROVIDE ( _lock_try_acquire = 0x4000be3c ); -PROVIDE ( _lock_try_acquire_recursive = 0x4000be50 ); -PROVIDE ( longjmp = 0x400562cc ); -PROVIDE ( _lseek_r = 0x4000bd8c ); -PROVIDE ( __lshrdi3 = 0x4000c84c ); -PROVIDE ( __ltdf2 = 0x40063790 ); -PROVIDE ( __ltsf2 = 0x4006342c ); -PROVIDE ( malloc = 0x4000bea0 ); -PROVIDE ( _malloc_r = 0x4000bbb4 ); -PROVIDE ( maxSecretKey_256 = 0x3ff97448 ); -PROVIDE ( __mb_cur_max = 0x3ff96530 ); -PROVIDE ( MD5Final = 0x4005db1c ); -PROVIDE ( MD5Init = 0x4005da7c ); -PROVIDE ( MD5Update = 0x4005da9c ); -PROVIDE ( md5_vector = 0x4005db80 ); -PROVIDE ( memccpy = 0x4000c220 ); -PROVIDE ( memchr = 0x4000c244 ); -PROVIDE ( memcmp = 0x4000c260 ); -PROVIDE ( memcpy = 0x4000c2c8 ); -PROVIDE ( MemDwnLdStartMsgProc = 0x40008948 ); -PROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc ); -PROVIDE ( memmove = 0x4000c3c0 ); -PROVIDE ( MemPacketSendReqMsgProc = 0x40008978 ); -PROVIDE ( memrchr = 0x4000c400 ); -PROVIDE ( memset = 0x4000c44c ); -PROVIDE ( mktime = 0x4005a5e8 ); -PROVIDE ( mmu_init = 0x400095a4 ); -PROVIDE ( __moddi3 = 0x4000cd4c ); -PROVIDE ( __modsi3 = 0x4000c7c0 ); -PROVIDE ( __month_lengths = 0x3ff9609c ); -PROVIDE ( __muldc3 = 0x40063bf4 ); -PROVIDE ( __muldf3 = 0x4006358c ); -PROVIDE ( __muldi3 = 0x4000c9fc ); -PROVIDE ( __mulsc3 = 0x40063934 ); -PROVIDE ( __mulsf3 = 0x400632c8 ); -PROVIDE ( __mulsi3 = 0x4000c7b0 ); -PROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 ); -PROVIDE ( MultiplyBigHexModP256 = 0x400160b8 ); -PROVIDE ( MultiplyByU32ModP256 = 0x40015fdc ); -PROVIDE ( multofup = 0x4000ab8c ); -PROVIDE ( __mulvdi3 = 0x40002d78 ); -PROVIDE ( __mulvsi3 = 0x40002d60 ); -PROVIDE ( mz_adler32 = 0x4005edbc ); -PROVIDE ( mz_crc32 = 0x4005ee88 ); -PROVIDE ( mz_free = 0x4005eed4 ); -PROVIDE ( __nedf2 = 0x400636a8 ); -PROVIDE ( __negdf2 = 0x400634a0 ); -PROVIDE ( __negdi2 = 0x4000ca14 ); -PROVIDE ( __negsf2 = 0x400020c0 ); -PROVIDE ( __negvdi2 = 0x40002e98 ); -PROVIDE ( __negvsi2 = 0x40002e78 ); -PROVIDE ( __nesf2 = 0x40063374 ); -PROVIDE ( _NMIExceptionVector = 0x400002c0 ); -PROVIDE ( notEqual256 = 0x40015b04 ); -PROVIDE ( __nsau_data = 0x3ff96544 ); -PROVIDE ( one_bits = 0x3ff971f8 ); -PROVIDE ( open = 0x4000178c ); -PROVIDE ( _open_r = 0x4000bd54 ); -PROVIDE ( __paritysi2 = 0x40002f3c ); -PROVIDE ( pbkdf2_sha1 = 0x40060ba4 ); -PROVIDE ( phy_get_romfuncs = 0x40004100 ); -PROVIDE ( __popcountdi2 = 0x40002ef8 ); -PROVIDE ( __popcountsi2 = 0x40002ed0 ); -PROVIDE ( __popcount_tab = 0x3ff96544 ); -PROVIDE ( __powidf2 = 0x400638d4 ); -PROVIDE ( __powisf2 = 0x4006389c ); -PROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 ); -PROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c ); -PROVIDE ( printf = 0x40056978 ); -PROVIDE ( _printf_common = 0x40057338 ); -PROVIDE ( _printf_float = 0x4000befc ); -PROVIDE ( _printf_i = 0x40057404 ); -PROVIDE ( _printf_r = 0x40056944 ); -PROVIDE ( qsort = 0x40056424 ); -PROVIDE ( _raise_r = 0x4000bc70 ); -PROVIDE ( rand = 0x40001058 ); -PROVIDE ( rand_r = 0x400010d4 ); -PROVIDE ( r_btdm_option_data = 0x3ffae6e0 ); -PROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 ); -PROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 ); -PROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 ); -PROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 ); -PROVIDE ( r_bt_util_buf_init = 0x400100e4 ); -PROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 ); -PROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec ); -PROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 ); -PROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 ); -PROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 ); -PROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c ); -PROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec ); -PROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 ); -PROVIDE ( rc4_skip = 0x40060928 ); -PROVIDE ( r_co_bdaddr_compare = 0x40014324 ); -PROVIDE ( r_co_bytes_to_string = 0x400142e4 ); -PROVIDE ( r_co_list_check_size_available = 0x400142c4 ); -PROVIDE ( r_co_list_extract = 0x4001404c ); -PROVIDE ( r_co_list_extract_after = 0x40014118 ); -PROVIDE ( r_co_list_find = 0x4001419c ); -PROVIDE ( r_co_list_init = 0x40013f14 ); -PROVIDE ( r_co_list_insert_after = 0x40014254 ); -PROVIDE ( r_co_list_insert_before = 0x40014200 ); -PROVIDE ( r_co_list_merge = 0x400141bc ); -PROVIDE ( r_co_list_pool_init = 0x40013f30 ); -PROVIDE ( r_co_list_pop_front = 0x40014028 ); -PROVIDE ( r_co_list_push_back = 0x40013fb8 ); -PROVIDE ( r_co_list_push_front = 0x40013ff4 ); -PROVIDE ( r_co_list_size = 0x400142ac ); -PROVIDE ( r_co_nb_good_channels = 0x40014360 ); -PROVIDE ( r_co_slot_to_duration = 0x40014348 ); -PROVIDE ( RcvMsg = 0x4000954c ); -PROVIDE ( r_dbg_init = 0x40014394 ); -PROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 ); -PROVIDE ( r_dbg_swdiag_init = 0x40014470 ); -PROVIDE ( r_dbg_swdiag_read = 0x400144a4 ); -PROVIDE ( r_dbg_swdiag_write = 0x400144d0 ); -PROVIDE ( r_E1 = 0x400108e8 ); -PROVIDE ( r_E21 = 0x40010968 ); -PROVIDE ( r_E22 = 0x400109b4 ); -PROVIDE ( r_E3 = 0x40010a58 ); -PROVIDE ( r_ea_alarm_clear = 0x40015ab4 ); -PROVIDE ( r_ea_alarm_set = 0x40015a10 ); -PROVIDE ( read = 0x400017dc ); -PROVIDE ( _read_r = 0x4000bda8 ); -PROVIDE ( r_ea_elt_cancel = 0x400150d0 ); -PROVIDE ( r_ea_elt_create = 0x40015264 ); -PROVIDE ( r_ea_elt_insert = 0x400152a8 ); -PROVIDE ( r_ea_elt_remove = 0x400154f0 ); -PROVIDE ( r_ea_finetimer_isr = 0x400155d4 ); -PROVIDE ( r_ea_init = 0x40015228 ); -PROVIDE ( r_ea_interval_create = 0x4001555c ); -PROVIDE ( r_ea_interval_delete = 0x400155a8 ); -PROVIDE ( r_ea_interval_duration_req = 0x4001597c ); -PROVIDE ( r_ea_interval_insert = 0x4001557c ); -PROVIDE ( r_ea_interval_remove = 0x40015590 ); -PROVIDE ( realloc = 0x4000becc ); -PROVIDE ( _realloc_r = 0x4000bbe0 ); -PROVIDE ( r_ea_offset_req = 0x40015748 ); -PROVIDE ( r_ea_sleep_check = 0x40015928 ); -PROVIDE ( r_ea_sw_isr = 0x40015724 ); -PROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 ); -PROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 ); -PROVIDE ( r_ecc_abort_key256_generation = 0x40017070 ); -PROVIDE ( r_ecc_generate_key256 = 0x40016e00 ); -PROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 ); -PROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 ); -PROVIDE ( r_ecc_get_debug_Keys = 0x40017224 ); -PROVIDE ( r_ecc_init = 0x40016dbc ); -PROVIDE ( RecvBuff = 0x3ffe009c ); -PROVIDE ( recv_packet = 0x40009424 ); -PROVIDE ( r_em_buf_init = 0x4001729c ); -PROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 ); -PROVIDE ( r_em_buf_rx_free = 0x400173c4 ); -PROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 ); -PROVIDE ( r_em_buf_tx_free = 0x4001741c ); -PROVIDE ( _rename_r = 0x4000bc28 ); -PROVIDE ( _ResetHandler = 0x40000450 ); -PROVIDE ( _ResetVector = 0x40000400 ); -PROVIDE ( r_F1_256 = 0x400133e4 ); -PROVIDE ( r_F2_256 = 0x40013568 ); -PROVIDE ( r_F3_256 = 0x40013664 ); -PROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c ); -PROVIDE ( r_G_256 = 0x40013470 ); -PROVIDE ( r_H3 = 0x40013760 ); -PROVIDE ( r_H4 = 0x40013830 ); -PROVIDE ( r_h4tl_init = 0x40017878 ); -PROVIDE ( r_h4tl_start = 0x40017924 ); -PROVIDE ( r_h4tl_stop = 0x40017934 ); -PROVIDE ( r_h4tl_write = 0x400178d0 ); -PROVIDE ( r_H5 = 0x400138dc ); -PROVIDE ( r_hashConcat = 0x40013a38 ); -PROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c ); -PROVIDE ( r_hci_acl_tx_data_received = 0x40019654 ); -PROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 ); -PROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac ); -PROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c ); -PROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 ); -PROVIDE ( r_hci_cmd_received = 0x400192f8 ); -PROVIDE ( r_hci_evt_filter_add = 0x40018a64 ); -PROVIDE ( r_hci_evt_mask_set = 0x400189e4 ); -PROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 ); -PROVIDE ( r_hci_fc_acl_en = 0x400179d8 ); -PROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c ); -PROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 ); -PROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 ); -PROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c ); -PROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 ); -PROVIDE ( r_hci_fc_init = 0x40017974 ); -PROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 ); -PROVIDE ( r_hci_fc_sync_en = 0x40017a30 ); -PROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 ); -PROVIDE ( r_hci_init = 0x40018538 ); -PROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 ); -PROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 ); -PROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 ); -PROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 ); -PROVIDE ( r_hci_reset = 0x4001856c ); -PROVIDE ( r_hci_send_2_host = 0x400185bc ); -PROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 ); -PROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 ); -PROVIDE ( r_hci_tl_init = 0x40019290 ); -PROVIDE ( r_hci_tl_send = 0x40019228 ); -PROVIDE ( r_hci_util_pack = 0x40019874 ); -PROVIDE ( r_hci_util_unpack = 0x40019998 ); -PROVIDE ( r_hci_voice_settings_get = 0x40018bdc ); -PROVIDE ( r_hci_voice_settings_set = 0x40018be8 ); -PROVIDE ( r_HMAC = 0x40013968 ); -PROVIDE ( r_import_rf_phy_func = 0x3ffb8354 ); -PROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 ); -PROVIDE ( r_ip_funcs = 0x3ffae710 ); -PROVIDE ( r_ip_funcs_p = 0x3ffae70c ); -PROVIDE ( r_ke_check_malloc = 0x40019de0 ); -PROVIDE ( r_ke_event_callback_set = 0x40019ba8 ); -PROVIDE ( r_ke_event_clear = 0x40019c2c ); -PROVIDE ( r_ke_event_flush = 0x40019ccc ); -PROVIDE ( r_ke_event_get = 0x40019c78 ); -PROVIDE ( r_ke_event_get_all = 0x40019cc0 ); -PROVIDE ( r_ke_event_init = 0x40019b90 ); -PROVIDE ( r_ke_event_schedule = 0x40019cdc ); -PROVIDE ( r_ke_event_set = 0x40019be0 ); -PROVIDE ( r_ke_flush = 0x4001a374 ); -PROVIDE ( r_ke_free = 0x4001a014 ); -PROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 ); -PROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 ); -PROVIDE ( r_ke_init = 0x4001a318 ); -PROVIDE ( r_ke_is_free = 0x4001a184 ); -PROVIDE ( r_ke_malloc = 0x40019eb4 ); -PROVIDE ( r_ke_mem_init = 0x40019d3c ); -PROVIDE ( r_ke_mem_is_empty = 0x40019d8c ); -PROVIDE ( r_ke_msg_alloc = 0x4001a1e0 ); -PROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 ); -PROVIDE ( r_ke_msg_discard = 0x4001a850 ); -PROVIDE ( r_ke_msg_forward = 0x4001a290 ); -PROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac ); -PROVIDE ( r_ke_msg_free = 0x4001a2cc ); -PROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 ); -PROVIDE ( r_ke_msg_save = 0x4001a858 ); -PROVIDE ( r_ke_msg_send = 0x4001a234 ); -PROVIDE ( r_ke_msg_send_basic = 0x4001a26c ); -PROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec ); -PROVIDE ( r_ke_queue_extract = 0x40055fd0 ); -PROVIDE ( r_ke_queue_insert = 0x40056020 ); -PROVIDE ( r_ke_sleep_check = 0x4001a3d8 ); -PROVIDE ( r_ke_state_get = 0x4001a7d8 ); -PROVIDE ( r_ke_state_set = 0x4001a6fc ); -PROVIDE ( r_ke_stats_get = 0x4001a3f0 ); -PROVIDE ( r_ke_task_check = 0x4001a8a4 ); -PROVIDE ( r_ke_task_create = 0x4001a674 ); -PROVIDE ( r_ke_task_delete = 0x4001a6c0 ); -PROVIDE ( r_ke_task_init = 0x4001a650 ); -PROVIDE ( r_ke_task_msg_flush = 0x4001a860 ); -PROVIDE ( r_ke_timer_active = 0x4001ac08 ); -PROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 ); -PROVIDE ( r_ke_timer_clear = 0x4001ab90 ); -PROVIDE ( r_ke_timer_init = 0x4001aa9c ); -PROVIDE ( r_ke_timer_set = 0x4001aac0 ); -PROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 ); -PROVIDE ( r_KPrimC = 0x40010ad4 ); -PROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 ); -PROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 ); -PROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 ); -PROVIDE ( r_lb_init = 0x4001acd4 ); -PROVIDE ( r_lb_mst_key = 0x4001afc0 ); -PROVIDE ( r_lb_mst_key_cmp = 0x4001af74 ); -PROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 ); -PROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 ); -PROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c ); -PROVIDE ( r_lb_reset = 0x4001ad38 ); -PROVIDE ( r_lb_send_lmp = 0x4001adbc ); -PROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c ); -PROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 ); -PROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 ); -PROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 ); -PROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c ); -PROVIDE ( r_lc_afh_set = 0x4001cc74 ); -PROVIDE ( r_lc_afh_start = 0x4001d240 ); -PROVIDE ( r_lc_auth_cmp = 0x4001cd54 ); -PROVIDE ( r_lc_calc_link_key = 0x4001ce7c ); -PROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 ); -PROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc ); -PROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac ); -PROVIDE ( r_lc_chk_to = 0x4001d2a8 ); -PROVIDE ( r_lc_cmd_stat_send = 0x4001c914 ); -PROVIDE ( r_lc_comb_key_svr = 0x4001d30c ); -PROVIDE ( r_lc_con_cmp = 0x4001d44c ); -PROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc ); -PROVIDE ( r_lc_conn_seq_done = 0x40021334 ); -PROVIDE ( r_lc_detach = 0x4002037c ); -PROVIDE ( r_lc_dhkey = 0x4001d564 ); -PROVIDE ( r_lc_enc_cmp = 0x4001d8bc ); -PROVIDE ( r_lc_enc_key_refresh = 0x4001d720 ); -PROVIDE ( r_lc_end_chk_colli = 0x4001d858 ); -PROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 ); -PROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 ); -PROVIDE ( r_lc_epr_change_lk = 0x4001db38 ); -PROVIDE ( r_lc_epr_cmp = 0x4001da88 ); -PROVIDE ( r_lc_epr_resp = 0x4001e0b4 ); -PROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 ); -PROVIDE ( r_lc_ext_feat = 0x40020d6c ); -PROVIDE ( r_lc_feat = 0x40020984 ); -PROVIDE ( r_lc_hl_connect = 0x400209e8 ); -PROVIDE ( r_lc_init = 0x4001c948 ); -PROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 ); -PROVIDE ( r_lc_initiator_epr = 0x4001e064 ); -PROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 ); -PROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 ); -PROVIDE ( r_lc_key_exch_end = 0x4001e140 ); -PROVIDE ( r_lc_legacy_pair = 0x4001e1c0 ); -PROVIDE ( r_lc_local_switch = 0x4001e22c ); -PROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 ); -PROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 ); -PROVIDE ( r_lc_loc_auth = 0x40020ecc ); -PROVIDE ( r_lc_locepr_lkref = 0x4001d648 ); -PROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 ); -PROVIDE ( r_lc_loc_sniff = 0x40020a6c ); -PROVIDE ( r_lc_max_slot_mgt = 0x4001e410 ); -PROVIDE ( r_lc_mst_key = 0x4001e7c0 ); -PROVIDE ( r_lc_mst_qos_done = 0x4001ea80 ); -PROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 ); -PROVIDE ( r_lc_mutual_auth_end = 0x4001e670 ); -PROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 ); -PROVIDE ( r_lc_packet_type = 0x40021038 ); -PROVIDE ( r_lc_pair = 0x40020ddc ); -PROVIDE ( r_lc_pairing_cont = 0x4001eafc ); -PROVIDE ( r_lc_passkey_comm = 0x4001ed20 ); -PROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 ); -PROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec ); -PROVIDE ( r_lc_ptt = 0x4001ee2c ); -PROVIDE ( r_lc_ptt_cmp = 0x4001eeec ); -PROVIDE ( r_lc_qos_setup = 0x4001ef50 ); -PROVIDE ( r_lc_rd_rem_name = 0x4001efd0 ); -PROVIDE ( r_lc_release = 0x4001f8a8 ); -PROVIDE ( r_lc_rem_enc = 0x4001f124 ); -PROVIDE ( r_lc_rem_name_cont = 0x4001f290 ); -PROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 ); -PROVIDE ( r_lc_rem_sniff = 0x40020ca4 ); -PROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 ); -PROVIDE ( r_lc_rem_switch = 0x4001f070 ); -PROVIDE ( r_lc_rem_trans_mode = 0x4001f314 ); -PROVIDE ( r_lc_rem_unsniff = 0x400207a0 ); -PROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c ); -PROVIDE ( r_lc_reset = 0x4001c99c ); -PROVIDE ( r_lc_resp_auth = 0x4001f518 ); -PROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 ); -PROVIDE ( r_lc_resp_num_comp = 0x40020074 ); -PROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 ); -PROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c ); -PROVIDE ( r_lc_resp_pair = 0x400208a4 ); -PROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 ); -PROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c ); -PROVIDE ( r_lc_restart_enc = 0x4001f8ec ); -PROVIDE ( r_lc_restart_enc_cont = 0x4001f940 ); -PROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 ); -PROVIDE ( r_lc_restore_to = 0x4001f9e0 ); -PROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 ); -PROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 ); -PROVIDE ( r_lc_rsw_done = 0x4001db94 ); -PROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 ); -PROVIDE ( r_lc_sco_detach = 0x40021e40 ); -PROVIDE ( r_lc_sco_host_accept = 0x40022118 ); -PROVIDE ( r_lc_sco_host_reject = 0x400222b8 ); -PROVIDE ( r_lc_sco_host_request = 0x40021f4c ); -PROVIDE ( r_lc_sco_host_request_disc = 0x4002235c ); -PROVIDE ( r_lc_sco_init = 0x40021dc8 ); -PROVIDE ( r_lc_sco_peer_accept = 0x40022780 ); -PROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 ); -PROVIDE ( r_lc_sco_peer_reject = 0x40022824 ); -PROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c ); -PROVIDE ( r_lc_sco_peer_request = 0x4002240c ); -PROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec ); -PROVIDE ( r_lc_sco_release = 0x40021eec ); -PROVIDE ( r_lc_sco_reset = 0x40021dfc ); -PROVIDE ( r_lc_sco_timeout = 0x40022bd4 ); -PROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec ); -PROVIDE ( r_lc_semi_key_cmp = 0x40020294 ); -PROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c ); -PROVIDE ( r_lc_send_enc_mode = 0x40020220 ); -PROVIDE ( r_lc_send_lmp = 0x4001c1a8 ); -PROVIDE ( r_lc_send_pdu_acc = 0x4001c21c ); -PROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 ); -PROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 ); -PROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 ); -PROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c ); -PROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 ); -PROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 ); -PROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 ); -PROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 ); -PROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 ); -PROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 ); -PROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 ); -PROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec ); -PROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 ); -PROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 ); -PROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c ); -PROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c ); -PROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 ); -PROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec ); -PROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c ); -PROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 ); -PROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 ); -PROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 ); -PROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 ); -PROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 ); -PROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c ); -PROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 ); -PROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 ); -PROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 ); -PROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 ); -PROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 ); -PROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 ); -PROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 ); -PROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 ); -PROVIDE ( r_lc_send_pdu_sres = 0x4001c548 ); -PROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc ); -PROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 ); -PROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 ); -PROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 ); -PROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc ); -PROVIDE ( r_lc_sniff_init = 0x40022cac ); -PROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 ); -PROVIDE ( r_lc_sniff_reset = 0x40022cc8 ); -PROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 ); -PROVIDE ( r_lc_sniff_sub_mode = 0x400204fc ); -PROVIDE ( r_lc_sp_end = 0x400213a8 ); -PROVIDE ( r_lc_sp_fail = 0x40020470 ); -PROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc ); -PROVIDE ( r_lc_ssr_nego = 0x4002125c ); -PROVIDE ( r_lc_start = 0x4001ca28 ); -PROVIDE ( r_lc_start_enc = 0x4001fb28 ); -PROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c ); -PROVIDE ( r_lc_start_key_exch = 0x4001fe10 ); -PROVIDE ( r_lc_start_lmp_to = 0x4001fae8 ); -PROVIDE ( r_lc_start_oob = 0x4001fffc ); -PROVIDE ( r_lc_start_passkey = 0x4001feac ); -PROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 ); -PROVIDE ( r_lc_stop_afh_report = 0x40020184 ); -PROVIDE ( r_lc_stop_enc = 0x40020110 ); -PROVIDE ( r_lc_switch_cmp = 0x40020448 ); -PROVIDE ( r_lc_unit_key_svr = 0x400206d8 ); -PROVIDE ( r_lc_unsniff = 0x40020c50 ); -PROVIDE ( r_lc_unsniff_cmp = 0x40020810 ); -PROVIDE ( r_lc_unsniff_cont = 0x40020750 ); -PROVIDE ( r_lc_upd_to = 0x4002065c ); -PROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 ); -PROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac ); -PROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 ); -PROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c ); -PROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 ); -PROVIDE ( r_lc_version = 0x40020a30 ); -PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 ); -PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 ); -PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 ); -PROVIDE ( r_ld_acl_afh_set = 0x40036b60 ); -PROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 ); -PROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 ); -PROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 ); -PROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 ); -PROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 ); -PROVIDE ( r_ld_acl_clk_set = 0x40036950 ); -PROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 ); -PROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 ); -PROVIDE ( r_ld_acl_data_flush = 0x400357bc ); -PROVIDE ( r_ld_acl_data_tx = 0x4003544c ); -PROVIDE ( r_ld_acl_edr_set = 0x4003678c ); -PROVIDE ( r_ld_acl_enc_key_load = 0x40036404 ); -PROVIDE ( r_ld_acl_flow_off = 0x40035400 ); -PROVIDE ( r_ld_acl_flow_on = 0x4003541c ); -PROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c ); -PROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 ); -PROVIDE ( r_ld_acl_init = 0x40034d08 ); -PROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 ); -PROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 ); -PROVIDE ( r_ld_acl_lsto_get = 0x400366b4 ); -PROVIDE ( r_ld_acl_lsto_set = 0x400366f8 ); -PROVIDE ( r_ld_acl_reset = 0x40034d24 ); -PROVIDE ( r_ld_acl_role_get = 0x40036b30 ); -PROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 ); -PROVIDE ( r_ld_acl_rsw_req = 0x40035e74 ); -PROVIDE ( r_ld_acl_rx_enc = 0x40036344 ); -PROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 ); -PROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 ); -PROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c ); -PROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 ); -PROVIDE ( r_ld_acl_sniff = 0x4003617c ); -PROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 ); -PROVIDE ( r_ld_acl_ssr_set = 0x40036274 ); -PROVIDE ( r_ld_acl_start = 0x40034ddc ); -PROVIDE ( r_ld_acl_stop = 0x4003532c ); -PROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 ); -PROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c ); -PROVIDE ( r_ld_acl_t_poll_get = 0x40036024 ); -PROVIDE ( r_ld_acl_t_poll_set = 0x40036068 ); -PROVIDE ( r_ld_acl_tx_enc = 0x400362f8 ); -PROVIDE ( r_ld_acl_unsniff = 0x400361e0 ); -PROVIDE ( r_ld_active_check = 0x4003cac4 ); -PROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec ); -PROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c ); -PROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 ); -PROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc ); -PROVIDE ( r_ld_bcst_acl_start = 0x4003882c ); -PROVIDE ( r_ld_bcst_afh_update = 0x40038f3c ); -PROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c ); -PROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 ); -PROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 ); -PROVIDE ( r_ld_bd_addr_get = 0x4003ca20 ); -PROVIDE ( r_ld_channel_assess = 0x4003c184 ); -PROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 ); -PROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 ); -PROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 ); -PROVIDE ( r_ld_csb_rx_init = 0x40039690 ); -PROVIDE ( r_ld_csb_rx_reset = 0x4003969c ); -PROVIDE ( r_ld_csb_rx_start = 0x4003972c ); -PROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 ); -PROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc ); -PROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c ); -PROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 ); -PROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 ); -PROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 ); -PROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 ); -PROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 ); -PROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 ); -PROVIDE ( r_ld_fm_frame_isr = 0x4003a82c ); -PROVIDE ( r_ld_fm_init = 0x4003a760 ); -PROVIDE ( r_ld_fm_prog_check = 0x4003ab28 ); -PROVIDE ( r_ld_fm_prog_disable = 0x4003a984 ); -PROVIDE ( r_ld_fm_prog_enable = 0x4003a944 ); -PROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 ); -PROVIDE ( r_ld_fm_reset = 0x4003a794 ); -PROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 ); -PROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 ); -PROVIDE ( r_ld_init = 0x4003c294 ); -PROVIDE ( r_ld_inq_init = 0x4003b15c ); -PROVIDE ( r_ld_inq_reset = 0x4003b168 ); -PROVIDE ( r_ld_inq_start = 0x4003b1f0 ); -PROVIDE ( r_ld_inq_stop = 0x4003b4f0 ); -PROVIDE ( r_ld_iscan_eir_get = 0x4003c118 ); -PROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 ); -PROVIDE ( r_ld_iscan_init = 0x4003b9f0 ); -PROVIDE ( r_ld_iscan_reset = 0x4003ba14 ); -PROVIDE ( r_ld_iscan_restart = 0x4003ba44 ); -PROVIDE ( r_ld_iscan_start = 0x4003bb28 ); -PROVIDE ( r_ld_iscan_stop = 0x4003bf1c ); -PROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 ); -PROVIDE ( r_ld_page_init = 0x4003d808 ); -PROVIDE ( r_ld_page_reset = 0x4003d814 ); -PROVIDE ( r_ld_page_start = 0x4003d848 ); -PROVIDE ( r_ld_page_stop = 0x4003da54 ); -PROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 ); -PROVIDE ( r_ld_pca_init = 0x4003deb4 ); -PROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac ); -PROVIDE ( r_ld_pca_local_config = 0x4003df6c ); -PROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 ); -PROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 ); -PROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 ); -PROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 ); -PROVIDE ( r_ld_pca_reset = 0x4003df0c ); -PROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 ); -PROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 ); -PROVIDE ( r_ld_pscan_init = 0x4003f474 ); -PROVIDE ( r_ld_pscan_reset = 0x4003f498 ); -PROVIDE ( r_ld_pscan_restart = 0x4003f4b8 ); -PROVIDE ( r_ld_pscan_start = 0x4003f514 ); -PROVIDE ( r_ld_pscan_stop = 0x4003f618 ); -PROVIDE ( r_ld_read_clock = 0x4003c9e4 ); -PROVIDE ( r_ld_reset = 0x4003c714 ); -PROVIDE ( r_ld_sched_acl_add = 0x4003f978 ); -PROVIDE ( r_ld_sched_acl_remove = 0x4003f99c ); -PROVIDE ( r_ld_sched_compute = 0x4003f6f8 ); -PROVIDE ( r_ld_sched_init = 0x4003f7ac ); -PROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 ); -PROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 ); -PROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 ); -PROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 ); -PROVIDE ( r_ld_sched_page_add = 0x4003f910 ); -PROVIDE ( r_ld_sched_page_remove = 0x4003f938 ); -PROVIDE ( r_ld_sched_pscan_add = 0x4003f828 ); -PROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 ); -PROVIDE ( r_ld_sched_reset = 0x4003f7d4 ); -PROVIDE ( r_ld_sched_sco_add = 0x4003fa4c ); -PROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c ); -PROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 ); -PROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c ); -PROVIDE ( r_ld_sched_sscan_add = 0x4003f868 ); -PROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 ); -PROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 ); -PROVIDE ( r_ld_sco_data_tx = 0x40037ee8 ); -PROVIDE ( r_ld_sco_start = 0x40037110 ); -PROVIDE ( r_ld_sco_stop = 0x40037c40 ); -PROVIDE ( r_ld_sco_update = 0x40037a74 ); -PROVIDE ( r_ld_sscan_activated = 0x4004031c ); -PROVIDE ( r_ld_sscan_init = 0x400402f0 ); -PROVIDE ( r_ld_sscan_reset = 0x400402fc ); -PROVIDE ( r_ld_sscan_start = 0x40040384 ); -PROVIDE ( r_ld_strain_init = 0x400409f4 ); -PROVIDE ( r_ld_strain_reset = 0x40040a00 ); -PROVIDE ( r_ld_strain_start = 0x40040a8c ); -PROVIDE ( r_ld_strain_stop = 0x40040df0 ); -PROVIDE ( r_ld_timing_accuracy_get = 0x4003caac ); -PROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c ); -PROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 ); -PROVIDE ( r_ld_util_bch_create = 0x40040fcc ); -PROVIDE ( r_ld_util_fhs_pk = 0x400411c8 ); -PROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 ); -PROVIDE ( r_ld_util_stp_pk = 0x400413f4 ); -PROVIDE ( r_ld_util_stp_unpk = 0x40041324 ); -PROVIDE ( r_ld_version_get = 0x4003ca6c ); -PROVIDE ( r_ld_wlcoex_set = 0x4003caf8 ); -PROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 ); -PROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c ); -PROVIDE ( r_llc_ch_assess_local = 0x40041494 ); -PROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 ); -PROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 ); -PROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac ); -PROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 ); -PROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c ); -PROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 ); -PROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c ); -PROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 ); -PROVIDE ( r_llc_con_update_complete_send = 0x40044d68 ); -PROVIDE ( r_llc_con_update_finished = 0x4004518c ); -PROVIDE ( r_llc_con_update_ind = 0x40045038 ); -PROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 ); -PROVIDE ( r_llc_end_evt_defer = 0x40046330 ); -PROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c ); -PROVIDE ( r_llc_init = 0x40044778 ); -PROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 ); -PROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 ); -PROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc ); -PROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 ); -PROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 ); -PROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 ); -PROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 ); -PROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 ); -PROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 ); -PROVIDE ( r_llc_llcp_get_autorize = 0x4004475c ); -PROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 ); -PROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac ); -PROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 ); -PROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 ); -PROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c ); -PROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 ); -PROVIDE ( r_llc_llcp_recv_handler = 0x40044678 ); -PROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c ); -PROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c ); -PROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 ); -PROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 ); -PROVIDE ( r_llc_llcp_tester_send = 0x400445e4 ); -PROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 ); -PROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c ); -PROVIDE ( r_llc_lsto_con_update = 0x40045098 ); -PROVIDE ( r_llc_ltk_req_send = 0x40044dc0 ); -PROVIDE ( r_llc_map_update_finished = 0x40045260 ); -PROVIDE ( r_llc_map_update_ind = 0x400450f0 ); -PROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc ); -PROVIDE ( r_llc_pdu_defer = 0x40046528 ); -PROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac ); -PROVIDE ( r_llc_reset = 0x400447b8 ); -PROVIDE ( r_llc_start = 0x400447f4 ); -PROVIDE ( r_llc_stop = 0x400449ac ); -PROVIDE ( r_llc_util_bw_mgt = 0x4004629c ); -PROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 ); -PROVIDE ( r_llc_util_dicon_procedure = 0x40046130 ); -PROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 ); -PROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 ); -PROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 ); -PROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 ); -PROVIDE ( r_llc_util_update_channel_map = 0x400461ac ); -PROVIDE ( r_llc_version_rd_event_send = 0x40044e60 ); -PROVIDE ( r_lld_adv_start = 0x40048b38 ); -PROVIDE ( r_lld_adv_stop = 0x40048ea0 ); -PROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 ); -PROVIDE ( r_lld_con_param_req = 0x40049f0c ); -PROVIDE ( r_lld_con_param_rsp = 0x40049e00 ); -PROVIDE ( r_lld_con_start = 0x400491f8 ); -PROVIDE ( r_lld_con_stop = 0x40049fdc ); -PROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc ); -PROVIDE ( r_lld_con_update_ind = 0x4004a30c ); -PROVIDE ( r_lld_con_update_req = 0x40049b60 ); -PROVIDE ( r_lld_core_reset = 0x40048a9c ); -PROVIDE ( r_lld_crypt_isr = 0x4004a324 ); -PROVIDE ( r_lld_evt_adv_create = 0x400481f4 ); -PROVIDE ( r_lld_evt_canceled = 0x400485c8 ); -PROVIDE ( r_lld_evt_channel_next = 0x40046aac ); -PROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc ); -PROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 ); -PROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c ); -PROVIDE ( r_lld_evt_drift_compute = 0x40047670 ); -PROVIDE ( r_lld_evt_elt_delete = 0x40047538 ); -PROVIDE ( r_lld_evt_elt_insert = 0x400474c8 ); -PROVIDE ( r_lld_evt_end = 0x400483e8 ); -PROVIDE ( r_lld_evt_end_isr = 0x4004862c ); -PROVIDE ( r_lld_evt_init = 0x40046b3c ); -PROVIDE ( r_lld_evt_init_evt = 0x40046cd0 ); -PROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 ); -PROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 ); -PROVIDE ( r_lld_evt_prevent_stop = 0x40047adc ); -PROVIDE ( r_lld_evt_restart = 0x40046d50 ); -PROVIDE ( r_lld_evt_rx = 0x40048578 ); -PROVIDE ( r_lld_evt_rx_isr = 0x40048678 ); -PROVIDE ( r_lld_evt_scan_create = 0x40047ae8 ); -PROVIDE ( r_lld_evt_schedule = 0x40047908 ); -PROVIDE ( r_lld_evt_schedule_next = 0x400477dc ); -PROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 ); -PROVIDE ( r_lld_evt_slave_update = 0x40048138 ); -PROVIDE ( r_lld_evt_update_create = 0x40047cd8 ); -PROVIDE ( r_lld_get_mode = 0x40049ff8 ); -PROVIDE ( r_lld_init = 0x4004873c ); -PROVIDE ( r_lld_move_to_master = 0x400499e0 ); -PROVIDE ( r_lld_move_to_slave = 0x4004a024 ); -PROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 ); -PROVIDE ( r_lld_pdu_check = 0x4004ac34 ); -PROVIDE ( r_lld_pdu_data_send = 0x4004b018 ); -PROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc ); -PROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 ); -PROVIDE ( r_lld_pdu_send_packet = 0x4004b774 ); -PROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 ); -PROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 ); -PROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 ); -PROVIDE ( r_lld_pdu_tx_push = 0x4004b080 ); -PROVIDE ( r_lld_ral_renew_req = 0x4004a73c ); -/**************************************************************************** - * boards/xtensa/elf32-core/scripts/esp32_rom.ld - ****************************************************************************/ - -PROVIDE ( r_lld_scan_start = 0x40048ee0 ); -PROVIDE ( r_lld_scan_stop = 0x40049190 ); -PROVIDE ( r_lld_test_mode_rx = 0x4004a540 ); -PROVIDE ( r_lld_test_mode_tx = 0x4004a350 ); -PROVIDE ( r_lld_test_stop = 0x4004a710 ); -PROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc ); -PROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c ); -PROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 ); -PROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 ); -PROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 ); -PROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 ); -PROVIDE ( r_lld_util_flush_list = 0x4004bbd8 ); -PROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 ); -PROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac ); -PROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 ); -PROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 ); -PROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 ); -PROVIDE ( r_lld_util_instant_get = 0x4004b890 ); -PROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc ); -PROVIDE ( r_lld_util_priority_set = 0x4004bd10 ); -PROVIDE ( r_lld_util_priority_update = 0x4004bd78 ); -PROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 ); -PROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 ); -PROVIDE ( r_lld_wlcoex_set = 0x4004bd98 ); -PROVIDE ( r_llm_ble_ready = 0x4004cc34 ); -PROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 ); -PROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 ); -PROVIDE ( r_llm_con_req_ind = 0x4004cc54 ); -PROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 ); -PROVIDE ( r_llm_create_con = 0x4004de78 ); -PROVIDE ( r_llm_encryption_done = 0x4004dff8 ); -PROVIDE ( r_llm_encryption_start = 0x4004e128 ); -PROVIDE ( r_llm_end_evt_defer = 0x4004eb6c ); -PROVIDE ( r_llm_init = 0x4004c9f8 ); -PROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 ); -PROVIDE ( r_llm_pdu_defer = 0x4004ec48 ); -PROVIDE ( r_llm_ral_clear = 0x4004e1fc ); -PROVIDE ( r_llm_ral_dev_add = 0x4004e23c ); -PROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc ); -PROVIDE ( r_llm_ral_get_rpa = 0x4004e400 ); -PROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 ); -PROVIDE ( r_llm_ral_update = 0x4004e4f8 ); -PROVIDE ( r_llm_set_adv_data = 0x4004d960 ); -PROVIDE ( r_llm_set_adv_en = 0x4004d7ec ); -PROVIDE ( r_llm_set_adv_param = 0x4004d5f4 ); -PROVIDE ( r_llm_set_scan_en = 0x4004db64 ); -PROVIDE ( r_llm_set_scan_param = 0x4004dac8 ); -PROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 ); -PROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 ); -PROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc ); -PROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc ); -PROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 ); -PROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 ); -PROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 ); -PROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 ); -PROVIDE ( r_llm_util_bl_add = 0x4004e9ac ); -PROVIDE ( r_llm_util_bl_check = 0x4004e930 ); -PROVIDE ( r_llm_util_bl_rem = 0x4004ea70 ); -PROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 ); -PROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 ); -PROVIDE ( r_llm_util_check_map_validity = 0x4004e800 ); -PROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 ); -PROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 ); -PROVIDE ( r_llm_util_set_public_addr = 0x4004e89c ); -PROVIDE ( r_llm_wl_clr = 0x4004dc54 ); -PROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 ); -PROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 ); -PROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc ); -PROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 ); -PROVIDE ( r_lm_acl_disc = 0x4004f148 ); -PROVIDE ( r_LM_AddSniff = 0x40022d20 ); -PROVIDE ( r_lm_add_sync = 0x40051358 ); -PROVIDE ( r_lm_afh_activate_timer = 0x4004f444 ); -PROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 ); -PROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 ); -PROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c ); -PROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 ); -PROVIDE ( r_lm_check_active_sync = 0x40051334 ); -PROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c ); -PROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 ); -PROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c ); -PROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 ); -PROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 ); -PROVIDE ( r_LM_ComputePacketType = 0x4002f554 ); -PROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac ); -PROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 ); -PROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 ); -PROVIDE ( r_lm_dhkey_calc_init = 0x40013234 ); -PROVIDE ( r_lm_dhkey_compare = 0x400132d8 ); -PROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec ); -PROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 ); -PROVIDE ( r_lm_f1 = 0x40012bb8 ); -PROVIDE ( r_lm_f2 = 0x40012cfc ); -PROVIDE ( r_lm_f3 = 0x40013050 ); -PROVIDE ( r_lm_g = 0x40012f90 ); -PROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c ); -PROVIDE ( r_lm_get_auth_en = 0x4004f1ac ); -PROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c ); -PROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 ); -PROVIDE ( r_LM_GetFeature = 0x4002f924 ); -PROVIDE ( r_LM_GetLinkTimeout = 0x400233ec ); -PROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 ); -PROVIDE ( r_lm_get_loopback_mode = 0x4004f248 ); -PROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c ); -PROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 ); -PROVIDE ( r_LM_GetMasterKey = 0x4001b260 ); -PROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 ); -PROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 ); -PROVIDE ( r_lm_get_nb_acl = 0x4004ef9c ); -PROVIDE ( r_lm_get_nb_sync_link = 0x4005179c ); -PROVIDE ( r_lm_get_nonce = 0x400131c4 ); -PROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 ); -PROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 ); -PROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 ); -PROVIDE ( r_LM_GetPINType = 0x4004f1e8 ); -PROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 ); -PROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 ); -PROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 ); -PROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 ); -PROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 ); -PROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 ); -PROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c ); -PROVIDE ( r_lm_get_sp_en = 0x4004f1c0 ); -PROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 ); -PROVIDE ( r_lm_get_synchdl = 0x4005175c ); -PROVIDE ( r_lm_get_sync_param = 0x400503b4 ); -PROVIDE ( r_lm_init = 0x4004ed34 ); -PROVIDE ( r_lm_init_sync = 0x400512d8 ); -PROVIDE ( r_lm_is_acl_con = 0x4004f47c ); -PROVIDE ( r_lm_is_acl_con_role = 0x4004f49c ); -PROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 ); -PROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 ); -PROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 ); -PROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 ); -PROVIDE ( r_lm_look_for_sync = 0x40051774 ); -PROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c ); -PROVIDE ( r_lm_lt_addr_free = 0x4004ef74 ); -PROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 ); -PROVIDE ( r_LM_MakeCof = 0x4002f84c ); -PROVIDE ( r_LM_MakeRandVec = 0x400112d8 ); -PROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 ); -PROVIDE ( r_LM_MaxSlot = 0x4002f694 ); -PROVIDE ( r_lm_modif_sync = 0x40051578 ); -PROVIDE ( r_lm_n_is_zero = 0x40012170 ); -PROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 ); -PROVIDE ( r_lm_oob_f1 = 0x40012e54 ); -PROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 ); -PROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 ); -PROVIDE ( r_lmp_pack = 0x4001135c ); -PROVIDE ( r_lmp_unpack = 0x4001149c ); -PROVIDE ( r_lm_read_features = 0x4004f0d8 ); -PROVIDE ( r_LM_RemoveSniff = 0x40023124 ); -PROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 ); -PROVIDE ( r_lm_remove_sync = 0x400517c8 ); -PROVIDE ( r_lm_reset_sync = 0x40051304 ); -PROVIDE ( r_lm_role_switch_finished = 0x4004f028 ); -PROVIDE ( r_lm_role_switch_start = 0x4004efe0 ); -PROVIDE ( r_lm_sco_nego_end = 0x40051828 ); -PROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 ); -PROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 ); -PROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc ); -PROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 ); -PROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 ); -PROVIDE ( r_lm_sp_n_one = 0x400123a4 ); -PROVIDE ( r_lm_sp_p192_add = 0x40012828 ); -PROVIDE ( r_lm_sp_p192_dbl = 0x4001268c ); -PROVIDE ( r_lm_sp_p192_invert = 0x40012b6c ); -PROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 ); -PROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 ); -PROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 ); -PROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 ); -PROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 ); -PROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 ); -PROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 ); -PROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 ); -PROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 ); -PROVIDE ( r_modules_funcs = 0x3ffafd6c ); -PROVIDE ( r_modules_funcs_p = 0x3ffafd68 ); -PROVIDE ( r_nvds_del = 0x400544c4 ); -PROVIDE ( r_nvds_get = 0x40054488 ); -PROVIDE ( r_nvds_init = 0x40054410 ); -PROVIDE ( r_nvds_lock = 0x400544fc ); -PROVIDE ( r_nvds_put = 0x40054534 ); -PROVIDE ( rom_abs_temp = 0x400054f0 ); -PROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c ); -PROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac ); -PROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 ); -PROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 ); -PROVIDE ( rom_bb_wdg_test_en = 0x40003b70 ); -PROVIDE ( rom_cbw2040_cfg = 0x400040b0 ); -PROVIDE ( rom_check_noise_floor = 0x40003c78 ); -PROVIDE ( rom_chip_i2c_readReg = 0x40004110 ); -PROVIDE ( rom_chip_i2c_writeReg = 0x40004168 ); -PROVIDE ( rom_chip_v7_bt_init = 0x40004d8c ); -PROVIDE ( rom_chip_v7_rx_init = 0x40004cec ); -PROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 ); -PROVIDE ( rom_chip_v7_tx_init = 0x40004d18 ); -PROVIDE ( rom_clk_force_on_vit = 0x40003710 ); -PROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 ); -PROVIDE ( rom_dc_iq_est = 0x400055c8 ); -PROVIDE ( rom_disable_agc = 0x40002fa4 ); -PROVIDE ( rom_enable_agc = 0x40002fcc ); -PROVIDE ( rom_en_pwdet = 0x4000506c ); -PROVIDE ( rom_gen_rx_gain_table = 0x40003e3c ); -PROVIDE ( rom_get_data_sat = 0x4000312c ); -PROVIDE ( rom_get_fm_sar_dout = 0x40005204 ); -PROVIDE ( rom_get_power_db = 0x40005fc8 ); -PROVIDE ( rom_get_pwctrl_correct = 0x400065d4 ); -PROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc ); -PROVIDE ( rom_get_rf_gain_qdb = 0x40006290 ); -PROVIDE ( rom_get_sar_dout = 0x40006564 ); -PROVIDE ( rom_i2c_readreg = 0x40004148 ); -PROVIDE ( rom_i2c_readreg_Mask = 0x400041c0 ); -PROVIDE ( rom_i2c_writereg = 0x400041a4 ); -PROVIDE ( rom_i2c_writereg_Mask = 0x400041fc ); -PROVIDE ( rom_index_to_txbbgain = 0x40004df8 ); -PROVIDE ( rom_iq_est_disable = 0x40005590 ); -PROVIDE ( rom_iq_est_enable = 0x40005514 ); -PROVIDE ( rom_linear_to_db = 0x40005f64 ); -PROVIDE ( rom_loopback_mode_en = 0x400030f8 ); -PROVIDE ( rom_main = 0x400076c4 ); -PROVIDE ( rom_meas_tone_pwr_db = 0x40006004 ); -PROVIDE ( rom_mhz2ieee = 0x4000404c ); -PROVIDE ( rom_noise_floor_auto_set = 0x40003bdc ); -PROVIDE ( rom_pbus_debugmode = 0x40004458 ); -PROVIDE ( rom_pbus_force_mode = 0x40004270 ); -PROVIDE ( rom_pbus_force_test = 0x400043c0 ); -PROVIDE ( rom_pbus_rd = 0x40004414 ); -PROVIDE ( rom_pbus_rd_addr = 0x40004334 ); -PROVIDE ( rom_pbus_rd_shift = 0x40004374 ); -PROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 ); -PROVIDE ( rom_pbus_set_dco = 0x40004638 ); -PROVIDE ( rom_pbus_set_rxgain = 0x40004480 ); -PROVIDE ( rom_pbus_workmode = 0x4000446c ); -PROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 ); -PROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c ); -PROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 ); -PROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 ); -PROVIDE ( rom_phy_disable_agc = 0x40002f6c ); -PROVIDE ( rom_phy_disable_cca = 0x40003000 ); -PROVIDE ( rom_phy_enable_agc = 0x40002f88 ); -PROVIDE ( rom_phy_enable_cca = 0x4000302c ); -PROVIDE ( rom_phy_freq_correct = 0x40004b44 ); -PROVIDE ( rom_phyFuns = 0x3ffae0c0 ); -PROVIDE ( rom_phy_get_noisefloor = 0x40003c2c ); -PROVIDE ( rom_phy_get_vdd33 = 0x4000642c ); -PROVIDE ( rom_pow_usr = 0x40003044 ); -PROVIDE ( rom_read_sar_dout = 0x400051c0 ); -PROVIDE ( rom_restart_cal = 0x400046e0 ); -PROVIDE ( rom_rfcal_pwrctrl = 0x40006058 ); -PROVIDE ( rom_rfcal_rxiq = 0x40005b4c ); -PROVIDE ( rom_rfcal_txcap = 0x40005dec ); -PROVIDE ( rom_rfpll_reset = 0x40004680 ); -PROVIDE ( rom_rfpll_set_freq = 0x400047f8 ); -PROVIDE ( rom_rtc_mem_backup = 0x40003db4 ); -PROVIDE ( rom_rtc_mem_recovery = 0x40003df4 ); -PROVIDE ( rom_rx_gain_force = 0x4000351c ); -PROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 ); -PROVIDE ( rom_rxiq_get_mis = 0x400058e4 ); -PROVIDE ( rom_rxiq_set_reg = 0x40005a00 ); -PROVIDE ( rom_set_cal_rxdc = 0x400030b8 ); -PROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 ); -PROVIDE ( rom_set_channel_freq = 0x40004880 ); -PROVIDE ( rom_set_loopback_gain = 0x40003060 ); -PROVIDE ( rom_set_noise_floor = 0x40003d48 ); -PROVIDE ( rom_set_pbus_mem = 0x400031a4 ); -PROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 ); -PROVIDE ( rom_set_rxclk_en = 0x40003594 ); -PROVIDE ( rom_set_txcap_reg = 0x40005d50 ); -PROVIDE ( rom_set_txclk_en = 0x40003564 ); -PROVIDE ( rom_spur_coef_cfg = 0x40003ac8 ); -PROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 ); -PROVIDE ( rom_start_tx_tone = 0x400036b4 ); -PROVIDE ( rom_start_tx_tone_step = 0x400035d0 ); -PROVIDE ( rom_stop_tx_tone = 0x40003f98 ); -PROVIDE ( _rom_store = 0x4000d66c ); -PROVIDE ( _rom_store_table = 0x4000d4f8 ); -PROVIDE ( rom_target_power_add_backoff = 0x40006268 ); -PROVIDE ( rom_tx_atten_set_interp = 0x400061cc ); -PROVIDE ( rom_txbbgain_to_index = 0x40004dc0 ); -PROVIDE ( rom_txcal_work_mode = 0x4000510c ); -PROVIDE ( rom_txdc_cal_init = 0x40004e10 ); -PROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 ); -PROVIDE ( rom_txiq_cover = 0x4000538c ); -PROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc ); -PROVIDE ( rom_txiq_set_reg = 0x40005154 ); -PROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c ); -PROVIDE ( rom_txtone_linear_pwr = 0x40005290 ); -PROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 ); -PROVIDE ( rom_write_gain_mem = 0x4000348c ); -PROVIDE ( rom_write_rfpll_sdm = 0x40004740 ); -PROVIDE ( roundup2 = 0x4000ab7c ); -PROVIDE ( r_plf_funcs_p = 0x3ffb8360 ); -PROVIDE ( r_rf_rw_bt_init = 0x40054868 ); -PROVIDE ( r_rf_rw_init = 0x40054b0c ); -PROVIDE ( r_rf_rw_le_init = 0x400549d0 ); -PROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c ); -PROVIDE ( r_rwble_init = 0x40054bf4 ); -PROVIDE ( r_rwble_isr = 0x40054e08 ); -PROVIDE ( r_rwble_reset = 0x40054ce8 ); -PROVIDE ( r_rwble_sleep_check = 0x40054d78 ); -PROVIDE ( r_rwble_version = 0x40054dac ); -PROVIDE ( r_rwbt_init = 0x40055160 ); -PROVIDE ( r_rwbt_isr = 0x40055248 ); -PROVIDE ( r_rwbt_reset = 0x400551bc ); -PROVIDE ( r_rwbt_sleep_check = 0x4005577c ); -PROVIDE ( r_rwbt_sleep_enter = 0x400557a4 ); -PROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc ); -PROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc ); -PROVIDE ( r_rwbt_version = 0x4005520c ); -PROVIDE ( r_rwip_assert_err = 0x40055f88 ); -PROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc ); -PROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c ); -PROVIDE ( r_rwip_init = 0x4005595c ); -PROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 ); -PROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 ); -PROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 ); -PROVIDE ( r_rwip_reset = 0x40055ab8 ); -PROVIDE ( r_rwip_schedule = 0x40055b38 ); -PROVIDE ( r_rwip_sleep = 0x40055b5c ); -PROVIDE ( r_rwip_sleep_enable = 0x40055f30 ); -PROVIDE ( r_rwip_version = 0x40055b20 ); -PROVIDE ( r_rwip_wakeup = 0x40055dc4 ); -PROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c ); -PROVIDE ( r_rwip_wakeup_end = 0x40055e18 ); -PROVIDE ( r_rwip_wlcoex_set = 0x40055f60 ); -PROVIDE ( r_SHA_256 = 0x40013a90 ); -PROVIDE ( rtc_boot_control = 0x4000821c ); -PROVIDE ( rtc_get_reset_reason = 0x400081d4 ); -PROVIDE ( rtc_get_wakeup_cause = 0x400081f4 ); -PROVIDE ( rtc_select_apb_bridge = 0x40008288 ); -PROVIDE ( rwip_coex_cfg = 0x3ff9914c ); -PROVIDE ( rwip_priority = 0x3ff99159 ); -PROVIDE ( rwip_rf = 0x3ffbdb28 ); -PROVIDE ( rwip_rf_p_get = 0x400558f4 ); -PROVIDE ( r_XorKey = 0x400112c0 ); -PROVIDE ( sbrk = 0x400017f4 ); -PROVIDE ( _sbrk_r = 0x4000bce4 ); -PROVIDE ( scanf = 0x40058760 ); -PROVIDE ( _scanf_chars = 0x40058384 ); -PROVIDE ( _scanf_float = 0x4000bf18 ); -PROVIDE ( _scanf_i = 0x4005845c ); -PROVIDE ( _scanf_r = 0x4005879c ); -PROVIDE ( __sccl = 0x4000c498 ); -PROVIDE ( __sclose = 0x400011b8 ); -PROVIDE ( SelectSpiFunction = 0x40061f84 ); -PROVIDE ( SelectSpiQIO = 0x40061ddc ); -PROVIDE ( SendMsg = 0x40009384 ); -PROVIDE ( send_packet = 0x40009340 ); -PROVIDE ( __seofread = 0x40001148 ); -PROVIDE ( setjmp = 0x40056268 ); -PROVIDE ( setlocale = 0x40059568 ); -PROVIDE ( _setlocale_r = 0x4005950c ); -PROVIDE ( set_rtc_memory_crc = 0x40008208 ); -PROVIDE ( SetSpiDrvs = 0x40061e78 ); -PROVIDE ( __sf_fake_stderr = 0x3ff96458 ); -PROVIDE ( __sf_fake_stdin = 0x3ff96498 ); -PROVIDE ( __sf_fake_stdout = 0x3ff96478 ); -PROVIDE ( __sflush_r = 0x400591e0 ); -PROVIDE ( __sfmoreglue = 0x40001dc8 ); -PROVIDE ( __sfp = 0x40001e90 ); -PROVIDE ( __sfp_lock_acquire = 0x40001e08 ); -PROVIDE ( __sfp_lock_release = 0x40001e14 ); -PROVIDE ( __sfputs_r = 0x40057790 ); -PROVIDE ( __sfvwrite_r = 0x4005893c ); -PROVIDE ( sha1_prf = 0x40060ae8 ); -PROVIDE ( sha1_vector = 0x40060b64 ); -PROVIDE ( sha256_prf = 0x40060d70 ); -PROVIDE ( sha256_vector = 0x40060e08 ); -PROVIDE ( sha_blk_bits = 0x3ff99290 ); -PROVIDE ( sha_blk_bits_bytes = 0x3ff99288 ); -PROVIDE ( sha_blk_hash_bytes = 0x3ff9928c ); -PROVIDE ( sig_matrix = 0x3ffae293 ); -PROVIDE ( __sinit = 0x40001e38 ); -PROVIDE ( __sinit_lock_acquire = 0x40001e20 ); -PROVIDE ( __sinit_lock_release = 0x40001e2c ); -PROVIDE ( sip_after_tx_complete = 0x4000b358 ); -PROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c ); -PROVIDE ( sip_get_ptr = 0x4000b34c ); -PROVIDE ( sip_get_state = 0x4000ae2c ); -PROVIDE ( sip_init_attach = 0x4000ae58 ); -PROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 ); -PROVIDE ( sip_install_rx_data_cb = 0x4000ae20 ); -PROVIDE ( sip_is_active = 0x4000b3c0 ); -PROVIDE ( sip_post_init = 0x4000aed8 ); -PROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc ); -PROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c ); -PROVIDE ( siprintf = 0x40056c08 ); -PROVIDE ( _siprintf_r = 0x40056bbc ); -PROVIDE ( sip_send = 0x4000af54 ); -PROVIDE ( sip_to_host_chain_append = 0x4000aef8 ); -PROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 ); -PROVIDE ( siscanf = 0x400587d0 ); -PROVIDE ( _siscanf_r = 0x40058830 ); -PROVIDE ( slc_add_credits = 0x4000baf4 ); -PROVIDE ( slc_enable = 0x4000b64c ); -PROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 ); -PROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 ); -PROVIDE ( slc_has_pkt_to_host = 0x4000b5fc ); -PROVIDE ( slc_init_attach = 0x4000b918 ); -PROVIDE ( slc_init_credit = 0x4000badc ); -PROVIDE ( slc_reattach = 0x4000b62c ); -PROVIDE ( slc_send_to_host_chain = 0x4000b6a0 ); -PROVIDE ( slc_set_host_io_max_window = 0x4000b89c ); -PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 ); -PROVIDE ( __smakebuf_r = 0x40059108 ); -PROVIDE ( sniprintf = 0x40056b4c ); -PROVIDE ( _sniprintf_r = 0x40056ae4 ); -PROVIDE ( snprintf = 0x40056b4c ); -PROVIDE ( _snprintf_r = 0x40056ae4 ); -PROVIDE ( software_reset = 0x4000824c ); -PROVIDE ( software_reset_cpu = 0x40008264 ); -PROVIDE ( specialModP256 = 0x4001600c ); -PROVIDE ( spi_cache_sram_init = 0x400626e4 ); -PROVIDE ( SPIClkConfig = 0x40062bc8 ); -PROVIDE ( SPI_Common_Command = 0x4006246c ); -PROVIDE ( spi_dummy_len_fix = 0x40061d90 ); -PROVIDE ( SPI_Encrypt_Write = 0x40062e78 ); -PROVIDE ( SPIEraseArea = 0x400631ac ); -PROVIDE ( SPIEraseBlock = 0x40062c4c ); -PROVIDE ( SPIEraseChip = 0x40062c14 ); -PROVIDE ( SPIEraseSector = 0x40062ccc ); -PROVIDE ( spi_flash_attach = 0x40062a6c ); -PROVIDE ( SPILock = 0x400628f0 ); -PROVIDE ( SPIMasterReadModeCnfig = 0x40062b64 ); -PROVIDE ( spi_modes = 0x3ff99270 ); -PROVIDE ( SPIParamCfg = 0x40063238 ); -PROVIDE ( SPI_Prepare_Encrypt_Data = 0x40062e1c ); -PROVIDE ( SPIRead = 0x40062ed8 ); -PROVIDE ( SPIReadModeCnfig = 0x40062944 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_read_status = 0x4006226c ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_read_status_high = 0x40062448 ); -PROVIDE ( SPIUnlock = 0x400628b0 ); -PROVIDE ( SPI_user_command_read = 0x400621b0 ); -PROVIDE ( spi_w25q16 = 0x3ffae270 ); -PROVIDE ( SPIWrite = 0x40062d50 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_write_enable = 0x40062320 ); -PROVIDE ( SPI_Write_Encrypt_Disable = 0x40062e60 ); -PROVIDE ( SPI_Write_Encrypt_Enable = 0x40062df4 ); -/* This is static function, but can be used, not generated by script*/ -PROVIDE ( SPI_write_status = 0x400622f0 ); -PROVIDE ( sprintf = 0x40056c08 ); -PROVIDE ( _sprintf_r = 0x40056bbc ); -PROVIDE ( __sprint_r = 0x400577e4 ); -PROVIDE ( srand = 0x40001004 ); -PROVIDE ( __sread = 0x40001118 ); -PROVIDE ( __srefill_r = 0x400593d4 ); -PROVIDE ( sscanf = 0x400587d0 ); -PROVIDE ( _sscanf_r = 0x40058830 ); -PROVIDE ( __sseek = 0x40001184 ); -PROVIDE ( __ssprint_r = 0x40056ff8 ); -PROVIDE ( __ssputs_r = 0x40056f2c ); -PROVIDE ( __ssrefill_r = 0x40057fec ); -PROVIDE ( __ssvfiscanf_r = 0x4005802c ); -PROVIDE ( __ssvfscanf_r = 0x4005802c ); -PROVIDE ( __stack = 0x3ffe3f20 ); -PROVIDE ( __stack_app = 0x3ffe7e30 ); -PROVIDE ( _stack_sentry = 0x3ffe1320 ); -PROVIDE ( _stack_sentry_app = 0x3ffe5230 ); -PROVIDE ( _start = 0x40000704 ); -PROVIDE ( start_tb_console = 0x4005a980 ); -PROVIDE ( _stat_r = 0x4000bcb4 ); -PROVIDE ( _stext = 0x40000560 ); -PROVIDE ( strcasecmp = 0x400011cc ); -PROVIDE ( strcasestr = 0x40001210 ); -PROVIDE ( strcat = 0x4000c518 ); -PROVIDE ( strchr = 0x4000c53c ); -PROVIDE ( strcmp = 0x40001274 ); -PROVIDE ( strcoll = 0x40001398 ); -PROVIDE ( strcpy = 0x400013ac ); -PROVIDE ( strcspn = 0x4000c558 ); -PROVIDE ( strdup = 0x4000143c ); -PROVIDE ( _strdup_r = 0x40001450 ); -PROVIDE ( strftime = 0x40059ab4 ); -PROVIDE ( strlcat = 0x40001470 ); -PROVIDE ( strlcpy = 0x4000c584 ); -PROVIDE ( strlen = 0x400014c0 ); -PROVIDE ( strlwr = 0x40001524 ); -PROVIDE ( strncasecmp = 0x40001550 ); -PROVIDE ( strncat = 0x4000c5c4 ); -PROVIDE ( strncmp = 0x4000c5f4 ); -PROVIDE ( strncpy = 0x400015d4 ); -PROVIDE ( strndup = 0x400016b0 ); -PROVIDE ( _strndup_r = 0x400016c4 ); -PROVIDE ( strnlen = 0x4000c628 ); -PROVIDE ( strrchr = 0x40001708 ); -PROVIDE ( strsep = 0x40001734 ); -PROVIDE ( strspn = 0x4000c648 ); -PROVIDE ( strstr = 0x4000c674 ); -PROVIDE ( __strtok_r = 0x4000c6a8 ); -PROVIDE ( strtok_r = 0x4000c70c ); -PROVIDE ( strtol = 0x4005681c ); -PROVIDE ( _strtol_r = 0x40056714 ); -PROVIDE ( strtoul = 0x4005692c ); -PROVIDE ( _strtoul_r = 0x40056834 ); -PROVIDE ( strupr = 0x4000174c ); -PROVIDE ( __subdf3 = 0x400026e4 ); -PROVIDE ( __submore = 0x40058f3c ); -PROVIDE ( __subsf3 = 0x400021d0 ); -PROVIDE ( SubtractBigHex256 = 0x40015bcc ); -PROVIDE ( SubtractBigHexMod256 = 0x40015e8c ); -PROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c ); -PROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 ); -PROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 ); -PROVIDE ( __subvdi3 = 0x40002d20 ); -PROVIDE ( __subvsi3 = 0x40002cf8 ); -PROVIDE ( _sungetc_r = 0x40057f6c ); -PROVIDE ( _svfiprintf_r = 0x40057100 ); -PROVIDE ( __svfiscanf_r = 0x40057b08 ); -PROVIDE ( _svfprintf_r = 0x40057100 ); -PROVIDE ( __svfscanf = 0x40057f04 ); -PROVIDE ( __svfscanf_r = 0x40057b08 ); -PROVIDE ( __swbuf = 0x40058cb4 ); -PROVIDE ( __swbuf_r = 0x40058bec ); -PROVIDE ( __swrite = 0x40001150 ); -PROVIDE ( __swsetup_r = 0x40058cc8 ); -PROVIDE ( sw_to_hw = 0x3ffb8d40 ); -PROVIDE ( _SyscallException = 0x400007cf ); -PROVIDE ( syscall_table_ptr_app = 0x3ffae020 ); -PROVIDE ( syscall_table_ptr_pro = 0x3ffae024 ); -PROVIDE ( _system_r = 0x4000bc10 ); -PROVIDE ( tdefl_compress = 0x400600bc ); -PROVIDE ( tdefl_compress_buffer = 0x400607f4 ); -PROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 ); -PROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 ); -PROVIDE ( tdefl_get_adler32 = 0x400608d8 ); -PROVIDE ( tdefl_get_prev_return_status = 0x400608d0 ); -PROVIDE ( tdefl_init = 0x40060810 ); -PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c ); -PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 ); -PROVIDE ( time = 0x40001844 ); -PROVIDE ( __time_load_locale = 0x4000183c ); -PROVIDE ( times = 0x40001808 ); -PROVIDE ( _times_r = 0x4000bc40 ); -PROVIDE ( _timezone = 0x3ffae0a0 ); -PROVIDE ( tinfl_decompress = 0x4005ef30 ); -PROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 ); -PROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 ); -PROVIDE ( toascii = 0x4000c720 ); -PROVIDE ( tolower = 0x40001868 ); -PROVIDE ( toupper = 0x40001884 ); -PROVIDE ( __truncdfsf2 = 0x40002b90 ); -PROVIDE ( __tzcalc_limits = 0x400018a0 ); -PROVIDE ( __tz_lock = 0x40001a04 ); -PROVIDE ( _tzname = 0x3ffae030 ); -PROVIDE ( tzset = 0x40001a1c ); -PROVIDE ( _tzset_r = 0x40001a28 ); -PROVIDE ( __tz_unlock = 0x40001a10 ); -PROVIDE ( uartAttach = 0x40008fd0 ); -PROVIDE ( uart_baudrate_detect = 0x40009034 ); -PROVIDE ( uart_buff_switch = 0x400093c0 ); -PROVIDE ( UartConnCheck = 0x40008738 ); -PROVIDE ( UartConnectProc = 0x40008a04 ); -PROVIDE ( UartDev = 0x3ffe019c ); -PROVIDE ( uart_div_modify = 0x400090cc ); -PROVIDE ( UartDwnLdProc = 0x40008ce8 ); -PROVIDE ( UartGetCmdLn = 0x40009564 ); -PROVIDE ( Uart_Init = 0x40009120 ); -PROVIDE ( UartRegReadProc = 0x40008a58 ); -PROVIDE ( UartRegWriteProc = 0x40008a14 ); -PROVIDE ( uart_rx_intr_handler = 0x40008f4c ); -PROVIDE ( uart_rx_one_char = 0x400092d0 ); -PROVIDE ( uart_rx_one_char_block = 0x400092a4 ); -PROVIDE ( uart_rx_readbuff = 0x40009394 ); -PROVIDE ( UartRxString = 0x400092fc ); -PROVIDE ( UartSetBaudProc = 0x40008aac ); -PROVIDE ( UartSpiAttachProc = 0x40008a6c ); -PROVIDE ( UartSpiReadProc = 0x40008a80 ); -PROVIDE ( uart_tx_flush = 0x40009258 ); -PROVIDE ( uart_tx_one_char = 0x40009200 ); -PROVIDE ( uart_tx_one_char2 = 0x4000922c ); -PROVIDE ( uart_tx_switch = 0x40009028 ); -PROVIDE ( uart_tx_wait_idle = 0x40009278 ); -PROVIDE ( __ucmpdi2 = 0x40063840 ); -PROVIDE ( __udivdi3 = 0x4000cff8 ); -PROVIDE ( __udivmoddi4 = 0x40064ab0 ); -PROVIDE ( __udivsi3 = 0x4000c7c8 ); -PROVIDE ( __udiv_w_sdiv = 0x40064aa8 ); -PROVIDE ( __umoddi3 = 0x4000d280 ); -PROVIDE ( __umodsi3 = 0x4000c7d0 ); -PROVIDE ( __umulsidi3 = 0x4000c7d8 ); -PROVIDE ( ungetc = 0x400590f4 ); -PROVIDE ( _ungetc_r = 0x40058fa0 ); -PROVIDE ( _unlink_r = 0x4000bc84 ); -PROVIDE ( __unorddf2 = 0x400637f4 ); -PROVIDE ( __unordsf2 = 0x40063478 ); -PROVIDE ( user_code_start = 0x3ffe0400 ); -PROVIDE ( _UserExceptionVector = 0x40000340 ); -PROVIDE ( utoa = 0x40056258 ); -PROVIDE ( __utoa = 0x400561f0 ); -PROVIDE ( vasiprintf = 0x40056eb8 ); -PROVIDE ( _vasiprintf_r = 0x40056e80 ); -PROVIDE ( vasniprintf = 0x40056e58 ); -PROVIDE ( _vasniprintf_r = 0x40056df8 ); -PROVIDE ( vasnprintf = 0x40056e58 ); -PROVIDE ( _vasnprintf_r = 0x40056df8 ); -PROVIDE ( vasprintf = 0x40056eb8 ); -PROVIDE ( _vasprintf_r = 0x40056e80 ); -PROVIDE ( VerifyFlashMd5Proc = 0x40008c44 ); -PROVIDE ( veryBigHexP256 = 0x3ff9736c ); -PROVIDE ( vfiprintf = 0x40057ae8 ); -PROVIDE ( _vfiprintf_r = 0x40057850 ); -PROVIDE ( vfiscanf = 0x40057eb8 ); -PROVIDE ( _vfiscanf_r = 0x40057f24 ); -PROVIDE ( vfprintf = 0x40057ae8 ); -PROVIDE ( _vfprintf_r = 0x40057850 ); -PROVIDE ( vfscanf = 0x40057eb8 ); -PROVIDE ( _vfscanf_r = 0x40057f24 ); -PROVIDE ( viprintf = 0x400569b4 ); -PROVIDE ( _viprintf_r = 0x400569e4 ); -PROVIDE ( viscanf = 0x40058698 ); -PROVIDE ( _viscanf_r = 0x400586c8 ); -PROVIDE ( vprintf = 0x400569b4 ); -PROVIDE ( _vprintf_r = 0x400569e4 ); -PROVIDE ( vscanf = 0x40058698 ); -PROVIDE ( _vscanf_r = 0x400586c8 ); -PROVIDE ( vsiprintf = 0x40056ac4 ); -PROVIDE ( _vsiprintf_r = 0x40056a90 ); -PROVIDE ( vsiscanf = 0x40058740 ); -PROVIDE ( _vsiscanf_r = 0x400586f8 ); -PROVIDE ( vsniprintf = 0x40056a68 ); -PROVIDE ( _vsniprintf_r = 0x40056a14 ); -PROVIDE ( vsnprintf = 0x40056a68 ); -PROVIDE ( _vsnprintf_r = 0x40056a14 ); -PROVIDE ( vsprintf = 0x40056ac4 ); -PROVIDE ( _vsprintf_r = 0x40056a90 ); -PROVIDE ( vsscanf = 0x40058740 ); -PROVIDE ( _vsscanf_r = 0x400586f8 ); -PROVIDE ( wcrtomb = 0x40058920 ); -PROVIDE ( _wcrtomb_r = 0x400588d8 ); -PROVIDE ( __wctomb = 0x3ff96540 ); -PROVIDE ( _wctomb_r = 0x40058f14 ); -PROVIDE ( _WindowOverflow12 = 0x40000100 ); -PROVIDE ( _WindowOverflow4 = 0x40000000 ); -PROVIDE ( _WindowOverflow8 = 0x40000080 ); -PROVIDE ( _WindowUnderflow12 = 0x40000140 ); -PROVIDE ( _WindowUnderflow4 = 0x40000040 ); -PROVIDE ( _WindowUnderflow8 = 0x400000c0 ); -PROVIDE ( write = 0x4000181c ); -PROVIDE ( _write_r = 0x4000bd70 ); -PROVIDE ( xthal_bcopy = 0x4000c098 ); -PROVIDE ( xthal_copy123 = 0x4000c124 ); -PROVIDE ( xthal_get_ccompare = 0x4000c078 ); -PROVIDE ( xthal_get_ccount = 0x4000c050 ); -PROVIDE ( xthal_get_interrupt = 0x4000c1e4 ); -PROVIDE ( xthal_get_intread = 0x4000c1e4 ); -PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 ); -PROVIDE ( xthal_memcpy = 0x4000c0bc ); -PROVIDE ( xthal_set_ccompare = 0x4000c058 ); -PROVIDE ( xthal_set_intclear = 0x4000c1ec ); -PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 ); -PROVIDE ( _xtos_alloca_handler = 0x40000010 ); -PROVIDE ( _xtos_cause3_handler = 0x40000dd8 ); -PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 ); -PROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 ); -PROVIDE ( _xtos_enabled = 0x3ffe0650 ); -PROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 ); -PROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 ); -PROVIDE ( _xtos_interrupt_table = 0x3ffe0658 ); -PROVIDE ( _xtos_ints_off = 0x4000bfac ); -PROVIDE ( _xtos_ints_on = 0x4000bf88 ); -PROVIDE ( _xtos_intstruct = 0x3ffe0650 ); -PROVIDE ( _xtos_l1int_handler = 0x40000814 ); -PROVIDE ( _xtos_p_none = 0x4000bfd4 ); -PROVIDE ( _xtos_restore_intlevel = 0x40000928 ); -PROVIDE ( _xtos_return_from_exc = 0x4000c034 ); -PROVIDE ( _xtos_set_exception_handler = 0x4000074c ); -PROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 ); -PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 ); -PROVIDE ( _xtos_set_intlevel = 0x4000bfdc ); -PROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 ); -PROVIDE ( _xtos_set_vpri = 0x40000934 ); -PROVIDE ( _xtos_syscall_handler = 0x40000790 ); -PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); -PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); -PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); -PROVIDE ( g_rom_flashchip = 0x3ffae270 ); -PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 ); -PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 ); -PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 ); -PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 ); -PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c ); - -PROVIDE ( esp_rom_printf = ets_printf ); -PROVIDE ( esp_rom_delay_us = ets_delay_us ); diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/gnu-elf.ld b/boards/xtensa/esp32/esp32-wrover-kit/scripts/gnu-elf.ld deleted file mode 100644 index e16152f4669..00000000000 --- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/gnu-elf.ld +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/xtensa/esp32/esp32-wrover-kit/scripts/gnu-elf.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -SECTIONS -{ - .text 0x00000000 : - { - _stext = . ; - *(.text) - *(.text.*) - *(.gnu.warning) - *(.stub) - *(.glue_7) - *(.glue_7t) - *(.jcr) - - /* C++ support: The .init and .fini sections contain specific logic - * to manage static constructors and destructors. - */ - - *(.gnu.linkonce.t.*) - *(.init) /* Old ABI */ - *(.fini) /* Old ABI */ - _etext = . ; - } - - .rodata : - { - _srodata = . ; - *(.rodata) - *(.rodata1) - *(.rodata.*) - *(.gnu.linkonce.r*) - _erodata = . ; - } - - .data : - { - _sdata = . ; - *(.data) - *(.data1) - *(.data.*) - *(.gnu.linkonce.d*) - . = ALIGN(4); - _edata = . ; - } - - /* C++ support. For each global and static local C++ object, - * GCC creates a small subroutine to construct the object. Pointers - * to these routines (not the routines themselves) are stored as - * simple, linear arrays in the .ctors section of the object file. - * Similarly, pointers to global/static destructor routines are - * stored in .dtors. - */ - - .ctors : - { - _sctors = . ; - *(.ctors) /* Old ABI: Unallocated */ - *(.init_array) /* New ABI: Allocated */ - _ectors = . ; - } - - .dtors : - { - _sdtors = . ; - *(.dtors) /* Old ABI: Unallocated */ - *(.fini_array) /* New ABI: Allocated */ - _edtors = . ; - } - - .bss : - { - _sbss = . ; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.b*) - *(COMMON) - _ebss = . ; - } - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c index 41300a2eb9a..a9ee883427a 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c @@ -81,11 +81,19 @@ # include #endif +#ifdef CONFIG_ESP32_RT_TIMER +# include "esp32_rt_timer.h" +#endif + #ifdef CONFIG_LCD_DEV # include # include #endif +#ifdef CONFIG_RTC_DRIVER +# include "esp32_rtc_lowerhalf.h" +#endif + #include "esp32-wrover-kit.h" /**************************************************************************** @@ -173,6 +181,14 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESP32_RT_TIMER + ret = esp32_rt_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); + } +#endif + #ifdef CONFIG_ESP32_WIRELESS ret = board_wlan_init(); if (ret < 0) @@ -346,6 +362,17 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the ESP32 RTC driver */ + + ret = esp32_rtc_driverinit(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_buttons.c index 6b1594f9f90..da9b8ecb74a 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_buttons.c @@ -24,10 +24,11 @@ #include +#include +#include #include #include #include -#include #include #include diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c index 0453dc14b1f..785ad3b35aa 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c @@ -25,9 +25,9 @@ #include #include -#include #include #include +#include #include #include diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_spiflash.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_spiflash.c index 25ac83e38d8..a0622e7dce3 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_spiflash.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_spiflash.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/boards/xtensa/esp32s2/common/Kconfig b/boards/xtensa/esp32s2/common/Kconfig new file mode 100644 index 00000000000..18c7905aed7 --- /dev/null +++ b/boards/xtensa/esp32s2/common/Kconfig @@ -0,0 +1,5 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + diff --git a/boards/xtensa/esp32s2/common/Makefile b/boards/xtensa/esp32s2/common/Makefile new file mode 100644 index 00000000000..fa894b6eb7e --- /dev/null +++ b/boards/xtensa/esp32s2/common/Makefile @@ -0,0 +1,33 @@ +############################################################################# +# boards/xtensa/esp32s2/common/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +include board/Make.defs +include src/Make.defs + +DEPPATH += --dep-path board +DEPPATH += --dep-path src + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(BOARDDIR)$(DELIM)include) diff --git a/boards/xtensa/esp32s2/common/src/Make.defs b/boards/xtensa/esp32s2/common/src/Make.defs new file mode 100644 index 00000000000..e0193190688 --- /dev/null +++ b/boards/xtensa/esp32s2/common/src/Make.defs @@ -0,0 +1,23 @@ +############################################################################# +# boards/xtensa/esp32s2/common/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +DEPPATH += --dep-path src +VPATH += :src +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src) diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/Kconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/Kconfig new file mode 100644 index 00000000000..58cf2191c8f --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32S2_SAOLA_1 + +endif # ARCH_BOARD_ESP32S2_SAOLA_1 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig new file mode 100644 index 00000000000..4034dc9807e --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s2-saola-1" +CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y +CONFIG_ARCH_CHIP="esp32s2" +CONFIG_ARCH_CHIP_ESP32S2=y +CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32S2_DATA_CACHE_0KB=y +CONFIG_ESP32S2_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/include/board.h b/boards/xtensa/esp32s2/esp32s2-saola-1/include/board.h new file mode 100644 index 00000000000..be5ecb0cdbf --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/include/board.h @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_INCLUDE_BOARD_H +#define __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The ESP32S2 board V2 is fitted with a 40MHz crystal */ + +#define BOARD_XTAL_FREQUENCY 40000000 + +/* Clock reconfiguration is currently disabled, so the CPU will be running + * at the XTAL frequency or at two times the XTAL frequency, depending upon + * how we load the code: + * + * - If we load the code into FLASH at address 0x1000 where it is started by + * the second level bootloader, then the frequency is the crystal + * frequency. + * - If we load the code into IRAM after the second level bootloader has run + * this frequency will be twice the crystal frequency. + * + * Don't ask me for an explanation. + */ + +/* Note: The bootloader (esp-idf bootloader.bin) configures: + * + * - CPU frequency to 80MHz + * - The XTAL frequency according to the SDK config CONFIG_ESP32S2_XTAL_FREQ, + * which is 40MHz by default. + * + * Reference: + * https://github.com/espressif/esp-idf/blob + * /6fd855ab8d00d23bad4660216bc2122c2285d5be/components + * /bootloader_support/src/bootloader_clock.c#L38-L62 + */ + +#ifdef CONFIG_ESP32S2_RUN_IRAM +# define BOARD_CLOCK_FREQUENCY (2 * BOARD_XTAL_FREQUENCY) +#else +#ifdef CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ +# define BOARD_CLOCK_FREQUENCY (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000) +#else +# define BOARD_CLOCK_FREQUENCY 80000000 +#endif +#endif + +/* LED definitions **********************************************************/ + +/* Define how many LEDs this board has (needed by userleds) */ + +#define BOARD_NLEDS 1 + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOIN 1 /* Amount of GPIO Input without Interruption */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +#endif /* __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_INCLUDE_BOARD_H */ diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/.gitignore b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/.gitignore new file mode 100644 index 00000000000..f93f56cccd7 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/.gitignore @@ -0,0 +1 @@ +/esp32s2_out.ld diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs new file mode 100644 index 00000000000..df80445414c --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs @@ -0,0 +1,109 @@ +############################################################################ +# boards/xtensa/esp32s2/esp32s2-devkitc/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/esp32s2/Config.mk +include $(TOPDIR)/arch/xtensa/src/lx7/Toolchain.defs + +LDSCRIPT1 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_out.ld +LDSCRIPT3 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_rom.ld +LDSCRIPT4 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_peripherals.ld + +ifeq ($(CONFIG_ESP32S2_RUN_IRAM),y) + LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_iram.ld +else + LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_flash.ld +endif + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}" +else + ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls +ARCHCXXFLAGS = $(ARCHCFLAGS) -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic + +# if SPIRAM/PSRAM is used then we need to include a workaround + +ifeq ($(CONFIG_ESP32S2_SPIRAM),y) + ARCHCFLAGS += -mfix-esp32s2-psram-cache-issue +endif + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mtext-section-literals + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mtext-section-literals +CXXELFFLAGS = $(CXXFLAGS) -mtext-section-literals + +LDELFFLAGS = -r -e main +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}" +else + LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld +endif + +LDFLAGS += -nostartfiles -nodefaultlibs + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDFLAGS += -Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" --cref +else + LDFLAGS += -Map=$(TOPDIR)/nuttx.map --cref +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld new file mode 100644 index 00000000000..36172801df9 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld + * ESP32S2 Linker Script Memory Layout + * + * This file describes the memory layout (memory blocks) as virtual + * memory addresses. + * + * esp32s2.common.ld contains output sections to link compiler output + * into these memory blocks. + * + * NOTE: That this is not the actual linker script but rather a "template" + * for the elf32_out.ld script. This template script is passed through + * the C preprocessor to include selected configuration options. + * + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB +# define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000 +#else +# define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000 +#endif + +#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB +# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0 +#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB +# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000 +#else +# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000 +#endif + +#define RAM_IRAM_START 0x40020000 +#define RAM_DRAM_START 0x3ffb0000 + +#define DATA_RAM_END 0x3ffe0000 /* 2nd stage bootloader iram_loader_seg + * starts at SRAM block 14 (reclaimed + * after app boots) + */ + +#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + + CONFIG_ESP32S2_DATA_CACHE_SIZE) + +#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + + CONFIG_ESP32S2_DATA_CACHE_SIZE) + +#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG + +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this + * uses subtracted from the length of the various regions. The 'data access + * port' dram/drom regions map to the same iram/irom regions but are + * connected to the data port of the CPU and eg allow bytewise access. + */ + + /* IRAM for CPU */ + + iram0_0_seg (RX) : org = IRAM_ORG, len = I_D_RAM_SIZE + + /* Even though the segment name is iram, it is actually mapped to flash */ + + iram0_2_seg (RX) : org = 0x40080020, len = 0x780000-0x20 + + /* (0x20 offset above is a convenience for the app binary image generation. + * Flash cache has 64KB pages. The .bin file which is flashed to the chip + * has a 0x18 byte file header, and each segment has a 0x08 byte segment + * header. Setting this offset makes it simple to meet the flash cache MMU's + * constraint that (paddr % 64KB == vaddr % 64KB).) + */ + + /* Shared data RAM, excluding memory reserved for bootloader and ROM + * bss/data/stack. + */ + + dram0_0_seg (RW) : org = DRAM_ORG, len = I_D_RAM_SIZE + + /* Flash mapped constant data */ + + drom0_0_seg (R) : org = 0x3f000020, len = 0x3f0000-0x20 + + /* RTC fast memory (executable). Persists over deep sleep. */ + + rtc_iram_seg(RWX) : org = 0x40070000, len = 0x2000 + + /* RTC slow memory (data accessible). Persists over deep sleep. + * Start of RTC slow memory is reserved for ULP co-processor code + data, + * if enabled. + */ + + rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM, + len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM +} + diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_iram.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_flash.ld similarity index 83% rename from boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_iram.ld rename to boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_flash.ld index 06a79a40e92..74acf2fd6f4 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_iram.ld +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32_iram.ld + * boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_flash.ld ****************************************************************************/ /* Default entry point: */ @@ -12,7 +12,9 @@ SECTIONS .iram0.vectors : { - /* Vectors go to IRAM */ + _iram_start = ABSOLUTE(.); + + /* Vectors go to IRAM. */ _init_start = ABSOLUTE(.); @@ -45,37 +47,25 @@ SECTIONS *(.entry.text) *(.init.literal) *(.init) - _init_end = ABSOLUTE(.); } > iram0_0_seg .iram0.text : { /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) - *libphy.a:(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) - *libpp.a:(.literal .text .literal.* .text.*) - *libhal.a:(.literal .text .literal.* .text.*) - _iram_text_end = ABSOLUTE(.); - _stext = .; - _text_start = ABSOLUTE(.); - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; + /* align + add 16B for CPU dummy speculative instr. fetch */ - /* Module text area starts at the end of iram0_0_seg */ - - . = ALIGN (4); - _smodtext = ABSOLUTE(.); + . = ALIGN(4) + 16; + _iram_text = ABSOLUTE(.); } > iram0_0_seg + .dram0_reserved_for_iram (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_text - _iram_start; + } > dram0_0_seg + /* Shared RAM */ .dram0.bss (NOLOAD) : @@ -108,7 +98,9 @@ SECTIONS * or during the application's initialization sequence. */ + . = ALIGN(4); *(.noinit) + . = ALIGN(4); } >dram0_0_seg .dram0.data : @@ -131,6 +123,13 @@ SECTIONS . = ALIGN(4); _edata = ABSOLUTE(.); + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } >dram0_0_seg + + .flash.rodata : + { _srodata = ABSOLUTE(.); *(.rodata) *(.rodata.*) @@ -140,6 +139,7 @@ SECTIONS __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); *(.xt_except_table) *(.gcc_except_table) + *(.gcc_except_table.*) *(.gnu.linkonce.e.*) *(.gnu.version_r) *(.eh_frame) @@ -169,18 +169,36 @@ SECTIONS *(.dynamic) *(.gnu.version_d) _erodata = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); *(*.lit4) *(.lit4.*) *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); + } >drom0_0_seg - /* Heap starts at the end of .data */ + .flash.text : + { + _stext = .; + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) - _sheap = ABSOLUTE(.); - } >dram0_0_seg + /* CPU will try to prefetch up to 16 bytes of instructions. + * This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + + . += 16; + + _etext = .; + } >iram0_2_seg .rtc.text : { diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32_iram.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_iram.ld similarity index 85% rename from boards/xtensa/esp32/esp32-devkitc/scripts/esp32_iram.ld rename to boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_iram.ld index 410c6cbe7d4..52b211d65c9 100644 --- a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32_iram.ld +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_iram.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/xtensa/esp32/esp32-devkitc/scripts/esp32_iram.ld + * boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2s2_iram.ld ****************************************************************************/ /* Default entry point: */ @@ -52,28 +52,19 @@ SECTIONS { /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) - *libphy.a:(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) - *libpp.a:(.literal .text .literal.* .text.*) - *libhal.a:(.literal .text .literal.* .text.*) - _iram_text_end = ABSOLUTE(.); _stext = .; - _text_start = ABSOLUTE(.); *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ *(.fini.literal) *(.fini) *(.gnu.version) - _text_end = ABSOLUTE(.); + + /* align + add 16B for CPU dummy speculative instr. fetch */ + + . = ALIGN(4) + 16; _etext = .; - - /* Module text area starts at the end of iram0_0_seg */ - - . = ALIGN (4); - _smodtext = ABSOLUTE(.); } > iram0_0_seg /* Shared RAM */ @@ -100,15 +91,12 @@ SECTIONS *(COMMON) . = ALIGN(8); _ebss = ABSOLUTE(.); - } >dram0_0_seg - .noinit (NOLOAD): - { - /* This section contains data that is not initialized during load, - * or during the application's initialization sequence. - */ + /* Uninitialized .bss */ + . = ALIGN(4); *(.noinit) + . = ALIGN(4); } >dram0_0_seg .dram0.data : diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_peripherals.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_peripherals.ld new file mode 100644 index 00000000000..62f5f970cb3 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_peripherals.ld @@ -0,0 +1,36 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_peripherals.ld + ****************************************************************************/ + +PROVIDE ( UART0 = 0x3f400000 ); +PROVIDE ( SPIMEM1 = 0x3f402000 ); +PROVIDE ( SPIMEM0 = 0x3f403000 ); +PROVIDE ( GPIO = 0x3f404000 ); +PROVIDE ( SIGMADELTA = 0x3f404f00 ); +PROVIDE ( RTCCNTL = 0x3f408000 ); +PROVIDE ( RTCIO = 0x3f408400 ); +PROVIDE ( SENS = 0x3f408800 ); +PROVIDE ( HINF = 0x3f40b000 ); +PROVIDE ( I2S0 = 0x3f40F000 ); +PROVIDE ( UART1 = 0x3f410000 ); +PROVIDE ( I2C0 = 0x3f413000 ); +PROVIDE ( UHCI0 = 0x3f414000 ); +PROVIDE ( HOST = 0x3f415000 ); +PROVIDE ( RMT = 0x3f416000 ); +PROVIDE ( RMTMEM = 0x3f416400 ); +PROVIDE ( PCNT = 0x3f417000 ); +PROVIDE ( SLC = 0x3f418000 ); +PROVIDE ( LEDC = 0x3f419000 ); +PROVIDE ( CP_DMA = 0x3f4c3000 ); +PROVIDE ( TIMERG0 = 0x3f41f000 ); +PROVIDE ( TIMERG1 = 0x3f420000 ); +PROVIDE ( SPI2 = 0x3f424000 ); +PROVIDE ( SPI3 = 0x3f425000 ); +PROVIDE ( SYSCON = 0x3f426000 ); +PROVIDE ( I2C1 = 0x3f427000 ); +PROVIDE ( TWAI = 0x3f42b000 ); +PROVIDE ( APB_SARADC = 0x3f440000 ); +PROVIDE ( DEDIC_GPIO = 0x3f4cf000 ); +PROVIDE ( USB0 = 0x60080000 ); +PROVIDE ( USBH = 0x60080000 ); +PROVIDE ( USB_WRAP = 0x3f439000 ); diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld new file mode 100644 index 00000000000..d6d6e1b2410 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld @@ -0,0 +1,817 @@ +/** + * ESP32-S2 ROM address table (except symbols from libgcc and libc) + * Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796 + * + * These are all weak symbols that could be overwritten in ESP-IDF. + */ + +PROVIDE ( abort = 0x40019fb4 ); +PROVIDE ( acm_config_descr = 0x3ffaef0f ); +PROVIDE ( acm_usb_descriptors = 0x3ffaee68 ); +PROVIDE ( boot_prepare = 0x4000f348 ); +PROVIDE ( Cache_Address_Through_DCache = 0x400180f0 ); +PROVIDE ( Cache_Address_Through_ICache = 0x400180bc ); +PROVIDE ( Cache_Allocate_SRAM = 0x40018d6c ); +PROVIDE ( Cache_Clean_Addr = 0x40018370 ); +PROVIDE ( Cache_Clean_All = 0x40018438 ); +PROVIDE ( Cache_Clean_Items = 0x40018250 ); +PROVIDE ( Cache_Config_DCache_Autoload = 0x40018794 ); +PROVIDE ( Cache_Config_ICache_Autoload = 0x40018664 ); +PROVIDE ( Cache_Count_Flash_Pages = 0x40018f70 ); +PROVIDE ( Cache_Dbus_MMU_Set = 0x40018eb0 ); +PROVIDE ( Cache_DCache_Preload_Done = 0x40018630 ); +PROVIDE ( Cache_Disable_DCache = 0x40018c68 ); +PROVIDE ( Cache_Disable_DCache_Autoload = 0x4001888c ); +PROVIDE ( Cache_Disable_DCache_PreLock = 0x40018a5c ); +PROVIDE ( Cache_Disable_ICache = 0x40018c2c ); +PROVIDE ( Cache_Disable_ICache_Autoload = 0x4001875c ); +PROVIDE ( Cache_Disable_ICache_PreLock = 0x4001892c ); +PROVIDE ( Cache_Enable_DCache = 0x40018d58 ); +PROVIDE ( Cache_Enable_DCache_Autoload = 0x40018874 ); +PROVIDE ( Cache_Enable_DCache_PreLock = 0x400189f0 ); +PROVIDE ( Cache_Enable_Defalut_DCache_Mode = 0x40018170 ); +PROVIDE ( Cache_Enable_ICache = 0x40018cf8 ); +PROVIDE ( Cache_Enable_ICache_Autoload = 0x40018744 ); +PROVIDE ( Cache_Enable_ICache_PreLock = 0x400188c0 ); +PROVIDE ( Cache_End_DCache_Preload = 0x40018644 ); +PROVIDE ( Cache_End_ICache_Preload = 0x400185b0 ); +PROVIDE ( Cache_Flash_To_SPIRAM_Copy = 0x40018fc4 ); +PROVIDE ( Cache_Get_DCache_Line_Size = 0x40017fd8 ); +PROVIDE ( Cache_Get_ICache_Line_Size = 0x40017fbc ); +PROVIDE ( Cache_Get_Memory_Addr = 0x4001929c ); +PROVIDE ( Cache_Get_Memory_BaseAddr = 0x40019244 ); +PROVIDE ( Cache_Get_Memory_value = 0x400192d8 ); +PROVIDE ( Cache_Get_Mode = 0x40017ff0 ); +PROVIDE ( Cache_Get_Virtual_Addr = 0x40019210 ); +PROVIDE ( Cache_Ibus_MMU_Set = 0x40018df4 ); +PROVIDE ( Cache_ICache_Preload_Done = 0x4001859c ); +PROVIDE ( Cache_Invalidate_Addr = 0x400182e4 ); +PROVIDE ( Cache_Invalidate_DCache_All = 0x4001842c ); +PROVIDE ( Cache_Invalidate_DCache_Items = 0x40018208 ); +PROVIDE ( Cache_Invalidate_ICache_All = 0x40018420 ); +PROVIDE ( Cache_Invalidate_ICache_Items = 0x400181b8 ); +PROVIDE ( Cache_Lock_Addr = 0x40018b10 ); +PROVIDE ( Cache_Lock_DCache_Items = 0x40018a80 ); +PROVIDE ( Cache_Lock_ICache_Items = 0x40018950 ); +PROVIDE ( Cache_Mask_All = 0x40018458 ); +PROVIDE ( cache_memory_baseaddrs = 0x3ffaf020 ); +PROVIDE ( Cache_MMU_Init = 0x40018dd8 ); +PROVIDE ( Cache_Resume_DCache = 0x40018d3c ); +PROVIDE ( Cache_Resume_DCache_Autoload = 0x4001850c ); +PROVIDE ( Cache_Resume_ICache = 0x40018cdc ); +PROVIDE ( Cache_Resume_ICache_Autoload = 0x400184c4 ); +PROVIDE ( Cache_Set_DCache_Mode = 0x40018074 ); +PROVIDE ( Cache_Set_Default_Mode = 0x4001810c ); +PROVIDE ( Cache_Set_ICache_Mode = 0x4001803c ); +PROVIDE ( Cache_Start_DCache_Preload = 0x400185c4 ); +PROVIDE ( Cache_Start_ICache_Preload = 0x40018530 ); +PROVIDE ( Cache_Suspend_DCache = 0x40018d04 ); +PROVIDE ( Cache_Suspend_DCache_Autoload = 0x400184e0 ); +PROVIDE ( Cache_Suspend_ICache = 0x40018ca4 ); +PROVIDE ( Cache_Suspend_ICache_Autoload = 0x40018498 ); +PROVIDE ( Cache_Travel_Tag_Memory = 0x4001908c ); +PROVIDE ( Cache_Unlock_Addr = 0x40018b9c ); +PROVIDE ( Cache_Unlock_DCache_Items = 0x40018ac8 ); +PROVIDE ( Cache_Unlock_ICache_Items = 0x40018998 ); +PROVIDE ( Cache_UnMask_Drom0 = 0x40018480 ); +PROVIDE ( Cache_WriteBack_Addr = 0x400183c8 ); +PROVIDE ( Cache_WriteBack_All = 0x40018444 ); +PROVIDE ( Cache_WriteBack_Items = 0x40018298 ); +PROVIDE ( cacl_rtc_memory_crc = 0x4000ffa0 ); +PROVIDE ( cdc_acm_class_handle_req = 0x40013050 ); +PROVIDE ( cdc_acm_config = 0x3ffffa10 ); +PROVIDE ( cdc_acm_dev = 0x3ffffce8 ); +PROVIDE ( cdc_acm_fifo_fill = 0x4001318c ); +PROVIDE ( cdc_acm_fifo_read = 0x40013200 ); +PROVIDE ( cdc_acm_init = 0x40013144 ); +PROVIDE ( cdc_acm_irq_callback_set = 0x400132d4 ); +PROVIDE ( cdc_acm_irq_is_pending = 0x400132b0 ); +PROVIDE ( cdc_acm_irq_rx_disable = 0x40013290 ); +PROVIDE ( cdc_acm_irq_rx_enable = 0x40013284 ); +PROVIDE ( cdc_acm_irq_rx_ready = 0x4001329c ); +PROVIDE ( cdc_acm_irq_state_disable = 0x40013264 ); +PROVIDE ( cdc_acm_irq_state_enable = 0x40013258 ); +PROVIDE ( cdc_acm_irq_tx_disable = 0x4001324c ); +PROVIDE ( cdc_acm_irq_tx_enable = 0x40013240 ); +PROVIDE ( cdc_acm_irq_tx_ready = 0x40013270 ); +PROVIDE ( cdc_acm_line_ctrl_get = 0x40013330 ); +PROVIDE ( cdc_acm_line_ctrl_set = 0x400132dc ); +PROVIDE ( cdc_acm_poll_out = 0x40013360 ); +PROVIDE ( cdc_acm_rx_fifo_cnt = 0x400131ec ); +PROVIDE ( chip723_phyrom_version = 0x4000a8a8 ); +PROVIDE ( chip_usb_detach = 0x40013508 ); +PROVIDE ( chip_usb_dw_did_persist = 0x4001337c ); +PROVIDE ( chip_usb_dw_init = 0x400133bc ); +PROVIDE ( chip_usb_dw_prepare_persist = 0x40013588 ); +PROVIDE ( chip_usb_get_persist_flags = 0x400135d8 ); +PROVIDE ( chip_usb_set_persist_flags = 0x400135e8 ); +PROVIDE ( context = 0x3fffeb34 ); +PROVIDE ( cpio_destroy = 0x4001599c ); +PROVIDE ( cpio_done = 0x40015968 ); +PROVIDE ( cpio_feed = 0x40015668 ); +PROVIDE ( cpio_start = 0x4001561c ); +PROVIDE ( crc16_le = 0x40011a10 ); +PROVIDE ( crc32_le = 0x400119dc ); +PROVIDE ( crc8_le = 0x40011a4c ); +PROVIDE ( _cvt = 0x4000f9b8 ); +PROVIDE ( _data_end_all_pro = 0x3fffff98 ); +PROVIDE ( _data_end_c = 0x3ffffd80 ); +PROVIDE ( _data_end_ets = 0x3fffe710 ); +PROVIDE ( _data_end_ets_delay = 0x3ffffd74 ); +PROVIDE ( _data_end_ets_printf = 0x3ffffd5c ); +PROVIDE ( _data_end_newlib = 0x3ffffd74 ); +PROVIDE ( _data_end_phyrom = 0x3fffff98 ); +PROVIDE ( _data_end_sip = 0x3fffeb70 ); +PROVIDE ( _data_end_slc = 0x3fffeb70 ); +PROVIDE ( _data_end_spi_flash = 0x3ffffd54 ); +PROVIDE ( _data_end_spi_slave = 0x3fffeb30 ); +PROVIDE ( _data_end_uart = 0x3ffffcf4 ); +PROVIDE ( _data_end_usbdev = 0x3ffffa6c ); +PROVIDE ( _data_end_xtos = 0x3fffef88 ); +PROVIDE ( _data_start_all_pro = 0x3fffff98 ); +PROVIDE ( _data_start_c = 0x3ffffd7c ); +PROVIDE ( _data_start_ets = 0x3fffe710 ); +PROVIDE ( _data_start_ets_delay = 0x3ffffd70 ); +PROVIDE ( _data_start_ets_printf = 0x3ffffd5c ); +PROVIDE ( _data_start_newlib = 0x3ffffd74 ); +PROVIDE ( _data_start_phyrom = 0x3ffffd90 ); +PROVIDE ( _data_start_sip = 0x3fffeb70 ); +PROVIDE ( _data_start_slc = 0x3fffeb70 ); +PROVIDE ( _data_start_spi_flash = 0x3ffffd38 ); +PROVIDE ( _data_start_spi_slave = 0x3fffeb30 ); +PROVIDE ( _data_start_uart = 0x3ffffcf4 ); +PROVIDE ( _data_start_usbdev = 0x3ffffa10 ); +PROVIDE ( _data_start_xtos = 0x3fffeb70 ); +PROVIDE ( dbus_baseaddrs = 0x3ffaf030 ); +PROVIDE ( _DebugExceptionVector = 0x40000280 ); +PROVIDE ( _DebugExceptionVector_text_end = 0x4000028b ); +PROVIDE ( _DebugExceptionVector_text_start = 0x40000280 ); +PROVIDE ( __default_global_locale = 0x3ffac600 ); +PROVIDE ( dfu_class_handle_req = 0x400152f0 ); +PROVIDE ( dfu_config_descr = 0x3ffaeeb2 ); +PROVIDE ( dfu_cpio_callback = 0x4001360c ); +PROVIDE ( dfu_custom_handle_req = 0x40015568 ); +PROVIDE ( dfu_flash_attach = 0x40015a34 ); +PROVIDE ( dfu_flash_deinit = 0x400159b4 ); +PROVIDE ( dfu_flash_erase = 0x400159bc ); +PROVIDE ( dfu_flash_init = 0x400159a4 ); +PROVIDE ( dfu_flash_program = 0x400159d0 ); +PROVIDE ( dfu_flash_read = 0x40015a24 ); +PROVIDE ( dfu_status_cb = 0x40015514 ); +PROVIDE ( dfu_updater_begin = 0x40013858 ); +PROVIDE ( dfu_updater_clear_err = 0x40013810 ); +PROVIDE ( dfu_updater_enable = 0x40013828 ); +PROVIDE ( dfu_updater_end = 0x40013900 ); +PROVIDE ( dfu_updater_feed = 0x400138b4 ); +PROVIDE ( dfu_updater_flash_read = 0x400139e8 ); +PROVIDE ( dfu_updater_get_err = 0x400137fc ); +PROVIDE ( dfu_updater_set_raw_addr = 0x400139d4 ); +PROVIDE ( dfu_usb_descriptors = 0x3ffaee4c ); +PROVIDE ( dh_group14_generator = 0x3ffadfec ); +PROVIDE ( dh_group14_prime = 0x3ffadeec ); +PROVIDE ( dh_group15_generator = 0x3ffadeeb ); +PROVIDE ( dh_group15_prime = 0x3ffadd6b ); +PROVIDE ( dh_group16_generator = 0x3ffadd6a ); +PROVIDE ( dh_group16_prime = 0x3ffadb6a ); +PROVIDE ( dh_group17_generator = 0x3ffadb69 ); +PROVIDE ( dh_group17_prime = 0x3ffad869 ); +PROVIDE ( dh_group18_generator = 0x3ffad868 ); +PROVIDE ( dh_group18_prime = 0x3ffad468 ); +PROVIDE ( dh_group1_generator = 0x3ffae18f ); +PROVIDE ( dh_group1_prime = 0x3ffae12f ); +PROVIDE ( dh_group2_generator = 0x3ffae12e ); +PROVIDE ( dh_group2_prime = 0x3ffae0ae ); +PROVIDE ( dh_group5_generator = 0x3ffae0ad ); +PROVIDE ( dh_group5_prime = 0x3ffadfed ); +PROVIDE ( disable_default_watchdog = 0x4000f270 ); +PROVIDE ( Disable_QMode = 0x400166e0 ); +PROVIDE ( dmadesc_rx = 0x3fffeb4c ); +PROVIDE ( dmadesc_tx = 0x3fffeb40 ); +PROVIDE ( _DoubleExceptionVector = 0x400003c0 ); +PROVIDE ( _DoubleExceptionVector_text_end = 0x400003c6 ); +PROVIDE ( _DoubleExceptionVector_text_start = 0x400003c0 ); +PROVIDE ( _dram0_0_start = 0x3ffeab00 ); +PROVIDE ( _dram0_rtos_reserved_start = 0x3ffffa10 ); +PROVIDE ( dummy_len_plus = 0x3ffffd54 ); +PROVIDE ( Enable_QMode = 0x40016690 ); +PROVIDE ( esp_crc8 = 0x40011a78 ); +PROVIDE ( esp_rom_config_pad_power_select = 0x40016e58 ); +PROVIDE ( esp_rom_opiflash_cache_mode_config = 0x40016754 ); +PROVIDE ( esp_rom_opiflash_exec_cmd = 0x40017e30 ); +PROVIDE ( esp_rom_opiflash_exit_continuous_read_mode = 0x40017ee8 ); +PROVIDE ( esp_rom_opiflash_mode_reset = 0x40017f90 ); +PROVIDE ( esp_rom_opiflash_pin_config = 0x400177f8 ); +PROVIDE ( esp_rom_opiflash_soft_reset = 0x40017f24 ); +PROVIDE ( esp_rom_spi_cmd_config = 0x40017c58 ); +PROVIDE ( esp_rom_spi_cmd_start = 0x40017ba8 ); +PROVIDE ( esp_rom_spi_flash_auto_sus_res = 0x400175e0 ); +PROVIDE ( esp_rom_spi_flash_auto_wait_idle = 0x4001751c ); +PROVIDE ( esp_rom_spi_flash_send_resume = 0x40017570 ); +PROVIDE ( esp_rom_spi_flash_update_id = 0x40016e44 ); +PROVIDE ( esp_rom_spi_reset_rw_mode = 0x40017984 ); +PROVIDE ( esp_rom_spi_set_dtr_swap_mode = 0x40017b60 ); +PROVIDE ( esp_rom_spi_set_op_mode = 0x400179e8 ); +PROVIDE ( _etext = 0x4001bed0 ); +PROVIDE ( ets_aes_block = 0x4000d610 ); +PROVIDE ( ets_aes_disable = 0x4000d4f8 ); +PROVIDE ( ets_aes_enable = 0x4000d4cc ); +PROVIDE ( ets_aes_set_endian = 0x4000d528 ); +PROVIDE ( ets_aes_setkey = 0x4000d594 ); +PROVIDE ( ets_aes_setkey_dec = 0x4000d5f0 ); +PROVIDE ( ets_aes_setkey_enc = 0x4000d5e0 ); +PROVIDE ( ets_bigint_disable = 0x4000d750 ); +PROVIDE ( ets_bigint_enable = 0x4000d708 ); +PROVIDE ( ets_bigint_getz = 0x4000d858 ); +PROVIDE ( ets_bigint_modexp = 0x4000d818 ); +PROVIDE ( ets_bigint_modmult = 0x4000d7f4 ); +PROVIDE ( ets_bigint_multiply = 0x4000d790 ); +PROVIDE ( ets_bigint_wait_finish = 0x4000d840 ); +PROVIDE ( ets_config_flash_by_image_hdr = 0x40010e40 ); +PROVIDE ( ets_delay_us = 0x4000d888 ); +PROVIDE ( ets_ds_disable = 0x4000d910 ); +PROVIDE ( ets_ds_enable = 0x4000d8e4 ); +PROVIDE ( ets_ds_encrypt_params = 0x4000da90 ); +PROVIDE ( ets_ds_finish_sign = 0x4000d9f8 ); +PROVIDE ( ets_ds_is_busy = 0x4000d93c ); +PROVIDE ( ets_ds_start_sign = 0x4000d96c ); +PROVIDE ( ets_efuse_cache_encryption_enabled = 0x4000e690 ); +PROVIDE ( ets_efuse_clear_program_registers = 0x4000e100 ); +PROVIDE ( ets_efuse_count_unused_key_blocks = 0x4000e2c4 ); +PROVIDE ( ets_efuse_download_modes_disabled = 0x4000e594 ); +PROVIDE ( ets_efuse_find_purpose = 0x4000e224 ); +PROVIDE ( ets_efuse_find_unused_key_block = 0x4000e2ac ); +PROVIDE ( ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x4000e640 ); +PROVIDE ( ets_efuse_flash_opi_mode = 0x4000e650 ); +PROVIDE ( ets_efuse_force_send_resume = 0x4000e660 ); +PROVIDE ( ets_efuse_get_flash_delay_us = 0x4000e6d4 ); +PROVIDE ( ets_efuse_get_key_purpose = 0x4000e1b0 ); +PROVIDE ( ets_efuse_get_opiconfig = 0x4000e4fc ); +PROVIDE ( ets_efuse_get_read_register_address = 0x4000e18c ); +PROVIDE ( ets_efuse_get_spiconfig = 0x4000e4a0 ); +PROVIDE ( ets_efuse_get_uart_print_channel = 0x4000e5b4 ); +PROVIDE ( ets_efuse_get_uart_print_control = 0x4000e5a4 ); +PROVIDE ( ets_efuse_get_wp_pad = 0x4000e444 ); +PROVIDE ( ets_efuse_key_block_unused = 0x4000e250 ); +PROVIDE ( ets_efuse_legacy_spi_boot_mode_disabled = 0x4000e6b0 ); +PROVIDE ( ets_efuse_program = 0x4000e134 ); +PROVIDE ( ets_efuse_read = 0x4000e0c0 ); +PROVIDE ( ets_efuse_rs_calculate = 0x4000e6f8 ); +PROVIDE ( ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000e680 ); +PROVIDE ( ets_efuse_secure_boot_enabled = 0x4000e670 ); +PROVIDE ( ets_efuse_security_download_modes_enabled = 0x4000e5d4 ); +PROVIDE ( ets_efuse_set_timing = 0x4000df3c ); +PROVIDE ( ets_efuse_start = 0x4000e084 ); +PROVIDE ( ets_efuse_usb_download_mode_disabled = 0x4000e5f4 ); +PROVIDE ( ets_efuse_usb_force_nopersist = 0x4000e630 ); +PROVIDE ( ets_efuse_usb_module_disabled = 0x4000e5c4 ); +PROVIDE ( ets_efuse_usb_use_ext_phy = 0x4000e620 ); +PROVIDE ( ets_efuse_write_key = 0x4000e2f4 ); +PROVIDE ( ets_emsa_pss_verify = 0x40011818 ); +PROVIDE ( ets_get_apb_freq = 0x40010c58 ); +PROVIDE ( ets_get_cpu_frequency = 0x4000d8b0 ); +PROVIDE ( ets_get_printf_channel = 0x4000ff48 ); +PROVIDE ( ets_get_xtal_div = 0x40010bfc ); +PROVIDE ( ets_get_xtal_freq = 0x40010c38 ); +PROVIDE ( ets_hmac_calculate_downstream = 0x4000f120 ); +PROVIDE ( ets_hmac_calculate_message = 0x4000f020 ); +PROVIDE ( ets_hmac_disable = 0x4000eff4 ); +PROVIDE ( ets_hmac_enable = 0x4000efd8 ); +PROVIDE ( ets_hmac_invalidate_downstream = 0x4000f140 ); +PROVIDE ( ets_install_lock = 0x4000fea0 ); +PROVIDE ( ets_install_putc1 = 0x4000feb0 ); +PROVIDE ( ets_install_putc2 = 0x4000fed0 ); +PROVIDE ( ets_install_uart_printf = 0x4000fec0 ); +PROVIDE ( ets_intr_count = 0x3fffe710 ); +PROVIDE ( ets_intr_lock = 0x4000f168 ); +PROVIDE ( ets_intr_unlock = 0x4000f17c ); +PROVIDE ( ets_is_print_boot = 0x4000f2a0 ); +PROVIDE ( ets_isr_attach = 0x4000f1a4 ); +PROVIDE ( ets_isr_mask = 0x4000f1b4 ); +PROVIDE ( ets_isr_unmask = 0x4000f1c0 ); +PROVIDE ( ets_jtag_enable_temporarily = 0x4000e548 ); +PROVIDE ( ets_loader_map_range = 0x40010d4c ); +PROVIDE ( ets_mgf1_sha256 = 0x400117b0 ); +PROVIDE ( ets_printf = 0x4000fee0 ); +PROVIDE ( ets_printf_lock = 0x3ffffd64 ); +PROVIDE ( ets_printf_uart = 0x3ffffd5c ); +PROVIDE ( ets_printf_unlock = 0x3ffffd60 ); +PROVIDE ( ets_rsa_pss_verify = 0x4001191c ); +PROVIDE ( ets_run_flash_bootloader = 0x40010f58 ); +PROVIDE ( ets_secure_boot_read_key_digests = 0x400101ac ); +PROVIDE ( ets_secure_boot_revoke_public_key_digest = 0x4001025c ); +PROVIDE ( ets_secure_boot_verify_bootloader_with_keys = 0x40010444 ); +PROVIDE ( ets_secure_boot_verify_signature = 0x400102cc ); +PROVIDE ( ets_secure_boot_verify_stage_bootloader = 0x40010720 ); +PROVIDE ( ets_set_printf_channel = 0x4000ff3c ); +PROVIDE ( ets_set_user_start = 0x4000f25c ); +PROVIDE ( ets_set_xtal_div = 0x40010c18 ); +PROVIDE ( ets_sha_clone = 0x4001095c ); +PROVIDE ( ets_sha_disable = 0x400107b4 ); +PROVIDE ( ets_sha_enable = 0x40010788 ); +PROVIDE ( ets_sha_finish = 0x40010ab8 ); +PROVIDE ( ets_sha_get_state = 0x40010934 ); +PROVIDE ( ets_sha_init = 0x400107e0 ); +PROVIDE ( ets_sha_process = 0x40010988 ); +PROVIDE ( ets_sha_starts = 0x40010828 ); +PROVIDE ( ets_sha_update = 0x400109f8 ); +PROVIDE ( ets_startup_callback = 0x3fffe718 ); +PROVIDE ( ets_unpack_flash_code_legacy = 0x40011430 ); +PROVIDE ( ets_update_cpu_frequency = 0x4000d8a4 ); +PROVIDE ( ets_vprintf = 0x4000fa3c ); +PROVIDE ( ets_waiti0 = 0x4000f190 ); +PROVIDE ( ets_wdt_reset_cpu = 0x4001a82c ); +PROVIDE ( ets_write_char = 0x4000f974 ); +PROVIDE ( ets_write_char_uart = 0x4000f998 ); +PROVIDE ( exc_cause_table = 0x3ffacbe8 ); +PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40011ed8 ); +PROVIDE ( FilePacketSendReqMsgProc = 0x40011bd8 ); +PROVIDE ( flashchip = 0x3ffffd38 ); +PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40011e80 ); +PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x40011cc0 ); +PROVIDE ( FlashDwnLdStartMsgProc = 0x40011b74 ); +PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40011fd8 ); +PROVIDE ( FlashDwnLdStopReqMsgProc = 0x40011c90 ); +PROVIDE ( general_device_descr = 0x3ffffa58 ); +PROVIDE ( _GeneralException = 0x400073cf ); +PROVIDE ( get_id = 0x4001610c ); +PROVIDE ( GetSecurityInfoProc = 0x40012098 ); +PROVIDE ( GetUartDevice = 0x40012f60 ); +PROVIDE ( __global_locale_ptr = 0x3ffffd7c ); +PROVIDE ( g_phyFuns = 0x3ffffd90 ); +PROVIDE ( g_phyFuns_instance = 0x3ffffd94 ); +PROVIDE ( gpio_input_get = 0x400193a0 ); +PROVIDE ( gpio_input_get_high = 0x400193b4 ); +PROVIDE ( gpio_matrix_in = 0x40019430 ); +PROVIDE ( gpio_matrix_out = 0x40019460 ); +PROVIDE ( gpio_output_disable = 0x400194dc ); +PROVIDE ( gpio_output_enable = 0x400194b0 ); +PROVIDE ( gpio_output_set = 0x4001933c ); +PROVIDE ( gpio_output_set_high = 0x40019374 ); +PROVIDE ( gpio_pad_hold = 0x40019654 ); +PROVIDE ( gpio_pad_input_disable = 0x400195f0 ); +PROVIDE ( gpio_pad_input_enable = 0x400195cc ); +PROVIDE ( gpio_pad_pulldown = 0x40019598 ); +PROVIDE ( gpio_pad_pullup = 0x40019564 ); +PROVIDE ( gpio_pad_select_gpio = 0x40019510 ); +PROVIDE ( gpio_pad_set_drv = 0x40019538 ); +PROVIDE ( gpio_pad_unhold = 0x4001961c ); +PROVIDE ( gpio_pin_wakeup_disable = 0x40019404 ); +PROVIDE ( gpio_pin_wakeup_enable = 0x400193c8 ); +PROVIDE ( g_shared_buffers = 0x3ffeab04 ); +PROVIDE ( g_ticks_per_us = 0x3ffffd70 ); +PROVIDE ( hmac_md5 = 0x40005490 ); +PROVIDE ( hmac_md5_vector = 0x400053a0 ); +PROVIDE ( ibus_baseaddrs = 0x3ffaf03c ); +PROVIDE ( intr_matrix_set = 0x4000f1d0 ); +PROVIDE ( _iram0_text_end = 0x40000540 ); +PROVIDE ( _iram0_text_start = 0x40000540 ); +PROVIDE ( _iram1_text_end = 0x60021100 ); +PROVIDE ( _iram1_text_start = 0x60021100 ); +PROVIDE ( _KernelExceptionVector = 0x40000300 ); +PROVIDE ( _KernelExceptionVector_text_end = 0x40000306 ); +PROVIDE ( _KernelExceptionVector_text_start = 0x40000300 ); +PROVIDE ( _Level2FromVector = 0x400074f8 ); +PROVIDE ( _Level2HandlerLabel = 0x00000000 ); +PROVIDE ( _Level2InterruptVector_text_end = 0x40000186 ); +PROVIDE ( _Level2InterruptVector_text_start = 0x40000180 ); +PROVIDE ( _Level2Vector = 0x40000180 ); +PROVIDE ( _Level3FromVector = 0x40007594 ); +PROVIDE ( _Level3HandlerLabel = 0x00000000 ); +PROVIDE ( _Level3InterruptVector_text_end = 0x400001c6 ); +PROVIDE ( _Level3InterruptVector_text_start = 0x400001c0 ); +PROVIDE ( _Level3Vector = 0x400001c0 ); +PROVIDE ( _Level4FromVector = 0x4000762c ); +PROVIDE ( _Level4HandlerLabel = 0x00000000 ); +PROVIDE ( _Level4InterruptVector_text_end = 0x40000206 ); +PROVIDE ( _Level4InterruptVector_text_start = 0x40000200 ); +PROVIDE ( _Level4Vector = 0x40000200 ); +PROVIDE ( _Level5FromVector = 0x4000775c ); +PROVIDE ( _Level5HandlerLabel = 0x00000000 ); +PROVIDE ( _Level5InterruptVector_text_end = 0x40000246 ); +PROVIDE ( _Level5InterruptVector_text_start = 0x40000240 ); +PROVIDE ( _Level5Vector = 0x40000240 ); +PROVIDE ( _LevelOneInterrupt = 0x4000740a ); +PROVIDE ( _lit4_end = 0x40000540 ); +PROVIDE ( _lit4_start = 0x40000540 ); +PROVIDE ( lldesc_build_chain = 0x4000907c ); +PROVIDE ( lldesc_num2link = 0x4000916c ); +PROVIDE ( lldesc_set_owner = 0x40009198 ); +PROVIDE ( lldesc_setup = 0x40019ed8 ); +PROVIDE ( main = 0x4000f6c4 ); +PROVIDE ( MD5Final = 0x4000530c ); +PROVIDE ( MD5Init = 0x4000526c ); +PROVIDE ( MD5Update = 0x4000528c ); +PROVIDE ( md5_vector = 0x40005374 ); +PROVIDE ( MemDwnLdStartMsgProc = 0x40011cec ); +PROVIDE ( MemDwnLdStopReqMsgProc = 0x40011d80 ); +PROVIDE ( _memmap_cacheattr_bp_allvalid = 0x22222222 ); +PROVIDE ( _memmap_cacheattr_bp_base = 0x00000220 ); +PROVIDE ( _memmap_cacheattr_bp_strict = 0xfffff22f ); +PROVIDE ( _memmap_cacheattr_bp_trapnull = 0x2222222f ); +PROVIDE ( _memmap_cacheattr_reset = 0x2222211f ); +PROVIDE ( _memmap_cacheattr_unused_mask = 0xfffff00f ); +PROVIDE ( _memmap_cacheattr_wb_allvalid = 0x22222112 ); +PROVIDE ( _memmap_cacheattr_wba_trapnull = 0x2222211f ); +PROVIDE ( _memmap_cacheattr_wb_base = 0x00000110 ); +PROVIDE ( _memmap_cacheattr_wbna_trapnull = 0x2222211f ); +PROVIDE ( _memmap_cacheattr_wb_strict = 0xfffff11f ); +PROVIDE ( _memmap_cacheattr_wb_trapnull = 0x2222211f ); +PROVIDE ( _memmap_cacheattr_wt_allvalid = 0x22222112 ); +PROVIDE ( _memmap_cacheattr_wt_base = 0x00000110 ); +PROVIDE ( _memmap_cacheattr_wt_strict = 0xfffff11f ); +PROVIDE ( _memmap_cacheattr_wt_trapnull = 0x2222211f ); +PROVIDE ( _memmap_vecbase_reset = 0x40000000 ); +PROVIDE ( MemPacketSendReqMsgProc = 0x40011d1c ); +PROVIDE ( multofup = 0x4001bce0 ); +PROVIDE ( must_reset = 0x3ffffcf4 ); +PROVIDE ( mz_adler32 = 0x40002e90 ); +PROVIDE ( mz_crc32 = 0x40002f58 ); +PROVIDE ( mz_free = 0x40002fa4 ); +PROVIDE ( _NMIExceptionVector = 0x400002c0 ); +PROVIDE ( _NMIExceptionVector_text_end = 0x400002c3 ); +PROVIDE ( _NMIExceptionVector_text_start = 0x400002c0 ); +PROVIDE ( __packed = 0x3ffffcec ); +PROVIDE ( phy_get_romfuncs = 0x4000a88c ); +PROVIDE ( _Pri_4_HandlerAddress = 0x3fffed78 ); +PROVIDE ( _Pri_5_HandlerAddress = 0x3fffed7c ); +PROVIDE ( pthread_setcancelstate = 0x40019fa8 ); +PROVIDE ( _putc1 = 0x3ffffd6c ); +PROVIDE ( _putc2 = 0x3ffffd68 ); +PROVIDE ( RcvMsg = 0x40012f10 ); +PROVIDE ( recv_packet = 0x40012de8 ); +PROVIDE ( _ResetHandler = 0x4000044c ); +PROVIDE ( _ResetVector = 0x40000400 ); +PROVIDE ( _ResetVector_literal_end = 0x40000540 ); +PROVIDE ( _ResetVector_literal_start = 0x40000540 ); +PROVIDE ( _ResetVector_text_end = 0x4000053d ); +PROVIDE ( _ResetVector_text_start = 0x40000400 ); +PROVIDE ( _rodata_end = 0x3ffaff2c ); +PROVIDE ( _rodata_start = 0x3ffac600 ); +PROVIDE ( rom_abs_temp = 0x4000c330 ); +PROVIDE ( rom_ant_btrx_cfg = 0x4000a0fc ); +PROVIDE ( rom_ant_bttx_cfg = 0x4000a0c0 ); +PROVIDE ( rom_ant_dft_cfg = 0x40009fc8 ); +PROVIDE ( rom_ant_wifirx_cfg = 0x4000a03c ); +PROVIDE ( rom_ant_wifitx_cfg = 0x40009ff8 ); +PROVIDE ( rom_bb_bss_cbw40_dig = 0x40009a84 ); +PROVIDE ( rom_bb_wdg_cfg = 0x40009eb8 ); +PROVIDE ( rom_bb_wdg_test_en = 0x40009a48 ); +PROVIDE ( rom_bb_wdt_get_status = 0x40009d18 ); +PROVIDE ( rom_bb_wdt_int_enable = 0x40009cd4 ); +PROVIDE ( rom_bb_wdt_rst_enable = 0x40009cb4 ); +PROVIDE ( rom_bb_wdt_timeout_clear = 0x40009cfc ); +PROVIDE ( rom_cbw2040_cfg = 0x4000a550 ); +PROVIDE ( rom_check_noise_floor = 0x40009b4c ); +PROVIDE ( rom_chip_i2c_readReg = 0x4000a8e4 ); +PROVIDE ( rom_chip_i2c_writeReg = 0x4000a960 ); +PROVIDE ( rom_correct_rf_ana_gain = 0x4000d2b4 ); +PROVIDE ( rom_dc_iq_est = 0x4000c414 ); +PROVIDE ( rom_disable_agc = 0x400091cc ); +PROVIDE ( rom_enable_agc = 0x400091e4 ); +PROVIDE ( rom_freq_get_i2c_data = 0x4000bb84 ); +PROVIDE ( rom_freq_i2c_set_wifi_data = 0x4000b948 ); +PROVIDE ( rom_freq_i2c_write_set = 0x4000b3bc ); +PROVIDE ( rom_gen_rx_gain_table = 0x4000a300 ); +PROVIDE ( rom_get_bbgain_db = 0x400094ec ); +PROVIDE ( rom_get_data_sat = 0x40009338 ); +PROVIDE ( rom_get_fm_sar_dout = 0x4000c024 ); +PROVIDE ( rom_get_i2c_read_mask = 0x4000a8c0 ); +PROVIDE ( rom_get_power_db = 0x4000ce28 ); +PROVIDE ( rom_get_pwctrl_correct = 0x4000d470 ); +PROVIDE ( rom_get_rfcal_rxiq_data = 0x4000cab0 ); +PROVIDE ( rom_get_rf_gain_qdb = 0x4000d29c ); +PROVIDE ( rom_get_sar_dout = 0x4000d400 ); +PROVIDE ( rom_i2c_clk_sel = 0x4000a788 ); +PROVIDE ( rom_i2c_readreg = 0x4000a940 ); +PROVIDE ( rom_i2c_readreg_mask = 0x4000a9c4 ); +PROVIDE ( rom_i2c_writereg = 0x4000a9a8 ); +PROVIDE ( rom_i2c_writereg_mask = 0x4000aa00 ); +PROVIDE ( rom_index_to_txbbgain = 0x4000bd10 ); +PROVIDE ( rom_iq_est_disable = 0x4000c3d8 ); +PROVIDE ( rom_iq_est_enable = 0x4000c358 ); +PROVIDE ( rom_linear_to_db = 0x4000cdbc ); +PROVIDE ( rom_loopback_mode_en = 0x40009304 ); +PROVIDE ( rom_mac_enable_bb = 0x40009e48 ); +PROVIDE ( rom_meas_tone_pwr_db = 0x4000ce64 ); +PROVIDE ( rom_mhz2ieee = 0x4000a4e8 ); +PROVIDE ( rom_noise_floor_auto_set = 0x40009ab4 ); +PROVIDE ( rom_pbus_debugmode = 0x4000ac70 ); +PROVIDE ( rom_pbus_force_mode = 0x4000aa6c ); +PROVIDE ( rom_pbus_force_test = 0x4000abd0 ); +PROVIDE ( rom_pbus_rd = 0x4000ac2c ); +PROVIDE ( rom_pbus_rd_addr = 0x4000ab34 ); +PROVIDE ( rom_pbus_rd_shift = 0x4000ab80 ); +PROVIDE ( rom_pbus_rx_dco_cal = 0x4000c49c ); +PROVIDE ( rom_pbus_set_dco = 0x4000ae2c ); +PROVIDE ( rom_pbus_set_rxgain = 0x4000ac98 ); +PROVIDE ( rom_pbus_workmode = 0x4000ac84 ); +PROVIDE ( rom_pbus_xpd_rx_off = 0x4000acfc ); +PROVIDE ( rom_pbus_xpd_rx_on = 0x4000ad30 ); +PROVIDE ( rom_pbus_xpd_tx_off = 0x4000ad84 ); +PROVIDE ( rom_pbus_xpd_tx_on = 0x4000add4 ); +PROVIDE ( rom_phy_ant_init = 0x40009f48 ); +PROVIDE ( rom_phy_byte_to_word = 0x40009d60 ); +PROVIDE ( rom_phy_chan_dump_cfg = 0x4000a180 ); +PROVIDE ( rom_phy_chan_filt_set = 0x4000a614 ); +PROVIDE ( rom_phy_close_pa = 0x4000a810 ); +PROVIDE ( rom_phy_disable_cca = 0x40009208 ); +PROVIDE ( rom_phy_disable_low_rate = 0x4000a2b8 ); +PROVIDE ( rom_phy_enable_cca = 0x40009234 ); +PROVIDE ( rom_phy_enable_low_rate = 0x4000a280 ); +PROVIDE ( rom_phy_freq_correct = 0x4000b0b4 ); +PROVIDE ( rom_phy_get_noisefloor = 0x40009b04 ); +PROVIDE ( rom_phy_get_rx_freq = 0x4000a6ac ); +PROVIDE ( rom_phy_get_tx_rate = 0x40009d50 ); +PROVIDE ( rom_phy_rx11blr_cfg = 0x40009c5c ); +PROVIDE ( rom_phy_rx_sense_set = 0x4000a704 ); +PROVIDE ( rom_phy_set_bbfreq_init = 0x4000d3d0 ); +PROVIDE ( rom_pll_correct_dcap = 0x4000bad4 ); +PROVIDE ( rom_pow_usr = 0x4000924c ); +PROVIDE ( rom_read_hw_noisefloor = 0x40009c38 ); +PROVIDE ( rom_read_sar_dout = 0x4000bfd4 ); +PROVIDE ( rom_restart_cal = 0x4000ae74 ); +PROVIDE ( rom_rfcal_pwrctrl = 0x4000d098 ); +PROVIDE ( rom_rfcal_rxiq = 0x4000ca3c ); +PROVIDE ( rom_rfcal_txcap = 0x4000ccac ); +PROVIDE ( rom_rfpll_set_freq = 0x4000afa4 ); +PROVIDE ( rom_rftx_init = 0x4000b24c ); +PROVIDE ( rom_rx_gain_force = 0x40009558 ); +PROVIDE ( rom_rxiq_cover_mg_mp = 0x4000c954 ); +PROVIDE ( rom_rxiq_get_mis = 0x4000c7d8 ); +PROVIDE ( rom_rxiq_set_reg = 0x4000c8ec ); +PROVIDE ( rom_set_cal_rxdc = 0x400092c4 ); +PROVIDE ( rom_set_cca = 0x4000a59c ); +PROVIDE ( rom_set_chan_cal_interp = 0x4000cba4 ); +PROVIDE ( rom_set_channel_freq = 0x4000b00c ); +PROVIDE ( rom_set_loopback_gain = 0x40009268 ); +PROVIDE ( rom_set_noise_floor = 0x40009bf4 ); +PROVIDE ( rom_set_pbus_mem = 0x40009380 ); +PROVIDE ( rom_set_rf_freq_offset = 0x4000b214 ); +PROVIDE ( rom_set_rxclk_en = 0x400095cc ); +PROVIDE ( rom_set_txcap_reg = 0x4000cc34 ); +PROVIDE ( rom_set_txclk_en = 0x4000959c ); +PROVIDE ( rom_set_tx_dig_gain = 0x40009514 ); +PROVIDE ( rom_set_xpd_sar = 0x40009f08 ); +PROVIDE ( rom_spur_cal = 0x4000a47c ); +PROVIDE ( rom_spur_reg_write_one_tone = 0x400097c4 ); +PROVIDE ( rom_start_tx_tone = 0x400096f0 ); +PROVIDE ( rom_start_tx_tone_step = 0x40009608 ); +PROVIDE ( rom_stop_tx_tone = 0x4000a428 ); +PROVIDE ( _rom_store = 0x4001bed0 ); +PROVIDE ( _rom_store_table = 0x4001bd64 ); +PROVIDE ( rom_target_power_add_backoff = 0x4000d278 ); +PROVIDE ( rom_txbbgain_to_index = 0x4000bce0 ); +PROVIDE ( rom_txcal_work_mode = 0x4000bf30 ); +PROVIDE ( rom_txdc_cal_init = 0x4000bd2c ); +PROVIDE ( rom_txdc_cal_v70 = 0x4000bdc0 ); +PROVIDE ( rom_txiq_cover = 0x4000c1ac ); +PROVIDE ( rom_txiq_get_mis_pwr = 0x4000c0f8 ); +PROVIDE ( rom_txiq_set_reg = 0x4000bf64 ); +PROVIDE ( rom_tx_paon_set = 0x40009db8 ); +PROVIDE ( rom_tx_pwr_backoff = 0x4000ceb8 ); +PROVIDE ( rom_txtone_linear_pwr = 0x4000c0b0 ); +PROVIDE ( rom_usb_dev = 0x3ffffb9c ); /* static "usb_dev" */ +PROVIDE ( rom_usb_dev_end = 0x3ffffc78 ); /* end of "usb_dev" */ +PROVIDE ( rom_usb_dw_ctrl = 0x3ffffa74 ); /* static "usb_dw_ctrl" */ +PROVIDE ( rom_usb_dw_ctrl_end = 0x3ffffb9c ); /* end of "usb_dw_ctrl" */ +PROVIDE ( rom_usb_curr_desc = 0x3ffffa54 ); /* static "s_curr_descr" */ +PROVIDE ( rom_wait_rfpll_cal_end = 0x4000af3c ); +PROVIDE ( rom_wifi_11g_rate_chg = 0x4000d260 ); +PROVIDE ( rom_wifi_rifs_mode_en = 0x40009d2c ); +PROVIDE ( rom_write_dac_gain2 = 0x4000a210 ); +PROVIDE ( rom_write_gain_mem = 0x400094bc ); +PROVIDE ( rom_write_pll_cap_mem = 0x4000ba58 ); +PROVIDE ( rom_write_rfpll_sdm = 0x4000aed4 ); +PROVIDE ( rom_wr_rf_freq_mem = 0x4000b2f0 ); +PROVIDE ( roundup2 = 0x4001bcd0 ); +PROVIDE ( rtc_boot_control = 0x4001002c ); +PROVIDE ( rtc_get_reset_reason = 0x4000ff58 ); +PROVIDE ( rtc_get_wakeup_cause = 0x4000ff7c ); +PROVIDE ( rtc_select_apb_bridge = 0x400100a0 ); +PROVIDE ( s_cdcacm_old_rts = 0x3ffffd34 ); +PROVIDE ( SelectSpiFunction = 0x40015d08 ); +PROVIDE ( SelectSpiQIO = 0x40015b88 ); +PROVIDE ( SendMsg = 0x40012d0c ); +PROVIDE ( send_packet = 0x40012cc8 ); +PROVIDE ( set_rtc_memory_crc = 0x40010010 ); +PROVIDE ( SetSpiDrvs = 0x40015c18 ); +PROVIDE ( sig_matrix = 0x3ffffd57 ); +PROVIDE ( software_reset = 0x40010068 ); +PROVIDE ( software_reset_cpu = 0x40010080 ); +PROVIDE ( SPI_block_erase = 0x4001623c ); +PROVIDE ( spi_cache_mode_switch = 0x40016a00 ); +PROVIDE ( SPI_chip_erase = 0x400161b8 ); +PROVIDE ( SPIClkConfig = 0x400170a0 ); +PROVIDE ( SPI_Common_Command = 0x400162e8 ); +PROVIDE ( spi_common_set_flash_cs_timing = 0x40016c0c ); +PROVIDE ( spi_dummy_len_fix = 0x40015b50 ); +PROVIDE ( SPI_Encrypt_Write = 0x400177e0 ); +PROVIDE ( SPI_Encrypt_Write_Dest = 0x400176cc ); +PROVIDE ( SPIEraseArea = 0x40017470 ); +PROVIDE ( SPIEraseBlock = 0x4001710c ); +PROVIDE ( SPIEraseChip = 0x400170ec ); +PROVIDE ( SPIEraseSector = 0x4001716c ); +PROVIDE ( esp_rom_spiflash_attach = 0x40017004 ); +PROVIDE ( spi_flash_boot_attach = 0x40016fc0 ); +PROVIDE ( spi_flash_check_suspend_cb = 0x3ffffd58 ); +PROVIDE ( SPI_flashchip_data = 0x3ffffd3c ); +PROVIDE ( spi_flash_set_check_suspend_cb = 0x40015b3c ); +PROVIDE ( SPI_init = 0x40016ce8 ); +PROVIDE ( SPILock = 0x40016ed4 ); +PROVIDE ( SPIMasterReadModeCnfig = 0x40017014 ); +PROVIDE ( SPI_page_program = 0x400165a8 ); +PROVIDE ( SPIParamCfg = 0x40017500 ); +PROVIDE ( SPIRead = 0x4001728c ); +PROVIDE ( SPI_read_data = 0x40015ed8 ); +PROVIDE ( SPIReadModeCnfig = 0x40016f1c ); +PROVIDE ( SPI_read_status = 0x40016084 ); +PROVIDE ( SPI_read_status_high = 0x40016284 ); +PROVIDE ( SPI_sector_erase = 0x400161ec ); +PROVIDE ( spi_slave_download = 0x4001998c ); +PROVIDE ( spi_slave_rom_check_conn = 0x40019724 ); +PROVIDE ( spi_slave_rom_init = 0x40019774 ); +PROVIDE ( spi_slave_rom_init_hw = 0x40019b5c ); +PROVIDE ( spi_slave_rom_intr_enable = 0x40019b3c ); +PROVIDE ( spi_slave_rom_rxdma_load = 0x40019da8 ); +PROVIDE ( spi_slave_rom_txdma_load = 0x40019e3c ); +PROVIDE ( SPIUnlock = 0x40016e88 ); +PROVIDE ( SPI_user_command_read = 0x40015fc8 ); +PROVIDE ( SPI_Wait_Idle = 0x40016680 ); +PROVIDE ( SPI_WakeUp = 0x400160f4 ); +PROVIDE ( SPIWrite = 0x400171cc ); +PROVIDE ( SPI_write_enable = 0x4001655c ); +PROVIDE ( SPI_Write_Encrypt_Disable = 0x40017694 ); +PROVIDE ( SPI_Write_Encrypt_Enable = 0x40017678 ); +PROVIDE ( SPI_write_status = 0x400162a4 ); +PROVIDE ( __stack = 0x3fffe710 ); +PROVIDE ( _stack_sentry = 0x3fffc410 ); +PROVIDE ( _start = 0x4000726c ); +PROVIDE ( _stext = 0x40007118 ); +PROVIDE ( string0_descr = 0x3ffaeeae ); +PROVIDE ( str_manu_descr = 0x3ffaee9a ); +PROVIDE ( str_prod_descr = 0x3ffaee88 ); +PROVIDE ( str_serial_descr = 0x3ffaee84 ); +PROVIDE ( rom_usb_osglue = 0x3ffffcdc ); +PROVIDE ( _SyscallException = 0x4000732a ); +PROVIDE ( syscall_table_ptr_pro = 0x3ffffd78 ); +PROVIDE ( tdefl_compress = 0x400041dc ); +PROVIDE ( tdefl_compress_buffer = 0x40004938 ); +PROVIDE ( tdefl_compress_mem_to_mem = 0x40004a50 ); +PROVIDE ( tdefl_compress_mem_to_output = 0x40004a30 ); +PROVIDE ( tdefl_get_adler32 = 0x40004a28 ); +PROVIDE ( tdefl_get_prev_return_status = 0x40004a20 ); +PROVIDE ( tdefl_init = 0x40004954 ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x40004a64 ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40004a58 ); +PROVIDE ( _text_end = 0x4001bed0 ); +PROVIDE ( _text_start = 0x40007118 ); +PROVIDE ( tinfl_decompress = 0x40003000 ); +PROVIDE ( tinfl_decompress_mem_to_callback = 0x400041a8 ); +PROVIDE ( tinfl_decompress_mem_to_mem = 0x40004168 ); +PROVIDE ( uart_acm_dev = 0x3ffffcf8 ); +PROVIDE ( uartAttach = 0x40012890 ); +PROVIDE ( uart_baudrate_detect = 0x400128f0 ); +PROVIDE ( uart_buff_switch = 0x40012d64 ); +PROVIDE ( UartConnCheck = 0x40011ab4 ); +PROVIDE ( UartConnectProc = 0x40011da8 ); +PROVIDE ( UartDev = 0x3ffffcfc ); +PROVIDE ( uart_div_modify = 0x40012984 ); +PROVIDE ( uart_div_reinit = 0x400129d0 ); +PROVIDE ( UartDwnLdProc = 0x400121ac ); +PROVIDE ( UartGetCmdLn = 0x40012f28 ); +PROVIDE ( Uart_Init = 0x40012a04 ); +PROVIDE ( Uart_Init_USB = 0x40012818 ); +PROVIDE ( UartRegReadProc = 0x40011df8 ); +PROVIDE ( UartRegWriteProc = 0x40011db8 ); +PROVIDE ( uart_rx_intr_handler = 0x40012690 ); +PROVIDE ( uart_rx_one_char = 0x40012bf0 ); +PROVIDE ( uart_rx_one_char_block = 0x40012b9c ); +PROVIDE ( uart_rx_readbuff = 0x40012d1c ); +PROVIDE ( UartRxString = 0x40012c84 ); +PROVIDE ( UartSecureDwnLdProc = 0x40012464 ); +PROVIDE ( UartSetBaudProc = 0x40011e54 ); +PROVIDE ( UartSpiAttachProc = 0x40011e0c ); +PROVIDE ( UartSpiReadProc = 0x40011e28 ); +PROVIDE ( uart_tx_flush = 0x40012b40 ); +PROVIDE ( uart_tx_one_char = 0x40012b10 ); +PROVIDE ( uart_tx_one_char2 = 0x40012b28 ); +PROVIDE ( uart_tx_switch = 0x400128e4 ); +PROVIDE ( uart_tx_wait_idle = 0x40012b6c ); +PROVIDE ( uart_usb_enable_reset_on_rts = 0x40012858 ); +PROVIDE ( Uart_USB_Send_Testament = 0x400127d8 ); +PROVIDE ( usb_cancel_transfer = 0x40015200 ); +PROVIDE ( usb_data_stuff = 0x3ffacc88 ); +PROVIDE ( usb_dc_attach = 0x40013ecc ); +PROVIDE ( usb_dc_check_poll_for_interrupts = 0x40014980 ); +PROVIDE ( usb_dc_detach = 0x40014010 ); +PROVIDE ( usb_dc_ep_check_cap = 0x40014094 ); +PROVIDE ( usb_dc_ep_clear_stall = 0x400142f0 ); +PROVIDE ( usb_dc_ep_configure = 0x400140d8 ); +PROVIDE ( usb_dc_ep_disable = 0x400144ec ); +PROVIDE ( usb_dc_ep_enable = 0x4001442c ); +PROVIDE ( usb_dc_ep_flush = 0x400145b8 ); +PROVIDE ( usb_dc_ep_halt = 0x4001435c ); +PROVIDE ( usb_dc_ep_is_stalled = 0x400143bc ); +PROVIDE ( usb_dc_ep_mps = 0x40014958 ); +PROVIDE ( usb_dc_ep_read = 0x400148d8 ); +PROVIDE ( usb_dc_ep_read_continue = 0x40014898 ); +PROVIDE ( usb_dc_ep_read_wait = 0x400147bc ); +PROVIDE ( usb_dc_ep_set_callback = 0x40014910 ); +PROVIDE ( usb_dc_ep_set_stall = 0x40014290 ); +PROVIDE ( usb_dc_ep_write = 0x40014684 ); +PROVIDE ( usb_dc_ep_write_would_block = 0x40014624 ); +PROVIDE ( usb_dc_prepare_persist = 0x40013bec ); +PROVIDE ( usb_dc_reset = 0x40014044 ); +PROVIDE ( usb_dc_set_address = 0x4001405c ); +PROVIDE ( usb_dc_set_status_callback = 0x4001494c ); +PROVIDE ( usb_deconfig = 0x40014fa8 ); +PROVIDE ( usb_dev_get_configuration = 0x40014f4c ); +PROVIDE ( usb_dev_resume = 0x40014f38 ); +PROVIDE ( usb_dfu_force_detach = 0x400155b0 ); +PROVIDE ( usb_dfu_init = 0x40015598 ); +PROVIDE ( usb_dfu_set_detach_cb = 0x400152dc ); +PROVIDE ( usb_disable = 0x40015058 ); +PROVIDE ( usb_dw_isr_handler = 0x40013c48 ); +PROVIDE ( usb_enable = 0x40014fc8 ); +PROVIDE ( usb_ep_clear_stall = 0x400150c8 ); +PROVIDE ( usb_ep_read_continue = 0x400150f0 ); +PROVIDE ( usb_ep_read_wait = 0x400150d8 ); +PROVIDE ( usb_ep_set_stall = 0x400150b8 ); +PROVIDE ( usb_get_descriptor = 0x400149c0 ); +PROVIDE ( usb_read = 0x400150a0 ); +PROVIDE ( usb_set_config = 0x40014f64 ); +PROVIDE ( usb_set_current_descriptor = 0x400149a8 ); +PROVIDE ( usb_transfer = 0x40015150 ); +PROVIDE ( usb_transfer_ep_callback = 0x40015100 ); +PROVIDE ( usb_transfer_sync = 0x40015250 ); +PROVIDE ( usb_write = 0x40015088 ); +PROVIDE ( usb_write_would_block = 0x40015078 ); +PROVIDE ( user_code_start = 0x3fffe714 ); +PROVIDE ( _UserExceptionVector = 0x40000340 ); +PROVIDE ( _UserExceptionVector_text_end = 0x40000357 ); +PROVIDE ( _UserExceptionVector_text_start = 0x40000340 ); +PROVIDE ( VerifyFlashMd5Proc = 0x40012004 ); +PROVIDE ( Wait_SPI_Idle = 0x40016188 ); +PROVIDE ( _WindowOverflow12 = 0x40000100 ); +PROVIDE ( _WindowOverflow4 = 0x40000000 ); +PROVIDE ( _WindowOverflow8 = 0x40000080 ); +PROVIDE ( _WindowUnderflow12 = 0x40000140 ); +PROVIDE ( _WindowUnderflow4 = 0x40000040 ); +PROVIDE ( _WindowUnderflow8 = 0x400000c0 ); +PROVIDE ( _WindowVectors_text_end = 0x40000170 ); +PROVIDE ( _WindowVectors_text_start = 0x40000000 ); +PROVIDE ( __XT_EXCEPTION_DESCS__ = 0x3ffaff2c ); +PROVIDE ( __XT_EXCEPTION_DESCS_END__ = 0x3ffaff2c ); +PROVIDE ( __XT_EXCEPTION_TABLE__ = 0x3ffafe3a ); +PROVIDE ( xthal_bcopy = 0x4001a918 ); +PROVIDE ( xthal_copy123 = 0x4001a9ac ); +PROVIDE ( xthal_get_ccompare = 0x4001aabc ); +PROVIDE ( xthal_get_ccount = 0x4001aa90 ); +PROVIDE ( xthal_get_interrupt = 0x4001aadc ); +PROVIDE ( Xthal_intlevel = 0x3ffaf06c ); +PROVIDE ( xthal_memcpy = 0x4001a93c ); +PROVIDE ( xthal_set_ccompare = 0x4001aa98 ); +PROVIDE ( xthal_set_intclear = 0x4001aae4 ); +PROVIDE ( xthals_hw_configid0 = 0xc2ecfafe ); +PROVIDE ( xthals_hw_configid1 = 0x224787b1 ); +PROVIDE ( xthals_release_major = 0x00002ee0 ); +PROVIDE ( xthals_release_minor = 0x00000009 ); +PROVIDE ( _xtos_alloca_handler = 0x40000010 ); +PROVIDE ( xtos_cause3_handler = 0x40007370 ); +PROVIDE ( xtos_c_handler_table = 0x3fffec78 ); +PROVIDE ( xtos_c_wrapper_handler = 0x40007380 ); +PROVIDE ( _xtos_enabled = 0x3fffed80 ); +PROVIDE ( xtos_exc_handler_table = 0x3fffeb78 ); +PROVIDE ( xtos_interrupt_mask_table = 0x3fffee88 ); +PROVIDE ( xtos_interrupt_table = 0x3fffed88 ); +PROVIDE ( _xtos_ints_off = 0x4001a3e0 ); +PROVIDE ( _xtos_ints_on = 0x4001a3bc ); +PROVIDE ( _xtos_intstruct = 0x3fffed80 ); +PROVIDE ( _xtos_l1int_handler = 0x400073ec ); +PROVIDE ( xtos_p_none = 0x4001a8a0 ); +PROVIDE ( _xtos_restore_intlevel = 0x400074cc ); +PROVIDE ( _xtos_return_from_exc = 0x4001a8a8 ); +PROVIDE ( _xtos_set_exception_handler = 0x400072b4 ); +PROVIDE ( _xtos_set_interrupt_handler = 0x4001a380 ); +PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4001a344 ); +PROVIDE ( _xtos_set_intlevel = 0x4001a8c0 ); +PROVIDE ( _xtos_set_min_intlevel = 0x4001a8dc ); +PROVIDE ( _xtos_set_vpri = 0x400074d8 ); +PROVIDE ( _xtos_syscall_handler = 0x400072fc ); +PROVIDE ( xtos_unhandled_exception = 0x4001a900 ); +PROVIDE ( xtos_unhandled_interrupt = 0x4001a910 ); +PROVIDE ( _xtos_vectors_ref_ = 0x00000000 ); +PROVIDE ( _xtos_vpri_enabled = 0x3fffed84 ); +PROVIDE ( memchr = 0x4001ab24 ); +PROVIDE ( memcmp = 0x4001ab40 ); +PROVIDE ( memcpy = 0x4001aba8 ); +PROVIDE ( memmove = 0x4001acb0 ); +PROVIDE ( memrchr = 0x4001acec ); +PROVIDE ( memset = 0x4001ad3c ); +PROVIDE ( strchr = 0x4001adb0 ); +PROVIDE ( strcmp = 0x40007be4 ); +PROVIDE ( strcpy = 0x40007cfc ); +PROVIDE ( strlcpy = 0x4001adf8 ); +PROVIDE ( strncpy = 0x40007f20 ); +PROVIDE ( strlen = 0x40007e08 ); +PROVIDE ( strnlen = 0x4001ae9c ); diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/Make.defs b/boards/xtensa/esp32s2/esp32s2-saola-1/src/Make.defs new file mode 100644 index 00000000000..cf1df5706b1 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# boards/xtensa/esp32s2/esp32s2-saola-1/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +SCRIPTDIR = $(BOARD_DIR)$(DELIM)scripts + +CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h + +CSRCS = esp32s2_boot.c esp32s2_bringup.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += esp32s2_appinit.c +endif + +SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32s2.template.ld +SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32s2_out.ld + +.PHONY = context distclean + +$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE) + $(Q) $(CC) -isystem $(TOPDIR)/include -C -P -x c -E $(SCRIPTIN) -o $@ + +context:: $(SCRIPTOUT) + +distclean:: + $(call DELFILE, $(SCRIPTOUT)) + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) + diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h new file mode 100644 index 00000000000..c51409441d7 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32S2_ESP32S2_SAOLA_1_SRC_ESP32S2_SAOLA_1_H +#define __BOARDS_XTENSA_ESP32S2_ESP32S2_SAOLA_1_SRC_ESP32S2_SAOLA_1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ESP32S2-DevKitC GPIOs ****************************************************/ + +/* BOOT Button */ + +#define BUTTON_BOOT 0 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via board_app_initialize() + * + ****************************************************************************/ + +int esp32s2_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_XTENSA_ESP32S2_ESP32S2_SAOLA_1_SRC_ESP32S2_SAOLA_1_H */ diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_appinit.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_appinit.c new file mode 100644 index 00000000000..94eef2d5d4b --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_appinit.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp32s2-saola-1.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp32s2_bringup(); +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_boot.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_boot.c new file mode 100644 index 00000000000..857ba140354 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_boot.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "esp32s2-saola-1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_board_initialize + * + * Description: + * All ESP32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void esp32s2_board_initialize(void) +{ +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + esp32s2_bringup(); +} +#endif diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c new file mode 100644 index 00000000000..171172eb672 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "esp32s2-saola-1.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int esp32s2_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", + CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = esp32s2_gpio_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + UNUSED(ret); + return OK; +} diff --git a/boards/z16/z16f/z16f2800100zcog/configs/nsh/defconfig b/boards/z16/z16f/z16f2800100zcog/configs/nsh/defconfig index 20e9946594a..853c0f787b7 100644 --- a/boards/z16/z16f/z16f2800100zcog/configs/nsh/defconfig +++ b/boards/z16/z16f/z16f2800100zcog/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_ARCH_Z16=y CONFIG_BOARD_LOOPSPERMSEC=1250 CONFIG_BUILTIN=y CONFIG_ENDIAN_BIG=y -CONFIG_MAX_TASKS=16 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y diff --git a/boards/z16/z16f/z16f2800100zcog/configs/ostest/defconfig b/boards/z16/z16f/z16f2800100zcog/configs/ostest/defconfig index 0a9aab8ce8b..cac2649d7ea 100644 --- a/boards/z16/z16f/z16f2800100zcog/configs/ostest/defconfig +++ b/boards/z16/z16f/z16f2800100zcog/configs/ostest/defconfig @@ -17,7 +17,6 @@ CONFIG_CONSOLE_SYSLOG=y CONFIG_ENDIAN_BIG=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_RAM_SIZE=65536 diff --git a/boards/z80/ez80/ez80f910200kitg/configs/ostest/defconfig b/boards/z80/ez80/ez80f910200kitg/configs/ostest/defconfig index edf2238c535..84408580282 100644 --- a/boards/z80/ez80/ez80f910200kitg/configs/ostest/defconfig +++ b/boards/z80/ez80/ez80f910200kitg/configs/ostest/defconfig @@ -22,7 +22,6 @@ CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_PTHREAD=y CONFIG_EZ80_UART0=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_MMCSD=y CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/z80/ez80/ez80f910200zco/configs/dhcpd/defconfig b/boards/z80/ez80/ez80f910200zco/configs/dhcpd/defconfig index ed74ce38dc6..b817d81c45a 100644 --- a/boards/z80/ez80/ez80f910200zco/configs/dhcpd/defconfig +++ b/boards/z80/ez80/ez80f910200zco/configs/dhcpd/defconfig @@ -27,7 +27,6 @@ CONFIG_EZ80_EMAC=y CONFIG_EZ80_PHYCONFIG=1 CONFIG_EZ80_UART0=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_NET=y CONFIG_NETUTILS_DHCPD=y CONFIG_NETUTILS_NETLIB=y diff --git a/boards/z80/ez80/ez80f910200zco/configs/httpd/defconfig b/boards/z80/ez80/ez80f910200zco/configs/httpd/defconfig index 54f51e8e4fb..188f526eb67 100644 --- a/boards/z80/ez80/ez80f910200zco/configs/httpd/defconfig +++ b/boards/z80/ez80/ez80f910200zco/configs/httpd/defconfig @@ -24,7 +24,6 @@ CONFIG_EZ80_EMAC=y CONFIG_EZ80_PHYCONFIG=1 CONFIG_EZ80_UART0=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NETUTILS_WEBSERVER=y diff --git a/boards/z80/ez80/ez80f910200zco/configs/nettest/defconfig b/boards/z80/ez80/ez80f910200zco/configs/nettest/defconfig index 04e8530f9ae..7330a11208a 100644 --- a/boards/z80/ez80/ez80f910200zco/configs/nettest/defconfig +++ b/boards/z80/ez80/ez80f910200zco/configs/nettest/defconfig @@ -26,7 +26,6 @@ CONFIG_EZ80_EMAC=y CONFIG_EZ80_PHYCONFIG=1 CONFIG_EZ80_UART0=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NET_ICMP=y diff --git a/boards/z80/ez80/ez80f910200zco/configs/nsh/defconfig b/boards/z80/ez80/ez80f910200zco/configs/nsh/defconfig index 84c69be96ff..743420408ef 100644 --- a/boards/z80/ez80/ez80f910200zco/configs/nsh/defconfig +++ b/boards/z80/ez80/ez80f910200zco/configs/nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_EZ80_EMAC=y CONFIG_EZ80_PHYCONFIG=1 CONFIG_EZ80_UART0=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 diff --git a/boards/z80/ez80/ez80f910200zco/configs/poll/defconfig b/boards/z80/ez80/ez80f910200zco/configs/poll/defconfig index 248780e4376..328e2f5d1bf 100644 --- a/boards/z80/ez80/ez80f910200zco/configs/poll/defconfig +++ b/boards/z80/ez80/ez80f910200zco/configs/poll/defconfig @@ -25,7 +25,6 @@ CONFIG_EZ80_EMAC=y CONFIG_EZ80_PHYCONFIG=1 CONFIG_EZ80_UART0=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_NET=y CONFIG_NETUTILS_NETLIB=y CONFIG_NET_ICMP=y diff --git a/boards/z80/ez80/makerlisp/configs/nsh_flash/defconfig b/boards/z80/ez80/makerlisp/configs/nsh_flash/defconfig index 08258dac409..94d5e89d7b4 100644 --- a/boards/z80/ez80/makerlisp/configs/nsh_flash/defconfig +++ b/boards/z80/ez80/makerlisp/configs/nsh_flash/defconfig @@ -27,7 +27,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/z80/ez80/makerlisp/configs/nsh_ram/defconfig b/boards/z80/ez80/makerlisp/configs/nsh_ram/defconfig index 32cc23b8ce2..b59ef5e5271 100644 --- a/boards/z80/ez80/makerlisp/configs/nsh_ram/defconfig +++ b/boards/z80/ez80/makerlisp/configs/nsh_ram/defconfig @@ -28,7 +28,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/z80/ez80/makerlisp/configs/sdboot/defconfig b/boards/z80/ez80/makerlisp/configs/sdboot/defconfig index c343c8bf259..7367a6c252c 100644 --- a/boards/z80/ez80/makerlisp/configs/sdboot/defconfig +++ b/boards/z80/ez80/makerlisp/configs/sdboot/defconfig @@ -27,7 +27,6 @@ CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_LIB_HEX2BIN=y CONFIG_MAKERLISP_SDBOOT=y -CONFIG_MAX_TASKS=8 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 diff --git a/boards/z80/ez80/z20x/configs/hello/defconfig b/boards/z80/ez80/z20x/configs/hello/defconfig index e15986b3411..cfb12cf7bd4 100644 --- a/boards/z80/ez80/z20x/configs/hello/defconfig +++ b/boards/z80/ez80/z20x/configs/hello/defconfig @@ -21,7 +21,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_HELLO=y CONFIG_EZ80_UART1=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_RAM_SIZE=65536 diff --git a/boards/z80/ez80/z20x/configs/nsh/defconfig b/boards/z80/ez80/z20x/configs/nsh/defconfig index 1e32d93d0f5..61776ad50fd 100644 --- a/boards/z80/ez80/z20x/configs/nsh/defconfig +++ b/boards/z80/ez80/z20x/configs/nsh/defconfig @@ -28,7 +28,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=16 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/z80/ez80/z20x/configs/sdboot/defconfig b/boards/z80/ez80/z20x/configs/sdboot/defconfig index 94a543c9f78..93555aa5a21 100644 --- a/boards/z80/ez80/z20x/configs/sdboot/defconfig +++ b/boards/z80/ez80/z20x/configs/sdboot/defconfig @@ -25,7 +25,6 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_MMCSD=y CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 diff --git a/boards/z80/ez80/z20x/configs/w25boot/defconfig b/boards/z80/ez80/z20x/configs/w25boot/defconfig index ef77523100f..2ceaee09477 100644 --- a/boards/z80/ez80/z20x/configs/w25boot/defconfig +++ b/boards/z80/ez80/z20x/configs/w25boot/defconfig @@ -20,7 +20,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EZ80_SPI=y CONFIG_EZ80_UART1=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_MTD=y CONFIG_MTD_W25=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 diff --git a/boards/z80/z180/p112/configs/ostest/defconfig b/boards/z80/z180/p112/configs/ostest/defconfig index 1b8faadd86b..bb71518c28f 100644 --- a/boards/z80/z180/p112/configs/ostest/defconfig +++ b/boards/z80/z180/p112/configs/ostest/defconfig @@ -22,7 +22,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y CONFIG_GRAN=y CONFIG_HOST_WINDOWS=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=3 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/z80/z8/z8encore000zco/configs/ostest/defconfig b/boards/z80/z8/z8encore000zco/configs/ostest/defconfig index 4aac4208289..11b63c1025c 100644 --- a/boards/z80/z8/z8encore000zco/configs/ostest/defconfig +++ b/boards/z80/z8/z8encore000zco/configs/ostest/defconfig @@ -23,7 +23,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=256 -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=3 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/z80/z8/z8f64200100kit/configs/ostest/defconfig b/boards/z80/z8/z8f64200100kit/configs/ostest/defconfig index 638a171d0c7..48ca2cb32a2 100644 --- a/boards/z80/z8/z8f64200100kit/configs/ostest/defconfig +++ b/boards/z80/z8/z8f64200100kit/configs/ostest/defconfig @@ -22,7 +22,6 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y CONFIG_HOST_WINDOWS=y CONFIG_IDLETHREAD_STACKSIZE=256 -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=3 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/boards/z80/z80/z80sim/configs/nsh/defconfig b/boards/z80/z80/z80sim/configs/nsh/defconfig index f17dcf7f097..c61270b8913 100644 --- a/boards/z80/z80/z80sim/configs/nsh/defconfig +++ b/boards/z80/z80/z80sim/configs/nsh/defconfig @@ -30,7 +30,6 @@ CONFIG_DEFAULT_SMALL=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_LINELEN=40 diff --git a/boards/z80/z80/z80sim/configs/ostest/defconfig b/boards/z80/z80/z80sim/configs/ostest/defconfig index f39174e0319..5f6c7288742 100644 --- a/boards/z80/z80/z80sim/configs/ostest/defconfig +++ b/boards/z80/z80/z80sim/configs/ostest/defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_SMALL=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_PTHREAD=y -CONFIG_MAX_TASKS=8 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=3 CONFIG_NUNGET_CHARS=0 CONFIG_PREALLOC_TIMERS=0 diff --git a/crypto/crypto.c b/crypto/crypto.c index 66b20873941..1b01ab547c3 100644 --- a/crypto/crypto.c +++ b/crypto/crypto.c @@ -1,35 +1,20 @@ /**************************************************************************** * crypto/crypto.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Max Nekludov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -43,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/crypto/cryptodev.c b/crypto/cryptodev.c index b67d9ecbdd7..c6e5c6bae56 100644 --- a/crypto/cryptodev.c +++ b/crypto/cryptodev.c @@ -1,35 +1,20 @@ /**************************************************************************** * crypto/cryptodev.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Max Nekludov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/crypto/random_pool.c b/crypto/random_pool.c index 985d3121bca..bdb109c960b 100644 --- a/crypto/random_pool.c +++ b/crypto/random_pool.c @@ -323,7 +323,7 @@ static void rng_reseed(void) g_rng.output_initialized = true; } -static void rng_buf_internal(FAR void *bytes, size_t nbytes) +static void rng_buf_internal(FAR uint8_t *bytes, size_t nbytes) { if (!g_rng.output_initialized) { diff --git a/crypto/testmngr.c b/crypto/testmngr.c index d002e6d5c6b..4f5489ccfc8 100644 --- a/crypto/testmngr.c +++ b/crypto/testmngr.c @@ -1,35 +1,20 @@ /**************************************************************************** * crypto/testmngr.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. - * Author: Max Nekludov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/crypto/testmngr.h b/crypto/testmngr.h index f2c559c6cc1..f8e79e330d7 100644 --- a/crypto/testmngr.h +++ b/crypto/testmngr.h @@ -1,35 +1,20 @@ /**************************************************************************** * crypto/testmngr.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Max Nekludov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/1wire/1wire.c b/drivers/1wire/1wire.c index 13a3a188ff8..7e18014707a 100644 --- a/drivers/1wire/1wire.c +++ b/drivers/1wire/1wire.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -541,7 +542,7 @@ int onewire_search(FAR struct onewire_master_s *master, DEBUGASSERT(master->insearch == false); - /* Make complete search on the bus mutal exlusive */ + /* Make complete search on the bus mutal exclusive */ ret = onewire_sem_wait(master); if (ret < 0) diff --git a/drivers/1wire/1wire_internal.h b/drivers/1wire/1wire_internal.h index 86812f9cd18..5ded0971f6d 100644 --- a/drivers/1wire/1wire_internal.h +++ b/drivers/1wire/1wire_internal.h @@ -81,7 +81,7 @@ struct onewire_slave_s * Public Function Prototypes ****************************************************************************/ -/* Aditional CRC helpers from 1wire_crc.c */ +/* Additional CRC helpers from 1wire_crc.c */ bool onewire_valid_rom(uint64_t rom); diff --git a/drivers/1wire/ds28e17.c b/drivers/1wire/ds28e17.c index 3d6602d5bf8..de8ebdab542 100644 --- a/drivers/1wire/ds28e17.c +++ b/drivers/1wire/ds28e17.c @@ -39,6 +39,7 @@ #include +#include #include #include #include diff --git a/drivers/addrenv.c b/drivers/addrenv.c index ae4968baf0d..dd4d78494bd 100644 --- a/drivers/addrenv.c +++ b/drivers/addrenv.c @@ -68,7 +68,7 @@ void simple_addrenv_initialize(FAR const struct simple_addrenv_s *addrenv) FAR void *up_addrenv_pa_to_va(uintptr_t pa) { FAR struct simple_addrenv_node_s *node; - FAR struct simple_addrenv_s *addrenv; + FAR const struct simple_addrenv_s *addrenv; uint32_t i; list_for_every_entry(&g_addrenv_list, node, @@ -91,7 +91,7 @@ FAR void *up_addrenv_pa_to_va(uintptr_t pa) uintptr_t up_addrenv_va_to_pa(FAR void *va_) { FAR struct simple_addrenv_node_s *node; - FAR struct simple_addrenv_s *addrenv; + FAR const struct simple_addrenv_s *addrenv; uintptr_t va = C2B((uintptr_t)va_); uint32_t i; diff --git a/drivers/analog/adc.c b/drivers/analog/adc.c index 6797ed7457e..1b16f9428f8 100644 --- a/drivers/analog/adc.c +++ b/drivers/analog/adc.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -71,6 +72,7 @@ static int adc_close(FAR struct file *filep); static ssize_t adc_read(FAR struct file *fielp, FAR char *buffer, size_t buflen); static int adc_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int adc_reset(FAR struct adc_dev_s *dev); static int adc_receive(FAR struct adc_dev_s *dev, uint8_t ch, int32_t data); static void adc_notify(FAR struct adc_dev_s *dev); @@ -97,7 +99,8 @@ static const struct file_operations g_adc_fops = static const struct adc_callback_s g_adc_callback = { - adc_receive /* au_receive */ + adc_receive, /* au_receive */ + adc_reset /* au_reset */ }; /**************************************************************************** @@ -157,6 +160,10 @@ static int adc_open(FAR struct file *filep) dev->ad_recv.af_head = 0; dev->ad_recv.af_tail = 0; + /* Clear overrun indicator */ + + dev->ad_isovr = false; + /* Finally, Enable the ADC RX interrupt */ dev->ad_ops->ao_rxint(dev, true); @@ -279,6 +286,15 @@ static ssize_t adc_read(FAR struct file *filep, FAR char *buffer, flags = enter_critical_section(); while (dev->ad_recv.af_head == dev->ad_recv.af_tail) { + /* Check if there was an overrun, if set we need to return EIO */ + + if (dev->ad_isovr) + { + dev->ad_isovr = false; + ret = -EIO; + goto return_with_irqdisabled; + } + /* The receive FIFO is empty -- was non-blocking mode selected? */ if (filep->f_oflags & O_NONBLOCK) @@ -419,6 +435,23 @@ static int adc_ioctl(FAR struct file *filep, int cmd, unsigned long arg) return ret; } +/**************************************************************************** + * Name: adc_reset + ****************************************************************************/ + +static int adc_reset(FAR struct adc_dev_s *dev) +{ + /* Set overrun flag to give read a chance to recover */ + + dev->ad_isovr = true; + + /* No need to notify here. The adc_receive callback will be called next. + * If an ADC overrun occurs then there must be at least one conversion. + */ + + return OK; +} + /**************************************************************************** * Name: adc_receive ****************************************************************************/ diff --git a/drivers/analog/ads1242.c b/drivers/analog/ads1242.c index 812dc2ae32d..e0c53d4415e 100644 --- a/drivers/analog/ads1242.c +++ b/drivers/analog/ads1242.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/drivers/analog/comp.c b/drivers/analog/comp.c index d3703a13bad..580a18c1052 100644 --- a/drivers/analog/comp.c +++ b/drivers/analog/comp.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/analog/dac7554.c b/drivers/analog/dac7554.c index cde097e2b01..8c57625cbea 100644 --- a/drivers/analog/dac7554.c +++ b/drivers/analog/dac7554.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include diff --git a/drivers/analog/dac7571.c b/drivers/analog/dac7571.c index 235ddb2aa9c..712c8a3d46b 100644 --- a/drivers/analog/dac7571.c +++ b/drivers/analog/dac7571.c @@ -48,6 +48,7 @@ #include #include #include +#include #include #include diff --git a/drivers/analog/lmp92001.c b/drivers/analog/lmp92001.c index ab1f1948c7c..f21cd34565a 100644 --- a/drivers/analog/lmp92001.c +++ b/drivers/analog/lmp92001.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/audio/audio_i2s.c b/drivers/audio/audio_i2s.c index 1b027a63753..ec2dc5bcad5 100644 --- a/drivers/audio/audio_i2s.c +++ b/drivers/audio/audio_i2s.c @@ -23,6 +23,10 @@ ****************************************************************************/ #include + +#include +#include + #include #include #include diff --git a/drivers/audio/audio_null.c b/drivers/audio/audio_null.c index 1a2a495facb..c8ab7944418 100644 --- a/drivers/audio/audio_null.c +++ b/drivers/audio/audio_null.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/audio/cs4344.c b/drivers/audio/cs4344.c index 520ab672bd6..798df3007b8 100644 --- a/drivers/audio/cs4344.c +++ b/drivers/audio/cs4344.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/audio/cs43l22.c b/drivers/audio/cs43l22.c index 56eb160b09a..e805afb2438 100644 --- a/drivers/audio/cs43l22.c +++ b/drivers/audio/cs43l22.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/audio/cs43l22.c - * Audio device driver for Cirrus logic CS43L22 Audio codec. * - * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. - * Author: Taras Drozdovskiy + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -48,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/audio/cs43l22_debug.c b/drivers/audio/cs43l22_debug.c index 597808cde6e..fbc1c91e27a 100644 --- a/drivers/audio/cs43l22_debug.c +++ b/drivers/audio/cs43l22_debug.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/audio/cs43l22_debug.c - * Audio device driver for Cirrus Logic CS43L22 Audio codec. * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Taras Drozdovsky + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/audio/cxd56.c b/drivers/audio/cxd56.c index bff508f435e..fcb0916348d 100644 --- a/drivers/audio/cxd56.c +++ b/drivers/audio/cxd56.c @@ -22,6 +22,8 @@ * Included Files ****************************************************************************/ +#include +#include #include #include #include @@ -39,6 +41,7 @@ #include #include #include +#include #include "cxd56.h" @@ -160,7 +163,6 @@ #define CXD56_DMA_SMP_WAIT_HIRES 10 /* usec per sample. */ #define CXD56_DMA_SMP_WAIT_NORMALT 40 /* usec per sample. */ #define CXD56_DMA_CMD_FIFO_NOT_FULL 1 -#define CXD56_DMA_START_ADDR_MASK 0x3fffffff /**************************************************************************** * Public Function Prototypes @@ -3223,11 +3225,11 @@ static int cxd56_start_dma(FAR struct cxd56_dev_s *dev) #ifdef CONFIG_AUDIO_CXD56_SRC src_apb = (struct ap_buffer_s *) dq_peek(&dev->down_pendq); - addr = ((uint32_t)src_apb->samp) & CXD56_DMA_START_ADDR_MASK; + addr = CXD56_PHYSADDR(src_apb->samp); size = (src_apb->nbytes / (dev->bitwidth / 8) / dev->channels) - 1; #else apb = (struct ap_buffer_s *) dq_peek(&dev->up_pendq); - addr = ((uint32_t)apb->samp) & CXD56_DMA_START_ADDR_MASK; + addr = CXD56_PHYSADDR(apb->samp); size = (apb->nbytes / (dev->bitwidth / 8) / dev->channels) - 1; #endif diff --git a/drivers/audio/vs1053.c b/drivers/audio/vs1053.c index d40ad86c85e..37cbd3e1918 100644 --- a/drivers/audio/vs1053.c +++ b/drivers/audio/vs1053.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/audio/wm8776.c b/drivers/audio/wm8776.c index 1b67dda4b3b..31a4eb5f02a 100644 --- a/drivers/audio/wm8776.c +++ b/drivers/audio/wm8776.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/audio/wm8904.c b/drivers/audio/wm8904.c index a0bab6404af..baec14523c6 100644 --- a/drivers/audio/wm8904.c +++ b/drivers/audio/wm8904.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/audio/wm8994.c b/drivers/audio/wm8994.c index 839d639d597..75764fb7cf6 100644 --- a/drivers/audio/wm8994.c +++ b/drivers/audio/wm8994.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/can/mcp2515.c b/drivers/can/mcp2515.c index 8872d6f4586..d31f14fdbe4 100644 --- a/drivers/can/mcp2515.c +++ b/drivers/can/mcp2515.c @@ -1,37 +1,20 @@ /**************************************************************************** * drivers/can/mcp2515.c * - * Copyright (C) 2017, 2019 Gregory Nutt. All rights reserved. - * Copyright (C) 2017 Alan Carvalho de Assis. All rights reserved. - * Author: Alan Carvalho de Assis - * Modified: Ben + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX, Atmel, nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -47,6 +30,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/contactless/mfrc522.c b/drivers/contactless/mfrc522.c index 0794fa83d33..78c256510ea 100644 --- a/drivers/contactless/mfrc522.c +++ b/drivers/contactless/mfrc522.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include diff --git a/drivers/eeprom/i2c_xx24xx.c b/drivers/eeprom/i2c_xx24xx.c index 01f0ea990d1..71d969db6a5 100644 --- a/drivers/eeprom/i2c_xx24xx.c +++ b/drivers/eeprom/i2c_xx24xx.c @@ -77,6 +77,7 @@ #include #include +#include #include #include #include diff --git a/drivers/eeprom/spi_xx25xx.c b/drivers/eeprom/spi_xx25xx.c index 07ddded6593..ff485da0965 100644 --- a/drivers/eeprom/spi_xx25xx.c +++ b/drivers/eeprom/spi_xx25xx.c @@ -102,6 +102,7 @@ #include #include +#include #include #include #include @@ -850,7 +851,8 @@ int ee25xx_initialize(FAR struct spi_dev_s *dev, FAR char *devname, eedev->readonly = !!readonly; - finfo("EEPROM device %s, %d bytes, %d per page, addrlen %d, readonly %d\n", + finfo("EEPROM device %s, %"PRIu32" bytes, " + "%u per page, addrlen %u, readonly %d\n", devname, eedev->size, eedev->pgsize, eedev->addrlen, eedev->readonly); return register_driver(devname, &ee25xx_fops, 0666, eedev); diff --git a/drivers/i2c/Make.defs b/drivers/i2c/Make.defs index b0c77b077bf..475b533ea03 100644 --- a/drivers/i2c/Make.defs +++ b/drivers/i2c/Make.defs @@ -1,36 +1,20 @@ ############################################################################ # drivers/i2c/Make.defs # -# Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt , -# Giorgio Gross +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: +# http://www.apache.org/licenses/LICENSE-2.0 # -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. # ############################################################################ diff --git a/drivers/i2c/i2c_bitbang.c b/drivers/i2c/i2c_bitbang.c index 96bcd5cac86..6beca586830 100644 --- a/drivers/i2c/i2c_bitbang.c +++ b/drivers/i2c/i2c_bitbang.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/drivers/i2c/i2c_driver.c b/drivers/i2c/i2c_driver.c index 15a042920bb..06f4c09ce4b 100644 --- a/drivers/i2c/i2c_driver.c +++ b/drivers/i2c/i2c_driver.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/i2c/pca9540bdp.c b/drivers/i2c/pca9540bdp.c index 82720b8e59b..e87f8e21bc2 100644 --- a/drivers/i2c/pca9540bdp.c +++ b/drivers/i2c/pca9540bdp.c @@ -42,6 +42,7 @@ #include #include +#include #include #include diff --git a/drivers/i2s/i2schar.c b/drivers/i2s/i2schar.c index 7d73b224c54..934fe5aa334 100644 --- a/drivers/i2s/i2schar.c +++ b/drivers/i2s/i2schar.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include diff --git a/drivers/input/ads7843e.c b/drivers/input/ads7843e.c index e4c88a4fceb..f299c93afcd 100644 --- a/drivers/input/ads7843e.c +++ b/drivers/input/ads7843e.c @@ -1,37 +1,20 @@ /**************************************************************************** * drivers/input/ads7843e.c * - * Copyright (C) 2011-2012, 2014, 2016-2017 Gregory Nutt. All rights - * reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/input/ajoystick.c b/drivers/input/ajoystick.c index c3b623549da..33e428a4379 100644 --- a/drivers/input/ajoystick.c +++ b/drivers/input/ajoystick.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include diff --git a/drivers/input/button_upper.c b/drivers/input/button_upper.c index d7388c41268..1a948c16992 100644 --- a/drivers/input/button_upper.c +++ b/drivers/input/button_upper.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include diff --git a/drivers/input/cypress_mbr3108.c b/drivers/input/cypress_mbr3108.c index cefc78b8709..89034f88d44 100644 --- a/drivers/input/cypress_mbr3108.c +++ b/drivers/input/cypress_mbr3108.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include diff --git a/drivers/input/djoystick.c b/drivers/input/djoystick.c index 2d28431b3f8..4dabf23fb5e 100644 --- a/drivers/input/djoystick.c +++ b/drivers/input/djoystick.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include diff --git a/drivers/input/max11802.c b/drivers/input/max11802.c index f7dcb5a7a4b..0a1e00b737f 100644 --- a/drivers/input/max11802.c +++ b/drivers/input/max11802.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/input/max11802.c * - * Copyright (C) 2011-2012, 2014-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/input/max11802.h b/drivers/input/max11802.h index a880003a616..6fe9228a9ef 100644 --- a/drivers/input/max11802.h +++ b/drivers/input/max11802.h @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/input/max11802.h * - * Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/input/nunchuck.c b/drivers/input/nunchuck.c index 642b8d1e760..4421f5939e4 100644 --- a/drivers/input/nunchuck.c +++ b/drivers/input/nunchuck.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include diff --git a/drivers/input/spq10kbd.c b/drivers/input/spq10kbd.c index 183355fb528..65a8ae57fbb 100644 --- a/drivers/input/spq10kbd.c +++ b/drivers/input/spq10kbd.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/drivers/input/stmpe811_base.c b/drivers/input/stmpe811_base.c index b9d91ffcf6f..bc4f5d19f69 100644 --- a/drivers/input/stmpe811_base.c +++ b/drivers/input/stmpe811_base.c @@ -30,6 +30,7 @@ #include #include +#include #include #include diff --git a/drivers/ioexpander/Kconfig b/drivers/ioexpander/Kconfig index f0995241b4b..487036845c2 100644 --- a/drivers/ioexpander/Kconfig +++ b/drivers/ioexpander/Kconfig @@ -14,6 +14,50 @@ config IOEXPANDER if IOEXPANDER +config IOEXPANDER_MCP23X17 + bool "MCP23017/MCP23S17 I2C/SPI IO expander" + default n + depends on I2C + ---help--- + Enable support for the MCP23017/MCP23S17 IO Expander + +if IOEXPANDER_MCP23X17 + +config MCP23X17_MULTIPLE + bool "Multiple MCP23x17 Devices" + default n + ---help--- + Can be defined to support multiple MCP23x17 devices on board. + +config MCP23X17_INT_ENABLE + bool "Enable MCP23x17 Interrupt Support" + default n + select IOEXPANDER_INT_ENABLE + ---help--- + Enable driver interrupt functionality + +config MCP23X17_INT_NCALLBACKS + int "Max number of interrupt callbacks" + default 4 + depends on MCP23X17_INT_ENABLE + ---help--- + This is the maximum number of interrupt callbacks supported + +config MCP23X17_INT_POLL + bool "Enable interrupt poll" + default n + ---help--- + Enable polling for missed interrupts. + +config MCP23X17_INT_POLLDELAY + int "Interrupt poll delay (used)" + default 500000 + depends on MCP23X17_INT_POLL + ---help--- + This microsecond delay defines the polling rate for missed interrupts. + +endif # IOEXPANDER_MCP23X17 + config IOEXPANDER_PCA9555 bool "PCA9555 I2C IO expander" default n diff --git a/drivers/ioexpander/Make.defs b/drivers/ioexpander/Make.defs index 866a131aeef..fcedba5f098 100644 --- a/drivers/ioexpander/Make.defs +++ b/drivers/ioexpander/Make.defs @@ -40,6 +40,10 @@ ifeq ($(CONFIG_IOEXPANDER_PCF8574),y) CSRCS += pcf8574.c endif +ifeq ($(CONFIG_IOEXPANDER_MCP23X17),y) + CSRCS += mcp23x17.c +endif + endif # CONFIG_IOEXPANDER # GPIO test device driver (independent of IOEXPANDERS) diff --git a/drivers/ioexpander/gpio.c b/drivers/ioexpander/gpio.c index 2032159622e..7889e637617 100644 --- a/drivers/ioexpander/gpio.c +++ b/drivers/ioexpander/gpio.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/drivers/ioexpander/gpio_lower_half.c b/drivers/ioexpander/gpio_lower_half.c index b59d3a1d042..8445b25545f 100644 --- a/drivers/ioexpander/gpio_lower_half.c +++ b/drivers/ioexpander/gpio_lower_half.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/ioexpander/mcp23x17.c b/drivers/ioexpander/mcp23x17.c new file mode 100644 index 00000000000..ec1620e3625 --- /dev/null +++ b/drivers/ioexpander/mcp23x17.c @@ -0,0 +1,995 @@ +/**************************************************************************** + * drivers/ioexpander/mcp23x17.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "mcp23x17.h" + +#if defined(CONFIG_IOEXPANDER_MCP23X17) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_I2C +# warning I2C support is required (CONFIG_I2C) +#endif + +#ifndef CONFIG_SCHED_WORKQUEUE +# error Work queue support is required (CONFIG_SCHED_WORKQUEUE) +#endif + +#ifndef CONFIG_SCHED_HPWORK +# error High-Priority Work support is required (CONFIG_SCHED_HPWORK) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline int mcp23x17_write(FAR struct mcp23x17_dev_s *priv, + FAR const uint8_t *wbuffer, int wbuflen); +static inline int mcp23x17_writeread(FAR struct mcp23x17_dev_s *priv, + FAR const uint8_t *wbuffer, int wbuflen, FAR uint8_t *rbuffer, + int rbuflen); +static int mcp23x17_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int dir); +static int mcp23x17_option(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int opt, void *val); +static int mcp23x17_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + bool value); +static int mcp23x17_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + FAR bool *value); +static int mcp23x17_readbuf(FAR struct ioexpander_dev_s *dev, uint8_t pin, + FAR bool *value); +#ifdef CONFIG_IOEXPANDER_MULTIPIN +static int mcp23x17_multiwritepin(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, int count); +static int mcp23x17_multireadpin(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, int count); +static int mcp23x17_multireadbuf(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, int count); +#endif +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +static FAR void *mcp23x17_attach(FAR struct ioexpander_dev_s *dev, + ioe_pinset_t pinset, ioe_callback_t callback, FAR void *arg); +static int mcp23x17_detach(FAR struct ioexpander_dev_s *dev, + FAR void *handle); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifndef CONFIG_MCP23X17_MULTIPLE +/* If only a single MCP23X17 device is supported, then the driver state + * structure may as well be pre-allocated. + */ + +static struct mcp23x17_dev_s g_mcp23x17; + +/* Otherwise, we will need to maintain allocated driver instances in a list */ + +#else +static struct mcp23x17_dev_s *g_mcp23x17list; +#endif + +/* I/O expander vtable */ + +static const struct ioexpander_ops_s g_mcp23x17_ops = +{ + mcp23x17_direction, + mcp23x17_option, + mcp23x17_writepin, + mcp23x17_readpin, + mcp23x17_readbuf +#ifdef CONFIG_IOEXPANDER_MULTIPIN + , mcp23x17_multiwritepin + , mcp23x17_multireadpin + , mcp23x17_multireadbuf +#endif +#ifdef CONFIG_IOEXPANDER_INT_ENABLE + , mcp23x17_attach + , mcp23x17_detach +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mcp23x17_lock + * + * Description: + * Get exclusive access to the MCP23X17 + * + ****************************************************************************/ + +static int mcp23x17_lock(FAR struct mcp23x17_dev_s *priv) +{ + return nxsem_wait_uninterruptible(&priv->exclsem); +} + +#define mcp23x17_unlock(p) nxsem_post(&(p)->exclsem) + +/**************************************************************************** + * Name: mcp23x17_write + * + * Description: + * Write to the I2C device. + * + ****************************************************************************/ + +static inline int mcp23x17_write(FAR struct mcp23x17_dev_s *priv, + FAR const uint8_t *wbuffer, int wbuflen) +{ + struct i2c_msg_s msg; + int ret; + + /* Setup for the transfer */ + + msg.frequency = priv->config->frequency; + msg.addr = priv->config->address; + msg.flags = 0; + msg.buffer = (FAR uint8_t *)wbuffer; /* Override const */ + msg.length = wbuflen; + + /* Then perform the transfer. */ + + ret = I2C_TRANSFER(priv->i2c, &msg, 1); + return (ret >= 0) ? OK : ret; +} + +/**************************************************************************** + * Name: mcp23x17_writeread + * + * Description: + * Write to then read from the I2C device. + * + ****************************************************************************/ + +static inline int mcp23x17_writeread(FAR struct mcp23x17_dev_s *priv, + FAR const uint8_t *wbuffer, int wbuflen, + FAR uint8_t *rbuffer, int rbuflen) +{ + struct i2c_config_s config; + + /* Set up the configuration and perform the write-read operation */ + + config.frequency = priv->config->frequency; + config.address = priv->config->address; + config.addrlen = 7; + + return i2c_writeread(priv->i2c, &config, wbuffer, wbuflen, + rbuffer, rbuflen); +} + +/**************************************************************************** + * Name: mcp23x17_setbit + * + * Description: + * Write a bit in a register pair + * + ****************************************************************************/ + +static int mcp23x17_setbit(FAR struct mcp23x17_dev_s *priv, uint8_t addr, + uint8_t pin, int bitval) +{ + uint8_t buf[2]; + int ret; + + if (pin > 15) + { + return -ENXIO; + } + else if (pin > 7) + { + addr += 1; + pin -= 8; + } + + buf[0] = addr; + +#ifdef CONFIG_MCP23X17_SHADOW_MODE + /* Get the shadowed register value */ + + buf[1] = priv->sreg[addr]; + +#else + /* Get the register value from the IO-Expander */ + + ret = mcp23x17_writeread(priv, &buf[0], 1, &buf[1], 1); + if (ret < 0) + { + return ret; + } +#endif + + if (bitval) + { + buf[1] |= (1 << pin); + } + else + { + buf[1] &= ~(1 << pin); + } + +#ifdef CONFIG_MCP23X17_SHADOW_MODE + /* Save the new register value in the shadow register */ + + priv->sreg[addr] = buf[1]; +#endif + + ret = mcp23x17_write(priv, buf, 2); +#ifdef CONFIG_MCP23X17_RETRY + if (ret != OK) + { + /* Try again (only once) */ + + ret = mcp23x17_write(priv, buf, 2); + } +#endif + + return ret; +} + +/**************************************************************************** + * Name: mcp23x17_getbit + * + * Description: + * Get a bit from a register pair + * + ****************************************************************************/ + +static int mcp23x17_getbit(FAR struct mcp23x17_dev_s *priv, uint8_t addr, + uint8_t pin, FAR bool *val) +{ + uint8_t buf; + int ret; + + if (pin > 15) + { + return -ENXIO; + } + else if (pin > 7) + { + addr += 1; + pin -= 8; + } + + ret = mcp23x17_writeread(priv, &addr, 1, &buf, 1); + if (ret < 0) + { + return ret; + } + +#ifdef CONFIG_MCP23X17_SHADOW_MODE + /* Save the new register value in the shadow register */ + + priv->sreg[addr] = buf; +#endif + + *val = (buf >> pin) & 1; + return OK; +} + +/**************************************************************************** + * Name: mcp23x17_direction + * + * Description: + * Set the direction of an ioexpander pin. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * dir - One of the IOEXPANDER_DIRECTION_ macros + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int direction) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + int ret; + + if (direction != IOEXPANDER_DIRECTION_IN && + direction != IOEXPANDER_DIRECTION_OUT) + { + return -EINVAL; + } + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + ret = mcp23x17_setbit(priv, MCP23X17_IODIRA, pin, + (direction == IOEXPANDER_DIRECTION_IN)); + mcp23x17_unlock(priv); + return ret; +} + +/**************************************************************************** + * Name: mcp23x17_option + * + * Description: + * Set pin options. Required. + * Since all IO expanders have various pin options, this API allows setting + * pin options in a flexible way. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * opt - One of the IOEXPANDER_OPTION_ macros + * val - The option's value + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_option(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int opt, FAR void *val) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + int ret = -EINVAL; + + if (opt == IOEXPANDER_OPTION_INVERT) + { + int ival = (int)((intptr_t)val); + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + ret = mcp23x17_setbit(priv, MCP23X17_IPOLA, pin, ival); + mcp23x17_unlock(priv); + } + + return ret; +} + +/**************************************************************************** + * Name: mcp23x17_writepin + * + * Description: + * Set the pin level. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * val - The pin level. Usually TRUE will set the pin high, + * except if OPTION_INVERT has been set on this pin. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + bool value) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + int ret; + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + ret = mcp23x17_setbit(priv, MCP23X17_GPIOA, pin, value); + mcp23x17_unlock(priv); + return ret; +} + +/**************************************************************************** + * Name: mcp23x17_readpin + * + * Description: + * Read the actual PIN level. This can be different from the last value + * written to this pin. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin + * valptr - Pointer to a buffer where the pin level is stored. Usually TRUE + * if the pin is high, except if OPTION_INVERT has been set on + * this pin. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + FAR bool *value) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + int ret; + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + ret = mcp23x17_getbit(priv, MCP23X17_GPIOA, pin, value); + + mcp23x17_unlock(priv); + return ret; +} + +/**************************************************************************** + * Name: mcp23x17_readbuf + * + * Description: + * Read the buffered pin level. + * This can be different from the actual pin state. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin + * valptr - Pointer to a buffer where the level is stored. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_readbuf(FAR struct ioexpander_dev_s *dev, uint8_t pin, + FAR bool *value) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + int ret; + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + ret = mcp23x17_getbit(priv, MCP23X17_GPIOA, pin, value); + mcp23x17_unlock(priv); + return ret; +} + +#ifdef CONFIG_IOEXPANDER_MULTIPIN + +/**************************************************************************** + * Name: mcp23x17_getmultibits + * + * Description: + * Read multiple bits from MCP23X17 registers. + * + ****************************************************************************/ + +static int mcp23x17_getmultibits(FAR struct mcp23x17_dev_s *priv, + uint8_t addr, + FAR uint8_t *pins, + FAR bool *values, + int count) +{ + uint8_t buf[2]; + int ret = OK; + int i; + int index; + int pin; + + ret = mcp23x17_writeread(priv, &addr, 1, buf, 2); + if (ret < 0) + { + return ret; + } + +#ifdef CONFIG_MCP23X17_SHADOW_MODE + /* Save the new register value in the shadow register */ + + priv->sreg[addr] = buf[0]; + priv->sreg[addr + 1] = buf[1]; +#endif + + /* Read the requested bits */ + + for (i = 0; i < count; i++) + { + index = 0; + pin = pins[i]; + if (pin > 15) + { + return -ENXIO; + } + else if (pin > 7) + { + index = 1; + pin -= 8; + } + + values[i] = (buf[index] >> pin) & 1; + } + + return OK; +} + +/**************************************************************************** + * Name: mcp23x17_multiwritepin + * + * Description: + * Set the pin level for multiple pins. This routine may be faster than + * individual pin accesses. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * pins - The list of pin indexes to alter in this call + * val - The list of pin levels. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_multiwritepin(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, + int count) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + uint8_t addr = MCP23X17_GPIOA; + uint8_t buf[3]; + int ret; + int i; + int index; + int pin; + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + /* Start by reading both registers, whatever the pins to change. We could + * attempt to read one port only if all pins were on the same port, but + * this would not save much. + */ + +#ifndef CONFIG_MCP23X17_SHADOW_MODE + ret = mcp23x17_writeread(priv, &addr, 1, &buf[1], 2); + if (ret < 0) + { + mcp23x17_unlock(priv); + return ret; + } +#else + /* In Shadow-Mode we "read" the pin status from the shadow registers */ + + buf[1] = priv->sreg[addr]; + buf[2] = priv->sreg[addr + 1]; +#endif + + /* Apply the user defined changes */ + + for (i = 0; i < count; i++) + { + index = 1; + pin = pins[i]; + if (pin > 15) + { + mcp23x17_unlock(priv); + return -ENXIO; + } + else if (pin > 7) + { + index = 2; + pin -= 8; + } + + if (values[i]) + { + buf[index] |= (1 << pin); + } + else + { + buf[index] &= ~(1 << pin); + } + } + + /* Now write back the new pins states */ + + buf[0] = addr; +#ifdef CONFIG_MCP23X17_SHADOW_MODE + /* Save the new register values in the shadow register */ + + priv->sreg[addr] = buf[1]; + priv->sreg[addr + 1] = buf[2]; +#endif + ret = mcp23x17_write(priv, buf, 3); + + mcp23x17_unlock(priv); + return ret; +} + +/**************************************************************************** + * Name: mcp23x17_multireadpin + * + * Description: + * Read the actual level for multiple pins. This routine may be faster than + * individual pin accesses. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The list of pin indexes to read + * valptr - Pointer to a buffer where the pin levels are stored. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_multireadpin(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, + int count) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + int ret; + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + ret = mcp23x17_getmultibits(priv, MCP23X17_GPIOA, + pins, values, count); + mcp23x17_unlock(priv); + return ret; +} + +/**************************************************************************** + * Name: mcp23x17_multireadbuf + * + * Description: + * Read the buffered level of multiple pins. This routine may be faster + * than individual pin accesses. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin + * valptr - Pointer to a buffer where the buffered levels are stored. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_multireadbuf(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, + int count) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + int ret; + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + ret = mcp23x17_getmultibits(priv, MCP23X17_GPIOA, + pins, values, count); + mcp23x17_unlock(priv); + return ret; +} + +#endif + +#ifdef CONFIG_MCP23X17_INT_ENABLE + +/**************************************************************************** + * Name: mcp23x17_attach + * + * Description: + * Attach and enable a pin interrupt callback function. + * + * Input Parameters: + * dev - Device-specific state data + * pinset - The set of pin events that will generate the callback + * callback - The pointer to callback function. NULL will detach the + * callback. + * arg - User-provided callback argument + * + * Returned Value: + * A non-NULL handle value is returned on success. This handle may be + * used later to detach and disable the pin interrupt. + * + ****************************************************************************/ + +static FAR void *mcp23x17_attach(FAR struct ioexpander_dev_s *dev, + ioe_pinset_t pinset, + ioe_callback_t callback, + FAR void *arg) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + FAR void *handle = NULL; + int i; + int ret; + + /* Get exclusive access to the MCP23X17 */ + + ret = mcp23x17_lock(priv); + if (ret < 0) + { + return ret; + } + + /* Find and available in entry in the callback table */ + + for (i = 0; i < CONFIG_MCP23X17_INT_NCALLBACKS; i++) + { + /* Is this entry available (i.e., no callback attached) */ + + if (priv->cb[i].cbfunc == NULL) + { + /* Yes.. use this entry */ + + priv->cb[i].pinset = pinset; + priv->cb[i].cbfunc = callback; + priv->cb[i].cbarg = arg; + handle = &priv->cb[i]; + break; + } + } + + /* Add this callback to the table */ + + mcp23x17_unlock(priv); + return handle; +} + +/**************************************************************************** + * Name: mcp23x17_detach + * + * Description: + * Detach and disable a pin interrupt callback function. + * + * Input Parameters: + * dev - Device-specific state data + * handle - The non-NULL opaque value return by mcp23x17_attch() + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int mcp23x17_detach(FAR struct ioexpander_dev_s *dev, + FAR void *handle) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)dev; + FAR struct mcp23x17_callback_s *cb = + (FAR struct mcp23x17_callback_s *)handle; + + DEBUGASSERT(priv != NULL && cb != NULL); + DEBUGASSERT((uintptr_t)cb >= (uintptr_t)&priv->cb[0] && + (uintptr_t)cb <= + (uintptr_t)&priv->cb[CONFIG_TCA64XX_INT_NCALLBACKS - 1]); + UNUSED(priv); + + cb->pinset = 0; + cb->cbfunc = NULL; + cb->cbarg = NULL; + return OK; +} + +/**************************************************************************** + * Name: mcp23x17_irqworker + * + * Description: + * Handle GPIO interrupt events (this function actually executes in the + * context of the worker thread). + * + ****************************************************************************/ + +static void mcp23x17_irqworker(void *arg) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)arg; + uint8_t addr = MCP23X17_GPIOA; + uint8_t buf[2]; + ioe_pinset_t pinset; + int ret; + int i; + + /* Read inputs */ + + ret = mcp23x17_writeread(priv, &addr, 1, buf, 2); + if (ret == OK) + { +#ifdef CONFIG_MCP23X17_SHADOW_MODE + /* Don't forget to update the shadow registers at this point */ + + priv->sreg[addr] = buf[0]; + priv->sreg[addr + 1] = buf[1]; +#endif + /* Create a 16-bit pinset */ + + pinset = ((unsigned int)buf[0] << 8) | buf[1]; + + /* Perform pin interrupt callbacks */ + + for (i = 0; i < CONFIG_MCP23X17_INT_NCALLBACKS; i++) + { + /* Is this entry valid (i.e., callback attached)? If so, did + * any of the requested pin interrupts occur? + */ + + if (priv->cb[i].cbfunc != NULL) + { + /* Did any of the requested pin interrupts occur? */ + + ioe_pinset_t match = pinset & priv->cb[i].pinset; + if (match != 0) + { + /* Yes.. perform the callback */ + + priv->cb[i].cbfunc(&priv->dev, match, + priv->cb[i].cbarg); + } + } + } + } + + /* Re-enable interrupts */ + + priv->config->enable(priv->config, TRUE); +} + +/**************************************************************************** + * Name: mcp23x17_interrupt + * + * Description: + * Handle GPIO interrupt events (this function executes in the + * context of the interrupt). + * + ****************************************************************************/ + +static int mcp23x17_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct mcp23x17_dev_s *priv = (FAR struct mcp23x17_dev_s *)arg; + + /* In complex environments, we cannot do I2C transfers from the interrupt + * handler because semaphores are probably used to lock the I2C bus. In + * this case, we will defer processing to the worker thread. This is also + * much kinder in the use of system resources and is, therefore, probably + * a good thing to do in any event. + */ + + /* Notice that further GPIO interrupts are disabled until the work is + * actually performed. This is to prevent overrun of the worker thread. + * Interrupts are re-enabled in mcp23x17_irqworker() when the work is + * completed. + */ + + if (work_available(&priv->work)) + { + priv->config->enable(priv->config, FALSE); + work_queue(HPWORK, &priv->work, mcp23x17_irqworker, + (FAR void *)priv, 0); + } + + return OK; +} + +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mcp23x17_initialize + * + * Description: + * Initialize a MCP23X17 I2C device. + * + * TODO: Add support for more than one device. + * + ****************************************************************************/ + +FAR struct ioexpander_dev_s *mcp23x17_initialize( + FAR struct i2c_master_s *i2cdev, + FAR struct mcp23x17_config_s *config) +{ + FAR struct mcp23x17_dev_s *priv; + int ret; + + DEBUGASSERT(i2cdev != NULL && config != NULL); + +#ifdef CONFIG_MCP23X17_MULTIPLE + /* Allocate the device state structure */ + + priv = (FAR struct mcp23x17_dev_s *) + kmm_zalloc(sizeof(struct mcp23x17_dev_s)); + if (!priv) + { + return NULL; + } + + /* And save the device structure in the list of MCP23X17 so that we can + * find it later. + */ + + priv->flink = g_mcp23x17list; + g_mcp23x17list = priv; + +#else + /* Use the global MCP23X17 driver instance */ + + priv = &g_mcp23x17; +#endif + + /* Initialize the device state structure */ + + priv->i2c = i2cdev; + priv->dev.ops = &g_mcp23x17_ops; + priv->config = config; + +#ifdef CONFIG_MCP23X17_INT_ENABLE + priv->config->attach(priv->config, mcp23x17_interrupt, priv); + priv->config->enable(priv->config, TRUE); +#endif + + nxsem_init(&priv->exclsem, 0, 1); + return &priv->dev; +} + +#endif /* CONFIG_IOEXPANDER_MCP23X17 */ diff --git a/drivers/ioexpander/mcp23x17.h b/drivers/ioexpander/mcp23x17.h new file mode 100644 index 00000000000..9edf00354cb --- /dev/null +++ b/drivers/ioexpander/mcp23x17.h @@ -0,0 +1,175 @@ +/**************************************************************************** + * drivers/ioexpander/mcp23x17.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __DRIVERS_IOEXPANDER_MCP23X17_H +#define __DRIVERS_IOEXPANDER_MCP23X17_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#if defined(CONFIG_IOEXPANDER) && defined(CONFIG_IOEXPANDER_MCP23X17) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Prerequisites: + * CONFIG_I2C + * I2C support is required + * CONFIG_IOEXPANDER + * Enables I/O expander support + * + * CONFIG_IOEXPANDER_MCP23X17 + * Enables support for the MCP23X17 driver (Needs CONFIG_INPUT) + * CONFIG_MCP23X17_MULTIPLE + * Can be defined to support multiple MCP23X17 devices on board. + * CONFIG_MCP23X17_INT_NCALLBACKS + * Maximum number of supported pin interrupt callbacks. + * CONFIG_MCP23X17_INT_POLL + * Enables a poll for missed interrupts + * CONFIG_MCP23X17_INT_POLLDELAY + * If CONFIG_MCP23X17_INT_POLL=y, then this is the delay in microseconds + * between polls for missed interrupts. + */ + +#ifndef CONFIG_I2C +# error "CONFIG_I2C is required by MCP23X17" +#endif + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +# ifndef CONFIG_MCP23X17_INT_NCALLBACKS +# define CONFIG_MCP23X17_INT_NCALLBACKS 4 +# endif +#endif + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +# ifndef CONFIG_SCHED_WORKQUEUE +# error Work queue support required. CONFIG_SCHED_WORKQUEUE must be selected. +# endif +#endif + +#ifndef CONFIG_MCP23X17_INT_POLLDELAY +# define CONFIG_MCP23X17_INT_POLLDELAY 500000 +#endif + +/* MCP23X17 Definitions *****************************************************/ + +/* I2C frequency */ + +#define MCP23X17_I2C_MAXFREQUENCY 400000 /* 400KHz */ + +/* MCP23X17 *****************************************************************/ + +/* If IOCON.BANK = 0 Addressing Mode */ + +#define MCP23X17_IODIRA 0x00 +#define MCP23X17_IODIRB 0x01 +#define MCP23X17_IPOLA 0x02 +#define MCP23X17_IPOLB 0x03 +#define MCP23X17_GPINTENA 0x04 +#define MCP23X17_GPINTENB 0x05 +#define MCP23X17_DEFVALA 0x06 +#define MCP23X17_DEFVALB 0x07 +#define MCP23X17_INTCONA 0x08 +#define MCP23X17_INTCONB 0x09 +#define MCP23X17_IOCON 0x0a +#define MCP23X17_IOCON_2 0x0b +#define MCP23X17_GPPUA 0x0c +#define MCP23X17_GPPUB 0x0d +#define MCP23X17_INTFA 0x0e +#define MCP23X17_INTFB 0x0f +#define MCP23X17_INTCAPA 0x10 +#define MCP23X17_INTCAPB 0x11 +#define MCP23X17_GPIOA 0x12 +#define MCP23X17_GPIOB 0x13 +#define MCP23X17_OLATA 0x14 +#define MCP23X17_OLATB 0x15 + +#define MCP23X17_IOCON_INTPOL (1 << 1) /* Polarity of INT output pin */ +#define MCP23X17_IOCON_ODR (1 << 2) /* Config INT pin as open-drain */ +#define MCP23X17_IOCON_HAEN (1 << 3) /* HW Address enable bit */ +#define MCP23X17_IOCON_DISSLW (1 << 4) /* Disable Slew Rate for SDA output */ +#define MCP23X17_IOCON_SEQOP (1 << 5) /* Disable Sequencial Operation */ +#define MCP23X17_IOCON_MIRROR (1 << 6) /* Mirror INT pins */ +#define MCP23X17_IOCON_BANK (1 << 7) /* Configure how to address register */ + +#define MCP23X17_NR_GPIO_MAX 16 + +#define MCP23X17_POLLDELAY (CONFIG_MCP23X17_INT_POLLDELAY / USEC_PER_TICK) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +/* This type represents on registered pin interrupt callback */ + +struct mcp23x17_callback_s +{ + ioe_pinset_t pinset; /* Set of pin interrupts that will generate + * the callback. */ + ioe_callback_t cbfunc; /* The saved callback function pointer */ + FAR void *cbarg; /* Callback argument */ +}; +#endif + +/* This structure represents the state of the MCP23X17 driver */ + +struct mcp23x17_dev_s +{ + struct ioexpander_dev_s dev; /* Nested structure to allow casting + * as public gpio expander. + */ + FAR struct mcp23x17_config_s *config; /* Board configuration data */ + FAR struct i2c_master_s *i2c; /* Saved I2C driver instance */ + sem_t exclsem; /* Mutual exclusion */ + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +#ifdef CONFIG_MCP23X17_INT_POLL + struct wdog_s wdog; /* Timer used to poll for missed interrupts */ +#endif + + ioe_pinset_t input; /* Last input registers */ + ioe_pinset_t intstat; /* Pending interrupts */ + struct work_s work; /* Supports the interrupt handling "bottom half" */ + + /* Saved callback information for each I/O expander client */ + + struct mcp23x17_callback_s cb[CONFIG_MCP23X17_INT_NCALLBACKS]; +#endif +}; + +#endif /* CONFIG_IOEXPANDER && CONFIG_IOEXPANDER_MCP23X17 */ +#endif /* __DRIVERS_IOEXPANDER_MCP23X17_H */ diff --git a/drivers/ioexpander/pca9555.c b/drivers/ioexpander/pca9555.c index 88b0ad4ab5c..a80715581b2 100644 --- a/drivers/ioexpander/pca9555.c +++ b/drivers/ioexpander/pca9555.c @@ -814,7 +814,7 @@ static int pca9555_detach(FAR struct ioexpander_dev_s *dev, FAR void *handle) DEBUGASSERT(pca != NULL && cb != NULL); DEBUGASSERT((uintptr_t)cb >= (uintptr_t)&pca->cb[0] && (uintptr_t)cb <= - (uintptr_t)&pca->cb[CONFIG_TCA64XX_INT_NCALLBACKS - 1]); + (uintptr_t)&pca->cb[CONFIG_PCA9555_INT_NCALLBACKS - 1]); UNUSED(pca); cb->pinset = 0; diff --git a/drivers/lcd/Kconfig b/drivers/lcd/Kconfig index a1f061a8abf..08f3a2e3cf5 100644 --- a/drivers/lcd/Kconfig +++ b/drivers/lcd/Kconfig @@ -1451,6 +1451,36 @@ config LCD_ST7032 connected to a pull-up resistor and the pin SHLC is connected to the ground. So only I2C pins SDA and SCL are used by NuttX. +config LCD_HT16K33 + bool "Holtek HT16K32 4 Digits 14-Segment Display" + default n + depends on I2C + ---help--- + Enable support for Holtek HT16K33 (and Vinka VK16K33) 4 Digits + 14-Segment module: 0.54" 14-segment LED HT16K32 Backpack. + +if LCD_HT16K33 +config LCD_HT16K33_MULT_MODULE + bool "Enable support to multiple modules as a single display" + default n + depends on I2C + ---help--- + It is possible to connect many HT16K33 modules with sequential + I2C addresses to work as a single display to support length + text strings. The device at the I2C address 0x70 will display the + 4 more significant characters, the device 0x71 will display the + previous 4 more significant characters and so on. + +config LCD_HT16K33_NUMBER_MODULES + int "Quantity of HT16K33 modules to be used as a single display" + range 1 8 + depends on LCD_HT16K33_MULT_MODULE + ---help--- + Quantity of sequential modules to be used to create a single + display. We can have up to 8 to I2C Addresses: 0x70 - 0x77. + +endif # LCD_HT16K33 + endif # SLCD comment "Other LCD-related Devices" diff --git a/drivers/lcd/Make.defs b/drivers/lcd/Make.defs index bd3d3b63a0b..058c4978a10 100644 --- a/drivers/lcd/Make.defs +++ b/drivers/lcd/Make.defs @@ -146,6 +146,10 @@ endif ifeq ($(CONFIG_LCD_ST7032),y) CSRCS += st7032.c endif + +ifeq ($(CONFIG_LCD_HT16K33),y) + CSRCS += ht16k33_14seg.c +endif endif # CONFIG_SLCD # Other LCD-related devices diff --git a/drivers/lcd/ft80x.c b/drivers/lcd/ft80x.c index c64a540cdc6..40978f18f6c 100644 --- a/drivers/lcd/ft80x.c +++ b/drivers/lcd/ft80x.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/ft80x_spi.c b/drivers/lcd/ft80x_spi.c index 77080b49578..53895d795e1 100644 --- a/drivers/lcd/ft80x_spi.c +++ b/drivers/lcd/ft80x_spi.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/lcd/ht16k33_14seg.c b/drivers/lcd/ht16k33_14seg.c new file mode 100644 index 00000000000..df6a8f23c2f --- /dev/null +++ b/drivers/lcd/ht16k33_14seg.c @@ -0,0 +1,1171 @@ +/**************************************************************************** + * drivers/lcd/ht16k33_14seg.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Alphanumeric display driver for HOLTEK HT16K33 (and VINKA VK16K33 clone) + * This driver is specific for a 0.54" 14-segment LED HT16K33 Backpack + * module with 4 14-segment digits (2 Kingbright 5241AS display). + * Note: the model I'm testing uses the VK16K33. + * + * This is how the displays are connected: + * Left Display: Digit 1: Catode connected to COM3 + * Left Display: Digit 2: Catode connected to COM2 + * Right Display: Digit 1: Catode connected to COM1 + * Right Display: Digit 2: Catode connected to COM0 + * + * 14-Segment | LED Controller + * ------------------------------- + * 8 - DP | ROW14 - 11 + * 13 - p | ROW6 - 19 + * 2 - n | ROW11 - 14 + * 4 - m | ROW12 - 13 + * 5 - l | ROW13 - 12 + * 6 - k | ROW7 - 18 + * 14 - j | ROW10 - 15 + * 15 - h | ROW9 - 16 + * 17 - g | ROW8 - 17 + * 18 - f | ROW5 - 20 + * 1 - e | ROW4 - 21 + * 7 - d | ROW3 - 22 + * 9 - c | ROW2 - 23 + * 10 - b | ROW1 - 24 + * 12 - a | ROW0 - 25 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_LIB_SLCDCODEC +# error please also select Library Routines, Segment LCD CODEC +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_LCD_HT16K33) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* I2C frequency */ + +#ifndef CONFIG_HT16K33_I2C_FREQ +# define CONFIG_HT16K33_I2C_FREQ 400000 +#endif + +#ifndef CONFIG_LCD_HT16K33_NUMBER_MODULES +# define CONFIG_LCD_HT16K33_NUMBER_MODULES 1 +#endif + +#define HT16K33_MAX_ROW 1 +#define HT16K33_MAX_COL 4 * CONFIG_LCD_HT16K33_NUMBER_MODULES + +/* Device naming ************************************************************/ + +#define DEVNAME_FMT "/dev/slcd%d" +#define DEVNAME_FMTLEN (9 + 3 + 1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct ht16k33_dev_s +{ + FAR struct i2c_master_s *i2c; /* I2C interface */ + uint8_t row; /* Current row position to write on display */ + uint8_t col; /* Current col position to write on display */ + uint8_t buffer[HT16K33_MAX_COL]; + bool pendscroll; + sem_t sem_excl; +}; + +struct lcd_instream_s +{ + struct lib_instream_s stream; + FAR const char *buffer; + ssize_t nbytes; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline void ht16k33_write_cmd(FAR struct ht16k33_dev_s *priv, + int dev_id, uint8_t cmd); + +static inline void ht16k33_write_data(FAR struct ht16k33_dev_s *priv, + int dev_id, uint8_t cmd, + uint8_t *values, int nbytes); + +static inline void ht16k33_setcontrast(FAR struct ht16k33_dev_s *priv, + int dev_id, int8_t contrast); + +static void lcd_scroll_up(FAR struct ht16k33_dev_s *priv); + +static void ht16k33_clear_display(FAR struct ht16k33_dev_s *priv); + +/* Character driver methods */ + +static int ht16k33_open(FAR struct file *filep); +static int ht16k33_close(FAR struct file *filep); +static ssize_t ht16k33_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t ht16k33_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); +static off_t ht16k33_seek(FAR struct file *filep, off_t offset, + int whence); +static int ht16k33_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_ht16k33fops = +{ + ht16k33_open, /* open */ + ht16k33_close, /* close */ + ht16k33_read, /* read */ + ht16k33_write, /* write */ + ht16k33_seek, /* seek */ + ht16k33_ioctl, /* ioctl */ + NULL, /* poll */ +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + NULL /* unlink */ +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ht16k33_write_cmd + * + * Description: + * Write an Instruction command to HT16K33 + * + ****************************************************************************/ + +static inline void ht16k33_write_cmd(FAR struct ht16k33_dev_s *priv, + int dev_id, uint8_t cmd) +{ + struct i2c_msg_s msg; + uint8_t data[1]; + int ret; + + /* Prepare data to send */ + + data[0] = cmd; + + /* Setup the HT16K33 Command */ + + msg.frequency = CONFIG_HT16K33_I2C_FREQ; /* I2C frequency */ + msg.addr = HT16K33_I2C_ADDR + dev_id; /* 7-bit address */ + msg.flags = 0; /* Write transaction */ + msg.buffer = (FAR uint8_t *) data; /* Transfer from this address */ + msg.length = 1; /* Send one byte */ + + /* Perform the transfer */ + + ret = I2C_TRANSFER(priv->i2c, &msg, 1); + if (ret < 0) + { + lcderr("ERROR: I2C_TRANSFER failed: %d\n", ret); + } +} + +/**************************************************************************** + * Name: ht16k33_write_data + * + * Description: + * Write a Data command to HT16K33 + * + ****************************************************************************/ + +static inline void ht16k33_write_data(FAR struct ht16k33_dev_s *priv, + int dev_id, uint8_t cmd, + uint8_t *values, int nbytes) +{ + struct i2c_msg_s msg; + uint8_t data[16]; + int ret; + int i; + + /* Prepare data to send */ + + data[0] = cmd; + + for (i = 0; i < nbytes; i++) + { + data[i + 1] = values[i]; + } + + /* Setup the message to write data to HT16K33 */ + + msg.frequency = CONFIG_HT16K33_I2C_FREQ; /* I2C frequency */ + msg.addr = HT16K33_I2C_ADDR + dev_id; /* 7-bit address */ + msg.flags = 0; /* Write transaction */ + msg.buffer = (FAR uint8_t *) data; /* Transfer from here */ + msg.length = nbytes + 1; /* Send cmd + nbytes */ + + /* Perform the transfer */ + + ret = I2C_TRANSFER(priv->i2c, &msg, 1); + if (ret < 0) + { + lcderr("ERROR: I2C_TRANSFER failed: %d\n", ret); + } +} + +static inline void ht16k33_setcontrast(FAR struct ht16k33_dev_s *priv, + int dev_id, int8_t contrast) +{ + int i; + + if (contrast < HT16K33_CONTRAST_MIN) + { + contrast = HT16K33_CONTRAST_MIN; + } + else if (contrast > HT16K33_CONTRAST_MAX) + { + contrast = HT16K33_CONTRAST_MAX; + } + + for (i = 0; i < CONFIG_LCD_HT16K33_NUMBER_MODULES; i++) + { + ht16k33_write_cmd(priv, i, HT16K33_DIMMING_SET | (contrast & 0x0f)); + } +} + +/**************************************************************************** + * Name: lcd_getdata + * + * Description: + * Simulate reading data from LCD, we are reading from internal buffer + * + ****************************************************************************/ + +static inline uint8_t lcd_getdata(FAR struct ht16k33_dev_s *priv) +{ + uint8_t data; + data = priv->buffer[priv->row * priv->col]; + return data; +} + +/**************************************************************************** + * Name: rc2addr + * + * Description: + * This converts a row/column pair to a screen memory address. + * + ****************************************************************************/ + +static inline uint8_t rc2addr(FAR struct ht16k33_dev_s *priv) +{ + /* Each module has 4 digits they correspond to these columns: + * + * col0: 0x00 - 0x01, col1: 0x02 - 0x03, + * col2: 0x04 - 0x05, col3: 0x06 - 0x07 + */ + + return (priv->col % 4) * 0x02; +} + +/**************************************************************************** + * Name: addr2rc + * + * Description: + * This converts a screen memory address to a row/column pair. + * + ****************************************************************************/ + +static inline void addr2rc(FAR struct ht16k33_dev_s *priv, uint8_t addr, + FAR uint8_t *row, FAR uint8_t *col) +{ + *row = 0; + *col = addr / 2; +} + +/**************************************************************************** + * Name: lcd_set_curpos + * + * Description: + * This sets the cursor position based on row, column addressing. + * + * Input Parameters: + * priv - device instance + * + ****************************************************************************/ + +static void lcd_set_curpos(FAR struct ht16k33_dev_s *priv) +{ + uint8_t addr; + int dev_id; + + addr = rc2addr(priv); + dev_id = priv->col / 4; + + /* Define the memory address position */ + + ht16k33_write_cmd(priv, dev_id, HT16K33_DISP_DATA_ADDR | addr); +} + +/**************************************************************************** + * Name: lcd_putdata + * + * Description: + * Write a byte to the LCD and update column/row position + * + ****************************************************************************/ + +static inline void lcd_putdata(FAR struct ht16k33_dev_s *priv, uint8_t data) +{ + uint8_t segment[2]; + uint8_t addr; + uint8_t cmd; + int dev_id; + + /* Get current display memory position */ + + addr = rc2addr(priv); + + /* Setup the memory command */ + + cmd = HT16K33_DISP_DATA_ADDR | addr; + + /* Get the segments setting */ + + segment[0] = asciito14seg[data - 32] & 0xff; + segment[1] = (asciito14seg[data - 32] & 0xff00) >> 8; + + dev_id = priv->col / 4; + + /* Send data to display */ + + ht16k33_write_data(priv, dev_id, cmd, segment, 2); + + /* Save it in the buffer because we cannot read from display */ + + priv->buffer[priv->col * priv->row] = data; + + /* Update col/row positions */ + + priv->col++; + + if (priv->col >= HT16K33_MAX_COL) + { + priv->col = 0; + priv->row++; + } + + if (priv->row >= HT16K33_MAX_ROW) + { + priv->pendscroll = true; + priv->row = HT16K33_MAX_ROW - 1; + } + + /* Update cursor position */ + + lcd_set_curpos(priv); +} + +/**************************************************************************** + * Name: lcd_scroll_up + * + * Description: + * Scroll the display up, and clear the new (last) line. + * + ****************************************************************************/ + +static void lcd_scroll_up(FAR struct ht16k33_dev_s *priv) +{ + FAR uint8_t *data; + int currow; + int curcol; + + data = (FAR uint8_t *)kmm_malloc(HT16K33_MAX_COL); + if (NULL == data) + { + lcdinfo("Failed to allocate buffer in lcd_scroll_up()\n"); + return; + } + + for (currow = 1; currow < HT16K33_MAX_ROW; ++currow) + { + priv->row = currow; + for (curcol = 0; curcol < HT16K33_MAX_COL; ++curcol) + { + priv->col = curcol; + data[curcol] = lcd_getdata(priv); + } + + priv->col = 0; + priv->row = currow - 1; + lcd_set_curpos(priv); + for (curcol = 0; curcol < HT16K33_MAX_COL; ++curcol) + { + lcd_putdata(priv, data[curcol]); + } + } + + ht16k33_clear_display(priv); + + kmm_free(data); + return; +} + +/**************************************************************************** + * Name: ht16k33_clear_display + * + * Description: + * Clear the display writing space (' ') to all positions + * + ****************************************************************************/ + +static void ht16k33_clear_display(FAR struct ht16k33_dev_s *priv) +{ + int curcol; + + priv->col = 0; + priv->row = HT16K33_MAX_ROW - 1; + lcd_set_curpos(priv); + for (curcol = 0; curcol < HT16K33_MAX_COL; ++curcol) + { + lcd_putdata(priv, ' '); + } + + priv->col = 0; + priv->row = HT16K33_MAX_ROW - 1; + lcd_set_curpos(priv); +} + +/**************************************************************************** + * Name: lcd_codec_action + * + * Description: + * Perform an 'action' as per the Segment LCD codec. + * + * Input Parameters: + * priv - device instance + * code - SLCD code action code + * count - count param for those actions that take it + * + ****************************************************************************/ + +static void lcd_codec_action(FAR struct ht16k33_dev_s *priv, + enum slcdcode_e code, uint8_t count) +{ + switch (code) + { + /* Erasure */ + + case SLCDCODE_BACKDEL: /* Backspace (backward delete) + * N characters + */ + { + if (count <= 0) /* we need to delete more 0 positions */ + { + break; + } + else + { + if (count > priv->col) /* saturate to preceding columns + * available + */ + { + count = priv->col; + } + + priv->col = priv->col - count; + lcd_set_curpos(priv); + } + + /* ... and conscientiously fall through to next case ... */ + } + + case SLCDCODE_FWDDEL: /* Delete (forward delete) N characters + * moving text + */ + { + if (count <= 0) /* we need to delete more 0 positions */ + { + break; + } + else + { + uint8_t start; + uint8_t end; + uint8_t i; + uint8_t data; + + start = priv->col + count; + + if (start >= HT16K33_MAX_COL) /* nothing left */ + { + break; + } + + end = start + count; + if (end > HT16K33_MAX_COL) /* saturate */ + { + end = HT16K33_MAX_COL; + } + + for (i = priv->col; i < end; ++start, ++i) /* like memmove */ + { + priv->col = start; + lcd_set_curpos(priv); + data = lcd_getdata(priv); + priv->col = i; + lcd_set_curpos(priv); + lcd_putdata(priv, data); + } + + for (; i < HT16K33_MAX_COL; ++i) /* much like memset */ + { + lcd_putdata(priv, ' '); + } + + lcd_set_curpos(priv); + } + } + break; + + case SLCDCODE_ERASE: /* Erase N characters from the cursor + * position + */ + if (count > 0) + { + uint8_t end; + uint8_t i; + + end = priv->col + count; + if (end > HT16K33_MAX_COL) + { + end = HT16K33_MAX_COL; + } + + for (i = priv->col; i < end; ++i) + { + lcd_putdata(priv, ' '); + } + + lcd_set_curpos(priv); + } + break; + + case SLCDCODE_CLEAR: /* Home the cursor and erase the entire + * display + */ + { + /* ht16k33_write_cmd(priv, HT16K33_CLEAR_DISPLAY); */ + } + break; + + case SLCDCODE_ERASEEOL: /* Erase from the cursor position to + * the end of line + */ + { + uint8_t i; + + for (i = priv->col; i < HT16K33_MAX_COL; ++i) + { + lcd_putdata(priv, ' '); + } + + lcd_set_curpos(priv); + } + break; + + /* Cursor movement */ + + case SLCDCODE_LEFT: /* Cursor left by N characters */ + { + if (count > priv->col) + { + priv->col = 0; + } + else + { + priv->col -= count; + } + + lcd_set_curpos(priv); + } + break; + + case SLCDCODE_RIGHT: /* Cursor right by N characters */ + { + priv->col += count; + if (priv->col >= HT16K33_MAX_COL) + { + priv->col = HT16K33_MAX_COL - 1; + } + + lcd_set_curpos(priv); + } + break; + + case SLCDCODE_UP: /* Cursor up by N lines */ + { + if (count > priv->row) + { + priv->row = 0; + } + else + { + priv->row -= count; + } + + lcd_set_curpos(priv); + } + break; + + case SLCDCODE_DOWN: /* Cursor down by N lines */ + { + priv->row += count; + if (priv->row >= HT16K33_MAX_ROW) + { + priv->row = HT16K33_MAX_ROW - 1; + } + + lcd_set_curpos(priv); + } + break; + + case SLCDCODE_HOME: /* Cursor home */ + { + priv->col = 0; + lcd_set_curpos(priv); + } + break; + + case SLCDCODE_END: /* Cursor end */ + { + priv->col = HT16K33_MAX_COL - 1; + lcd_set_curpos(priv); + } + break; + + case SLCDCODE_PAGEUP: /* Cursor up by N pages */ + case SLCDCODE_PAGEDOWN: /* Cursor down by N pages */ + break; /* Not supportable on this SLCD */ + + /* Blinking */ + + case SLCDCODE_BLINKSTART: /* Start blinking with current cursor + * position + */ + ht16k33_write_cmd(priv, 0, HT16K33_DISPLAY_SETUP | + DISPLAY_SETUP_BLINK_2HZ); + break; + + case SLCDCODE_BLINKEND: /* End blinking after the current cursor + * position + */ + case SLCDCODE_BLINKOFF: /* Turn blinking off */ + ht16k33_write_cmd(priv, 0, HT16K33_DISPLAY_SETUP | + DISPLAY_SETUP_BLINK_OFF); + break; /* Not implemented */ + + /* These are actually unreportable errors */ + + default: + case SLCDCODE_NORMAL: /* Not a special keycode */ + break; + } +} + +/**************************************************************************** + * Name: lcd_getstream + * + * Description: + * Get one character from the LCD codec stream. + * + ****************************************************************************/ + +static int lcd_getstream(FAR struct lib_instream_s *instream) +{ + FAR struct lcd_instream_s *lcdstream = + (FAR struct lcd_instream_s *)instream; + + if (lcdstream->nbytes > 0) + { + lcdstream->nbytes--; + lcdstream->stream.nget++; + return (int)*lcdstream->buffer++; + } + + return EOF; +} + +/**************************************************************************** + * Name: lcd_init + * + * Description: + * perform the initialization sequence to get the LCD into a known state. + * + ****************************************************************************/ + +static void lcd_init(FAR struct ht16k33_dev_s *priv) +{ + uint8_t data; + int i; + + for (i = 0; i < CONFIG_LCD_HT16K33_NUMBER_MODULES; i++) + { + /* Initialize the Display: Turn ON Oscillator */ + + data = HT16K33_SYSTEM_SETUP | SYSTEM_SETUP_OSC_ON; + + ht16k33_write_cmd(priv, i, data); + + /* Clear display */ + + ht16k33_clear_display(priv); + + /* Display ON */ + + data = HT16K33_DISPLAY_SETUP | DISPLAY_SETUP_DISP_ON; + + ht16k33_write_cmd(priv, i, data); + } +} + +/**************************************************************************** + * Name: lcd_curpos_to_fpos + * + * Description: + * Convert a screen cursor pos (row,col) to a file logical offset. This + * includes 'synthesized' line feeds at the end of screen lines. + * + ****************************************************************************/ + +static void lcd_curpos_to_fpos(FAR struct ht16k33_dev_s *priv, + uint8_t row, uint8_t col, FAR off_t *fpos) +{ + /* the logical file position is the linear position plus any synthetic LF */ + + *fpos = (row * HT16K33_MAX_COL) + col + row; +} + +/**************************************************************************** + * Name: ht16k33_open + * + * Description: + * This function is called whenever the HT16K33 device is opened. + * + ****************************************************************************/ + +static int ht16k33_open(FAR struct file *filep) +{ + return OK; +} + +/**************************************************************************** + * Name: ht16k33_close + * + * Description: + * This routine is called when the LM-75 device is closed. + * + ****************************************************************************/ + +static int ht16k33_close(FAR struct file *filep) +{ + return OK; +} + +/**************************************************************************** + * Name: ht16k33_read + ****************************************************************************/ + +static ssize_t ht16k33_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Name: ht16k33_write + ****************************************************************************/ + +static ssize_t ht16k33_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct ht16k33_dev_s *priv = inode->i_private; + struct lcd_instream_s instream; + struct slcdstate_s state; + enum slcdret_e result; + uint8_t ch; + uint8_t count; + + nxsem_wait(&priv->sem_excl); + + /* Initialize the stream for use with the SLCD CODEC */ + + instream.stream.get = lcd_getstream; + instream.stream.nget = 0; + instream.buffer = buffer; + instream.nbytes = buflen; + + /* Now decode and process every byte in the input buffer */ + + memset(&state, 0, sizeof(struct slcdstate_s)); + while ((result = slcd_decode(&instream.stream, &state, &ch, &count)) != + SLCDRET_EOF) + { + /* Is there some pending scroll? */ + + if (priv->pendscroll) + { + lcd_scroll_up(priv); + priv->pendscroll = false; + } + + if (result == SLCDRET_CHAR) /* A normal character was returned */ + { + /* Check for ASCII control characters */ + + if (ch == ASCII_TAB) + { + /* TODO: define what TAB should do */ + } + else if (ch == ASCII_VT) + { + /* Turn the backlight on */ + + /* TODO: lcd_backlight(priv, true); */ + } + else if (ch == ASCII_FF) + { + /* Turn the backlight off */ + + /* TODO: lcd_backlight(priv, false); */ + } + else if (ch == ASCII_CR) + { + /* Perform a Home */ + + priv->col = 0; + lcd_set_curpos(priv); + } + else if (ch == ASCII_SO) + { + /* TODO: We don't have cursor */ + } + else if (ch == ASCII_SI) + { + /* Perform the re-initialize */ + + lcd_init(priv); + priv->row = 0; + priv->col = 0; + } + else if (ch == ASCII_LF) + { + /* unixian line term; go to start of next line */ + + priv->row += 1; + if (priv->row >= HT16K33_MAX_ROW) + { + priv->pendscroll = true; + priv->row = HT16K33_MAX_ROW - 1; + } + + priv->col = 0; + lcd_set_curpos(priv); + } + else if (ch == ASCII_BS) + { + /* Perform the backward deletion */ + + lcd_codec_action(priv, SLCDCODE_BACKDEL, 1); + } + else if (ch == ASCII_DEL) + { + /* Perform the forward deletion */ + + lcd_codec_action(priv, SLCDCODE_FWDDEL, 1); + } + else + { + /* Just print it! */ + + lcd_putdata(priv, ch); + } + } + else /* (result == SLCDRET_SPEC) */ /* A special SLCD action was returned */ + { + lcd_codec_action(priv, (enum slcdcode_e)ch, count); + } + } + + /* Wherever we wound up, update our logical file pos to reflect it */ + + lcd_curpos_to_fpos(priv, priv->row, priv->col, &filep->f_pos); + + nxsem_post(&priv->sem_excl); + return buflen; +} + +/**************************************************************************** + * Name: ht16k33_seek + * + * Description: + * Seek the logical file pointer to the specified position. This is + * probably not very interesting except possibly for (SEEK_SET, 0) to + * rewind the pointer for a subsequent read(). + * The file pointer is logical, and includes synthesized LF chars at the + * end of the display lines. + * + ****************************************************************************/ + +static off_t ht16k33_seek(FAR struct file *filep, off_t offset, int whence) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct ht16k33_dev_s *priv = + (FAR struct ht16k33_dev_s *)inode->i_private; + off_t maxpos; + off_t pos; + + nxsem_wait(&priv->sem_excl); + + maxpos = HT16K33_MAX_ROW * HT16K33_MAX_COL + (HT16K33_MAX_ROW - 1); + pos = filep->f_pos; + + switch (whence) + { + case SEEK_CUR: + pos += offset; + if (pos > maxpos) + { + pos = maxpos; + } + else if (pos < 0) + { + pos = 0; + } + + filep->f_pos = pos; + break; + + case SEEK_SET: + pos = offset; + if (pos > maxpos) + { + pos = maxpos; + } + else if (pos < 0) + { + pos = 0; + } + + filep->f_pos = pos; + break; + + case SEEK_END: + pos = maxpos + offset; + if (pos > maxpos) + { + pos = maxpos; + } + else if (pos < 0) + { + pos = 0; + } + + filep->f_pos = pos; + break; + + default: + + /* Return EINVAL if the whence argument is invalid */ + + pos = (off_t)-EINVAL; + break; + } + + nxsem_post(&priv->sem_excl); + return pos; +} + +/**************************************************************************** + * Name: ht16k33_ioctl + * + * Description: + * Perform device operations that are outside the standard I/O model. + * + ****************************************************************************/ + +static int ht16k33_ioctl(FAR struct file *filep, int cmd, + unsigned long arg) +{ + switch (cmd) + { + case SLCDIOC_GETATTRIBUTES: /* Get the attributes of the SLCD */ + { + FAR struct slcd_attributes_s *attr = + (FAR struct slcd_attributes_s *)((uintptr_t)arg); + + lcdinfo("SLCDIOC_GETATTRIBUTES:\n"); + + if (!attr) + { + return -EINVAL; + } + + attr->nrows = HT16K33_MAX_ROW; + attr->ncolumns = HT16K33_MAX_COL; + attr->nbars = 0; + attr->maxcontrast = 0; + attr->maxbrightness = 16; /* 'brightness' for us is the backlight */ + } + break; + + case SLCDIOC_CURPOS: /* Get the SLCD cursor position */ + { + FAR struct inode *inode = filep->f_inode; + FAR struct ht16k33_dev_s *priv = + (FAR struct ht16k33_dev_s *)inode->i_private; + FAR struct slcd_curpos_s *attr = + (FAR struct slcd_curpos_s *)((uintptr_t)arg); + + attr->row = priv->row; + attr->column = priv->col; + } + break; + + case SLCDIOC_GETBRIGHTNESS: /* Get the current brightness setting */ + { + FAR struct inode *inode = filep->f_inode; + FAR struct ht16k33_dev_s *priv = + (FAR struct ht16k33_dev_s *)inode->i_private; + + nxsem_wait(&priv->sem_excl); + *(FAR int *)((uintptr_t)arg) = 1; /* Hardcoded */ + nxsem_post(&priv->sem_excl); + } + break; + + case SLCDIOC_SETBRIGHTNESS: /* Set the brightness to a new value */ + { + FAR struct inode *inode = filep->f_inode; + FAR struct ht16k33_dev_s *priv = + (FAR struct ht16k33_dev_s *)inode->i_private; + + nxsem_wait(&priv->sem_excl); + + ht16k33_setcontrast(priv, 0, (uint8_t)arg); + + nxsem_post(&priv->sem_excl); + } + break; + + case SLCDIOC_SETBAR: /* Set bars on a bar display */ + case SLCDIOC_GETCONTRAST: /* Get the current contrast setting */ + case SLCDIOC_SETCONTRAST: /* Set the contrast to a new value */ + default: + return -ENOTTY; + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ht16k33_register + * + * Description: + * Register the HT16K33 character device as 'devpath' + * + * Input Parameters: + * devno - The device number to register. E.g., "/dev/slcd0" + * i2c - An instance of the I2C interface to use to communicate with + * HT16K33 + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int ht16k33_register(int devno, FAR struct i2c_master_s *i2c) +{ + FAR struct ht16k33_dev_s *priv; + char devname[DEVNAME_FMTLEN]; + int ret; + + /* Initialize the HT16K33 device structure */ + + priv = (FAR struct ht16k33_dev_s *) + kmm_malloc(sizeof(struct ht16k33_dev_s)); + if (!priv) + { + snerr("ERROR: Failed to allocate instance\n"); + return -ENOMEM; + } + + /* Setup priv with initial values */ + + priv->i2c = i2c; + priv->col = 0; + priv->row = 0; + priv->pendscroll = false; + + nxsem_init(&priv->sem_excl, 0, 1); + + /* Initialize the display */ + + lcd_init(priv); + + /* Create the character device name */ + + snprintf(devname, DEVNAME_FMTLEN, DEVNAME_FMT, devno); + + /* Register the driver */ + + ret = register_driver(devname, &g_ht16k33fops, 0666, priv); + if (ret < 0) + { + snerr("ERROR: Failed to register driver: %d\n", ret); + kmm_free(priv); + } + + return ret; +} +#endif /* CONFIG_SPI && CONFIG_HT16K33 */ diff --git a/drivers/lcd/ili9225.c b/drivers/lcd/ili9225.c index b7807ec38d6..f339caec210 100644 --- a/drivers/lcd/ili9225.c +++ b/drivers/lcd/ili9225.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/ili9340.c b/drivers/lcd/ili9340.c index dd738520b12..29b8f56da0e 100644 --- a/drivers/lcd/ili9340.c +++ b/drivers/lcd/ili9340.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/ili9341.c b/drivers/lcd/ili9341.c index 7d63e59461a..187e1071ce8 100644 --- a/drivers/lcd/ili9341.c +++ b/drivers/lcd/ili9341.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/lpm013m091a.c b/drivers/lcd/lpm013m091a.c index 0609b0632e5..5ce914212fa 100644 --- a/drivers/lcd/lpm013m091a.c +++ b/drivers/lcd/lpm013m091a.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/max7219.c b/drivers/lcd/max7219.c index 8d95ef786fc..17174671fd6 100644 --- a/drivers/lcd/max7219.c +++ b/drivers/lcd/max7219.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/memlcd.c b/drivers/lcd/memlcd.c index 76dc2f35eed..85e15549a36 100644 --- a/drivers/lcd/memlcd.c +++ b/drivers/lcd/memlcd.c @@ -1,37 +1,20 @@ /**************************************************************************** * drivers/lcd/memlcd.c - * Driver for Sharp Memory LCD. * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Librae + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -45,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/mio283qt2.c b/drivers/lcd/mio283qt2.c index d27f0d5190d..9b351cd8381 100644 --- a/drivers/lcd/mio283qt2.c +++ b/drivers/lcd/mio283qt2.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/mio283qt9a.c b/drivers/lcd/mio283qt9a.c index 5117da40a04..cd0f5fed608 100644 --- a/drivers/lcd/mio283qt9a.c +++ b/drivers/lcd/mio283qt9a.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/lcd/mio283qt9a.c * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Tobias Duckworth + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -44,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/p14201.c b/drivers/lcd/p14201.c index 159ed827bed..40384164cf6 100644 --- a/drivers/lcd/p14201.c +++ b/drivers/lcd/p14201.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/pcd8544.c b/drivers/lcd/pcd8544.c index 29f69fe651c..04cf853ed16 100644 --- a/drivers/lcd/pcd8544.c +++ b/drivers/lcd/pcd8544.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/pcf8574_lcd_backpack.c b/drivers/lcd/pcf8574_lcd_backpack.c index 5883a1679f4..9d87594e69d 100644 --- a/drivers/lcd/pcf8574_lcd_backpack.c +++ b/drivers/lcd/pcf8574_lcd_backpack.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/lcd/pcf8574_lcd_backpack.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/lcd/ra8875.c b/drivers/lcd/ra8875.c index cce2ffd7c23..c63a38ef529 100644 --- a/drivers/lcd/ra8875.c +++ b/drivers/lcd/ra8875.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/skeleton.c b/drivers/lcd/skeleton.c index b34db01af78..6b8e419da29 100644 --- a/drivers/lcd/skeleton.c +++ b/drivers/lcd/skeleton.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/ssd1289.c b/drivers/lcd/ssd1289.c index 122df9bddbb..2d1f0a3e3cc 100644 --- a/drivers/lcd/ssd1289.c +++ b/drivers/lcd/ssd1289.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/ssd1306_base.c b/drivers/lcd/ssd1306_base.c index 0ba1c7c5e27..8957873f91e 100644 --- a/drivers/lcd/ssd1306_base.c +++ b/drivers/lcd/ssd1306_base.c @@ -116,6 +116,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/ssd1351.c b/drivers/lcd/ssd1351.c index a44582c288f..e696800d9fb 100644 --- a/drivers/lcd/ssd1351.c +++ b/drivers/lcd/ssd1351.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/st7565.c b/drivers/lcd/st7565.c index ec9f7b3c903..e6fb2a0b900 100644 --- a/drivers/lcd/st7565.c +++ b/drivers/lcd/st7565.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/st7567.c b/drivers/lcd/st7567.c index 75ad64c4f58..6c8a46b491a 100644 --- a/drivers/lcd/st7567.c +++ b/drivers/lcd/st7567.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/st7735.c b/drivers/lcd/st7735.c index c4cbb8a9e54..e663409a8ac 100644 --- a/drivers/lcd/st7735.c +++ b/drivers/lcd/st7735.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/st7789.c b/drivers/lcd/st7789.c index d7567094e34..a9e519e4bea 100644 --- a/drivers/lcd/st7789.c +++ b/drivers/lcd/st7789.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -196,6 +197,9 @@ static void st7789_fill(FAR struct st7789_dev_s *dev, uint16_t color); static int st7789_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, size_t npixels); +static int st7789_putarea(fb_coord_t row_start, fb_coord_t row_end, + fb_coord_t col_start, fb_coord_t col_end, + FAR const uint8_t *buffer); #ifndef CONFIG_LCD_NOGETRUN static int st7789_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, size_t npixels); @@ -518,6 +522,40 @@ static int st7789_putrun(fb_coord_t row, fb_coord_t col, return OK; } +/**************************************************************************** + * Name: st7789_putarea + * + * Description: + * This method can be used to write a partial area to the LCD: + * + * row_start - Starting row to write to (range: 0 <= row < yres) + * row_end - Ending row to write to (range: row_start <= row < yres) + * col_start - Starting column to write to (range: 0 <= col <= xres) + * col_end - Ending column to write to + * (range: col_start <= col_end < xres) + * buffer - The buffer containing the area to be written to the LCD + * + ****************************************************************************/ + +static int st7789_putarea(fb_coord_t row_start, fb_coord_t row_end, + fb_coord_t col_start, fb_coord_t col_end, + FAR const uint8_t *buffer) +{ + FAR struct st7789_dev_s *priv = &g_lcddev; + FAR const uint16_t *src = (FAR const uint16_t *)buffer; + + ginfo("row_start: %d row_end: %d col_start: %d col_end: %d\n", + row_start, row_end, col_start, col_end); + + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + st7789_setarea(priv, col_start, row_start, col_end, row_end); + st7789_wrram(priv, src, + (row_end - row_start + 1) * (col_end - col_start + 1)); + + return OK; +} + /**************************************************************************** * Name: st7789_getrun * @@ -589,6 +627,7 @@ static int st7789_getplaneinfo(FAR struct lcd_dev_s *dev, lcdinfo("planeno: %d bpp: %d\n", planeno, ST7789_BPP); pinfo->putrun = st7789_putrun; /* Put a run into LCD memory */ + pinfo->putarea = st7789_putarea; /* Put an area into LCD */ #ifndef CONFIG_LCD_NOGETRUN pinfo->getrun = st7789_getrun; /* Get a run from LCD memory */ #endif diff --git a/drivers/lcd/tda19988.c b/drivers/lcd/tda19988.c index 7e13a0de398..41867d3e4f5 100644 --- a/drivers/lcd/tda19988.c +++ b/drivers/lcd/tda19988.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/ug-2864ambag01.c b/drivers/lcd/ug-2864ambag01.c index 4f436c35177..9cc6f2b83ba 100644 --- a/drivers/lcd/ug-2864ambag01.c +++ b/drivers/lcd/ug-2864ambag01.c @@ -113,6 +113,7 @@ #include #include #include +#include #include #include diff --git a/drivers/lcd/ug-9664hswag01.c b/drivers/lcd/ug-9664hswag01.c index 957327085f1..afe9fb839f3 100644 --- a/drivers/lcd/ug-9664hswag01.c +++ b/drivers/lcd/ug-9664hswag01.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include diff --git a/drivers/leds/ncp5623c.c b/drivers/leds/ncp5623c.c index 31b1f1f093d..e387f6bbd3d 100644 --- a/drivers/leds/ncp5623c.c +++ b/drivers/leds/ncp5623c.c @@ -39,6 +39,7 @@ #include +#include #include #include diff --git a/drivers/leds/pca9635pw.c b/drivers/leds/pca9635pw.c index 59087528e4b..dcd3afd6b9e 100644 --- a/drivers/leds/pca9635pw.c +++ b/drivers/leds/pca9635pw.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/drivers/leds/userled_upper.c b/drivers/leds/userled_upper.c index dc8cb102fcc..9ebfe970599 100644 --- a/drivers/leds/userled_upper.c +++ b/drivers/leds/userled_upper.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/drivers/loop/losetup.c b/drivers/loop/losetup.c index bf7c5c7862a..ca5c4c5f02a 100644 --- a/drivers/loop/losetup.c +++ b/drivers/loop/losetup.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index 226f56f09f3..a94a526fcc5 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mmcsd/mmcsd_spi.c b/drivers/mmcsd/mmcsd_spi.c index 942966469a9..31dbe18632d 100644 --- a/drivers/mmcsd/mmcsd_spi.c +++ b/drivers/mmcsd/mmcsd_spi.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/modem/altair/altmdm_pm.c b/drivers/modem/altair/altmdm_pm.c index df57dc23aef..9fd72688561 100644 --- a/drivers/modem/altair/altmdm_pm.c +++ b/drivers/modem/altair/altmdm_pm.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/drivers/modem/altair/altmdm_spi.c b/drivers/modem/altair/altmdm_spi.c index ec62233eeeb..7e261d25c25 100644 --- a/drivers/modem/altair/altmdm_spi.c +++ b/drivers/modem/altair/altmdm_spi.c @@ -23,6 +23,7 @@ ****************************************************************************/ #include +#include #include #include @@ -1232,12 +1233,24 @@ static int do_trxreset(FAR struct altmdm_dev_s *priv) ret = wait_receiverready(priv, WAIT_RXREQ_TIMEOUT); if (ret >= 0) { - /* If a conflict occurs with the reset packet, - * the packet is transferred by the size specified - * by the receiving side. Discard the data on the sending side. + /* Even in the case of a conflict between a reset packet + * and a send packet, the send size is compared and the + * larger size is sent as the payload. + * If the send packet that conflicts with the reset packet + * is in ALTCOM command format, the modem may assert. + * If it is not in the ALTCOM command format, it will be + * discarded by the modem, so dummy data will be sent to + * avoid assertion. */ - xfer_size = spidev->rx_param.total_size; + if (spidev->tx_param.total_size < spidev->rx_param.total_size) + { + xfer_size = spidev->rx_param.total_size; + } + else + { + xfer_size = spidev->tx_param.total_size; + } /* Get DMA transfer size */ diff --git a/drivers/modem/u-blox.c b/drivers/modem/u-blox.c index 2fb3b93ae1f..3628df7c1c3 100644 --- a/drivers/modem/u-blox.c +++ b/drivers/modem/u-blox.c @@ -43,6 +43,8 @@ #include #include #include +#include +#include #include #include diff --git a/drivers/motor/Kconfig b/drivers/motor/Kconfig index a6a6f2f1f6b..7c220916b42 100644 --- a/drivers/motor/Kconfig +++ b/drivers/motor/Kconfig @@ -9,6 +9,56 @@ menuconfig MOTOR if MOTOR +config MOTOR_UPPER + bool "Motor generic upper-half driver" + default n + ---help--- + Enables building of a motor generic upper half driver. + +if MOTOR_UPPER + +config MOTOR_UPPER_HAVE_POSITION + bool "Have position control" + default n + +config MOTOR_UPPER_HAVE_DIRECTION + bool "Have direction control" + default n + +config MOTOR_UPPER_HAVE_SPEED + bool "Have speed control" + default n + +config MOTOR_UPPER_HAVE_TORQUE + bool "Have torque control (rotary motors)" + default n + +config MOTOR_UPPER_HAVE_FORCE + bool "Have force control (linear motors)" + default n + +config MOTOR_UPPER_HAVE_ACCELERATION + bool "Have acceleration control" + default n + +config MOTOR_UPPER_HAVE_DECELERATION + bool "Have deceleration control" + default n + +config MOTOR_UPPER_HAVE_INPUT_VOLTAGE + bool "Have input voltage protection" + default n + +config MOTOR_UPPER_HAVE_INPUT_CURRENT + bool "Have input current protection" + default n + +config MOTOR_UPPER_HAVE_INPUT_POWER + bool "Have input power protection" + default n + +endif + source "drivers/motor/foc/Kconfig" endif # MOTOR diff --git a/drivers/motor/Make.defs b/drivers/motor/Make.defs index 5a05409b923..40080e5aa90 100644 --- a/drivers/motor/Make.defs +++ b/drivers/motor/Make.defs @@ -24,11 +24,17 @@ ifeq ($(CONFIG_MOTOR_FOC),y) include motor$(DELIM)foc$(DELIM)Make.defs endif +# Add generic upper-half motor driver + +ifeq ($(CONFIG_MOTOR_UPPER),y) +CSRCS += motor.c +endif + # Include motor drivers in the build MOTOR_DEPPATH := --dep-path motor MOTOR_VPATH := :motor -MOTOR_CFLAGS := ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)motr} +MOTOR_CFLAGS := ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)motor} DEPPATH += $(MOTOR_DEPPATH) VPATH += $(MOTOR_VPATH) diff --git a/drivers/power/motor.c b/drivers/motor/motor.c similarity index 85% rename from drivers/power/motor.c rename to drivers/motor/motor.c index fafba7fcda1..14e41846168 100644 --- a/drivers/power/motor.c +++ b/drivers/motor/motor.c @@ -1,5 +1,5 @@ /**************************************************************************** - * drivers/power/motor.c + * drivers/motor/motor.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -30,12 +30,13 @@ #include #include #include +#include #include #include #include #include -#include +#include #include @@ -214,7 +215,7 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) switch (cmd) { - case PWRIOC_START: + case MTRIOC_START: { /* Allow motor start only when some limits available * and structure is locked. @@ -222,30 +223,30 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) if ((motor->limits.lock == false) || ( -#ifdef CONFIG_MOTOR_HAVE_POSITION +#ifdef CONFIG_MOTOR_UPPER_HAVE_POSITION motor->limits.position <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_SPEED +#ifdef CONFIG_MOTOR_UPPER_HAVE_SPEED motor->limits.speed <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_TORQUE +#ifdef CONFIG_MOTOR_UPPER_HAVE_TORQUE motor->limits.torque <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_FORCE +#ifdef CONFIG_MOTOR_UPPER_HAVE_FORCE motor->limits.force <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_VOLTAGE +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_VOLTAGE motor->limits.v_in <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_CURRENT +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_CURRENT motor->limits.i_in <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_POWER +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_POWER motor->limits.p_in <= 0.0 && #endif 1)) { - pwrerr("ERROR: motor limits data must be set" + mtrerr("Motor limits data must be set" " and locked before motor start\n"); ret = -EPERM; @@ -256,7 +257,7 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) if (motor->opmode == MOTOR_OPMODE_INIT) { - pwrerr("ERROR: motor operation mode not specified\n"); + mtrerr("Motor operation mode not specified\n"); ret = -EPERM; goto errout; @@ -269,43 +270,43 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) ret = dev->ops->start(dev); if (ret != OK) { - pwrerr("ERROR: PWRIOC_START failed %d\n", ret); + mtrerr("MTRIOC_START failed %d\n", ret); } break; } - case PWRIOC_STOP: + case MTRIOC_STOP: { /* Call stop from lower-half driver */ ret = dev->ops->stop(dev); if (ret != OK) { - pwrerr("ERROR: PWRIOC_STOP failed %d\n", ret); + mtrerr("MTRIOC_STOP failed %d\n", ret); } break; } - case PWRIOC_SET_MODE: + case MTRIOC_SET_MODE: { uint8_t mode = ((uint8_t)arg); ret = dev->ops->mode_set(dev, mode); if (ret != OK) { - pwrerr("ERROR: PWRIOC_SET_MODE failed %d\n", ret); + mtrerr("MTRIOC_SET_MODE failed %d\n", ret); } break; } - case PWRIOC_SET_LIMITS: + case MTRIOC_SET_LIMITS: { FAR struct motor_limits_s *limits = (FAR struct motor_limits_s *)((uintptr_t)arg); if (motor->limits.lock == true) { - pwrerr("ERROR: motor limits locked!\n"); + mtrerr("Motor limits locked!\n"); ret = -EPERM; goto errout; @@ -316,12 +317,12 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) ret = dev->ops->limits_set(dev, limits); if (ret != OK) { - pwrerr("ERROR: PWRIOC_SET_LIMITS failed %d\n", ret); + mtrerr("MTRIOC_SET_LIMITS failed %d\n", ret); } break; } - case PWRIOC_GET_STATE: + case MTRIOC_GET_STATE: { FAR struct motor_state_s *state = (FAR struct motor_state_s *)((uintptr_t)arg); @@ -329,55 +330,55 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) ret = dev->ops->state_get(dev, state); if (ret != OK) { - pwrerr("ERROR: PWRIOC_GET_STATE failed %d\n", ret); + mtrerr("MTRIOC_GET_STATE failed %d\n", ret); } break; } - case PWRIOC_SET_FAULT: + case MTRIOC_SET_FAULT: { uint8_t fault = ((uint8_t)arg); ret = dev->ops->fault_set(dev, fault); if (ret != OK) { - pwrerr("ERROR: PWRIOC_SET_FAULT failed %d\n", ret); + mtrerr("MTRIOC_SET_FAULT failed %d\n", ret); } break; } - case PWRIOC_GET_FAULT: + case MTRIOC_GET_FAULT: { FAR uint8_t *fault = ((FAR uint8_t *)arg); ret = dev->ops->fault_get(dev, fault); if (ret != OK) { - pwrerr("ERROR: PWRIOC_GET_FAULT failed %d\n", ret); + mtrerr("MTRIOC_GET_FAULT failed %d\n", ret); } break; } - case PWRIOC_CLEAN_FAULT: + case MTRIOC_CLEAR_FAULT: { uint8_t fault = ((uint8_t)arg); - ret = dev->ops->fault_clean(dev, fault); + ret = dev->ops->fault_clear(dev, fault); if (ret != OK) { - pwrerr("ERROR: PWRIOC_CLEAN_FAULT failed %d\n", ret); + mtrerr("MTRIOC_CLEAR_FAULT failed %d\n", ret); } break; } - case PWRIOC_SET_PARAMS: + case MTRIOC_SET_PARAMS: { FAR struct motor_params_s *params = (FAR struct motor_params_s *)((uintptr_t)arg); if (motor->param.lock == true) { - pwrerr("ERROR: motor params locked!\n"); + mtrerr("Motor params locked!\n"); ret = -EPERM; goto errout; @@ -385,42 +386,42 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) if ((motor->limits.lock == false) || ( -#ifdef CONFIG_MOTOR_HAVE_POSITION +#ifdef CONFIG_MOTOR_UPPER_HAVE_POSITION motor->limits.position <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_SPEED +#ifdef CONFIG_MOTOR_UPPER_HAVE_SPEED motor->limits.speed <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_TORQUE +#ifdef CONFIG_MOTOR_UPPER_HAVE_TORQUE motor->limits.torque <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_FORCE +#ifdef CONFIG_MOTOR_UPPER_HAVE_FORCE motor->limits.force <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_VOLTAGE +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_VOLTAGE motor->limits.v_in <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_CURRENT +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_CURRENT motor->limits.i_in <= 0.0 && #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_POWER +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_POWER motor->limits.p_in <= 0.0 && #endif 1)) { - pwrerr("ERROR: limits must be set prior to params!\n"); + mtrerr("Limits must be set prior to params!\n"); ret = -EPERM; goto errout; } -#ifdef CONFIG_MOTOR_HAVE_DIRECTION +#ifdef CONFIG_MOTOR_UPPER_HAVE_DIRECTION /* Check direction configuration */ if (params->direction != MOTOR_DIR_CCW && params->direction != MOTOR_DIR_CW) { - pwrerr("ERROR: invalid direction value %d\n", + mtrerr("Invalid direction value %d\n", params->direction); ret = -EPERM; @@ -428,13 +429,13 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } #endif -#ifdef CONFIG_MOTOR_HAVE_POSITION +#ifdef CONFIG_MOTOR_UPPER_HAVE_POSITION /* Check position configuration */ if (params->position < 0.0 || params->position > motor->limits.position) { - pwrerr("ERROR: params->position > limits.position: " + mtrerr("params->position > limits.position: " "%.2f > %.2f\n", params->position, motor->limits.position); @@ -443,13 +444,13 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } #endif -#ifdef CONFIG_MOTOR_HAVE_SPEED +#ifdef CONFIG_MOTOR_UPPER_HAVE_SPEED /* Check speed configuration */ if (motor->limits.speed > 0.0 && params->speed > motor->limits.speed) { - pwrerr("ERROR: params->speed > limits.speed: %.2f > %.2f\n", + mtrerr("params->speed > limits.speed: %.2f > %.2f\n", params->speed, motor->limits.speed); ret = -EPERM; @@ -457,13 +458,13 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } #endif -#ifdef CONFIG_MOTOR_HAVE_TORQUE +#ifdef CONFIG_MOTOR_UPPER_HAVE_TORQUE /* Check torque configuration */ if (motor->limits.torque > 0.0 && params->torque > motor->limits.torque) { - pwrerr("ERROR: params->torque > limits.torque: %.2f > %.2f\n", + mtrerr("params->torque > limits.torque: %.2f > %.2f\n", params->torque, motor->limits.torque); ret = -EPERM; @@ -471,13 +472,13 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } #endif -#ifdef CONFIG_MOTOR_HAVE_FORCE +#ifdef CONFIG_MOTOR_UPPER_HAVE_FORCE /* Check force configuration */ if (motor->limits.force > 0.0 && params->force > motor->limits.force) { - pwrerr("ERROR: params->force > limits.force: %.2f > %.2f\n", + mtrerr("params->force > limits.force: %.2f > %.2f\n", params->force, motor->limits.force); ret = -EPERM; @@ -488,14 +489,14 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) ret = dev->ops->params_set(dev, params); if (ret != OK) { - pwrerr("ERROR: PWRIOC_SET_PARAMS failed %d\n", ret); + mtrerr("MTRIOC_SET_PARAMS failed %d\n", ret); } break; } default: { - pwrinfo("Forwarding unrecognized cmd: %d arg: %ld\n", cmd, arg); + mtrinfo("Forwarding unrecognized cmd: %d arg: %ld\n", cmd, arg); ret = dev->ops->ioctl(dev, cmd, arg); break; } @@ -537,7 +538,7 @@ int motor_register(FAR const char *path, FAR struct motor_dev_s *dev, DEBUGASSERT(dev->ops->fault_set != NULL); DEBUGASSERT(dev->ops->state_get != NULL); DEBUGASSERT(dev->ops->fault_get != NULL); - DEBUGASSERT(dev->ops->fault_clean != NULL); + DEBUGASSERT(dev->ops->fault_clear != NULL); DEBUGASSERT(dev->ops->ioctl != NULL); /* Initialize the motor device structure */ diff --git a/drivers/mtd/at24xx.c b/drivers/mtd/at24xx.c index 0e4918ac9e2..9823e0cbd07 100644 --- a/drivers/mtd/at24xx.c +++ b/drivers/mtd/at24xx.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mtd/at25.c b/drivers/mtd/at25.c index 6e410765419..7316d793aef 100644 --- a/drivers/mtd/at25.c +++ b/drivers/mtd/at25.c @@ -1,37 +1,20 @@ /**************************************************************************** * drivers/mtd/at25.c - * Driver for SPI-based AT25DF321 (32Mbit) flash. * - * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/mtd/ftl.c b/drivers/mtd/ftl.c index 572189dc6ec..28741c0f37d 100644 --- a/drivers/mtd/ftl.c +++ b/drivers/mtd/ftl.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mtd/mtd_config.c b/drivers/mtd/mtd_config.c index 3b2d3b79158..48ab8e200f5 100644 --- a/drivers/mtd/mtd_config.c +++ b/drivers/mtd/mtd_config.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mtd/mx25rxx.c b/drivers/mtd/mx25rxx.c index 5a115c51c3c..e99275488f5 100644 --- a/drivers/mtd/mx25rxx.c +++ b/drivers/mtd/mx25rxx.c @@ -1,38 +1,20 @@ /**************************************************************************** * drivers/mtd/mx25rxx.c * - * Copyright (C) 201, 2019 Gregory Nutt. All rights reserved. - * Author: Simon Piriou - - * Derived from QuadSPI-based N25QxxxA driver (drivers/mtd/n25qxxx.c) - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -41,6 +23,7 @@ ****************************************************************************/ #include +#include #include #include #include diff --git a/drivers/mtd/mx35.c b/drivers/mtd/mx35.c index 87b3221492a..d9de59839b3 100644 --- a/drivers/mtd/mx35.c +++ b/drivers/mtd/mx35.c @@ -1,39 +1,20 @@ /**************************************************************************** * drivers/mtd/mx35.c - * Driver for SPI-based MX35LFxGE4AB parts of 1 or 2GBit. * - * Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved. - * Author: Ekaterina Kovylova + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Copied from / based on mx25lx.c driver written by - * Aleksandr Vyhovanec + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/mtd/n25qxxx.c b/drivers/mtd/n25qxxx.c index 3bad978783d..e33263980e3 100644 --- a/drivers/mtd/n25qxxx.c +++ b/drivers/mtd/n25qxxx.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/mtd/n25qxxx.c - * Driver for QuadSPI-based N25QxxxA * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/mtd/ramtron.c b/drivers/mtd/ramtron.c index c6a7cbc1ddc..4cbe13015d6 100644 --- a/drivers/mtd/ramtron.c +++ b/drivers/mtd/ramtron.c @@ -41,6 +41,7 @@ #include #include +#include #include #include #include @@ -506,10 +507,10 @@ static inline int ramtron_readid(struct ramtron_dev_s *priv) UNUSED(manufacturer); /* Eliminate warnings when debug is off */ UNUSED(memory); /* Eliminate warnings when debug is off */ - finfo( - "RAMTRON %s of size %d bytes (mf:%02x mem:%02x cap:%02x part:%02x)\n", - priv->part->name, priv->part->size, - manufacturer, memory, capacity, part); + finfo("RAMTRON %s of size %" PRIu32 " bytes (mf:%02" PRIx16 " mem:%02" + PRIx16 " cap:%02" PRIx16 " part:%02" PRIx16 ")\n", + priv->part->name, priv->part->size, manufacturer, memory, + capacity, part); priv->sectorshift = RAMTRON_EMULATE_SECTOR_SHIFT; priv->nsectors = priv->part->size / @@ -945,7 +946,7 @@ static int ramtron_ioctl(FAR struct mtd_dev_s *dev, geo->neraseblocks = priv->nsectors; ret = OK; - finfo("blocksize: %d erasesize: %d neraseblocks: %d\n", + finfo("blocksize: %ld erasesize: %ld neraseblocks: %ld\n", geo->blocksize, geo->erasesize, geo->neraseblocks); } } diff --git a/drivers/mtd/smart.c b/drivers/mtd/smart.c index 52b7bf32b84..468fb95cce7 100644 --- a/drivers/mtd/smart.c +++ b/drivers/mtd/smart.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -5894,6 +5895,10 @@ static int smart_fsck_directory(FAR struct smart_struct_s *dev, ferr("Invalidate next log sector %d\n", nextsector); *(uint16_t *)chain->nextsector = 0xffff; + + /* Set flag to relocate later */ + + relocate = 1; } } diff --git a/drivers/mtd/w25qxxxjv.c b/drivers/mtd/w25qxxxjv.c index 81bb541c69b..830a814755f 100644 --- a/drivers/mtd/w25qxxxjv.c +++ b/drivers/mtd/w25qxxxjv.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/mtd/w25qxxxjv.c - * Driver for QuadSPI-based W25QxxxJV NOR FLASH * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: kyChu + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 287d0489bc1..3d59d5b1e05 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/encx24j600.c b/drivers/net/encx24j600.c index 7769cb0df41..ef29f4173a1 100644 --- a/drivers/net/encx24j600.c +++ b/drivers/net/encx24j600.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/net/phy_notify.c b/drivers/net/phy_notify.c index 2e29c266058..35b13ebea01 100644 --- a/drivers/net/phy_notify.c +++ b/drivers/net/phy_notify.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/net/slip.c b/drivers/net/slip.c index 78dc637b0f4..a78966e8ab6 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/telnet.c b/drivers/net/telnet.c index c21c24a1095..f2bb20bd13a 100644 --- a/drivers/net/telnet.c +++ b/drivers/net/telnet.c @@ -866,6 +866,13 @@ static ssize_t telnet_read(FAR struct file *filep, FAR char *buffer, } while (nread == 0); + /* Notify the I/O thread the rxbuffer is available */ + + if (nread > 0) + { + nxsem_post(&g_iosem); + } + /* Returned Value: * * nread > 0: The number of characters copied into the user buffer by @@ -1270,7 +1277,10 @@ static int telnet_io_main(int argc, FAR char** argv) for (i = 0; i < CONFIG_TELNET_MAXLCLIENTS; i++) { priv = g_telnet_clients[i]; - if (priv != NULL && !(priv->td_fds.revents & (POLLHUP | POLLERR))) + if (priv != NULL && + !(priv->td_fds.revents & (POLLHUP | POLLERR)) && + (CONFIG_TELNET_RXBUFFER_SIZE - + priv->td_pending - priv->td_offset) > 0) { priv->td_fds.sem = &g_iosem; priv->td_fds.events = POLLIN | POLLHUP | POLLERR; diff --git a/drivers/note/Kconfig b/drivers/note/Kconfig index 61a22740e04..0644402f088 100644 --- a/drivers/note/Kconfig +++ b/drivers/note/Kconfig @@ -46,6 +46,12 @@ config DRIVER_NOTEARCH ---help--- The note driver is provided by arch specific code. +config DRIVER_NOTELOG + bool "Note syslog driver" + select SCHED_INSTRUMENTATION_EXTERNAL + ---help--- + The note driver output to syslog. + endchoice config DRIVER_NOTERAM_BUFSIZE diff --git a/drivers/note/Make.defs b/drivers/note/Make.defs index 943e4ff01c4..fc74611f992 100644 --- a/drivers/note/Make.defs +++ b/drivers/note/Make.defs @@ -26,6 +26,10 @@ ifeq ($(CONFIG_DRIVER_NOTERAM),y) CSRCS += noteram_driver.c endif +ifeq ($(CONFIG_DRIVER_NOTELOG),y) + CSRCS += notelog_driver.c +endif + ifeq ($(CONFIG_DRIVER_NOTECTL),y) CSRCS += notectl_driver.c endif diff --git a/arch/sim/src/sim/up_schednote.c b/drivers/note/notelog_driver.c similarity index 52% rename from arch/sim/src/sim/up_schednote.c rename to drivers/note/notelog_driver.c index e06976b6124..cba8be643f6 100644 --- a/arch/sim/src/sim/up_schednote.c +++ b/drivers/note/notelog_driver.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/sim/src/sim/up_schednote.c + * drivers/note/notelog_driver.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -23,9 +23,12 @@ ****************************************************************************/ #include -#include +#include +#include +#include #include #include +#include /**************************************************************************** * Public Functions @@ -130,6 +133,74 @@ void sched_note_resume(FAR struct tcb_s *tcb) #endif } +#ifdef CONFIG_SMP +void sched_note_cpu_start(FAR struct tcb_s *tcb, int cpu) +{ +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p CPU%d START\n", + tcb->cpu, tcb->name, tcb, cpu); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p CPU%d START\n", + tcb->cpu, tcb, cpu); +#endif +} + +void sched_note_cpu_started(FAR struct tcb_s *tcb) +{ +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p CPU%d STARTED\n", + tcb->cpu, tcb->name, tcb, tcb->cpu); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p CPU%d STARTED\n", + tcb->cpu, tcb, tcb->cpu); +#endif +} + +void sched_note_cpu_pause(FAR struct tcb_s *tcb, int cpu) +{ +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p CPU%d PAUSE\n", + tcb->cpu, tcb->name, tcb, cpu); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p CPU%d PAUSE\n", + tcb->cpu, tcb, cpu); +#endif +} + +void sched_note_cpu_paused(FAR struct tcb_s *tcb) +{ +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p CPU%d PAUSED\n", + tcb->cpu, tcb->name, tcb, tcb->cpu); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p CPU%d PAUSED\n", + tcb->cpu, tcb, tcb->cpu); +#endif +} + +void sched_note_cpu_resume(FAR struct tcb_s *tcb, int cpu) +{ +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p CPU%d RESUME\n", + tcb->cpu, tcb->name, tcb, cpu); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p CPU%d RESUME\n", + tcb->cpu, tcb, cpu); +#endif +} + +void sched_note_cpu_resumed(FAR struct tcb_s *tcb) +{ +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p CPU%d RESUMED\n", + tcb->cpu, tcb->name, tcb, tcb->cpu); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p CPU%d RESUMED\n", + tcb->cpu, tcb, tcb->cpu); +#endif +} +#endif + #ifdef CONFIG_SCHED_INSTRUMENTATION_PREEMPTION /* This does not work well... it interferes with the operation of the * simulated /dev/console device which, of course, does disable preemption @@ -189,3 +260,131 @@ void sched_note_csection(FAR struct tcb_s *tcb, bool enter) #endif } #endif + +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS +void sched_note_spinlock(FAR struct tcb_s *tcb, + FAR volatile void *spinlock) +{ +#ifdef CONFIG_SMP +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p spinlock@%p LOCK\n", + tcb->cpu, tcb->name, tcb, spinlock); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p spinlock@%p LOCK\n", + tcb->cpu, tcb, spinlock); +#endif +#else +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "Task %s TCB@%p spinlock@%p LOCK\n", + tcb->name, tcb, spinlock); +#else + syslog(LOG_INFO, "TCB@%p spinlock@%p LOCK\n", + tcb, spinlock); +#endif +#endif +} + +void sched_note_spinlocked(FAR struct tcb_s *tcb, + FAR volatile void *spinlock) +{ +#ifdef CONFIG_SMP +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p spinlock@%p LOCKED\n", + tcb->cpu, tcb->name, tcb, spinlock); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p spinlock@%p LOCKED\n", + tcb->cpu, tcb, spinlock); +#endif +#else +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "Task %s TCB@%p spinlock@%p LOCKED\n", + tcb->name, tcb, spinlock); +#else + syslog(LOG_INFO, "TCB@%p spinlock@%p LOCKED\n", + tcb, spinlock); +#endif +#endif +} + +void sched_note_spinunlock(FAR struct tcb_s *tcb, + FAR volatile void *spinlock) +{ +#ifdef CONFIG_SMP +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p spinlock@%p UNLOCK\n", + tcb->cpu, tcb->name, tcb, spinlock); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p spinlock@%p UNLOCK\n", + tcb->cpu, tcb, spinlock); +#endif +#else +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "Task %s TCB@%p spinlock@%p UNLOCK\n", + tcb->name, tcb, spinlock); +#else + syslog(LOG_INFO, "TCB@%p spinlock@%p UNLOCK\n", + tcb, spinlock); +#endif +#endif +} + +void sched_note_spinabort(FAR struct tcb_s *tcb, + FAR volatile void *spinlock) +{ +#ifdef CONFIG_SMP +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "CPU%d: Task %s TCB@%p spinlock@%p ABORT\n", + tcb->cpu, tcb->name, tcb, spinlock); +#else + syslog(LOG_INFO, "CPU%d: TCB@%p spinlock@%p ABORT\n", + tcb->cpu, tcb, spinlock); +#endif +#else +#if CONFIG_TASK_NAME_SIZE > 0 + syslog(LOG_INFO, "Task %s TCB@%p spinlock@%p ABORT\n", + tcb->name, tcb, spinlock); +#else + syslog(LOG_INFO, "TCB@%p spinlock@%p ABORT\n", + tcb, spinlock); +#endif +#endif +} +#endif + +#ifdef CONFIG_SCHED_INSTRUMENTATION_SYSCALL +void sched_note_syscall_enter(int nr, int argc, ...) +{ + char buf[128]; + FAR char *p = buf; + va_list ap; + + va_start(ap, argc); + while (argc-- > 0) + { + if (argc) + { + p += sprintf(p, "%#"PRIxPTR", ", va_arg(ap, uintptr_t)); + } + else + { + p += sprintf(p, "%#"PRIxPTR, va_arg(ap, uintptr_t)); + } + } + + va_end(ap); + syslog(LOG_INFO, "%s@%d ENTER %s\n", g_funcnames[nr], nr, buf); +} + +void sched_note_syscall_leave(int nr, uintptr_t result) +{ + syslog(LOG_INFO, "%s@%d LEAVE %"PRIdPTR"\n", g_funcnames[nr], nr, result); +} +#endif + +#ifdef CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER +void sched_note_irqhandler(int irq, FAR void *handler, bool enter) +{ + syslog(LOG_INFO, "IRQ%d handler@%p %s\n", + irq, handler, enter ? "ENTER" : "LEAVE"); +} +#endif diff --git a/drivers/pipes/pipe.c b/drivers/pipes/pipe.c index 366f345c5c8..2032d32f027 100644 --- a/drivers/pipes/pipe.c +++ b/drivers/pipes/pipe.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 5c3cf0da778..38a19941805 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -334,56 +334,6 @@ config SMPS_HAVE_EFFICIENCY endif -config DRIVERS_MOTOR - bool "Motor driver" - default n - ---help--- - Enables building of a motor upper half driver. - -if DRIVERS_MOTOR - -config MOTOR_HAVE_POSITION - bool "Have position control" - default n - -config MOTOR_HAVE_DIRECTION - bool "Have direction control" - default n - -config MOTOR_HAVE_SPEED - bool "Have speed control" - default n - -config MOTOR_HAVE_TORQUE - bool "Have torque control (rotary motors)" - default n - -config MOTOR_HAVE_FORCE - bool "Have force control (linear motors)" - default n - -config MOTOR_HAVE_ACCELERATION - bool "Have acceleration control" - default n - -config MOTOR_HAVE_DECELERATION - bool "Have deceleration control" - default n - -config MOTOR_HAVE_INPUT_VOLTAGE - bool "Have input voltage protection" - default n - -config MOTOR_HAVE_INPUT_CURRENT - bool "Have input current protection" - default n - -config MOTOR_HAVE_INPUT_POWER - bool "Have input power protection" - default n - -endif - menuconfig POWER bool "Power Management Support" default n diff --git a/drivers/power/Make.defs b/drivers/power/Make.defs index 48f6aaa147b..ed7698ff491 100644 --- a/drivers/power/Make.defs +++ b/drivers/power/Make.defs @@ -71,18 +71,6 @@ POWER_CFLAGS := ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)power} endif -# Add motor driver - -ifeq ($(CONFIG_DRIVERS_MOTOR),y) - -CSRCS += motor.c - -POWER_DEPPATH := --dep-path power -POWER_VPATH := :power -POWER_CFLAGS := ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)power} - -endif - # Add battery charger drivers ifeq ($(CONFIG_BATTERY_CHARGER),y) diff --git a/drivers/power/bq2429x.c b/drivers/power/bq2429x.c index 5de34e2af2b..34754b5a3ea 100644 --- a/drivers/power/bq2429x.c +++ b/drivers/power/bq2429x.c @@ -72,6 +72,7 @@ #include #include #include +#include #include #include diff --git a/drivers/power/pm_unregister.c b/drivers/power/pm_unregister.c index d5cb7d5c3f7..bc9d0a61ed3 100644 --- a/drivers/power/pm_unregister.c +++ b/drivers/power/pm_unregister.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/power/pm_unregister.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/power/powerled.c b/drivers/power/powerled.c index 9e50b222226..2591c61f9ca 100644 --- a/drivers/power/powerled.c +++ b/drivers/power/powerled.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/drivers/power/smps.c b/drivers/power/smps.c index b192c110d2d..65bf0c10d7a 100644 --- a/drivers/power/smps.c +++ b/drivers/power/smps.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/drivers/ramdisk.c b/drivers/ramdisk.c index 40df070d437..317cdce28de 100644 --- a/drivers/ramdisk.c +++ b/drivers/ramdisk.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include diff --git a/drivers/rc/lirc_dev.c b/drivers/rc/lirc_dev.c index a7ce5cf91d0..da36f2b8f42 100644 --- a/drivers/rc/lirc_dev.c +++ b/drivers/rc/lirc_dev.c @@ -25,6 +25,8 @@ #include #include +#include +#include #include #include #include diff --git a/drivers/rf/dat-31r5-sp.c b/drivers/rf/dat-31r5-sp.c index b2b147ef8e5..f68e32e24a9 100644 --- a/drivers/rf/dat-31r5-sp.c +++ b/drivers/rf/dat-31r5-sp.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/rptun/rptun.c b/drivers/rptun/rptun.c index 9c468d5ed81..14a115ba0d4 100644 --- a/drivers/rptun/rptun.c +++ b/drivers/rptun/rptun.c @@ -93,14 +93,17 @@ static FAR struct remoteproc *rptun_init(FAR struct remoteproc *rproc, FAR struct remoteproc_ops *ops, FAR void *arg); static void rptun_remove(FAR struct remoteproc *rproc); -static int rptun_mmap(FAR struct remoteproc *rproc, - FAR metal_phys_addr_t *pa, FAR metal_phys_addr_t *da, - FAR void **va, size_t size, unsigned int attribute, - FAR struct metal_io_region **io_); static int rptun_config(struct remoteproc *rproc, void *data); static int rptun_start(FAR struct remoteproc *rproc); static int rptun_stop(FAR struct remoteproc *rproc); static int rptun_notify(FAR struct remoteproc *rproc, uint32_t id); +static FAR struct remoteproc_mem * +rptun_get_mem(FAR struct remoteproc *rproc, + FAR const char *name, + metal_phys_addr_t pa, + metal_phys_addr_t da, + FAR void *va, size_t size, + FAR struct remoteproc_mem *buf); static void rptun_ns_bind(FAR struct rpmsg_device *rdev, FAR const char *name, uint32_t dest); @@ -130,13 +133,13 @@ static metal_phys_addr_t rptun_da_to_pa(FAR struct rptun_dev_s *dev, static struct remoteproc_ops g_rptun_ops = { - .init = rptun_init, - .remove = rptun_remove, - .mmap = rptun_mmap, - .config = rptun_config, - .start = rptun_start, - .stop = rptun_stop, - .notify = rptun_notify, + .init = rptun_init, + .remove = rptun_remove, + .config = rptun_config, + .start = rptun_start, + .stop = rptun_stop, + .notify = rptun_notify, + .get_mem = rptun_get_mem, }; static const struct file_operations g_rptun_devops = @@ -205,55 +208,6 @@ static void rptun_remove(FAR struct remoteproc *rproc) rproc->priv = NULL; } -static int rptun_mmap(FAR struct remoteproc *rproc, - FAR metal_phys_addr_t *pa, FAR metal_phys_addr_t *da, - FAR void **va, size_t size, unsigned int attribute, - FAR struct metal_io_region **io_) -{ - FAR struct rptun_priv_s *priv = rproc->priv; - FAR struct metal_io_region *io = metal_io_get_region(); - - if (*pa != METAL_BAD_PHYS) - { - *da = rptun_pa_to_da(priv->dev, *pa); - *va = metal_io_phys_to_virt(io, *pa); - if (!*va) - { - return -RPROC_EINVAL; - } - } - else if (*da != METAL_BAD_PHYS) - { - *pa = rptun_da_to_pa(priv->dev, *da); - *va = metal_io_phys_to_virt(io, *pa); - if (!*va) - { - return -RPROC_EINVAL; - } - } - else if (*va) - { - *pa = metal_io_virt_to_phys(io, *va); - if (*pa == METAL_BAD_PHYS) - { - return -RPROC_EINVAL; - } - - *da = rptun_pa_to_da(priv->dev, *pa); - } - else - { - return -RPROC_EINVAL; - } - - if (io_) - { - *io_ = io; - } - - return 0; -} - static int rptun_config(struct remoteproc *rproc, void *data) { struct rptun_priv_s *priv = rproc->priv; @@ -299,6 +253,45 @@ static int rptun_notify(FAR struct remoteproc *rproc, uint32_t id) return 0; } +static FAR struct remoteproc_mem * +rptun_get_mem(FAR struct remoteproc *rproc, + FAR const char *name, + metal_phys_addr_t pa, + metal_phys_addr_t da, + FAR void *va, size_t size, + FAR struct remoteproc_mem *buf) +{ + FAR struct rptun_priv_s *priv = rproc->priv; + + metal_list_init(&buf->node); + strcpy(buf->name, name ? name : ""); + buf->io = metal_io_get_region(); + buf->size = size; + + if (pa != METAL_BAD_PHYS) + { + buf->pa = pa; + buf->da = rptun_pa_to_da(priv->dev, pa); + } + else if (da != METAL_BAD_PHYS) + { + buf->pa = rptun_da_to_pa(priv->dev, da); + buf->da = da; + } + else + { + buf->pa = metal_io_virt_to_phys(buf->io, va); + buf->da = rptun_pa_to_da(priv->dev, buf->pa); + } + + if (buf->pa == METAL_BAD_PHYS || buf->da == METAL_BAD_PHYS) + { + return NULL; + } + + return buf; +} + static void *rptun_get_priv_by_rdev(FAR struct rpmsg_device *rdev) { struct rpmsg_virtio_device *rvdev; @@ -418,6 +411,9 @@ static int rptun_dev_start(FAR struct remoteproc *rproc) FAR void *va0; FAR void *va1; FAR void *shbuf; + FAR struct metal_io_region *io; + metal_phys_addr_t pa0; + metal_phys_addr_t pa1; align0 = B2C(rsc->rpmsg_vring0.align); align1 = B2C(rsc->rpmsg_vring1.align); @@ -426,13 +422,17 @@ static int rptun_dev_start(FAR struct remoteproc *rproc) v0sz = ALIGN_UP(vring_size(rsc->rpmsg_vring0.num, align0), align0); v1sz = ALIGN_UP(vring_size(rsc->rpmsg_vring1.num, align1), align1); - va0 = (char *)rsc + tbsz; - va1 = (char *)rsc + tbsz + v0sz; + va0 = (FAR char *)rsc + tbsz; + va1 = (FAR char *)rsc + tbsz + v0sz; + + io = metal_io_get_region(); + pa0 = metal_io_virt_to_phys(io, va0); + pa1 = metal_io_virt_to_phys(io, va1); da0 = da1 = METAL_BAD_PHYS; - remoteproc_mmap(rproc, NULL, &da0, &va0, v0sz, 0, NULL); - remoteproc_mmap(rproc, NULL, &da1, &va1, v1sz, 0, NULL); + remoteproc_mmap(rproc, &pa0, &da0, v0sz, 0, NULL); + remoteproc_mmap(rproc, &pa1, &da1, v1sz, 0, NULL); rsc->rpmsg_vring0.da = da0; rsc->rpmsg_vring1.da = da1; diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig index 79b344101c8..1f3e782e955 100644 --- a/drivers/sensors/Kconfig +++ b/drivers/sensors/Kconfig @@ -346,6 +346,7 @@ config SENSORS_L3GD20_BUFFER_SIZE The size of the circular buffer used. If the value equal to zero, indicates that the circular buffer is disabled. + config SENSOR_KXTJ9 bool "Kionix KXTJ9 Accelerometer support" default n diff --git a/drivers/sensors/Make.defs b/drivers/sensors/Make.defs index 71ccab1e2b8..2322f6b9e24 100644 --- a/drivers/sensors/Make.defs +++ b/drivers/sensors/Make.defs @@ -36,10 +36,6 @@ ifeq ($(CONFIG_SENSORS_HCSR04),y) CSRCS += hc_sr04.c endif -ifeq ($(CONFIG_SENSORS_FAKESENSOR),y) - CSRCS += fakesensor.c -endif - ifeq ($(CONFIG_SENSORS_ADXL345),y) CSRCS += adxl345_base.c endif diff --git a/drivers/sensors/adt7320.c b/drivers/sensors/adt7320.c index 2bcf15f1edc..33b94afe71b 100644 --- a/drivers/sensors/adt7320.c +++ b/drivers/sensors/adt7320.c @@ -44,6 +44,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/adxl345_base.c b/drivers/sensors/adxl345_base.c index cb71e5f4bb5..03ff01204e3 100644 --- a/drivers/sensors/adxl345_base.c +++ b/drivers/sensors/adxl345_base.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include diff --git a/drivers/sensors/adxl372.c b/drivers/sensors/adxl372.c index d3a17026088..96236fa5be4 100644 --- a/drivers/sensors/adxl372.c +++ b/drivers/sensors/adxl372.c @@ -27,6 +27,7 @@ #if defined(CONFIG_SPI) && defined(CONFIG_SENSORS_ADXL372) \ && defined(CONFIG_SPI_EXCHANGE) +#include #include #include #include diff --git a/drivers/sensors/aht10.c b/drivers/sensors/aht10.c index a55c1263407..66b11badd8e 100644 --- a/drivers/sensors/aht10.c +++ b/drivers/sensors/aht10.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/sensors/aht10.c - * Driver for the ASAIR AHT10 temperature and humidity sensors * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: kyChu + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -41,6 +25,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/apds9960.c b/drivers/sensors/apds9960.c index a6ec443877d..79f3cc47f4a 100644 --- a/drivers/sensors/apds9960.c +++ b/drivers/sensors/apds9960.c @@ -31,6 +31,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/as5048b.c b/drivers/sensors/as5048b.c index 85f81f3d638..15a31408c24 100644 --- a/drivers/sensors/as5048b.c +++ b/drivers/sensors/as5048b.c @@ -43,6 +43,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/as726x.c b/drivers/sensors/as726x.c index dea5c5733f6..38b794ec67c 100644 --- a/drivers/sensors/as726x.c +++ b/drivers/sensors/as726x.c @@ -42,6 +42,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/bh1750fvi.c b/drivers/sensors/bh1750fvi.c index cb6f10b5b9c..4e434d30ab6 100644 --- a/drivers/sensors/bh1750fvi.c +++ b/drivers/sensors/bh1750fvi.c @@ -26,6 +26,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/bmg160.c b/drivers/sensors/bmg160.c index 3dec3e35132..bb8abb2ac15 100644 --- a/drivers/sensors/bmg160.c +++ b/drivers/sensors/bmg160.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/bmi160.c b/drivers/sensors/bmi160.c index 66c3089d1ea..b340cadf21c 100644 --- a/drivers/sensors/bmi160.c +++ b/drivers/sensors/bmi160.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/ds18b20.c b/drivers/sensors/ds18b20.c index 8716a17eaea..40053d1fd96 100644 --- a/drivers/sensors/ds18b20.c +++ b/drivers/sensors/ds18b20.c @@ -25,6 +25,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/fakesensor.c b/drivers/sensors/fakesensor.c index 792b5301b95..f937a352df4 100644 --- a/drivers/sensors/fakesensor.c +++ b/drivers/sensors/fakesensor.c @@ -36,6 +36,7 @@ #include #include #include +#include /**************************************************************************** * Private Types @@ -50,7 +51,7 @@ struct fakesensor_s int raw_start; FAR const char *file_path; sem_t wakeup; - bool running; + volatile bool running; }; /**************************************************************************** diff --git a/drivers/sensors/fxos8700cq.c b/drivers/sensors/fxos8700cq.c index 34e2289396f..a7b39af89f3 100644 --- a/drivers/sensors/fxos8700cq.c +++ b/drivers/sensors/fxos8700cq.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/hc_sr04.c b/drivers/sensors/hc_sr04.c index 68a19291d7a..284856a4b59 100644 --- a/drivers/sensors/hc_sr04.c +++ b/drivers/sensors/hc_sr04.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include diff --git a/drivers/sensors/hdc1008.c b/drivers/sensors/hdc1008.c index 8023e47d2f1..674964d118b 100644 --- a/drivers/sensors/hdc1008.c +++ b/drivers/sensors/hdc1008.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -299,6 +300,7 @@ static int hdc1008_set_operational_mode(struct hdc1008_dev_s *priv, case HDC1008_MEAS_T_AND_RH: { reg |= HDC1008_CONFIGURATION_MODE; + break; } default: diff --git a/drivers/sensors/hts221.c b/drivers/sensors/hts221.c index e8031504557..b77d4febf4f 100644 --- a/drivers/sensors/hts221.c +++ b/drivers/sensors/hts221.c @@ -39,6 +39,7 @@ #include #include +#include #include #include #include diff --git a/drivers/sensors/hyt271.c b/drivers/sensors/hyt271.c index 91700887ee0..22033b2f69c 100644 --- a/drivers/sensors/hyt271.c +++ b/drivers/sensors/hyt271.c @@ -25,6 +25,7 @@ #include +#include #include #include #include @@ -92,7 +93,7 @@ struct hyt271_dev_s struct hyt271_sensor_s sensor[HYT271_SENSOR_MAX]; /* Sensor types */ FAR struct i2c_master_s *i2c; /* I2C interface */ FAR struct hyt271_bus_s *bus; /* Bus power interface */ - sem_t lock_measure_cylce; /* Locks measure cycle */ + sem_t lock_measure_cycle; /* Locks measure cycle */ uint32_t freq; /* I2C Frequency */ #ifdef CONFIG_SENSORS_HYT271_POLL unsigned int interval; /* Polling interval */ @@ -255,7 +256,7 @@ static int hyt271_df(FAR struct hyt271_dev_s *dev, /**************************************************************************** * Name: hyt271_mr * - * Description: Helper for sending a measurement cylce request. + * Description: Helper for sending a measurement cycle request. * * Parameter: * dev - Pointer to private driver instance @@ -273,10 +274,10 @@ static int hyt271_mr(FAR struct hyt271_dev_s *dev, /* We only must send the i2c address with write bit enabled here. This * isn't provided by the i2c api, so instead sending a null byte seems - * working fine. + * to work fine. */ - buffer = 0x00; + buffer = 0x00; /* Send address only with write bit enabled */ @@ -329,7 +330,7 @@ static int hyt271_cmd(FAR struct hyt271_dev_s *dev, * Name: hyt271_cmd_response * * Description: Helper for sending a command fetching the response after a - * neccessary timeout. + * necessary timeout. * Parameter: * dev - Pointer to private driver instance * config - I2C configuration @@ -411,12 +412,12 @@ static int hyt271_change_addr(FAR struct hyt271_dev_s *dev, uint8_t addr) return -EINVAL; } - /* Reset and subsequently operation must be mutual exclusive - * Prevents from beeing used by another open driver instance during this - * operations. + /* Reset and subsequent operations must be mutually exclusive. Prevents + * from being used by another open driver instance during this address + * change operation. */ - ret = nxsem_wait(&dev->lock_measure_cylce); + ret = nxsem_wait(&dev->lock_measure_cycle); if (ret < 0) { return ret; @@ -473,7 +474,7 @@ static int hyt271_change_addr(FAR struct hyt271_dev_s *dev, uint8_t addr) if ((buffer[2] & 0x7f) != dev->addr) { - snerr("wrong current I2C address responsed: 0x%x\n", buffer[2] & 0x7f); + snerr("wrong current I2C address response: 0x%x\n", buffer[2] & 0x7f); ret = -EIO; goto err_unlock; } @@ -499,7 +500,7 @@ static int hyt271_change_addr(FAR struct hyt271_dev_s *dev, uint8_t addr) if ((buffer[2] & 0x7f) != addr) { - snerr("wrong changed I2C address responsed: 0x%x\n", buffer[2] & 0x7f); + snerr("wrong changed I2C address response: 0x%x\n", buffer[2] & 0x7f); ret = -EIO; goto err_unlock; } @@ -517,11 +518,11 @@ static int hyt271_change_addr(FAR struct hyt271_dev_s *dev, uint8_t addr) dev->addr = addr; - nxsem_post(&dev->lock_measure_cylce); + nxsem_post(&dev->lock_measure_cycle); return OK; err_unlock: - nxsem_post(&dev->lock_measure_cylce); + nxsem_post(&dev->lock_measure_cycle); return ret; } @@ -529,7 +530,7 @@ err_unlock: * Name: hyt271_measure_read * * Description: - * Performs a measuremnt cylce and reads measured data. + * Performs a measurement cycle and reads measured data. * * Parameter: * dev - Pointer to private driver instance @@ -546,12 +547,12 @@ static int hyt271_measure_read(FAR struct hyt271_dev_s *dev, struct i2c_config_s config; uint8_t buffer[4]; - /* Measure request and read operation must be mutual exclusive - * Prevents from beeing used by another open driver instance during this + /* Measure request and read operation must be mutually exclusive. + * Prevents from being used by another open driver instance during this * read operation. */ - ret = nxsem_wait(&dev->lock_measure_cylce); + ret = nxsem_wait(&dev->lock_measure_cycle); if (ret < 0) { return ret; @@ -588,19 +589,19 @@ static int hyt271_measure_read(FAR struct hyt271_dev_s *dev, buffer[2] << 8 | buffer[3]; data->timestamp = hyt271_curtime(); - nxsem_post(&dev->lock_measure_cylce); + nxsem_post(&dev->lock_measure_cycle); return OK; err_unlock: - nxsem_post(&dev->lock_measure_cylce); + nxsem_post(&dev->lock_measure_cycle); return ret; } /**************************************************************************** * Name: hyt271_fetch * - * Description: Performs a measuremnt cylce and data read with data + * Description: Performs a measurement cycle and data read with data * conversion. * * Parameter: @@ -789,7 +790,7 @@ static int hyt271_thread(int argc, char** argv) if (!hsensor->enabled && !tsensor->enabled) { - /* Reset inital read identifier */ + /* Reset initial read identifier */ priv->initial_read = false; @@ -907,7 +908,7 @@ int hyt271_register(int devno, FAR struct i2c_master_s *i2c, uint8_t addr, priv->initial_read = false; #endif - nxsem_init(&priv->lock_measure_cylce, 0, 1); + nxsem_init(&priv->lock_measure_cycle, 0, 1); #ifdef CONFIG_SENSORS_HYT271_POLL nxsem_init(&priv->run, 0, 0); nxsem_set_protocol(&priv->run, SEM_PRIO_NONE); @@ -969,7 +970,7 @@ humi_err: temp_err: sensor_unregister(&priv->sensor[HYT271_SENSOR_TEMP].lower, devno); - nxsem_destroy(&priv->lock_measure_cylce); + nxsem_destroy(&priv->lock_measure_cycle); kmm_free(priv); return ret; } diff --git a/drivers/sensors/ina219.c b/drivers/sensors/ina219.c index 2e17454029c..cc0cd485166 100644 --- a/drivers/sensors/ina219.c +++ b/drivers/sensors/ina219.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/ina226.c b/drivers/sensors/ina226.c index e44bfa7e87d..ea40cf4a477 100644 --- a/drivers/sensors/ina226.c +++ b/drivers/sensors/ina226.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/ina3221.c b/drivers/sensors/ina3221.c index 3dc0eccb766..47ab2846b27 100644 --- a/drivers/sensors/ina3221.c +++ b/drivers/sensors/ina3221.c @@ -47,6 +47,7 @@ #include #include +#include #include #include #include diff --git a/drivers/sensors/kxtj9.c b/drivers/sensors/kxtj9.c index c35693d768c..90d4c372e4d 100644 --- a/drivers/sensors/kxtj9.c +++ b/drivers/sensors/kxtj9.c @@ -44,6 +44,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/l3gd20.c b/drivers/sensors/l3gd20.c index 99679ce239a..99a8fa8a884 100644 --- a/drivers/sensors/l3gd20.c +++ b/drivers/sensors/l3gd20.c @@ -25,6 +25,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/lis3dh.c b/drivers/sensors/lis3dh.c index 7a8cb92dcc3..321f58215ae 100644 --- a/drivers/sensors/lis3dh.c +++ b/drivers/sensors/lis3dh.c @@ -39,6 +39,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/lis3dsh.c b/drivers/sensors/lis3dsh.c index cb7759c0a1a..9e6e10ea540 100644 --- a/drivers/sensors/lis3dsh.c +++ b/drivers/sensors/lis3dsh.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/lis3mdl.c b/drivers/sensors/lis3mdl.c index 5c34a5bab9d..2e526e1df08 100644 --- a/drivers/sensors/lis3mdl.c +++ b/drivers/sensors/lis3mdl.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/lm75.c b/drivers/sensors/lm75.c index e916ae348a4..7efb17a0b49 100644 --- a/drivers/sensors/lm75.c +++ b/drivers/sensors/lm75.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/drivers/sensors/lm92.c b/drivers/sensors/lm92.c index af6848c6a4e..0d7d8775f10 100644 --- a/drivers/sensors/lm92.c +++ b/drivers/sensors/lm92.c @@ -44,6 +44,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/lps25h.c b/drivers/sensors/lps25h.c index 7efc611a225..2517269252a 100644 --- a/drivers/sensors/lps25h.c +++ b/drivers/sensors/lps25h.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/sensors/lsm303agr.c b/drivers/sensors/lsm303agr.c index 5a0bb3319f1..0566c1d8dd6 100644 --- a/drivers/sensors/lsm303agr.c +++ b/drivers/sensors/lsm303agr.c @@ -48,6 +48,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/lsm330_spi.c b/drivers/sensors/lsm330_spi.c index 13c08efec00..61ecd01e05f 100644 --- a/drivers/sensors/lsm330_spi.c +++ b/drivers/sensors/lsm330_spi.c @@ -27,6 +27,7 @@ #if defined(CONFIG_SPI) && defined(CONFIG_SENSORS_LSM330SPI) \ && defined(CONFIG_SPI_EXCHANGE) +#include #include #include #include diff --git a/drivers/sensors/lsm6dsl.c b/drivers/sensors/lsm6dsl.c index 238806e323f..a834971340b 100644 --- a/drivers/sensors/lsm6dsl.c +++ b/drivers/sensors/lsm6dsl.c @@ -48,6 +48,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/lsm9ds1.c b/drivers/sensors/lsm9ds1.c index 48a8f3d8f7c..3f2ca277ef4 100644 --- a/drivers/sensors/lsm9ds1.c +++ b/drivers/sensors/lsm9ds1.c @@ -42,6 +42,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/ltc4151.c b/drivers/sensors/ltc4151.c index 2addbef568d..df64c3af140 100644 --- a/drivers/sensors/ltc4151.c +++ b/drivers/sensors/ltc4151.c @@ -42,6 +42,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/max31855.c b/drivers/sensors/max31855.c index cebaf12b54a..e6e39d5dc64 100644 --- a/drivers/sensors/max31855.c +++ b/drivers/sensors/max31855.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/drivers/sensors/max44009.c b/drivers/sensors/max44009.c index 64dfa1020cd..67cde887d47 100644 --- a/drivers/sensors/max44009.c +++ b/drivers/sensors/max44009.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include diff --git a/drivers/sensors/max6675.c b/drivers/sensors/max6675.c index 97ad66ceb6d..fc1986f9dae 100644 --- a/drivers/sensors/max6675.c +++ b/drivers/sensors/max6675.c @@ -33,6 +33,7 @@ #include #include +#include #include #include diff --git a/drivers/sensors/mb7040.c b/drivers/sensors/mb7040.c index a7688b29ba7..23202d95cf2 100644 --- a/drivers/sensors/mb7040.c +++ b/drivers/sensors/mb7040.c @@ -43,6 +43,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/mcp9844.c b/drivers/sensors/mcp9844.c index 4d6175056d6..26502f0c138 100644 --- a/drivers/sensors/mcp9844.c +++ b/drivers/sensors/mcp9844.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/drivers/sensors/mlx90393.c b/drivers/sensors/mlx90393.c index 5b4ff51e430..97b166c9d75 100644 --- a/drivers/sensors/mlx90393.c +++ b/drivers/sensors/mlx90393.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/mlx90614.c b/drivers/sensors/mlx90614.c index 756624e990a..b34b4a9f296 100644 --- a/drivers/sensors/mlx90614.c +++ b/drivers/sensors/mlx90614.c @@ -38,6 +38,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/mpu60x0.c b/drivers/sensors/mpu60x0.c index 35d622fc86a..fb7f13aab60 100644 --- a/drivers/sensors/mpu60x0.c +++ b/drivers/sensors/mpu60x0.c @@ -77,7 +77,7 @@ /* Masks and shifts @v into bit field @m */ -#define TO_BITFIELD(m,v) ((v) & MASK(m ##__WIDTH) << (m ##__SHIFT)) +#define TO_BITFIELD(m,v) (((v) & MASK(m ##__WIDTH)) << (m ##__SHIFT)) /* Un-masks and un-shifts bit field @m from @v */ @@ -693,6 +693,7 @@ static void inline mpu_unlock(FAR struct mpu_dev_s *dev) static int mpu_reset(FAR struct mpu_dev_s *dev) { + int ret; #ifdef CONFIG_MPU60X0_SPI if (dev->config.spi == NULL) { @@ -709,7 +710,12 @@ static int mpu_reset(FAR struct mpu_dev_s *dev) /* Awaken chip, issue hardware reset */ - __mpu_write_pwr_mgmt_1(dev, PWR_MGMT_1__DEVICE_RESET); + ret = __mpu_write_pwr_mgmt_1(dev, PWR_MGMT_1__DEVICE_RESET); + if (ret != OK) + { + snerr("Could not find mpu60x0!\n"); + return ret; + } /* Wait for reset cycle to finish (note: per the datasheet, we don't need * to hold NSS for this) @@ -994,6 +1000,19 @@ int mpu60x0_register(FAR const char *path, FAR struct mpu_config_s *config) priv->config = *config; + /* Reset the chip, to give it an initial configuration. */ + + ret = mpu_reset(priv); + if (ret < 0) + { + snerr("ERROR: Failed to configure mpu60x0: %d\n", ret); + + nxmutex_destroy(&priv->lock); + + kmm_free(priv); + return ret; + } + /* Register the device node. */ ret = register_driver(path, &g_mpu_fops, 0666, priv); @@ -1007,7 +1026,5 @@ int mpu60x0_register(FAR const char *path, FAR struct mpu_config_s *config) return ret; } - /* Reset the chip, to give it an initial configuration. */ - - return mpu_reset(priv); + return OK; } diff --git a/drivers/sensors/ms58xx.c b/drivers/sensors/ms58xx.c index 87c05e919bb..fbc653343a9 100644 --- a/drivers/sensors/ms58xx.c +++ b/drivers/sensors/ms58xx.c @@ -44,6 +44,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/scd30.c b/drivers/sensors/scd30.c index dcde8c580a3..ab2fb4d24a5 100644 --- a/drivers/sensors/scd30.c +++ b/drivers/sensors/scd30.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/sensors/sensor.c b/drivers/sensors/sensor.c index f69cf3f83f4..95a4fcc441d 100644 --- a/drivers/sensors/sensor.c +++ b/drivers/sensors/sensor.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/sensors/sgp30.c b/drivers/sensors/sgp30.c index bed0ada114e..88199cd9352 100644 --- a/drivers/sensors/sgp30.c +++ b/drivers/sensors/sgp30.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/sensors/sht21.c b/drivers/sensors/sht21.c index e511293c99e..ddcd6b61443 100644 --- a/drivers/sensors/sht21.c +++ b/drivers/sensors/sht21.c @@ -41,6 +41,7 @@ #include #include +#include #include #include #include diff --git a/drivers/sensors/sht3x.c b/drivers/sensors/sht3x.c index 008dd918bbd..f616b4b45eb 100644 --- a/drivers/sensors/sht3x.c +++ b/drivers/sensors/sht3x.c @@ -42,6 +42,7 @@ #include #include +#include #include #include #include diff --git a/drivers/sensors/sps30.c b/drivers/sensors/sps30.c index e42bc141ca7..2af4f89c5f5 100644 --- a/drivers/sensors/sps30.c +++ b/drivers/sensors/sps30.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/sensors/t67xx.c b/drivers/sensors/t67xx.c index 201cdb3d9e9..6c73da018a5 100644 --- a/drivers/sensors/t67xx.c +++ b/drivers/sensors/t67xx.c @@ -40,6 +40,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/veml6070.c b/drivers/sensors/veml6070.c index cf6902625a7..8b992708683 100644 --- a/drivers/sensors/veml6070.c +++ b/drivers/sensors/veml6070.c @@ -26,6 +26,7 @@ #include +#include #include #include #include diff --git a/drivers/sensors/wtgahrs2.c b/drivers/sensors/wtgahrs2.c index 7cad78ceb7d..42d28d99617 100644 --- a/drivers/sensors/wtgahrs2.c +++ b/drivers/sensors/wtgahrs2.c @@ -34,6 +34,7 @@ #include #include #include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/drivers/sensors/xen1210.c b/drivers/sensors/xen1210.c index b979e123542..3e3943bbe66 100644 --- a/drivers/sensors/xen1210.c +++ b/drivers/sensors/xen1210.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 58247c33caf..8dce5dabcc8 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -190,8 +190,6 @@ config TTY_FORCE_PANIC_CHAR config TTY_SIGINT bool "Support SIGINT" default n - select SIG_DEFAULT - select SIG_SIGKILL_ACTION depends on SERIAL_TERMIOS ---help--- Whether support Ctrl-c/x event. Enabled automatically for console @@ -236,8 +234,6 @@ config TTY_SIGINT_CHAR config TTY_SIGTSTP bool "Support SIGTSTP" default n - select SIG_DEFAULT - select CONFIG_SIG_SIGSTOP_ACTION depends on SERIAL_TERMIOS ---help--- Whether support Ctrl-z event. Enabled automatically for console diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 9f101e0459f..26792547a99 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -166,24 +167,15 @@ static void uart_pollnotify(FAR uart_dev_t *dev, pollevent_t eventset) #endif if (fds->revents != 0) { - irqstate_t flags; int semcount; finfo("Report events: %02x\n", fds->revents); - /* Limit the number of times that the semaphore is posted. - * The critical section is needed to make the following - * operation atomic. - */ - - flags = enter_critical_section(); nxsem_get_value(fds->sem, &semcount); if (semcount < 1) { nxsem_post(fds->sem); } - - leave_critical_section(flags); } } } @@ -199,10 +191,6 @@ static int uart_putxmitchar(FAR uart_dev_t *dev, int ch, bool oktoblock) int nexthead; int ret; -#ifdef CONFIG_SMP - irqstate_t flags2 = enter_critical_section(); -#endif - /* Increment to see what the next head pointer will be. * We need to use the "next" head pointer to determine when the circular * buffer would overrun @@ -226,8 +214,7 @@ static int uart_putxmitchar(FAR uart_dev_t *dev, int ch, bool oktoblock) dev->xmit.buffer[dev->xmit.head] = ch; dev->xmit.head = nexthead; - ret = OK; - goto err_out; + return OK; } /* The TX buffer is full. Should be block, waiting for the hardware @@ -301,8 +288,7 @@ static int uart_putxmitchar(FAR uart_dev_t *dev, int ch, bool oktoblock) if (dev->disconnected) { - ret = -ENOTCONN; - goto err_out; + return -ENOTCONN; } #endif @@ -314,8 +300,7 @@ static int uart_putxmitchar(FAR uart_dev_t *dev, int ch, bool oktoblock) * become non-full will abort the transfer. */ - ret = -EINTR; - goto err_out; + return -EINTR; } } @@ -325,8 +310,7 @@ static int uart_putxmitchar(FAR uart_dev_t *dev, int ch, bool oktoblock) else { - ret = -EAGAIN; - goto err_out; + return -EAGAIN; } } @@ -334,15 +318,7 @@ static int uart_putxmitchar(FAR uart_dev_t *dev, int ch, bool oktoblock) * unreachable. */ - ret = OK; - -err_out: - -#ifdef CONFIG_SMP - leave_critical_section(flags2); -#endif - - return ret; + return OK; } /**************************************************************************** @@ -900,17 +876,13 @@ static ssize_t uart_read(FAR struct file *filep, else { -#ifdef CONFIG_SERIAL_RXDMA - /* Disable all interrupts and test again... - * uart_disablerxint() is insufficient for the check in DMA mode. - */ + /* Disable all interrupts and test again... */ flags = enter_critical_section(); -#else + /* Disable Rx interrupts and test again... */ uart_disablerxint(dev); -#endif /* If the Rx ring buffer still empty? Bytes may have been added * between the last time that we checked and when we disabled @@ -927,14 +899,12 @@ static ssize_t uart_read(FAR struct file *filep, /* Notify DMA that there is free space in the RX buffer */ uart_dmarxfree(dev); -#else +#endif /* Wait with the RX interrupt re-enabled. All interrupts are * disabled briefly to assure that the following operations * are atomic. */ - flags = enter_critical_section(); - /* Re-enable UART Rx interrupts */ uart_enablerxint(dev); @@ -952,7 +922,6 @@ static ssize_t uart_read(FAR struct file *filep, leave_critical_section(flags); continue; } -#endif #ifdef CONFIG_SERIAL_REMOVABLE /* Check again if the removable device is still connected @@ -1020,11 +989,9 @@ static ssize_t uart_read(FAR struct file *filep, * the loop. */ -#ifdef CONFIG_SERIAL_RXDMA leave_critical_section(flags); -#else + uart_enablerxint(dev); -#endif } } } @@ -1037,11 +1004,9 @@ static ssize_t uart_read(FAR struct file *filep, leave_critical_section(flags); #endif -#ifndef CONFIG_SERIAL_RXDMA /* RX interrupt could be disabled by RX buffer overflow. Enable it now. */ uart_enablerxint(dev); -#endif #ifdef CONFIG_SERIAL_IFLOWCONTROL #ifdef CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS @@ -1420,7 +1385,6 @@ static int uart_ioctl(FAR struct file *filep, int cmd, unsigned long arg) else { dev->pid = (pid_t)arg; - DEBUGASSERT((unsigned long)(dev->pid) == arg); ret = 0; } } @@ -1542,8 +1506,8 @@ static int uart_poll(FAR struct file *filep, if (i >= CONFIG_SERIAL_NPOLLWAITERS) { - fds->priv = NULL; - ret = -EBUSY; + fds->priv = NULL; + ret = -EBUSY; goto errout; } @@ -1609,15 +1573,15 @@ static int uart_poll(FAR struct file *filep, #ifdef CONFIG_DEBUG_FEATURES if (!slot) { - ret = -EIO; + ret = -EIO; goto errout; } #endif /* Remove all memory of the poll setup */ - *slot = NULL; - fds->priv = NULL; + *slot = NULL; + fds->priv = NULL; } errout: diff --git a/drivers/serial/serial_dma.c b/drivers/serial/serial_dma.c index 1786ade04cc..b328c5d9875 100644 --- a/drivers/serial/serial_dma.c +++ b/drivers/serial/serial_dma.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/serial/serial_dma.c * - * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. - * Author: Max Neklyudov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c index 1fdd4b3c465..73c7c9a4995 100644 --- a/drivers/serial/uart_16550.c +++ b/drivers/serial/uart_16550.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 50210bf4406..4743edec5ba 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -26,21 +26,81 @@ menuconfig SPI if SPI config SPI_SLAVE - bool "SPI slave" + bool "SPI Slave" default n ---help--- - Enable support for SPI slave features + Enable support for SPI Slave features if SPI_SLAVE +config SPI_SLAVE_DRIVER + bool "SPI Slave character driver" + default n + ---help--- + Built-in support for a character driver at /dev/spislv[N] that may be + used to perform SPI bus transfers from applications. + The intent of this driver is to support SPI Slave testing. + +if SPI_SLAVE_DRIVER + +config SPI_SLAVE_DRIVER_MODE + int "SPI Slave character driver default mode" + default 0 + ---help--- + Default SPI Slave character driver mode, where: + 0 = CPOL=0, CPHA=0 + 1 = CPOL=0, CPHA=1 + 2 = CPOL=1, CPHA=0 + 3 = CPOL=1, CPHA=1 + +config SPI_SLAVE_DRIVER_WIDTH + int "SPI Slave character driver default bit width" + default 8 + ---help--- + Number of bits per SPI Slave transfer (default 8). + +config SPI_SLAVE_DRIVER_BUFFER_SIZE + int "SPI Slave character driver TX and RX buffer sizes" + default 128 + ---help--- + Size of the internal TX and RX buffers of the SPI Slave + character driver. + +config SPI_SLAVE_DRIVER_COLORIZE_TX_BUFFER + bool "SPI Slave character driver colorize TX buffer" + default n + ---help--- + Initialize entries of the TX buffer with a given pattern. + If the SPI Slave controller performs a call to "getdata" API during + the "bind" operation, the colorized buffer may be sent as part of the + first TX transfer of the SPI Slave controller. + This feature might be useful for a quick communication test between + Master and Slave. + +config SPI_SLAVE_DRIVER_COLORIZE_PATTERN + hex "SPI Slave character driver colorize pattern" + default 0xa5 + depends on SPI_SLAVE_DRIVER_COLORIZE_TX_BUFFER + ---help--- + Pattern to be used as the coloration of the TX buffer. + +config SPI_SLAVE_DRIVER_COLORIZE_NUM_BYTES + int "SPI Slave character driver colorize number of bytes" + default 4 + depends on SPI_SLAVE_DRIVER_COLORIZE_TX_BUFFER + ---help--- + Number of bytes of the TX buffer to be colorized. + +endif # SPI_SLAVE_DRIVER + config SPI_SLAVE_DMA - bool "SPI slave DMA" + bool "SPI Slave DMA" default n depends on ARCH_DMA && EXPERIMENTAL ---help--- Enable support for DMA data transfers (not yet implemented). -endif +endif # SPI_SLAVE config SPI_EXCHANGE bool "SPI exchange" diff --git a/drivers/spi/Make.defs b/drivers/spi/Make.defs index ca1527a7fb4..e95d9f75c26 100644 --- a/drivers/spi/Make.defs +++ b/drivers/spi/Make.defs @@ -29,6 +29,10 @@ ifeq ($(CONFIG_SPI_EXCHANGE),y) endif endif +ifeq ($(CONFIG_SPI_SLAVE_DRIVER),y) + CSRCS += spi_slave_driver.c +endif + # Include the selected SPI drivers ifeq ($(CONFIG_SPI_BITBANG),y) diff --git a/drivers/spi/spi_driver.c b/drivers/spi/spi_driver.c index da371f9f388..f2b2dff8ffa 100644 --- a/drivers/spi/spi_driver.c +++ b/drivers/spi/spi_driver.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/spi/spi_slave_driver.c b/drivers/spi/spi_slave_driver.c new file mode 100644 index 00000000000..6f9ae1e2054 --- /dev/null +++ b/drivers/spi/spi_slave_driver.c @@ -0,0 +1,632 @@ +/**************************************************************************** + * drivers/spi/spi_slave_driver.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_SPI_SLAVE_DRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DEVNAME_FMT "/dev/spislv%d" +#define DEVNAME_FMTLEN (11 + 3 + 1) + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#define WORDS2BYTES(_wn) ((_wn) * (CONFIG_SPI_SLAVE_DRIVER_WIDTH / 8)) +#define BYTES2WORDS(_bn) ((_bn) / (CONFIG_SPI_SLAVE_DRIVER_WIDTH / 8)) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct spi_slave_driver_s +{ + /* Externally visible part of the SPI Slave device interface */ + + struct spi_slave_dev_s dev; + + /* Reference to SPI Slave controller interface */ + + struct spi_slave_ctrlr_s *ctrlr; + + /* Receive buffer */ + + uint8_t rx_buffer[CONFIG_SPI_SLAVE_DRIVER_BUFFER_SIZE]; + uint32_t rx_length; /* Location of next RX value */ + + /* Transmit buffer */ + + uint8_t tx_buffer[CONFIG_SPI_SLAVE_DRIVER_BUFFER_SIZE]; + uint32_t tx_length; /* Location of next TX value */ +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + sem_t exclsem; /* Mutual exclusion */ + int16_t crefs; /* Number of open references */ + bool unlinked; /* Indicates if the driver has been unlinked */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Character driver methods */ + +static int spi_slave_open(FAR struct file *filep); +static int spi_slave_close(FAR struct file *filep); +static ssize_t spi_slave_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t spi_slave_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen); +static int spi_slave_unlink(FAR struct inode *inode); + +/* SPI Slave driver methods */ + +static void spi_slave_select(FAR struct spi_slave_dev_s *sdev, + bool selected); +static void spi_slave_cmddata(FAR struct spi_slave_dev_s *sdev, + bool data); +static size_t spi_slave_getdata(FAR struct spi_slave_dev_s *sdev, + FAR const void **data); +static size_t spi_slave_receive(FAR struct spi_slave_dev_s *sdev, + FAR const void *data, size_t nwords); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_spislavefops = +{ +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + spi_slave_open, /* open */ + spi_slave_close, /* close */ +#else + NULL, /* open */ + NULL, /* close */ +#endif + spi_slave_read, /* read */ + spi_slave_write, /* write */ + NULL, /* seek */ + NULL, /* ioctl */ + NULL /* poll */ +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , spi_slave_unlink /* unlink */ +#endif +}; + +static const struct spi_slave_devops_s g_spisdev_ops = +{ + spi_slave_select, /* select */ + spi_slave_cmddata, /* cmddata */ + spi_slave_getdata, /* getdata */ + spi_slave_receive, /* receive */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_slave_open + * + * Description: + * This function is called whenever the SPI Slave device is opened. + * + * Input Parameters: + * filep - File structure instance + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int spi_slave_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct spi_slave_driver_s *priv; + int ret; + + DEBUGASSERT(filep != NULL); + DEBUGASSERT(filep->f_inode != NULL); + DEBUGASSERT(filep->f_inode->i_private != NULL); + + spiinfo("filep: %p\n", filep); + + /* Get our private data structure */ + + inode = filep->f_inode; + priv = (FAR struct spi_slave_driver_s *)inode->i_private; + + /* Get exclusive access to the SPI Slave driver state structure */ + + ret = nxsem_wait(&priv->exclsem); + if (ret < 0) + { + spierr("Failed to get exclusive access to the driver: %d\n", ret); + return ret; + } + + /* Increment the count of open references on the driver */ + + priv->crefs++; + DEBUGASSERT(priv->crefs > 0); + + nxsem_post(&priv->exclsem); + return OK; +} +#endif + +/**************************************************************************** + * Name: spi_slave_close + * + * Description: + * This routine is called when the SPI Slave device is closed. + * + * Input Parameters: + * filep - File structure instance + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int spi_slave_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct spi_slave_driver_s *priv; + int ret; + + DEBUGASSERT(filep != NULL); + DEBUGASSERT(filep->f_inode != NULL); + DEBUGASSERT(filep->f_inode->i_private != NULL); + + spiinfo("filep: %p\n", filep); + + /* Get our private data structure */ + + inode = filep->f_inode; + priv = (FAR struct spi_slave_driver_s *)inode->i_private; + + /* Get exclusive access to the SPI Slave driver state structure */ + + ret = nxsem_wait(&priv->exclsem); + if (ret < 0) + { + spierr("Failed to get exclusive access to the driver: %d\n", ret); + return ret; + } + + /* Decrement the count of open references on the driver */ + + DEBUGASSERT(priv->crefs > 0); + priv->crefs--; + + /* If the count has decremented to zero and the driver has been already + * unlinked, then dispose of the driver resources. + */ + + if (priv->crefs <= 0 && priv->unlinked) + { + nxsem_destroy(&priv->exclsem); + kmm_free(priv); + inode->i_private = NULL; + return OK; + } + + nxsem_post(&priv->exclsem); + return OK; +} +#endif + +/**************************************************************************** + * Name: spi_slave_read + * + * Description: + * This routine is called when the application requires to read the data + * received by the SPI Slave device. + * + * Input Parameters: + * filep - File structure instance + * buffer - User-provided to save the data + * buflen - The maximum size of the user-provided buffer + * + * Returned Value: + * The positive non-zero number of bytes read on success, 0 on if an + * end-of-file condition, or a negated errno value on any failure. + * + ****************************************************************************/ + +static ssize_t spi_slave_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct inode *inode; + FAR struct spi_slave_driver_s *priv; + size_t read_bytes; + size_t remaining_words; + + spiinfo("filep=%p buffer=%p buflen=%zu\n", filep, buffer, buflen); + + /* Get our private data structure */ + + inode = filep->f_inode; + priv = (FAR struct spi_slave_driver_s *)inode->i_private; + + if (buffer == NULL) + { + spierr("ERROR: Buffer is NULL\n"); + return -ENOBUFS; + } + + remaining_words = SPIS_CTRLR_QPOLL(priv->ctrlr); + if (remaining_words == 0) + { + spiinfo("All words retrieved!\n"); + } + else + { + spiinfo("%zu words left in the buffer\n", remaining_words); + } + + read_bytes = MIN(buflen, priv->rx_length); + + memcpy(buffer, priv->rx_buffer, read_bytes); + + return (ssize_t)read_bytes; +} + +/**************************************************************************** + * Name: spi_slave_write + * + * Description: + * This routine is called when the application needs to enqueue data to be + * transferred at the next leading clock edge of the SPI Slave controller. + * + * Input Parameters: + * filep - Instance of struct file to use with the write + * buffer - Data to write + * buflen - Length of data to write in bytes + * + * Returned Value: + * On success, the number of bytes written are returned (zero indicates + * nothing was written). On any failure, a negated errno value is returned. + * + ****************************************************************************/ + +static ssize_t spi_slave_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen) +{ + FAR struct inode *inode; + FAR struct spi_slave_driver_s *priv; + size_t num_words; + size_t enqueued_bytes; + + spiinfo("filep=%p buffer=%p buflen=%zu\n", filep, buffer, buflen); + + /* Get our private data structure */ + + inode = filep->f_inode; + priv = (FAR struct spi_slave_driver_s *)inode->i_private; + + memcpy(priv->tx_buffer, buffer, buflen); + priv->tx_length = buflen; + num_words = BYTES2WORDS(priv->tx_length); + + enqueued_bytes = WORDS2BYTES(SPIS_CTRLR_ENQUEUE(priv->ctrlr, + priv->tx_buffer, + num_words)); + + spiinfo("%zu bytes enqueued\n", enqueued_bytes); + + return (ssize_t)enqueued_bytes; +} + +/**************************************************************************** + * Name: spi_slave_unlink + * + * Description: + * This routine is called when the SPI Slave device is unlinked. + * + * Input Parameters: + * inode - The inode associated with the SPI Slave device + * + * Returned Value: + * Zero is returned on success; a negated value is returned on any failure. + * + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int spi_slave_unlink(FAR struct inode *inode) +{ + FAR struct spi_slave_driver_s *priv; + int ret; + + DEBUGASSERT(inode != NULL); + DEBUGASSERT(inode->i_private != NULL); + + /* Get our private data structure */ + + priv = (FAR struct spi_slave_driver_s *)inode->i_private; + + /* Get exclusive access to the SPI Slave driver state structure */ + + ret = nxsem_wait(&priv->exclsem); + if (ret < 0) + { + spierr("Failed to get exclusive access to the driver: %d\n", ret); + return ret; + } + + /* Are there open references to the driver data structure? */ + + if (priv->crefs <= 0) + { + nxsem_destroy(&priv->exclsem); + kmm_free(priv); + inode->i_private = NULL; + return OK; + } + + /* No... just mark the driver as unlinked and free the resources when the + * last client closes their reference to the driver. + */ + + priv->unlinked = true; + nxsem_post(&priv->exclsem); + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_slave_select + * + * Description: + * This is a SPI device callback that is used when the SPI controller + * driver detects any change in the chip select pin. + * + * Input Parameters: + * dev - SPI Slave device interface instance + * selected - Indicates whether the chip select is in active state + * + * Returned Value: + * None. + * + * Assumptions: + * May be called from an interrupt handler. Processing should be as + * brief as possible. + * + ****************************************************************************/ + +static void spi_slave_select(FAR struct spi_slave_dev_s *dev, bool selected) +{ + spiinfo("sdev: %p CS: %s\n", dev, selected ? "select" : "free"); +} + +/**************************************************************************** + * Name: spi_slave_cmddata + * + * Description: + * This is a SPI device callback that is used when the SPI controller + * driver detects any change in the command/data condition. + * + * Normally only LCD devices distinguish command and data. For devices + * that do not distinguish between command and data, this method may be + * a stub. For devices that do make that distinction, they should treat + * all subsequent calls to getdata() or receive() appropriately for the + * current command/data selection. + * + * Input Parameters: + * dev - SPI Slave device interface instance + * data - True: Data is selected + * + * Returned Value: + * None. + * + * Assumptions: + * May be called from an interrupt handler. Processing should be as + * brief as possible. + * + ****************************************************************************/ + +static void spi_slave_cmddata(FAR struct spi_slave_dev_s *dev, bool data) +{ + spiinfo("sdev: %p CMD: %s\n", dev, data ? "data" : "command"); +} + +/**************************************************************************** + * Name: spi_slave_getdata + * + * Description: + * This is a SPI device callback that is used when the SPI controller + * requires data be shifted out at the next leading clock edge. This + * is necessary to "prime the pump" so that the SPI controller driver + * can keep pace with the shifted-in data. + * + * The SPI controller driver will prime for both command and data + * transfers as determined by a preceding call to the device cmddata() + * method. Normally only LCD devices distinguish command and data. + * + * Input Parameters: + * dev - SPI Slave device interface instance + * data - Pointer to the data buffer pointer to be shifed out. + * The device will set the data buffer pointer to the actual data + * + * Returned Value: + * The number of data units to be shifted out from the data buffer. + * + * Assumptions: + * May be called from an interrupt handler and the response is usually + * time-critical. + * + ****************************************************************************/ + +static size_t spi_slave_getdata(FAR struct spi_slave_dev_s *dev, + FAR const void **data) +{ + FAR struct spi_slave_driver_s *priv = (FAR struct spi_slave_driver_s *)dev; + + *data = priv->tx_buffer; + + return BYTES2WORDS(priv->tx_length); +} + +/**************************************************************************** + * Name: spi_slave_receive + * + * Description: + * This is a SPI device callback that is used when the SPI controller + * receives a new value shifted in. Notice that these values may be out of + * synchronization by several words. + * + * Input Parameters: + * dev - SPI Slave device interface instance + * data - Pointer to the new data that has been shifted in + * len - Length of the new data in units of nbits wide, + * nbits being the data width previously provided to the bind() + * method. + * + * Returned Value: + * Number of units accepted by the device. In other words, + * number of units to be removed from controller's receive queue. + * + * Assumptions: + * May be called from an interrupt handler and in time-critical + * circumstances. A good implementation might just add the newly + * received word to a queue, post a processing task, and return as + * quickly as possible to avoid any data overrun problems. + * + ****************************************************************************/ + +static size_t spi_slave_receive(FAR struct spi_slave_dev_s *dev, + FAR const void *data, size_t len) +{ + FAR struct spi_slave_driver_s *priv = (FAR struct spi_slave_driver_s *)dev; + size_t recv_bytes = MIN(len, sizeof(priv->rx_buffer)); + + memcpy(priv->rx_buffer, data, recv_bytes); + + priv->rx_length = recv_bytes; + + return BYTES2WORDS(recv_bytes); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_slave_register + * + * Description: + * Register the SPI Slave character device driver as 'devpath'. + * + * Input Parameters: + * ctrlr - An instance of the SPI Slave interface to use to communicate + * with the SPI Slave device + * bus - The SPI Slave bus number. This will be used as the SPI device + * minor number. The SPI Slave character device will be + * registered as /dev/spislvN where N is the minor number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int spi_slave_register(FAR struct spi_slave_ctrlr_s *ctrlr, int bus) +{ + FAR struct spi_slave_driver_s *priv; + char devname[DEVNAME_FMTLEN]; + int ret; + + /* Sanity check */ + + DEBUGASSERT(ctrlr != NULL && (unsigned int)bus < 1000); + + /* Initialize the SPI Slave device structure */ + + priv = (FAR struct spi_slave_driver_s *) + kmm_zalloc(sizeof(struct spi_slave_driver_s)); + if (!priv) + { + spierr("ERROR: Failed to allocate instance\n"); + return -ENOMEM; + } + + priv->dev.ops = &g_spisdev_ops; + priv->ctrlr = ctrlr; + +#ifdef CONFIG_SPI_SLAVE_DRIVER_COLORIZE_TX_BUFFER + memset(priv->tx_buffer, + CONFIG_SPI_SLAVE_DRIVER_COLORIZE_PATTERN, + CONFIG_SPI_SLAVE_DRIVER_COLORIZE_NUM_BYTES); + priv->tx_length = CONFIG_SPI_SLAVE_DRIVER_COLORIZE_NUM_BYTES; +#endif + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + nxsem_init(&priv->exclsem, 0, 1); +#endif + + /* Create the character device name */ + + snprintf(devname, DEVNAME_FMTLEN, DEVNAME_FMT, bus); + + /* Register the character driver */ + + ret = register_driver(devname, &g_spislavefops, 0666, priv); + if (ret < 0) + { + spierr("ERROR: Failed to register driver: %d\n", ret); + kmm_free(priv); + } + + SPIS_CTRLR_BIND(priv->ctrlr, (FAR struct spi_slave_dev_s *)priv, + CONFIG_SPI_SLAVE_DRIVER_MODE, + CONFIG_SPI_SLAVE_DRIVER_WIDTH); + + spiinfo("SPI Slave driver loaded successfully!\n"); + + return ret; +} + +#endif /* CONFIG_SPI_SLAVE_DRIVER */ diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig index d54bd5b0596..66cfd5b5330 100644 --- a/drivers/syslog/Kconfig +++ b/drivers/syslog/Kconfig @@ -13,6 +13,8 @@ config ARCH_SYSLOG # Selected if the SYSLOG device supports multi-byte write operations +comment "SYSLOG options" + config SYSLOG_MAX_CHANNELS int "Maximum SYSLOG channels" default 1 @@ -34,6 +36,14 @@ config RAMLOG details as needed to support logging. if RAMLOG +config RAMLOG_BUFFER_SECTION + string "The section where ramlog buffer is located" + default ".bss" + depends on RAMLOG_SYSLOG + ---help--- + The section where ramlog buffer is located. + The section shall not be initialized on system boot. + config RAMLOG_BUFSIZE int "RAMLOG buffer size" default 1024 @@ -97,6 +107,8 @@ config SYSLOG_INTBUFSIZE ---help--- The size of the interrupt buffer in bytes. +comment "Formatting options" + config SYSLOG_TIMESTAMP bool "Prepend timestamp to syslog message" default n @@ -180,9 +192,12 @@ config SYSLOG_COLOR_OUTPUT ---help--- Enables colored output in syslog, according to message priority. +comment "SYSLOG channels" + if !ARCH_SYSLOG config SYSLOG_CHAR bool "Log to a character device" + default n ---help--- Enable the generic character device for the SYSLOG. The full path to the SYSLOG device is provided by SYSLOG_DEVPATH. A valid character device (or @@ -191,6 +206,7 @@ config SYSLOG_CHAR config RAMLOG_SYSLOG bool "Use RAMLOG for SYSLOG" depends on RAMLOG + default n ---help--- Use the RAM logging device for the syslogging interface. If this feature is enabled (along with SYSLOG), then all debug output (only) @@ -208,6 +224,7 @@ config SYSLOG_RPMSG bool "Log to RPMSG" depends on OPENAMP depends on SCHED_WORKQUEUE + default n ---help--- Use the rpmsg as a SYSLOG output device, send message to remote proc. @@ -220,17 +237,10 @@ config SYSLOG_DEFAULT endif -config RAMLOG_BUFFER_SECTION - string "The section where ramlog buffer is located" - default ".bss" - depends on RAMLOG_SYSLOG - ---help--- - The section where ramlog buffer is located, this section cannot - be initialized each time when the system boot. - config SYSLOG_RPMSG_SERVER_NAME string "The name of Syslog Rpmsg Server" depends on SYSLOG_RPMSG + default "" ---help--- The proc name of rpmsg server. Client sends message to specified name of remote proc. @@ -247,7 +257,7 @@ config SYSLOG_RPMSG_SERVER ---help--- Use rpmsg to receive message from remote proc. -config SYSLOG_FILE +menuconfig SYSLOG_FILE bool "Syslog file output" default n ---help--- @@ -261,6 +271,48 @@ config SYSLOG_FILE NOTE interrupt level SYSLOG output will be lost in this case unless the interrupt buffer is used. +if SYSLOG_FILE + +config SYSLOG_FILE_SEPARATE + bool "Log file separation" + default n + depends on SYSLOG_FILE + ---help--- + If enabled, every time the file logger is re-attached, a separator + will be printed in the file. + + This can be useful to easily distinguish between log entries that + belong to different log sessions (e.g. system reboot), and to + indicate that between the separated lines there may be more logs + that were lost. + +config SYSLOG_FILE_ROTATIONS + int "Log file rotations" + default 0 + depends on SYSLOG_FILE + ---help--- + If enabled (set to a non-zero number), the log file size will be + checked before opening. If it is larger than the specified limit + it will be "rotated", i.e. the old file will be kept as a backup, + and a new empty file will be created. + + The number of rotations specifies the number of old log files to + keep. + + This option is useful to ensure that log files do not get + huge after prolonged periods of system operation. + +config SYSLOG_FILE_SIZE_LIMIT + int "Log file size limit" + default 524288 + depends on SYSLOG_FILE_ROTATIONS > 0 + ---help--- + File size limit when the log is rotated automatically. + If a log file is found larger than this limit, it will + be rotated. + +endif # SYSLOG_FILE + config CONSOLE_SYSLOG bool "Use SYSLOG for /dev/console" default n diff --git a/drivers/syslog/README.txt b/drivers/syslog/README.txt index 97bda14aa2d..2e1019cd7b6 100644 --- a/drivers/syslog/README.txt +++ b/drivers/syslog/README.txt @@ -372,7 +372,7 @@ SYSLOG Channel Options Prototype: #ifdef CONFIG_SYSLOG_FILE - int syslog_file_channel(FAR const char *devpath); + FAR struct syslog_channel_s *syslog_file_channel(FAR const char *devpath); #endif Description: @@ -406,8 +406,7 @@ SYSLOG Channel Options Returned Value: - Zero (OK) is returned on success; a negated errno value is returned on - any failure. + A pointer to the new SYSLOG channel; NULL is returned on any failure. References: drivers/syslog/syslog_filechannel.c, drivers/syslog/syslog_device.c, and include/nuttx/syslog/syslog.h. diff --git a/drivers/syslog/ramlog.c b/drivers/syslog/ramlog.c index ca7d6292c87..d19c613c1ca 100644 --- a/drivers/syslog/ramlog.c +++ b/drivers/syslog/ramlog.c @@ -94,12 +94,12 @@ static int ramlog_addchar(FAR struct ramlog_dev_s *priv, char ch); static ssize_t ramlog_file_read(FAR struct file *filep, FAR char *buffer, size_t buflen); -static ssize_t ramlog_file_write(FAR struct file *filep, FAR const char *buffer, - size_t buflen); +static ssize_t ramlog_file_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen); static int ramlog_file_ioctl(FAR struct file *filep, int cmd, unsigned long arg); -static int ramlog_file_poll(FAR struct file *filep, FAR struct pollfd *fds, - bool setup); +static int ramlog_file_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup); /**************************************************************************** * Private Data @@ -398,8 +398,8 @@ static ssize_t ramlog_addbuf(FAR struct ramlog_dev_s *priv, /* If there are multiple readers, some of them might block despite * POLLIN because first reader might read all data. Favor readers - * and notify poll waiters only if no reader was awaken, even if the - * latter may starve. + * and notify poll waiters only if no reader was awakened, even if + * the latter may starve. * * This also implies we do not have to make these two notify * operations a critical section. @@ -492,8 +492,8 @@ static ssize_t ramlog_file_read(FAR struct file *filep, FAR char *buffer, /* Otherwise, wait for something to be written to the circular * buffer. Increment the number of waiters so that the - * ramlog_file_write() will note that it needs to post the semaphore - * to wake us up. + * ramlog_file_write() will note that it needs to post the + * semaphore to wake us up. */ sched_lock(); @@ -593,8 +593,8 @@ errout_without_sem: * Name: ramlog_file_write ****************************************************************************/ -static ssize_t ramlog_file_write(FAR struct file *filep, FAR const char *buffer, - size_t len) +static ssize_t ramlog_file_write(FAR struct file *filep, + FAR const char *buffer, size_t len) { FAR struct inode *inode = filep->f_inode; FAR struct ramlog_dev_s *priv; @@ -611,7 +611,8 @@ static ssize_t ramlog_file_write(FAR struct file *filep, FAR const char *buffer, * Name: ramlog_file_ioctl ****************************************************************************/ -static int ramlog_file_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +static int ramlog_file_ioctl(FAR struct file *filep, int cmd, + unsigned long arg) { FAR struct inode *inode = filep->f_inode; FAR struct ramlog_dev_s *priv; @@ -863,8 +864,8 @@ int ramlog_putc(FAR struct syslog_channel_s *channel, int ch) /* If there are multiple readers, some of them might block despite * POLLIN because first reader might read all data. Favor readers - * and notify poll waiters only if no reader was awaken, even if the - * latter may starve. + * and notify poll waiters only if no reader was awakened, even if + * the latter may starve. * * This also implies we do not have to make these two notify * operations a critical section. @@ -882,7 +883,6 @@ int ramlog_putc(FAR struct syslog_channel_s *channel, int ch) return ch; } - ssize_t ramlog_write(FAR struct syslog_channel_s *channel, FAR const char *buffer, size_t buflen) { diff --git a/drivers/syslog/syslog.h b/drivers/syslog/syslog.h index 331f82c7b3e..a1e7e2803ed 100644 --- a/drivers/syslog/syslog.h +++ b/drivers/syslog/syslog.h @@ -94,10 +94,6 @@ FAR struct syslog_channel_s *syslog_dev_initialize(FAR const char *devpath, * Input Parameters: * channel - Handle to syslog channel to be used. * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * * Assumptions: * The caller has already switched the SYSLOG source to some safe channel * (the default channel). @@ -125,13 +121,12 @@ void syslog_dev_uninitialize(FAR struct syslog_channel_s *channel); * None * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. + * A pointer to the new SYSLOG channel; NULL is returned on any failure. * ****************************************************************************/ #ifdef CONFIG_SYSLOG_CHAR -int syslog_dev_channel(void); +FAR struct syslog_channel_s *syslog_dev_channel(void); #endif /**************************************************************************** @@ -156,13 +151,12 @@ int syslog_dev_channel(void); * None * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. + * A pointer to the new SYSLOG channel; NULL is returned on any failure. * ****************************************************************************/ #ifdef CONFIG_SYSLOG_CONSOLE -int syslog_console_channel(void); +FAR struct syslog_channel_s *syslog_console_channel(void); #endif /**************************************************************************** diff --git a/drivers/syslog/syslog_channel.c b/drivers/syslog/syslog_channel.c index 293d3f0a021..c05c4ba1df4 100644 --- a/drivers/syslog/syslog_channel.c +++ b/drivers/syslog/syslog_channel.c @@ -269,6 +269,15 @@ int syslog_channel_remove(FAR struct syslog_channel_s *channel) g_syslog_channel[i] = NULL; + /* The channel is now removed from the list and its driver + * can be safely uninitialized. + */ + + if (channel->sc_ops->sc_close) + { + channel->sc_ops->sc_close(channel); + } + return OK; } } diff --git a/drivers/syslog/syslog_consolechannel.c b/drivers/syslog/syslog_consolechannel.c index c85a4a80801..9fcd426f7b2 100644 --- a/drivers/syslog/syslog_consolechannel.c +++ b/drivers/syslog/syslog_consolechannel.c @@ -75,12 +75,11 @@ FAR static struct syslog_channel_s *g_syslog_console_channel; * None * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. + * A pointer to the new SYSLOG channel; NULL is returned on any failure. * ****************************************************************************/ -int syslog_console_channel(void) +FAR struct syslog_channel_s *syslog_console_channel(void) { /* Initialize the character driver interface */ @@ -88,12 +87,18 @@ int syslog_console_channel(void) OPEN_FLAGS, OPEN_MODE); if (g_syslog_console_channel == NULL) { - return -ENOMEM; + return NULL; } /* Use the character driver as the SYSLOG channel */ - return syslog_channel(g_syslog_console_channel); + if (syslog_channel(g_syslog_console_channel) != OK) + { + syslog_dev_uninitialize(g_syslog_console_channel); + g_syslog_console_channel = NULL; + } + + return g_syslog_console_channel; } #endif /* CONFIG_SYSLOG_CONSOLE */ diff --git a/drivers/syslog/syslog_devchannel.c b/drivers/syslog/syslog_devchannel.c index d3826880ebe..00b534dbc5f 100644 --- a/drivers/syslog/syslog_devchannel.c +++ b/drivers/syslog/syslog_devchannel.c @@ -72,12 +72,11 @@ FAR static struct syslog_channel_s *g_syslog_dev_channel; * None * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. + * A pointer to the new SYSLOG channel; NULL is returned on any failure. * ****************************************************************************/ -int syslog_dev_channel(void) +FAR struct syslog_channel_s *syslog_dev_channel(void) { /* Initialize the character driver interface */ @@ -85,12 +84,18 @@ int syslog_dev_channel(void) OPEN_FLAGS, OPEN_MODE); if (g_syslog_dev_channel == NULL) { - return -ENOMEM; + return NULL; } /* Use the character driver as the SYSLOG channel */ - return syslog_channel(g_syslog_dev_channel); + if (syslog_channel(g_syslog_dev_channel) != OK) + { + syslog_dev_uninitialize(g_syslog_dev_channel); + g_syslog_dev_channel = NULL; + } + + return g_syslog_dev_channel; } #endif /* CONFIG_SYSLOG_CHAR */ diff --git a/drivers/syslog/syslog_device.c b/drivers/syslog/syslog_device.c index eee530ed1d3..16d74942e37 100644 --- a/drivers/syslog/syslog_device.c +++ b/drivers/syslog/syslog_device.c @@ -110,7 +110,8 @@ static const struct syslog_channel_ops_s g_syslog_dev_ops = syslog_dev_putc, syslog_dev_force, syslog_dev_flush, - syslog_dev_write + syslog_dev_write, + syslog_dev_uninitialize }; static const uint8_t g_syscrlf[2] = diff --git a/drivers/syslog/syslog_filechannel.c b/drivers/syslog/syslog_filechannel.c index 0a5346d0087..ddc27aa0fd9 100644 --- a/drivers/syslog/syslog_filechannel.c +++ b/drivers/syslog/syslog_filechannel.c @@ -25,11 +25,18 @@ #include #include +#include #include #include #include +#include +#include +#include +#include #include +#include +#include #include "syslog.h" @@ -50,6 +57,83 @@ FAR static struct syslog_channel_s *g_syslog_file_channel; +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_SYSLOG_FILE_SEPARATE +static void log_separate(FAR const char *log_file) +{ + struct file fp; + + if (file_open(&fp, log_file, O_WRONLY) < 0) + { + return; + } + + file_write(&fp, "\n\n", 2); + + file_close(&fp); +} +#endif + +#if CONFIG_SYSLOG_FILE_ROTATIONS > 0 +static void log_rotate(FAR const char *log_file) +{ + int i; + off_t size; + struct stat f_stat; + size_t name_size; + FAR char *rotate_to; + FAR char *rotate_from; + + /* Get the size of the current log file. */ + + if (stat(log_file, &f_stat) < 0) + { + return; + } + + size = f_stat.st_size; + + /* If it does not exceed the limit we are OK. */ + + if (size < CONFIG_SYSLOG_FILE_SIZE_LIMIT) + { + return; + } + + /* Rotated file names. */ + + name_size = strlen(log_file) + 8; + rotate_to = kmm_malloc(name_size); + rotate_from = kmm_malloc(name_size); + if ((rotate_to == NULL) || (rotate_from == NULL)) + { + goto end; + } + + /* Rotate the logs. */ + + for (i = (CONFIG_SYSLOG_FILE_ROTATIONS - 1); i > 0; i--) + { + snprintf(rotate_to, name_size, "%s.%d", log_file, i); + snprintf(rotate_from, name_size, "%s.%d", log_file, i - 1); + + rename(rotate_from, rotate_to); + } + + snprintf(rotate_to, name_size, "%s.0", log_file); + + rename(log_file, rotate_to); + +end: + + kmm_free(rotate_to); + kmm_free(rotate_from); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -85,15 +169,12 @@ FAR static struct syslog_channel_s *g_syslog_file_channel; * file. * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. + * A pointer to the new SYSLOG channel; NULL is returned on any failure. * ****************************************************************************/ -int syslog_file_channel(FAR const char *devpath) +FAR struct syslog_channel_s *syslog_file_channel(FAR const char *devpath) { - int ret; - /* Reset the default SYSLOG channel so that we can safely modify the * SYSLOG device. This is an atomic operation and we should be safe * after the default channel has been selected. @@ -111,13 +192,24 @@ int syslog_file_channel(FAR const char *devpath) syslog_dev_uninitialize(g_syslog_file_channel); } + /* Rotate the log file, if needed. */ + +#if CONFIG_SYSLOG_FILE_ROTATIONS > 0 + log_rotate(devpath); +#endif + + /* Separate the old log entries. */ + +#ifdef CONFIG_SYSLOG_FILE_SEPARATE + log_separate(devpath); +#endif + /* Then initialize the file interface */ g_syslog_file_channel = syslog_dev_initialize(devpath, OPEN_FLAGS, OPEN_MODE); if (g_syslog_file_channel == NULL) { - ret = -ENOMEM; goto errout_with_lock; } @@ -125,11 +217,15 @@ int syslog_file_channel(FAR const char *devpath) * screwed. */ - ret = syslog_channel(g_syslog_file_channel); + if (syslog_channel(g_syslog_file_channel) != OK) + { + syslog_dev_uninitialize(g_syslog_file_channel); + g_syslog_file_channel = NULL; + } errout_with_lock: sched_unlock(); - return ret; + return g_syslog_file_channel; } #endif /* CONFIG_SYSLOG_FILE */ diff --git a/drivers/syslog/syslog_initialize.c b/drivers/syslog/syslog_initialize.c index 671d74d9666..d6c302b9679 100644 --- a/drivers/syslog/syslog_initialize.c +++ b/drivers/syslog/syslog_initialize.c @@ -72,11 +72,11 @@ int syslog_initialize(void) #if defined(CONFIG_SYSLOG_CHAR) /* Enable use of a character device as the SYSLOG device */ - ret = syslog_dev_channel(); + syslog_dev_channel(); #elif defined(CONFIG_SYSLOG_CONSOLE) /* Use the console device as the SYSLOG device */ - ret = syslog_console_channel(); + syslog_console_channel(); #endif #ifdef CONFIG_RAMLOG_SYSLOG diff --git a/drivers/syslog/syslog_rpmsg_server.c b/drivers/syslog/syslog_rpmsg_server.c index 1572771857a..d57c5c45fef 100644 --- a/drivers/syslog/syslog_rpmsg_server.c +++ b/drivers/syslog/syslog_rpmsg_server.c @@ -24,6 +24,8 @@ #include +#include + #include #include #include diff --git a/drivers/syslog/syslog_write.c b/drivers/syslog/syslog_write.c index 005823fc916..9bc320fbbea 100644 --- a/drivers/syslog/syslog_write.c +++ b/drivers/syslog/syslog_write.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/drivers/syslog/vsyslog.c b/drivers/syslog/vsyslog.c index d7365cd011c..5592995c176 100644 --- a/drivers/syslog/vsyslog.c +++ b/drivers/syslog/vsyslog.c @@ -72,9 +72,15 @@ int nx_vsyslog(int priority, FAR const IPTR char *fmt, FAR va_list *ap) struct tcb_s *tcb; #endif #ifdef CONFIG_SYSLOG_TIMESTAMP - struct timespec ts = { }; + struct timespec ts = + { + }; + #if defined(CONFIG_SYSLOG_TIMESTAMP_FORMATTED) - struct tm tm = { }; + struct tm tm = + { + }; + char date_buf[CONFIG_SYSLOG_TIMESTAMP_BUFFER]; #endif #endif @@ -111,7 +117,7 @@ int nx_vsyslog(int priority, FAR const IPTR char *fmt, FAR va_list *ap) clock_systime_timespec(&ts); #endif - /* Prepend the message with the current time, if available */ + /* Prepend the message with the current time, if available */ #if defined(CONFIG_SYSLOG_TIMESTAMP_FORMATTED) #if defined(CONFIG_SYSLOG_TIMESTAMP_LOCALTIME) @@ -200,7 +206,8 @@ int nx_vsyslog(int priority, FAR const IPTR char *fmt, FAR va_list *ap) /* Prepend the process name */ tcb = nxsched_get_tcb(getpid()); - ret += lib_sprintf(&stream.public, "%s: ", tcb->name); + ret += lib_sprintf(&stream.public, "%s: ", + (tcb != NULL) ? tcb->name : "(null)"); #endif /* Generate the output */ diff --git a/drivers/timers/pwm.c b/drivers/timers/pwm.c index 257ff11c1b0..0b2f02e6aca 100644 --- a/drivers/timers/pwm.c +++ b/drivers/timers/pwm.c @@ -131,7 +131,7 @@ static void pwm_dump(FAR const char *msg, FAR const struct pwm_info_s *info, #endif #ifdef CONFIG_PWM_PULSECOUNT - pwminfo(" count: %d\n", info->count); + pwminfo(" count: %" PRIx32 "\n", info->count); #endif pwminfo(" started: %d\n", started); diff --git a/drivers/timers/rtc.c b/drivers/timers/rtc.c index d53809a108a..727301a3943 100644 --- a/drivers/timers/rtc.c +++ b/drivers/timers/rtc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index d1db8291778..189556391a3 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/timers/timer.c * - * Copyright (C) 2014, 2016-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/usbdev/Kconfig b/drivers/usbdev/Kconfig index b3a943f91b5..cfcb4e46a8e 100644 --- a/drivers/usbdev/Kconfig +++ b/drivers/usbdev/Kconfig @@ -852,6 +852,14 @@ config USBMSC_SCSI_STACKSIZE Stack size used with the SCSI kernel thread. The default value is not tuned. +config USBMSC_NOT_STALL_BULKEP + bool "Not stall USBMSC bulk endpoints for workaround" + default n + ---help--- + Not stall USBMSC bulk endpoints in some conditions. + Because RP2040 usbdev driver cannot handle stalling/resuming bulk + endpoints well, this workaround is required. + endif menuconfig RNDIS diff --git a/drivers/usbdev/adb.c b/drivers/usbdev/adb.c index 0b6f7a6565d..f87402bba80 100644 --- a/drivers/usbdev/adb.c +++ b/drivers/usbdev/adb.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include diff --git a/drivers/usbdev/cdcacm.c b/drivers/usbdev/cdcacm.c index f5fe66421d1..91c574b1827 100644 --- a/drivers/usbdev/cdcacm.c +++ b/drivers/usbdev/cdcacm.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usbdev/cdcecm.c b/drivers/usbdev/cdcecm.c index 31d3ea81613..742502112ec 100644 --- a/drivers/usbdev/cdcecm.c +++ b/drivers/usbdev/cdcecm.c @@ -1,53 +1,28 @@ /**************************************************************************** * drivers/usbdev/cdcecm.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Michael Jung + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * [CDCECM1.2] Universal Serial Bus - Communications Class - Subclass - * Specification for Ethernet Control Model Devices - Rev 1.2 + * http://www.apache.org/licenses/LICENSE-2.0 * - * This driver derives in part from the NuttX CDC/ACM driver: - * - * Copyright (C) 2011-2013, 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * and also from the NuttX RNDIS driver: - * - * Copyright (C) 2011-2017 Gregory Nutt. All rights reserved. - * Authors: Sakari Kapanen , - * Petteri Aimonen - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * [CDCECM1.2] Universal Serial Bus - Communications Class - Subclass + * Specification for Ethernet Control Model Devices - Rev 1.2 + */ + /**************************************************************************** * Included Files ****************************************************************************/ diff --git a/drivers/usbdev/composite.c b/drivers/usbdev/composite.c index 053dc363693..cf7c6c2c147 100644 --- a/drivers/usbdev/composite.c +++ b/drivers/usbdev/composite.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/drivers/usbdev/dfu.c b/drivers/usbdev/dfu.c index 64e3a6ca2af..ca27059b9c8 100644 --- a/drivers/usbdev/dfu.c +++ b/drivers/usbdev/dfu.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/usbdev/dfu.c * - * Copyright (C) 2011-2018 Gregory Nutt. All rights reserved. - * Authors: Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -54,6 +39,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usbdev/pl2303.c b/drivers/usbdev/pl2303.c index f95a29c91ae..3eb72e8943c 100644 --- a/drivers/usbdev/pl2303.c +++ b/drivers/usbdev/pl2303.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usbdev/rndis.c b/drivers/usbdev/rndis.c index 2ea46ce47f0..0f486d560b0 100644 --- a/drivers/usbdev/rndis.c +++ b/drivers/usbdev/rndis.c @@ -1,48 +1,35 @@ /**************************************************************************** * drivers/usbdev/rndis.c * - * Copyright (C) 2011-2018 Gregory Nutt. All rights reserved. - * Authors: Sakari Kapanen , - * Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * [MS-RNDIS]: - * Remote Network Driver Interface Specification (RNDIS) Protocol + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * [MS-RNDIS]: + * Remote Network Driver Interface Specification (RNDIS) Protocol + */ + /**************************************************************************** * Included Files ****************************************************************************/ #include +#include +#include #include #include #include diff --git a/drivers/usbdev/rndis_std.h b/drivers/usbdev/rndis_std.h index 8fdb1df91ba..3b75e3951ff 100644 --- a/drivers/usbdev/rndis_std.h +++ b/drivers/usbdev/rndis_std.h @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/usbdev/rndis_std.h * - * Copyright (C) 2011-2017 Gregory Nutt. All rights reserved. - * Authors: Sakari Kapanen , - * Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/usbdev/usbmsc.c b/drivers/usbdev/usbmsc.c index 41d2dfe55b4..5c3a3fbf161 100644 --- a/drivers/usbdev/usbmsc.c +++ b/drivers/usbdev/usbmsc.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usbdev/usbmsc_scsi.c b/drivers/usbdev/usbmsc_scsi.c index 68d08400d7f..7cd5bd8f88b 100644 --- a/drivers/usbdev/usbmsc_scsi.c +++ b/drivers/usbdev/usbmsc_scsi.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include #include @@ -662,12 +663,14 @@ static inline int usbmsc_cmdinquiry(FAR struct usbmsc_dev_s *priv, response->qualtype = SCSIRESP_INQUIRYPQ_NOTCAPABLE | SCSIRESP_INQUIRYPD_UNKNOWN; } +#ifndef CONFIG_USBMSC_NOT_STALL_BULKEP else if ((inquiry->flags != 0) || (inquiry->pagecode != 0)) { usbtrace(TRACE_CLSERROR(USBMSC_TRACEERR_INQUIRYFLAGS), 0); priv->lun->sd = SCSI_KCQIR_INVALIDFIELDINCBA; ret = -EINVAL; } +#endif else { memset(response, 0, SCSIRESP_INQUIRY_SIZEOF); @@ -821,7 +824,9 @@ static int inline usbmsc_cmdmodesense6(FAR struct usbmsc_dev_s *priv, (FAR struct scsicmd_modesense6_s *)priv->cdb; FAR struct scsiresp_modeparameterhdr6_s *mph = (FAR struct scsiresp_modeparameterhdr6_s *)buf; +#ifndef CONFIG_USBMSC_NOT_STALL_BULKEP int mdlen; +#endif int ret; priv->u.alloclen = modesense->alloclen; @@ -829,6 +834,11 @@ static int inline usbmsc_cmdmodesense6(FAR struct usbmsc_dev_s *priv, USBMSC_FLAGS_DIRDEVICE2HOST); if (ret == OK) { +#ifdef CONFIG_USBMSC_NOT_STALL_BULKEP + priv->residue = priv->cbwlen = priv->nreqbytes = + SCSIRESP_MODEPARAMETERHDR6_SIZEOF; +#endif + if ((modesense->flags & ~SCSICMD_MODESENSE6_DBD) != 0 || modesense->subpgcode != 0) { @@ -850,6 +860,7 @@ static int inline usbmsc_cmdmodesense6(FAR struct usbmsc_dev_s *priv, (priv->lun->readonly ? SCSIRESP_MODEPARMHDR_DAPARM_WP : 0x00); mph->bdlen = 0; /* Block descriptor length */ +#ifndef CONFIG_USBMSC_NOT_STALL_BULKEP /* There are no block descriptors, only the following mode page: */ ret = usbmsc_modepage(priv, @@ -866,6 +877,7 @@ static int inline usbmsc_cmdmodesense6(FAR struct usbmsc_dev_s *priv, priv->nreqbytes = mdlen + SCSIRESP_MODEPARAMETERHDR6_SIZEOF; } +#endif } } @@ -2583,6 +2595,7 @@ static int usbmsc_cmdfinishstate(FAR struct usbmsc_dev_s *priv) if (priv->residue > 0) { +#ifndef CONFIG_USBMSC_NOT_STALL_BULKEP usbtrace(TRACE_CLSERROR(USBMSC_TRACEERR_CMDFINISHRESIDUE), (uint16_t)priv->residue); @@ -2600,6 +2613,9 @@ static int usbmsc_cmdfinishstate(FAR struct usbmsc_dev_s *priv) nxsig_usleep (100000); #else EP_STALL(priv->epbulkin); +#endif +#else + priv->residue = 0; #endif } } diff --git a/drivers/usbhost/usbhost_devaddr.c b/drivers/usbhost/usbhost_devaddr.c index 3dd60b05d42..37cc2308037 100644 --- a/drivers/usbhost/usbhost_devaddr.c +++ b/drivers/usbhost/usbhost_devaddr.c @@ -27,6 +27,7 @@ #include #include +#include #include #include diff --git a/drivers/usbhost/usbhost_hub.c b/drivers/usbhost/usbhost_hub.c index 9c22367632a..209ac561a70 100644 --- a/drivers/usbhost/usbhost_hub.c +++ b/drivers/usbhost/usbhost_hub.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/usbhost/usbhost_hub.c * - * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. - * Author: Kaushal Parikh - * Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/usbhost/usbhost_max3421e.c b/drivers/usbhost/usbhost_max3421e.c index 3166db61f7b..6546bb8adac 100644 --- a/drivers/usbhost/usbhost_max3421e.c +++ b/drivers/usbhost/usbhost_max3421e.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include diff --git a/drivers/usbhost/usbhost_trace.c b/drivers/usbhost/usbhost_trace.c index 2107f86c5d7..b8b267bd180 100644 --- a/drivers/usbhost/usbhost_trace.c +++ b/drivers/usbhost/usbhost_trace.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/usbhost/usbhost_xboxcontroller.c b/drivers/usbhost/usbhost_xboxcontroller.c index f3e3a160b15..78d51a60ae2 100644 --- a/drivers/usbhost/usbhost_xboxcontroller.c +++ b/drivers/usbhost/usbhost_xboxcontroller.c @@ -1,36 +1,20 @@ /**************************************************************************** * drivers/usbhost/usbhost_xboxcontroller.c * - * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Brian Webb + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/usbmonitor/usbmonitor.c b/drivers/usbmonitor/usbmonitor.c index fc100211d48..209690892d4 100644 --- a/drivers/usbmonitor/usbmonitor.c +++ b/drivers/usbmonitor/usbmonitor.c @@ -30,8 +30,8 @@ #include #include #include -#include #include +#include #include #include diff --git a/drivers/video/fb.c b/drivers/video/fb.c index d08a7b40fbf..e97ec5af2d4 100644 --- a/drivers/video/fb.c +++ b/drivers/video/fb.c @@ -30,6 +30,8 @@ #include #include #include +#include +#include #include #include diff --git a/drivers/wireless/bluetooth/bt_uart_bcm4343x.c b/drivers/wireless/bluetooth/bt_uart_bcm4343x.c index 43e0f491f85..facd7ed1b9c 100644 --- a/drivers/wireless/bluetooth/bt_uart_bcm4343x.c +++ b/drivers/wireless/bluetooth/bt_uart_bcm4343x.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/drivers/wireless/bluetooth/bt_uart_shim.c b/drivers/wireless/bluetooth/bt_uart_shim.c index a7c340482c7..1c250e4baba 100644 --- a/drivers/wireless/bluetooth/bt_uart_shim.c +++ b/drivers/wireless/bluetooth/bt_uart_shim.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/bluetooth/bt_uart_shim.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/gs2200m.c b/drivers/wireless/gs2200m.c index bd28cb9dca8..6364c9f2016 100644 --- a/drivers/wireless/gs2200m.c +++ b/drivers/wireless/gs2200m.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include @@ -216,6 +217,8 @@ static int gs2200m_poll(FAR struct file *filep, FAR struct pollfd *fds, static int gs2200m_irq(int irq, FAR void *context, FAR void *arg); static void gs2200m_irq_worker(FAR void *arg); +static void _remove_all_pkt(FAR struct gs2200m_dev_s *dev, uint8_t c); + /**************************************************************************** * Private Data ****************************************************************************/ @@ -524,7 +527,7 @@ static void _check_pkt_q_empty(FAR struct gs2200m_dev_s *dev, char cid) pkt_dat = (FAR struct pkt_dat_s *)pkt_dat->dq.flink; } - ASSERT(false); + _remove_all_pkt(dev, c); } } @@ -2380,6 +2383,7 @@ static int gs2200m_ioctl_send(FAR struct gs2200m_dev_s *dev, { wlinfo("+++ already closed \n"); type = TYPE_DISCONNECT; + ret = -ENOTCONN; goto errout; } @@ -2389,7 +2393,7 @@ static int gs2200m_ioctl_send(FAR struct gs2200m_dev_s *dev, errout: - if (type != TYPE_OK) + if (type != TYPE_OK && type != TYPE_DISCONNECT) { ret = -EINVAL; } diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.c index 85536352532..c32305fd049 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.c * - * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.h index a6725f06ac6..52b644ce315 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.h @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_bdc.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.c index d88fb8f3dd3..b260f4a3b92 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.h index ac11e963b51..15f4cf7ca91 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.h @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_cdc.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43362.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43362.c index 9ef97bc3ec7..22531e790d3 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43362.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43362.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43362.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43438.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43438.c index 49f76acac3a..97a341e79cf 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43438.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43438.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43438.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_core.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_core.c index 0b7b4007963..cdd37cabd7a 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_core.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_core.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_core.c * - * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_core.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_core.h index 86d1f588834..ae4c4348b0e 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_core.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_core.h @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_core.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c index bb17e33c923..f0ed29e89ac 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c * - * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -1081,7 +1066,7 @@ int bcmf_wl_start_scan(FAR struct bcmf_dev_s *priv, struct iwreq *iwr) /* Scan specific ESSID */ memcpy(scan_params.params.ssid.SSID, req->essid, req->essid_len); - scan_params.params.ssid.SSID_len = req->essid_len; + scan_params.params.ssid.ssid_len = req->essid_len; } } else @@ -1309,6 +1294,10 @@ int bcmf_wl_set_auth_param(FAR struct bcmf_dev_s *priv, struct iwreq *iwr) switch (iwr->u.param.value) { + case IW_AUTH_CIPHER_NONE: + cipher_mode = OPEN_AUTH; + break; + case IW_AUTH_CIPHER_WEP40: case IW_AUTH_CIPHER_WEP104: cipher_mode = WEP_ENABLED; @@ -1443,7 +1432,7 @@ int bcmf_wl_set_ssid(FAR struct bcmf_dev_s *priv, struct iwreq *iwr) return -EINVAL; } - ssid.SSID_len = iwr->u.essid.length; + ssid.ssid_len = iwr->u.essid.length; memcpy(ssid.SSID, iwr->u.essid.pointer, iwr->u.essid.length); /* Configure AP SSID and trig authentication request */ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h index 4fe9195c513..bb468526389 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h index f8f2b67dd31..f02894b3ce7 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h @@ -61,7 +61,7 @@ typedef struct wl_action_frame { struct ether_addr da; uint16_t len; - uint32_t packetId; + uint32_t packet_id; uint8_t data[ACTION_FRAME_SIZE]; } wl_action_frame_t; @@ -87,7 +87,7 @@ typedef struct wl_bss_info struct ether_addr BSSID; uint16_t beacon_period; /* units are Kusec */ uint16_t capability; /* Capability information */ - uint8_t SSID_len; + uint8_t ssid_len; uint8_t SSID[32]; struct { @@ -123,7 +123,7 @@ typedef struct wl_bss_info typedef struct wlc_ssid { - uint32_t SSID_len; + uint32_t ssid_len; uint8_t SSID[32]; } wlc_ssid_t; @@ -1210,13 +1210,13 @@ typedef struct uint8_t txpwr_local_constraint; uint8_t txpwr_chan_reg_max; uint8_t txpwr_target[2][NUM_PWRCTRL_RATES]; - uint8_t txpwr_est_Pout[2]; + uint8_t txpwr_est_pout[2]; uint8_t txpwr_opo[NUM_PWRCTRL_RATES]; uint8_t txpwr_bphy_cck_max[NUM_PWRCTRL_RATES]; uint8_t txpwr_bphy_ofdm_max; uint8_t txpwr_aphy_max[NUM_PWRCTRL_RATES]; int8_t txpwr_antgain[2]; - uint8_t txpwr_est_Pout_gofdm; + uint8_t txpwr_est_pout_gofdm; } tx_power_legacy_t; #define WL_TX_POWER_RATES 45 @@ -1246,8 +1246,8 @@ typedef struct uint8_t local_constraint; int8_t antgain[2]; uint8_t rf_cores; - uint8_t est_Pout[4]; - uint8_t est_Pout_cck; + uint8_t est_pout[4]; + uint8_t est_pout_cck; uint8_t user_limit[WL_TX_POWER_RATES]; uint8_t reg_limit[WL_TX_POWER_RATES]; uint8_t board_limit[WL_TX_POWER_RATES]; @@ -1256,8 +1256,8 @@ typedef struct typedef struct tx_inst_power { - uint8_t txpwr_est_Pout[2]; - uint8_t txpwr_est_Pout_gofdm; + uint8_t txpwr_est_pout[2]; + uint8_t txpwr_est_pout_gofdm; } tx_inst_power_t; #define WLC_MEASURE_TPC 1 @@ -2161,18 +2161,18 @@ typedef struct uint32_t rxampdu_stbc; uint32_t rxmpdu_sgi; uint32_t rxmpdu_stbc; - uint32_t rxmcs0_40M; - uint32_t rxmcs1_40M; - uint32_t rxmcs2_40M; - uint32_t rxmcs3_40M; - uint32_t rxmcs4_40M; - uint32_t rxmcs5_40M; - uint32_t rxmcs6_40M; - uint32_t rxmcs7_40M; - uint32_t rxmcs32_40M; - uint32_t txfrmsnt_20Mlo; - uint32_t txfrmsnt_20Mup; - uint32_t txfrmsnt_40M; + uint32_t rxmcs0_40; + uint32_t rxmcs1_40; + uint32_t rxmcs2_40; + uint32_t rxmcs3_40; + uint32_t rxmcs4_40; + uint32_t rxmcs5_40; + uint32_t rxmcs6_40; + uint32_t rxmcs7_40; + uint32_t rxmcs32_40; + uint32_t txfrmsnt_20lo; + uint32_t txfrmsnt_20up; + uint32_t txfrmsnt_40; uint32_t rx_20ul; } wl_cnt_ext_t; #define WL_RXDIV_STATS_T_VERSION 1 @@ -2687,20 +2687,20 @@ typedef struct wl_rssi_event typedef struct sta_prbreq_wps_ie_hdr { - struct ether_addr staAddr; - uint16_t ieLen; + struct ether_addr sta_addr; + uint16_t ie_len; } sta_prbreq_wps_ie_hdr_t; typedef struct sta_prbreq_wps_ie_data { sta_prbreq_wps_ie_hdr_t hdr; - uint8_t ieData[1]; + uint8_t ie_data[1]; } sta_prbreq_wps_ie_data_t; typedef struct sta_prbreq_wps_ie_list { - uint32_t totLen; - uint8_t ieDataList[1]; + uint32_t tot_len; + uint8_t ie_data_list[1]; } sta_prbreq_wps_ie_list_t; /* EDCF related items from 802.11.h */ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.h index 826e22c1d9b..c20fdd57bf1 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.h @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c index d34d456acdb..910e33e4ea7 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c * - * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.h index fdd575475a9..7059314eade 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.h @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.h * - * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.c index c697422eae4..01266d65b22 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.h index 33c6b047671..c354426a708 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.h @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_sdpcm.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.c index 9bb60ec85d9..f0bd937fcc7 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.h index 94520a996de..26492386b1d 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.h @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/drivers/wireless/ieee80211/bcm43xxx/mmc_sdio.c b/drivers/wireless/ieee80211/bcm43xxx/mmc_sdio.c index 4d8355c8acd..e38034a0ade 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/mmc_sdio.c +++ b/drivers/wireless/ieee80211/bcm43xxx/mmc_sdio.c @@ -1,35 +1,20 @@ /**************************************************************************** * drivers/wireless/ieee80211/bcm43xxx/mmc_sdio.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -241,15 +226,15 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write, if ((SDIO_CAPABILITIES(dev) & SDIO_CAPS_DMABEFOREWRITE) != 0) { SDIO_DMASENDSETUP(dev, buf, blocklen * nblocks); - SDIO_SENDCMD(dev, SD_ACMD53, arg.value); + SDIO_SENDCMD(dev, SD_ACMD53WR, arg.value); wkupevent = SDIO_EVENTWAIT(dev); - ret = SDIO_RECVR5(dev, SD_ACMD53, &data); + ret = SDIO_RECVR5(dev, SD_ACMD53WR, &data); } else { - sdio_sendcmdpoll(dev, SD_ACMD53, arg.value); - ret = SDIO_RECVR5(dev, SD_ACMD53, &data); + sdio_sendcmdpoll(dev, SD_ACMD53WR, arg.value); + ret = SDIO_RECVR5(dev, SD_ACMD53WR, &data); SDIO_DMASENDSETUP(dev, buf, blocklen * nblocks); wkupevent = SDIO_EVENTWAIT(dev); @@ -259,10 +244,10 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write, { wlinfo("prep read %d\n", blocklen * nblocks); SDIO_DMARECVSETUP(dev, buf, blocklen * nblocks); - SDIO_SENDCMD(dev, SD_ACMD53, arg.value); + SDIO_SENDCMD(dev, SD_ACMD53RD, arg.value); wkupevent = SDIO_EVENTWAIT(dev); - ret = SDIO_RECVR5(dev, SD_ACMD53, &data); + ret = SDIO_RECVR5(dev, SD_ACMD53RD, &data); } wlinfo("Transaction ends\n"); diff --git a/drivers/wireless/ieee802154/xbee/xbee_mac.c b/drivers/wireless/ieee802154/xbee/xbee_mac.c index 8ec76f52ce2..df86fa5d625 100644 --- a/drivers/wireless/ieee802154/xbee/xbee_mac.c +++ b/drivers/wireless/ieee802154/xbee/xbee_mac.c @@ -40,6 +40,8 @@ #include #include +#include +#include #include #include diff --git a/fs/Kconfig b/fs/Kconfig index 02b9f769452..e8f8b295614 100644 --- a/fs/Kconfig +++ b/fs/Kconfig @@ -82,6 +82,7 @@ config EVENT_FD_POLL config EVENT_FD_NPOLLWAITERS int "Number of eventFD poll waiters" default 2 + depends on EVENT_FD_POLL ---help--- Maximum number of threads that can be waiting on poll() diff --git a/fs/aio/aio_queue.c b/fs/aio/aio_queue.c index 7c93babf5af..719d40fd523 100644 --- a/fs/aio/aio_queue.c +++ b/fs/aio/aio_queue.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/fs/aio/aioc_contain.c b/fs/aio/aioc_contain.c index a95d4146325..a40a9860c5e 100644 --- a/fs/aio/aioc_contain.c +++ b/fs/aio/aioc_contain.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/fs/cromfs/fs_cromfs.c b/fs/cromfs/fs_cromfs.c index 71b27a22fa4..644d7823dc5 100644 --- a/fs/cromfs/fs_cromfs.c +++ b/fs/cromfs/fs_cromfs.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include @@ -509,7 +510,8 @@ static int cromfs_compare_node(FAR const struct cromfs_volume_s *fs, name = (FAR char *)cromfs_offset2addr(fs, node->cn_name); namlen = strlen(name); - finfo("Compare %s to %s[0-%u]\n", name, cpnode->segment, cpnode->seglen); + finfo("Compare %s to %s[0-%" PRIu16 "]\n", name, cpnode->segment, + cpnode->seglen); /* If the lengths of the name does not match the length of the next path * segment, then this is not the node we are looking for. @@ -952,8 +954,8 @@ static ssize_t cromfs_read(FAR struct file *filep, FAR char *buffer, src = (FAR const uint8_t *)currhdr + LZF_TYPE0_HDR_SIZE; memcpy(dest, &src[copyoffs], copysize); - finfo("blkoffs=%lu ulen=%u copysize=%u\n", - (unsigned long)blkoffs, ulen, copysize); + finfo("blkoffs=%" PRIu32 " ulen=%" PRIu16 " copysize=%u\n", + blkoffs, ulen, copysize); } else { @@ -986,10 +988,9 @@ static ssize_t cromfs_read(FAR struct file *filep, FAR char *buffer, ff->ff_ulen = decomplen; } - finfo( - "voloffs=%lu blkoffs=%lu ulen=%u ff_offset=%u copysize=%u\n", - (unsigned long)voloffs, (unsigned long)blkoffs, ulen, - ff->ff_offset, copysize); + finfo("voloffs=%" PRIu32 " blkoffs=%" PRIu32 + " ulen=%" PRIu16 " ff_offset=%" PRIu32 " copysize=%u\n", + voloffs, blkoffs, ulen, ff->ff_offset, copysize); DEBUGASSERT(ff->ff_ulen >= copysize); } else @@ -1025,10 +1026,11 @@ static ssize_t cromfs_read(FAR struct file *filep, FAR char *buffer, ff->ff_ulen = decomplen; } - finfo("voloffs=%lu blkoffs=%lu ulen=%u clen=%u ff_offset=%u " - "copyoffs=%u copysize=%u\n", - (unsigned long)voloffs, (unsigned long)blkoffs, ulen, - clen, ff->ff_offset, copyoffs, copysize); + finfo("voloffs=%" PRIu32 " blkoffs=%" PRIu32 " ulen=%" PRIu16 + " clen=%" PRIu16 " ff_offset=%" PRIu32 + " copyoffs=%u copysize=%u\n", + voloffs, blkoffs, ulen, clen, ff->ff_offset, + copyoffs, copysize); DEBUGASSERT(ff->ff_ulen >= (copyoffs + copysize)); /* Then copy to user buffer */ @@ -1254,7 +1256,7 @@ static int cromfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) * special error -ENOENT */ - finfo("Entry %d: End of directory\n", offset); + finfo("Entry %" PRIu32 ": End of directory\n", offset); return -ENOENT; } @@ -1269,7 +1271,7 @@ static int cromfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) * special error -ENOENT */ - finfo("Entry %d: End of directory\n", offset); + finfo("Entry %" PRIu32 ": End of directory\n", offset); return -ENOENT; } @@ -1284,7 +1286,7 @@ static int cromfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) /* Save the filename and file type */ name = (FAR char *)cromfs_offset2addr(fs, node->cn_name); - finfo("Entry %lu: %s\n", (unsigned long)offset, name); + finfo("Entry %" PRIu32 ": %s\n", offset, name); strncpy(dir->fd_dir.d_name, name, NAME_MAX); switch (node->cn_mode & S_IFMT) diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig index 710d634d5c1..27ebb018bd7 100644 --- a/fs/fat/Kconfig +++ b/fs/fat/Kconfig @@ -12,6 +12,18 @@ config FS_FAT if FS_FAT +config FAT_COMPUTE_FSINFO + bool "FAT compute free space in FSINFO at mount time" + default n + ---help--- + Enables the computation of free clusters at mount time as suggested by the + white paper for FAT. The standard behavior of NuttX is to trust the stored + value and only recompute it once required. This works if the file system + is never mounted to another OS. SD-cards which are mounted to Windows to + modify the content might report wrong space after reinserting it to NuttX. + It is recommended to activate this setting if the "SD-Card" is swapped + between systems. + config FAT_LCNAMES bool "FAT upper/lower names" default n diff --git a/fs/fat/fs_fat32.h b/fs/fat/fs_fat32.h index 5858aedf6b3..70e958ee13a 100644 --- a/fs/fat/fs_fat32.h +++ b/fs/fat/fs_fat32.h @@ -1082,6 +1082,7 @@ EXTERN int fat_ffcacheinvalidate(struct fat_mountpt_s *fs, /* FSINFO sector support */ EXTERN int fat_updatefsinfo(struct fat_mountpt_s *fs); +EXTERN int fat_computefreeclusters(struct fat_mountpt_s *fs); EXTERN int fat_nfreeclusters(struct fat_mountpt_s *fs, off_t *pfreeclusters); EXTERN int fat_currentsector(struct fat_mountpt_s *fs, diff --git a/fs/fat/fs_fat32attrib.c b/fs/fat/fs_fat32attrib.c index 76ebe160fb2..79df97df27f 100644 --- a/fs/fat/fs_fat32attrib.c +++ b/fs/fat/fs_fat32attrib.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/fs/fat/fs_fat32util.c b/fs/fat/fs_fat32util.c index 1b758e87a70..d24d8fec08b 100644 --- a/fs/fat/fs_fat32util.c +++ b/fs/fat/fs_fat32util.c @@ -633,6 +633,16 @@ int fat_mount(struct fat_mountpt_s *fs, bool writeable) } } + /* Enforce computation of free clusters if configured */ + +#ifdef CONFIG_FAT_COMPUTE_FSINFO + ret = fat_computefreeclusters(fs); + if (ret != OK) + { + goto errout_with_buffer; + } +#endif + /* We did it! */ finfo("FAT%d:\n", fs->fs_type == 0 ? 12 : fs->fs_type == 1 ? 16 : 32); @@ -1142,7 +1152,7 @@ int fat_removechain(struct fat_mountpt_s *fs, uint32_t cluster) if (fs->fs_fsifreecount != 0xffffffff) { fs->fs_fsifreecount++; - fs->fs_fsidirty = 1; + fs->fs_fsidirty = true; } /* Then set up to remove the next cluster */ @@ -1308,7 +1318,7 @@ int32_t fat_extendchain(struct fat_mountpt_s *fs, uint32_t cluster) if (fs->fs_fsifreecount != 0xffffffff) { fs->fs_fsifreecount--; - fs->fs_fsidirty = 1; + fs->fs_fsidirty = true; } /* Return then number of the new cluster that was added to the chain */ @@ -2019,30 +2029,18 @@ int fat_updatefsinfo(struct fat_mountpt_s *fs) } /**************************************************************************** - * Name: fat_nfreeclusters + * Name: fat_computefreeclusters * * Description: - * Get the number of free clusters + * Compute the number of free clusters from scratch * ****************************************************************************/ -int fat_nfreeclusters(struct fat_mountpt_s *fs, off_t *pfreeclusters) +int fat_computefreeclusters(struct fat_mountpt_s *fs) { - uint32_t nfreeclusters; + /* We have to count the number of free clusters */ - /* If number of the first free cluster is valid, then just return that - * value. - */ - - if (fs->fs_fsifreecount <= fs->fs_nclusters - 2) - { - *pfreeclusters = fs->fs_fsifreecount; - return OK; - } - - /* Otherwise, we will have to count the number of free clusters */ - - nfreeclusters = 0; + uint32_t nfreeclusters = 0; if (fs->fs_type == FSTYPE_FAT12) { off_t sector; @@ -2052,7 +2050,7 @@ int fat_nfreeclusters(struct fat_mountpt_s *fs, off_t *pfreeclusters) for (sector = 2; sector < fs->fs_nclusters; sector++) { /* If the cluster is unassigned, then increment the count of free - * clusters. + * clusters */ if ((uint16_t)fat_getcluster(fs, sector) == 0) @@ -2076,12 +2074,12 @@ int fat_nfreeclusters(struct fat_mountpt_s *fs, off_t *pfreeclusters) for (cluster = fs->fs_nclusters; cluster > 0; cluster--) { /* If we are starting a new sector, then read the new sector in - * fs_buffer. + * fs_buffer */ if (offset >= fs->fs_hwsectorsize) { - ret = fat_fscacheread(fs, fatsector++); + ret = fat_fscacheread(fs, fatsector); if (ret < 0) { return ret; @@ -2126,7 +2124,6 @@ int fat_nfreeclusters(struct fat_mountpt_s *fs, off_t *pfreeclusters) fs->fs_fsidirty = true; } - *pfreeclusters = nfreeclusters; return OK; } @@ -2134,6 +2131,37 @@ int fat_nfreeclusters(struct fat_mountpt_s *fs, off_t *pfreeclusters) * Name: fat_nfreeclusters * * Description: + * Get the number of free clusters + * + ****************************************************************************/ + +int fat_nfreeclusters(struct fat_mountpt_s *fs, off_t *pfreeclusters) +{ + /* If number of the first free cluster is valid, then just return that + * value. + */ + + if (fs->fs_fsifreecount <= fs->fs_nclusters - 2) + { + *pfreeclusters = fs->fs_fsifreecount; + return OK; + } + + /* Otherwise, we will have to compute the number of free clusters */ + + int ret = fat_computefreeclusters(fs); + if (ret == OK) + { + *pfreeclusters = fs->fs_fsifreecount; + } + + return ret; +} + +/**************************************************************************** + * Name: fat_currentsector + * + * Description: * Given the file position, set the correct current sector to access. * ****************************************************************************/ @@ -2142,6 +2170,7 @@ int fat_currentsector(struct fat_mountpt_s *fs, struct fat_file_s *ff, off_t position) { int sectoroffset; + off_t cluster_start_sector; if (position <= ff->ff_size) { @@ -2149,12 +2178,18 @@ int fat_currentsector(struct fat_mountpt_s *fs, struct fat_file_s *ff, sectoroffset = SEC_NSECTORS(fs, position) & CLUS_NDXMASK(fs); - /* The current cluster is the first sector of the cluster plus + /* The current sector is the first sector of the cluster plus * the sector offset */ - ff->ff_currentsector = fat_cluster2sector(fs, ff->ff_currentcluster) - + sectoroffset; + cluster_start_sector = fat_cluster2sector(fs, ff->ff_currentcluster); + + if (cluster_start_sector < 0) + { + return cluster_start_sector; + } + + ff->ff_currentsector = cluster_start_sector + sectoroffset; /* The remainder is the number of sectors left in the cluster to be * read/written diff --git a/fs/hostfs/hostfs_rpmsg.c b/fs/hostfs/hostfs_rpmsg.c index 8b75610c3b6..0b724e5dad7 100644 --- a/fs/hostfs/hostfs_rpmsg.c +++ b/fs/hostfs/hostfs_rpmsg.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/fs/hostfs/hostfs_rpmsg_server.c b/fs/hostfs/hostfs_rpmsg_server.c index 830cd0f0951..d7ea8190f99 100644 --- a/fs/hostfs/hostfs_rpmsg_server.c +++ b/fs/hostfs/hostfs_rpmsg_server.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/fs/inode/fs_files.c b/fs/inode/fs_files.c index 838dcbddb4b..50ec037b780 100644 --- a/fs/inode/fs_files.c +++ b/fs/inode/fs_files.c @@ -25,7 +25,6 @@ #include #include -#include #include #include #include diff --git a/fs/inode/fs_inodegetpath.c b/fs/inode/fs_inodegetpath.c index a1a909fe535..4c4a163d668 100644 --- a/fs/inode/fs_inodegetpath.c +++ b/fs/inode/fs_inodegetpath.c @@ -53,7 +53,7 @@ int inode_getpath(FAR struct inode *node, FAR char *path) path[0] = '\0'; return OK; } - else if (node->i_parent) + else if (node->i_parent != NULL) { int ret = inode_getpath(node->i_parent, path); if (ret < 0) diff --git a/fs/inode/fs_inoderelease.c b/fs/inode/fs_inoderelease.c index 85eca493e44..33d06c0cddc 100644 --- a/fs/inode/fs_inoderelease.c +++ b/fs/inode/fs_inoderelease.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/fs/inode/fs_inoderemove.c b/fs/inode/fs_inoderemove.c index db7c91c5c24..a9ce4cc0d5c 100644 --- a/fs/inode/fs_inoderemove.c +++ b/fs/inode/fs_inoderemove.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/fs/littlefs/Make.defs b/fs/littlefs/Make.defs index c9282abafbd..ad81711a174 100644 --- a/fs/littlefs/Make.defs +++ b/fs/littlefs/Make.defs @@ -36,6 +36,7 @@ CFLAGS += -DLFS_DEBUG=finfo CFLAGS += -DLFS_WARN=fwarn CFLAGS += -DLFS_ERROR=ferr CFLAGS += -DLFS_ASSERT=DEBUGASSERT +CFLAGS += -DLFS_CONFIG=../lfs_vfs.h LITTLEFS_VERSION ?= 2.4.0 LITTLEFS_TARBALL = v$(LITTLEFS_VERSION).tar.gz diff --git a/fs/littlefs/lfs_vfs.h b/fs/littlefs/lfs_vfs.h new file mode 100644 index 00000000000..7b621e6f06e --- /dev/null +++ b/fs/littlefs/lfs_vfs.h @@ -0,0 +1,29 @@ +/**************************************************************************** + * fs/littlefs/lfs_vfs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#undef LFS_CONFIG +#undef LFS_UTIL_H + +#include +#include "littlefs/lfs_util.h" diff --git a/fs/mmap/fs_mmap.c b/fs/mmap/fs_mmap.c index baab91f4871..c764af29bfa 100644 --- a/fs/mmap/fs_mmap.c +++ b/fs/mmap/fs_mmap.c @@ -37,10 +37,156 @@ #include "inode/inode.h" #include "fs_rammap.h" +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: file_mmap_ + ****************************************************************************/ + +static int file_mmap_(FAR struct file *filep, FAR void *start, + size_t length, int prot, int flags, + off_t offset, bool kernel, FAR void **mapped) +{ + FAR void *addr; + int ret; + + /* Since only a tiny subset of mmap() functionality, we have to verify many + * things. + */ + +#ifdef CONFIG_DEBUG_FEATURES + /* Fixed mappings and protections are not currently supported. These + * options could be supported in the KERNEL build with an MMU, but that + * logic is not in place. + */ + + if ((flags & (MAP_FIXED | MAP_DENYWRITE)) != 0) + { + ferr("ERROR: Unsupported options, prot=%x flags=%04x\n", prot, flags); + return -ENOSYS; + } + +#ifndef CONFIG_FS_RAMMAP + if ((flags & MAP_PRIVATE) != 0) + { + ferr("ERROR: MAP_PRIVATE is not supported without file mapping" + "emulation\n"); + return -ENOSYS; + } +#endif /* CONFIG_FS_RAMMAP */ + + /* A length of 0 is invalid. */ + + if (length == 0) + { + ferr("ERROR: Invalid length, length=%zu\n", length); + return -EINVAL; + } +#endif /* CONFIG_DEBUG_FEATURES */ + + if ((filep->f_oflags & O_WROK) == 0 && prot == PROT_WRITE && + (flags & MAP_SHARED) != 0) + { + ferr("ERROR: Unsupported options for read-only file descriptor," + "prot=%x flags=%04x\n", prot, flags); + return -EACCES; + } + + if ((filep->f_oflags & O_RDOK) == 0) + { + ferr("ERROR: File descriptor does not have read permission\n"); + return -EACCES; + } + + /* Check if we are just be asked to allocate memory, i.e., MAP_ANONYMOUS + * set meaning that the memory is not backed up from a file. The file + * descriptor should be -1 (or refer to opened /dev/zero) in this case. + * The file descriptor is ignored in either case. + */ + + if ((flags & MAP_ANONYMOUS) != 0) + { + /* REVISIT: Should reside outside of the heap. That is really the + * only purpose of MAP_ANONYMOUS: To get non-heap memory. In KERNEL + * build, this could be accomplished using pgalloc(), provided that + * you had logic in place to assign a virtual address to the mapping. + */ + + *mapped = kernel ? kmm_zalloc(length) : kumm_zalloc(length); + if (*mapped == NULL) + { + ferr("ERROR: kumm_alloc() failed: %d\n", ret); + return -ENOMEM; + } + + return OK; + } + + if ((flags & MAP_PRIVATE) != 0) + { +#ifdef CONFIG_FS_RAMMAP + /* Allocate memory and copy the file into memory. We would, of course, + * do much better in the KERNEL build using the MMU. + */ + + return rammap(filep, length, offset, kernel, mapped); +#endif + } + + /* Perform the ioctl to get the base address of the file in 'mapped' + * in memory. (casting to uintptr_t first eliminates complaints on some + * architectures where the sizeof long is different from the size of + * a pointer). + */ + + ret = file_ioctl(filep, FIOC_MMAP, (unsigned long)((uintptr_t)&addr)); + if (ret < 0) + { + /* Not directly mappable, probably because the underlying media does + * not support random access. + */ + +#ifdef CONFIG_FS_RAMMAP + /* Allocate memory and copy the file into memory. We would, of course, + * do much better in the KERNEL build using the MMU. + */ + + return rammap(filep, length, offset, kernel, mapped); +#else + ferr("ERROR: file_ioctl(FIOC_MMAP) failed: %d\n", ret); + return ret; +#endif + } + + /* Return the offset address */ + + *mapped = (FAR void *)(((FAR uint8_t *)addr) + offset); + return OK; +} + /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: file_mmap + * + * Description: + * Equivalent to the standard mmap() function except that is accepts + * a struct file instance instead of a file descriptor and it does not set + * the errno variable. + * + ****************************************************************************/ + +int file_mmap(FAR struct file *filep, FAR void *start, size_t length, + int prot, int flags, off_t offset, FAR void **mapped) +{ + return file_mmap_(filep, start, length, + prot, flags, offset, true, mapped); +} + /**************************************************************************** * Name: mmap * @@ -118,47 +264,10 @@ FAR void *mmap(FAR void *start, size_t length, int prot, int flags, int fd, off_t offset) { - FAR void *addr; FAR struct file *filep; + FAR void *mapped; int ret; - /* Since only a tiny subset of mmap() functionality, we have to verify many - * things. - */ - -#ifdef CONFIG_DEBUG_FEATURES - /* Fixed mappings and protections are not currently supported. These - * options could be supported in the KERNEL build with an MMU, but that - * logic is not in place. - */ - - if ((flags & (MAP_FIXED | MAP_DENYWRITE)) != 0) - { - ferr("ERROR: Unsupported options, prot=%x flags=%04x\n", prot, flags); - ret = -ENOSYS; - goto errout; - } - -#ifndef CONFIG_FS_RAMMAP - if ((flags & MAP_PRIVATE) != 0) - { - ferr("ERROR: MAP_PRIVATE is not supported without file mapping" - "emulation\n"); - ret = -ENOSYS; - goto errout; - } -#endif /* CONFIG_FS_RAMMAP */ - - /* A length of 0 is invalid. */ - - if (length == 0) - { - ferr("ERROR: Invalid length, length=%zu\n", length); - ret = -EINVAL; - goto errout; - } -#endif /* CONFIG_DEBUG_FEATURES */ - if (fs_getfilep(fd, &filep) < 0) { ferr("ERROR: Invalid file descriptor, fd=%d\n", fd); @@ -166,89 +275,14 @@ FAR void *mmap(FAR void *start, size_t length, int prot, int flags, goto errout; } - if ((filep->f_oflags & O_WROK) == 0 && prot == PROT_WRITE && - (flags & MAP_SHARED) != 0) - { - ferr("ERROR: Unsupported options for read-only file descriptor," - "fd=%d prot=%x flags=%04x\n", fd, prot, flags); - ret = -EACCES; - goto errout; - } - - if ((filep->f_oflags & O_RDOK) == 0) - { - ferr("ERROR: File descriptor does not have read permission," - "fd=%d\n", fd); - ret = -EACCES; - goto errout; - } - - /* Check if we are just be asked to allocate memory, i.e., MAP_ANONYMOUS - * set meaning that the memory is not backed up from a file. The file - * descriptor should be -1 (or refer to opened /dev/zero) in this case. - * The file descriptor is ignored in either case. - */ - - if ((flags & MAP_ANONYMOUS) != 0) - { - FAR void *alloc; - - /* REVISIT: Should reside outside of the heap. That is really the - * only purpose of MAP_ANONYMOUS: To get non-heap memory. In KERNEL - * build, this could be accomplished using pgalloc(), provided that - * you had logic in place to assign a virtual address to the mapping. - */ - - alloc = kumm_zalloc(length); - if (alloc == NULL) - { - ferr("ERROR: kumm_alloc() failed: %d\n", ret); - ret = -ENOMEM; - goto errout; - } - - return alloc; - } - - if ((flags & MAP_PRIVATE) != 0) - { -#ifdef CONFIG_FS_RAMMAP - /* Allocate memory and copy the file into memory. We would, of course, - * do much better in the KERNEL build using the MMU. - */ - - return rammap(fd, length, offset); -#endif - } - - /* Perform the ioctl to get the base address of the file in 'mapped' - * in memory. (casting to uintptr_t first eliminates complaints on some - * architectures where the sizeof long is different from the size of - * a pointer). - */ - - ret = nx_ioctl(fd, FIOC_MMAP, (unsigned long)((uintptr_t)&addr)); + ret = file_mmap_(filep, start, length, + prot, flags, offset, false, &mapped); if (ret < 0) { - /* Not directly mappable, probably because the underlying media does - * not support random access. - */ - -#ifdef CONFIG_FS_RAMMAP - /* Allocate memory and copy the file into memory. We would, of course, - * do much better in the KERNEL build using the MMU. - */ - - return rammap(fd, length, offset); -#else - ferr("ERROR: nx_ioctl(FIOC_MMAP) failed: %d\n", ret); goto errout; -#endif } - /* Return the offset address */ - - return (FAR void *)(((FAR uint8_t *)addr) + offset); + return mapped; errout: set_errno(-ret); diff --git a/fs/mmap/fs_munmap.c b/fs/mmap/fs_munmap.c index bb4f1271e92..9ef45f44142 100644 --- a/fs/mmap/fs_munmap.c +++ b/fs/mmap/fs_munmap.c @@ -37,10 +37,149 @@ #include "inode/inode.h" #include "fs_rammap.h" +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int file_munmap_(FAR void *start, size_t length, bool kernel) +{ +#ifdef CONFIG_FS_RAMMAP + FAR struct fs_rammap_s *prev; + FAR struct fs_rammap_s *curr; + FAR void *newaddr; + unsigned int offset; + int ret; + + /* Find a region containing this start and length in the list of regions */ + + ret = nxsem_wait(&g_rammaps.exclsem); + if (ret < 0) + { + return ret; + } + + /* Search the list of regions */ + + for (prev = NULL, curr = g_rammaps.head; curr; + prev = curr, curr = curr->flink) + { + /* Does this region include any part of the specified range? */ + + if ((uintptr_t)start < (uintptr_t)curr->addr + curr->length && + (uintptr_t)start + length >= (uintptr_t)curr->addr) + { + break; + } + } + + /* Did we find the region */ + + if (!curr) + { + ferr("ERROR: Region not found\n"); + ret = -EINVAL; + goto errout_with_semaphore; + } + + /* Get the offset from the beginning of the region and the actual number + * of bytes to "unmap". All mappings must extend to the end of the region. + * There is no support for free a block of memory but leaving a block of + * memory at the end. This is a consequence of using kumm_realloc() to + * simulate the unmapping. + */ + + offset = start - curr->addr; + if (offset + length < curr->length) + { + ferr("ERROR: Cannot umap without unmapping to the end\n"); + ret = -ENOSYS; + goto errout_with_semaphore; + } + + /* Okay.. the region is beging umapped to the end. Make sure the length + * indicates that. + */ + + length = curr->length - offset; + + /* Are we unmapping the entire region (offset == 0)? */ + + if (length >= curr->length) + { + /* Yes.. remove the mapping from the list */ + + if (prev) + { + prev->flink = curr->flink; + } + else + { + g_rammaps.head = curr->flink; + } + + /* Then free the region */ + + if (curr->kernel) + { + kmm_free(curr) + } + else + { + kumm_free(curr); + } + } + + /* No.. We have been asked to "unmap' only a portion of the memory + * (offset > 0). + */ + + else + { + if (kernel) + { + newaddr = kmm_realloc(curr->addr, + sizeof(struct fs_rammap_s) + length); + } + else + { + newaddr = kumm_realloc(curr->addr, + sizeof(struct fs_rammap_s) + length); + } + + DEBUGASSERT(newaddr == (FAR void *)(curr->addr)); + UNUSED(newaddr); /* May not be used */ + curr->length = length; + } + + nxsem_post(&g_rammaps.exclsem); + return OK; + +errout_with_semaphore: + nxsem_post(&g_rammaps.exclsem); + return ret; +#else + return OK; +#endif /* CONFIG_FS_RAMMAP */ +} + /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: file_mummap + * + * Description: + * Equivalent to the standard file_mummap() function except it does not set + * the errno variable. + * + ****************************************************************************/ + +int file_munmap(FAR void *start, size_t length) +{ + return file_munmap_(start, length, true); +} + /**************************************************************************** * Name: munmap * @@ -93,110 +232,14 @@ int munmap(FAR void *start, size_t length) { -#ifdef CONFIG_FS_RAMMAP - FAR struct fs_rammap_s *prev; - FAR struct fs_rammap_s *curr; - FAR void *newaddr; - unsigned int offset; int ret; - int errcode; - /* Find a region containing this start and length in the list of regions */ - - ret = nxsem_wait(&g_rammaps.exclsem); + ret = file_munmap_(start, length, false); if (ret < 0) { - errcode = ret; - goto errout; + set_errno(-ret); + ret = ERROR; } - /* Search the list of regions */ - - for (prev = NULL, curr = g_rammaps.head; curr; - prev = curr, curr = curr->flink) - { - /* Does this region include any part of the specified range? */ - - if ((uintptr_t)start < (uintptr_t)curr->addr + curr->length && - (uintptr_t)start + length >= (uintptr_t)curr->addr) - { - break; - } - } - - /* Did we find the region */ - - if (!curr) - { - ferr("ERROR: Region not found\n"); - errcode = EINVAL; - goto errout_with_semaphore; - } - - /* Get the offset from the beginning of the region and the actual number - * of bytes to "unmap". All mappings must extend to the end of the region. - * There is no support for free a block of memory but leaving a block of - * memory at the end. This is a consequence of using kumm_realloc() to - * simulate the unmapping. - */ - - offset = start - curr->addr; - if (offset + length < curr->length) - { - ferr("ERROR: Cannot umap without unmapping to the end\n"); - errcode = ENOSYS; - goto errout_with_semaphore; - } - - /* Okay.. the region is beging umapped to the end. Make sure the length - * indicates that. - */ - - length = curr->length - offset; - - /* Are we unmapping the entire region (offset == 0)? */ - - if (length >= curr->length) - { - /* Yes.. remove the mapping from the list */ - - if (prev) - { - prev->flink = curr->flink; - } - else - { - g_rammaps.head = curr->flink; - } - - /* Then free the region */ - - kumm_free(curr); - } - - /* No.. We have been asked to "unmap' only a portion of the memory - * (offset > 0). - */ - - else - { - newaddr = kumm_realloc(curr->addr, - sizeof(struct fs_rammap_s) + length); - DEBUGASSERT(newaddr == (FAR void *)(curr->addr)); - UNUSED(newaddr); /* May not be used */ - curr->length = length; - } - - nxsem_post(&g_rammaps.exclsem); - return OK; - -errout_with_semaphore: - nxsem_post(&g_rammaps.exclsem); - -errout: - set_errno(errcode); - return ERROR; -#else - return OK; -#endif /* CONFIG_FS_RAMMAP */ + return ret; } diff --git a/fs/mmap/fs_rammap.c b/fs/mmap/fs_rammap.c index ca525432399..30f5d610a96 100644 --- a/fs/mmap/fs_rammap.c +++ b/fs/mmap/fs_rammap.c @@ -62,14 +62,15 @@ struct fs_allmaps_s g_rammaps = * Support simulation of memory mapped files by copying files into RAM. * * Input Parameters: - * fd file descriptor of the backing file -- required. + * filep file descriptor of the backing file -- required. * length The length of the mapping. For exception #1 above, this length * ignored: The entire underlying media is always accessible. * offset The offset into the file to map + * kernel kmm_zalloc or kumm_zalloc + * mapped The pointer to the mapped area * * Returned Value: - * On success, rammmap() returns a pointer to the mapped area. On error, - * the value MAP_FAILED is returned, and errno is set appropriately. + * On success, rammmap returns 0. Otherwise errno is returned appropriately. * * EBADF * 'fd' is not a valid file descriptor. @@ -80,7 +81,8 @@ struct fs_allmaps_s g_rammaps = * ****************************************************************************/ -FAR void *rammap(int fd, size_t length, off_t offset) +int rammap(FAR struct file *filep, size_t length, + off_t offset, bool kernel, FAR void **mapped) { FAR struct fs_rammap_s *map; FAR uint8_t *alloc; @@ -104,12 +106,13 @@ FAR void *rammap(int fd, size_t length, off_t offset) /* Allocate a region of memory of the specified size */ - alloc = (FAR uint8_t *)kumm_malloc(sizeof(struct fs_rammap_s) + length); + alloc = (FAR uint8_t *)kernel ? + kmm_malloc(sizeof(struct fs_rammap_s) + length); + kumm_malloc(sizeof(struct fs_rammap_s) + length); if (!alloc) { ferr("ERROR: Region allocation failed, length: %d\n", (int)length); - ret = -ENOMEM; - goto errout; + return -ENOMEM; } /* Initialize the region */ @@ -122,9 +125,13 @@ FAR void *rammap(int fd, size_t length, off_t offset) /* Seek to the specified file offset */ - fpos = nx_seek(fd, offset, SEEK_SET); + fpos = file_seek(filep, offset, SEEK_SET); if (fpos < 0) { + /* Seek failed... errno has already been set, but EINVAL is probably + * the correct response. + */ + ferr("ERROR: Seek to position %d failed\n", (int)offset); ret = fpos; goto errout_with_region; @@ -135,7 +142,7 @@ FAR void *rammap(int fd, size_t length, off_t offset) rdbuffer = map->addr; while (length > 0) { - nread = nx_read(fd, rdbuffer, length); + nread = file_read(filep, rdbuffer, length); if (nread < 0) { /* Handle the special case where the read was interrupted by a @@ -183,14 +190,20 @@ FAR void *rammap(int fd, size_t length, off_t offset) g_rammaps.head = map; nxsem_post(&g_rammaps.exclsem); - return map->addr; + *mapped = map->addr; + return OK; errout_with_region: - kumm_free(alloc); + if (kernel) + { + kmm_free(alloc); + } + else + { + kumm_free(alloc); + } -errout: - set_errno(-ret); - return MAP_FAILED; + return ret; } #endif /* CONFIG_FS_RAMMAP */ diff --git a/fs/mmap/fs_rammap.h b/fs/mmap/fs_rammap.h index fc8a6c9b117..ec4fbbc87c7 100644 --- a/fs/mmap/fs_rammap.h +++ b/fs/mmap/fs_rammap.h @@ -81,22 +81,6 @@ extern struct fs_allmaps_s g_rammaps; * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: rammap_initialize - * - * Description: - * Verified that this capability has been initialized. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rammap_initialize(void); - /**************************************************************************** * Name: rammmap * @@ -104,14 +88,15 @@ void rammap_initialize(void); * Support simulation of memory mapped files by copying files into RAM. * * Input Parameters: - * fd file descriptor of the backing file -- required. + * filep file descriptor of the backing file -- required. * length The length of the mapping. For exception #1 above, this length * ignored: The entire underlying media is always accessible. * offset The offset into the file to map + * kernel kmm_zalloc or kumm_zalloc + * mapped The pointer to the mapped area * * Returned Value: - * On success, rammmap() returns a pointer to the mapped area. On error, - * the value MAP_FAILED is returned, and errno is set appropriately. + * On success rammmap returns 0. Otherwise errno is returned appropriately. * * EBADF * 'fd' is not a valid file descriptor. @@ -122,7 +107,8 @@ void rammap_initialize(void); * ****************************************************************************/ -FAR void *rammap(int fd, size_t length, off_t offset); +int rammap(FAR struct file *filep, size_t length, + off_t offset, bool kernel, FAR void **mapped); #endif /* CONFIG_FS_RAMMAP */ #endif /* __FS_MMAP_RAMMAP_H */ diff --git a/fs/mqueue/mq_open.c b/fs/mqueue/mq_open.c index dbe75d6da77..2eadefd179e 100644 --- a/fs/mqueue/mq_open.c +++ b/fs/mqueue/mq_open.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/fs/nfs/nfs_util.c b/fs/nfs/nfs_util.c index 452d36cfc95..d7137f99b54 100644 --- a/fs/nfs/nfs_util.c +++ b/fs/nfs/nfs_util.c @@ -128,7 +128,32 @@ int nfs_request(FAR struct nfsmount *nmp, int procnum, if (error != 0) { ferr("ERROR: rpcclnt_request failed: %d\n", error); - return error; + + if (error != -ENOTCONN) + { + return error; + } + + /* Reconnect */ + + finfo("Reconnect due to timeout \n"); + + error = rpcclnt_connect(nmp->nm_rpcclnt); + + if (error != 0) + { + return error; + } + + /* Send the request again */ + + error = rpcclnt_request(clnt, procnum, NFS_PROG, NFS_VER3, + request, reqlen, response, resplen); + + if (error != 0) + { + return error; + } } memcpy(&replyh, response, sizeof(struct nfs_reply_header)); diff --git a/fs/nfs/rpc_clnt.c b/fs/nfs/rpc_clnt.c index f57fed23bf0..cdc029dc251 100644 --- a/fs/nfs/rpc_clnt.c +++ b/fs/nfs/rpc_clnt.c @@ -241,28 +241,31 @@ static int rpcclnt_socket(FAR struct rpcclnt *rpc, in_port_t rport) goto bad; } - /* Some servers require that the client port be a reserved port - * number. We always allocate a reserved port, as this prevents - * filehandle disclosure through UDP port capture. - */ - - do + if (rpc->rc_sotype == SOCK_DGRAM) { - *lport = htons(--port); - error = psock_bind(&rpc->rc_so, (FAR struct sockaddr *)&laddr, - addrlen); - if (error < 0) + /* Some servers require that the client port be a reserved port + * number. We always allocate a reserved port, as this prevents + * filehandle disclosure through UDP port capture. + */ + + do + { + *lport = htons(--port); + error = psock_bind(&rpc->rc_so, (FAR struct sockaddr *)&laddr, + addrlen); + if (error < 0) + { + ferr("ERROR: psock_bind failed: %d\n", error); + } + } + while (error == -EADDRINUSE && port >= 512); + + if (error) { ferr("ERROR: psock_bind failed: %d\n", error); + goto bad; } } - while (error == -EADDRINUSE && port >= 512); - - if (error) - { - ferr("ERROR: psock_bind failed: %d\n", error); - goto bad; - } /* Protocols that do not require connections could be optionally left * unconnected. That would allow servers to reply from a port other than @@ -297,32 +300,49 @@ bad: static int rpcclnt_send(FAR struct rpcclnt *rpc, FAR void *call, int reqlen) { + struct iovec iov[2]; + struct msghdr msg; uint32_t mark; int ret = OK; - /* Send the record marking(RM) for stream only */ - if (rpc->rc_sotype == SOCK_STREAM) { - mark = txdr_unsigned(0x80000000 | reqlen); - ret = psock_send(&rpc->rc_so, &mark, sizeof(mark), 0); - if (ret < 0) - { - ferr("ERROR: psock_send mark failed: %d\n", ret); - return ret; - } + /* Prepare the record marking(RM) and compose an RPC request + * NOTE: Sending a separate packet does not work with Linux host + */ + + mark = txdr_unsigned(0x80000000 | (reqlen)); + + iov[0].iov_base = (FAR void *)&mark; + iov[0].iov_len = sizeof(mark); + iov[1].iov_base = (FAR void *)call; + iov[1].iov_len = reqlen; + + msg.msg_name = NULL; + msg.msg_namelen = 0; + msg.msg_iov = iov; + msg.msg_iovlen = 2; + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags = 0; + + ret = psock_sendmsg(&rpc->rc_so, &msg, 0); + ferr("ERROR: psock_sendmsg request failed: %d\n", ret); + } + else + { + /* Send the call message + * + * On success, psock_send returns the number of bytes sent; + * On failure, it returns a negated errno value. + */ + + ret = psock_send(&rpc->rc_so, call, reqlen, 0); + ferr("ERROR: psock_send request failed: %d\n", ret); } - /* Send the call message - * - * On success, psock_send returns the number of bytes sent; - * On failure, it returns a negated errno value. - */ - - ret = psock_send(&rpc->rc_so, call, reqlen, 0); if (ret < 0) { - ferr("ERROR: psock_send request failed: %d\n", ret); return ret; } @@ -342,6 +362,7 @@ static int rpcclnt_receive(FAR struct rpcclnt *rpc, { uint32_t mark; int error = 0; + int offset = 0; /* Receive the record marking(RM) for stream only */ @@ -371,12 +392,20 @@ static int rpcclnt_receive(FAR struct rpcclnt *rpc, resplen = mark; } - error = psock_recv(&rpc->rc_so, reply, resplen, 0); - if (error < 0) + do { - ferr("ERROR: psock_recv response failed: %d\n", error); - return error; + error = psock_recv(&rpc->rc_so, reply + offset, resplen, 0); + + if (error < 0) + { + ferr("ERROR: psock_recv response failed: %d\n", error); + return error; + } + + resplen -= error; + offset += error; } + while (rpc->rc_sotype == SOCK_STREAM && resplen != 0); return OK; } diff --git a/fs/procfs/Kconfig b/fs/procfs/Kconfig index 5ce77fc79fb..f0bd7a60851 100644 --- a/fs/procfs/Kconfig +++ b/fs/procfs/Kconfig @@ -21,6 +21,12 @@ config FS_PROCFS_REGISTER Support run-time registration of the new entries in the procfs file system. +config FS_PROCFS_MAX_TASKS + int "The maxinum number of active tasks for procfs snapshot" + default 128 + ---help--- + The maxinum number of active tasks for procfs snapshot. + menu "Exclude individual procfs entries" config FS_PROCFS_EXCLUDE_PROCESS diff --git a/fs/procfs/fs_procfs.c b/fs/procfs/fs_procfs.c index 3376a24e322..6a067d5c782 100644 --- a/fs/procfs/fs_procfs.c +++ b/fs/procfs/fs_procfs.c @@ -279,9 +279,9 @@ struct procfs_level0_s /* Our private data */ - uint8_t lastlen; /* length of last reported static dir */ - pid_t pid[CONFIG_MAX_TASKS]; /* Snapshot of all active task IDs */ - FAR const char *lastread; /* Pointer to last static dir read */ + uint8_t lastlen; /* length of last reported static dir */ + pid_t pid[CONFIG_FS_PROCFS_MAX_TASKS]; /* Snapshot of all active task IDs */ + FAR const char *lastread; /* Pointer to last static dir read */ }; /* Level 1 is an internal virtual directory (such as /proc/fs) which @@ -321,7 +321,10 @@ static void procfs_enum(FAR struct tcb_s *tcb, FAR void *arg) /* Add the PID to the list */ index = dir->base.nentries; - DEBUGASSERT(index < CONFIG_MAX_TASKS); + if (index >= CONFIG_FS_PROCFS_MAX_TASKS) + { + return; + } dir->pid[index] = tcb->pid; dir->base.nentries = index + 1; diff --git a/fs/procfs/fs_procfsiobinfo.c b/fs/procfs/fs_procfsiobinfo.c index fb8baac674e..48d7902444e 100644 --- a/fs/procfs/fs_procfsiobinfo.c +++ b/fs/procfs/fs_procfsiobinfo.c @@ -1,36 +1,20 @@ /**************************************************************************** * fs/procfs/fs_procfsiobinfo.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Anthony Merlino - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -144,7 +128,6 @@ static FAR const char *g_iob_user_names[] = #endif #if defined(CONFIG_NET_TCP) && !defined(NET_TCP_NO_STACK) "tcp_readahead", - "tcp_pendingahead", #endif #ifdef CONFIG_NET_TCP_WRITE_BUFFERS "tcp_writebuffer", @@ -329,10 +312,10 @@ static ssize_t iobinfo_read(FAR struct file *filep, FAR char *buffer, userstats = iob_getuserstats(i); linesize = procfs_snprintf(iobfile->line, IOBINFO_LINELEN, - "%-16s%16lu%16lu\n", - g_iob_user_names[i], - (unsigned long)userstats->totalconsumed, - (unsigned long)userstats->totalproduced); + "%-16s%16lu%16lu\n", + g_iob_user_names[i], + (unsigned long)userstats->totalconsumed, + (unsigned long)userstats->totalproduced); copysize = procfs_memcpy(iobfile->line, linesize, buffer, buflen, &offset); diff --git a/fs/procfs/fs_procfsproc.c b/fs/procfs/fs_procfsproc.c index ef4e72e0771..a75b520b94d 100644 --- a/fs/procfs/fs_procfsproc.c +++ b/fs/procfs/fs_procfsproc.c @@ -475,12 +475,12 @@ static ssize_t proc_status(FAR struct proc_file_s *procfile, /* Show the thread type */ - linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, - "%-12s%s\n", "Type:", - g_ttypenames[(tcb->flags & TCB_FLAG_TTYPE_MASK) - >> TCB_FLAG_TTYPE_SHIFT]); - copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, - &offset); + linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, "%-12s%s\n", + "Type:", + g_ttypenames[(tcb->flags & TCB_FLAG_TTYPE_MASK) + >> TCB_FLAG_TTYPE_SHIFT]); + copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, + &offset); totalsize += copysize; buffer += copysize; @@ -494,8 +494,9 @@ static ssize_t proc_status(FAR struct proc_file_s *procfile, group = tcb->group; DEBUGASSERT(group != NULL); - linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, "%-12s%d\n", "PPID:", - group->tg_ppid); + linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, + "%-12s%d\n", "PPID:", + group->tg_ppid); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -536,8 +537,9 @@ static ssize_t proc_status(FAR struct proc_file_s *procfile, /* Show the thread state */ - linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, "%-12s%s\n", - "State:", g_statenames[tcb->task_state]); + linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, + "%-12s%s\n", "State:", + g_statenames[tcb->task_state]); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -552,14 +554,11 @@ static ssize_t proc_status(FAR struct proc_file_s *procfile, /* Show task flags */ - linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, - "%-12s%c%c%c\n", "Flags:", - tcb->flags & TCB_FLAG_NONCANCELABLE - ? 'N' : '-', - tcb->flags & TCB_FLAG_CANCEL_PENDING - ? 'P' : '-', - tcb->flags & TCB_FLAG_EXIT_PROCESSING - ? 'P' : '-'); + linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, + "%-12s%c%c%c\n", "Flags:", + tcb->flags & TCB_FLAG_NONCANCELABLE ? 'N' : '-', + tcb->flags & TCB_FLAG_CANCEL_PENDING ? 'P' : '-', + tcb->flags & TCB_FLAG_EXIT_PROCESSING ? 'P' : '-'); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -616,8 +615,8 @@ static ssize_t proc_status(FAR struct proc_file_s *procfile, /* Show the signal mask. Note: sigset_t is uint32_t on NuttX. */ linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, - "%-12s%08" PRIx32 "\n", "SigMask:", - tcb->sigprocmask); + "%-12s%08" PRIx32 "\n", + "SigMask:", tcb->sigprocmask); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -928,7 +927,7 @@ static ssize_t proc_stack(FAR struct proc_file_s *procfile, /* Show the stack size */ linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, "%-12s%ld\n", - "StackSize:", (long)tcb->adj_stack_size); + "StackSize:", (long)tcb->adj_stack_size); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -945,7 +944,7 @@ static ssize_t proc_stack(FAR struct proc_file_s *procfile, /* Show the stack size */ linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, "%-12s%ld\n", - "StackUsed:", (long)up_check_tcbstack(tcb)); + "StackUsed:", (long)up_check_tcbstack(tcb)); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -980,7 +979,7 @@ static ssize_t proc_groupstatus(FAR struct proc_file_s *procfile, totalsize = 0; linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, "%-12s%d\n", - "Main task:", group->tg_pid); + "Main task:", group->tg_pid); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -994,7 +993,8 @@ static ssize_t proc_groupstatus(FAR struct proc_file_s *procfile, } linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, - "%-12s0x%02x\n", "Flags:", group->tg_flags); + "%-12s0x%02x\n", + "Flags:", group->tg_flags); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -1115,10 +1115,10 @@ static ssize_t proc_groupfd(FAR struct proc_file_s *procfile, if (file->f_inode && !INODE_IS_SOCKET(file->f_inode)) { linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, - "%3d %8ld %04x\n", - i * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK + - j, (long)file->f_pos, - file->f_oflags); + "%3d %8ld %04x\n", + i * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK + + j, (long)file->f_pos, + file->f_oflags); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -1164,10 +1164,10 @@ static ssize_t proc_groupfd(FAR struct proc_file_s *procfile, { FAR struct socket *socket = file->f_priv; linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, - "%3d %3d %02x", - i * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK + - j, socket->s_type, - socket->s_flags); + "%3d %3d %02x", + i * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK + + j, socket->s_type, + socket->s_flags); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -1236,8 +1236,9 @@ static int proc_groupenv_callback(FAR void *arg, FAR const char *pair) /* Output the header */ - linesize = procfs_snprintf(info->procfile->line, STATUS_LINELEN, - "%s=%s\n", name, value); + linesize = procfs_snprintf(info->procfile->line, + STATUS_LINELEN, "%s=%s\n", + name, value); copysize = procfs_memcpy(info->procfile->line, linesize, info->buffer, info->remaining, &info->offset); diff --git a/fs/procfs/fs_procfsutil.c b/fs/procfs/fs_procfsutil.c index 6e5dd62a9f3..87c91d2c5b4 100644 --- a/fs/procfs/fs_procfsutil.c +++ b/fs/procfs/fs_procfsutil.c @@ -139,11 +139,9 @@ int procfs_snprintf(FAR char *buf, size_t size, { va_list ap; int n; - va_start(ap, format); n = vsnprintf(buf, size, format, ap); va_end(ap); - return n < size - 1 ? n : size - 1; } diff --git a/fs/semaphore/sem_close.c b/fs/semaphore/sem_close.c index 6af20977857..8e5176c701d 100644 --- a/fs/semaphore/sem_close.c +++ b/fs/semaphore/sem_close.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/fs/semaphore/sem_open.c b/fs/semaphore/sem_open.c index 84b274b0ada..11606fdbadb 100644 --- a/fs/semaphore/sem_open.c +++ b/fs/semaphore/sem_open.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/fs/spiffs/src/spiffs_cache.h b/fs/spiffs/src/spiffs_cache.h index 94ec3201cf3..d4fb6f3785e 100644 --- a/fs/spiffs/src/spiffs_cache.h +++ b/fs/spiffs/src/spiffs_cache.h @@ -32,6 +32,7 @@ extern "C" #include +#include #include /**************************************************************************** diff --git a/fs/spiffs/src/spiffs_volume.c b/fs/spiffs/src/spiffs_volume.c index 2f2ca7d30f9..efc6b2ef01c 100644 --- a/fs/spiffs/src/spiffs_volume.c +++ b/fs/spiffs/src/spiffs_volume.c @@ -50,6 +50,7 @@ #include #include #include +#include #include diff --git a/fs/unionfs/fs_unionfs.c b/fs/unionfs/fs_unionfs.c index 22342c8ae1f..d64b194927d 100644 --- a/fs/unionfs/fs_unionfs.c +++ b/fs/unionfs/fs_unionfs.c @@ -2231,7 +2231,7 @@ static int unionfs_mkdir(FAR struct inode *mountpt, FAR const char *relpath, * read-only and the other is write-able? */ - return (ret1 >= 0 || ret2 >= 0) ? OK : ret; + return (ret1 >= 0 || ret2 >= 0) ? OK : ret1; } /**************************************************************************** diff --git a/fs/vfs/fs_close.c b/fs/vfs/fs_close.c index 86b7b656385..139ea2592e7 100644 --- a/fs/vfs/fs_close.c +++ b/fs/vfs/fs_close.c @@ -24,7 +24,9 @@ #include +#include #include +#include #include #include diff --git a/fs/vfs/fs_dup.c b/fs/vfs/fs_dup.c index 8ca557b5293..e815afde964 100644 --- a/fs/vfs/fs_dup.c +++ b/fs/vfs/fs_dup.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/fs/vfs/fs_dup2.c b/fs/vfs/fs_dup2.c index 48f781e81f1..cb075565243 100644 --- a/fs/vfs/fs_dup2.c +++ b/fs/vfs/fs_dup2.c @@ -26,6 +26,7 @@ #include #include +#include #include #include "inode/inode.h" diff --git a/fs/vfs/fs_eventfd.c b/fs/vfs/fs_eventfd.c index 46997506f96..490d2ccb614 100644 --- a/fs/vfs/fs_eventfd.c +++ b/fs/vfs/fs_eventfd.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include diff --git a/fs/vfs/fs_fdopen.c b/fs/vfs/fs_fdopen.c index e2436784da3..b1114a70021 100644 --- a/fs/vfs/fs_fdopen.c +++ b/fs/vfs/fs_fdopen.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/fs/vfs/fs_fstat.c b/fs/vfs/fs_fstat.c index fa9b96ba9f2..ff785e816c3 100644 --- a/fs/vfs/fs_fstat.c +++ b/fs/vfs/fs_fstat.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/fs/vfs/fs_fstatfs.c b/fs/vfs/fs_fstatfs.c index 05c31c75777..d5b31ac400d 100644 --- a/fs/vfs/fs_fstatfs.c +++ b/fs/vfs/fs_fstatfs.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include "inode/inode.h" diff --git a/fs/vfs/fs_ioctl.c b/fs/vfs/fs_ioctl.c index b9e18410264..689a69cd4c6 100644 --- a/fs/vfs/fs_ioctl.c +++ b/fs/vfs/fs_ioctl.c @@ -107,7 +107,7 @@ int file_vioctl(FAR struct file *filep, int req, va_list ap) case FIOC_FILEPATH: if (!INODE_IS_MOUNTPT(inode)) { - ret = inode_getpath(inode, (FAR char *)arg); + ret = inode_getpath(inode, (FAR char *)(uintptr_t)arg); } break; } diff --git a/fs/vfs/fs_read.c b/fs/vfs/fs_read.c index 1c3208fca7d..ba5316d31a2 100644 --- a/fs/vfs/fs_read.c +++ b/fs/vfs/fs_read.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/fs/vfs/fs_rename.c b/fs/vfs/fs_rename.c index 61dbc87cf9e..c180b2b23fd 100644 --- a/fs/vfs/fs_rename.c +++ b/fs/vfs/fs_rename.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -113,6 +114,8 @@ next_subdir: FAR char *subdirname; FAR char *tmp; + inode_release(newinode); + /* Yes.. In this case, the target of the rename must be a * subdirectory of newinode, not the newinode itself. For * example: mv b a/ must move b to a/b. @@ -131,7 +134,6 @@ next_subdir: if (subdir == NULL) { - inode_release(newinode); ret = -ENOMEM; goto errout; } diff --git a/fs/vfs/fs_select.c b/fs/vfs/fs_select.c index 5384f7f78db..1a3734aeffa 100644 --- a/fs/vfs/fs_select.c +++ b/fs/vfs/fs_select.c @@ -90,6 +90,12 @@ int select(int nfds, FAR fd_set *readfds, FAR fd_set *writefds, enter_cancellation_point(); + if (nfds < 0) + { + errcode = EINVAL; + goto errout; + } + /* How many pollfd structures do we need to allocate? */ /* Initialize the descriptor list for poll() */ diff --git a/fs/vfs/fs_stat.c b/fs/vfs/fs_stat.c index 257a9e5f6ac..5d8ffde2632 100644 --- a/fs/vfs/fs_stat.c +++ b/fs/vfs/fs_stat.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include "inode/inode.h" diff --git a/fs/vfs/fs_statfs.c b/fs/vfs/fs_statfs.c index 9c5b6b09e41..94e5835becc 100644 --- a/fs/vfs/fs_statfs.c +++ b/fs/vfs/fs_statfs.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include "inode/inode.h" diff --git a/fs/vfs/fs_symlink.c b/fs/vfs/fs_symlink.c index 5897954631e..07a3f90e1de 100644 --- a/fs/vfs/fs_symlink.c +++ b/fs/vfs/fs_symlink.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/fs/vfs/fs_truncate.c b/fs/vfs/fs_truncate.c index 4968023a92b..17b89edab65 100644 --- a/fs/vfs/fs_truncate.c +++ b/fs/vfs/fs_truncate.c @@ -28,6 +28,7 @@ #include #include #include +#include #include diff --git a/graphics/nxbe/nxbe_cursor.c b/graphics/nxbe/nxbe_cursor.c index 34f75b3639c..a7f7dafbf77 100644 --- a/graphics/nxbe/nxbe_cursor.c +++ b/graphics/nxbe/nxbe_cursor.c @@ -25,6 +25,7 @@ #include #include +#include #include diff --git a/graphics/nxbe/nxbe_setsize.c b/graphics/nxbe/nxbe_setsize.c index cd78635fa7a..5a53dd93f49 100644 --- a/graphics/nxbe/nxbe_setsize.c +++ b/graphics/nxbe/nxbe_setsize.c @@ -25,9 +25,9 @@ #include #include +#include #ifdef CONFIG_NX_RAMBACKED -# include # include #ifdef CONFIG_BUILD_KERNEL # include diff --git a/graphics/nxglib/nxglib_copyrun.h b/graphics/nxglib/nxglib_copyrun.h index 8909eab95b2..3dd05506c53 100644 --- a/graphics/nxglib/nxglib_copyrun.h +++ b/graphics/nxglib/nxglib_copyrun.h @@ -28,6 +28,7 @@ #include #include #include +#include /**************************************************************************** * Public Functions Definitions diff --git a/graphics/nxmu/nxmu_openwindow.c b/graphics/nxmu/nxmu_openwindow.c index 86fd07b79d1..08993dd636e 100644 --- a/graphics/nxmu/nxmu_openwindow.c +++ b/graphics/nxmu/nxmu_openwindow.c @@ -23,6 +23,7 @@ ****************************************************************************/ #include +#include #include #ifdef CONFIG_NX_RAMBACKED diff --git a/graphics/nxmu/nxmu_start.c b/graphics/nxmu/nxmu_start.c index 971236d9718..271ffe6740c 100644 --- a/graphics/nxmu/nxmu_start.c +++ b/graphics/nxmu/nxmu_start.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/graphics/nxterm/nxterm_unregister.c b/graphics/nxterm/nxterm_unregister.c index bae442b190c..6c6721cc848 100644 --- a/graphics/nxterm/nxterm_unregister.c +++ b/graphics/nxterm/nxterm_unregister.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/graphics/vnc/server/vnc_keymap.c b/graphics/vnc/server/vnc_keymap.c index bafaf76caa6..0271bdfb771 100644 --- a/graphics/vnc/server/vnc_keymap.c +++ b/graphics/vnc/server/vnc_keymap.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/include/fcntl.h b/include/fcntl.h index 88b1cc9b926..e17f69ffb36 100644 --- a/include/fcntl.h +++ b/include/fcntl.h @@ -95,7 +95,7 @@ #define F_SETLKW 12 /* Like F_SETLK, but wait for lock to become available */ #define F_SETOWN 13 /* Set pid that will receive SIGIO and SIGURG signals for fd */ #define F_SETSIG 14 /* Set the signal to be sent */ -#define F_GETPATH 15 /* Get the path of the file descriptor(macos) */ +#define F_GETPATH 15 /* Get the path of the file descriptor(BSD/macOS) */ /* For posix fcntl() and lockf() */ diff --git a/include/limits.h b/include/limits.h index e2e5ef718cd..9836f159c29 100644 --- a/include/limits.h +++ b/include/limits.h @@ -120,10 +120,10 @@ #define _POSIX_MAX_INPUT 255 #define _POSIX_NAME_MAX CONFIG_NAME_MAX #define _POSIX_NGROUPS_MAX 0 -#define _POSIX_OPEN_MAX 255 +#define _POSIX_OPEN_MAX 16 #define _POSIX_PATH_MAX CONFIG_PATH_MAX #define _POSIX_PIPE_BUF 512 -#define _POSIX_STREAM_MAX 255 +#define _POSIX_STREAM_MAX 16 #define _POSIX_TZNAME_MAX 3 #ifdef CONFIG_SMALL_MEMORY diff --git a/include/malloc.h b/include/malloc.h index ddfa96f9dec..0854174ad42 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -31,6 +31,8 @@ * Pre-processor Definitions ****************************************************************************/ +/* For Linux and MacOS compatibility */ + #define malloc_usable_size malloc_size /**************************************************************************** diff --git a/include/net/if.h b/include/net/if.h index 5b04a9c862d..28da8d73242 100644 --- a/include/net/if.h +++ b/include/net/if.h @@ -50,6 +50,7 @@ #define IFF_UP (1 << 1) /* Interface is up */ #define IFF_RUNNING (1 << 2) /* Carrier is available */ #define IFF_IPv6 (1 << 3) /* Configured for IPv6 packet (vs ARP or IPv4) */ +#define IFF_BOUND (1 << 4) /* Bound to a socket */ #define IFF_NOARP (1 << 7) /* ARP is not required for this packet */ /* Interface flag helpers */ @@ -57,20 +58,23 @@ #define IFF_SET_DOWN(f) do { (f) |= IFF_DOWN; } while (0) #define IFF_SET_UP(f) do { (f) |= IFF_UP; } while (0) #define IFF_SET_RUNNING(f) do { (f) |= IFF_RUNNING; } while (0) +#define IFF_SET_BOUND(f) do { (f) |= IFF_BOUND; } while (0) #define IFF_SET_NOARP(f) do { (f) |= IFF_NOARP; } while (0) #define IFF_CLR_DOWN(f) do { (f) &= ~IFF_DOWN; } while (0) #define IFF_CLR_UP(f) do { (f) &= ~IFF_UP; } while (0) #define IFF_CLR_RUNNING(f) do { (f) &= ~IFF_RUNNING; } while (0) +#define IFF_CLR_BOUND(f) do { (f) &= ~IFF_BOUND; } while (0) #define IFF_CLR_NOARP(f) do { (f) &= ~IFF_NOARP; } while (0) #define IFF_IS_DOWN(f) (((f) & IFF_DOWN) != 0) #define IFF_IS_UP(f) (((f) & IFF_UP) != 0) #define IFF_IS_RUNNING(f) (((f) & IFF_RUNNING) != 0) +#define IFF_IS_BOUND(f) (((f) & IFF_BOUND) != 0) #define IFF_IS_NOARP(f) (((f) & IFF_NOARP) != 0) /* We only need to manage the IPv6 bit if both IPv6 and IPv4 are supported. - * Otherwise, we can save a few bytes by ignoring it. + * Otherwise, we can save a few bytes by ignoring it. */ #if defined(CONFIG_NET_IPv4) && defined(CONFIG_NET_IPv6) diff --git a/include/netpacket/packet.h b/include/netpacket/packet.h index af8c75f032e..0dd19473633 100644 --- a/include/netpacket/packet.h +++ b/include/netpacket/packet.h @@ -1,39 +1,20 @@ /**************************************************************************** * include/netpacket/packet.h - * Definitions for use with AF_PACKET sockets * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Daniel Laszlo Sitzer + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Includes some definitions that a compatible with the LGPL GNU C Library - * header file of the same name. + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/analog/adc.h b/include/nuttx/analog/adc.h index 0fb99c199b0..aa094855714 100644 --- a/include/nuttx/analog/adc.h +++ b/include/nuttx/analog/adc.h @@ -110,6 +110,19 @@ struct adc_callback_s CODE int (*au_receive)(FAR struct adc_dev_s *dev, uint8_t ch, int32_t data); + + /* This method is called from the lower half, platform-specific ADC logic + * when an overrun appeared to free / reset upper half. + * + * Input Parameters: + * dev - The ADC device structure that was previously registered by + * adc_register() + * + * Returned Value: + * Zero on success; a negated errno value on failure. + */ + + CODE int (*au_reset)(FAR struct adc_dev_s *dev); }; /* This describes on ADC message */ @@ -195,6 +208,7 @@ struct adc_dev_s sem_t ad_closesem; /* Locks out new opens while close is in progress */ sem_t ad_recvsem; /* Used to wakeup user waiting for space in ad_recv.buffer */ struct adc_fifo_s ad_recv; /* Describes receive FIFO */ + bool ad_isovr; /* Flag to indicate an ADC overrun */ /* The following is a list of poll structures of threads waiting for * driver events. The 'struct pollfd' reference for each open is also diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index d2b4efad2cb..517ec3ff8dc 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -558,6 +558,8 @@ void up_task_start(main_t taskentry, int argc, FAR char *argv[]) noreturn_function; #endif +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) && \ + !defined(CONFIG_DISABLE_PTHREAD) /**************************************************************************** * Name: up_pthread_start * @@ -569,9 +571,10 @@ void up_task_start(main_t taskentry, int argc, FAR char *argv[]) * pthread by calling this function. * * Normally the a user-mode start-up stub will also execute before the - * pthread actually starts. See libc/pthread/pthread_startup.c + * pthread actually starts. See libc/pthread/pthread_create.c * * Input Parameters: + * startup - The user-space pthread startup function * entrypt - The user-space address of the pthread entry point * arg - Standard argument for the pthread entry point * @@ -582,10 +585,28 @@ void up_task_start(main_t taskentry, int argc, FAR char *argv[]) * ****************************************************************************/ -#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) && \ - !defined(CONFIG_DISABLE_PTHREAD) -void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) +void up_pthread_start(pthread_trampoline_t startup, + pthread_startroutine_t entrypt, pthread_addr_t arg); noreturn_function; + +/**************************************************************************** + * Name: up_pthread_exit + * + * Description: + * In this kernel mode build, this function will be called to execute a + * pthread in user-space. This kernel-mode stub will then be called + * transfer control to the user-mode pthread_exit. + * + * Input Parameters: + * exit - The user-space pthread_exit function + * exit_value - The pointer of the pthread exit parameter + * + * Returned Value: + * None + ****************************************************************************/ + +void up_pthread_exit(pthread_exitroutine_t exit, FAR void *exit_value); + noreturn_function; #endif /**************************************************************************** @@ -733,39 +754,39 @@ uintptr_t pgalloc(uintptr_t brkaddr, unsigned int npages); #endif /**************************************************************************** - * Name: up_module_text_init + * Name: up_extraheaps_init * * Description: - * Initialize the module text allocator + * Initialize any extra heap. * ****************************************************************************/ -#if defined(CONFIG_ARCH_USE_MODULE_TEXT) -void up_module_text_init(void); +#if defined(CONFIG_ARCH_HAVE_EXTRA_HEAPS) +void up_extraheaps_init(void); #endif /**************************************************************************** - * Name: up_module_text_memalign + * Name: up_textheap_memalign * * Description: - * Allocate memory for module text with the specified alignment. + * Allocate memory for text sections with the specified alignment. * ****************************************************************************/ -#if defined(CONFIG_ARCH_USE_MODULE_TEXT) -FAR void *up_module_text_memalign(size_t align, size_t size); +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) +FAR void *up_textheap_memalign(size_t align, size_t size); #endif /**************************************************************************** - * Name: up_module_text_free + * Name: up_textheap_free * * Description: - * Free memory for module text. + * Free memory allocated for text sections. * ****************************************************************************/ -#if defined(CONFIG_ARCH_USE_MODULE_TEXT) -void up_module_text_free(FAR void *p); +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) +void up_textheap_free(FAR void *p); #endif /**************************************************************************** diff --git a/include/nuttx/binfmt/elf.h b/include/nuttx/binfmt/elf.h index e29eaf76587..7d59f285903 100644 --- a/include/nuttx/binfmt/elf.h +++ b/include/nuttx/binfmt/elf.h @@ -95,6 +95,9 @@ struct elf_loadinfo_s uintptr_t textalloc; /* .text memory allocated when ELF file was loaded */ uintptr_t dataalloc; /* .bss/.data memory allocated when ELF file was loaded */ size_t textsize; /* Size of the ELF .text memory allocation */ +#ifdef CONFIG_ARCH_USE_TEXT_HEAP + size_t textalign; /* Necessary alignment of .text */ +#endif size_t datasize; /* Size of the ELF .bss/.data memory allocation */ off_t filelen; /* Length of the entire ELF file */ @@ -129,7 +132,7 @@ struct elf_loadinfo_s uint16_t symtabidx; /* Symbol table section index */ uint16_t strtabidx; /* String table section index */ uint16_t buflen; /* size of iobuffer[] */ - int filfd; /* Descriptor for the file being loaded */ + struct file file; /* Descriptor for the file being loaded */ }; /**************************************************************************** diff --git a/include/nuttx/binfmt/nxflat.h b/include/nuttx/binfmt/nxflat.h index c9015708433..04ce55341f0 100644 --- a/include/nuttx/binfmt/nxflat.h +++ b/include/nuttx/binfmt/nxflat.h @@ -95,7 +95,7 @@ struct nxflat_loadinfo_s /* File descriptors */ - int filfd; /* Descriptor for the file being loaded */ + struct file file; /* Descriptor for the file being loaded */ /* This is a copy of the NXFLAT header (still in network order) */ diff --git a/include/nuttx/board.h b/include/nuttx/board.h index ee3f72d7eac..efefaa7d7fc 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -285,6 +285,31 @@ int board_reset(int status); int board_uniqueid(FAR uint8_t *uniqueid); #endif +/**************************************************************************** + * Name: board_uniquekey + * + * Description: + * Return a unique KEY associated with the board. The meaning of this + * unique KEY is not specified. It may be a trusted key or a private + * identity, etc. The only requirement is that the length of the + * unique KEY be exactly CONFIG_BOARDCTL_UNIQUEKEY_SIZE in length. + * + * Input Parameters: + * uniquekey - A reference to a writable memory location provided by the + * caller to receive the board unique KEY. The memory memory referenced + * by this pointer must be at least CONFIG_BOARDCTL_UNIQUEKEY_SIZE in + * length. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned indicating the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARDCTL_UNIQUEKEY +int board_uniquekey(FAR uint8_t *uniquekey); +#endif + /**************************************************************************** * Name: board_timerhook * diff --git a/include/nuttx/crypto/crypto.h b/include/nuttx/crypto/crypto.h index 6cc0985d5d3..46d798ab8ba 100644 --- a/include/nuttx/crypto/crypto.h +++ b/include/nuttx/crypto/crypto.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/crypto/crypto.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Max Nekludov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -41,7 +26,6 @@ ****************************************************************************/ #include -#include /**************************************************************************** * Pre-processor Definitions diff --git a/include/nuttx/crypto/cryptodev.h b/include/nuttx/crypto/cryptodev.h index 08d62d11036..23e1cacc4ec 100644 --- a/include/nuttx/crypto/cryptodev.h +++ b/include/nuttx/crypto/cryptodev.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/crypto/cryptodev.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Max Nekludov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/fs/fs.h b/include/nuttx/fs/fs.h index aa2bf209958..7bdf79c8d08 100644 --- a/include/nuttx/fs/fs.h +++ b/include/nuttx/fs/fs.h @@ -793,7 +793,7 @@ int file_dup2(FAR struct file *filep1, FAR struct file *filep2); * applications. * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is return on + * fd2 is returned on success; a negated errno value is return on * any failure. * ****************************************************************************/ @@ -1169,6 +1169,30 @@ int file_fsync(FAR struct file *filep); int file_truncate(FAR struct file *filep, off_t length); #endif +/**************************************************************************** + * Name: file_mmap + * + * Description: + * Equivalent to the standard mmap() function except that is accepts + * a struct file instance instead of a file descriptor and it does not set + * the errno variable. + * + ****************************************************************************/ + +int file_mmap(FAR struct file *filep, FAR void *start, size_t length, + int prot, int flags, off_t offset, FAR void **mapped); + +/**************************************************************************** + * Name: file_mummap + * + * Description: + * Equivalent to the standard mummap() function except it does not set + * the errno variable. + * + ****************************************************************************/ + +int file_munmap(FAR void *start, size_t length); + /**************************************************************************** * Name: file_ioctl * diff --git a/include/nuttx/fs/ioctl.h b/include/nuttx/fs/ioctl.h index d822c1f871b..d93390f2484 100644 --- a/include/nuttx/fs/ioctl.h +++ b/include/nuttx/fs/ioctl.h @@ -180,7 +180,7 @@ #define FIONCLEX _FIOC(0x000e) /* IN: None * OUT: None */ -#define FIOC_FILEPATH _FIOC(0x0004) /* IN: FAR char *(length >= PATH_MAX) +#define FIOC_FILEPATH _FIOC(0x000f) /* IN: FAR char *(length >= PATH_MAX) * OUT: The full file path */ diff --git a/include/nuttx/input/ads7843e.h b/include/nuttx/input/ads7843e.h index 085f8759d40..e3d3ff258db 100644 --- a/include/nuttx/input/ads7843e.h +++ b/include/nuttx/input/ads7843e.h @@ -1,43 +1,28 @@ /**************************************************************************** * include/nuttx/input/ads7843e.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Diego Sanchez + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * "Touch Screen Controller, ADS7843," Burr-Brown Products from Texas - * Instruments, SBAS090B, September 2000, Revised May 2002" + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * "Touch Screen Controller, ADS7843," Burr-Brown Products from Texas + * Instruments, SBAS090B, September 2000, Revised May 2002" + */ + #ifndef __INCLUDE_NUTTX_INPUT_ADS7843E_H #define __INCLUDE_NUTTX_INPUT_ADS7843E_H diff --git a/include/nuttx/input/max11802.h b/include/nuttx/input/max11802.h index b189c0877bb..cb74ce551d4 100644 --- a/include/nuttx/input/max11802.h +++ b/include/nuttx/input/max11802.h @@ -1,43 +1,28 @@ /**************************************************************************** * include/nuttx/input/max11802.h * - * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * References: - * "Low-Power, Ultra-Small Resistive Touch-Screen Controllers - * with I2C/SPI Interface" Maxim IC, Rev 3, 10/2010 + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* References: + * "Low-Power, Ultra-Small Resistive Touch-Screen Controllers + * with I2C/SPI Interface" Maxim IC, Rev 3, 10/2010 + */ + #ifndef __INCLUDE_NUTTX_INPUT_MAX11802_H #define __INCLUDE_NUTTX_INPUT_MAX11802_H diff --git a/include/nuttx/ioexpander/mcp23x17.h b/include/nuttx/ioexpander/mcp23x17.h new file mode 100644 index 00000000000..706e26036cd --- /dev/null +++ b/include/nuttx/ioexpander/mcp23x17.h @@ -0,0 +1,108 @@ +/**************************************************************************** + * include/nuttx/ioexpander/mcp23x17.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_IOEXPANDER_MCP23X17_H +#define __INCLUDE_NUTTX_IOEXPANDER_MCP23X17_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the mcp23x17 + * driver when the driver is instantiated. This structure provides + * information about the configuration of the mcp23x17 and provides some + * board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied by + * the driver and is presumed to persist while the driver is active. The + * memory must be writeable because, under certain circumstances, the driver + * may modify the frequency. + */ + +struct mcp23x17_config_s +{ + /* Device characterization */ + + uint8_t address; /* 7-bit I2C address (only bits 0-6 used) */ + uint32_t frequency; /* I2C or SPI frequency */ + + /* Sets the state of the MCP23X17's nReset pin */ + + CODE void (*set_nreset_pin)(bool state); + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE + /* If multiple mcp23x17 devices are supported, then an IRQ number must + * be provided for each so that their interrupts can be distinguished. + */ + + /* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the mcp23x17 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the mcp23x17 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + */ + + CODE int (*attach)(FAR struct mcp23x17_config_s *state, xcpt_t isr, + FAR void *arg); + CODE void (*enable)(FAR struct mcp23x17_config_s *state, bool enable); +#endif +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: mcp23x17_initialize + * + * Description: + * Initialize a MCP23X17 I2C device. + * + * TODO: Add support for more than one device. + * + ****************************************************************************/ + +FAR struct ioexpander_dev_s *mcp23x17_initialize( + FAR struct i2c_master_s *i2cdev, + FAR struct mcp23x17_config_s *config); + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_IOEXPANDER_MCP23X17_H */ diff --git a/include/nuttx/irq.h b/include/nuttx/irq.h index c5dfbb2861b..95009545455 100644 --- a/include/nuttx/irq.h +++ b/include/nuttx/irq.h @@ -29,7 +29,6 @@ #ifndef __ASSEMBLY__ # include -# include # include #endif diff --git a/include/nuttx/kmalloc.h b/include/nuttx/kmalloc.h index 71a86abf567..9ea6916d0b6 100644 --- a/include/nuttx/kmalloc.h +++ b/include/nuttx/kmalloc.h @@ -73,7 +73,7 @@ extern "C" #define kumm_calloc(n,s) calloc(n,s); #define kumm_malloc(s) malloc(s) -#define kumm_malloc_size(s) malloc_size(s) +#define kumm_malloc_size(p) malloc_size(p) #define kumm_zalloc(s) zalloc(s) #define kumm_realloc(p,s) realloc(p,s) #define kumm_memalign(a,s) memalign(a,s) @@ -93,7 +93,7 @@ extern "C" # define kmm_calloc(n,s) calloc(n,s); # define kmm_malloc(s) malloc(s) -# define kmm_malloc_size(s) malloc_size(s) +# define kmm_malloc_size(p) malloc_size(p) # define kmm_zalloc(s) zalloc(s) # define kmm_realloc(p,s) realloc(p,s) # define kmm_memalign(a,s) memalign(a,s) diff --git a/include/nuttx/lcd/ht16k33.h b/include/nuttx/lcd/ht16k33.h new file mode 100644 index 00000000000..63e52d0d937 --- /dev/null +++ b/include/nuttx/lcd/ht16k33.h @@ -0,0 +1,221 @@ +/**************************************************************************** + * include/nuttx/lcd/ht16k33.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_LEDS_HT16K33_H +#define __INCLUDE_NUTTX_LEDS_HT16K33_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/* Configuration + * CONFIG_I2C - Enables support for SPI drivers + * CONFIG_LCD_HT16K33 - Enables support for the HT16K33 driver + */ + +#if defined(CONFIG_I2C) && defined(CONFIG_LCD_HT16K33) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* HT16K33 Address */ + +#define HT16K33_I2C_ADDR 0x70 + +/* Default contrast */ + +#define DEFAULT_CONTRAST 0xf + +#define HT16K33_CONTRAST_MIN 0 +#define HT16K33_CONTRAST_MAX 15 + +/* HT16K33 register addresses */ + +#define HT16K33_DISP_DATA_ADDR 0x00 /* Display Data Address Pointer: 0x00-0x0f */ +#define HT16K33_SYSTEM_SETUP 0x20 /* System Setup: bit 0 = System Oscilator */ +#define HT16K33_KEY_DATA_ADDR 0x40 /* Key Data Address Pointer: 0x00-0x07 */ +#define HT16K33_INT_FLAG_ADDR 0x60 /* INT Flag Address */ +#define HT16K33_DISPLAY_SETUP 0x80 /* DISPLAY Setup */ +#define HT16K33_ROW_INT_SET 0xa0 /* ROW/INT set */ +#define HT16K33_DIMMING_SET 0xe0 /* Dimming set */ +#define HT16K33_TEST_MODE 0xd9 /* Holtek Test Mode */ + +/* Bits and flags definitions */ + +#define SYSTEM_SETUP_OSC_ON (1 << 0) /* Turn ON the Oscillator */ +#define DISPLAY_SETUP_DISP_ON (1 << 0) /* Display ON */ +#define DISPLAY_SETUP_BLINK_SHIFT 1 +#define DISPLAY_SETUP_BLINK_MASK (3 << DISPLAY_SETUP_BLINK_SHIFT) +# define DISPLAY_SETUP_BLINK_OFF (0 << DISPLAY_SETUP_BLINK_SHIFT) +# define DISPLAY_SETUP_BLINK_2HZ (1 << DISPLAY_SETUP_BLINK_SHIFT) +# define DISPLAY_SETUP_BLINK_1HZ (2 << DISPLAY_SETUP_BLINK_SHIFT) +# define DISPLAY_SETUP_BLINK_0P5HZ (3 << DISPLAY_SETUP_BLINK_SHIFT) +#define DIMMING_SHIFT 0 +#define DIMMING_MASK (0xf << DIMMING_SHIFT) +#define DIMMING_DUTY(N) ((N - 1) << DIMMING_SHIFT) + +/* This 14-segment mapping comes from Dave Madison's LED-Segment-ASCII + * released under MIT license: + * https://github.com/dmadison/LED-Segment-ASCII + */ + +static const uint16_t asciito14seg[96] = +{ + 0x0000, /* (space) */ + 0x4006, /* ! */ + 0x0202, /* " */ + 0x12ce, /* # */ + 0x12ed, /* $ */ + 0x3fe4, /* % */ + 0x2359, /* & */ + 0x0200, /* ' */ + 0x2400, /* ( */ + 0x0900, /* ) */ + 0x3fc0, /* * */ + 0x12c0, /* + */ + 0x0800, /* , */ + 0x00c0, /* - */ + 0x4000, /* . */ + 0x0c00, /* / */ + 0x0c3f, /* 0 */ + 0x0406, /* 1 */ + 0x00db, /* 2 */ + 0x008f, /* 3 */ + 0x00e6, /* 4 */ + 0x2069, /* 5 */ + 0x00fd, /* 6 */ + 0x0007, /* 7 */ + 0x00ff, /* 8 */ + 0x00ef, /* 9 */ + 0x1200, /* : */ + 0x0a00, /* ; */ + 0x2440, /* < */ + 0x00c8, /* = */ + 0x0980, /* > */ + 0x5083, /* ? */ + 0x02bb, /* @ */ + 0x00f7, /* A */ + 0x128f, /* B */ + 0x0039, /* C */ + 0x120f, /* D */ + 0x0079, /* E */ + 0x0071, /* F */ + 0x00bd, /* G */ + 0x00f6, /* H */ + 0x1209, /* I */ + 0x001e, /* J */ + 0x2470, /* K */ + 0x0038, /* L */ + 0x0536, /* M */ + 0x2136, /* N */ + 0x003f, /* O */ + 0x00f3, /* P */ + 0x203f, /* Q */ + 0x20f3, /* R */ + 0x00ed, /* S */ + 0x1201, /* T */ + 0x003e, /* U */ + 0x0c30, /* V */ + 0x2836, /* W */ + 0x2d00, /* X */ + 0x00ee, /* Y */ + 0x0c09, /* Z */ + 0x0039, /* [ */ + 0x2100, /* \ */ + 0x000f, /* ] */ + 0x2800, /* ^ */ + 0x0008, /* _ */ + 0x0100, /* ` */ + 0x1058, /* a */ + 0x2078, /* b */ + 0x00d8, /* c */ + 0x088e, /* d */ + 0x0858, /* e */ + 0x14c0, /* f */ + 0x048e, /* g */ + 0x1070, /* h */ + 0x1000, /* i */ + 0x0a10, /* j */ + 0x3600, /* k */ + 0x0030, /* l */ + 0x10d4, /* m */ + 0x1050, /* n */ + 0x00dc, /* o */ + 0x0170, /* p */ + 0x0486, /* q */ + 0x0050, /* r */ + 0x2088, /* s */ + 0x0078, /* t */ + 0x001c, /* u */ + 0x0810, /* v */ + 0x2814, /* w */ + 0x2d00, /* x */ + 0x028e, /* y */ + 0x0848, /* z */ + 0x0949, /* { */ + 0x1200, /* | */ + 0x2489, /* } */ + 0x0cc0, /* ~ */ + 0x0000, /* (del) */ +}; + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: ht16k33_register + * + * Description: + * Initialize the HT16K33 device as a LEDS interface. + * + * Input Parameters: + * spi - An instance of the SPI interface to use to communicate + * with the HT16K33. + * devno - Device number to identify current display. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +struct i2c_master_s; /* Forward reference */ + +int ht16k33_register(int devno, FAR struct i2c_master_s *i2c); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_I2C && CONFIG_HT16K33 */ +#endif /* __INCLUDE_NUTTX_LEDS_HT16K33_H */ diff --git a/include/nuttx/lcd/lcddrv_spiif.h b/include/nuttx/lcd/lcddrv_spiif.h index eb3a7b96505..f986729b22d 100644 --- a/include/nuttx/lcd/lcddrv_spiif.h +++ b/include/nuttx/lcd/lcddrv_spiif.h @@ -1,36 +1,20 @@ /**************************************************************************** * include/nuttx/lcd/lcddrv_spiif.h * - * Copyright (C) 2020 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/lcd/mio283qt9a.h b/include/nuttx/lcd/mio283qt9a.h index d1d8c09cbcb..ab80202069a 100644 --- a/include/nuttx/lcd/mio283qt9a.h +++ b/include/nuttx/lcd/mio283qt9a.h @@ -1,43 +1,28 @@ /**************************************************************************** * include/nuttx/lcd/mio283qt9a.h * - * Interface definition for - * the MI0283QT-9A LCD from Multi-Inno Technology Co., Ltd. - * This LCD is based on the Ilitek ILI9341 LCD controller. + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Tobias Duckworth + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ +/* Interface definition for + * the MI0283QT-9A LCD from Multi-Inno Technology Co., Ltd. + * This LCD is based on the Ilitek ILI9341 LCD controller. + */ + #ifndef __INCLUDE_NUTTX_LCD_MIO283QT9A_H #define __INCLUDE_NUTTX_LCD_MIO283QT9A_H diff --git a/include/nuttx/lcd/pcf8574_lcd_backpack.h b/include/nuttx/lcd/pcf8574_lcd_backpack.h index 24f7716b92e..4452e693914 100644 --- a/include/nuttx/lcd/pcf8574_lcd_backpack.h +++ b/include/nuttx/lcd/pcf8574_lcd_backpack.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/lcd/pcf8574_lcd_backpack.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: dev@ziggurat29.com + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/lib/getopt.h b/include/nuttx/lib/getopt.h index f155648b4fd..9eb7b3abc6b 100644 --- a/include/nuttx/lib/getopt.h +++ b/include/nuttx/lib/getopt.h @@ -29,20 +29,6 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define GETOPT_INIITIALIZER() = \ - { \ - NULL, \ - 0, \ - 1, \ - '?' \ - NULL, \ - false \ - } - /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/include/nuttx/lib/lib.h b/include/nuttx/lib/lib.h index 27949e43617..2b2e1f63db4 100644 --- a/include/nuttx/lib/lib.h +++ b/include/nuttx/lib/lib.h @@ -46,7 +46,7 @@ /* Domain-specific allocations */ # define lib_malloc(s) kmm_malloc(s) -# define lib_malloc_size(s) kmm_malloc_size(s) +# define lib_malloc_size(p) kmm_malloc_size(p) # define lib_zalloc(s) kmm_zalloc(s) # define lib_realloc(p,s) kmm_realloc(p,s) # define lib_memalign(p,s) kmm_memalign(p,s) @@ -55,7 +55,7 @@ /* User-accessible allocations */ # define lib_umalloc(s) kumm_malloc(s) -# define lib_umalloc_size(s) kumm_malloc_size(s) +# define lib_umalloc_size(p) kumm_malloc_size(p) # define lib_uzalloc(s) kumm_zalloc(s) # define lib_urealloc(p,s) kumm_realloc(p,s) # define lib_umemalign(p,s) kumm_memalign(p,s) @@ -66,7 +66,7 @@ /* Domain-specific allocations */ # define lib_malloc(s) malloc(s) -# define lib_malloc_size(s) malloc_size(s) +# define lib_malloc_size(p) malloc_size(p) # define lib_zalloc(s) zalloc(s) # define lib_realloc(p,s) realloc(p,s) # define lib_memalign(p,s) memalign(p,s) @@ -75,7 +75,7 @@ /* User-accessible allocations */ # define lib_umalloc(s) malloc(s) -# define lib_umalloc_size(s) malloc_size(s) +# define lib_umalloc_size(p) malloc_size(p) # define lib_uzalloc(s) zalloc(s) # define lib_urealloc(p,s) realloc(p,s) # define lib_umemalign(p,s) memalign(p,s) diff --git a/include/nuttx/mm/iob.h b/include/nuttx/mm/iob.h index b0911d281fe..5aa9980f481 100644 --- a/include/nuttx/mm/iob.h +++ b/include/nuttx/mm/iob.h @@ -106,7 +106,7 @@ struct iob_s uint16_t io_len; /* Length of the data in the entry */ uint16_t io_offset; /* Data begins at this offset */ #endif - uint16_t io_pktlen; /* Total length of the packet */ + unsigned int io_pktlen; /* Total length of the packet */ uint8_t io_data[CONFIG_IOB_BUFSIZE]; }; @@ -125,10 +125,6 @@ struct iob_qentry_s /* Payload -- Head of the I/O buffer chain */ FAR struct iob_s *qe_head; - - /* Private data */ - - FAR void *qe_priv; }; /* The I/O buffer queue head structure */ @@ -185,7 +181,6 @@ enum iob_user_e #endif #if defined(CONFIG_NET_TCP) && !defined(NET_TCP_NO_STACK) IOBUSER_NET_TCP_READAHEAD, - IOBUSER_NET_TCP_PENDINGAHEAD, #endif #ifdef CONFIG_NET_TCP_WRITE_BUFFERS IOBUSER_NET_TCP_WRITEBUFFER, @@ -367,8 +362,7 @@ void iob_free_chain(FAR struct iob_s *iob, enum iob_user_e producerid); ****************************************************************************/ #if CONFIG_IOB_NCHAINS > 0 -int iob_add_queue(FAR struct iob_s *iob, FAR void *priv, - FAR struct iob_queue_s *iobq); +int iob_add_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq); #endif /* CONFIG_IOB_NCHAINS > 0 */ /**************************************************************************** @@ -381,8 +375,7 @@ int iob_add_queue(FAR struct iob_s *iob, FAR void *priv, ****************************************************************************/ #if CONFIG_IOB_NCHAINS > 0 -int iob_tryadd_queue(FAR struct iob_s *iob, FAR void *priv, - FAR struct iob_queue_s *iobq); +int iob_tryadd_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq); #endif /* CONFIG_IOB_NCHAINS > 0 */ /**************************************************************************** @@ -428,40 +421,29 @@ FAR struct iob_s *iob_peek_queue(FAR struct iob_queue_s *iobq); ****************************************************************************/ #if CONFIG_IOB_NCHAINS > 0 -void iob_free_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq, +void iob_free_queue(FAR struct iob_queue_s *qhead, enum iob_user_e producerid); #endif /* CONFIG_IOB_NCHAINS > 0 */ /**************************************************************************** - * Name: iob_destroy_queue + * Name: iob_free_queue_qentry * * Description: - * Destroy all I/O buffer chains from the iob queue. + * Free an iob entire queue of I/O buffer chains. * ****************************************************************************/ #if CONFIG_IOB_NCHAINS > 0 -void iob_destroy_queue(FAR struct iob_queue_s *qhead, - enum iob_user_e producerid); -#endif /* CONFIG_IOB_NCHAINS > 0 */ - -/**************************************************************************** - * Name: iob_get_queue_count - * - * Description: - * Queue helper for get the iob entry count. - * - ****************************************************************************/ - -#if CONFIG_IOB_NCHAINS > 0 -int iob_get_queue_count(FAR struct iob_queue_s *queue); +void iob_free_queue_qentry(FAR struct iob_s *iob, + FAR struct iob_queue_s *iobq, + enum iob_user_e producerid); #endif /* CONFIG_IOB_NCHAINS > 0 */ /**************************************************************************** * Name: iob_get_queue_size * * Description: - * Queue helper for get the iob entry size. + * Queue helper for get the iob queue buffer size. * ****************************************************************************/ @@ -508,6 +490,17 @@ int iob_trycopyin(FAR struct iob_s *iob, FAR const uint8_t *src, int iob_copyout(FAR uint8_t *dest, FAR const struct iob_s *iob, unsigned int len, unsigned int offset); +/**************************************************************************** + * Name: iob_tailroom + * + * Description: + * Return the number of bytes at the tail of the I/O buffer chain which + * can be used to append data without additional allocations. + * + ****************************************************************************/ + +unsigned int iob_tailroom(FAR struct iob_s *iob); + /**************************************************************************** * Name: iob_clone * diff --git a/include/nuttx/mm/shm.h b/include/nuttx/mm/shm.h index dbeebad3e60..0045b846b37 100644 --- a/include/nuttx/mm/shm.h +++ b/include/nuttx/mm/shm.h @@ -27,8 +27,6 @@ #include -#include - #include #ifdef CONFIG_MM_SHM diff --git a/include/nuttx/motor/foc/foc.h b/include/nuttx/motor/foc/foc.h index a1f4a07ece6..7468976610c 100644 --- a/include/nuttx/motor/foc/foc.h +++ b/include/nuttx/motor/foc/foc.h @@ -108,7 +108,6 @@ struct foc_info_s /* FOC device upper-half */ struct foc_lower_s; -struct foc_typespec_s; struct foc_dev_s { /* Fields managed by common upper-half FOC logic **************************/ diff --git a/include/nuttx/power/motor.h b/include/nuttx/motor/motor.h similarity index 87% rename from include/nuttx/power/motor.h rename to include/nuttx/motor/motor.h index d2674853110..f1f5f5dff54 100644 --- a/include/nuttx/power/motor.h +++ b/include/nuttx/motor/motor.h @@ -1,5 +1,5 @@ /**************************************************************************** - * include/nuttx/power/motor.h + * include/nuttx/motor/motor.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __INCLUDE_NUTTX_DRIVERS_POWER_MOTOR_H -#define __INCLUDE_NUTTX_DRIVERS_POWER_MOTOR_H +#ifndef __INCLUDE_NUTTX_DRIVERS_MOTOR_MOTOR_H +#define __INCLUDE_NUTTX_DRIVERS_MOTOR_MOTOR_H /* The motor driver is split into two parts: * @@ -42,10 +42,10 @@ #include #include -#include +#include #include -#ifdef CONFIG_DRIVERS_MOTOR +#ifdef CONFIG_MOTOR_UPPER /**************************************************************************** * Pre-processor Definitions @@ -103,25 +103,25 @@ enum motor_direction_e struct motor_feedback_s { -#ifdef CONFIG_MOTOR_HAVE_POSITION +#ifdef CONFIG_MOTOR_UPPER_HAVE_POSITION float position; /* Current motor position */ #endif -#ifdef CONFIG_MOTOR_HAVE_SPEED +#ifdef CONFIG_MOTOR_UPPER_HAVE_SPEED float speed; /* Current motor speed */ #endif -#ifdef CONFIG_MOTOR_HAVE_TORQUE +#ifdef CONFIG_MOTOR_UPPER_HAVE_TORQUE float torque; /* Current motor torque (rotary motor) */ #endif -#ifdef CONFIG_MOTOR_HAVE_FORCE +#ifdef CONFIG_MOTOR_UPPER_HAVE_FORCE float force; /* Current motor force (linear motor) */ #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_VOLTAGE +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_VOLTAGE float v_in; /* Current input voltage */ #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_CURRENT +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_CURRENT float i_in; /* Current input current */ #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_POWER +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_POWER float p_in; /* Current input power */ #endif }; @@ -145,31 +145,31 @@ struct motor_limits_s bool lock; /* This bit must be set after * limits configuration. */ -#ifdef CONFIG_MOTOR_HAVE_POSITION +#ifdef CONFIG_MOTOR_UPPER_HAVE_POSITION float position; /* Maximum motor position */ #endif -#ifdef CONFIG_MOTOR_HAVE_SPEED +#ifdef CONFIG_MOTOR_UPPER_HAVE_SPEED float speed; /* Maximum motor speed */ #endif -#ifdef CONFIG_MOTOR_HAVE_TORQUE +#ifdef CONFIG_MOTOR_UPPER_HAVE_TORQUE float torque; /* Maximum motor torque (rotary motor) */ #endif -#ifdef CONFIG_MOTOR_HAVE_FORCE +#ifdef CONFIG_MOTOR_UPPER_HAVE_FORCE float force; /* Maximum motor force (linear motor) */ #endif -#ifdef CONFIG_MOTOR_HAVE_ACCELERATION +#ifdef CONFIG_MOTOR_UPPER_HAVE_ACCELERATION float acceleration; /* Maximum motor acceleration */ #endif -#ifdef CONFIG_MOTOR_HAVE_DECELERATION +#ifdef CONFIG_MOTOR_UPPER_HAVE_DECELERATION float deceleration; /* Maximum motor decelaration */ #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_VOLTAGE +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_VOLTAGE float v_in; /* Maximum input voltage */ #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_CURRENT +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_CURRENT float i_in; /* Maximum input current */ #endif -#ifdef CONFIG_MOTOR_HAVE_INPUT_POWER +#ifdef CONFIG_MOTOR_UPPER_HAVE_INPUT_POWER float p_in; /* Maximum input power */ #endif }; @@ -184,7 +184,7 @@ struct motor_params_s * if there is no need to change motor * parameter during run-time. */ -#ifdef CONFIG_MOTOR_HAVE_DIRECTION +#ifdef CONFIG_MOTOR_UPPER_HAVE_DIRECTION int8_t direction; /* Motor movement direction. We do not * support negative values for parameters, * so this flag can be used to allow movement @@ -192,22 +192,22 @@ struct motor_params_s * a given coordinate system. */ #endif -#ifdef CONFIG_MOTOR_HAVE_POSITION +#ifdef CONFIG_MOTOR_UPPER_HAVE_POSITION float position; /* Motor position */ #endif -#ifdef CONFIG_MOTOR_HAVE_SPEED +#ifdef CONFIG_MOTOR_UPPER_HAVE_SPEED float speed; /* Motor speed */ #endif -#ifdef CONFIG_MOTOR_HAVE_TORQUE +#ifdef CONFIG_MOTOR_UPPER_HAVE_TORQUE float torque; /* Motor torque (rotary motor) */ #endif -#ifdef CONFIG_MOTOR_HAVE_FORCE +#ifdef CONFIG_MOTOR_UPPER_HAVE_FORCE float force; /* Motor force (linear motor) */ #endif -#ifdef CONFIG_MOTOR_HAVE_ACCELERATION +#ifdef CONFIG_MOTOR_UPPER_HAVE_ACCELERATION float acceleration; /* Motor acceleration */ #endif -#ifdef CONFIG_MOTOR_HAVE_DECELERATION +#ifdef CONFIG_MOTOR_UPPER_HAVE_DECELERATION float deceleration; /* Motor deceleration */ #endif }; @@ -268,15 +268,15 @@ struct motor_ops_s /* Get motor state */ CODE int (*state_get)(FAR struct motor_dev_s *dev, - FAR struct motor_state_s *state); + FAR struct motor_state_s *state); /* Get current fault state */ CODE int (*fault_get)(FAR struct motor_dev_s *dev, FAR uint8_t *fault); - /* Clean fault state */ + /* Clear fault state */ - CODE int (*fault_clean)(FAR struct motor_dev_s *dev, uint8_t fault); + CODE int (*fault_clear)(FAR struct motor_dev_s *dev, uint8_t fault); /* Lower-half logic may support platform-specific ioctl commands */ @@ -331,5 +331,5 @@ int motor_register(FAR const char *path, FAR struct motor_dev_s *dev, } #endif -#endif /* CONFIG_DRIVERS_MOTOR */ -#endif /* __INCLUDE_NUTTX_DRIVERS_POWER_MOTOR_H */ +#endif /* CONFIG_MOTOR_UPPER */ +#endif /* __INCLUDE_NUTTX_DRIVERS_MOTOR_MOTOR_H */ diff --git a/include/nuttx/motor/motor_ioctl.h b/include/nuttx/motor/motor_ioctl.h index 725c51c55e6..51220643f68 100644 --- a/include/nuttx/motor/motor_ioctl.h +++ b/include/nuttx/motor/motor_ioctl.h @@ -45,5 +45,9 @@ #define MTRIOC_SET_PARAMS _MTRIOC(5) #define MTRIOC_SET_CONFIG _MTRIOC(6) #define MTRIOC_GET_INFO _MTRIOC(7) +#define MTRIOC_SET_MODE _MTRIOC(8) +#define MTRIOC_SET_LIMITS _MTRIOC(9) +#define MTRIOC_SET_FAULT _MTRIOC(10) +#define MTRIOC_GET_FAULT _MTRIOC(11) #endif /* __INCLUDE_NUTTX_MOTOR_MOTOR_IOCTL_H */ diff --git a/include/nuttx/mqueue.h b/include/nuttx/mqueue.h index 9752d7d1ed6..90688cdca06 100644 --- a/include/nuttx/mqueue.h +++ b/include/nuttx/mqueue.h @@ -360,12 +360,12 @@ ssize_t nxmq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen, * Description: * This function deallocates an initialized message queue structure. * First, it deallocates all of the queued messages in the message - * queue. It is assumed that this message is fully unlinked and - * closed so that no thread will attempt access it while it is being - * deleted. + * queue. It is assumed that this message queue is fully unlinked + * and closed so that no thread will attempt to access it while it + * is being deleted. * * Input Parameters: - * msgq - Named essage queue to be freed + * msgq - Named message queue to be freed * * Returned Value: * None @@ -400,10 +400,10 @@ FAR struct mqueue_inode_s *nxmq_alloc_msgq(mode_t mode, * Name: nxmq_pollnotify * * Description: - * pollnotify, used for notify the poll + * pollnotify, used for notifying the poll * * Input Parameters: - * msgq - Named essage queue + * msgq - Named message queue * eventset - evnet * * Returned Value: diff --git a/include/nuttx/net/tcp.h b/include/nuttx/net/tcp.h index e209ea5ef7c..1a983f3473a 100644 --- a/include/nuttx/net/tcp.h +++ b/include/nuttx/net/tcp.h @@ -76,8 +76,11 @@ #define TCP_OPT_END 0 /* End of TCP options list */ #define TCP_OPT_NOOP 1 /* "No-operation" TCP option */ #define TCP_OPT_MSS 2 /* Maximum segment size TCP option */ +#define TCP_OPT_WS 3 /* Window size scaling factor */ +#define TCP_OPT_NOOP_LEN 1 /* Length of TCP NOOP option. */ #define TCP_OPT_MSS_LEN 4 /* Length of TCP MSS option. */ +#define TCP_OPT_WS_LEN 3 /* Length of TCP WS option. */ /* The TCP states used in the struct tcp_conn_s tcpstateflags field */ @@ -171,7 +174,7 @@ struct tcp_hdr_s uint8_t wnd[2]; uint16_t tcpchksum; uint8_t urgp[2]; - uint8_t optdata[4]; + uint8_t optdata[0]; }; /* The structure holding the TCP/IP statistics that are gathered if diff --git a/include/nuttx/nx/nxfonts.h b/include/nuttx/nx/nxfonts.h index 9988e86e469..16bb00e9303 100644 --- a/include/nuttx/nx/nxfonts.h +++ b/include/nuttx/nx/nxfonts.h @@ -490,7 +490,7 @@ extern "C" * fontid: Identifies the font set to get * * Returned Value: - * One success, a non-NULL font handle is returned. + * On success, a non-NULL font handle is returned. * ****************************************************************************/ @@ -638,7 +638,7 @@ void nxf_cache_disconnect(FCACHE fhandle); * Zero (OK) is returned if the metrics were * * Returned Value: - * One success, a non-NULL font handle is returned. + * On success, a non-NULL font handle is returned. * ****************************************************************************/ diff --git a/include/nuttx/pthread.h b/include/nuttx/pthread.h index e92b2075eff..7c4b8ceba27 100644 --- a/include/nuttx/pthread.h +++ b/include/nuttx/pthread.h @@ -100,7 +100,7 @@ #endif /**************************************************************************** - * Public Data + * Public Types ****************************************************************************/ #ifdef __cplusplus @@ -111,6 +111,10 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Public Data + ****************************************************************************/ + /* Default pthread attributes. This global can only be shared within the * kernel- or within the user- address space. */ @@ -121,6 +125,70 @@ EXTERN const pthread_attr_t g_default_pthread_attr; * Public Function Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: nx_pthread_create + * + * Description: + * This function creates and activates a new thread with specified + * attributes. + * + * Input Parameters: + * trampoline - The user space startup function + * thread - The pthread handle to be used + * attr - It points to a pthread_attr_t structure whose contents are + * used at thread creation time to determine attributes + * for the new thread + * entry - The new thread starts execution by invoking entry + * arg - It is passed as the sole argument of entry + * exit - The user-space pthread exit function + * + * Returned Value: + * OK (0) on success; a (non-negated) errno value on failure. The errno + * variable is not set. + * + ****************************************************************************/ + +int nx_pthread_create(pthread_trampoline_t trampoline, FAR pthread_t *thread, + FAR const pthread_attr_t *attr, + pthread_startroutine_t entry, pthread_addr_t arg, + pthread_exitroutine_t exit); + +/**************************************************************************** + * Name: nx_pthread_exit + * + * Description: + * Terminate execution of a thread started with pthread_create. + * + * Input Parameters: + * exit_value + * + * Returned Value: + * None + * + ****************************************************************************/ + +void nx_pthread_exit(FAR void *exit_value) noreturn_function; + +/**************************************************************************** + * Name: pthread_cleanup_popall + * + * Description: + * The pthread_cleanup_popall() is an internal function that will pop and + * execute all clean-up functions. This function is only called from + * within the pthread_exit() and pthread_cancellation() logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PTHREAD_CLEANUP +void pthread_cleanup_popall(void); +#endif + #undef EXTERN #ifdef __cplusplus } diff --git a/include/nuttx/rptun/openamp.h b/include/nuttx/rptun/openamp.h index 8a96b98889e..3e52e501494 100644 --- a/include/nuttx/rptun/openamp.h +++ b/include/nuttx/rptun/openamp.h @@ -26,12 +26,11 @@ ****************************************************************************/ #include - -#ifdef CONFIG_RPTUN - #include #include +#ifdef CONFIG_RPTUN + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index fb73ef8bcb8..21671190881 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -1,4 +1,4 @@ -/******************************************************************************** +/**************************************************************************** * include/nuttx/sched.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************/ + ****************************************************************************/ #ifndef __INCLUDE_NUTTX_SCHED_H #define __INCLUDE_NUTTX_SCHED_H -/******************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************/ + ****************************************************************************/ #include @@ -45,11 +45,11 @@ #include -/******************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************/ + ****************************************************************************/ -/* Configuration ****************************************************************/ +/* Configuration ************************************************************/ /* Task groups currently only supported for retention of child status */ @@ -75,7 +75,7 @@ # define CONFIG_SCHED_SPORADIC_MAXREPL 3 #endif -/* Task Management Definitions **************************************************/ +/* Task Management Definitions **********************************************/ /* Special task IDS. Any negative PID is invalid. */ @@ -96,18 +96,19 @@ #define TCB_FLAG_NONCANCELABLE (1 << 2) /* Bit 2: Pthread is non-cancelable */ #define TCB_FLAG_CANCEL_DEFERRED (1 << 3) /* Bit 3: Deferred (vs asynch) cancellation type */ #define TCB_FLAG_CANCEL_PENDING (1 << 4) /* Bit 4: Pthread cancel is pending */ -#define TCB_FLAG_POLICY_SHIFT (5) /* Bit 5-6: Scheduling policy */ +#define TCB_FLAG_CANCEL_DOING (1 << 5) /* Bit 4: Pthread cancel/exit is doing */ +#define TCB_FLAG_POLICY_SHIFT (6) /* Bit 5-6: Scheduling policy */ #define TCB_FLAG_POLICY_MASK (3 << TCB_FLAG_POLICY_SHIFT) # define TCB_FLAG_SCHED_FIFO (0 << TCB_FLAG_POLICY_SHIFT) /* FIFO scheding policy */ # define TCB_FLAG_SCHED_RR (1 << TCB_FLAG_POLICY_SHIFT) /* Round robin scheding policy */ # define TCB_FLAG_SCHED_SPORADIC (2 << TCB_FLAG_POLICY_SHIFT) /* Sporadic scheding policy */ # define TCB_FLAG_SCHED_OTHER (3 << TCB_FLAG_POLICY_SHIFT) /* Other scheding policy */ -#define TCB_FLAG_CPU_LOCKED (1 << 7) /* Bit 7: Locked to this CPU */ -#define TCB_FLAG_SIGNAL_ACTION (1 << 8) /* Bit 8: In a signal handler */ -#define TCB_FLAG_SYSCALL (1 << 9) /* Bit 9: In a system call */ -#define TCB_FLAG_EXIT_PROCESSING (1 << 10) /* Bit 10: Exitting */ -#define TCB_FLAG_FREE_STACK (1 << 11) /* Bit 11: Free stack after exit */ - /* Bits 12-15: Available */ +#define TCB_FLAG_CPU_LOCKED (1 << 8) /* Bit 7: Locked to this CPU */ +#define TCB_FLAG_SIGNAL_ACTION (1 << 9) /* Bit 8: In a signal handler */ +#define TCB_FLAG_SYSCALL (1 << 10) /* Bit 9: In a system call */ +#define TCB_FLAG_EXIT_PROCESSING (1 << 11) /* Bit 10: Exitting */ +#define TCB_FLAG_FREE_STACK (1 << 12) /* Bit 12: Free stack after exit */ + /* Bits 13-15: Available */ /* Values for struct task_group tg_flags */ @@ -183,18 +184,18 @@ # error "CONFIG_SCHED_EXIT_MAX < 1" #endif -/******************************************************************************** +/**************************************************************************** * Public Type Definitions - ********************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/* General Task Management Types ************************************************/ +/* General Task Management Types ********************************************/ /* This is the type of the task_state field of the TCB. NOTE: the order and - * content of this enumeration is critical since there are some OS tables indexed - * by these values. The range of values is assumed to fit into a uint8_t in - * struct tcb_s. + * content of this enumeration is critical since there are some OS tables + * indexed by these values. + * The range of values is assumed to fit into a uint8_t in struct tcb_s. */ enum tstate_e @@ -259,8 +260,8 @@ typedef union entry_u entry_t; typedef CODE void (*starthook_t)(FAR void *arg); #endif -/* These are the types of the functions that are executed with exit() is called - * (if registered via atexit() on on_exit()). +/* These are the types of the functions that are executed with exit() is + * called (if registered via atexit() on on_exit()). */ #ifdef CONFIG_SCHED_ATEXIT @@ -271,7 +272,7 @@ typedef CODE void (*atexitfunc_t)(void); typedef CODE void (*onexitfunc_t)(int exitcode, FAR void *arg); #endif -/* struct sporadic_s ************************************************************/ +/* struct sporadic_s ********************************************************/ #ifdef CONFIG_SCHED_SPORADIC @@ -289,10 +290,10 @@ struct replenishment_s }; /* This structure is an allocated "plug-in" to the main TCB structure. It is - * allocated when the sporadic scheduling policy is assigned to a thread. Thus, - * in the context of numerous threads of varying policies, there the overhead - * from this significant allocation is only borne by the threads with the - * sporadic scheduling policy. + * allocated when the sporadic scheduling policy is assigned to a thread. + * Thus, in the context of numerous threads of varying policies, there the + * overhead from this significant allocation is only borne by the threads + * with the sporadic scheduling policy. */ struct sporadic_s @@ -317,10 +318,11 @@ struct sporadic_s #endif /* CONFIG_SCHED_SPORADIC */ -/* struct child_status_s ********************************************************/ +/* struct child_status_s ****************************************************/ -/* This structure is used to maintain information about child tasks. pthreads - * work differently, they have join information. This is only for child tasks. +/* This structure is used to maintain information about child tasks. + * pthreads work differently, they have join information. + * This is only for child tasks. */ #ifdef CONFIG_SCHED_CHILD_STATUS @@ -334,7 +336,7 @@ struct child_status_s }; #endif -/* struct pthread_cleanup_s *****************************************************/ +/* struct pthread_cleanup_s *************************************************/ /* This structure describes one element of the pthread cleanup stack */ @@ -346,10 +348,10 @@ struct pthread_cleanup_s }; #endif -/* type tls_ndxset_t ************************************************************/ +/* type tls_ndxset_t & tls_dtor_t *******************************************/ -/* Smallest addressable type that can hold the entire configured number of TLS - * data indexes. +/* Smallest addressable type that can hold the entire configured number of + * TLS data indexes. */ #if CONFIG_TLS_NELEM > 0 @@ -362,13 +364,16 @@ struct pthread_cleanup_s # else typedef uint8_t tls_ndxset_t; # endif + +typedef CODE void (*tls_dtor_t)(FAR void *); + #endif -/* struct dspace_s **************************************************************/ +/* struct dspace_s **********************************************************/ -/* This structure describes a reference counted D-Space region. This must be a - * separately allocated "break-away" structure that can be owned by a task and - * any pthreads created by the task. +/* This structure describes a reference counted D-Space region. + * This must be a separately allocated "break-away" structure that + * can be owned by a task and any pthreads created by the task. */ #ifdef CONFIG_PIC @@ -383,15 +388,15 @@ struct dspace_s uint16_t crefs; /* This is the allocated D-Space memory region. This may be a physical - * address allocated with kmm_malloc(), or it may be virtual address associated - * with an address environment (if CONFIG_ARCH_ADDRENV=y). + * address allocated with kmm_malloc(), or it may be virtual address + * associated with an address environment (if CONFIG_ARCH_ADDRENV=y). */ FAR uint8_t *region; }; #endif -/* struct stackinfo_s ***********************************************************/ +/* struct stackinfo_s *******************************************************/ /* Used to report stack information */ @@ -407,7 +412,7 @@ struct stackinfo_s /* from the stack. */ }; -/* struct exitinfo_s ************************************************************/ +/* struct exitinfo_s ********************************************************/ struct exitinfo_s { @@ -425,15 +430,17 @@ struct exitinfo_s #endif }; -/* struct task_group_s **********************************************************/ +struct task_info_s; + +/* struct task_group_s ******************************************************/ /* All threads created by pthread_create belong in the same task group (along * with the thread of the original task). struct task_group_s is a shared - * structure referenced by the TCB of each thread that is a member of the task - * group. + * structure referenced by the TCB of each thread that is a member of the + * task group. * - * This structure should contain *all* resources shared by tasks and threads that - * belong to the same task group: + * This structure should contain *all* resources shared by tasks and threads + * that belong to the same task group: * * Child exit status * Environment variables @@ -443,11 +450,11 @@ struct exitinfo_s * Sockets * Address environments. * - * Each instance of struct task_group_s is reference counted. Each instance is - * created with a reference count of one. The reference incremented when each - * thread joins the group and decremented when each thread exits, leaving the - * group. When the reference count decrements to zero, the struct task_group_s - * is free. + * Each instance of struct task_group_s is reference counted. Each instance + * is created with a reference count of one. The reference incremented when + * each thread joins the group and decremented when each thread exits, + * leaving the group. When the reference count decrements to zero, + * the struct task_group_s is free. */ #ifndef CONFIG_DISABLE_PTHREAD @@ -468,14 +475,14 @@ struct task_group_s pid_t tg_ppid; /* This is the ID of the parent thread */ uint8_t tg_flags; /* See GROUP_FLAG_* definitions */ - /* User identity **************************************************************/ + /* User identity **********************************************************/ #ifdef CONFIG_SCHED_USER_IDENTITY uid_t tg_uid; /* User identity */ gid_t tg_gid; /* User group identity */ #endif - /* Group membership ***********************************************************/ + /* Group membership *******************************************************/ uint8_t tg_nmembers; /* Number of members in the group */ #ifdef HAVE_GROUP_MEMBERS @@ -483,20 +490,20 @@ struct task_group_s FAR pid_t *tg_members; /* Members of the group */ #endif - /* [at|on]exit support ********************************************************/ + /* [at|on]exit support ****************************************************/ #ifdef CONFIG_SCHED_EXIT_MAX struct exitinfo_s tg_exit[CONFIG_SCHED_EXIT_MAX]; #endif #ifdef CONFIG_BINFMT_LOADABLE - /* Loadable module support ****************************************************/ + /* Loadable module support ************************************************/ FAR struct binary_s *tg_bininfo; /* Describes resources used by program */ #endif #ifdef CONFIG_SCHED_HAVE_PARENT - /* Child exit status **********************************************************/ + /* Child exit status ******************************************************/ #ifdef CONFIG_SCHED_CHILD_STATUS FAR struct child_status_s *tg_children; /* Head of a list of child status */ @@ -506,33 +513,37 @@ struct task_group_s #endif /* CONFIG_SCHED_HAVE_PARENT */ #if defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_SCHED_HAVE_PARENT) - /* waitpid support ************************************************************/ + /* waitpid support ********************************************************/ - /* Simple mechanism used only when there is no support for SIGCHLD */ + /* Simple mechanism used only when there is no support for SIGCHLD */ - uint8_t tg_nwaiters; /* Number of waiters */ - uint8_t tg_waitflags; /* User flags for waitpid behavior */ - sem_t tg_exitsem; /* Support for waitpid */ - FAR int *tg_statloc; /* Location to return exit status */ + uint8_t tg_nwaiters; /* Number of waiters */ + uint8_t tg_waitflags; /* User flags for waitpid behavior */ + sem_t tg_exitsem; /* Support for waitpid */ + FAR int *tg_statloc; /* Location to return exit status */ #endif #ifndef CONFIG_DISABLE_PTHREAD - /* Pthreads *******************************************************************/ + /* Pthreads ***************************************************************/ - /* Pthread join Info: */ + /* Pthread join Info: */ - sem_t tg_joinsem; /* Mutually exclusive access to join data */ - FAR struct join_s *tg_joinhead; /* Head of a list of join data */ - FAR struct join_s *tg_jointail; /* Tail of a list of join data */ + sem_t tg_joinsem; /* Mutually exclusive access to join data */ + FAR struct join_s *tg_joinhead; /* Head of a list of join data */ + FAR struct join_s *tg_jointail; /* Tail of a list of join data */ #endif - /* Thread local storage *******************************************************/ + /* Thread local storage ***************************************************/ + + FAR struct task_info_s *tg_info; #if CONFIG_TLS_NELEM > 0 - tls_ndxset_t tg_tlsset; /* Set of TLS data indexes allocated */ + tls_ndxset_t tg_tlsset; /* Set of TLS indexes allocated */ + + tls_dtor_t tg_tlsdestr[CONFIG_TLS_NELEM]; /* List of TLS destructors */ #endif - /* POSIX Signal Control Fields ************************************************/ + /* POSIX Signal Control Fields ********************************************/ sq_queue_t tg_sigactionq; /* List of actions for signals */ sq_queue_t tg_sigpendingq; /* List of pending signals */ @@ -541,169 +552,159 @@ struct task_group_s #endif #ifndef CONFIG_DISABLE_ENVIRON - /* Environment variables ******************************************************/ + /* Environment variables **************************************************/ size_t tg_envsize; /* Size of environment string allocation */ FAR char *tg_envp; /* Allocated environment strings */ #endif #ifndef CONFIG_DISABLE_POSIX_TIMERS - /* Interval timer *************************************************************/ + /* Interval timer *********************************************************/ timer_t itimer; #endif - /* PIC data space and address environments ************************************/ + /* PIC data space and address environments ********************************/ /* Logically the PIC data space belongs here (see struct dspace_s). The * current logic needs review: There are differences in the away that the * life of the PIC data is managed. */ - /* File descriptors ***********************************************************/ + /* File descriptors *******************************************************/ - struct filelist tg_filelist; /* Maps file descriptor to file */ + struct filelist tg_filelist; /* Maps file descriptor to file */ #ifdef CONFIG_FILE_STREAM - /* FILE streams ***************************************************************/ + /* FILE streams ***********************************************************/ /* In a flat, single-heap build. The stream list is allocated with this - * structure. But kernel mode with a kernel allocator, it must be separately - * allocated using a user-space allocator. + * structure. But kernel mode with a kernel allocator, + * it must be separately allocated using a user-space allocator. */ #ifdef CONFIG_MM_KERNEL_HEAP FAR struct streamlist *tg_streamlist; #else - struct streamlist tg_streamlist; /* Holds C buffered I/O info */ + struct streamlist tg_streamlist; /* Holds C buffered I/O info */ #endif #endif #ifdef CONFIG_ARCH_ADDRENV - /* Address Environment ********************************************************/ + /* Address Environment ****************************************************/ - group_addrenv_t tg_addrenv; /* Task group address environment */ + group_addrenv_t tg_addrenv; /* Task group address environment */ #endif #ifdef CONFIG_MM_SHM - /* Shared Memory **************************************************************/ + /* Shared Memory **********************************************************/ - struct group_shm_s tg_shm; /* Task shared memory logic */ + struct group_shm_s tg_shm; /* Task shared memory logic */ #endif }; -/* struct tcb_s *****************************************************************/ +/* struct tcb_s *************************************************************/ -/* This is the common part of the task control block (TCB). The TCB is the heart - * of the NuttX task-control logic. Each task or thread is represented by a TCB - * that includes these common definitions. +/* This is the common part of the task control block (TCB). + * The TCB is the heart of the NuttX task-control logic. + * Each task or thread is represented by a TCB that includes these common + * definitions. */ struct tcb_s { - /* Fields used to support list management *************************************/ + /* Fields used to support list management *********************************/ - FAR struct tcb_s *flink; /* Doubly linked list */ + FAR struct tcb_s *flink; /* Doubly linked list */ FAR struct tcb_s *blink; - /* Task Group *****************************************************************/ + /* Task Group *************************************************************/ - FAR struct task_group_s *group; /* Pointer to shared task group data */ + FAR struct task_group_s *group; /* Pointer to shared task group data */ - /* Task Management Fields *****************************************************/ + /* Task Management Fields *************************************************/ - pid_t pid; /* This is the ID of the thread */ - start_t start; /* Thread start function */ - entry_t entry; /* Entry Point into the thread */ - uint8_t sched_priority; /* Current priority of the thread */ - uint8_t init_priority; /* Initial priority of the thread */ + pid_t pid; /* This is the ID of the thread */ + start_t start; /* Thread start function */ + entry_t entry; /* Entry Point into the thread */ + uint8_t sched_priority; /* Current priority of the thread */ + uint8_t init_priority; /* Initial priority of the thread */ #ifdef CONFIG_PRIORITY_INHERITANCE #if CONFIG_SEM_NNESTPRIO > 0 - uint8_t npend_reprio; /* Number of nested reprioritizations */ + uint8_t npend_reprio; /* Number of nested reprioritizations */ uint8_t pend_reprios[CONFIG_SEM_NNESTPRIO]; #endif - uint8_t base_priority; /* "Normal" priority of the thread */ + uint8_t base_priority; /* "Normal" priority of the thread */ #endif - uint8_t task_state; /* Current state of the thread */ + uint8_t task_state; /* Current state of the thread */ #ifdef CONFIG_SMP - uint8_t cpu; /* CPU index if running or assigned */ - cpu_set_t affinity; /* Bit set of permitted CPUs */ + uint8_t cpu; /* CPU index if running/assigned */ + cpu_set_t affinity; /* Bit set of permitted CPUs */ #endif - uint16_t flags; /* Misc. general status flags */ - int16_t lockcount; /* 0=preemptible (not-locked) */ + uint16_t flags; /* Misc. general status flags */ + int16_t lockcount; /* 0=preemptible (not-locked) */ #ifdef CONFIG_IRQCOUNT - int16_t irqcount; /* 0=Not in critical section */ + int16_t irqcount; /* 0=Not in critical section */ #endif #ifdef CONFIG_CANCELLATION_POINTS - int16_t cpcount; /* Nested cancellation point count */ + int16_t cpcount; /* Nested cancellation point count */ #endif - int16_t errcode; /* Used to pass error information */ + int16_t errcode; /* Used to pass error information */ #if CONFIG_RR_INTERVAL > 0 || defined(CONFIG_SCHED_SPORADIC) - int32_t timeslice; /* RR timeslice OR Sporadic budget */ - /* interval remaining */ + int32_t timeslice; /* RR timeslice OR Sporadic budget */ + /* interval remaining */ #endif #ifdef CONFIG_SCHED_SPORADIC - FAR struct sporadic_s *sporadic; /* Sporadic scheduling parameters */ + FAR struct sporadic_s *sporadic; /* Sporadic scheduling parameters */ #endif - struct wdog_s waitdog; /* All timed waits use this timer */ + struct wdog_s waitdog; /* All timed waits use this timer */ - /* Stack-Related Fields *******************************************************/ + /* Stack-Related Fields ***************************************************/ - size_t adj_stack_size; /* Stack size after adjustment */ - /* for hardware, processor, etc. */ - /* (for debug purposes only) */ - FAR void *stack_alloc_ptr; /* Pointer to allocated stack */ - /* Needed to deallocate stack */ - FAR void *stack_base_ptr; /* Adjusted initial stack pointer */ - /* after the frame has been removed */ - /* from the stack. */ + size_t adj_stack_size; /* Stack size after adjustment */ + /* for hardware, processor, etc. */ + /* (for debug purposes only) */ + FAR void *stack_alloc_ptr; /* Pointer to allocated stack */ + /* Needed to deallocate stack */ + FAR void *stack_base_ptr; /* Adjusted initial stack pointer */ + /* after the frame has been */ + /* removed from the stack. */ - /* External Module Support ****************************************************/ + /* External Module Support ************************************************/ #ifdef CONFIG_PIC FAR struct dspace_s *dspace; /* Allocated area for .bss and .data */ #endif - /* POSIX Semaphore Control Fields *********************************************/ + /* POSIX Semaphore Control Fields *****************************************/ - sem_t *waitsem; /* Semaphore ID waiting on */ + sem_t *waitsem; /* Semaphore ID waiting on */ - /* POSIX Signal Control Fields ************************************************/ + /* POSIX Signal Control Fields ********************************************/ - sigset_t sigprocmask; /* Signals that are blocked */ - sigset_t sigwaitmask; /* Waiting for pending signals */ - sq_queue_t sigpendactionq; /* List of pending signal actions */ - sq_queue_t sigpostedq; /* List of posted signals */ - siginfo_t sigunbinfo; /* Signal info when task unblocked */ + sigset_t sigprocmask; /* Signals that are blocked */ + sigset_t sigwaitmask; /* Waiting for pending signals */ + sq_queue_t sigpendactionq; /* List of pending signal actions */ + sq_queue_t sigpostedq; /* List of posted signals */ + siginfo_t sigunbinfo; /* Signal info when task unblocked */ - /* POSIX Named Message Queue Fields *******************************************/ + /* POSIX Named Message Queue Fields ***************************************/ #ifndef CONFIG_DISABLE_MQUEUE - FAR struct mqueue_inode_s *msgwaitq; /* Waiting for this message queue */ + FAR struct mqueue_inode_s *msgwaitq; /* Waiting for this message queue */ #endif - /* Robust mutex support *******************************************************/ + /* Robust mutex support ***************************************************/ #if !defined(CONFIG_DISABLE_PTHREAD) && !defined(CONFIG_PTHREAD_MUTEX_UNSAFE) - FAR struct pthread_mutex_s *mhead; /* List of mutexes held by thread */ + FAR struct pthread_mutex_s *mhead; /* List of mutexes held by thread */ #endif - /* Clean-up stack *************************************************************/ - -#ifdef CONFIG_PTHREAD_CLEANUP - /* tos - The index to the next available entry at the top of the stack. - * stack - The pre-allocated clean-up stack memory. - */ - - uint8_t tos; - struct pthread_cleanup_s stack[CONFIG_PTHREAD_CLEANUP_STACKSIZE]; -#endif - - /* Pre-emption monitor support ************************************************/ + /* Pre-emption monitor support ********************************************/ #ifdef CONFIG_SCHED_CRITMONITOR uint32_t premp_start; /* Time when preemption disabled */ @@ -714,67 +715,70 @@ struct tcb_s uint32_t run_max; /* Max time thread run */ #endif - /* State save areas ***********************************************************/ + /* State save areas *******************************************************/ - /* The form and content of these fields are platform-specific. */ + /* The form and content of these fields are platform-specific. */ - struct xcptcontext xcp; /* Interrupt register save area */ + struct xcptcontext xcp; /* Interrupt register save area */ #if CONFIG_TASK_NAME_SIZE > 0 - char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NUL terminator) */ + char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NUL terminator */ #endif }; -/* struct task_tcb_s ************************************************************/ +/* struct task_tcb_s ********************************************************/ -/* This is the particular form of the task control block (TCB) structure used by - * tasks (and kernel threads). There are two TCB forms: one for pthreads and - * one for tasks. Both share the common TCB fields (which must appear at the - * top of the structure) plus additional fields unique to tasks and threads. - * Having separate structures for tasks and pthreads adds some complexity, but - * saves memory in that it prevents pthreads from being burdened with the +/* This is the particular form of the task control block (TCB) structure used + * by tasks (and kernel threads). There are two TCB forms: one for pthreads + * and one for tasks. + * Both share the common TCB fields (which must appear at the top of the + * structure) plus additional fields unique to tasks and threads. + * Having separate structures for tasks and pthreads adds some complexity, + * but saves memory in that it prevents pthreads from being burdened with the * overhead required for tasks (and vice versa). */ struct task_tcb_s { - /* Common TCB fields **********************************************************/ + /* Common TCB fields ******************************************************/ struct tcb_s cmn; /* Common TCB fields */ - /* Task Management Fields *****************************************************/ + /* Task Management Fields *************************************************/ #ifdef CONFIG_SCHED_STARTHOOK starthook_t starthook; /* Task startup function */ FAR void *starthookarg; /* The argument passed to the function */ #endif - /* [Re-]start name + start-up parameters **************************************/ + /* [Re-]start name + start-up parameters **********************************/ - FAR char **argv; /* Name+start-up parameters */ + FAR char **argv; /* Name+start-up parameters */ }; -/* struct pthread_tcb_s *********************************************************/ +/* struct pthread_tcb_s *****************************************************/ -/* This is the particular form of the task control block (TCB) structure used by - * pthreads. There are two TCB forms: one for pthreads and one for tasks. Both - * share the common TCB fields (which must appear at the top of the structure) - * plus additional fields unique to tasks and threads. Having separate - * structures for tasks and pthreads adds some complexity, but saves memory in - * that it prevents pthreads from being burdened with the overhead required for - * tasks (and vice versa). +/* This is the particular form of the task control block (TCB) structure used + * by pthreads. There are two TCB forms: one for pthreads and one for tasks. + * Both share the common TCB fields (which must appear at the top of the + * structure) plus additional fields unique to tasks and threads. + * Having separate structures for tasks and pthreads adds some complexity, + * but saves memory in that it prevents pthreads from being burdened with + * the overhead required for tasks (and vice versa). */ #ifndef CONFIG_DISABLE_PTHREAD struct pthread_tcb_s { - /* Common TCB fields **********************************************************/ + /* Common TCB fields ******************************************************/ - struct tcb_s cmn; /* Common TCB fields */ + struct tcb_s cmn; /* Common TCB fields */ - /* Task Management Fields *****************************************************/ + /* Task Management Fields *************************************************/ + pthread_trampoline_t trampoline; /* User-space pthread startup function */ pthread_addr_t arg; /* Startup argument */ + pthread_exitroutine_t exit; /* User-space pthread exit function */ FAR void *joininfo; /* Detach-able info to support join */ }; #endif /* !CONFIG_DISABLE_PTHREAD */ @@ -785,9 +789,9 @@ typedef CODE void (*nxsched_foreach_t)(FAR struct tcb_s *tcb, FAR void *arg); #endif /* __ASSEMBLY__ */ -/******************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ #undef EXTERN @@ -811,11 +815,11 @@ EXTERN uint32_t g_crit_max[1]; #endif #endif /* CONFIG_SCHED_CRITMONITOR */ -/******************************************************************************** +/**************************************************************************** * Public Function Prototypes - ********************************************************************************/ + ****************************************************************************/ -/******************************************************************************** +/**************************************************************************** * Name: nxsched_self * * Description: @@ -823,11 +827,11 @@ EXTERN uint32_t g_crit_max[1]; * head of the ready-to-run list and manages access to the TCB from outside * of the sched/ sub-directory. * - ********************************************************************************/ + ****************************************************************************/ FAR struct tcb_s *nxsched_self(void); -/******************************************************************************** +/**************************************************************************** * Name: nxsched_foreach * * Description: @@ -848,11 +852,11 @@ FAR struct tcb_s *nxsched_self(void); * Returned Value: * None * - ********************************************************************************/ + ****************************************************************************/ void nxsched_foreach(nxsched_foreach_t handler, FAR void *arg); -/******************************************************************************** +/**************************************************************************** * Name: nxsched_get_tcb * * Description: @@ -866,25 +870,25 @@ void nxsched_foreach(nxsched_foreach_t handler, FAR void *arg); * should establish the critical section BEFORE calling this function and * hold that critical section as long as necessary. * - ********************************************************************************/ + ****************************************************************************/ FAR struct tcb_s *nxsched_get_tcb(pid_t pid); -/******************************************************************************** +/**************************************************************************** * Name: nxsched_releasepid * * Description: * When a task is destroyed, this function must be called to make its * process ID available for re-use. * - ********************************************************************************/ + ****************************************************************************/ int nxsched_release_tcb(FAR struct tcb_s *tcb, uint8_t ttype); -/* File system helpers **********************************************************/ +/* File system helpers ******************************************************/ -/* These functions all extract lists from the group structure associated with the - * currently executing task. +/* These functions all extract lists from the group structure associated with + * the currently executing task. */ FAR struct filelist *nxsched_get_files(void); @@ -892,7 +896,7 @@ FAR struct filelist *nxsched_get_files(void); FAR struct streamlist *nxsched_get_streams(void); #endif /* CONFIG_FILE_STREAM */ -/******************************************************************************** +/**************************************************************************** * Name: nxtask_init * * Description: @@ -928,13 +932,13 @@ FAR struct streamlist *nxsched_get_streams(void); * nxsched_release_tcb() to free the TCB (which could be in most any * state). * - ********************************************************************************/ + ****************************************************************************/ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, FAR void *stack, uint32_t stack_size, main_t entry, FAR char * const argv[]); -/******************************************************************************** +/**************************************************************************** * Name: nxtask_uninit * * Description: @@ -951,11 +955,11 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, * Returned Value: * OK on success; negative error value on failure appropriately. * - ********************************************************************************/ + ****************************************************************************/ void nxtask_uninit(FAR struct task_tcb_s *tcb); -/******************************************************************************** +/**************************************************************************** * Name: nxtask_activate * * Description: @@ -970,11 +974,11 @@ void nxtask_uninit(FAR struct task_tcb_s *tcb); * Returned Value: * None * - ********************************************************************************/ + ****************************************************************************/ void nxtask_activate(FAR struct tcb_s *tcb); -/******************************************************************************** +/**************************************************************************** * Name: nxtask_starthook * * Description: @@ -991,14 +995,14 @@ void nxtask_activate(FAR struct tcb_s *tcb); * Returned Value: * None * - ********************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SCHED_STARTHOOK void nxtask_starthook(FAR struct task_tcb_s *tcb, starthook_t starthook, FAR void *arg); #endif -/******************************************************************************** +/**************************************************************************** * Name: nxtask_startup * * Description: @@ -1012,20 +1016,20 @@ void nxtask_starthook(FAR struct task_tcb_s *tcb, starthook_t starthook, * Returned Value: * None. This function does not return. * - ********************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_BUILD_KERNEL void nxtask_startup(main_t entrypt, int argc, FAR char *argv[]); #endif -/******************************************************************************** +/**************************************************************************** * Internal vfork support. The overall sequence is: * * 1) User code calls vfork(). vfork() is provided in architecture-specific * code. * 2) vfork()and calls nxtask_setup_vfork(). - * 3) nxtask_setup_vfork() allocates and configures the child task's TCB. This - * consists of: + * 3) nxtask_setup_vfork() allocates and configures the child task's TCB. + * This consists of: * - Allocation of the child task's TCB. * - Initialization of file descriptors and streams * - Configuration of environment variables @@ -1038,15 +1042,16 @@ void nxtask_startup(main_t entrypt, int argc, FAR char *argv[]); * 5) vfork() then calls nxtask_start_vfork() * 6) nxtask_start_vfork() then executes the child thread. * - * nxtask_abort_vfork() may be called if an error occurs between steps 3 and 6. + * nxtask_abort_vfork() may be called if an error occurs between + * steps 3 and 6. * - ********************************************************************************/ + ****************************************************************************/ FAR struct task_tcb_s *nxtask_setup_vfork(start_t retaddr); pid_t nxtask_start_vfork(FAR struct task_tcb_s *child); void nxtask_abort_vfork(FAR struct task_tcb_s *child, int errcode); -/******************************************************************************** +/**************************************************************************** * Name: group_exitinfo * * Description: @@ -1064,18 +1069,19 @@ void nxtask_abort_vfork(FAR struct task_tcb_s *child, int errcode); * 0 (OK) is returned on success and a negated errno is returned on * failure. * - ********************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_BINFMT_LOADABLE struct binary_s; /* Forward reference */ int group_exitinfo(pid_t pid, FAR struct binary_s *bininfo); #endif -/******************************************************************************** +/**************************************************************************** * Name: nxsched_resume_scheduler * * Description: - * Called by architecture specific implementations that block task execution. + * Called by architecture specific implementations that block task + * execution. * This function prepares the scheduler for the thread that is about to be * restarted. * @@ -1085,7 +1091,7 @@ int group_exitinfo(pid_t pid, FAR struct binary_s *bininfo); * Returned Value: * None * - ********************************************************************************/ + ****************************************************************************/ #if CONFIG_RR_INTERVAL > 0 || defined(CONFIG_SCHED_RESUMESCHEDULER) void nxsched_resume_scheduler(FAR struct tcb_s *tcb); @@ -1093,13 +1099,14 @@ void nxsched_resume_scheduler(FAR struct tcb_s *tcb); # define nxsched_resume_scheduler(tcb) #endif -/******************************************************************************** +/**************************************************************************** * Name: nxsched_suspend_scheduler * * Description: - * Called by architecture specific implementations to resume task execution. - * This function performs scheduler operations for the thread that is about to - * be suspended. + * Called by architecture specific implementations to resume task + * execution. + * This function performs scheduler operations for the thread that is about + * to be suspended. * * Input Parameters: * tcb - The TCB of the thread to be restarted. @@ -1107,7 +1114,7 @@ void nxsched_resume_scheduler(FAR struct tcb_s *tcb); * Returned Value: * None * - ********************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SCHED_SUSPENDSCHEDULER void nxsched_suspend_scheduler(FAR struct tcb_s *tcb); @@ -1115,7 +1122,7 @@ void nxsched_suspend_scheduler(FAR struct tcb_s *tcb); # define nxsched_suspend_scheduler(tcb) #endif -/******************************************************************************** +/**************************************************************************** * Name: nxsched_get_param * * Description: @@ -1141,12 +1148,12 @@ void nxsched_suspend_scheduler(FAR struct tcb_s *tcb); * This function can fail if param is null (EINVAL) or if pid does * not correspond to any task (ESRCH). * - ********************************************************************************/ + ****************************************************************************/ struct sched_param; /* Forward reference */ int nxsched_get_param (pid_t pid, FAR struct sched_param *param); -/******************************************************************************** +/**************************************************************************** * Name: nxsched_set_param * * Description: @@ -1178,12 +1185,12 @@ int nxsched_get_param (pid_t pid, FAR struct sched_param *param); * EPERM The calling task does not have appropriate privileges. * ESRCH The task whose ID is pid could not be found. * - ********************************************************************************/ + ****************************************************************************/ struct sched_param; /* Forward reference */ int nxsched_set_param(pid_t pid, FAR const struct sched_param *param); -/******************************************************************************** +/**************************************************************************** * Name: nxsched_get_scheduler * * Description: @@ -1210,11 +1217,11 @@ int nxsched_set_param(pid_t pid, FAR const struct sched_param *param); * * ESRCH The task whose ID is pid could not be found. * - ********************************************************************************/ + ****************************************************************************/ int nxsched_get_scheduler(pid_t pid); -/******************************************************************************** +/**************************************************************************** * Name: nxsched_set_scheduler * * Description: @@ -1246,12 +1253,12 @@ int nxsched_get_scheduler(pid_t pid); * EINVAL The scheduling policy is not one of the recognized policies. * ESRCH The task whose ID is pid could not be found. * - ********************************************************************************/ + ****************************************************************************/ int nxsched_set_scheduler(pid_t pid, int policy, FAR const struct sched_param *param); -/******************************************************************************** +/**************************************************************************** * Name: nxsched_get_affinity * * Description: @@ -1278,13 +1285,13 @@ int nxsched_set_scheduler(pid_t pid, int policy, * * ESRCH The task whose ID is pid could not be found. * - ********************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SMP int nxsched_get_affinity(pid_t pid, size_t cpusetsize, FAR cpu_set_t *mask); #endif -/******************************************************************************** +/**************************************************************************** * Name: nxsched_set_affinity * * Description: @@ -1314,14 +1321,14 @@ int nxsched_get_affinity(pid_t pid, size_t cpusetsize, FAR cpu_set_t *mask); * * ESRCH The task whose ID is pid could not be found. * - ********************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SMP int nxsched_set_affinity(pid_t pid, size_t cpusetsize, FAR const cpu_set_t *mask); #endif -/******************************************************************************** +/**************************************************************************** * Name: nxsched_get_stackinfo * * Description: @@ -1339,13 +1346,13 @@ int nxsched_set_affinity(pid_t pid, size_t cpusetsize, * -EACCES The calling thread does not have privileges to access the * stack of the thread associated with the pid. * - ********************************************************************************/ + ****************************************************************************/ int nxsched_get_stackinfo(pid_t pid, FAR struct stackinfo_s *stackinfo); -/******************************************************************************** +/**************************************************************************** * Name: nx_wait/nx_waitid/nx_waitpid - ********************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SCHED_WAITPID pid_t nx_wait(FAR int *stat_loc); diff --git a/include/nuttx/sdio.h b/include/nuttx/sdio.h index 71edb7dbe20..04f42183936 100644 --- a/include/nuttx/sdio.h +++ b/include/nuttx/sdio.h @@ -199,7 +199,7 @@ # define SD_ACMDIDX52 52 /* IO_RW_DIRECT: (SDIO only) * -R5 response, 23:16=status 15:8=data */ # define SD_ACMDIDX53 53 /* IO_RW_EXTENDED: (SDIO only) - * -R5 response, 23:16=status */ + * -Addressed data transfer command, R5 response, 23:16=status */ /* Response Encodings: * @@ -316,8 +316,9 @@ #define SD_ACMD49 (SD_ACMDIDX49 |MMCSD_R1_RESPONSE |MMCSD_NODATAXFR) #define SD_ACMD51 (SD_ACMDIDX51 |MMCSD_R1_RESPONSE |MMCSD_RDDATAXFR) #define SD_ACMD52 (SD_ACMDIDX52 |MMCSD_R5_RESPONSE |MMCSD_NODATAXFR) -#define SD_ACMD52ABRT (SD_ACMDIDX52 |MMCSD_R1_RESPONSE |MMCSD_NODATAXFR|MMCSD_STOPXFR) -#define SD_ACMD53 (SD_ACMDIDX53 |MMCSD_R5_RESPONSE |MMCSD_NODATAXFR) +#define SD_ACMD52ABRT (SD_ACMDIDX52 |MMCSD_R1_RESPONSE |MMCSD_NODATAXFR |MMCSD_STOPXFR) +#define SD_ACMD53RD (SD_ACMDIDX53 |MMCSD_R5_RESPONSE |MMCSD_RDDATAXFR) +#define SD_ACMD53WR (SD_ACMDIDX53 |MMCSD_R5_RESPONSE |MMCSD_WRDATAXFR) /* SDIO Card Common Control Registers definitions * see https://www.sdcard.org/developers/overview/sdio/ diff --git a/include/nuttx/sensors/aht10.h b/include/nuttx/sensors/aht10.h index 8048de234d0..86352c1ec28 100644 --- a/include/nuttx/sensors/aht10.h +++ b/include/nuttx/sensors/aht10.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/sensors/aht10.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: kyChu + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/spi/qspi.h b/include/nuttx/spi/qspi.h index f3cb27d32bb..51c95476ea2 100644 --- a/include/nuttx/spi/qspi.h +++ b/include/nuttx/spi/qspi.h @@ -228,10 +228,10 @@ enum qspi_mode_e { - QSPIDEV_MODE0 = 0, /* CPOL=0 CHPHA=0 */ - QSPIDEV_MODE1, /* CPOL=0 CHPHA=1 */ - QSPIDEV_MODE2, /* CPOL=1 CHPHA=0 */ - QSPIDEV_MODE3 /* CPOL=1 CHPHA=1 */ + QSPIDEV_MODE0 = 0, /* CPOL=0 CPHA=0 */ + QSPIDEV_MODE1, /* CPOL=0 CPHA=1 */ + QSPIDEV_MODE2, /* CPOL=1 CPHA=0 */ + QSPIDEV_MODE3 /* CPOL=1 CPHA=1 */ }; /* This structure describes one command transfer */ diff --git a/include/nuttx/spi/slave.h b/include/nuttx/spi/slave.h index c6fa92c9aef..44c07257b98 100644 --- a/include/nuttx/spi/slave.h +++ b/include/nuttx/spi/slave.h @@ -45,115 +45,116 @@ /* Access macros ************************************************************/ /**************************************************************************** - * Name: SPI_SCTRLR_BIND + * Name: SPIS_CTRLR_BIND * * Description: * Bind the SPI slave device interface to the SPI slave controller - * interface and configure the SPI interface. Upon return, the SPI + * interface and configure the SPI interface. Upon return, the SPI * slave controller driver is fully operational and ready to perform * transfers. * * Input Parameters: - * sctrlr - SPI slave controller interface instance - * sdev - SPI slave device interface instance - * mode - The SPI mode requested - * nbits - The number of bits requests. - * If value is greater > 0 then it implies MSB first - * If value is below < 0, then it implies LSB first with -nbits + * ctrlr - SPI Slave controller interface instance + * dev - SPI Slave device interface instance + * mode - The SPI Slave mode requested + * nbits - The number of bits requested. + * If value is greater than 0, then it implies MSB first + * If value is less than 0, then it implies LSB first with -nbits * * Returned Value: - * none + * None. * ****************************************************************************/ -#define SPI_SCTRLR_BIND(c,d,m,n) ((c)->ops->bind(c,d,m,n)) +#define SPIS_CTRLR_BIND(c,d,m,n) ((c)->ops->bind(c,d,m,n)) /**************************************************************************** - * Name: SPI_SCTRLR_UNBIND + * Name: SPIS_CTRLR_UNBIND * * Description: * Un-bind the SPI slave device interface from the SPI slave controller - * interface. Reset the SPI interface and restore the SPI slave - * controller driver to its initial state, + * interface. Reset the SPI interface and restore the SPI slave + * controller driver to its initial state. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * none + * None. * ****************************************************************************/ -#define SPI_SCTRLR_UNBIND(c) ((c)->ops->unbind(c)) +#define SPIS_CTRLR_UNBIND(c) ((c)->ops->unbind(c)) /**************************************************************************** - * Name: SPI_SCTRLR_ENQUEUE + * Name: SPIS_CTRLR_ENQUEUE * * Description: - * Enqueue the next value to be shifted out from the interface. This adds + * Enqueue the next value to be shifted out from the interface. This adds * the word the controller driver for a subsequent transfer but has no - * effect on any in-process or currently "committed" transfers + * effect on any in-process or currently "committed" transfers. * * Input Parameters: - * sctrlr - SPI slave controller interface instance - * data - Pointer to the command/data mode data to be shifted out. - * The data width must be aligned to the nbits parameter which was - * previously provided to the bind() methods. - * len - Number of units of "nbits" wide to enqueue, - * "nbits" being the data width given in "bind" + * ctrlr - SPI Slave controller interface instance + * data - Pointer to the command/data mode data to be shifted out. + * The data width must be aligned to the nbits parameter which was + * previously provided to the bind() method. + * len - Number of units of "nbits" wide to enqueue, + * "nbits" being the data width previously provided to the bind() + * method. * * Returned Value: * Number of data items successfully queued, or a negated errno: - * - "len" if all the data was successfully queued - * - "0..len-1" if queue is full - * - "-errno" in any other error + * - "len" if all the data was successfully queued + * - "0..len-1" if queue is full + * - "-errno" in any other error * ****************************************************************************/ -#define SPI_SCTRLR_ENQUEUE(c,v,l) ((c)->ops->enqueue(c,v,l)) +#define SPIS_CTRLR_ENQUEUE(c,v,l) ((c)->ops->enqueue(c,v,l)) /**************************************************************************** - * Name: SPI_SCTRLR_QFULL + * Name: SPIS_CTRLR_QFULL * * Description: * Return true if the queue is full or false if there is space to add an * additional word to the queue. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * true if the output queue is full + * true if the output queue is full, false otherwise. * ****************************************************************************/ -#define SPI_SCTRLR_QFULL(c) ((c)->ops->qfull(c)) +#define SPIS_CTRLR_QFULL(c) ((c)->ops->qfull(c)) /**************************************************************************** - * Name: SPI_SCTRLR_QFLUSH + * Name: SPIS_CTRLR_QFLUSH * * Description: - * Discard all saved values in the output queue. On return from this - * function the output queue will be empty. Any in-progress or otherwise + * Discard all saved values in the output queue. On return from this + * function the output queue will be empty. Any in-progress or otherwise * "committed" output values may not be flushed. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * None + * None. * ****************************************************************************/ -#define SPI_SCTRLR_QFLUSH(c) ((c)->ops->qflush(c)) +#define SPIS_CTRLR_QFLUSH(c) ((c)->ops->qflush(c)) /**************************************************************************** - * Name: SPI_SCTRLR_QPOLL + * Name: SPIS_CTRLR_QPOLL * * Description: * Tell the controller to output all the receive queue data. * - * This will cause 1..n SPI_SDEV_RECEIVE calls back to the slave device, + * This will cause 1..n SPIS_DEV_RECEIVE calls back to the slave device, * offering blocks of data to the device. From each call, the slave device * driver will return the number of data units it accepted/read out. * @@ -174,109 +175,109 @@ * of bytes that was offered to each receive call. * * Input Parameters: - * sctrlr - SPI slave controller interface instance + * ctrlr - SPI Slave controller interface instance * * Returned Value: - * Number of units of width "nbits" left in the rx queue. If the device - * accepted all the data, the return value will be 0 + * Number of units of width "nbits" left in the RX queue. If the device + * accepted all the data, the return value will be 0. * ****************************************************************************/ -#define SPI_SCTRLR_QPOLL(c) ((c)->ops->qpoll(c)) +#define SPIS_CTRLR_QPOLL(c) ((c)->ops->qpoll(c)) /**************************************************************************** - * Name: SPI_SDEV_SELECT + * Name: SPIS_DEV_SELECT * * Description: - * This is a SPI device callback that used when the SPI device controller + * This is a SPI device callback that is used when the SPI controller * driver detects any change in the chip select pin. * * Input Parameters: - * sdev - SPI device interface instance - * selected - True: chip select is low (selected); + * dev - SPI Slave device interface instance + * selected - Indicates whether the chip select is in active state * * Returned Value: - * none + * None. * * Assumptions: - * May be called from an interrupt handler. Processing should be as + * May be called from an interrupt handler. Processing should be as * brief as possible. * ****************************************************************************/ -#define SPI_SDEV_SELECT(d,s) ((d)->ops->select(d,s)) +#define SPIS_DEV_SELECT(d,s) ((d)->ops->select(d,s)) /**************************************************************************** - * Name: SPI_SDEV_CMDDATA + * Name: SPIS_DEV_CMDDATA * * Description: - * This is a SPI device callback that used when the SPI device controller - * driver detects any change command/data condition. + * This is a SPI device callback that is used when the SPI controller + * driver detects any change in the command/data condition. * - * Normally only LCD devices distinguish command and data. For devices + * Normally only LCD devices distinguish command and data. For devices * that do not distinguish between command and data, this method may be - * a stub.; For devices that do make that distinction, they should treat - * all subsequent calls to enqueue() or rece() appropriately for the + * a stub. For devices that do make that distinction, they should treat + * all subsequent calls to getdata() or receive() appropriately for the * current command/data selection. * * Input Parameters: - * sdev - SPI device interface instance + * dev - SPI Slave device interface instance * data - True: Data is selected * * Returned Value: - * none + * None. * * Assumptions: - * May be called from an interrupt handler. Processing should be as + * May be called from an interrupt handler. Processing should be as * brief as possible. * ****************************************************************************/ -#define SPI_SDEV_CMDDATA(d,i) ((d)->ops->cmddata(d,i)) +#define SPIS_DEV_CMDDATA(d,i) ((d)->ops->cmddata(d,i)) /**************************************************************************** - * Name: SPI_SDEV_GETDATA + * Name: SPIS_DEV_GETDATA * * Description: - * This is a SPI device callback that used when the SPI device controller - * requires data be shifted out at the next leading clock edge. This + * This is a SPI device callback that is used when the SPI controller + * requires data be shifted out at the next leading clock edge. This * is necessary to "prime the pump" so that the SPI controller driver * can keep pace with the shifted-in data. * * The SPI controller driver will prime for both command and data * transfers as determined by a preceding call to the device cmddata() - * method. Normally only LCD devices distinguish command and data. + * method. Normally only LCD devices distinguish command and data. * * Input Parameters: - * sdev - SPI device interface instance + * dev - SPI Slave device interface instance * data - Pointer to the data buffer pointer to be shifed out. * The device will set the data buffer pointer to the actual data * * Returned Value: - * The number of data bytes to be shifted out from the data buffer + * The number of data units to be shifted out from the data buffer. * * Assumptions: * May be called from an interrupt handler and the response is usually - * time critical. + * time-critical. * ****************************************************************************/ -#define SPI_SDEV_GETDATA(d,v) ((d)->ops->getdata(d,v)) +#define SPIS_DEV_GETDATA(d,v) ((d)->ops->getdata(d,v)) /**************************************************************************** - * Name: SPI_SDEV_RECEIVE + * Name: SPIS_DEV_RECEIVE * * Description: - * This is a SPI device callback that used when the SPI device controller - * receives a new value shifted in and requires the next value to be - * shifted out. Notice that these values my be out of synchronization by - * several words. + * This is a SPI device callback that is used when the SPI controller + * receives a new value shifted in. Notice that these values may be out of + * synchronization by several words. * * Input Parameters: - * sdev - SPI device interface instance + * dev - SPI Slave device interface instance * data - Pointer to the new data that has been shifted in * len - Length of the new data in units of nbits wide, - * nbits being the data width given in "bind" + * nbits being the data width previously provided to the bind() + * method. * * Returned Value: * Number of units accepted by the device. In other words, @@ -284,13 +285,13 @@ * * Assumptions: * May be called from an interrupt handler and in time-critical - * circumstances. A good implementation might just add the newly + * circumstances. A good implementation might just add the newly * received word to a queue, post a processing task, and return as * quickly as possible to avoid any data overrun problems. * ****************************************************************************/ -#define SPI_SDEV_RECEIVE(d,v,l) ((d)->ops->receive(d,v,l)) +#define SPIS_DEV_RECEIVE(d,v,l) ((d)->ops->receive(d,v,l)) /**************************************************************************** * Public Types @@ -298,15 +299,15 @@ /* There are two interfaces defined for the implementation of SPI slave: * - * 1) struct spi_sctrlr_s: Defines one interface between the SPI - * slave device and the SPI slave controller hardware. This interface + * 1) struct spi_slave_ctrlr_s: Defines one interface between the SPI + * slave device and the SPI slave controller hardware. This interface * is implemented by the SPI slave device controller lower-half driver * and is provided to the SPI slave device driver when that driver - * is initialized. That SPI slave device initialization function is - * unique to the SPI slave implementation. The prototype is probably + * is initialized. That SPI slave device initialization function is + * unique to the SPI slave implementation. The prototype is probably * something like: * - * FAR struct spi_sctrlr_s *xyz_spi_slave_initialize(int port); + * FAR struct spi_slave_ctrlr_s *xyz_spi_slave_initialize(int port); * * Given an SPI port number, this function returns an instance of the * SPI slave controller interface. @@ -315,35 +316,36 @@ * appear in a header file associated with the specific SPI slave * implementation. * - * 2) struct spi_sdev_s: Defines the second interface between the SPI - * slave device and the SPI slave controller hardware. This interface - * is implemented by the SPI slave device. The slave device passes this - * interface to the struct spi_sctrlr_s during initialization - * be calling the bind() method of the struct spi_sctrlr_s + * 2) struct spi_slave_dev_s: Defines the second interface between the SPI + * slave device and the SPI slave controller hardware. This interface + * is implemented by the SPI slave device. The slave device passes this + * interface to the struct spi_slave_ctrlr_s during initialization + * by calling the bind() method of the struct spi_slave_ctrlr_s * interface. * * The basic initialization steps are: * * 1) Board-specific logic calls board- or chip-specific logic to create an - * instance of the SPI slave controller interface, struct spi_sctrlr_s. + * instance of the SPI slave controller interface, + * struct spi_slave_ctrlr_s. * * 2) Board-specific logic then calls up_dev_initialize() to initialize - * the SPI slave device. The board-specific logic passes the instance - * of struct spi_sctrlr_s to support the initialization. + * the SPI slave device. The board-specific logic passes the instance + * of struct spi_slave_ctrlr_s to support the initialization. * * 3) The SPI slave device driver creates and initializes an instance of - * struct spi_sdev_s; it passes this instance to the bind() method of + * struct spi_slave_dev_s; it passes this instance to the bind() method of * of the SPI slave controller interface. * - * 4) The SPI slave controller will (1) call the slaved device's select() + * 4) The SPI slave controller will (1) call the slave device's select() * and cmddata() methods to indicate the initial state of the chip select * and any command/data selection, then (2) call the slave device's - * getdata() method to get the value that will be shifted out the SPI - * clock is detected. The kind of data returned the getdata() method - * may be contingent on the current command/data setting reported the - * device cmddata() method. The driver may enqueue additional words - * to be shifted out at any time by The calling the SPI slave - * controller's enqueue() method. + * getdata() method to get the value that will be shifted out once the SPI + * clock is detected. The kind of data returned by the getdata() method + * may be contingent on the current command/data setting reported by the + * device cmddata() method. The driver may enqueue additional words + * to be shifted out at any time by calling the SPI slave controller's + * enqueue() method. * * 5) Upon return from the bind method, the SPI slave controller will be * fully "armed" and ready to begin normal SPI data transfers. @@ -351,21 +353,21 @@ * A typical (non-DMA) data transfer proceeds as follows: * * 1) Internally, the SPI slave driver detects that the SPI chip select - * has gone low, selecting this device for data transfer. The SPI - * slave controller will notify the slave device by called its + * has gone low, selecting this device for data transfer. The SPI + * slave controller will notify the slave device by calling its * select() method. * - * 2) If a change in the command/data state changes any time before, - * during, or after the chip is selected, that new command/data state - * will reported to the device driver via the cmddata() method. + * 2) If the command/data state changes any time before, during, or after the + * chip is selected, that new command/data state will be reported to the + * device driver via the cmddata() method. * * 3) As the first word is shifted in, the command or data word obtained - * by the initial call to getdata() will be shifted out. As soon as + * by the initial call to getdata() will be shifted out. As soon as * the clock is detected, the SPI controller driver will call the * getdata() method again to get a default second word to be shifted - * out. NOTES: (1) the SPI slave device has only one word in bit + * out. NOTES: (1) the SPI slave device has only one word in bit * times to provide this value! (2) The SPI device probably cannot - * really output anything meaning until it receives a decodes the + * really output anything meaningful until it receives and decodes the * first word received from the master. * * 4) When the first word from the master is shifted in, the SPI @@ -377,8 +379,8 @@ * data from the SPI device to the master, the SPI device driver * should call the controller's enqueue() method to provide the next * value(s) to be shifted out. If the SPI device responds with this - * value before clocking begins for the next word, that that value - * will be used. Otherwise, the value obtained from getdata() in + * value before clocking begins for the next word, then that value + * will be used. Otherwise, the value obtained from getdata() in * step 3 will be shifted out. * * 5) The SPI device's receive() method will be called in a similar @@ -387,9 +389,9 @@ * For the case of bi-directional data transfer or of a uni-directional * transfer of data from the SPI device to the master, the SPI device * driver can call the enqueue() methods as it has new data to be shifted - * out. The goal of the SPI device driver for this kind of transfer is + * out. The goal of the SPI device driver for this kind of transfer is * to supply valid output data at such a rate that data underruns do not - * occur. In the event of a data underrun, the SPI slave controller + * occur. In the event of a data underrun, the SPI slave controller * driver will fallback to the default output value obtained from the * last getdata() call. * @@ -407,14 +409,14 @@ * the SPI device driver. * * 6) The activity of 5) will continue until the master raises the chip - * select signal. In that case, the SPI slave controller driver will - * again call the SPI device's select() method. At this point, the SPI - * controller driver may have several words enqueued. It will not + * select signal. In that case, the SPI slave controller driver will + * again call the SPI device's select() method. At this point, the SPI + * controller driver may have several words enqueued. It will not * discard these unless the SPI device driver calls the qflush() * method. * * Some master side implementations may simply tie the chip select signal - * to ground if there are no other devices on the SPI bus. In that case, + * to ground if there are no other devices on the SPI bus. In that case, * the initial indication of chip selected will be the only call to the * select() method that is made. * @@ -426,105 +428,105 @@ * * A typical DMA data transfer processes as follows: * To be provided -- I do not have a design in mind to support DMA on the - * Slave side. The design might be very complex because: + * Slave side. The design might be very complex because: * * 1) You need DMA buffers of fixed size, but you cannot know the size of a * transfer in advance, it could be much larger than your buffer or much - * smaller. The DMA would fail in either case. + * smaller. The DMA would fail in either case. * - * 2) You cannot setup the DMA before the transfer. In most SPI protocols, + * 2) You cannot setup the DMA before the transfer. In most SPI protocols, * the first word send is a command to read or write something following - * by a sequence of transfers to implement the write. So you have very, + * by a sequence of transfers to implement the write. So you have very, * very limited time window to setup the correct DMA to respond to the - * command. I am not certain that it can be done reliably. + * command. I am not certain that it can be done reliably. * * Inserting dummy words into the protocol between the first command word * and the remaining data transfer could allow time to set up the DMA. * * 3) I mentioned that you do not know the size of the transfer in advance. - * If you set up the DMA to terminate to soon, then you lose the last part - * of the transfer. If you set the DMA up to be too large, then you will - * get no indication when the transfer completes. + * If you set up the DMA to terminate too soon, then you lose the last + * part of the transfer. If you set the DMA up to be too large, then you + * will get no indication when the transfer completes. * * The chip select going high would be one possibility to detect the end - * of a transfer. You could cancel a DMA in progress if the CS changes, - * but I do not know if that would work. If there is only one device on + * of a transfer. You could cancel a DMA in progress if the CS changes, + * but I do not know if that would work. If there is only one device on * the SPI bus, then most board designs will save a pin and simply tie CS - * to ground. So the CS is not always a reliable indicator of when the + * to ground. So the CS is not always a reliable indicator of when the * transfer completes. * - * 4) The option is to use a timer but that would really slow down the - * transfers if each DMA has to end with a timeout. It would be faster - * non-DMA transfers. + * 4) Another option is to use a timer but that would really slow down the + * transfers if each DMA has to end with a timeout. It would be faster + * to perform non-DMA transfers. * - * If the device as a very restricted protocol, like just register reads - * and writes, then it might possible to implement DMA. However, that + * If the device has a very restricted protocol, like just register reads + * and writes, then it might be possible to implement DMA. However, that * solution would not be general and probably not an appropriate part of - * a general OS. But if the interface is unpredictable, such as reading/ - * variable amounts of data from FLASH, there is more risk. A general + * a general OS. But if the interface is unpredictable, such as reading + * variable amounts of data from FLASH, there is more risk. A general * solution might not be possible. */ -enum spi_smode_e +enum spi_slave_mode_e { - SPISLAVE_MODE0 = 0, /* CPOL=0 CHPHA=0 */ - SPISLAVE_MODE1, /* CPOL=0 CHPHA=1 */ - SPISLAVE_MODE2, /* CPOL=1 CHPHA=0 */ - SPISLAVE_MODE3 /* CPOL=1 CHPHA=1 */ + SPISLAVE_MODE0 = 0, /* CPOL=0 CPHA=0 */ + SPISLAVE_MODE1, /* CPOL=0 CPHA=1 */ + SPISLAVE_MODE2, /* CPOL=1 CPHA=0 */ + SPISLAVE_MODE3 /* CPOL=1 CPHA=1 */ }; /* The SPI slave controller driver vtable */ -struct spi_sctrlr_s; /* Forward reference */ -struct spi_sdev_s; /* Forward reference */ +struct spi_slave_ctrlr_s; /* Forward reference */ +struct spi_slave_dev_s; /* Forward reference */ -struct spi_sctrlrops_s +struct spi_slave_ctrlrops_s { - CODE void (*bind)(FAR struct spi_sctrlr_s *sctrlr, - FAR struct spi_sdev_s *sdev, enum spi_smode_e mode, - int nbits); - CODE void (*unbind)(FAR struct spi_sctrlr_s *sctrlr); - CODE int (*enqueue)(FAR struct spi_sctrlr_s *sctrlr, - FAR const void *data, size_t nwords); - CODE bool (*qfull)(FAR struct spi_sctrlr_s *sctrlr); - CODE void (*qflush)(FAR struct spi_sctrlr_s *sctrlr); - CODE size_t (*qpoll)(FAR struct spi_sctrlr_s *sctrlr); + CODE void (*bind)(FAR struct spi_slave_ctrlr_s *ctrlr, + FAR struct spi_slave_dev_s *sdev, + enum spi_slave_mode_e mode, int nbits); + CODE void (*unbind)(FAR struct spi_slave_ctrlr_s *ctrlr); + CODE int (*enqueue)(FAR struct spi_slave_ctrlr_s *ctrlr, + FAR const void *data, size_t nwords); + CODE bool (*qfull)(FAR struct spi_slave_ctrlr_s *ctrlr); + CODE void (*qflush)(FAR struct spi_slave_ctrlr_s *ctrlr); + CODE size_t (*qpoll)(FAR struct spi_slave_ctrlr_s *ctrlr); }; -/* SPI slave controller private data. This structure only defines the - * initial fields of the structure visible to the SPI device driver. The +/* SPI slave controller private data. This structure only defines the + * initial fields of the structure visible to the SPI device driver. The * specific implementation may add additional, device specific fields after * the vtable structure pointer. */ -struct spi_sctrlr_s +struct spi_slave_ctrlr_s { - FAR const struct spi_sctrlrops_s *ops; + FAR const struct spi_slave_ctrlrops_s *ops; /* Private SPI slave controller driver data may follow */ }; /* The SPI slave device driver vtable */ -struct spi_sdevops_s +struct spi_slave_devops_s { - CODE void (*select)(FAR struct spi_sdev_s *sdev, bool selected); - CODE void (*cmddata)(FAR struct spi_sdev_s *sdev, bool data); - CODE size_t (*getdata)(FAR struct spi_sdev_s *sdev, + CODE void (*select)(FAR struct spi_slave_dev_s *sdev, bool selected); + CODE void (*cmddata)(FAR struct spi_slave_dev_s *sdev, bool data); + CODE size_t (*getdata)(FAR struct spi_slave_dev_s *sdev, FAR const void **data); - CODE size_t (*receive)(FAR struct spi_sdev_s *sdev, + CODE size_t (*receive)(FAR struct spi_slave_dev_s *sdev, FAR const void *data, size_t nwords); }; -/* SPI slave device private data. This structure only defines the initial - * fields of the structure visible to the SPI slave controller driver. The +/* SPI slave device private data. This structure only defines the initial + * fields of the structure visible to the SPI slave controller driver. The * specific implementation may add additional, device specific fields after * the vtable structure pointer. */ -struct spi_sdev_s +struct spi_slave_dev_s { - FAR const struct spi_sdevops_s *ops; + FAR const struct spi_slave_devops_s *ops; /* Private SPI slave device driver data may follow */ }; @@ -533,6 +535,36 @@ struct spi_sdev_s * Public Data ****************************************************************************/ +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_slave_register + * + * Description: + * Register the SPI Slave character device driver as 'devpath'. + * + * Input Parameters: + * ctrlr - An instance of the SPI Slave interface to use to communicate + * with the SPI Slave device + * bus - The SPI Slave bus number. This will be used as the SPI device + * minor number. The SPI Slave character device will be + * registered as /dev/spislvN where N is the minor number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_SLAVE_DRIVER +int spi_slave_register(FAR struct spi_slave_ctrlr_s *ctrlr, int bus); +#endif /* CONFIG_SPI_SLAVE_DRIVER */ + #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" @@ -546,4 +578,5 @@ extern "C" #if defined(__cplusplus) } #endif + #endif /* __INCLUDE_NUTTX_SPI_SLAVE_H */ diff --git a/include/nuttx/spi/spi.h b/include/nuttx/spi/spi.h index 18d4506e5b9..3c50ed76a2e 100644 --- a/include/nuttx/spi/spi.h +++ b/include/nuttx/spi/spi.h @@ -30,7 +30,6 @@ #include #include #include -#include #include /**************************************************************************** @@ -521,10 +520,10 @@ enum spi_devtype_e enum spi_mode_e { - SPIDEV_MODE0 = 0, /* CPOL=0 CHPHA=0 */ - SPIDEV_MODE1, /* CPOL=0 CHPHA=1 */ - SPIDEV_MODE2, /* CPOL=1 CHPHA=0 */ - SPIDEV_MODE3, /* CPOL=1 CHPHA=1 */ + SPIDEV_MODE0 = 0, /* CPOL=0 CPHA=0 */ + SPIDEV_MODE1, /* CPOL=0 CPHA=1 */ + SPIDEV_MODE2, /* CPOL=1 CPHA=0 */ + SPIDEV_MODE3, /* CPOL=1 CPHA=1 */ SPIDEV_MODETI, /* CPOL=0 CPHA=1 TI Synchronous Serial Frame Format */ }; diff --git a/include/nuttx/spi/spi_bitbang.c b/include/nuttx/spi/spi_bitbang.c index b81fe81fbf4..02da3f8efd7 100644 --- a/include/nuttx/spi/spi_bitbang.c +++ b/include/nuttx/spi/spi_bitbang.c @@ -24,6 +24,8 @@ #include +#include + #include /**************************************************************************** diff --git a/include/nuttx/syslog/syslog.h b/include/nuttx/syslog/syslog.h index c056a663927..ec47110c1b4 100644 --- a/include/nuttx/syslog/syslog.h +++ b/include/nuttx/syslog/syslog.h @@ -93,6 +93,7 @@ typedef CODE ssize_t (*syslog_write_t)(FAR struct syslog_channel_s *channel, typedef CODE int (*syslog_putc_t)(FAR struct syslog_channel_s *channel, int ch); typedef CODE int (*syslog_flush_t)(FAR struct syslog_channel_s *channel); +typedef CODE void (*syslog_close_t)(FAR struct syslog_channel_s *channel); /* SYSLOG device operations */ @@ -102,6 +103,7 @@ struct syslog_channel_ops_s syslog_putc_t sc_force; /* Low-level output for interrupt handlers */ syslog_flush_t sc_flush; /* Flush buffered output (on crash) */ syslog_write_t sc_write; /* Write multiple bytes */ + syslog_close_t sc_close; /* Channel close callback */ }; /* This structure provides the interface to a SYSLOG channel */ @@ -233,13 +235,12 @@ int syslog_initialize(void); * file. * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. + * A pointer to the new SYSLOG channel; NULL is returned on any failure. * ****************************************************************************/ #ifdef CONFIG_SYSLOG_FILE -int syslog_file_channel(FAR const char *devpath); +FAR struct syslog_channel_s *syslog_file_channel(FAR const char *devpath); #endif /**************************************************************************** diff --git a/include/nuttx/timers/timer.h b/include/nuttx/timers/timer.h index 138973fd397..f756f665a50 100644 --- a/include/nuttx/timers/timer.h +++ b/include/nuttx/timers/timer.h @@ -1,36 +1,20 @@ /**************************************************************************** * include/nuttx/timers/timer.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Bob Doiron + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/tls.h b/include/nuttx/tls.h index 79f0e78abed..a7d28f3d3d1 100644 --- a/include/nuttx/tls.h +++ b/include/nuttx/tls.h @@ -27,7 +27,9 @@ #include +#include #include +#include /**************************************************************************** * Pre-processor Definitions @@ -59,6 +61,20 @@ * Public Types ****************************************************************************/ +struct task_info_s +{ + sem_t ta_sem; + +#if CONFIG_TLS_NELEM > 0 + tls_ndxset_t ta_tlsset; /* Set of TLS indexes allocated */ + tls_dtor_t ta_tlsdtor[CONFIG_TLS_NELEM]; /* List of TLS destructors */ +#endif + +#ifndef CONFIG_BUILD_KERNEL + struct getopt_s ta_getopt; /* Globals used by getopt() */ +#endif +}; + /* When TLS is enabled, up_createstack() will align allocated stacks to the * TLS_STACK_ALIGN value. An instance of the following structure will be * implicitly positioned at the "lower" end of the stack. Assuming a @@ -76,10 +92,10 @@ * * Push Down Push Up * +-------------+ +-------------+ <- Stack memory allocation - * | TLS Data | | TLS Data | - * +-------------+ +-------------+ * | Task Data* | | Task Data* | * +-------------+ +-------------+ + * | TLS Data | | TLS Data | + * +-------------+ +-------------+ * | Arguments | | Arguments | * +-------------+ +-------------+ | * | | | | v @@ -90,23 +106,27 @@ * | | ^ | | * +-------------+ | +-------------+ * - * Task data is allocated in the main's thread's stack only + * Task data is a pointer that pointed to a user space memory region. */ struct tls_info_s { + FAR struct task_info_s * tl_task; + #if CONFIG_TLS_NELEM > 0 uintptr_t tl_elem[CONFIG_TLS_NELEM]; /* TLS elements */ #endif - int tl_errno; /* Per-thread error number */ -}; -struct task_info_s -{ - struct tls_info_s ta_tls; /* Must be first field */ -#ifndef CONFIG_BUILD_KERNEL - struct getopt_s ta_getopt; /* Globals used by getopt() */ +#ifdef CONFIG_PTHREAD_CLEANUP + /* tos - The index to the next available entry at the top of the stack. + * stack - The pre-allocated clean-up stack memory. + */ + + uint8_t tos; + struct pthread_cleanup_s stack[CONFIG_PTHREAD_CLEANUP_STACKSIZE]; #endif + + int tl_errno; /* Per-thread error number */ }; /**************************************************************************** @@ -120,7 +140,7 @@ struct task_info_s * Allocate a group-unique TLS data index * * Input Parameters: - * None + * dtor - The destructor of TLS data element * * Returned Value: * A TLS index that is unique for use within this task group. @@ -128,7 +148,7 @@ struct task_info_s ****************************************************************************/ #if CONFIG_TLS_NELEM > 0 -int tls_alloc(void); +int tls_alloc(CODE void (*dtor)(FAR void *)); #endif /**************************************************************************** @@ -216,6 +236,24 @@ int tls_set_value(int tlsindex, uintptr_t tlsvalue); FAR struct tls_info_s *tls_get_info(void); #endif +/**************************************************************************** + * Name: tls_destruct + * + * Description: + * Destruct all TLS data element associated with allocated key + * + * Input Parameters: + * None + * + * Returned Value: + * A set of allocated TLS index + * + ****************************************************************************/ + +#if CONFIG_TLS_NELEM > 0 +void tls_destruct(void); +#endif + /**************************************************************************** * Name: task_get_info * diff --git a/include/nuttx/usb/dfu.h b/include/nuttx/usb/dfu.h index f2647d2970d..1d333d9dc69 100644 --- a/include/nuttx/usb/dfu.h +++ b/include/nuttx/usb/dfu.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/usb/dfu.h * - * Copyright (C) 2011-2018 Gregory Nutt. All rights reserved. - * Authors: Petteri Aimonen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/usb/hub.h b/include/nuttx/usb/hub.h index 117b2c28735..11bbc3f3226 100644 --- a/include/nuttx/usb/hub.h +++ b/include/nuttx/usb/hub.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/usb/hub.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Kaushal Parikh + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/userspace.h b/include/nuttx/userspace.h index d2574997e24..2cf14e30d54 100644 --- a/include/nuttx/userspace.h +++ b/include/nuttx/userspace.h @@ -100,13 +100,9 @@ struct userspace_s FAR struct mm_heap_s **us_heap; - /* Task/thread startup routines */ + /* Task startup routine */ CODE void (*task_startup)(main_t entrypt, int argc, FAR char *argv[]); -#ifndef CONFIG_DISABLE_PTHREAD - CODE void (*pthread_startup)(pthread_startroutine_t entrypt, - pthread_addr_t arg); -#endif /* Signal handler trampoline */ @@ -136,26 +132,6 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: pthread_startup - * - * Description: - * This function is the user-space, pthread startup function. It is called - * from up_pthread_start() in user-mode. - * - * Input Parameters: - * entrypt - The user-space address of the pthread entry point - * arg - Standard argument for the pthread entry point - * - * Returned Value: - * None. This function does not return. - * - ****************************************************************************/ - -#if !defined(__KERNEL__) && !defined(CONFIG_DISABLE_PTHREAD) -void pthread_startup(pthread_startroutine_t entrypt, pthread_addr_t arg); -#endif - #undef EXTERN #ifdef __cplusplus } diff --git a/include/nuttx/wireless/bluetooth/bt_uart_shim.h b/include/nuttx/wireless/bluetooth/bt_uart_shim.h index 69cf38edddb..c1240cb5186 100644 --- a/include/nuttx/wireless/bluetooth/bt_uart_shim.h +++ b/include/nuttx/wireless/bluetooth/bt_uart_shim.h @@ -1,36 +1,20 @@ /**************************************************************************** * include/nuttx/wireless/bluetooth/bt_uart_shim.h - * Shim for connecting generic UART ports to bluetooth H4 interfaces * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/wireless/ieee80211/bcmf_board.h b/include/nuttx/wireless/ieee80211/bcmf_board.h index 4a40fbc11e2..8c041f228ae 100644 --- a/include/nuttx/wireless/ieee80211/bcmf_board.h +++ b/include/nuttx/wireless/ieee80211/bcmf_board.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/wireless/ieee80211/bcmf_board.h * - * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/wireless/ieee80211/bcmf_sdio.h b/include/nuttx/wireless/ieee80211/bcmf_sdio.h index 7b52308e8e1..6797693ef46 100644 --- a/include/nuttx/wireless/ieee80211/bcmf_sdio.h +++ b/include/nuttx/wireless/ieee80211/bcmf_sdio.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/wireless/ieee80211/bcmf_sdio.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/nuttx/wireless/ieee80211/mmc_sdio.h b/include/nuttx/wireless/ieee80211/mmc_sdio.h index 8bda78807f6..bf8dcaf7cdb 100644 --- a/include/nuttx/wireless/ieee80211/mmc_sdio.h +++ b/include/nuttx/wireless/ieee80211/mmc_sdio.h @@ -1,35 +1,20 @@ /**************************************************************************** * include/nuttx/wireless/ieee80211/mmc_sdio.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Simon Piriou + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/include/pthread.h b/include/pthread.h index 8eacc33d420..4fd3bfdfb35 100644 --- a/include/pthread.h +++ b/include/pthread.h @@ -224,6 +224,10 @@ typedef FAR void *pthread_addr_t; typedef CODE pthread_addr_t (*pthread_startroutine_t)(pthread_addr_t); typedef pthread_startroutine_t pthread_func_t; +typedef void (*pthread_exitroutine_t)(pthread_addr_t); + +typedef void (*pthread_trampoline_t)(pthread_startroutine_t, pthread_addr_t); + struct pthread_attr_s { uint8_t priority; /* Priority of the pthread */ diff --git a/include/signal.h b/include/signal.h index 6c113f99571..50540c4988a 100644 --- a/include/signal.h +++ b/include/signal.h @@ -224,7 +224,7 @@ # endif #endif -/* SIGWORK is used to wake up various internal, NuttX worker thread */ +/* SIGWORK is used to wake up various internal NuttX worker threads */ #if defined(CONFIG_SCHED_WORKQUEUE) || defined(CONFIG_PAGING) # ifndef CONFIG_SIG_SIGWORK diff --git a/include/sys/boardctl.h b/include/sys/boardctl.h index 96e486f5078..306abc83b7a 100644 --- a/include/sys/boardctl.h +++ b/include/sys/boardctl.h @@ -200,6 +200,7 @@ #define BOARDIOC_NXTERM _BOARDIOC(0x000f) #define BOARDIOC_NXTERM_IOCTL _BOARDIOC(0x0010) #define BOARDIOC_TESTSET _BOARDIOC(0x0011) +#define BOARDIOC_UNIQUEKEY _BOARDIOC(0x0012) /* If CONFIG_BOARDCTL_IOCTL=y, then board-specific commands will be support. * In this case, all commands not recognized by boardctl() will be forwarded diff --git a/include/sys/select.h b/include/sys/select.h index ba65ddab198..956b7d1cdfa 100644 --- a/include/sys/select.h +++ b/include/sys/select.h @@ -71,11 +71,11 @@ /* Standard helper macros */ #define FD_CLR(fd,set) \ - ((((fd_set*)(set))->arr)[_FD_NDX(fd)] &= ~(1ul << _FD_BIT(fd))) + ((((fd_set*)(set))->arr)[_FD_NDX(fd)] &= ~(UINT32_C(1)<< _FD_BIT(fd))) #define FD_SET(fd,set) \ - ((((fd_set*)(set))->arr)[_FD_NDX(fd)] |= (1ul << _FD_BIT(fd))) + ((((fd_set*)(set))->arr)[_FD_NDX(fd)] |= (UINT32_C(1) << _FD_BIT(fd))) #define FD_ISSET(fd,set) \ - (((((fd_set*)(set))->arr)[_FD_NDX(fd)] & (1ul << _FD_BIT(fd))) != 0) + (((((fd_set*)(set))->arr)[_FD_NDX(fd)] & (UINT32_C(1) << _FD_BIT(fd))) != 0) #define FD_ZERO(set) \ memset((set), 0, sizeof(fd_set)) diff --git a/include/sys/syscall_lookup.h b/include/sys/syscall_lookup.h index 0ff9dae22d9..03de33c0d2f 100644 --- a/include/sys/syscall_lookup.h +++ b/include/sys/syscall_lookup.h @@ -33,10 +33,6 @@ SYSCALL_LOOKUP(gettid, 0) SYSCALL_LOOKUP(getppid, 0) #endif -#ifdef CONFIG_SCHED_HAVE_PARENT - SYSCALL_LOOKUP(getppid, 0) -#endif - SYSCALL_LOOKUP(sched_getparam, 2) SYSCALL_LOOKUP(sched_getscheduler, 1) SYSCALL_LOOKUP(sched_lock, 0) @@ -263,6 +259,9 @@ SYSCALL_LOOKUP(telldir, 1) #if defined(CONFIG_PIPES) && CONFIG_DEV_PIPE_SIZE > 0 SYSCALL_LOOKUP(nx_pipe, 3) +#endif + +#if defined(CONFIG_PIPES) && CONFIG_DEV_FIFO_SIZE > 0 SYSCALL_LOOKUP(nx_mkfifo, 3) #endif @@ -295,11 +294,6 @@ SYSCALL_LOOKUP(telldir, 1) SYSCALL_LOOKUP(shmdt, 1) #endif -#if CONFIG_TLS_NELEM > 0 - SYSCALL_LOOKUP(tls_alloc, 0) - SYSCALL_LOOKUP(tls_free, 1) -#endif - /* The following are defined if pthreads are enabled */ #ifndef CONFIG_DISABLE_PTHREAD @@ -307,9 +301,9 @@ SYSCALL_LOOKUP(telldir, 1) SYSCALL_LOOKUP(pthread_cond_broadcast, 1) SYSCALL_LOOKUP(pthread_cond_signal, 1) SYSCALL_LOOKUP(pthread_cond_wait, 2) - SYSCALL_LOOKUP(pthread_create, 4) + SYSCALL_LOOKUP(nx_pthread_create, 6) SYSCALL_LOOKUP(pthread_detach, 1) - SYSCALL_LOOKUP(pthread_exit, 1) + SYSCALL_LOOKUP(nx_pthread_exit, 1) SYSCALL_LOOKUP(pthread_getschedparam, 3) SYSCALL_LOOKUP(pthread_join, 2) SYSCALL_LOOKUP(pthread_mutex_destroy, 1) @@ -329,10 +323,6 @@ SYSCALL_LOOKUP(telldir, 1) SYSCALL_LOOKUP(pthread_cond_clockwait, 4) SYSCALL_LOOKUP(pthread_kill, 2) SYSCALL_LOOKUP(pthread_sigmask, 3) -#ifdef CONFIG_PTHREAD_CLEANUP - SYSCALL_LOOKUP(pthread_cleanup_push, 2) - SYSCALL_LOOKUP(pthread_cleanup_pop, 1) -#endif #endif /* The following are defined only if message queues are enabled */ diff --git a/include/termios.h b/include/termios.h index 463010da644..f2fb09075c4 100644 --- a/include/termios.h +++ b/include/termios.h @@ -85,19 +85,19 @@ /* Control Modes (c_cflag in the termios structure) */ -#define CSIZE (3 << 4) /* Bits 4-5: Character size: */ -# define CS5 (0 << 4) /* 5 bits */ -# define CS6 (1 << 4) /* 6 bits */ -# define CS7 (2 << 4) /* 7 bits */ -# define CS8 (3 << 4) /* 8 bits */ -#define CSTOPB (1 << 6) /* Bit 6: Send two stop bits, else one */ -#define CREAD (1 << 7) /* Bit 7: Enable receiver */ -#define PARENB (1 << 8) /* Bit 8: Parity enable */ -#define PARODD (1 << 9) /* Bit 9: Odd parity, else even */ -#define HUPCL (1 << 10) /* Bit 10: Hang up on last close */ -#define CLOCAL (1 << 11) /* Bit 11: Ignore modem status lines */ -#define CCTS_OFLOW (1 << 29)/* Bit 29: CTS flow control of output */ -#define CRTS_IFLOW (1u << 31)/* Bit 31: RTS flow control of input */ +#define CSIZE (3 << 4) /* Bits 4-5: Character size: */ +# define CS5 (0 << 4) /* 5 bits */ +# define CS6 (1 << 4) /* 6 bits */ +# define CS7 (2 << 4) /* 7 bits */ +# define CS8 (3 << 4) /* 8 bits */ +#define CSTOPB (1 << 6) /* Bit 6: Send two stop bits, else one */ +#define CREAD (1 << 7) /* Bit 7: Enable receiver */ +#define PARENB (1 << 8) /* Bit 8: Parity enable */ +#define PARODD (1 << 9) /* Bit 9: Odd parity, else even */ +#define HUPCL (1 << 10) /* Bit 10: Hang up on last close */ +#define CLOCAL (1 << 11) /* Bit 11: Ignore modem status lines */ +#define CCTS_OFLOW (1 << 29) /* Bit 29: CTS flow control of output */ +#define CRTS_IFLOW (1u << 31) /* Bit 31: RTS flow control of input */ #define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) /* Local Modes (c_lflag in the termios structure) */ diff --git a/include/time.h b/include/time.h index 6fd612b1843..97b5a73a1de 100644 --- a/include/time.h +++ b/include/time.h @@ -91,7 +91,6 @@ #define TIME_UTC 1 - /* Redirect the timelocal */ #define timelocal mktime diff --git a/libs/libc/audio/libsrc/Make.defs b/libs/libc/audio/libsrc/Make.defs index 63dda0e84c4..78d956bc762 100644 --- a/libs/libc/audio/libsrc/Make.defs +++ b/libs/libc/audio/libsrc/Make.defs @@ -27,7 +27,7 @@ libsamplerate: $(Q) curl -L https://codeload.github.com/libsndfile/libsamplerate/zip/master -o libsamplerate.zip $(Q) unzip -o libsamplerate.zip $(Q) mv libsamplerate-master libsamplerate - $(Q) cp -rf libsamplerate/src/samplerate.h $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio$(DELIM) + $(Q) cp -rf libsamplerate/include/samplerate.h $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio$(DELIM) context:: libsamplerate @@ -38,6 +38,8 @@ CSRCS += src_zoh.c CFLAGS += -DPACKAGE=\"$(PACKAGE)\" -DVERSION=\"$(VERSION)\" +CFLAGS += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio} + ifeq ($(CONFIG_SINC_FAST_CONVERTER),y) CFLAGS += -DENABLE_SINC_FAST_CONVERTER endif diff --git a/libs/libc/debug/Kconfig b/libs/libc/debug/Kconfig index 36366ed4cd6..f926d22e911 100644 --- a/libs/libc/debug/Kconfig +++ b/libs/libc/debug/Kconfig @@ -3,7 +3,7 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -# These are library functions that may be overriden by architecture- +# These are library functions that may be overridden by architecture- # specific implementations. Not all architectures support implementations # for every library function. diff --git a/libs/libc/dlfcn/lib_dlclose.c b/libs/libc/dlfcn/lib_dlclose.c index 414c32b59a7..167d92f9152 100644 --- a/libs/libc/dlfcn/lib_dlclose.c +++ b/libs/libc/dlfcn/lib_dlclose.c @@ -25,6 +25,8 @@ #include #include +#include +#include #include #include diff --git a/libs/libc/dlfcn/lib_dlopen.c b/libs/libc/dlfcn/lib_dlopen.c index cdeaf296dbc..ed51ac04185 100644 --- a/libs/libc/dlfcn/lib_dlopen.c +++ b/libs/libc/dlfcn/lib_dlopen.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/libs/libc/dlfcn/lib_dlsym.c b/libs/libc/dlfcn/lib_dlsym.c index cd6a6fedee1..75e21b23643 100644 --- a/libs/libc/dlfcn/lib_dlsym.c +++ b/libs/libc/dlfcn/lib_dlsym.c @@ -25,6 +25,8 @@ #include #include +#include +#include #include #include diff --git a/libs/libc/hex2bin/lib_hex2bin.c b/libs/libc/hex2bin/lib_hex2bin.c index e8ff4d2b60f..e3cc3bd921e 100644 --- a/libs/libc/hex2bin/lib_hex2bin.c +++ b/libs/libc/hex2bin/lib_hex2bin.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include diff --git a/libs/libc/libc.csv b/libs/libc/libc.csv index 6166f75fd12..cbd6c5cdef6 100644 --- a/libs/libc/libc.csv +++ b/libs/libc/libc.csv @@ -233,12 +233,12 @@ "wcslen","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR const wchar_t *" "wcsnrtombs","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR char *","FAR const wchar_t **","size_t","size_t","FAR mbstate_t *" "wcsrtombs","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR char *","FAR const wchar_t **","size_t","FAR mbstate_t *" -"wcstombs","stdlib.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR char *","FAR const wchar_t *","size_t" "wcstod","wchar.h","defined(CONFIG_LIBC_WCHAR)","double","FAR const wchar_t *","FAR wchar_t **" "wcstof","wchar.h","defined(CONFIG_LIBC_WCHAR)","float","FAR const wchar_t *","FAR wchar_t **" "wcstol","wchar.h","defined(CONFIG_LIBC_WCHAR)","long int","FAR const wchar_t *","FAR wchar_t **","int" "wcstold","wchar.h","defined(CONFIG_LIBC_WCHAR)","long double","FAR const wchar_t *","FAR wchar_t **" "wcstoll","wchar.h","defined(CONFIG_LIBC_WCHAR)","long long int","FAR const wchar_t *","FAR wchar_t **","int" +"wcstombs","stdlib.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR char *","FAR const wchar_t *","size_t" "wcstoul","wchar.h","defined(CONFIG_LIBC_WCHAR)","unsigned long int","FAR const wchar_t *","FAR wchar_t **","int" "wcsxfrm","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR wchar_t *","FAR const wchar_t *","size_t" "wctob","wchar.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" diff --git a/libs/libc/machine/Kconfig b/libs/libc/machine/Kconfig index f0f439f099d..f44af4a7f40 100644 --- a/libs/libc/machine/Kconfig +++ b/libs/libc/machine/Kconfig @@ -3,7 +3,7 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -# These are library functions that may be overriden by architecture- +# These are library functions that may be overridden by architecture- # specific implementations. Not all architectures support implementations # for every library function. @@ -174,5 +174,8 @@ endif if ARCH_XTENSA source libs/libc/machine/xtensa/Kconfig endif +if ARCH_RENESAS +source libs/libc/machine/renesas/Kconfig +endif endmenu # Architecture-Specific Support diff --git a/libs/libc/machine/Make.defs b/libs/libc/machine/Make.defs index 4817ca8f730..818dffbba3c 100644 --- a/libs/libc/machine/Make.defs +++ b/libs/libc/machine/Make.defs @@ -33,3 +33,6 @@ endif ifeq ($(CONFIG_ARCH_XTENSA),y) include $(TOPDIR)/libs/libc/machine/xtensa/Make.defs endif +ifeq ($(CONFIG_ARCH_RENESAS),y) +include $(TOPDIR)/libs/libc/machine/renesas/Make.defs +endif diff --git a/libs/libc/machine/renesas/Kconfig b/libs/libc/machine/renesas/Kconfig new file mode 100644 index 00000000000..a63872358e3 --- /dev/null +++ b/libs/libc/machine/renesas/Kconfig @@ -0,0 +1,9 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +#if ARCH_RENESAS_RX +#source libs/libc/machine/renesas/rx/Kconfig +#endif + diff --git a/libs/libc/machine/renesas/Make.defs b/libs/libc/machine/renesas/Make.defs new file mode 100644 index 00000000000..a99c83e7cc4 --- /dev/null +++ b/libs/libc/machine/renesas/Make.defs @@ -0,0 +1,23 @@ +############################################################################ +# libs/libc/machine/renesas/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_ARCH_RENESAS_RX),y) +include $(TOPDIR)/libs/libc/machine/renesas/rx/Make.defs +endif diff --git a/libs/libc/machine/renesas/rx/Kconfig b/libs/libc/machine/renesas/rx/Kconfig new file mode 100644 index 00000000000..cb611de9906 --- /dev/null +++ b/libs/libc/machine/renesas/rx/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_RENESAS_RX +endif diff --git a/libs/libc/machine/renesas/rx/Make.defs b/libs/libc/machine/renesas/rx/Make.defs new file mode 100644 index 00000000000..4e8aa5a1bf7 --- /dev/null +++ b/libs/libc/machine/renesas/rx/Make.defs @@ -0,0 +1,26 @@ +############################################################################ +# libs/libc/machine/renesas/rx/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_ARCH_SETJMP_H),y) +ASRCS += arch_setjmp.S +endif + +DEPPATH += --dep-path machine/renesas/rx/gnu +VPATH += :machine/renesas/rx/gnu diff --git a/libs/libc/machine/renesas/rx/gnu/arch_setjmp.S b/libs/libc/machine/renesas/rx/gnu/arch_setjmp.S new file mode 100644 index 00000000000..bff7aa1a74f --- /dev/null +++ b/libs/libc/machine/renesas/rx/gnu/arch_setjmp.S @@ -0,0 +1,146 @@ +/**************************************************************************** + * libs/libc/machine/renesas/rx/gnu/arm_setjmp.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .text + .global _setjmp + .global _longjmp + + .file "setjmp.S" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: setjmp + * + * Description: + * Given the pointer to a register save area (in R1), save the state of the + * all callee-saved registers + * + * C Function Prototype: + * int setjmp(jmp_buf env); + * + * Input Parameters: + * env - A pointer to the register save area in which to save the floating point + * registers and core registers. Since setjmp() can not be inlined, we + * only need to save the ABI-specified callee-saved registers. + * + * Returned Value: + * 0 setjmp called directly + * non-0 we justed returned from a longjmp() + * + ****************************************************************************/ + + .type _setjmp, function +_setjmp: + /* save Stack Pointer */ + mov.l r0, [r1] + + /* Store callee-saved registers R6-R13 */ + mov.l r6, 0x4[r1] + mov.l r7, 0x8[r1] + mov.l r8, 0xc[r1] + mov.l r9, 0x10[r1] + mov.l r10, 0x14[r1] + mov.l r11, 0x18[r1] + mov.l r12, 0x1c[r1] + mov.l r13, 0x20[r1] + + /* get return address from stack */ + mov.l [r0], r2 + + /* save return address */ + mov.l r2, 0x24[r1] + + /* return 0 */ + mov #0, r1 + rts + + .size _setjmp, .-_setjmp + +/**************************************************************************** + * Name: longjmp + * + * Description: + * The longjmp() function used the information saved in env to transfer control + * control back to the point where setjmp() was called and to restore ("rewind") + * the stack to its state at the time of the setjmp() call. When control is + * passed back to where setjmp() had been called, setjmp() will return with + * 'val', the second parameter passed to longjmp(). + * + * C Function Prototype: + * void longjmp(jmp_buf env, int val); + * + * Input Parameters: + * jmp_buf env + * int val + * + * Returned Value: + * This function does not return anything explicitly. + * + ****************************************************************************/ + + .type _longjmp, function +_longjmp: + /* check if r2 is zero */ + tst r2, r2 + /* set r2 to 1 if it was zero */ + stz #1, r2 + + /* restore stack pointer */ + mov.l [r1], r0 + + /* get the saved return address */ + mov.l 0x24[r1], r3 + /* set our return address */ + mov.l r3, [r0] + + /* restore callee-saved registers R6-R13 */ + mov.l 0x20[r1], r13 + mov.l 0x1c[r1], r12 + mov.l 0x18[r1], r11 + mov.l 0x14[r1], r10 + mov.l 0x10[r1], r9 + mov.l 0xc[r1], r8 + mov.l 0x8[r1], r7 + mov.l 0x4[r1], r6 + + /* return val */ + mov.l r2, r1 + /* return */ + rts + + .size _longjmp, .-_longjmp + .end diff --git a/libs/libc/math/Make.defs b/libs/libc/math/Make.defs index d4e30c8a687..5ea034d9595 100644 --- a/libs/libc/math/Make.defs +++ b/libs/libc/math/Make.defs @@ -52,6 +52,8 @@ CSRCS += lib_expm1.c lib_expm1f.c lib_expm1l.c CSRCS += lib_lround.c lib_lroundf.c lib_lroundl.c CSRCS += lib_llround.c lib_llroundf.c lib_llroundl.c CSRCS += lib_nan.c lib_nanf.c lib_nanl.c +CSRCS += lib_fmax.c lib_fmaxf.c lib_fmaxl.c +CSRCS += lib_fmin.c lib_fminf.c lib_fminl.c CSRCS += __cos.c __sin.c lib_gamma.c lib_lgamma.c diff --git a/libs/libc/math/lib_copysign.c b/libs/libc/math/lib_copysign.c index 639a3bd57f3..c13386c65fc 100644 --- a/libs/libc/math/lib_copysign.c +++ b/libs/libc/math/lib_copysign.c @@ -1,36 +1,20 @@ /**************************************************************************** * libs/libc/math/lib_copysign.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/math/lib_copysignl.c b/libs/libc/math/lib_copysignl.c index b28b4396493..0bdf48bf0a9 100644 --- a/libs/libc/math/lib_copysignl.c +++ b/libs/libc/math/lib_copysignl.c @@ -1,36 +1,20 @@ /**************************************************************************** * libs/libc/math/lib_copysignl.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/math/lib_erf.c b/libs/libc/math/lib_erf.c index 10b3c6f39b2..aba342d67b4 100644 --- a/libs/libc/math/lib_erf.c +++ b/libs/libc/math/lib_erf.c @@ -1,36 +1,20 @@ /**************************************************************************** * libs/libc/math/lib_erf.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Copyright (C) 2015 Brennan Ashton. All rights reserved. - * Author: Brennan Ashton + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/math/lib_erff.c b/libs/libc/math/lib_erff.c index 3dad93deeea..3a65072fca9 100644 --- a/libs/libc/math/lib_erff.c +++ b/libs/libc/math/lib_erff.c @@ -1,36 +1,20 @@ /**************************************************************************** * libs/libc/math/lib_erff.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Copyright (C) 2015 Brennan Ashton. All rights reserved. - * Author: Brennan Ashton + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/math/lib_fmax.c b/libs/libc/math/lib_fmax.c new file mode 100644 index 00000000000..1cb62c06a6e --- /dev/null +++ b/libs/libc/math/lib_fmax.c @@ -0,0 +1,39 @@ +/**************************************************************************** + * libs/libc/math/lib_fmax.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_HAVE_DOUBLE +double fmax(double x, double y) +{ + return ((x > y) ? x : y); +} +#endif diff --git a/libs/libc/math/lib_fmaxf.c b/libs/libc/math/lib_fmaxf.c new file mode 100644 index 00000000000..1e545aa26bf --- /dev/null +++ b/libs/libc/math/lib_fmaxf.c @@ -0,0 +1,37 @@ +/**************************************************************************** + * libs/libc/math/lib_fmaxf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +float fmaxf(float x, float y) +{ + return ((x > y) ? x : y); +} diff --git a/libs/libc/math/lib_fmaxl.c b/libs/libc/math/lib_fmaxl.c new file mode 100644 index 00000000000..ae7a27886e0 --- /dev/null +++ b/libs/libc/math/lib_fmaxl.c @@ -0,0 +1,39 @@ +/**************************************************************************** + * libs/libc/math/lib_fmaxl.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_HAVE_LONG_DOUBLE +long double fmaxl(long double x, long double y) +{ + return ((x > y) ? x : y); +} +#endif diff --git a/libs/libc/math/lib_fmin.c b/libs/libc/math/lib_fmin.c new file mode 100644 index 00000000000..c494575dbd6 --- /dev/null +++ b/libs/libc/math/lib_fmin.c @@ -0,0 +1,39 @@ +/**************************************************************************** + * libs/libc/math/lib_fmin.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_HAVE_DOUBLE +double fmin(double x, double y) +{ + return ((x < y) ? x : y); +} +#endif diff --git a/libs/libc/math/lib_fminf.c b/libs/libc/math/lib_fminf.c new file mode 100644 index 00000000000..1ba6edf78e5 --- /dev/null +++ b/libs/libc/math/lib_fminf.c @@ -0,0 +1,37 @@ +/**************************************************************************** + * libs/libc/math/lib_fminf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +float fminf(float x, float y) +{ + return ((x < y) ? x : y); +} diff --git a/libs/libc/math/lib_fminl.c b/libs/libc/math/lib_fminl.c new file mode 100644 index 00000000000..22e74cef847 --- /dev/null +++ b/libs/libc/math/lib_fminl.c @@ -0,0 +1,39 @@ +/**************************************************************************** + * libs/libc/math/lib_fminl.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_HAVE_LONG_DOUBLE +long double fminl(long double x, long double y) +{ + return ((x < y) ? x : y); +} +#endif diff --git a/libs/libc/math/lib_log.c b/libs/libc/math/lib_log.c index ba7aae3e7ce..638ed62b0a0 100644 --- a/libs/libc/math/lib_log.c +++ b/libs/libc/math/lib_log.c @@ -60,7 +60,7 @@ double log(double x) { double y; double y_old; - double ney; + double ey; double epsilon; int relax_factor; int iter; @@ -75,8 +75,8 @@ double log(double x) while (y > y_old + epsilon || y < y_old - epsilon) { y_old = y; - ney = exp(-y); - y -= 1.0 - x * ney; + ey = exp(y); + y -= (ey - x) / ey; if (y > 700.0) { diff --git a/libs/libc/math/lib_logf.c b/libs/libc/math/lib_logf.c index e813568bf39..b53805da843 100644 --- a/libs/libc/math/lib_logf.c +++ b/libs/libc/math/lib_logf.c @@ -58,7 +58,7 @@ float logf(float x) { float y; float y_old; - float ney; + float ey; float epsilon; int relax_factor; int iter; @@ -73,8 +73,8 @@ float logf(float x) while (y > y_old + epsilon || y < y_old - epsilon) { y_old = y; - ney = expf(-y); - y -= 1.0F - x * ney; + ey = expf(y); + y -= (ey - x) / ey; if (y > FLT_MAX_EXP_X) { diff --git a/libs/libc/math/lib_modfl.c b/libs/libc/math/lib_modfl.c index 6e2260ef1bf..b28f2aa124e 100644 --- a/libs/libc/math/lib_modfl.c +++ b/libs/libc/math/lib_modfl.c @@ -42,12 +42,12 @@ #ifdef CONFIG_HAVE_LONG_DOUBLE long double modfl(long double x, long double *iptr) { - if (fabs(x) >= 4503599627370496.0) + if (fabsl(x) >= 4503599627370496.0) { *iptr = x; return 0.0; } - else if (fabs(x) < 1.0) + else if (fabsl(x) < 1.0) { *iptr = (x * 0.0); return x; diff --git a/libs/libc/math/lib_round.c b/libs/libc/math/lib_round.c index dc432db6df0..bc9d1bee3f4 100644 --- a/libs/libc/math/lib_round.c +++ b/libs/libc/math/lib_round.c @@ -1,10 +1,20 @@ /**************************************************************************** * libs/libc/math/lib_round.c * - * This file is a part of NuttX: + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * (C) 2012 Petteri Aimonen + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/math/lib_roundf.c b/libs/libc/math/lib_roundf.c index a89c61ff1a8..defcf604f23 100644 --- a/libs/libc/math/lib_roundf.c +++ b/libs/libc/math/lib_roundf.c @@ -1,10 +1,20 @@ /**************************************************************************** * libs/libc/math/lib_roundf.c * - * This file is a part of NuttX: + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * (C) 2012 Petteri Aimonen + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/math/lib_roundl.c b/libs/libc/math/lib_roundl.c index 5a2d228bede..6b36ff6e7e6 100644 --- a/libs/libc/math/lib_roundl.c +++ b/libs/libc/math/lib_roundl.c @@ -1,10 +1,20 @@ /**************************************************************************** * libs/libc/math/lib_roundl.c * - * This file is a part of NuttX: + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * (C) 2012 Petteri Aimonen + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/misc/lib_stream.c b/libs/libc/misc/lib_stream.c index 125a2f53b14..1ba5d237f3c 100644 --- a/libs/libc/misc/lib_stream.c +++ b/libs/libc/misc/lib_stream.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/libs/libc/modlib/Kconfig b/libs/libc/modlib/Kconfig index 4f9e78d4064..a1529fac875 100644 --- a/libs/libc/modlib/Kconfig +++ b/libs/libc/modlib/Kconfig @@ -7,7 +7,7 @@ config LIBC_MODLIB bool default n select LIBC_ARCH_ELF - select ARCH_USE_MODULE_TEXT if ARCH_HAVE_MODULE_TEXT + select ARCH_USE_TEXT_HEAP if ARCH_HAVE_TEXT_HEAP menu "Module library configuration" depends on LIBC_MODLIB diff --git a/libs/libc/modlib/modlib_depend.c b/libs/libc/modlib/modlib_depend.c index 7ceaada9ec4..4fb5e18b4f2 100644 --- a/libs/libc/modlib/modlib_depend.c +++ b/libs/libc/modlib/modlib_depend.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/libs/libc/modlib/modlib_load.c b/libs/libc/modlib/modlib_load.c index efe936d4c0d..049a655f28f 100644 --- a/libs/libc/modlib/modlib_load.c +++ b/libs/libc/modlib/modlib_load.c @@ -265,10 +265,10 @@ int modlib_load(FAR struct mod_loadinfo_s *loadinfo) if (loadinfo->textsize > 0) { -#if defined(CONFIG_ARCH_USE_MODULE_TEXT) +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) loadinfo->textalloc = (uintptr_t) - up_module_text_memalign(loadinfo->textalign, - loadinfo->textsize); + up_textheap_memalign(loadinfo->textalign, + loadinfo->textsize); #else loadinfo->textalloc = (uintptr_t)lib_memalign(loadinfo->textalign, loadinfo->textsize); diff --git a/libs/libc/modlib/modlib_registry.c b/libs/libc/modlib/modlib_registry.c index 24d923c49b3..850242f03e2 100644 --- a/libs/libc/modlib/modlib_registry.c +++ b/libs/libc/modlib/modlib_registry.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/libs/libc/modlib/modlib_unload.c b/libs/libc/modlib/modlib_unload.c index 0e4a61a5724..3ac6026dd0d 100644 --- a/libs/libc/modlib/modlib_unload.c +++ b/libs/libc/modlib/modlib_unload.c @@ -60,8 +60,8 @@ int modlib_unload(struct mod_loadinfo_s *loadinfo) if (loadinfo->textalloc != 0) { -#if defined(CONFIG_ARCH_USE_MODULE_TEXT) - up_module_text_free((FAR void *)loadinfo->textalloc); +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) + up_textheap_free((FAR void *)loadinfo->textalloc); #else lib_free((FAR void *)loadinfo->textalloc); #endif diff --git a/libs/libc/net/lib_inetaton.c b/libs/libc/net/lib_inetaton.c index d27dfb615b7..4778918c131 100644 --- a/libs/libc/net/lib_inetaton.c +++ b/libs/libc/net/lib_inetaton.c @@ -1,35 +1,20 @@ /**************************************************************************** * libs/libc/net/lib_inetaton.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/net/lib_inetntop.c b/libs/libc/net/lib_inetntop.c index 17780512628..a97e8284c54 100644 --- a/libs/libc/net/lib_inetntop.c +++ b/libs/libc/net/lib_inetntop.c @@ -49,6 +49,7 @@ #include #include +#include #include #include diff --git a/libs/libc/net/lib_inetpton.c b/libs/libc/net/lib_inetpton.c index f2733d69d56..f1636fcf612 100644 --- a/libs/libc/net/lib_inetpton.c +++ b/libs/libc/net/lib_inetpton.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include diff --git a/libs/libc/netdb/Kconfig b/libs/libc/netdb/Kconfig index 254284d9d4c..b20cf8d1730 100644 --- a/libs/libc/netdb/Kconfig +++ b/libs/libc/netdb/Kconfig @@ -55,6 +55,7 @@ menuconfig NETDB_DNSCLIENT default n depends on NET && NET_UDP select LIBC_NETDB + select NET_SOCKOPTS ---help--- Enable support for the name resolution; Enable network host resolution via gethostbyname(). diff --git a/libs/libc/netdb/lib_dns.h b/libs/libc/netdb/lib_dns.h index 95e2dcc81a6..3ee8aee2ba7 100644 --- a/libs/libc/netdb/lib_dns.h +++ b/libs/libc/netdb/lib_dns.h @@ -224,6 +224,21 @@ void dns_save_answer(FAR const char *hostname, FAR const union dns_addr_u *addr, int naddr); #endif +/**************************************************************************** + * Name: dns_clear_answer + * + * Description: + * Clear the resolved hostname in the DNS cache + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if CONFIG_NETDB_DNSCLIENT_ENTRIES > 0 +void dns_clear_answer(void); +#endif + /**************************************************************************** * Name: dns_find_answer * diff --git a/libs/libc/netdb/lib_dnsaddserver.c b/libs/libc/netdb/lib_dnsaddserver.c index bcbc7ab8889..20dc3891a04 100644 --- a/libs/libc/netdb/lib_dnsaddserver.c +++ b/libs/libc/netdb/lib_dnsaddserver.c @@ -270,6 +270,9 @@ int dns_add_nameserver(FAR const struct sockaddr *addr, socklen_t addrlen) g_dns_nservers = nservers; dns_semgive(); +#if CONFIG_NETDB_DNSCLIENT_ENTRIES > 0 + dns_clear_answer(); +#endif dns_notify_nameserver(addr, addrlen); return OK; } diff --git a/libs/libc/netdb/lib_dnscache.c b/libs/libc/netdb/lib_dnscache.c index d4ba3968492..5f2ccafb57c 100644 --- a/libs/libc/netdb/lib_dnscache.c +++ b/libs/libc/netdb/lib_dnscache.c @@ -164,6 +164,31 @@ void dns_save_answer(FAR const char *hostname, dns_semgive(); } +/**************************************************************************** + * Name: dns_clear_answer + * + * Description: + * Clear the resolved hostname in the DNS cache + * + * Returned Value: + * None + * + ****************************************************************************/ + +void dns_clear_answer(void) +{ + /* Get exclusive access to the DNS cache */ + + dns_semtake(); + + /* Reset the circular of DNS cache */ + + g_dns_head = 0; + g_dns_tail = 0; + + dns_semgive(); +} + /**************************************************************************** * Name: dns_find_answer * diff --git a/libs/libc/netdb/lib_dnsquery.c b/libs/libc/netdb/lib_dnsquery.c index b24d4a1f287..45c984396c4 100644 --- a/libs/libc/netdb/lib_dnsquery.c +++ b/libs/libc/netdb/lib_dnsquery.c @@ -336,6 +336,7 @@ static int dns_recv_response(int sd, FAR union dns_addr_u *addr, int naddr, FAR struct dns_question_s *que; uint16_t nquestions; uint16_t nanswers; + uint16_t temp; int naddr_read; int ret; @@ -436,11 +437,12 @@ static int dns_recv_response(int sd, FAR union dns_addr_u *addr, int naddr, /* Validate query type and class */ que = (FAR struct dns_question_s *)nameptr; - ninfo("Question: type=%04x, class=%04x\n", - ntohs(que->type), ntohs(que->class)); - if (que->type != qinfo->rectype || - que->class != HTONS(DNS_CLASS_IN)) + /* N.B. Unaligned access may occur here */ + + temp = HTONS(DNS_CLASS_IN); + if (memcmp(&que->type, &qinfo->rectype, sizeof(uint16_t)) != 0 || + memcmp(&que->class, &temp, sizeof(uint16_t)) != 0) { nerr("ERROR: DNS response with wrong question\n"); return -EBADMSG; @@ -516,10 +518,14 @@ static int dns_recv_response(int sd, FAR union dns_addr_u *addr, int naddr, nameptr += 10 + 16; ninfo("IPv6 address: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - ntohs(ans->u.ipv6.s6_addr[7]), ntohs(ans->u.ipv6.s6_addr[6]), - ntohs(ans->u.ipv6.s6_addr[5]), ntohs(ans->u.ipv6.s6_addr[4]), - ntohs(ans->u.ipv6.s6_addr[3]), ntohs(ans->u.ipv6.s6_addr[2]), - ntohs(ans->u.ipv6.s6_addr[1]), ntohs(*ans->u.ipv6.s6_addr)); + ntohs(ans->u.ipv6.s6_addr16[0]), + ntohs(ans->u.ipv6.s6_addr16[1]), + ntohs(ans->u.ipv6.s6_addr16[2]), + ntohs(ans->u.ipv6.s6_addr16[3]), + ntohs(ans->u.ipv6.s6_addr16[4]), + ntohs(ans->u.ipv6.s6_addr16[5]), + ntohs(ans->u.ipv6.s6_addr16[6]), + ntohs(ans->u.ipv6.s6_addr16[7])); inaddr = &addr[naddr_read].ipv6; inaddr->sin6_family = AF_INET6; diff --git a/libs/libc/netdb/lib_freeaddrinfo.c b/libs/libc/netdb/lib_freeaddrinfo.c index 6b8a02dd38a..93b982d334b 100644 --- a/libs/libc/netdb/lib_freeaddrinfo.c +++ b/libs/libc/netdb/lib_freeaddrinfo.c @@ -1,35 +1,20 @@ /**************************************************************************** * libs/libc/netdb/lib_freeaddrinfo.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -39,6 +24,7 @@ #include +#include #include #include "libc.h" diff --git a/libs/libc/netdb/lib_gaistrerror.c b/libs/libc/netdb/lib_gaistrerror.c index 43ff791dfca..4f449c49c24 100644 --- a/libs/libc/netdb/lib_gaistrerror.c +++ b/libs/libc/netdb/lib_gaistrerror.c @@ -1,35 +1,20 @@ /**************************************************************************** * libs/libc/netdb/lib_gaistrerror.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/netdb/lib_getaddrinfo.c b/libs/libc/netdb/lib_getaddrinfo.c index d38cf356496..786c9b15684 100644 --- a/libs/libc/netdb/lib_getaddrinfo.c +++ b/libs/libc/netdb/lib_getaddrinfo.c @@ -1,35 +1,20 @@ /**************************************************************************** * libs/libc/netdb/lib_getaddrinfo.c * - * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/netdb/lib_gethostbyaddrr.c b/libs/libc/netdb/lib_gethostbyaddrr.c index fb503712d5a..702a9fd69aa 100644 --- a/libs/libc/netdb/lib_gethostbyaddrr.c +++ b/libs/libc/netdb/lib_gethostbyaddrr.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include #include diff --git a/libs/libc/netdb/lib_gethostentbynamer.c b/libs/libc/netdb/lib_gethostentbynamer.c index ea1dd5f0646..5b96c9d6819 100644 --- a/libs/libc/netdb/lib_gethostentbynamer.c +++ b/libs/libc/netdb/lib_gethostentbynamer.c @@ -32,6 +32,7 @@ #include #include #include +#include #include diff --git a/libs/libc/netdb/lib_getservbyname.c b/libs/libc/netdb/lib_getservbyname.c index 7187b700b8e..ac7b38f731d 100644 --- a/libs/libc/netdb/lib_getservbyname.c +++ b/libs/libc/netdb/lib_getservbyname.c @@ -1,35 +1,20 @@ /**************************************************************************** * libs/libc/netdb/lib_getservbyname.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/netdb/lib_getservbynamer.c b/libs/libc/netdb/lib_getservbynamer.c index e97f2786de6..927b0af81d1 100644 --- a/libs/libc/netdb/lib_getservbynamer.c +++ b/libs/libc/netdb/lib_getservbynamer.c @@ -1,35 +1,20 @@ /**************************************************************************** * libs/libc/netdb/lib_getservbynamer.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/netdb/lib_getservbyport.c b/libs/libc/netdb/lib_getservbyport.c index 02930fad8c5..eff2895c602 100644 --- a/libs/libc/netdb/lib_getservbyport.c +++ b/libs/libc/netdb/lib_getservbyport.c @@ -1,39 +1,20 @@ /**************************************************************************** * libs/libc/netdb/lib_getservbyport.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Michael Jung + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on libs/libc/netdb/lib_getservbyname.c - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/netdb/lib_getservbyportr.c b/libs/libc/netdb/lib_getservbyportr.c index af506ce40e2..b112f31033a 100644 --- a/libs/libc/netdb/lib_getservbyportr.c +++ b/libs/libc/netdb/lib_getservbyportr.c @@ -1,39 +1,20 @@ /**************************************************************************** * libs/libc/netdb/lib_getservbyportr.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Michael Jung + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Based on libs/libc/netdb/lib_getservbynamer.c - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Juha Niskanen + * http://www.apache.org/licenses/LICENSE-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/pthread/Make.defs b/libs/libc/pthread/Make.defs index 3f62e4e38dd..b4ba9959ea0 100644 --- a/libs/libc/pthread/Make.defs +++ b/libs/libc/pthread/Make.defs @@ -38,19 +38,20 @@ CSRCS += pthread_barrierattr_init.c pthread_barrierattr_destroy.c CSRCS += pthread_barrierattr_getpshared.c pthread_barrierattr_setpshared.c CSRCS += pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c CSRCS += pthread_condattr_init.c pthread_condattr_destroy.c +CSRCS += pthread_condattr_setclock.c pthread_condattr_getclock.c CSRCS += pthread_condinit.c pthread_conddestroy.c pthread_condtimedwait.c +CSRCS += pthread_create.c pthread_exit.c +CSRCS += pthread_get_stackaddr_np.c pthread_get_stacksize_np.c CSRCS += pthread_mutexattr_init.c pthread_mutexattr_destroy.c CSRCS += pthread_mutexattr_getpshared.c pthread_mutexattr_setpshared.c CSRCS += pthread_mutexattr_setprotocol.c pthread_mutexattr_getprotocol.c CSRCS += pthread_mutexattr_settype.c pthread_mutexattr_gettype.c CSRCS += pthread_mutexattr_setrobust.c pthread_mutexattr_getrobust.c CSRCS += pthread_mutex_lock.c +CSRCS += pthread_once.c pthread_yield.c +CSRCS += pthread_rwlock.c pthread_rwlock_rdlock.c pthread_rwlock_wrlock.c CSRCS += pthread_setcancelstate.c pthread_setcanceltype.c CSRCS += pthread_testcancel.c -CSRCS += pthread_rwlock.c pthread_rwlock_rdlock.c pthread_rwlock_wrlock.c -CSRCS += pthread_once.c pthread_yield.c -CSRCS += pthread_get_stackaddr_np.c pthread_get_stacksize_np.c -CSRCS += pthread_condattr_setclock.c pthread_condattr_getclock.c ifeq ($(CONFIG_SMP),y) CSRCS += pthread_attr_getaffinity.c pthread_attr_setaffinity.c @@ -60,8 +61,8 @@ ifeq ($(CONFIG_PTHREAD_SPINLOCKS),y) CSRCS += pthread_spinlock.c endif -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CSRCS += pthread_startup.c +ifeq ($(CONFIG_PTHREAD_CLEANUP),y) +CSRCS += pthread_cleanup.c endif endif # CONFIG_DISABLE_PTHREAD @@ -70,4 +71,3 @@ endif # CONFIG_DISABLE_PTHREAD DEPPATH += --dep-path pthread VPATH += :pthread - diff --git a/sched/pthread/pthread_cleanup.c b/libs/libc/pthread/pthread_cleanup.c similarity index 77% rename from sched/pthread/pthread_cleanup.c rename to libs/libc/pthread/pthread_cleanup.c index e735b15bfed..540a986e4c3 100644 --- a/sched/pthread/pthread_cleanup.c +++ b/libs/libc/pthread/pthread_cleanup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * sched/pthread/pthread_cleanup.c + * libs/libc/pthread/pthread_cleanup.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -26,11 +26,13 @@ #include #include +#include +#include #include - -#include "sched/sched.h" -#include "pthread/pthread.h" +#include +#include +#include #ifdef CONFIG_PTHREAD_CLEANUP @@ -39,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: pthread_cleanup_pop_tcb + * Name: pthread_cleanup_pop_tls * * Description: * The pthread_cleanup_pop_tcb() function will remove the routine at the @@ -57,15 +59,15 @@ * ****************************************************************************/ -static void pthread_cleanup_pop_tcb(FAR struct tcb_s *tcb, int execute) +static void pthread_cleanup_pop_tls(FAR struct tls_info_s *tls, int execute) { - if (tcb->tos > 0) + if (tls->tos > 0) { unsigned int ndx; /* Get the index to the last cleaner function pushed onto the stack */ - ndx = tcb->tos - 1; + ndx = tls->tos - 1; DEBUGASSERT(ndx >= 0 && ndx < CONFIG_PTHREAD_CLEANUP_STACKSIZE); /* Should we execute the cleanup routine at the top of the stack? */ @@ -81,11 +83,11 @@ static void pthread_cleanup_pop_tcb(FAR struct tcb_s *tcb, int execute) * mode! See also on_exit() and atexit() callbacks. */ - cb = &tcb->stack[ndx]; + cb = &tls->stack[ndx]; cb->pc_cleaner(cb->pc_arg); } - tcb->tos = ndx; + tls->tos = ndx; } } @@ -123,9 +125,9 @@ static void pthread_cleanup_pop_tcb(FAR struct tcb_s *tcb, int execute) void pthread_cleanup_pop(int execute) { - FAR struct tcb_s *tcb = this_task(); + FAR struct tls_info_s *tls = up_tls_info(); - DEBUGASSERT(tcb != NULL); + DEBUGASSERT(tls != NULL); /* sched_lock() should provide sufficient protection. We only need to * have this TCB stationary; the pthread cleanup stack should never be @@ -133,20 +135,16 @@ void pthread_cleanup_pop(int execute) */ sched_lock(); - if ((tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL) - { - pthread_cleanup_pop_tcb(tcb, execute); - } - + pthread_cleanup_pop_tls(tls, execute); sched_unlock(); } void pthread_cleanup_push(pthread_cleanup_t routine, FAR void *arg) { - FAR struct tcb_s *tcb = this_task(); + FAR struct tls_info_s *tls = up_tls_info(); - DEBUGASSERT(tcb != NULL); - DEBUGASSERT(tcb->tos < CONFIG_PTHREAD_CLEANUP_STACKSIZE); + DEBUGASSERT(tls != NULL); + DEBUGASSERT(tls->tos < CONFIG_PTHREAD_CLEANUP_STACKSIZE); /* sched_lock() should provide sufficient protection. We only need to * have this TCB stationary; the pthread cleanup stack should never be @@ -154,14 +152,13 @@ void pthread_cleanup_push(pthread_cleanup_t routine, FAR void *arg) */ sched_lock(); - if ((tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL && - tcb->tos < CONFIG_PTHREAD_CLEANUP_STACKSIZE) + if (tls->tos < CONFIG_PTHREAD_CLEANUP_STACKSIZE) { - unsigned int ndx = tcb->tos; + unsigned int ndx = tls->tos; - tcb->tos++; - tcb->stack[ndx].pc_cleaner = routine; - tcb->stack[ndx].pc_arg = arg; + tls->tos++; + tls->stack[ndx].pc_cleaner = routine; + tls->stack[ndx].pc_arg = arg; } sched_unlock(); @@ -176,36 +173,26 @@ void pthread_cleanup_push(pthread_cleanup_t routine, FAR void *arg) * within the pthread_exit() and pthread_cancellation() logic * * Input Parameters: - * tcb - The TCB of the pthread that is exiting or being canceled. + * None * * Returned Value: * None * ****************************************************************************/ -void pthread_cleanup_popall(FAR struct tcb_s *tcb) +void pthread_cleanup_popall(void) { - DEBUGASSERT(tcb != NULL); + FAR struct tls_info_s *tls = up_tls_info(); - /* Kernel threads do not support pthread APIs */ + DEBUGASSERT(tls != NULL); - if ((tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL) + sched_lock(); + while (tls->tos > 0) { - /* Pop and execute each cleanup routine/ - * - * sched_lock() should provide sufficient protection. We only need to - * have this TCB stationary; the pthread cleanup stack should never be - * modified by interrupt level logic. - */ - - sched_lock(); - while (tcb->tos > 0) - { - pthread_cleanup_pop_tcb(tcb, 1); - } - - sched_unlock(); + pthread_cleanup_pop_tls(tls, 1); } + + sched_unlock(); } #endif /* CONFIG_PTHREAD_CLEANUP */ diff --git a/libs/libc/pthread/pthread_create.c b/libs/libc/pthread/pthread_create.c new file mode 100644 index 00000000000..c46e36fc602 --- /dev/null +++ b/libs/libc/pthread/pthread_create.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * libs/libc/pthread/pthread_create.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_startup + * + * Description: + * This function is the user space pthread startup function. Its purpose + * is to catch the return from the pthread main function so that + * pthread_exit() can be called from user space + * + * Input Parameters: + * entry - The user-space address of the pthread entry point + * arg - Standard argument for the pthread entry point + * + * Returned Value: + * None. This function does not return. + * + ****************************************************************************/ + +static void pthread_startup(pthread_startroutine_t entry, + pthread_addr_t arg) +{ + DEBUGASSERT(entry != NULL); + + /* Pass control to the thread entry point. Handle any returned value. */ + + pthread_exit(entry(arg)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_create + * + * Description: + * This function creates and activates a new thread with specified + * attributes. It is simply a wrapper around the nx_pthread_create system + * call. + * + * Input Parameters: + * thread + * attr + * pthread_entry + * arg + * + * Returned Value: + * OK (0) on success; a (non-negated) errno value on failure. The errno + * variable is not set. + * + ****************************************************************************/ + +int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, + pthread_startroutine_t pthread_entry, pthread_addr_t arg) +{ + return nx_pthread_create(pthread_startup, thread, attr, pthread_entry, + arg, pthread_exit); +} diff --git a/libs/libc/pthread/pthread_exit.c b/libs/libc/pthread/pthread_exit.c new file mode 100644 index 00000000000..22d684eaf22 --- /dev/null +++ b/libs/libc/pthread/pthread_exit.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * libs/libc/pthread/pthread_exit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_exit + * + * Description: + * Terminate execution of a thread started with pthread_create. + * + * Input Parameters: + * exit_value - The pointer of the pthread_exit parameter + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +void pthread_exit(FAR void *exit_value) +{ +#ifdef CONFIG_PTHREAD_CLEANUP + pthread_cleanup_popall(); +#endif + +#if CONFIG_TLS_NELEM > 0 + tls_destruct(); +#endif + + nx_pthread_exit(exit_value); + PANIC(); +} diff --git a/libs/libc/pthread/pthread_keycreate.c b/libs/libc/pthread/pthread_keycreate.c index 5765fb694d6..fb9e458b8d8 100644 --- a/libs/libc/pthread/pthread_keycreate.c +++ b/libs/libc/pthread/pthread_keycreate.c @@ -53,8 +53,6 @@ * key - A pointer to the key to create. * destructor - An optional destructor() function that may be associated * with each key that is invoked when a thread exits. - * However, this argument is ignored in the current - * implementation. * * Returned Value: * If successful, the pthread_key_create() function will store the newly @@ -67,9 +65,6 @@ * has been exceeded * ENOMEM - Insufficient memory exist to create the key. * - * POSIX Compatibility: - * - The present implementation ignores the destructor argument. - * ****************************************************************************/ int pthread_key_create(FAR pthread_key_t *key, @@ -81,15 +76,13 @@ int pthread_key_create(FAR pthread_key_t *key, /* Allocate a TLS index */ - tlsindex = tls_alloc(); + tlsindex = tls_alloc(destructor); /* Check if found a TLS index. */ if (tlsindex >= 0) { - /* Yes.. Return the key value and success */ - - *key = (pthread_key_t)tlsindex; + *key = tlsindex; return OK; } diff --git a/libs/libc/pthread/pthread_spinlock.c b/libs/libc/pthread/pthread_spinlock.c index 249c6816ea2..c72ac9d6737 100644 --- a/libs/libc/pthread/pthread_spinlock.c +++ b/libs/libc/pthread/pthread_spinlock.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #ifdef CONFIG_PTHREAD_SPINLOCKS diff --git a/libs/libc/semaphore/sem_setprotocol.c b/libs/libc/semaphore/sem_setprotocol.c index 762232b086d..f1418740bda 100644 --- a/libs/libc/semaphore/sem_setprotocol.c +++ b/libs/libc/semaphore/sem_setprotocol.c @@ -47,7 +47,7 @@ * TASK A TASK B * nxsem_init(sem, 0, 0); * nxsem_wait(sem); - * snxem_post(sem); + * nxsem_post(sem); * Awakens as holder * * In this case priority inheritance can interfere with the operation of diff --git a/libs/libc/stdio/lib_libfread.c b/libs/libc/stdio/lib_libfread.c index 96f9d5ac376..bd41e6f37f5 100644 --- a/libs/libc/stdio/lib_libfread.c +++ b/libs/libc/stdio/lib_libfread.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/libs/libc/stdio/lib_libvsprintf.c b/libs/libc/stdio/lib_libvsprintf.c index 7f147cf7923..5eb97425f82 100644 --- a/libs/libc/stdio/lib_libvsprintf.c +++ b/libs/libc/stdio/lib_libvsprintf.c @@ -375,7 +375,7 @@ static int vsprintf_internal(FAR struct lib_outstream_s *stream, } } - /* Note: On Nuttx, ptrdiff_t == intptr_t == ssize_t. */ + /* Note: On NuttX, ptrdiff_t == intptr_t == ssize_t. */ if (c == 'z' || c == 't') { diff --git a/libs/libc/stdio/lib_setvbuf.c b/libs/libc/stdio/lib_setvbuf.c index d82274d1446..100e07616d5 100644 --- a/libs/libc/stdio/lib_setvbuf.c +++ b/libs/libc/stdio/lib_setvbuf.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/libs/libc/stdio/lib_vfscanf.c b/libs/libc/stdio/lib_vfscanf.c index e4d793979da..b76d85faed0 100644 --- a/libs/libc/stdio/lib_vfscanf.c +++ b/libs/libc/stdio/lib_vfscanf.c @@ -1,35 +1,20 @@ /**************************************************************************** * libs/libc/stdio/lib_vfscanf.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Johannes Shock + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/stdlib/lib_div.c b/libs/libc/stdlib/lib_div.c index 780100b5cca..818056a8317 100644 --- a/libs/libc/stdlib/lib_div.c +++ b/libs/libc/stdlib/lib_div.c @@ -62,7 +62,7 @@ * denom - Denominator of the division * * Returned Value: - * The result of the devision represent as values of type div_t + * The result of the division represented as values of type div_t * ****************************************************************************/ diff --git a/libs/libc/stdlib/lib_ldiv.c b/libs/libc/stdlib/lib_ldiv.c index 1c86649a5cf..9b095e7c076 100644 --- a/libs/libc/stdlib/lib_ldiv.c +++ b/libs/libc/stdlib/lib_ldiv.c @@ -67,7 +67,7 @@ * denom - Denominator of the division * * Returned Value: - * The result of the devision represent as values of type ldiv_t + * The result of the division represented as values of type ldiv_t * ****************************************************************************/ diff --git a/libs/libc/stdlib/lib_lldiv.c b/libs/libc/stdlib/lib_lldiv.c index b5c54b12614..34ba598d221 100644 --- a/libs/libc/stdlib/lib_lldiv.c +++ b/libs/libc/stdlib/lib_lldiv.c @@ -69,7 +69,7 @@ * denom - Denominator of the division * * Returned Value: - * The result of the devision represent as values of type lldiv_t + * The result of the division represented as values of type lldiv_t * ****************************************************************************/ diff --git a/libs/libc/stdlib/lib_mktemp.c b/libs/libc/stdlib/lib_mktemp.c index 40114bc1a33..cfbf7eed1ed 100644 --- a/libs/libc/stdlib/lib_mktemp.c +++ b/libs/libc/stdlib/lib_mktemp.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/libs/libc/string/lib_strnlen.c b/libs/libc/string/lib_strnlen.c index 0491e4529d9..26f94198430 100644 --- a/libs/libc/string/lib_strnlen.c +++ b/libs/libc/string/lib_strnlen.c @@ -1,42 +1,20 @@ /**************************************************************************** * libs/libc/string/lib_strnlen.c * - * This file is part of NuttX, contributed by Michael Hrabanek + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Michael Hrabanek + * http://www.apache.org/licenses/LICENSE-2.0 * - * Derives from the file libs/libc/lib_strlen.c: - * - * Copyright (C) 2007, 2008, 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/libs/libc/termios/lib_ttyname.c b/libs/libc/termios/lib_ttyname.c index 42d8b0c38b6..f94a7ca3447 100644 --- a/libs/libc/termios/lib_ttyname.c +++ b/libs/libc/termios/lib_ttyname.c @@ -22,6 +22,7 @@ * Included Files ****************************************************************************/ +#include #include #include @@ -55,9 +56,12 @@ FAR char *ttyname(int fd) { static char name[TTY_NAME_MAX]; + int ret; - if (ttyname_r(fd, name, TTY_NAME_MAX) < 0) + ret = ttyname_r(fd, name, TTY_NAME_MAX); + if (ret != 0) { + set_errno(ret); return NULL; } diff --git a/libs/libc/termios/lib_ttynamer.c b/libs/libc/termios/lib_ttynamer.c index 61a4575a726..97dd6d11284 100644 --- a/libs/libc/termios/lib_ttynamer.c +++ b/libs/libc/termios/lib_ttynamer.c @@ -58,13 +58,12 @@ int ttyname_r(int fd, FAR char *buf, size_t buflen) { if (!isatty(fd)) { - set_errno(ENOTTY); - return ERROR; + return ENOTTY; } if (buflen >= TTY_NAME_MAX) { - return fcntl(fd, F_GETPATH, buf); + return fcntl(fd, F_GETPATH, buf) < 0 ? get_errno() : 0; } else { @@ -72,13 +71,12 @@ int ttyname_r(int fd, FAR char *buf, size_t buflen) if (fcntl(fd, F_GETPATH, name) < 0) { - return ERROR; + return get_errno(); } if (strlen(name) >= buflen) { - set_errno(ERANGE); - return ERROR; + return ERANGE; } strcpy(buf, name); diff --git a/libs/libc/time/lib_asctime.c b/libs/libc/time/lib_asctime.c index 6bdb9084aae..5504b037e17 100644 --- a/libs/libc/time/lib_asctime.c +++ b/libs/libc/time/lib_asctime.c @@ -42,7 +42,7 @@ * tp - Pointer to the time to be converted. * * Returned Value: - * One success a pointer to the string is returned; on failure, NULL is + * On success, a pointer to the string is returned; on failure, NULL is * returned. * ****************************************************************************/ diff --git a/libs/libc/time/lib_asctimer.c b/libs/libc/time/lib_asctimer.c index fc9712ad1fa..6db2480e809 100644 --- a/libs/libc/time/lib_asctimer.c +++ b/libs/libc/time/lib_asctimer.c @@ -63,7 +63,7 @@ static const char * const g_mon_name[12] = * buf - A user provided buffer to receive the 26 character time string. * * Returned Value: - * One success, the pointer to the 'buf' is returned; on failure, NULL is + * On success, the pointer to the 'buf' is returned; on failure, NULL is * returned. * ****************************************************************************/ diff --git a/libs/libc/time/lib_ctime.c b/libs/libc/time/lib_ctime.c index 0dc8d5ead7e..7f0c335829c 100644 --- a/libs/libc/time/lib_ctime.c +++ b/libs/libc/time/lib_ctime.c @@ -42,7 +42,7 @@ * timep - The current time represented as seconds since the epoch. * * Returned Value: - * One success a pointer to the string is returned; on failure, NULL is + * On success, a pointer to the string is returned; on failure, NULL is * returned. * ****************************************************************************/ diff --git a/libs/libc/time/lib_ctimer.c b/libs/libc/time/lib_ctimer.c index 54f188ab97c..55b4eac1b03 100644 --- a/libs/libc/time/lib_ctimer.c +++ b/libs/libc/time/lib_ctimer.c @@ -47,7 +47,7 @@ * buf - A user provided buffer to receive the 26 character time string. * * Returned Value: - * One success, the pointer to the 'buf' is returned; on failure, NULL is + * On success, the pointer to the 'buf' is returned; on failure, NULL is * returned. * ****************************************************************************/ diff --git a/libs/libc/time/lib_localtime.c b/libs/libc/time/lib_localtime.c index e2374c84ec4..e94b6239fcd 100644 --- a/libs/libc/time/lib_localtime.c +++ b/libs/libc/time/lib_localtime.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include diff --git a/libs/libc/tls/Make.defs b/libs/libc/tls/Make.defs index 504d2c6a0bf..8cc8e83f801 100644 --- a/libs/libc/tls/Make.defs +++ b/libs/libc/tls/Make.defs @@ -21,7 +21,8 @@ CSRCS += task_getinfo.c ifneq ($(CONFIG_TLS_NELEM),0) -CSRCS += tls_setvalue.c tls_getvalue.c +CSRCS += tls_alloc.c tls_free.c +CSRCS += tls_setvalue.c tls_getvalue.c tls_destruct.c endif ifneq ($(CONFIG_TLS_ALIGNED),y) diff --git a/libs/libc/tls/task_getinfo.c b/libs/libc/tls/task_getinfo.c index 26941274154..5163a43f54f 100644 --- a/libs/libc/tls/task_getinfo.c +++ b/libs/libc/tls/task_getinfo.c @@ -26,6 +26,7 @@ #include #include +#include /**************************************************************************** * Public Functions @@ -48,15 +49,7 @@ FAR struct task_info_s *task_get_info(void) { - FAR struct task_info_s *info = NULL; - struct stackinfo_s stackinfo; - int ret; + FAR struct tls_info_s *info = up_tls_info(); - ret = nxsched_get_stackinfo(-1, &stackinfo); - if (ret >= 0) - { - info = (FAR struct task_info_s *)stackinfo.stack_alloc_ptr; - } - - return info; + return info->tl_task; } diff --git a/sched/group/group_tlsalloc.c b/libs/libc/tls/tls_alloc.c similarity index 80% rename from sched/group/group_tlsalloc.c rename to libs/libc/tls/tls_alloc.c index 5b09073abc5..7563d3834fb 100644 --- a/sched/group/group_tlsalloc.c +++ b/libs/libc/tls/tls_alloc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * sched/group/group_tlsalloc.c + * libs/libc/tls/tls_alloc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -31,9 +31,7 @@ #include #include - -#include "sched/sched.h" -#include "group/group.h" +#include #if CONFIG_TLS_NELEM > 0 @@ -52,48 +50,49 @@ * * Returned Value: * A TLS index that is unique for use within this task group. + * If unsuccessful, an errno value will be returned and set to errno. * ****************************************************************************/ -int tls_alloc(void) +int tls_alloc(CODE void (*dtor)(FAR void *)) { - FAR struct tcb_s *rtcb = this_task(); - FAR struct task_group_s *group = rtcb->group; - irqstate_t flags; + FAR struct task_info_s *info = task_get_info(); int candidate; - int ret = -EAGAIN; + int ret; - DEBUGASSERT(group != NULL); + DEBUGASSERT(info); /* Search for an unused index. This is done in a critical section here to * avoid concurrent modification of the group TLS index set. */ - flags = spin_lock_irqsave(NULL); + ret = _SEM_WAIT(&info->ta_sem); + + if (ret < 0) + { + ret = _SEM_ERRVAL(ret); + return ret; + } + + ret = -EAGAIN; + for (candidate = 0; candidate < CONFIG_TLS_NELEM; candidate++) { /* Is this candidate index available? */ tls_ndxset_t mask = (1 << candidate); - if ((group->tg_tlsset & mask) == 0) + if ((info->ta_tlsset & mask) == 0) { /* Yes.. allocate the index and break out of the loop */ - group->tg_tlsset |= mask; + info->ta_tlsset |= mask; + info->ta_tlsdtor[candidate] = dtor; + ret = candidate; break; } } - spin_unlock_irqrestore(NULL, flags); - - /* Check if found a valid TLS data index. */ - - if (candidate < CONFIG_TLS_NELEM) - { - /* Yes.. Return the TLS index and success */ - - ret = candidate; - } + _SEM_POST(&info->ta_sem); return ret; } diff --git a/libs/libc/tls/tls_destruct.c b/libs/libc/tls/tls_destruct.c new file mode 100644 index 00000000000..c63f05d2c95 --- /dev/null +++ b/libs/libc/tls/tls_destruct.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * libs/libc/tls/tls_destruct.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#if CONFIG_TLS_NELEM > 0 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tls_destruct + * + * Description: + * Destruct all TLS data element associated with allocated key + * + * Input Parameters: + * None + * + * Returned Value: + * A set of allocated TLS index + * + ****************************************************************************/ + +void tls_destruct(void) +{ + FAR struct task_info_s *info = task_get_info(); + FAR struct tls_info_s *tls = up_tls_info(); + FAR void *tls_elem_ptr = NULL; + tls_dtor_t destructor; + tls_ndxset_t tlsset; + int candidate; + + DEBUGASSERT(info != NULL); + tlsset = info->ta_tlsset; + + for (candidate = 0; candidate < CONFIG_TLS_NELEM; candidate++) + { + /* Is this candidate index available? */ + + tls_ndxset_t mask = (1 << candidate); + if (tlsset & mask) + { + tls_elem_ptr = (FAR void *)tls->tl_elem[candidate]; + destructor = info->ta_tlsdtor[candidate]; + if (tls_elem_ptr && destructor) + { + destructor(tls_elem_ptr); + } + } + } +} + +#endif /* CONFIG_TLS_NELEM > 0 */ diff --git a/sched/group/group_tlsfree.c b/libs/libc/tls/tls_free.c similarity index 72% rename from sched/group/group_tlsfree.c rename to libs/libc/tls/tls_free.c index c1eccaf25df..e9f7eb576f7 100644 --- a/sched/group/group_tlsfree.c +++ b/libs/libc/tls/tls_free.c @@ -1,5 +1,5 @@ /**************************************************************************** - * sched/group/group_tlsfree.c + * libs/libc/tls/tls_free.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -30,9 +30,7 @@ #include #include - -#include "sched/sched.h" -#include "group/group.h" +#include #if CONFIG_TLS_NELEM > 0 @@ -50,36 +48,40 @@ * tlsindex - The previously allocated TLS index to be freed * * Returned Value: - * OK is returned on success; a negated errno value will be returned on - * failure: - * - * -EINVAL - the index to be freed is out of range. + * OK is returned on success; + * If unsuccessful an errno value will be returned and set to errno. + * -EINVAL - the index to be freed is out of range. + * -EINTR - the wait operation interrupted by signal + * -ECANCELED - the thread was canceled during waiting * ****************************************************************************/ int tls_free(int tlsindex) { - FAR struct tcb_s *rtcb = this_task(); - FAR struct task_group_s *group = rtcb->group; + FAR struct task_info_s *info = task_get_info(); tls_ndxset_t mask; - irqstate_t flags; int ret = -EINVAL; - DEBUGASSERT((unsigned)tlsindex < CONFIG_TLS_NELEM && group != NULL); + DEBUGASSERT((unsigned)tlsindex < CONFIG_TLS_NELEM && info != NULL); if ((unsigned)tlsindex < CONFIG_TLS_NELEM) { - /* This is done in a critical section here to avoid concurrent + /* This is done while holding a semaphore here to avoid concurrent * modification of the group TLS index set. */ mask = (1 << tlsindex); - flags = spin_lock_irqsave(NULL); - DEBUGASSERT((group->tg_tlsset & mask) != 0); - group->tg_tlsset &= ~mask; - spin_unlock_irqrestore(NULL, flags); - - ret = OK; + ret = _SEM_WAIT(&info->ta_sem); + if (ret == OK) + { + DEBUGASSERT((info->ta_tlsset & mask) != 0); + info->ta_tlsset &= ~mask; + _SEM_POST(&info->ta_sem); + } + else + { + ret = _SEM_ERRVAL(ret); + } } return ret; diff --git a/libs/libc/unistd/lib_getopt_common.c b/libs/libc/unistd/lib_getopt_common.c index 750a596f730..cd9e481260d 100644 --- a/libs/libc/unistd/lib_getopt_common.c +++ b/libs/libc/unistd/lib_getopt_common.c @@ -29,15 +29,6 @@ #include "unistd.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef optarg -#undef opterr -#undef optind -#undef optopt - /**************************************************************************** * Prive Functions ****************************************************************************/ diff --git a/libs/libc/userfs/lib_userfs.c b/libs/libc/userfs/lib_userfs.c index 6220d14e408..0b0c414bc8e 100644 --- a/libs/libc/userfs/lib_userfs.c +++ b/libs/libc/userfs/lib_userfs.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include diff --git a/libs/libdsp/lib_observer.c b/libs/libdsp/lib_observer.c index 8df03e3722d..8d8c11def3f 100644 --- a/libs/libdsp/lib_observer.c +++ b/libs/libdsp/lib_observer.c @@ -440,7 +440,7 @@ void motor_sobserver_div(FAR struct motor_observer_f32_s *o, so->angle_diff += dir * 2 * M_PI_F; } - /* Get absoulte value */ + /* Get absolute value */ if (so->angle_diff < 0.0f) { diff --git a/libs/libnx/nxfonts/Makefile.sources b/libs/libnx/nxfonts/Makefile.sources index 40e01d22e6c..499a46b2518 100644 --- a/libs/libnx/nxfonts/Makefile.sources +++ b/libs/libnx/nxfonts/Makefile.sources @@ -207,12 +207,12 @@ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-6x13.c endif ifeq ($(NXFONTS_FONTID),28) -NXFONTS_PREFIX := g_x11_misc_fixed_6x13B_ +NXFONTS_PREFIX := g_x11_misc_fixed_6x13b_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-6x13b.c endif ifeq ($(NXFONTS_FONTID),29) -NXFONTS_PREFIX := g_x11_misc_fixed_6x13O_ +NXFONTS_PREFIX := g_x11_misc_fixed_6x13o_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-6x13o.c endif @@ -222,12 +222,12 @@ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-7x13.c endif ifeq ($(NXFONTS_FONTID),31) -NXFONTS_PREFIX := g_x11_misc_fixed_7x13B_ +NXFONTS_PREFIX := g_x11_misc_fixed_7x13b_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-7x13b.c endif ifeq ($(NXFONTS_FONTID),32) -NXFONTS_PREFIX := g_x11_misc_fixed_7x13O_ +NXFONTS_PREFIX := g_x11_misc_fixed_7x13o_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-7x13o.c endif @@ -237,7 +237,7 @@ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-7x14.c endif ifeq ($(NXFONTS_FONTID),34) -NXFONTS_PREFIX := g_x11_misc_fixed_7x14B_ +NXFONTS_PREFIX := g_x11_misc_fixed_7x14b_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-7x14b.c endif @@ -247,12 +247,12 @@ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-8x13.c endif ifeq ($(NXFONTS_FONTID),36) -NXFONTS_PREFIX := g_x11_misc_fixed_8x13B_ +NXFONTS_PREFIX := g_x11_misc_fixed_8x13b_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-8x13b.c endif ifeq ($(NXFONTS_FONTID),37) -NXFONTS_PREFIX := g_x11_misc_fixed_8x13O_ +NXFONTS_PREFIX := g_x11_misc_fixed_8x13o_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-8x13o.c endif @@ -262,7 +262,7 @@ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-9x15.c endif ifeq ($(NXFONTS_FONTID),39) -NXFONTS_PREFIX := g_x11_misc_fixed_9x15B_ +NXFONTS_PREFIX := g_x11_misc_fixed_9x15b_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-9x15b.c endif @@ -272,7 +272,7 @@ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-9x18.c endif ifeq ($(NXFONTS_FONTID),41) -NXFONTS_PREFIX := g_x11_misc_fixed_9x18B_ +NXFONTS_PREFIX := g_x11_misc_fixed_9x18b_ GEN_CSRC = nxfonts_bitmaps_x11-misc-fixed-9x18b.c endif diff --git a/libs/libnx/nxfonts/nxfonts_cache.c b/libs/libnx/nxfonts/nxfonts_cache.c index e7a83439d56..a08ceeecc79 100644 --- a/libs/libnx/nxfonts/nxfonts_cache.c +++ b/libs/libnx/nxfonts/nxfonts_cache.c @@ -878,7 +878,7 @@ void nxf_cache_disconnect(FCACHE fhandle) * Zero (OK) is returned if the metrics were * * Returned Value: - * One success, a non-NULL font handle is returned. + * On success, a non-NULL font handle is returned. * ****************************************************************************/ diff --git a/libs/libxx/0001-libc-Fix-a-few-warnings.patch b/libs/libxx/0001-libc-Fix-a-few-warnings.patch deleted file mode 100644 index b7bb109a015..00000000000 --- a/libs/libxx/0001-libc-Fix-a-few-warnings.patch +++ /dev/null @@ -1,43 +0,0 @@ -From acd7be74ca12f8f08e52d6d80850a9b230109134 Mon Sep 17 00:00:00 2001 -From: YAMAMOTO Takashi -Date: Wed, 28 Oct 2020 15:40:16 -0400 -Subject: [PATCH] [libc++] Fix a few warnings - -Found during a NuttX porting effort. -But these changes are not directly relevant to NuttX. - -Differential Revision: https://reviews.llvm.org/D90139 ---- - src/filesystem/operations.cpp | 2 +- - src/locale.cpp | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/filesystem/operations.cpp libcxx/src/filesystem/operations.cpp -index 95d7d0d9642..788e31b673a 100644 ---- a/src/filesystem/operations.cpp -+++ libcxx/src/filesystem/operations.cpp -@@ -534,7 +534,7 @@ path __canonical(path const& orig_p, error_code* ec) { - ErrorHandler err("canonical", ec, &orig_p, &cwd); - - path p = __do_absolute(orig_p, &cwd, ec); --#if _POSIX_VERSION >= 200112 -+#if defined(_POSIX_VERSION) && _POSIX_VERSION >= 200112 - std::unique_ptr - hold(::realpath(p.c_str(), nullptr), &::free); - if (hold.get() == nullptr) -diff --git a/src/locale.cpp libcxx/src/locale.cpp -index b9180880e49..02dbb334ff8 100644 ---- a/src/locale.cpp -+++ libcxx/src/locale.cpp -@@ -1149,7 +1149,7 @@ ctype::__classic_upper_table() _NOEXCEPT - { - return _LIBCPP_GET_C_LOCALE->__ctype_toupper; - } --#elif __NetBSD__ -+#elif defined(__NetBSD__) - const short* - ctype::__classic_lower_table() _NOEXCEPT - { --- -2.17.1 - diff --git a/libs/libxx/0001-libc-Fix-tests-failing-with-Clang-after-removing-GCC.patch b/libs/libxx/0001-libc-Fix-tests-failing-with-Clang-after-removing-GCC.patch deleted file mode 100644 index 5e288388118..00000000000 --- a/libs/libxx/0001-libc-Fix-tests-failing-with-Clang-after-removing-GCC.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 81b6aa0e27abc3037c84d1ff2065bf60207f9b8b Mon Sep 17 00:00:00 2001 -From: Louis Dionne -Date: Fri, 30 Oct 2020 14:55:37 -0400 -Subject: [PATCH] [libc++] Fix tests failing with Clang after removing GCC - warnings - ---- - src/filesystem/filesystem_common.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/filesystem/filesystem_common.h libcxx/src/filesystem/filesystem_common.h -index a7828ef3863..dc55f93da70 100644 ---- a/src/filesystem/filesystem_common.h -+++ libcxx/src/filesystem/filesystem_common.h -@@ -198,7 +198,7 @@ private: - using chrono::duration; - using chrono::duration_cast; - --using TimeSpec = std::timespec; -+using TimeSpec = timespec; - using StatT = struct stat; - - template -Date: Fri, 30 Oct 2020 11:19:07 -0400 -Subject: [PATCH] [libc++] NFC: Fix several GCC warnings in the test suite - -- Several -Wshadow warnings -- Several places where we did not initialize our base class explicitly -- Unused variable warnings -- Some tautological comparisons -- Some places where we'd pass null arguments to functions expecting - non-null (in unevaluated contexts) -- Add a few pragmas to turn off spurious warnings -- Fix warnings about declarations that don't declare anything -- Properly disable deprecation warnings in ext/ tests (the pragmas we - were using didn't work on GCC) -- Disable include_as_c.sh.cpp because GCC complains about C++ flags - when compiling as C. I couldn't find a way to fix this one properly, - so I'm disabling the test. This isn't great, but at least we'll be - able to enable warnings in the whole test suite with GCC. ---- - src/filesystem/filesystem_common.h | 55 ++++++++++++----------- - 1 file changed, 28 insertions(+), 27 deletions(-) - -diff --git a/src/filesystem/filesystem_common.h libcxx/src/filesystem/filesystem_common.h -index fe5c42f5e6d..a7828ef3863 100644 ---- a/src/filesystem/filesystem_common.h -+++ libcxx/src/filesystem/filesystem_common.h -@@ -13,8 +13,9 @@ - #include "filesystem" - #include "array" - #include "chrono" --#include "cstdlib" - #include "climits" -+#include "cstdlib" -+#include "ctime" - - #include - #include -@@ -47,7 +48,7 @@ static string format_string_imp(const char* msg, ...) { - struct GuardVAList { - va_list& target; - bool active = true; -- GuardVAList(va_list& target) : target(target), active(true) {} -+ GuardVAList(va_list& tgt) : target(tgt), active(true) {} - void clear() { - if (active) - va_end(target); -@@ -134,50 +135,50 @@ path error_value() { - - template - struct ErrorHandler { -- const char* func_name; -- error_code* ec = nullptr; -- const path* p1 = nullptr; -- const path* p2 = nullptr; -+ const char* func_name_; -+ error_code* ec_ = nullptr; -+ const path* p1_ = nullptr; -+ const path* p2_ = nullptr; - - ErrorHandler(const char* fname, error_code* ec, const path* p1 = nullptr, - const path* p2 = nullptr) -- : func_name(fname), ec(ec), p1(p1), p2(p2) { -- if (ec) -- ec->clear(); -+ : func_name_(fname), ec_(ec), p1_(p1), p2_(p2) { -+ if (ec_) -+ ec_->clear(); - } - -- T report(const error_code& m_ec) const { -- if (ec) { -- *ec = m_ec; -+ T report(const error_code& ec) const { -+ if (ec_) { -+ *ec_ = ec; - return error_value(); - } -- string what = string("in ") + func_name; -- switch (bool(p1) + bool(p2)) { -+ string what = string("in ") + func_name_; -+ switch (bool(p1_) + bool(p2_)) { - case 0: -- __throw_filesystem_error(what, m_ec); -+ __throw_filesystem_error(what, ec); - case 1: -- __throw_filesystem_error(what, *p1, m_ec); -+ __throw_filesystem_error(what, *p1_, ec); - case 2: -- __throw_filesystem_error(what, *p1, *p2, m_ec); -+ __throw_filesystem_error(what, *p1_, *p2_, ec); - } - _LIBCPP_UNREACHABLE(); - } - - template -- T report(const error_code& m_ec, const char* msg, Args const&... args) const { -- if (ec) { -- *ec = m_ec; -+ T report(const error_code& ec, const char* msg, Args const&... args) const { -+ if (ec_) { -+ *ec_ = ec; - return error_value(); - } - string what = -- string("in ") + func_name + ": " + format_string(msg, args...); -- switch (bool(p1) + bool(p2)) { -+ string("in ") + func_name_ + ": " + format_string(msg, args...); -+ switch (bool(p1_) + bool(p2_)) { - case 0: -- __throw_filesystem_error(what, m_ec); -+ __throw_filesystem_error(what, ec); - case 1: -- __throw_filesystem_error(what, *p1, m_ec); -+ __throw_filesystem_error(what, *p1_, ec); - case 2: -- __throw_filesystem_error(what, *p1, *p2, m_ec); -+ __throw_filesystem_error(what, *p1_, *p2_, ec); - } - _LIBCPP_UNREACHABLE(); - } -@@ -197,8 +198,8 @@ private: - using chrono::duration; - using chrono::duration_cast; - --using TimeSpec = struct ::timespec; --using StatT = struct ::stat; -+using TimeSpec = std::timespec; -+using StatT = struct stat; - - template ::value> --- -2.17.1 - diff --git a/libs/libxx/0001-libcxx-Check-_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE-fir.patch b/libs/libxx/0001-libcxx-Check-_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE-fir.patch deleted file mode 100644 index 87572590281..00000000000 --- a/libs/libxx/0001-libcxx-Check-_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE-fir.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 3e8b517a509ae043571d8d0b00625d8a03eb5d05 Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Mon, 9 Nov 2020 21:45:57 +0800 -Subject: [PATCH] [libcxx] Check _LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE first in - __locale - -just like what's done in __locale.cpp - -Co-authored-by: Chao An - -Signed-off-by: Xiang Xiao - -Differential Revision: https://reviews.llvm.org/D91074 ---- - include/__locale | 40 +++++++++++++++++++++------------------- - 1 file changed, 21 insertions(+), 19 deletions(-) - -diff --git a/include/__locale libcxx/include/__locale -index 125adcf68c8..e973ce52646 100644 ---- a/include/__locale -+++ libcxx/include/__locale -@@ -397,7 +397,26 @@ locale::operator()(const basic_string<_CharT, _Traits, _Allocator>& __x, - class _LIBCPP_TYPE_VIS ctype_base - { - public: --#if defined(__GLIBC__) -+#if defined(_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE) -+ typedef unsigned long mask; -+ static const mask space = 1<<0; -+ static const mask print = 1<<1; -+ static const mask cntrl = 1<<2; -+ static const mask upper = 1<<3; -+ static const mask lower = 1<<4; -+ static const mask alpha = 1<<5; -+ static const mask digit = 1<<6; -+ static const mask punct = 1<<7; -+ static const mask xdigit = 1<<8; -+ static const mask blank = 1<<9; -+#if defined(__BIONIC__) -+ // Historically this was a part of regex_traits rather than ctype_base. The -+ // historical value of the constant is preserved for ABI compatibility. -+ static const mask __regex_word = 0x8000; -+#else -+ static const mask __regex_word = 1<<10; -+#endif // defined(__BIONIC__) -+#elif defined(__GLIBC__) - typedef unsigned short mask; - static const mask space = _ISspace; - static const mask print = _ISprint; -@@ -486,24 +505,7 @@ public: - # define _LIBCPP_CTYPE_MASK_IS_COMPOSITE_ALPHA - # define _LIBCPP_CTYPE_MASK_IS_COMPOSITE_XDIGIT - #else -- typedef unsigned long mask; -- static const mask space = 1<<0; -- static const mask print = 1<<1; -- static const mask cntrl = 1<<2; -- static const mask upper = 1<<3; -- static const mask lower = 1<<4; -- static const mask alpha = 1<<5; -- static const mask digit = 1<<6; -- static const mask punct = 1<<7; -- static const mask xdigit = 1<<8; -- static const mask blank = 1<<9; --#if defined(__BIONIC__) -- // Historically this was a part of regex_traits rather than ctype_base. The -- // historical value of the constant is preserved for ABI compatibility. -- static const mask __regex_word = 0x8000; --#else -- static const mask __regex_word = 1<<10; --#endif // defined(__BIONIC__) -+#error unkown classic_table, try _LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE - #endif - static const mask alnum = alpha | digit; - static const mask graph = alnum | punct; --- -2.17.1 - diff --git a/libs/libxx/0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch b/libs/libxx/0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch deleted file mode 100644 index b8f0efd7b56..00000000000 --- a/libs/libxx/0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 6b12d8b5c30a84aa5767b1b18ecf5ba5e99a1654 Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Fri, 2 Oct 2020 13:25:43 +0800 -Subject: [PATCH] [libcxx] Port to NuttX(https://nuttx.apache.org/) RTOS - -Since NuttX conform to POSIX standard, the code need to add is very simple - -Co-authored-by: YAMAMOTO Takashi - -Differential Revision: https://reviews.llvm.org/D88718 ---- - include/__config | 3 ++- - include/__locale | 2 ++ - include/support/nuttx/xlocale.h | 18 ++++++++++++++++++ - src/include/config_elast.h | 4 ++++ - src/locale.cpp | 2 +- - 5 files changed, 27 insertions(+), 2 deletions(-) - create mode 100644 include/support/nuttx/xlocale.h - -diff --git a/include/__config libcxx/include/__config -index eeef9c53a9f..9ace3b46028 100644 ---- a/include/__config -+++ libcxx/include/__config -@@ -1117,6 +1117,7 @@ _LIBCPP_FUNC_VIS extern "C" void __sanitizer_annotate_contiguous_container( - # if defined(__FreeBSD__) || \ - defined(__wasi__) || \ - defined(__NetBSD__) || \ -+ defined(__NuttX__) || \ - defined(__linux__) || \ - defined(__GNU__) || \ - defined(__APPLE__) || \ -@@ -1219,7 +1220,7 @@ _LIBCPP_FUNC_VIS extern "C" void __sanitizer_annotate_contiguous_container( - # endif - #endif - --#if defined(__BIONIC__) || defined(__CloudABI__) || \ -+#if defined(__BIONIC__) || defined(__CloudABI__) || defined(__NuttX__) || \ - defined(__Fuchsia__) || defined(__wasi__) || defined(_LIBCPP_HAS_MUSL_LIBC) - #define _LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE - #endif -diff --git a/include/__locale libcxx/include/__locale -index 125adcf68c8..ebededf066b 100644 ---- a/include/__locale -+++ libcxx/include/__locale -@@ -22,6 +22,8 @@ - #if defined(_LIBCPP_MSVCRT_LIKE) - # include - # include -+#elif defined(__NuttX__) -+# include - #elif defined(_AIX) - # include - #elif defined(__ANDROID__) -diff --git a/include/support/nuttx/xlocale.h libcxx/include/support/nuttx/xlocale.h -new file mode 100644 -index 00000000000..b70d6200504 ---- /dev/null -+++ libcxx/include/support/nuttx/xlocale.h -@@ -0,0 +1,18 @@ -+// -*- C++ -*- -+//===-------------------- support/nuttx/xlocale.h -------------------------===// -+// -+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -+// See https://llvm.org/LICENSE.txt for license information. -+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -+// -+//===----------------------------------------------------------------------===// -+ -+#ifndef _LIBCPP_SUPPORT_NUTTX_XLOCALE_H -+#define _LIBCPP_SUPPORT_NUTTX_XLOCALE_H -+ -+#if defined(__NuttX__) -+#include -+#include -+#endif // __NuttX__ -+ -+#endif -diff --git a/src/include/config_elast.h libcxx/src/include/config_elast.h -index 501cbc4ffeb..3113f9fb5cd 100644 ---- a/src/include/config_elast.h -+++ libcxx/src/include/config_elast.h -@@ -17,10 +17,14 @@ - #include - #endif - -+// Note: _LIBCPP_ELAST needs to be defined only on platforms -+// where strerror/strerror_r can't handle out-of-range errno values. - #if defined(ELAST) - #define _LIBCPP_ELAST ELAST - #elif defined(_NEWLIB_VERSION) - #define _LIBCPP_ELAST __ELASTERROR -+#elif defined(__NuttX__) -+// No _LIBCPP_ELAST needed on NuttX - #elif defined(__Fuchsia__) - // No _LIBCPP_ELAST needed on Fuchsia - #elif defined(__wasi__) -diff --git a/src/locale.cpp libcxx/src/locale.cpp -index 5fdc14992f8..ed93727b544 100644 ---- a/src/locale.cpp -+++ libcxx/src/locale.cpp -@@ -30,7 +30,7 @@ - #include "__sso_allocator" - #if defined(_LIBCPP_MSVCRT) || defined(__MINGW32__) - #include "support/win32/locale_win32.h" --#elif !defined(__BIONIC__) -+#elif !defined(__BIONIC__) && !defined(__NuttX__) - #include - #endif - #include --- -2.17.1 - diff --git a/libs/libxx/libcxx.defs b/libs/libxx/libcxx.defs index 29392c6309d..37c1f204099 100644 --- a/libs/libxx/libcxx.defs +++ b/libs/libxx/libcxx.defs @@ -18,7 +18,7 @@ # ########################################################################### -VERSION=11.0.0 +VERSION=12.0.0 #libcxx-$(VERSION).src.tar.xz: # $(Q) curl -O -L https://github.com/llvm/llvm-project/releases/download/llvmorg-$(VERSION)/libcxx-$(VERSION).src.tar.xz @@ -26,11 +26,6 @@ VERSION=11.0.0 #libcxx: libcxx-$(VERSION).src.tar.xz # $(Q) tar -xf libcxx-$(VERSION).src.tar.xz # $(Q) mv libcxx-$(VERSION).src libcxx -# $(Q) patch -p0 < 0001-libc-Fix-a-few-warnings.patch -# $(Q) patch -p0 < 0001-libc-NFC-Fix-several-GCC-warnings-in-the-test-suite.patch -# $(Q) patch -p0 < 0001-libc-Fix-tests-failing-with-Clang-after-removing-GCC.patch -# $(Q) patch -p0 < 0001-libcxx-Check-_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE-fir.patch -# $(Q) patch -p0 < 0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch # $(Q) touch $@ $(TOPDIR)/include/libcxx: libcxx diff --git a/libs/libxx/libxx_stdthrow.cxx b/libs/libxx/libxx_stdthrow.cxx index fe1e0527b10..2859581f475 100644 --- a/libs/libxx/libxx_stdthrow.cxx +++ b/libs/libxx/libxx_stdthrow.cxx @@ -1,35 +1,20 @@ //*************************************************************************** // libs/libxx/libxx_newa.cxx // -// Copyright (C) 2012 Gregory Nutt. All rights reserved. -// Author: Petteri Aimonen ; +// Licensed to the Apache Software Foundation (ASF) under one or more +// contributor license agreements. See the NOTICE file distributed with +// this work for additional information regarding copyright ownership. The +// ASF licenses this file to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance with the +// License. You may obtain a copy of the License at // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: +// http://www.apache.org/licenses/LICENSE-2.0 // -// 1. Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// 3. Neither the name NuttX nor the names of its contributors may be -// used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -// AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -// ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +// License for the specific language governing permissions and limitations +// under the License. // //*************************************************************************** diff --git a/mm/circbuf/circbuf.c b/mm/circbuf/circbuf.c index 8bf79568808..d8973c9ea1b 100644 --- a/mm/circbuf/circbuf.c +++ b/mm/circbuf/circbuf.c @@ -31,6 +31,8 @@ #include +#include + #include #include diff --git a/mm/iob/Kconfig b/mm/iob/Kconfig index 9327ee1d3b0..85dc43fb9b4 100644 --- a/mm/iob/Kconfig +++ b/mm/iob/Kconfig @@ -47,6 +47,9 @@ config IOB_NCHAINS I/O buffer chain containers that also carry a payload of usage specific information. + Note: TCP doesn't use this. + Note: UDP and CAN use this. + config IOB_THROTTLE int "I/O buffer throttle value" default 0 if !NET_WRITE_BUFFERS || !NET_READAHEAD diff --git a/mm/iob/Make.defs b/mm/iob/Make.defs index 50a7adf57b7..b69a2a04815 100644 --- a/mm/iob/Make.defs +++ b/mm/iob/Make.defs @@ -24,11 +24,11 @@ ifeq ($(CONFIG_MM_IOB),y) CSRCS += iob_add_queue.c iob_alloc.c iob_alloc_qentry.c iob_clone.c CSRCS += iob_concat.c iob_copyin.c iob_copyout.c iob_contig.c iob_free.c -CSRCS += iob_free_chain.c iob_free_qentry.c iob_destroy_queue.c -CSRCS += iob_free_queue.c iob_get_queue_count.c iob_get_queue_size.c +CSRCS += iob_free_chain.c iob_free_qentry.c iob_free_queue.c CSRCS += iob_initialize.c iob_pack.c iob_peek_queue.c iob_remove_queue.c CSRCS += iob_statistics.c iob_trimhead.c iob_trimhead_queue.c iob_trimtail.c -CSRCS += iob_navail.c +CSRCS += iob_navail.c iob_free_queue_qentry.c iob_tailroom.c +CSRCS += iob_get_queue_size.c ifeq ($(CONFIG_IOB_NOTIFIER),y) CSRCS += iob_notifier.c diff --git a/mm/iob/iob_add_queue.c b/mm/iob/iob_add_queue.c index 2a0069c4de7..31ff1fc620b 100644 --- a/mm/iob/iob_add_queue.c +++ b/mm/iob/iob_add_queue.c @@ -57,13 +57,11 @@ static int iob_add_queue_internal(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq, - FAR struct iob_qentry_s *qentry, - FAR void *priv) + FAR struct iob_qentry_s *qentry) { /* Add the I/O buffer chain to the container */ qentry->qe_head = iob; - qentry->qe_priv = priv; /* Add the container to the end of the queue */ @@ -96,8 +94,7 @@ static int iob_add_queue_internal(FAR struct iob_s *iob, * ****************************************************************************/ -int iob_add_queue(FAR struct iob_s *iob, FAR void *priv, - FAR struct iob_queue_s *iobq) +int iob_add_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq) { FAR struct iob_qentry_s *qentry; @@ -110,7 +107,7 @@ int iob_add_queue(FAR struct iob_s *iob, FAR void *priv, return -ENOMEM; } - return iob_add_queue_internal(iob, iobq, qentry, priv); + return iob_add_queue_internal(iob, iobq, qentry); } /**************************************************************************** @@ -122,8 +119,7 @@ int iob_add_queue(FAR struct iob_s *iob, FAR void *priv, * ****************************************************************************/ -int iob_tryadd_queue(FAR struct iob_s *iob, FAR void *priv, - FAR struct iob_queue_s *iobq) +int iob_tryadd_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq) { FAR struct iob_qentry_s *qentry; @@ -136,6 +132,6 @@ int iob_tryadd_queue(FAR struct iob_s *iob, FAR void *priv, return -ENOMEM; } - return iob_add_queue_internal(iob, iobq, qentry, priv); + return iob_add_queue_internal(iob, iobq, qentry); } #endif /* CONFIG_IOB_NCHAINS > 0 */ diff --git a/mm/iob/iob_alloc_qentry.c b/mm/iob/iob_alloc_qentry.c index 4a2107e05ee..567b9005349 100644 --- a/mm/iob/iob_alloc_qentry.c +++ b/mm/iob/iob_alloc_qentry.c @@ -223,7 +223,6 @@ FAR struct iob_qentry_s *iob_tryalloc_qentry(void) /* Put the I/O buffer in a known state */ iobq->qe_head = NULL; /* Nothing is contained */ - iobq->qe_priv = NULL; } leave_critical_section(flags); diff --git a/mm/iob/iob_destroy_queue.c b/mm/iob/iob_destroy_queue.c deleted file mode 100644 index 2de475b5f1f..00000000000 --- a/mm/iob/iob_destroy_queue.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * mm/iob/iob_destroy_queue.c - * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "iob.h" - -#if CONFIG_IOB_NCHAINS > 0 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef NULL -# define NULL ((FAR void *)0) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: iob_destroy_queue - * - * Description: - * Destroy all I/O buffer chains from the iob queue. - * - ****************************************************************************/ - -void iob_destroy_queue(FAR struct iob_queue_s *qhead, - enum iob_user_e producerid) -{ - FAR struct iob_qentry_s *iobq; - FAR struct iob_qentry_s *nextq; - FAR struct iob_s *iob; - - /* Detach the list from the queue head so first for safety (should be safe - * anyway). - */ - - iobq = qhead->qh_head; - qhead->qh_head = NULL; - - /* Remove each I/O buffer chain from the queue */ - - while (iobq) - { - /* Remove the I/O buffer chain from the head of the queue and - * discard the queue container. - */ - - iob = iobq->qe_head; - DEBUGASSERT(iob); - - /* Remove the queue container from the list and discard it */ - - nextq = iobq->qe_flink; - iob_free_qentry(iobq); - iobq = nextq; - - /* Free the I/O chain */ - - iob_free_chain(iob, producerid); - } -} - -#endif /* CONFIG_IOB_NCHAINS > 0 */ diff --git a/mm/iob/iob_free_queue.c b/mm/iob/iob_free_queue.c index 2753d5d2d67..81362604d18 100644 --- a/mm/iob/iob_free_queue.c +++ b/mm/iob/iob_free_queue.c @@ -23,7 +23,9 @@ ****************************************************************************/ #include + #include + #include #include "iob.h" @@ -50,43 +52,40 @@ * ****************************************************************************/ -void iob_free_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq, +void iob_free_queue(FAR struct iob_queue_s *qhead, enum iob_user_e producerid) { - FAR struct iob_qentry_s *prev = NULL; - FAR struct iob_qentry_s *qentry; + FAR struct iob_qentry_s *iobq; + FAR struct iob_qentry_s *nextq; + FAR struct iob_s *iob; - for (qentry = iobq->qh_head; qentry != NULL; - prev = qentry, qentry = qentry->qe_flink) + /* Detach the list from the queue head so first for safety (should be safe + * anyway). + */ + + iobq = qhead->qh_head; + qhead->qh_head = NULL; + + /* Remove each I/O buffer chain from the queue */ + + while (iobq) { - /* Find head of the I/O buffer chain */ + /* Remove the I/O buffer chain from the head of the queue and + * discard the queue container. + */ - if (qentry->qe_head == iob) - { - if (prev == NULL) - { - iobq->qh_head = qentry->qe_flink; - } - else - { - prev->qe_flink = qentry->qe_flink; - } + iob = iobq->qe_head; + DEBUGASSERT(iob); - if (iobq->qh_tail == qentry) - { - iobq->qh_tail = prev; - } + /* Remove the queue container from the list and discard it */ - /* Remove the queue container */ + nextq = iobq->qe_flink; + iob_free_qentry(iobq); + iobq = nextq; - iob_free_qentry(qentry); + /* Free the I/O chain */ - /* Free the I/O chain */ - - iob_free_chain(iob, producerid); - - break; - } + iob_free_chain(iob, producerid); } } diff --git a/mm/iob/iob_free_queue_qentry.c b/mm/iob/iob_free_queue_qentry.c new file mode 100644 index 00000000000..ef390845cbc --- /dev/null +++ b/mm/iob/iob_free_queue_qentry.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * mm/iob/iob_free_queue_qentry.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "iob.h" + +#if CONFIG_IOB_NCHAINS > 0 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef NULL +# define NULL ((FAR void *)0) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: iob_free_queue_qentry + * + * Description: + * Free an iob entire queue of I/O buffer chains. + * + ****************************************************************************/ + +void iob_free_queue_qentry(FAR struct iob_s *iob, + FAR struct iob_queue_s *iobq, + enum iob_user_e producerid) +{ + FAR struct iob_qentry_s *prev = NULL; + FAR struct iob_qentry_s *qentry; + + for (qentry = iobq->qh_head; qentry != NULL; + prev = qentry, qentry = qentry->qe_flink) + { + /* Find head of the I/O buffer chain */ + + if (qentry->qe_head == iob) + { + if (prev == NULL) + { + iobq->qh_head = qentry->qe_flink; + } + else + { + prev->qe_flink = qentry->qe_flink; + } + + if (iobq->qh_tail == qentry) + { + iobq->qh_tail = prev; + } + + /* Remove the queue container */ + + iob_free_qentry(qentry); + + /* Free the I/O chain */ + + iob_free_chain(iob, producerid); + + break; + } + } +} + +#endif /* CONFIG_IOB_NCHAINS > 0 */ diff --git a/mm/iob/iob_get_queue_size.c b/mm/iob/iob_get_queue_size.c index 28f304c7438..26146c2fa1f 100644 --- a/mm/iob/iob_get_queue_size.c +++ b/mm/iob/iob_get_queue_size.c @@ -36,7 +36,7 @@ * Name: iob_get_queue_size * * Description: - * Queue helper for get the iob entry count. + * Queue helper for get the iob queue buffer size. * ****************************************************************************/ @@ -48,10 +48,8 @@ unsigned int iob_get_queue_size(FAR struct iob_queue_s *queue) for (iobq = queue->qh_head; iobq != NULL; iobq = iobq->qe_flink) { - for (iob = iobq->qe_head; iob; iob = iob->io_flink) - { - total += iob->io_len; - } + iob = iobq->qe_head; + total += iob->io_pktlen; } return total; diff --git a/mm/iob/iob_statistics.c b/mm/iob/iob_statistics.c index eecde4bd2d5..47f5a6121a1 100644 --- a/mm/iob/iob_statistics.c +++ b/mm/iob/iob_statistics.c @@ -1,35 +1,20 @@ /**************************************************************************** * mm/iob/iob_statistics.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Anthony Merlino + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -42,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/mm/iob/iob_get_queue_count.c b/mm/iob/iob_tailroom.c similarity index 76% rename from mm/iob/iob_get_queue_count.c rename to mm/iob/iob_tailroom.c index 744d3ac31b5..d0c999156c8 100644 --- a/mm/iob/iob_get_queue_count.c +++ b/mm/iob/iob_tailroom.c @@ -1,5 +1,5 @@ /**************************************************************************** - * mm/iob/iob_get_queue_count.c + * mm/iob/iob_tailroom.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -23,38 +23,30 @@ ****************************************************************************/ #include -#include -#include "iob.h" -#if CONFIG_IOB_NCHAINS > 0 +#include + +#include "iob.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: iob_get_queue_count + * Name: iob_tailroom * * Description: - * Queue helper for get the iob entry count. + * Return the number of bytes at the tail of the I/O buffer chain which + * can be used to append data without additional allocations. * ****************************************************************************/ -int iob_get_queue_count(FAR struct iob_queue_s *queue) +unsigned int iob_tailroom(FAR struct iob_s *iob) { - FAR struct iob_qentry_s *iobq; - FAR struct iob_s *iob; - int count = 0; - - for (iobq = queue->qh_head; iobq != NULL; iobq = iobq->qe_flink) + while (iob->io_flink != NULL) { - for (iob = iobq->qe_head; iob; iob = iob->io_flink) - { - count++; - } + iob = iob->io_flink; } - return count; + return CONFIG_IOB_BUFSIZE - (iob->io_offset + iob->io_len); } - -#endif /* CONFIG_IOB_NCHAINS > 0 */ diff --git a/mm/mm_heap/mm_mallinfo.c b/mm/mm_heap/mm_mallinfo.c index bd732241ea8..b9a26afbe51 100644 --- a/mm/mm_heap/mm_mallinfo.c +++ b/mm/mm_heap/mm_mallinfo.c @@ -90,7 +90,7 @@ int mm_mallinfo(FAR struct mm_heap_s *heap, FAR struct mallinfo *info) if ((node->preceding & MM_ALLOC_BIT) != 0) { DEBUGASSERT(node->size >= SIZEOF_MM_ALLOCNODE); - aordblks ++; + aordblks++; uordblks += node->size; } else diff --git a/mm/shm/shmat.c b/mm/shm/shmat.c index e37ca014b06..7c7a76b736d 100644 --- a/mm/shm/shmat.c +++ b/mm/shm/shmat.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/mm/shm/shmdt.c b/mm/shm/shmdt.c index aae2772eee9..7008da85c7c 100644 --- a/mm/shm/shmdt.c +++ b/mm/shm/shmdt.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/net/Kconfig b/net/Kconfig index a3d57202863..083e6e1821d 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -117,6 +117,12 @@ config NET_GUARDSIZE packet size will be chopped down to the size indicated in the TCP header. +config NET_RECV_BUFSIZE + int "Net Receive buffer size" + default 0 + ---help--- + This is the default value for receive buffer size. + endmenu # Driver buffer configuration menu "Link layer support" diff --git a/net/can/can_callback.c b/net/can/can_callback.c index e4e561ecc17..7413ce277b8 100644 --- a/net/can/can_callback.c +++ b/net/can/can_callback.c @@ -221,7 +221,7 @@ uint16_t can_datahandler(FAR struct can_conn_s *conn, FAR uint8_t *buffer, * without waiting). */ - ret = iob_tryadd_queue(iob, NULL, &conn->readahead); + ret = iob_tryadd_queue(iob, &conn->readahead); if (ret < 0) { nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret); diff --git a/net/devif/devif_poll.c b/net/devif/devif_poll.c index 71f83bf3ebe..6865742eec6 100644 --- a/net/devif/devif_poll.c +++ b/net/devif/devif_poll.c @@ -554,7 +554,7 @@ static int devif_poll_udp_connections(FAR struct net_driver_s *dev, * Name: devif_poll_tcp_connections * * Description: - * Poll all UDP connections for available packets to send. + * Poll all TCP connections for available packets to send. * * Assumptions: * This function is called from the MAC device driver with the network diff --git a/net/devif/ipv4_input.c b/net/devif/ipv4_input.c index e0227a1f996..fa45b930e90 100644 --- a/net/devif/ipv4_input.c +++ b/net/devif/ipv4_input.c @@ -297,7 +297,14 @@ int ipv4_input(FAR struct net_driver_s *dev) } else #endif - if (ipv4->proto != IP_PROTO_UDP) +#if defined(NET_UDP_HAVE_STACK) && defined(CONFIG_NET_UDP_BINDTODEVICE) + /* If the UDP protocol specific socket option UDP_BINDTODEVICE + * is selected, then we must forward all UDP packets to the bound + * socket. + */ + + if (ipv4->proto != IP_PROTO_UDP || !IFF_IS_BOUND(dev->d_flags)) +#endif { /* Not destined for us and not forwardable... Drop the * packet. diff --git a/net/devif/ipv6_input.c b/net/devif/ipv6_input.c index 168cffdbe61..2c42602b37d 100644 --- a/net/devif/ipv6_input.c +++ b/net/devif/ipv6_input.c @@ -433,7 +433,14 @@ int ipv6_input(FAR struct net_driver_s *dev) } else #endif - if (nxthdr != IP_PROTO_UDP) +#if defined(NET_UDP_HAVE_STACK) && defined(CONFIG_NET_UDP_BINDTODEVICE) + /* If the UDP protocol specific socket option UDP_BINDTODEVICE + * is selected, then we must forward all UDP packets to the bound + * socket. + */ + + if (nxthdr != IP_PROTO_UDP || !IFF_IS_BOUND(dev->d_flags)) +#endif { /* Not destined for us and not forwardable... * drop the packet. diff --git a/net/icmp/icmp_input.c b/net/icmp/icmp_input.c index 44465d7cd50..525ee2c145c 100644 --- a/net/icmp/icmp_input.c +++ b/net/icmp/icmp_input.c @@ -190,7 +190,7 @@ static uint16_t icmp_datahandler(FAR struct net_driver_s *dev, * without waiting). */ - ret = iob_tryadd_queue(iob, NULL, &conn->readahead); + ret = iob_tryadd_queue(iob, &conn->readahead); if (ret < 0) { nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret); diff --git a/net/icmp/icmp_netpoll.c b/net/icmp/icmp_netpoll.c index a2505fc444a..a9ee08c43c2 100644 --- a/net/icmp/icmp_netpoll.c +++ b/net/icmp/icmp_netpoll.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/net/icmp/icmp_recvmsg.c b/net/icmp/icmp_recvmsg.c index 9ec2743aec2..013d7fe5e36 100644 --- a/net/icmp/icmp_recvmsg.c +++ b/net/icmp/icmp_recvmsg.c @@ -162,7 +162,7 @@ static uint16_t recvfrom_eventhandler(FAR struct net_driver_s *dev, /* Return the size of the returned data */ - DEBUGASSERT(recvsize > INT16_MAX); + DEBUGASSERT(recvsize <= INT16_MAX); pstate->recv_result = recvsize; /* Return the IPv4 address of the sender from the IPv4 header */ @@ -181,7 +181,8 @@ static uint16_t recvfrom_eventhandler(FAR struct net_driver_s *dev, /* Indicate that the data has been consumed */ - flags &= ~ICMP_NEWDATA; + flags &= ~ICMP_NEWDATA; + dev->d_len = 0; goto end_wait; } @@ -377,6 +378,8 @@ ssize_t icmp_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg, } } + net_lock(); + /* We cannot receive a response from a device until a request has been * sent to the devivce. */ @@ -388,32 +391,6 @@ ssize_t icmp_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg, goto errout; } - /* Check if there is buffered read-ahead data for this socket. We may have - * already received the response to previous command. - */ - - if (!IOB_QEMPTY(&conn->readahead)) - { - return icmp_readahead(conn, buf, len, - (FAR struct sockaddr_in *)from, fromlen); - } - - /* Initialize the state structure */ - - memset(&state, 0, sizeof(struct icmp_recvfrom_s)); - - /* This semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - - nxsem_init(&state.recv_sem, 0, 0); - nxsem_set_protocol(&state.recv_sem, SEM_PRIO_NONE); - - state.recv_sock = psock; /* The IPPROTO_ICMP socket instance */ - state.recv_result = -ENOMEM; /* Assume allocation failure */ - state.recv_buf = buf; /* Location to return the response */ - state.recv_buflen = len; /* Size of the response */ - /* Get the device that was used to send the ICMP request. */ dev = conn->dev; @@ -424,68 +401,102 @@ ssize_t icmp_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg, goto errout; } - net_lock(); + /* Check if there is buffered read-ahead data for this socket. We may have + * already received the response to previous command. + */ - /* Set up the callback */ - - state.recv_cb = icmp_callback_alloc(dev, conn); - if (state.recv_cb != NULL) + if (!IOB_QEMPTY(&conn->readahead)) { - state.recv_cb->flags = (ICMP_NEWDATA | NETDEV_DOWN); - state.recv_cb->priv = (FAR void *)&state; - state.recv_cb->event = recvfrom_eventhandler; + ret = icmp_readahead(conn, buf, len, + (FAR struct sockaddr_in *)from, fromlen); + } + else if (_SS_ISNONBLOCK(psock->s_flags) || (flags & MSG_DONTWAIT) != 0) + { + /* Handle non-blocking ICMP sockets */ - /* Wait for either the response to be received or for timeout to - * occur. net_timedwait will also terminate if a signal is received. + ret = -EAGAIN; + } + else + { + /* Initialize the state structure */ + + memset(&state, 0, sizeof(struct icmp_recvfrom_s)); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. */ - ret = net_timedwait(&state.recv_sem, _SO_TIMEOUT(psock->s_rcvtimeo)); - if (ret < 0) + nxsem_init(&state.recv_sem, 0, 0); + nxsem_set_protocol(&state.recv_sem, SEM_PRIO_NONE); + + state.recv_sock = psock; /* The IPPROTO_ICMP socket instance */ + state.recv_result = -ENOMEM; /* Assume allocation failure */ + state.recv_buf = buf; /* Location to return the response */ + state.recv_buflen = len; /* Size of the response */ + + /* Set up the callback */ + + state.recv_cb = icmp_callback_alloc(dev, conn); + if (state.recv_cb != NULL) { - state.recv_result = ret; + state.recv_cb->flags = (ICMP_NEWDATA | NETDEV_DOWN); + state.recv_cb->priv = (FAR void *)&state; + state.recv_cb->event = recvfrom_eventhandler; + + /* Wait for either the response to be received or for timeout to + * occur. net_timedwait will also terminate if a signal is + * received. + */ + + ret = net_timedwait(&state.recv_sem, + _SO_TIMEOUT(psock->s_rcvtimeo)); + if (ret < 0) + { + state.recv_result = ret; + } + + icmp_callback_free(dev, conn, state.recv_cb); } - icmp_callback_free(dev, conn, state.recv_cb); + /* Return the negated error number in the event of a failure, or the + * number of bytes received on success. + */ + + if (state.recv_result < 0) + { + nerr("ERROR: Return error=%d\n", state.recv_result); + ret = state.recv_result; + goto errout; + } + + if (from != NULL) + { + inaddr = (FAR struct sockaddr_in *)from; + inaddr->sin_family = AF_INET; + inaddr->sin_port = 0; + + net_ipv4addr_copy(inaddr->sin_addr.s_addr, state.recv_from); + } + + ret = state.recv_result; + + /* If there a no further outstanding requests, + * make sure that the request struct is left pristine. + */ + +errout: + if (conn->nreqs < 1) + { + conn->id = 0; + conn->nreqs = 0; + conn->dev = NULL; + + iob_free_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMP); + } } net_unlock(); - /* Return the negated error number in the event of a failure, or the - * number of bytes received on success. - */ - - if (state.recv_result < 0) - { - nerr("ERROR: Return error=%d\n", state.recv_result); - ret = state.recv_result; - goto errout; - } - - if (from != NULL) - { - inaddr = (FAR struct sockaddr_in *)from; - inaddr->sin_family = AF_INET; - inaddr->sin_port = 0; - - net_ipv4addr_copy(inaddr->sin_addr.s_addr, state.recv_from); - } - - ret = state.recv_result; - - /* If there a no further outstanding requests, make sure that the request - * struct is left pristine. - */ - -errout: - if (conn->nreqs < 1) - { - conn->id = 0; - conn->nreqs = 0; - conn->dev = NULL; - - iob_destroy_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMP); - } - return ret; } diff --git a/net/icmp/icmp_sendmsg.c b/net/icmp/icmp_sendmsg.c index a8abdbccffe..a4a8f834867 100644 --- a/net/icmp/icmp_sendmsg.c +++ b/net/icmp/icmp_sendmsg.c @@ -358,7 +358,7 @@ ssize_t icmp_sendmsg(FAR struct socket *psock, FAR struct msghdr *msg, conn->nreqs = 0; conn->dev = NULL; - iob_destroy_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMP); + iob_free_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMP); } #ifdef CONFIG_NET_ARP_SEND @@ -466,7 +466,7 @@ errout: conn->nreqs = 0; conn->dev = NULL; - iob_destroy_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMP); + iob_free_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMP); return ret; } diff --git a/net/icmp/icmp_sockif.c b/net/icmp/icmp_sockif.c index 691edbb4daa..6985ada6da6 100644 --- a/net/icmp/icmp_sockif.c +++ b/net/icmp/icmp_sockif.c @@ -161,7 +161,7 @@ static int icmp_setup(FAR struct socket *psock, int protocol) static sockcaps_t icmp_sockcaps(FAR struct socket *psock) { - return 0; + return SOCKCAP_NONBLOCKING; } /**************************************************************************** @@ -475,7 +475,7 @@ static int icmp_close(FAR struct socket *psock) { /* Yes... free any read-ahead data */ - iob_destroy_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMP); + iob_free_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMP); /* Then free the connection structure */ diff --git a/net/icmpv6/icmpv6_autoconfig.c b/net/icmpv6/icmpv6_autoconfig.c index 02aa42ac6e1..968fe24848e 100644 --- a/net/icmpv6/icmpv6_autoconfig.c +++ b/net/icmpv6/icmpv6_autoconfig.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/net/icmpv6/icmpv6_input.c b/net/icmpv6/icmpv6_input.c index 13209855e22..0cbc391e2fd 100644 --- a/net/icmpv6/icmpv6_input.c +++ b/net/icmpv6/icmpv6_input.c @@ -193,7 +193,7 @@ static uint16_t icmpv6_datahandler(FAR struct net_driver_s *dev, * without waiting). */ - ret = iob_tryadd_queue(iob, NULL, &conn->readahead); + ret = iob_tryadd_queue(iob, &conn->readahead); if (ret < 0) { nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret); diff --git a/net/icmpv6/icmpv6_netpoll.c b/net/icmpv6/icmpv6_netpoll.c index 3b7d7417252..756e4c22e4d 100644 --- a/net/icmpv6/icmpv6_netpoll.c +++ b/net/icmpv6/icmpv6_netpoll.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/net/icmpv6/icmpv6_notify.c b/net/icmpv6/icmpv6_notify.c index d5991869059..8319f40cbd7 100644 --- a/net/icmpv6/icmpv6_notify.c +++ b/net/icmpv6/icmpv6_notify.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/net/icmpv6/icmpv6_recvmsg.c b/net/icmpv6/icmpv6_recvmsg.c index 6481f467b0b..0c764a771eb 100644 --- a/net/icmpv6/icmpv6_recvmsg.c +++ b/net/icmpv6/icmpv6_recvmsg.c @@ -169,7 +169,7 @@ static uint16_t recvfrom_eventhandler(FAR struct net_driver_s *dev, /* Return the size of the returned data */ - DEBUGASSERT(recvsize > INT16_MAX); + DEBUGASSERT(recvsize <= INT16_MAX); pstate->recv_result = recvsize; /* Return the IPv6 address of the sender from the IPv6 header */ @@ -188,7 +188,8 @@ static uint16_t recvfrom_eventhandler(FAR struct net_driver_s *dev, /* Indicate that the data has been consumed */ - flags &= ~ICMPv6_NEWDATA; + flags &= ~ICMPv6_NEWDATA; + dev->d_len = 0; goto end_wait; } @@ -384,6 +385,8 @@ ssize_t icmpv6_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg, } } + net_lock(); + /* We cannot receive a response from a device until a request has been * sent to the devivce. */ @@ -395,32 +398,6 @@ ssize_t icmpv6_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg, goto errout; } - /* Check if there is buffered read-ahead data for this socket. We may have - * already received the response to previous command. - */ - - if (!IOB_QEMPTY(&conn->readahead)) - { - return icmpv6_readahead(conn, buf, len, - (FAR struct sockaddr_in6 *)from, fromlen); - } - - /* Initialize the state structure */ - - memset(&state, 0, sizeof(struct icmpv6_recvfrom_s)); - - /* This semaphore is used for signaling and, hence, should not have - * priority inheritance enabled. - */ - - nxsem_init(&state.recv_sem, 0, 0); - nxsem_set_protocol(&state.recv_sem, SEM_PRIO_NONE); - - state.recv_sock = psock; /* The IPPROTO_ICMP6 socket instance */ - state.recv_result = -ENOMEM; /* Assume allocation failure */ - state.recv_buf = buf; /* Location to return the response */ - state.recv_buflen = len; /* Size of the response */ - /* Get the device that was used to send the ICMPv6 request. */ dev = conn->dev; @@ -431,72 +408,105 @@ ssize_t icmpv6_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg, goto errout; } - net_lock(); + /* Check if there is buffered read-ahead data for this socket. We may have + * already received the response to previous command. + */ - /* Set up the callback */ - - state.recv_cb = icmpv6_callback_alloc(dev, conn); - if (state.recv_cb) + if (!IOB_QEMPTY(&conn->readahead)) { - state.recv_cb->flags = (ICMPv6_NEWDATA | NETDEV_DOWN); - state.recv_cb->priv = (FAR void *)&state; - state.recv_cb->event = recvfrom_eventhandler; + ret = icmpv6_readahead(conn, buf, len, + (FAR struct sockaddr_in6 *)from, fromlen); + } + else if (_SS_ISNONBLOCK(psock->s_flags) || (flags & MSG_DONTWAIT) != 0) + { + /* Handle non-blocking ICMP sockets */ - /* Wait for either the response to be received or for timeout to - * occur. (1) net_timedwait will also terminate if a signal is - * received, (2) interrupts may be disabled! They will be re-enabled - * while the task sleeps and automatically re-enabled when the task - * restarts. + ret = -EAGAIN; + } + else + { + /* Initialize the state structure */ + + memset(&state, 0, sizeof(struct icmpv6_recvfrom_s)); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. */ - ret = net_timedwait(&state.recv_sem, _SO_TIMEOUT(psock->s_rcvtimeo)); - if (ret < 0) + nxsem_init(&state.recv_sem, 0, 0); + nxsem_set_protocol(&state.recv_sem, SEM_PRIO_NONE); + + state.recv_sock = psock; /* The IPPROTO_ICMP6 socket instance */ + state.recv_result = -ENOMEM; /* Assume allocation failure */ + state.recv_buf = buf; /* Location to return the response */ + state.recv_buflen = len; /* Size of the response */ + + /* Set up the callback */ + + state.recv_cb = icmpv6_callback_alloc(dev, conn); + if (state.recv_cb) { - state.recv_result = ret; + state.recv_cb->flags = (ICMPv6_NEWDATA | NETDEV_DOWN); + state.recv_cb->priv = (FAR void *)&state; + state.recv_cb->event = recvfrom_eventhandler; + + /* Wait for either the response to be received or for timeout to + * occur. (1) net_timedwait will also terminate if a signal is + * received, (2) interrupts may be disabled! They will be + * re-enabled while the task sleeps and automatically re-enabled + * when the task restarts. + */ + + ret = net_timedwait(&state.recv_sem, + _SO_TIMEOUT(psock->s_rcvtimeo)); + if (ret < 0) + { + state.recv_result = ret; + } + + icmpv6_callback_free(dev, conn, state.recv_cb); } - icmpv6_callback_free(dev, conn, state.recv_cb); + /* Return the negated error number in the event of a failure, or the + * number of bytes received on success. + */ + + if (state.recv_result < 0) + { + nerr("ERROR: Return error=%d\n", state.recv_result); + ret = state.recv_result; + goto errout; + } + + if (from != NULL) + { + inaddr = (FAR struct sockaddr_in6 *)from; + inaddr->sin6_family = AF_INET6; + inaddr->sin6_port = 0; + + net_ipv6addr_copy(inaddr->sin6_addr.s6_addr16, + state.recv_from.s6_addr16); + } + + ret = state.recv_result; + + /* If there a no further outstanding requests, + * make sure that the request struct is left pristine. + */ + +errout: + if (conn->nreqs < 1) + { + conn->id = 0; + conn->nreqs = 0; + conn->dev = NULL; + + iob_free_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMPv6); + } } net_unlock(); - /* Return the negated error number in the event of a failure, or the - * number of bytes received on success. - */ - - if (state.recv_result < 0) - { - nerr("ERROR: Return error=%d\n", state.recv_result); - ret = state.recv_result; - goto errout; - } - - if (from != NULL) - { - inaddr = (FAR struct sockaddr_in6 *)from; - inaddr->sin6_family = AF_INET6; - inaddr->sin6_port = 0; - - net_ipv6addr_copy(inaddr->sin6_addr.s6_addr16, - state.recv_from.s6_addr16); - } - - ret = state.recv_result; - - /* If there a no further outstanding requests, make sure that the request - * struct is left pristine. - */ - -errout: - if (conn->nreqs < 1) - { - conn->id = 0; - conn->nreqs = 0; - conn->dev = NULL; - - iob_destroy_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMPv6); - } - return ret; } diff --git a/net/icmpv6/icmpv6_rnotify.c b/net/icmpv6/icmpv6_rnotify.c index 95f217d0bd5..3e0caca7fe7 100644 --- a/net/icmpv6/icmpv6_rnotify.c +++ b/net/icmpv6/icmpv6_rnotify.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/net/icmpv6/icmpv6_sendmsg.c b/net/icmpv6/icmpv6_sendmsg.c index d5f943cd324..f8c4fb13766 100644 --- a/net/icmpv6/icmpv6_sendmsg.c +++ b/net/icmpv6/icmpv6_sendmsg.c @@ -349,7 +349,7 @@ ssize_t icmpv6_sendmsg(FAR struct socket *psock, FAR struct msghdr *msg, conn->nreqs = 0; conn->dev = NULL; - iob_destroy_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMPv6); + iob_free_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMPv6); } #ifdef CONFIG_NET_ICMPv6_NEIGHBOR @@ -457,7 +457,7 @@ errout: conn->nreqs = 0; conn->dev = NULL; - iob_destroy_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMPv6); + iob_free_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMPv6); return ret; } diff --git a/net/icmpv6/icmpv6_sockif.c b/net/icmpv6/icmpv6_sockif.c index f579ed441f9..a0a54566730 100644 --- a/net/icmpv6/icmpv6_sockif.c +++ b/net/icmpv6/icmpv6_sockif.c @@ -161,7 +161,7 @@ static int icmpv6_setup(FAR struct socket *psock, int protocol) static sockcaps_t icmpv6_sockcaps(FAR struct socket *psock) { - return 0; + return SOCKCAP_NONBLOCKING; } /**************************************************************************** @@ -475,7 +475,7 @@ static int icmpv6_close(FAR struct socket *psock) { /* Yes... free any read-ahead data */ - iob_destroy_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMPv6); + iob_free_queue(&conn->readahead, IOBUSER_NET_SOCK_ICMPv6); /* Then free the connection structure */ diff --git a/net/igmp/igmp_group.c b/net/igmp/igmp_group.c index 31ca186a096..d2573d408f4 100644 --- a/net/igmp/igmp_group.c +++ b/net/igmp/igmp_group.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include diff --git a/net/inet/inet_sockif.c b/net/inet/inet_sockif.c index b37df49a20e..3559e606624 100644 --- a/net/inet/inet_sockif.c +++ b/net/inet/inet_sockif.c @@ -1289,7 +1289,7 @@ static ssize_t inet_sendmsg(FAR struct socket *psock, for (len = 0, iov = msg->msg_iov; iov != end; iov++) { - memcpy(buf + len, iov->iov_base, iov->iov_len); + memcpy(((unsigned char *)buf) + len, iov->iov_base, iov->iov_len); len += iov->iov_len; } @@ -1355,8 +1355,11 @@ static int inet_ioctl(FAR struct socket *psock, int cmd, static int inet_socketpair(FAR struct socket *psocks[2]) { - FAR struct socket *pserver; +#if defined(CONFIG_NET_TCP) || defined(CONFIG_NET_UDP) + FAR struct socket *pserver = psocks[1]; +#if defined(CONFIG_NET_TCP) FAR struct socket server; +#endif union sockaddr_u addr[2]; socklen_t len; int ret; @@ -1396,6 +1399,7 @@ static int inet_socketpair(FAR struct socket *psocks[2]) * pserver process, psocks[1] will be replaced with a new accept handle */ +#if defined(CONFIG_NET_TCP) if (psocks[0]->s_type == SOCK_STREAM) { ret = psock_socket(psocks[1]->s_domain, psocks[1]->s_type, @@ -1407,10 +1411,7 @@ static int inet_socketpair(FAR struct socket *psocks[2]) pserver = &server; } - else - { - pserver = psocks[1]; - } +#endif /* CONFIG_NET_TCP */ ret = psock_bind(pserver, &addr[1].addr, len); if (ret < 0) @@ -1420,6 +1421,7 @@ static int inet_socketpair(FAR struct socket *psocks[2]) psock_getsockname(pserver, &addr[1].addr, &len); +#if defined(CONFIG_NET_UDP) if (psocks[0]->s_type == SOCK_DGRAM) { ret = psock_connect(psocks[0], &addr[1].addr, len); @@ -1434,7 +1436,10 @@ static int inet_socketpair(FAR struct socket *psocks[2]) goto errout; } } - else +#endif /* CONFIG_NET_UDP */ + +#if defined(CONFIG_NET_TCP) + if (psocks[0]->s_type == SOCK_STREAM) { ret = psock_listen(pserver, 2); if (ret < 0) @@ -1456,14 +1461,20 @@ static int inet_socketpair(FAR struct socket *psocks[2]) ret = psock_accept(pserver, &addr[1].addr, &len, psocks[1]); } +#endif /* CONFIG_NET_TCP */ errout: +#if defined(CONFIG_NET_TCP) if (pserver->s_type == SOCK_STREAM) { psock_close(pserver); } +#endif /* CONFIG_NET_TCP */ return ret; +#else + return -EOPNOTSUPP; +#endif /* CONFIG_NET_TCP || CONFIG_NET_UDP */ } /**************************************************************************** diff --git a/net/ipforward/ipv4_forward.c b/net/ipforward/ipv4_forward.c index f3e25193d08..298a274dbea 100644 --- a/net/ipforward/ipv4_forward.c +++ b/net/ipforward/ipv4_forward.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/net/local/local.h b/net/local/local.h index 37fb7bb0aa4..b37795fc895 100644 --- a/net/local/local.h +++ b/net/local/local.h @@ -252,6 +252,19 @@ FAR struct local_conn_s *local_alloc(void); void local_free(FAR struct local_conn_s *conn); +/**************************************************************************** + * Name: local_nextconn + * + * Description: + * Traverse the list of allocated Local connections + * + * Assumptions: + * Called from network stack logic with the network stack locked + * + ****************************************************************************/ + +FAR struct local_conn_s *local_nextconn(FAR struct local_conn_s *conn); + /**************************************************************************** * Name: psock_local_bind * diff --git a/net/local/local_conn.c b/net/local/local_conn.c index 9f61bfa4593..e6e421e31e5 100644 --- a/net/local/local_conn.c +++ b/net/local/local_conn.c @@ -55,6 +55,33 @@ void local_initialize(void) #endif } +/**************************************************************************** + * Name: local_nextconn + * + * Description: + * Traverse the list of listened local connections + * + * Assumptions: + * This function must be called with the network locked. + * + ****************************************************************************/ + +FAR struct local_conn_s *local_nextconn(FAR struct local_conn_s *conn) +{ +#ifdef CONFIG_NET_LOCAL_STREAM + if (!conn) + { + return (FAR struct local_conn_s *)g_local_listeners.head; + } + else + { + return (FAR struct local_conn_s *)conn->lc_node.flink; + } +#else + return NULL; +#endif +} + /**************************************************************************** * Name: local_alloc() * diff --git a/net/local/local_connect.c b/net/local/local_connect.c index 7e7e55e4768..cbff13df028 100644 --- a/net/local/local_connect.c +++ b/net/local/local_connect.c @@ -246,7 +246,7 @@ int psock_local_connect(FAR struct socket *psock, { FAR struct local_conn_s *client; FAR struct sockaddr_un *unaddr = (FAR struct sockaddr_un *)addr; - FAR struct local_conn_s *conn; + FAR struct local_conn_s *conn = NULL; DEBUGASSERT(psock && psock->s_conn); client = (FAR struct local_conn_s *)psock->s_conn; @@ -260,9 +260,7 @@ int psock_local_connect(FAR struct socket *psock, /* Find the matching server connection */ net_lock(); - for (conn = (FAR struct local_conn_s *)g_local_listeners.head; - conn; - conn = (FAR struct local_conn_s *)dq_next(&conn->lc_node)) + while ((conn = local_nextconn(conn)) != NULL) { /* Anything in the listener list should be a stream socket in the * listening state diff --git a/net/local/local_fifo.c b/net/local/local_fifo.c index 1dc66a17e55..905461288fa 100644 --- a/net/local/local_fifo.c +++ b/net/local/local_fifo.c @@ -36,6 +36,7 @@ #include #include #include +#include #include "local/local.h" diff --git a/net/local/local_sockif.c b/net/local/local_sockif.c index 561377567c3..8472c106906 100644 --- a/net/local/local_sockif.c +++ b/net/local/local_sockif.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -70,6 +71,7 @@ static int local_poll(FAR struct socket *psock, static int local_close(FAR struct socket *psock); static int local_ioctl(FAR struct socket *psock, int cmd, FAR void *arg, size_t arglen); +static int local_socketpair(FAR struct socket *psocks[2]); /**************************************************************************** * Public Data @@ -90,7 +92,8 @@ const struct sock_intf_s g_local_sockif = local_sendmsg, /* si_sendmsg */ local_recvmsg, /* si_recvmsg */ local_close, /* si_close */ - local_ioctl /* si_ioctl */ + local_ioctl, /* si_ioctl */ + local_socketpair /* si_socketpair */ }; /**************************************************************************** @@ -715,15 +718,119 @@ static int local_ioctl(FAR struct socket *psock, int cmd, { ret = file_ioctl(&conn->lc_infile, cmd, arg); } + else + { + ret = -ENOTCONN; + } break; default: - ret = -EINVAL; + ret = -ENOTTY; break; } return ret; } +/**************************************************************************** + * Name: local_socketpair + * + * Description: + * Create a pair of connected sockets between psocks[2] + * + * Parameters: + * psocks A reference to the socket structure of the socket pair + * + ****************************************************************************/ + +static int local_socketpair(FAR struct socket *psocks[2]) +{ +#if defined(CONFIG_NET_LOCAL_STREAM) || defined(CONFIG_NET_LOCAL_DGRAM) + FAR struct local_conn_s *conns[2]; +#ifdef CONFIG_NET_LOCAL_STREAM + bool nonblock; + int ret; +#endif /* CONFIG_NET_LOCAL_STREAM */ + int i; + + for (i = 0; i < 2; i++) + { + conns[i] = psocks[i]->s_conn; + snprintf(conns[i]->lc_path, + sizeof(conns[i]->lc_path), "socketpair%p", psocks[0]); + + conns[i]->lc_proto = psocks[i]->s_type; + conns[i]->lc_type = LOCAL_TYPE_PATHNAME; + conns[i]->lc_state = LOCAL_STATE_BOUND; + } + +#ifdef CONFIG_NET_LOCAL_DGRAM +#ifdef CONFIG_NET_LOCAL_STREAM + if (psocks[0]->s_type == SOCK_DGRAM) +#endif /* CONFIG_NET_LOCAL_STREAM */ + { + return OK; + } +#endif /* CONFIG_NET_LOCAL_DGRAM */ + +#ifdef CONFIG_NET_LOCAL_STREAM + conns[0]->lc_instance_id = conns[1]->lc_instance_id + = local_generate_instance_id(); + + /* Create the FIFOs needed for the connection */ + + ret = local_create_fifos(conns[0]); + if (ret < 0) + { + goto errout; + } + + nonblock = _SS_ISNONBLOCK(psocks[0]->s_flags); + + /* Open the client-side write-only FIFO. */ + + ret = local_open_client_tx(conns[0], nonblock); + if (ret < 0) + { + goto errout; + } + + /* Open the server-side read-only FIFO. */ + + ret = local_open_server_rx(conns[1], nonblock); + if (ret < 0) + { + goto errout; + } + + /* Open the server-side write-only FIFO. */ + + ret = local_open_server_tx(conns[1], nonblock); + if (ret < 0) + { + goto errout; + } + + /* Open the client-side read-only FIFO */ + + ret = local_open_client_rx(conns[0], nonblock); + if (ret < 0) + { + goto errout; + } + + conns[0]->lc_state = conns[1]->lc_state + = LOCAL_STATE_CONNECTED; + return OK; + +errout: + local_release_fifos(conns[0]); + return ret; +#endif /* CONFIG_NET_LOCAL_STREAM */ +#else + return -EOPNOTSUPP; +#endif /* CONFIG_NET_LOCAL_STREAM || CONFIG_NET_LOCAL_DGRAM */ +} + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/net/mld/mld_group.c b/net/mld/mld_group.c index cd7bf688cfd..f76c1d0e0ce 100644 --- a/net/mld/mld_group.c +++ b/net/mld/mld_group.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/net/mld/mld_send.c b/net/mld/mld_send.c index 03594c806ea..a1acac67216 100644 --- a/net/mld/mld_send.c +++ b/net/mld/mld_send.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/net/neighbor/neighbor_dumpentry.c b/net/neighbor/neighbor_dumpentry.c index 63284f658e9..ca6ecb2fec0 100644 --- a/net/neighbor/neighbor_dumpentry.c +++ b/net/neighbor/neighbor_dumpentry.c @@ -1,33 +1,20 @@ /**************************************************************************** * net/neighbor/neighbor_dumpentry.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/net/neighbor/neighbor_ethernet_out.c b/net/neighbor/neighbor_ethernet_out.c index f02e60b2dd6..09d97b21984 100644 --- a/net/neighbor/neighbor_ethernet_out.c +++ b/net/neighbor/neighbor_ethernet_out.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/net/netdev/netdev_register.c b/net/netdev/netdev_register.c index ee5da2dc8d5..cc70c2afa47 100644 --- a/net/netdev/netdev_register.c +++ b/net/netdev/netdev_register.c @@ -434,6 +434,7 @@ int netdev_register(FAR struct net_driver_s *dev, enum net_lltype_e lltype) { last = &((*last)->flink); } + *last = dev; dev->flink = NULL; diff --git a/net/procfs/netdev_statistics.c b/net/procfs/netdev_statistics.c index d5f8b270592..4919053b78f 100644 --- a/net/procfs/netdev_statistics.c +++ b/net/procfs/netdev_statistics.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/net/rpmsg/rpmsg_sockif.c b/net/rpmsg/rpmsg_sockif.c index df41efb9393..735d388940b 100644 --- a/net/rpmsg/rpmsg_sockif.c +++ b/net/rpmsg/rpmsg_sockif.c @@ -24,9 +24,11 @@ #include +#include #include #include #include +#include #include #include @@ -1082,7 +1084,7 @@ static ssize_t rpmsg_socket_sendmsg(FAR struct socket *psock, { FAR const struct iovec *buf = msg->msg_iov; size_t len = msg->msg_iovlen; - FAR struct sockaddr *to = msg->msg_name; + FAR const struct sockaddr *to = msg->msg_name; socklen_t tolen = msg->msg_namelen; ssize_t ret; diff --git a/net/sixlowpan/sixlowpan_reassbuf.c b/net/sixlowpan/sixlowpan_reassbuf.c index 7ba412fcb40..2eaef67d9df 100644 --- a/net/sixlowpan/sixlowpan_reassbuf.c +++ b/net/sixlowpan/sixlowpan_reassbuf.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/net/sixlowpan/sixlowpan_tcpsend.c b/net/sixlowpan/sixlowpan_tcpsend.c index c024cfc935c..f359bc8d6b4 100644 --- a/net/sixlowpan/sixlowpan_tcpsend.c +++ b/net/sixlowpan/sixlowpan_tcpsend.c @@ -257,7 +257,8 @@ static int sixlowpan_tcp_header(FAR struct tcp_conn_s *conn, { /* Update the TCP received window based on I/O buffer availability */ - uint16_t recvwndo = tcp_get_recvwindow(dev, conn); + uint32_t rcvseq = tcp_getsequence(conn->rcvseq); + uint32_t recvwndo = tcp_get_recvwindow(dev, conn); /* Set the TCP Window */ @@ -266,7 +267,7 @@ static int sixlowpan_tcp_header(FAR struct tcp_conn_s *conn, /* Update the Receiver Window */ - conn->rcv_wnd = recvwndo; + conn->rcv_adv = rcvseq + recvwndo; } /* Calculate TCP checksum. */ diff --git a/net/socket/getsockopt.c b/net/socket/getsockopt.c index d14586fdeb7..5d46bd5fdfd 100644 --- a/net/socket/getsockopt.c +++ b/net/socket/getsockopt.c @@ -1,36 +1,20 @@ /**************************************************************************** * net/socket/getsockopt.c * - * Copyright (C) 2007-2009, 2012, 2014, 2017-2019 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -67,12 +51,12 @@ * the size of the option value is greater than 'value_len', the value * stored in the object pointed to by the 'value' argument will be silently * truncated. Otherwise, the length pointed to by the 'value_len' argument - * will be modified to indicate the actual length of the'value'. + * will be modified to indicate the actual length of the 'value'. * * The 'level' argument specifies the protocol level of the option. To * retrieve options at the socket level, specify the level argument as * SOL_SOCKET; to retrieve options at the TCP-protocol level, the level - * argument is SOL_CP. + * argument is SOL_TCP. * * See a complete list of values for the socket-level * 'option' argument. Protocol-specific options are are protocol specific @@ -142,7 +126,7 @@ static int psock_socketlevel_option(FAR struct socket *psock, int option, *value_len = sizeof(struct timeval); } - return OK; + return OK; } #ifdef CONFIG_NET_USRSOCK @@ -309,7 +293,7 @@ static int psock_socketlevel_option(FAR struct socket *psock, int option, * The 'level' argument specifies the protocol level of the option. To * retrieve options at the socket level, specify the level argument as * SOL_SOCKET; to retrieve options at the TCP-protocol level, the level - * argument is SOL_CP. + * argument is SOL_TCP. * * See a complete list of values for the socket-level * 'option' argument. Protocol-specific options are are protocol specific @@ -412,7 +396,7 @@ int psock_getsockopt(FAR struct socket *psock, int level, int option, * The 'level' argument specifies the protocol level of the option. To * retrieve options at the socket level, specify the level argument as * SOL_SOCKET; to retrieve options at the TCP-protocol level, the level - * argument is SOL_CP. + * argument is SOL_TCP. * * See a complete list of values for the socket-level * 'option' argument. Protocol-specific options are are protocol specific diff --git a/net/socket/setsockopt.c b/net/socket/setsockopt.c index fd22f315aac..6e424ca7df0 100644 --- a/net/socket/setsockopt.c +++ b/net/socket/setsockopt.c @@ -131,9 +131,71 @@ static int psock_socketlevel_option(FAR struct socket *psock, int option, { _SO_SETOPT(psock->s_options, option); } + + return OK; } - return OK; +#if CONFIG_NET_RECV_BUFSIZE > 0 + case SO_RCVBUF: /* Sets receive buffer size */ + { + int buffersize; + + /* Verify that option is the size of an 'int'. Should also check + * that 'value' is properly aligned for an 'int' + */ + + if (value_len != sizeof(int)) + { + return -EINVAL; + } + + /* Get the value. Is the option being set or cleared? */ + + buffersize = *(FAR int *)value; + + if (buffersize < 0 || buffersize > INT_MAX) + { + return -EINVAL; + } + + net_lock(); + +#if defined(CONFIG_NET_TCP) && !defined(CONFIG_NET_TCP_NO_STACK) + if (psock->s_type == SOCK_STREAM) + { + FAR struct tcp_conn_s *conn; + + conn = (FAR struct tcp_conn_s *)psock->s_conn; + + /* Save the receive buffer size */ + + conn->rcv_bufs = buffersize; + } + else +#endif +#if defined(CONFIG_NET_UDP) && !defined(CONFIG_NET_UDP_NO_STACK) + if (psock->s_type == SOCK_DGRAM) + { + FAR struct udp_conn_s *conn; + + conn = (FAR struct udp_conn_s *)psock->s_conn; + + /* Save the receive buffer size */ + + conn->rcvbufs = buffersize; + } + else +#endif + { + net_unlock(); + return -ENOPROTOOPT; + } + + net_unlock(); + + return OK; + } +#endif } #ifdef CONFIG_NET_USRSOCK @@ -274,7 +336,6 @@ static int psock_socketlevel_option(FAR struct socket *psock, int option, #endif /* The following are not yet implemented */ - case SO_RCVBUF: /* Sets receive buffer size */ case SO_RCVLOWAT: /* Sets the minimum number of bytes to input */ case SO_SNDBUF: /* Sets send buffer size */ case SO_SNDLOWAT: /* Sets the minimum number of bytes to output */ diff --git a/net/socket/socketpair.c b/net/socket/socketpair.c index 1f4b6bac347..8b1bf60adf6 100644 --- a/net/socket/socketpair.c +++ b/net/socket/socketpair.c @@ -39,7 +39,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: socketpair + * Name: psock_socketpair * * Description: * Create an unbound pair of connected sockets in a specified domain, of a @@ -110,7 +110,7 @@ errsock: * type - (see sys/socket.h) * protocol - (see sys/socket.h) * sv[2] - The user provided array in which to catch the pair - descriptors + * descriptors * ****************************************************************************/ @@ -118,8 +118,10 @@ int socketpair(int domain, int type, int protocol, int sv[2]) { FAR struct socket *psocks[2]; int oflags = O_RDWR; - int i = 0; int ret; + int i; + int j = 0; + int k; if (sv == NULL) { @@ -127,10 +129,10 @@ int socketpair(int domain, int type, int protocol, int sv[2]) goto errout; } - for (i = 0; i < 2; i++) + for (k = 0; k < 2; k++) { - psocks[i] = kmm_zalloc(sizeof(*psocks[i])); - if (psocks[i] == NULL) + psocks[k] = kmm_zalloc(sizeof(*psocks[k])); + if (psocks[k] == NULL) { ret = -ENOMEM; goto errout_with_alloc; @@ -150,12 +152,12 @@ int socketpair(int domain, int type, int protocol, int sv[2]) /* Allocate a socket descriptor */ - for (i = 0; i < 2; i++) + for (; j < 2; j++) { - sv[i] = sockfd_allocate(psocks[i], oflags); - if (sv[i] < 0) + sv[j] = sockfd_allocate(psocks[j], oflags); + if (sv[j] < 0) { - ret = sv[i]; + ret = sv[j]; goto errout_with_psock; } } @@ -163,14 +165,18 @@ int socketpair(int domain, int type, int protocol, int sv[2]) return OK; errout_with_psock: - while (i-- > 0) + for (i = 0; i < j; i++) { nx_close(sv[i]); } - i = 2; + for (i = j; i < k; i++) + { + psock_close(psocks[i]); + } + errout_with_alloc: - while (i-- > 0) + for (i = j; i < k; i++) { kmm_free(psocks[i]); } diff --git a/net/tcp/Kconfig b/net/tcp/Kconfig index df88824b8f1..e53ee05b3ab 100644 --- a/net/tcp/Kconfig +++ b/net/tcp/Kconfig @@ -106,6 +106,27 @@ config NET_TCP_FAST_RETRANSMIT_WATERMARK missing segment, without waiting for a retransmission timer to expire. +config NET_TCP_WINDOW_SCALE + bool "Enable TCP/IP Window Scale Option" + default n + ---help--- + RFC1323: + 2. TCP WINDOW SCALE OPTION + The window scale extension expands the definition of the TCP + window to 32 bits and then uses a scale factor to carry this 32- + bit value in the 16-bit Window field of the TCP header (SEG.WND in + RFC-793). + +if NET_TCP_WINDOW_SCALE + +config NET_TCP_WINDOW_SCALE_FACTOR + int "TCP/IP Window Scale Factor" + default 0 + ---help--- + This is the default value for window scale factor. + +endif # NET_TCP_WINDOW_SCALE + config NET_TCP_NOTIFIER bool "Support TCP notifications" default n diff --git a/net/tcp/tcp.h b/net/tcp/tcp.h index ca24a4652df..d2a9975050c 100644 --- a/net/tcp/tcp.h +++ b/net/tcp/tcp.h @@ -86,6 +86,20 @@ # endif #endif +/* 32-bit modular arithmetics for tcp sequence numbers */ + +#define TCP_SEQ_LT(a, b) ((int32_t)((a) - (b)) < 0) +#define TCP_SEQ_GT(a, b) TCP_SEQ_LT(b, a) +#define TCP_SEQ_LTE(a, b) (!TCP_SEQ_GT(a, b)) +#define TCP_SEQ_GTE(a, b) (!TCP_SEQ_LT(a, b)) + +#define TCP_SEQ_ADD(a, b) ((uint32_t)((a) + (b))) +#define TCP_SEQ_SUB(a, b) ((uint32_t)((a) - (b))) + +/* The TCP options flags */ + +#define TCP_WSCALE 0x01U /* Window Scale option enabled */ + /**************************************************************************** * Public Type Definitions ****************************************************************************/ @@ -177,14 +191,25 @@ struct tcp_conn_s uint16_t rport; /* The remoteTCP port, in network byte order */ uint16_t mss; /* Current maximum segment size for the * connection */ + uint32_t rcv_adv; /* The right edge of the recv window advertized */ +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + uint32_t snd_wnd; /* Sequence and acknowledgement numbers of last + * window update */ + uint8_t snd_scale; /* Sender window scale factor */ + uint8_t rcv_scale; /* Receiver windows scale factor */ +#else uint16_t snd_wnd; /* Sequence and acknowledgement numbers of last * window update */ - uint16_t rcv_wnd; /* Receiver window available */ +#endif +#if CONFIG_NET_RECV_BUFSIZE > 0 + int32_t rcv_bufs; /* Maximum amount of bytes queued in recv */ +#endif #ifdef CONFIG_NET_TCP_WRITE_BUFFERS uint32_t tx_unacked; /* Number bytes sent but not yet ACKed */ #else uint16_t tx_unacked; /* Number bytes sent but not yet ACKed */ #endif + uint16_t flags; /* Flags of TCP-specific options */ /* If the TCP socket is bound to a local address, then this is * a reference to the device that routes traffic on the corresponding @@ -195,19 +220,11 @@ struct tcp_conn_s /* Read-ahead buffering. * - * readahead - A singly linked list of type struct iob_qentry_s + * readahead - A singly linked list of type struct iob_s * where the TCP/IP read-ahead data is retained. */ - struct iob_queue_s readahead; /* Read-ahead buffering */ - - /* Pending-ahead buffering. - * - * pendingahead - A singly linked list of type struct iob_qentry_s - * where the TCP/IP pending-ahead data is retained. - */ - - struct iob_queue_s pendingahead; /* Pending-ahead buffering */ + struct iob_s *readahead; /* Read-ahead buffering */ #ifdef CONFIG_NET_TCP_WRITE_BUFFERS /* Write buffering @@ -266,12 +283,6 @@ struct tcp_conn_s FAR struct devif_callback_s *connevents; - /* Receiver callback to indicate that the data has been consumed and that - * an ACK should be send. - */ - - FAR struct devif_callback_s *rcv_ackcb; - /* accept() is called when the TCP logic has created a connection * * accept_private: This is private data that will be available to the @@ -961,6 +972,22 @@ ssize_t tcp_sendfile(FAR struct socket *psock, FAR struct file *infile, void tcp_reset(FAR struct net_driver_s *dev); +/**************************************************************************** + * Name: tcp_rx_mss + * + * Description: + * Return the MSS to advertize to the peer. + * + * Input Parameters: + * dev - The device driver structure + * + * Returned Value: + * The MSS value. + * + ****************************************************************************/ + +uint16_t tcp_rx_mss(FAR struct net_driver_s *dev); + /**************************************************************************** * Name: tcp_synack * @@ -1029,6 +1056,25 @@ void tcp_appsend(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, void tcp_rexmit(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, uint16_t result); +/**************************************************************************** + * Name: tcp_send_txnotify + * + * Description: + * Notify the appropriate device driver that we are have data ready to + * be send (TCP) + * + * Input Parameters: + * psock - Socket state structure + * conn - The TCP connection structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +void tcp_send_txnotify(FAR struct socket *psock, + FAR struct tcp_conn_s *conn); + /**************************************************************************** * Name: tcp_ipv4_input * @@ -1102,8 +1148,6 @@ uint16_t tcp_callback(FAR struct net_driver_s *dev, * buffer - A pointer to the buffer to be copied to the read-ahead * buffers * buflen - The number of bytes to copy to the read-ahead buffer. - * priv - Private data. - * producerid - id representing who is producing the IOB. * * Returned Value: * The number of bytes actually buffered is returned. This will be either @@ -1117,8 +1161,7 @@ uint16_t tcp_callback(FAR struct net_driver_s *dev, ****************************************************************************/ uint16_t tcp_datahandler(FAR struct tcp_conn_s *conn, FAR uint8_t *buffer, - uint16_t nbytes, FAR void *priv, - enum iob_user_e producerid); + uint16_t nbytes); /**************************************************************************** * Name: tcp_backlogcreate @@ -1432,9 +1475,25 @@ int tcp_getsockopt(FAR struct socket *psock, int option, * ****************************************************************************/ -uint16_t tcp_get_recvwindow(FAR struct net_driver_s *dev, +uint32_t tcp_get_recvwindow(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn); +/**************************************************************************** + * Name: tcp_should_send_recvwindow + * + * Description: + * Determine if we should advertize the new recv window to the peer. + * + * Input Parameters: + * conn - The TCP connection structure holding connection information. + * + * Returned Value: + * If we should send an update. + * + ****************************************************************************/ + +bool tcp_should_send_recvwindow(FAR struct tcp_conn_s *conn); + /**************************************************************************** * Name: psock_tcp_cansend * diff --git a/net/tcp/tcp_appsend.c b/net/tcp/tcp_appsend.c index cff0740ed9b..d2a05bd175d 100644 --- a/net/tcp/tcp_appsend.c +++ b/net/tcp/tcp_appsend.c @@ -89,10 +89,20 @@ void tcp_appsend(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, ninfo("result: %04x d_sndlen: %d conn->tx_unacked: %" PRId32 "\n", result, dev->d_sndlen, (uint32_t)conn->tx_unacked); + /* Need to update the recv window? */ + + if (tcp_should_send_recvwindow(conn)) + { + result |= TCP_SNDACK; +#ifdef CONFIG_NET_TCP_DELAYED_ACK + conn->rx_unackseg = 0; +#endif + } + #ifdef CONFIG_NET_TCP_DELAYED_ACK /* Did the caller request that an ACK be sent? */ - if ((result & TCP_SNDACK) != 0) + else if ((result & TCP_SNDACK) != 0) { /* Yes.. Handle delayed acknowledgments */ diff --git a/net/tcp/tcp_callback.c b/net/tcp/tcp_callback.c index 45c7acac1df..4bf6e43bb3c 100644 --- a/net/tcp/tcp_callback.c +++ b/net/tcp/tcp_callback.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -84,23 +85,30 @@ tcp_data_event(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, * partial packets will not be buffered. */ - recvlen = tcp_datahandler(conn, buffer, buflen, NULL, - IOBUSER_NET_TCP_READAHEAD); + recvlen = tcp_datahandler(conn, buffer, buflen); if (recvlen < buflen) { /* There is no handler to receive new data and there are no free * read-ahead buffers to retain the data -- drop the packet. */ - ninfo("Dropped %d bytes\n", dev->d_len); + ninfo("Dropped %d/%d bytes\n", buflen - recvlen, buflen); #ifdef CONFIG_NET_STATISTICS g_netstats.tcp.drop++; #endif - /* Clear the TCP_SNDACK bit so that no ACK will be sent */ + /* Clear the TCP_SNDACK bit so that no ACK will be sent. + * Clear the TCP_CLOSE because we effectively dropped + * the FIN as well. + * + * Revisit: It might make more sense to send a dup ack + * to give a hint to the peer. + */ - ret &= ~TCP_SNDACK; + ret &= ~(TCP_SNDACK | TCP_CLOSE); } + + net_incr32(conn->rcvseq, recvlen); } /* In any event, the new data has now been handled */ @@ -224,94 +232,95 @@ uint16_t tcp_callback(FAR struct net_driver_s *dev, ****************************************************************************/ uint16_t tcp_datahandler(FAR struct tcp_conn_s *conn, FAR uint8_t *buffer, - uint16_t buflen, FAR void *priv, - enum iob_user_e producerid) + uint16_t buflen) { - FAR struct iob_queue_s *queue; FAR struct iob_s *iob; - bool throttled = true; + uint16_t copied = 0; int ret; + unsigned int i; - /* Get the I/O buffer queue from iob producer id */ - - if (producerid == IOBUSER_NET_TCP_READAHEAD) - { - queue = &conn->readahead; - } - else if (producerid == IOBUSER_NET_TCP_PENDINGAHEAD) - { - queue = &conn->pendingahead; - } - else - { - nwarn("ERROR: Invalid iob produce id\n"); - return 0; - } - - /* Try to allocate on I/O buffer to start the chain without waiting (and - * throttling as necessary). If we would have to wait, then drop the - * packet. + /* Try to allocate I/O buffers and copy the data into them + * without waiting (and throttling as necessary). */ - iob = iob_tryalloc(throttled, producerid); - if (iob == NULL) + iob = conn->readahead; + for (i = 0; i < 2; i++) { -#if CONFIG_IOB_THROTTLE > 0 - if (IOB_QEMPTY(queue)) - { - /* Fallback out of the throttled entry */ + bool throttled = i == 0; /* try throttled=true first */ - throttled = false; - iob = iob_tryalloc(throttled, producerid); - } + if (!throttled) + { +#if CONFIG_IOB_THROTTLE > 0 + if (conn->readahead != NULL) + { + ninfo("Do not use throttled=false because of " + "non-empty readahead\n"); + break; + } +#else + break; #endif + } if (iob == NULL) { - nerr("ERROR: Failed to create new I/O buffer chain\n"); - return 0; + iob = iob_tryalloc(throttled, IOBUSER_NET_TCP_READAHEAD); + if (iob == NULL) + { + continue; + } + + iob->io_pktlen = 0; } + + if (iob != NULL) + { + uint32_t olen = iob->io_pktlen; + + ret = iob_trycopyin(iob, buffer + copied, buflen - copied, + olen, throttled, + IOBUSER_NET_TCP_READAHEAD); + copied += iob->io_pktlen - olen; + if (ret < 0) + { + /* On a failure, iob_copyin return a negated error value but + * does not free any I/O buffers. + */ + + continue; + } + } + + break; } - /* Copy the new appdata into the I/O buffer chain (without waiting) */ - - ret = iob_trycopyin(iob, buffer, buflen, 0, throttled, - producerid); - if (ret < 0) + DEBUGASSERT(conn->readahead == iob || conn->readahead == NULL); + if (iob == NULL) { - /* On a failure, iob_copyin return a negated error value but does - * not free any I/O buffers. - */ - - nerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret); - iob_free_chain(iob, producerid); + nerr("ERROR: Failed to create new I/O buffer chain\n"); + DEBUGASSERT(copied == 0); return 0; } - /* Add the new I/O buffer chain to the tail of the read-ahead queue (again - * without waiting). - */ - - ret = iob_tryadd_queue(iob, priv, queue); - if (ret < 0) + if (copied == 0) { - nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret); - iob_free_chain(iob, producerid); + nerr("ERROR: Failed to append new I/O buffer\n"); + DEBUGASSERT(conn->readahead == iob); return 0; } + conn->readahead = iob; + #ifdef CONFIG_NET_TCP_NOTIFIER /* Provide notification(s) that additional TCP read-ahead data is * available. */ - if (queue == &conn->readahead) - { - tcp_readahead_signal(conn); - } + + tcp_readahead_signal(conn); #endif - ninfo("Buffered %d bytes\n", buflen); - return buflen; + ninfo("Buffered %" PRIu16 " bytes\n", copied); + return copied; } #endif /* NET_TCP_HAVE_STACK */ diff --git a/net/tcp/tcp_close.c b/net/tcp/tcp_close.c index bfad4df5bdd..87c2743b77d 100644 --- a/net/tcp/tcp_close.c +++ b/net/tcp/tcp_close.c @@ -118,10 +118,16 @@ static uint16_t tcp_close_eventhandler(FAR struct net_driver_s *dev, goto end_wait; } -#ifdef CONFIG_NET_TCP_WRITE_BUFFERS - /* Check if all outstanding bytes have been ACKed */ + /* Check if all outstanding bytes have been ACKed. + * + * Note: in case of passive close, this ensures our FIN is acked. + */ - else if (conn->tx_unacked != 0 || !sq_empty(&conn->write_q)) + else if (conn->tx_unacked != 0 +#ifdef CONFIG_NET_TCP_WRITE_BUFFERS + || !sq_empty(&conn->write_q) +#endif /* CONFIG_NET_TCP_WRITE_BUFFERS */ + ) { /* No... we are still waiting for ACKs. Drop any received data, but * do not yet report TCP_CLOSE in the response. @@ -129,16 +135,47 @@ static uint16_t tcp_close_eventhandler(FAR struct net_driver_s *dev, dev->d_len = 0; flags &= ~TCP_NEWDATA; + ninfo("waiting for ack\n"); } - -#endif /* CONFIG_NET_TCP_WRITE_BUFFERS */ - else { + /* Note: the following state shouldn't reach here because + * + * FIN_WAIT_1, CLOSING, LAST_ACK + * should have tx_unacked != 0, already handled above + * + * CLOSED, TIME_WAIT + * a TCP_CLOSE callback should have already cleared this callback + * when transitioning to these states. + * + * FIN_WAIT_2 + * new data is dropped by tcp_input without invoking tcp_callback. + * timer is handled by tcp_timer without invoking tcp_callback. + * TCP_CLOSE is handled above. + */ + + DEBUGASSERT(conn->tcpstateflags == TCP_ESTABLISHED); + /* Drop data received in this state and make sure that TCP_CLOSE * is set in the response */ +#ifdef CONFIG_NET_TCP_WRITE_BUFFERS + FAR struct socket *psock = pstate->cl_psock; + + /* We don't need the send callback anymore. */ + + if (psock->s_sndcb != NULL) + { + psock->s_sndcb->flags = 0; + psock->s_sndcb->event = NULL; + + /* The callback will be freed by tcp_free. */ + + psock->s_sndcb = NULL; + } +#endif + dev->d_len = 0; flags = (flags & ~TCP_NEWDATA) | TCP_CLOSE; } @@ -262,31 +299,16 @@ static inline int tcp_close_disconnect(FAR struct socket *psock) } #endif -#ifdef CONFIG_NET_TCP_WRITE_BUFFERS - /* If we have a semi-permanent write buffer callback in place, then - * is needs to be be nullified. + /* TCP_ESTABLISHED + * We need to initiate an active close and wait for its completion. * - * Commit f1ef2c6cdeb032eaa1833cc534a63b50c5058270: - * "When a socket is closed, it should make sure that any pending write - * data is sent before the FIN is sent. It already would wait for all - * sent data to be acked, however it would discard any pending write - * data that had not been sent at least once. - * - * "This change adds a check for pending write data in addition to unacked - * data. However, to be able to actually send any new data, the send - * callback must be left. The callback should be freed later when the - * socket is actually destroyed." - * - * REVISIT: Where and how exactly is s_sndcb ever freed? Is there a - * memory leak here? + * TCP_LAST_ACK + * We still need to wait for the ACK for our FIN, possibly + * retransmitting the FIN, before disposing the connection. */ - psock->s_sndcb = NULL; -#endif - - /* Check for the case where the host beat us and disconnected first */ - - if (conn->tcpstateflags == TCP_ESTABLISHED && + if ((conn->tcpstateflags == TCP_ESTABLISHED || + conn->tcpstateflags == TCP_LAST_ACK) && (state.cl_cb = tcp_callback_alloc(conn)) != NULL) { /* Set up to receive TCP data event callbacks */ diff --git a/net/tcp/tcp_conn.c b/net/tcp/tcp_conn.c index a45e035171f..f5ef61d91a0 100644 --- a/net/tcp/tcp_conn.c +++ b/net/tcp/tcp_conn.c @@ -672,6 +672,9 @@ FAR struct tcp_conn_s *tcp_alloc(uint8_t domain) conn->keepidle = 2 * DSEC_PER_HOUR; conn->keepintvl = 2 * DSEC_PER_SEC; conn->keepcnt = 3; +#endif +#if CONFIG_NET_RECV_BUFSIZE > 0 + conn->rcv_bufs = CONFIG_NET_RECV_BUFSIZE; #endif } @@ -703,8 +706,8 @@ void tcp_free(FAR struct tcp_conn_s *conn) DEBUGASSERT(conn->crefs == 0); net_lock(); - /* Free remaining callbacks, actually there should be only the close - * callback left. + /* Free remaining callbacks, actually there should be only the send + * callback for CONFIG_NET_TCP_WRITE_BUFFERS is left. */ for (cb = conn->list; cb; cb = next) @@ -726,11 +729,8 @@ void tcp_free(FAR struct tcp_conn_s *conn) /* Release any read-ahead buffers attached to the connection */ - iob_destroy_queue(&conn->readahead, IOBUSER_NET_TCP_READAHEAD); - - /* Release any pending-ahead buffers attached to the connection */ - - iob_destroy_queue(&conn->pendingahead, IOBUSER_NET_TCP_PENDINGAHEAD); + iob_free_chain(conn->readahead, IOBUSER_NET_TCP_READAHEAD); + conn->readahead = NULL; #ifdef CONFIG_NET_TCP_WRITE_BUFFERS /* Release any write buffers attached to the connection */ @@ -970,14 +970,11 @@ FAR struct tcp_conn_s *tcp_alloc_accept(FAR struct net_driver_s *dev, /* rcvseq should be the seqno from the incoming packet + 1. */ memcpy(conn->rcvseq, tcp->seqno, 4); + conn->rcv_adv = tcp_getsequence(conn->rcvseq); /* Initialize the list of TCP read-ahead buffers */ - IOB_QINIT(&conn->readahead); - - /* Initialize the list of TCP pending-ahead buffers */ - - IOB_QINIT(&conn->pendingahead); + conn->readahead = NULL; #ifdef CONFIG_NET_TCP_WRITE_BUFFERS /* Initialize the write buffer lists */ @@ -1251,11 +1248,7 @@ int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) /* Initialize the list of TCP read-ahead buffers */ - IOB_QINIT(&conn->readahead); - - /* Initialize the list of TCP pending-ahead buffers */ - - IOB_QINIT(&conn->pendingahead); + conn->readahead = NULL; #ifdef CONFIG_NET_TCP_WRITE_BUFFERS /* Initialize the TCP write buffer lists */ diff --git a/net/tcp/tcp_getsockopt.c b/net/tcp/tcp_getsockopt.c index 43a92345ca7..b864b19d680 100644 --- a/net/tcp/tcp_getsockopt.c +++ b/net/tcp/tcp_getsockopt.c @@ -156,65 +156,51 @@ int tcp_getsockopt(FAR struct socket *psock, int option, break; case TCP_KEEPIDLE: /* Start keepalives after this IDLE period */ - if (*value_len < sizeof(struct timeval)) - { - /* REVISIT: POSIX says that we should truncate the value if it - * is larger than value_len. That just doesn't make sense - * to me in this case. - */ - - ret = -EINVAL; - } - else - { - FAR struct timeval *tv = (FAR struct timeval *)value; - - if (tv == NULL) - { - ret = -EINVAL; - } - else - { - /* Convert the KeepIdle time from deciseconds to struct - * timeval. - */ - - net_dsec2timeval(conn->keepidle, tv); - *value_len = sizeof(struct timeval); - ret = OK; - } - } - break; - case TCP_KEEPINTVL: /* Interval between keepalives */ - if (*value_len < sizeof(struct timeval)) - { - /* REVISIT: POSIX says that we should truncate the value if it - * is larger than value_len. That just doesn't make sense - * to me in this case. - */ + { + int dsecs; - ret = -EINVAL; - } - else - { - FAR struct timeval *tv = (FAR struct timeval *)value; + if (option == TCP_KEEPIDLE) + { + dsecs = conn->keepidle; + } + else + { + dsecs = conn->keepintvl; + } - if (tv == NULL) - { - ret = -EINVAL; - } - else - { - /* Convert the KeepIdle time from deciseconds to struct - * timeval. - */ + if (value == NULL) + { + ret = -EINVAL; + } + else if (*value_len == sizeof(struct timeval)) + { + FAR struct timeval *tv = (FAR struct timeval *)value; - net_dsec2timeval(conn->keepintvl, tv); - *value_len = sizeof(struct timeval); - ret = OK; - } - } + /* Convert the KeepIdle time from deciseconds to struct + * timeval. + */ + + net_dsec2timeval(dsecs, tv); + *value_len = sizeof(struct timeval); + ret = OK; + } + else if (*value_len == sizeof(int)) + { + FAR int *pdsecs = (FAR int *)value; + *pdsecs = dsecs; + ret = OK; + } + else + { + /* REVISIT: POSIX says that we should truncate the value if it + * is larger than value_len. That just doesn't make sense + * to me in this case. + */ + + ret = -EINVAL; + } + } break; case TCP_KEEPCNT: /* Number of keepalives before death */ diff --git a/net/tcp/tcp_input.c b/net/tcp/tcp_input.c index 860459be414..96eeb5ac900 100644 --- a/net/tcp/tcp_input.c +++ b/net/tcp/tcp_input.c @@ -59,8 +59,6 @@ #include #include -#include - #include "devif/devif.h" #include "utils/utils.h" #include "tcp/tcp.h" @@ -76,55 +74,120 @@ ****************************************************************************/ /**************************************************************************** - * Name: tcp_input_cache + * Name: tcp_trim_head + * + * Description: + * Trim the head of the TCP segment. + * + * Input Parameters: + * dev - The device driver structure containing the received TCP + * packet. + * tcp - The TCP header. + * trimlen - The length to trim in bytes. + * + * Returned Value: + * True if nothing was left. + * + * Assumptions: + * The network is locked. + * ****************************************************************************/ -static void tcp_input_cache(FAR struct net_driver_s *dev, - FAR struct tcp_conn_s *conn, unsigned int iplen) +static bool tcp_trim_head(FAR struct net_driver_s *dev, + FAR struct tcp_hdr_s *tcp, + uint32_t trimlen) { - uint8_t header[iplen + NET_LL_HDRLEN(dev) + sizeof(struct tcp_hdr_s)]; - FAR struct iob_qentry_s *qentry; - FAR struct tcp_hdr_s *incoming; - FAR struct tcp_hdr_s *cached; - uint32_t ackseq; - uint32_t rcvseq; + uint32_t seq = tcp_getsequence(tcp->seqno); + uint16_t urg_ptr = (tcp->urgp[0] << 8) | tcp->urgp[1]; + uint32_t urg_trimlen = 0; + uint8_t th_flags = tcp->flags; - if (dev->d_len < sizeof(header)) + DEBUGASSERT(trimlen > 0); + ninfo("Dropping %" PRIu32 " bytes: " + "seq=%" PRIu32 ", " + "tcp flags=%" PRIx8 ", " + "d_len=%" PRIu16 ", " + "urg_ptr=%" PRIu16 "\n", + trimlen, + seq, + th_flags, + dev->d_len, + urg_ptr); + + if ((th_flags & TCP_SYN) != 0) { - return; + ninfo("Dropping SYN\n"); + seq = TCP_SEQ_ADD(seq, 1); + urg_trimlen++; + trimlen--; + th_flags &= ~TCP_SYN; } - /* Get a pointer to the TCP header. The TCP header lies just after the - * the link layer header and the IP header. - */ - - incoming = (FAR struct tcp_hdr_s *)&dev->d_buf[iplen + NET_LL_HDRLEN(dev)]; - - /* Get the sequence number of that has just been acknowledged by this - * incoming packet. - */ - - ackseq = tcp_getsequence(incoming->seqno); - rcvseq = tcp_getsequence(conn->rcvseq); - if (ackseq < rcvseq) + if (trimlen > 0) { - return; - } + uint32_t len = trimlen; - for (qentry = conn->pendingahead.qh_head; - qentry != NULL; qentry = qentry->qe_flink) - { - (void)iob_copyout(header, qentry->qe_head, sizeof(header), 0); - cached = (FAR struct tcp_hdr_s *)&header[iplen + NET_LL_HDRLEN(dev)]; - rcvseq = tcp_getsequence(cached->seqno); - if (rcvseq == ackseq) + if (len > dev->d_len) { - return; + len = dev->d_len; + } + + ninfo("Dropping %" PRIu32 " bytes app data\n", len); + seq = TCP_SEQ_ADD(seq, len); + urg_trimlen += len; + dev->d_appdata += len; + dev->d_len -= len; + trimlen -= len; + } + + if (trimlen > 0) + { + if ((th_flags & TCP_FIN) != 0) + { + ninfo("Dropping FIN\n"); + seq = TCP_SEQ_ADD(seq, 1); + urg_trimlen++; + trimlen--; + th_flags &= ~TCP_FIN; } } - tcp_datahandler(conn, dev->d_buf, dev->d_len, - (void *)iplen, IOBUSER_NET_TCP_PENDINGAHEAD); + /* Update the header */ + + if ((th_flags & TCP_URG) != 0) + { + /* Adjust URG pointer */ + + if (urg_trimlen >= urg_ptr) + { + th_flags &= ~TCP_URG; + urg_ptr = 0; + } + else + { + urg_ptr -= urg_trimlen; + } + + ninfo("Adjusting URG pointer by %" PRIu32 ", " + "new urg_ptr=%" PRIu16 "\n", + urg_trimlen, urg_ptr); + + tcp->urgp[0] = (uint8_t)(urg_ptr >> 8); + tcp->urgp[1] = (uint8_t)urg_ptr; + } + + tcp->flags = th_flags; + tcp_setsequence(tcp->seqno, seq); + + if ((th_flags & (TCP_SYN | TCP_FIN)) == 0 && dev->d_len == 0) + { + ninfo("Dropped the entire segment\n"); + return true; + } + + DEBUGASSERT(trimlen == 0); + ninfo("Dropped the segment partially\n"); + return false; } /**************************************************************************** @@ -147,7 +210,7 @@ static void tcp_input_cache(FAR struct net_driver_s *dev, ****************************************************************************/ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain, - unsigned int iplen, FAR struct tcp_conn_s **active) + unsigned int iplen) { FAR struct tcp_hdr_s *tcp; FAR struct tcp_conn_s *conn = NULL; @@ -205,11 +268,6 @@ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain, conn = tcp_active(dev, tcp); if (conn) { - if (active) - { - *active = conn; - } - /* We found an active connection.. Check for the subsequent SYN * arriving in TCP_SYN_RCVD state after the SYNACK packet was * lost. To avoid other issues, reset any active connection @@ -259,11 +317,6 @@ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain, conn = tcp_alloc_accept(dev, tcp); if (conn) { - if (active) - { - *active = conn; - } - /* The connection structure was successfully allocated and has * been initialized in the TCP_SYN_RECVD state. The expected * sequence of events is then the rest of the 3-way handshake: @@ -302,7 +355,7 @@ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain, goto drop; } - net_incr32(conn->rcvseq, 1); + net_incr32(conn->rcvseq, 1); /* ack SYN */ /* Parse the TCP MSS option, if present. */ @@ -322,6 +375,7 @@ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain, /* NOP option. */ ++i; + continue; } else if (opt == TCP_OPT_MSS && dev->d_buf[hdrlen + 1 + i] == TCP_OPT_MSS_LEN) @@ -333,11 +387,16 @@ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain, tmp16 = ((uint16_t)dev->d_buf[hdrlen + 2 + i] << 8) | (uint16_t)dev->d_buf[hdrlen + 3 + i]; conn->mss = tmp16 > tcp_mss ? tcp_mss : tmp16; - - /* And we are done processing options. */ - - break; } +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + else if (opt == TCP_OPT_WS && + dev->d_buf[hdrlen + 1 + i] == TCP_OPT_WS_LEN) + { + conn->snd_scale = dev->d_buf[hdrlen + 2 + i]; + conn->rcv_scale = CONFIG_NET_TCP_WINDOW_SCALE_FACTOR; + conn->flags |= TCP_WSCALE; + } +#endif else { /* All other options have a length field, so that we @@ -352,9 +411,9 @@ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain, break; } - - i += dev->d_buf[hdrlen + 1 + i]; } + + i += dev->d_buf[hdrlen + 1 + i]; } } @@ -390,7 +449,12 @@ found: /* Update the connection's window size */ - conn->snd_wnd = ((uint16_t)tcp->wnd[0] << 8) + (uint16_t)tcp->wnd[1]; +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + conn->snd_wnd = (((uint32_t)tcp->wnd[0] << 8) + (uint32_t)tcp->wnd[1]) << + conn->snd_scale; +#else + conn->snd_wnd = (((uint16_t)tcp->wnd[0] << 8) + (uint16_t)tcp->wnd[1]); +#endif flags = 0; @@ -463,46 +527,6 @@ found: dev->d_len -= (len + iplen); -#ifdef CONFIG_NET_TCP_KEEPALIVE - /* Check for a to KeepAlive probes. These packets have these properties: - * - * - TCP_ACK flag is set. SYN/FIN/RST never appear in a Keepalive probe. - * - Sequence number is the sequence number of previously ACKed data, - * i.e., the expected sequence number minus one. - * - The data payload is one or two bytes. - * - * We would expect a KeepAlive only in the ESTABLISHED state and only after - * some time has elapsed with no network activity. If there is un-ACKed - * data, then we will let the normal TCP re-transmission logic handle that - * case. - */ - - if ((tcp->flags & TCP_ACK) != 0 && - (tcp->flags & (TCP_SYN | TCP_FIN | TCP_RST)) == 0 && - (conn->tcpstateflags & TCP_STATE_MASK) == TCP_ESTABLISHED && - (dev->d_len == 0 || dev->d_len == 1) && - conn->tx_unacked <= 0) - { - uint32_t ackseq; - uint32_t rcvseq; - - /* Get the sequence number of that has just been acknowledged by this - * incoming packet. - */ - - ackseq = tcp_getsequence(tcp->seqno); - rcvseq = tcp_getsequence(conn->rcvseq); - - if (ackseq < rcvseq) - { - /* Send a "normal" acknowledgment of the KeepAlive probe */ - - tcp_send(dev, conn, TCP_ACK, tcpiplen); - return; - } - } -#endif - /* Check if the sequence number of the incoming packet is what we are * expecting next. If not, we send out an ACK with the correct numbers * in, unless we are in the SYN_RCVD state and receive a SYN, in which @@ -514,17 +538,38 @@ found: (((conn->tcpstateflags & TCP_STATE_MASK) == TCP_SYN_RCVD) && ((tcp->flags & TCP_CTL) == TCP_SYN)))) { - if ((dev->d_len > 0 || ((tcp->flags & (TCP_SYN | TCP_FIN)) != 0)) && - memcmp(tcp->seqno, conn->rcvseq, 4) != 0) + uint32_t seq; + uint32_t rcvseq; + + seq = tcp_getsequence(tcp->seqno); + rcvseq = tcp_getsequence(conn->rcvseq); + + if (seq != rcvseq) { - /* Restore the data length */ + /* Trim the head of the segment */ - dev->d_len += hdrlen; - tcp_input_cache(dev, conn, iplen); - dev->d_len -= hdrlen; + if (TCP_SEQ_LT(seq, rcvseq)) + { + uint32_t trimlen = TCP_SEQ_SUB(rcvseq, seq); - tcp_send(dev, conn, TCP_ACK, tcpiplen); - return; + if (tcp_trim_head(dev, tcp, trimlen)) + { + /* The segment was completely out of the window. + * E.g. a retransmit which was not necessary. + * E.g. a keep-alive segment. + */ + + tcp_send(dev, conn, TCP_ACK, tcpiplen); + return; + } + } + else + { + /* We never queue out-of-order segments. */ + + tcp_send(dev, conn, TCP_ACK, tcpiplen); + return; + } } } @@ -562,7 +607,7 @@ found: * new sequence number. */ - if (ackseq <= unackseq) + if (TCP_SEQ_LTE(ackseq, unackseq)) { /* Calculate the new number of outstanding, unacknowledged bytes */ @@ -692,7 +737,6 @@ found: if (dev->d_len > 0) { flags |= TCP_NEWDATA; - net_incr32(conn->rcvseq, dev->d_len); } dev->d_sndlen = 0; @@ -739,6 +783,7 @@ found: /* NOP option. */ ++i; + continue; } else if (opt == TCP_OPT_MSS && dev->d_buf[hdrlen + 1 + i] == TCP_OPT_MSS_LEN) @@ -751,11 +796,16 @@ found: (dev->d_buf[hdrlen + 2 + i] << 8) | dev->d_buf[hdrlen + 3 + i]; conn->mss = tmp16 > tcp_mss ? tcp_mss : tmp16; - - /* And we are done processing options. */ - - break; } +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + else if (opt == TCP_OPT_WS && + dev->d_buf[hdrlen + 1 + i] == TCP_OPT_WS_LEN) + { + conn->snd_scale = dev->d_buf[hdrlen + 2 + i]; + conn->rcv_scale = CONFIG_NET_TCP_WINDOW_SCALE_FACTOR; + conn->flags |= TCP_WSCALE; + } +#endif else { /* All other options have a length field, so that we @@ -770,16 +820,17 @@ found: break; } - - i += dev->d_buf[hdrlen + 1 + i]; } + + i += dev->d_buf[hdrlen + 1 + i]; } } conn->tcpstateflags = TCP_ESTABLISHED; memcpy(conn->rcvseq, tcp->seqno, 4); + conn->rcv_adv = tcp_getsequence(conn->rcvseq); - net_incr32(conn->rcvseq, 1); + net_incr32(conn->rcvseq, 1); /* ack SYN */ conn->tx_unacked = 0; #ifdef CONFIG_NET_TCP_WRITE_BUFFERS @@ -847,7 +898,6 @@ found: * has been closed. */ - net_incr32(conn->rcvseq, dev->d_len + 1); flags |= TCP_CLOSE; if (dev->d_len > 0) @@ -855,17 +905,26 @@ found: flags |= TCP_NEWDATA; } - tcp_callback(dev, conn, flags); + result = tcp_callback(dev, conn, flags); - conn->tcpstateflags = TCP_LAST_ACK; - conn->tx_unacked = 1; - conn->nrtx = 0; + if ((result & TCP_CLOSE) != 0) + { + conn->tcpstateflags = TCP_LAST_ACK; + conn->tx_unacked = 1; + conn->nrtx = 0; + net_incr32(conn->rcvseq, 1); /* ack FIN */ #ifdef CONFIG_NET_TCP_WRITE_BUFFERS - conn->sndseq_max = tcp_getsequence(conn->sndseq) + 1; + conn->sndseq_max = tcp_getsequence(conn->sndseq) + 1; #endif - ninfo("TCP state: TCP_LAST_ACK\n"); + ninfo("TCP state: TCP_LAST_ACK\n"); + tcp_send(dev, conn, TCP_FIN | TCP_ACK, tcpiplen); + } + else + { + ninfo("TCP: Dropped a FIN\n"); + tcp_appsend(dev, conn, result); + } - tcp_send(dev, conn, TCP_FIN | TCP_ACK, tcpiplen); return; } @@ -987,31 +1046,12 @@ found: if ((flags & (TCP_NEWDATA | TCP_ACKDATA)) != 0) { - /* Clear sndlen and remember the size in d_len. The application - * may modify d_len and we will need this value later when we - * update the sequence number. - */ - dev->d_sndlen = 0; - len = dev->d_len; /* Provide the packet to the application */ result = tcp_callback(dev, conn, flags); - /* If the application successfully handled the incoming data, - * then TCP_SNDACK will be set in the result. In this case, - * we need to update the sequence number. The ACK will be - * send by tcp_appsend(). - */ - - if ((result & TCP_SNDACK) != 0) - { - /* Update the sequence number using the saved length */ - - net_incr32(conn->rcvseq, len); - } - /* Send the response, ACKing the data or not, as appropriate */ tcp_appsend(dev, conn, result); @@ -1059,7 +1099,7 @@ found: ninfo("TCP state: TCP_CLOSING\n"); } - net_incr32(conn->rcvseq, 1); + net_incr32(conn->rcvseq, 1); /* ack FIN */ tcp_callback(dev, conn, TCP_CLOSE); tcp_send(dev, conn, TCP_ACK, tcpiplen); return; @@ -1091,7 +1131,7 @@ found: conn->timer = 0; ninfo("TCP state: TCP_TIME_WAIT\n"); - net_incr32(conn->rcvseq, 1); + net_incr32(conn->rcvseq, 1); /* ack FIN */ tcp_callback(dev, conn, TCP_CLOSE); tcp_send(dev, conn, TCP_ACK, tcpiplen); return; @@ -1125,114 +1165,6 @@ drop: dev->d_len = 0; } -/**************************************************************************** - * Name: tcp_process_cache - ****************************************************************************/ - -static void tcp_process_cache(FAR struct net_driver_s *dev, uint8_t domain, - FAR struct tcp_conn_s *conn) -{ - FAR struct iob_qentry_s *qentry; - FAR uint8_t *reassemble = NULL; - FAR struct iob_qentry_s *next; - FAR struct tcp_hdr_s tcp; - FAR struct iob_s *iob; - FAR uint8_t *d_buf; - unsigned int iplen; - uint32_t ackseq; - uint32_t rcvseq; - uint16_t d_len; - - if (!conn || !iob_peek_queue(&conn->pendingahead)) - { - return; - } - - d_len = dev->d_len; - d_buf = dev->d_buf; - - for (qentry = conn->pendingahead.qh_head; qentry != NULL; qentry = next) - { - next = qentry->qe_flink; - iob = qentry->qe_head; - iplen = (intptr_t)qentry->qe_priv; - - (void)iob_copyout((FAR uint8_t *)&tcp, iob, sizeof(tcp), - NET_LL_HDRLEN(dev) + iplen); - - rcvseq = tcp_getsequence(conn->rcvseq); - ackseq = tcp_getsequence(tcp.seqno); - - if (rcvseq == ackseq) - { - if (iob->io_pktlen > iob->io_len) - { - if (reassemble == NULL) - { - reassemble = kmm_malloc(CONFIG_NET_ETH_PKTSIZE); - if (reassemble == NULL) - { - iob_destroy_queue(&conn->pendingahead, - IOBUSER_NET_TCP_PENDINGAHEAD); - break; - } - } - - (void)iob_copyout(reassemble, iob, iob->io_pktlen, 0); - - dev->d_buf = reassemble; - } - else - { - dev->d_buf = IOB_DATA(iob); - } - - dev->d_len = iob->io_pktlen - NET_LL_HDRLEN(dev); - - if (IFF_IS_IPv4(dev->d_flags)) - { -#ifdef CONFIG_NET_IPv4 - tcp_ipv4_select(dev); -#endif - } - else - { -#ifdef CONFIG_NET_IPv6 - tcp_ipv6_select(dev); -#endif - } - - tcp_input(dev, domain, iplen, NULL); - - if (dev->d_len > 0) - { - d_len = dev->d_len; - memcpy(d_buf, dev->d_buf, d_len); - } - - iob_free_queue(iob, &conn->pendingahead, - IOBUSER_NET_TCP_PENDINGAHEAD); - - /* Re-traverse the pending list */ - - qentry = conn->pendingahead.qh_head; - } - else if (ackseq < rcvseq) - { - iob_free_queue(iob, &conn->pendingahead, - IOBUSER_NET_TCP_PENDINGAHEAD); - } - } - - dev->d_len = d_len; - dev->d_buf = d_buf; - - if (reassemble) - { - kmm_free(reassemble); - } -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -1258,7 +1190,6 @@ static void tcp_process_cache(FAR struct net_driver_s *dev, uint8_t domain, void tcp_ipv4_input(FAR struct net_driver_s *dev) { FAR struct ipv4_hdr_s *ipv4 = IPv4BUF; - FAR struct tcp_conn_s *conn = NULL; uint16_t iphdrlen; /* Configure to receive an TCP IPv4 packet */ @@ -1271,14 +1202,7 @@ void tcp_ipv4_input(FAR struct net_driver_s *dev) /* Then process in the TCP IPv4 input */ - tcp_input(dev, PF_INET, iphdrlen, &conn); - - /* Try the pending cache here */ - - if (conn) - { - tcp_process_cache(dev, PF_INET, conn); - } + tcp_input(dev, PF_INET, iphdrlen); } #endif @@ -1305,22 +1229,13 @@ void tcp_ipv4_input(FAR struct net_driver_s *dev) #ifdef CONFIG_NET_IPv6 void tcp_ipv6_input(FAR struct net_driver_s *dev, unsigned int iplen) { - FAR struct tcp_conn_s *conn = NULL; - /* Configure to receive an TCP IPv6 packet */ tcp_ipv6_select(dev); /* Then process in the TCP IPv6 input */ - tcp_input(dev, PF_INET6, iplen, &conn); - - /* Try the pending cache here */ - - if (conn) - { - tcp_process_cache(dev, PF_INET6, conn); - } + tcp_input(dev, PF_INET6, iplen); } #endif diff --git a/net/tcp/tcp_ioctl.c b/net/tcp/tcp_ioctl.c index 00e56972fb6..af5bb985e04 100644 --- a/net/tcp/tcp_ioctl.c +++ b/net/tcp/tcp_ioctl.c @@ -33,6 +33,7 @@ #include #include +#include #include "tcp/tcp.h" @@ -59,16 +60,26 @@ int tcp_ioctl(FAR struct tcp_conn_s *conn, { int ret = OK; + net_lock(); + switch (cmd) { case FIONREAD: - *(FAR int *)((uintptr_t)arg) = - iob_get_queue_size(&conn->readahead); + if (conn->readahead != NULL) + { + *(FAR int *)((uintptr_t)arg) = conn->readahead->io_pktlen; + } + else + { + *(FAR int *)((uintptr_t)arg) = 0; + } break; default: ret = -ENOTTY; break; } + net_unlock(); + return ret; } diff --git a/net/tcp/tcp_monitor.c b/net/tcp/tcp_monitor.c index cadfa147f21..ab550188b20 100644 --- a/net/tcp/tcp_monitor.c +++ b/net/tcp/tcp_monitor.c @@ -346,13 +346,15 @@ void tcp_close_monitor(FAR struct socket *psock) /* Find and free the the connection event callback */ net_lock(); - - for (cb = conn->connevents; cb != NULL; cb = cb->nxtconn) + for (cb = conn->connevents; + cb != NULL && cb->priv != (FAR void *)psock; + cb = cb->nxtconn) { - if (cb->priv == (FAR void *)psock) - { - devif_conn_callback_free(conn->dev, cb, &conn->connevents); - } + } + + if (cb != NULL) + { + devif_conn_callback_free(conn->dev, cb, &conn->connevents); } /* Make sure that this socket is explicitly marked as closed */ diff --git a/net/tcp/tcp_netpoll.c b/net/tcp/tcp_netpoll.c index 03ffe0feb18..8f28da48a48 100644 --- a/net/tcp/tcp_netpoll.c +++ b/net/tcp/tcp_netpoll.c @@ -229,7 +229,7 @@ int tcp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) /* Check for read data or backlogged connection availability now */ - if (!IOB_QEMPTY(&conn->readahead) || tcp_backlogavailable(conn)) + if (conn->readahead != NULL || tcp_backlogavailable(conn)) { /* Normal data may be read without blocking. */ diff --git a/net/tcp/tcp_notifier.c b/net/tcp/tcp_notifier.c index 6a9adfb099a..00b10a4de11 100644 --- a/net/tcp/tcp_notifier.c +++ b/net/tcp/tcp_notifier.c @@ -78,7 +78,7 @@ int tcp_readahead_notifier_setup(worker_t worker, * setting up the notification. */ - if (conn->readahead.qh_head != NULL) + if (conn->readahead != NULL) { return 0; } diff --git a/net/tcp/tcp_recvfrom.c b/net/tcp/tcp_recvfrom.c index 921e10afe4c..52997a2996e 100644 --- a/net/tcp/tcp_recvfrom.c +++ b/net/tcp/tcp_recvfrom.c @@ -166,9 +166,13 @@ static size_t tcp_recvfrom_newdata(FAR struct net_driver_s *dev, * ****************************************************************************/ -static inline void tcp_newdata(FAR struct net_driver_s *dev, - FAR struct tcp_recvfrom_s *pstate) +static inline uint16_t tcp_newdata(FAR struct net_driver_s *dev, + FAR struct tcp_recvfrom_s *pstate, + uint16_t flags) { + FAR struct tcp_conn_s *conn = (FAR struct tcp_conn_s *) + pstate->ir_sock->s_conn; + /* Take as much data from the packet as we can */ size_t recvlen = tcp_recvfrom_newdata(dev, pstate); @@ -179,41 +183,39 @@ static inline void tcp_newdata(FAR struct net_driver_s *dev, if (recvlen < dev->d_len) { - FAR struct tcp_conn_s *conn = - (FAR struct tcp_conn_s *)pstate->ir_sock->s_conn; FAR uint8_t *buffer = (FAR uint8_t *)dev->d_appdata + recvlen; uint16_t buflen = dev->d_len - recvlen; -#ifdef CONFIG_DEBUG_NET uint16_t nsaved; - nsaved = tcp_datahandler(conn, buffer, buflen, NULL, - IOBUSER_NET_TCP_READAHEAD); -#else - tcp_datahandler(conn, buffer, buflen, NULL, IOBUSER_NET_TCP_READAHEAD); -#endif - - /* There are complicated buffering issues that are not addressed fully - * here. For example, what if up_datahandler() cannot buffer the - * remainder of the packet? In that case, the data will be dropped but - * still ACKed. Therefore it would not be resent. - * - * This is probably not an issue here because we only get here if the - * read-ahead buffers are empty and there would have to be something - * serioulsy wrong with the configuration not to be able to buffer a - * partial packet in this context. - */ - -#ifdef CONFIG_DEBUG_NET + nsaved = tcp_datahandler(conn, buffer, buflen); if (nsaved < buflen) { - nerr("ERROR: packet data not saved (%d bytes)\n", buflen - nsaved); + nwarn("WARNING: packet data not fully saved " + "(%d/%u/%zu/%u bytes)\n", + buflen - nsaved, + (unsigned int)nsaved, + recvlen, + (unsigned int)dev->d_len); } -#endif + + recvlen += nsaved; } + if (recvlen < dev->d_len) + { + /* Clear the TCP_CLOSE because we effectively dropped the FIN as well. + */ + + flags &= ~TCP_CLOSE; + } + + net_incr32(conn->rcvseq, recvlen); + /* Indicate no data in the buffer */ dev->d_len = 0; + + return flags; } /**************************************************************************** @@ -244,7 +246,7 @@ static inline void tcp_readahead(struct tcp_recvfrom_s *pstate) * buffer. */ - while ((iob = iob_peek_queue(&conn->readahead)) != NULL && + while ((iob = conn->readahead) != NULL && pstate->ir_buflen > 0) { DEBUGASSERT(iob->io_pktlen > 0); @@ -268,29 +270,19 @@ static inline void tcp_readahead(struct tcp_recvfrom_s *pstate) if (recvlen >= iob->io_pktlen) { - FAR struct iob_s *tmp; - - /* Remove the I/O buffer chain from the head of the read-ahead - * buffer queue. - */ - - tmp = iob_remove_queue(&conn->readahead); - DEBUGASSERT(tmp == iob); - UNUSED(tmp); - - /* And free the I/O buffer chain */ + /* Free free the I/O buffer chain */ iob_free_chain(iob, IOBUSER_NET_TCP_READAHEAD); + conn->readahead = NULL; } else { /* The bytes that we have received from the head of the I/O - * buffer chain (probably changing the head of the I/O - * buffer queue). + * buffer chain. */ - iob_trimhead_queue(&conn->readahead, recvlen, - IOBUSER_NET_TCP_READAHEAD); + conn->readahead = iob_trimhead(iob, recvlen, + IOBUSER_NET_TCP_READAHEAD); } } } @@ -419,7 +411,7 @@ static uint16_t tcp_recvhandler(FAR struct net_driver_s *dev, * packet in the read-ahead buffer). */ - tcp_newdata(dev, pstate); + flags = tcp_newdata(dev, pstate, flags); /* Save the sender's address in the caller's 'from' location */ @@ -511,53 +503,6 @@ static uint16_t tcp_recvhandler(FAR struct net_driver_s *dev, return flags; } -/**************************************************************************** - * Name: tcp_ackhandler - * - * Description: - * This function is called with the network locked to send the ACK in - * response by the lower, device interfacing layer. - * - * Input Parameters: - * dev The structure of the network driver that generated the event. - * pvconn The connection structure associated with the socket - * flags Set of events describing why the callback was invoked - * - * Returned Value: - * ACK should be send in the response. - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -static uint16_t tcp_ackhandler(FAR struct net_driver_s *dev, - FAR void *pvconn, FAR void *pvpriv, - uint16_t flags) -{ - FAR struct tcp_conn_s *conn = (FAR struct tcp_conn_s *)pvconn; - - ninfo("flags: %04x\n", flags); - - if (conn != NULL && (flags & TCP_POLL) != 0) - { - /* Indicate that the data has been consumed and that an ACK - * should be send. - */ - - if (tcp_get_recvwindow(dev, conn) != 0 && - conn->rcv_wnd == 0) - { - flags |= TCP_SNDACK; - } - - tcp_callback_free(conn, conn->rcv_ackcb); - conn->rcv_ackcb = NULL; - } - - return flags; -} - /**************************************************************************** * Name: tcp_recvfrom_initialize * @@ -810,17 +755,16 @@ ssize_t psock_tcp_recvfrom(FAR struct socket *psock, FAR void *buf, } } - /* Receive additional data from read-ahead buffer, send the ACK timely. */ + /* Receive additional data from read-ahead buffer, send the ACK timely. + * + * Revisit: Because IOBs are system-wide resources, consuming the read + * ahead buffer would update recv window of all connections in the system, + * not only this particular connection. + */ - if (conn->rcv_wnd == 0 && conn->rcv_ackcb == NULL) + if (tcp_should_send_recvwindow(conn)) { - conn->rcv_ackcb = tcp_callback_alloc(conn); - if (conn->rcv_ackcb) - { - conn->rcv_ackcb->flags = TCP_POLL; - conn->rcv_ackcb->event = tcp_ackhandler; - netdev_txnotify_dev(conn->dev); - } + netdev_txnotify_dev(conn->dev); } net_unlock(); diff --git a/net/tcp/tcp_recvwindow.c b/net/tcp/tcp_recvwindow.c index 684cb955fc2..7be6fd16828 100644 --- a/net/tcp/tcp_recvwindow.c +++ b/net/tcp/tcp_recvwindow.c @@ -38,45 +38,87 @@ #include "tcp/tcp.h" /**************************************************************************** - * Static Functions + * Private Functions ****************************************************************************/ -static int tcp_iob_navail(FAR struct net_driver_s *dev, - FAR struct tcp_conn_s *conn) +/**************************************************************************** + * Name: tcp_calc_rcvsize + * + * Description: + * Calculate the possible max TCP receive buffer size for the connection. + * + * Input Parameters: + * conn - The TCP connection. + * recvwndo - The TCP receive window size + * + * Returned Value: + * The value of the TCP receive buffer size. + * + ****************************************************************************/ + +static uint32_t tcp_calc_rcvsize(FAR struct tcp_conn_s *conn, + uint32_t recvwndo) { - FAR struct tcp_conn_s *next = NULL; - int avail = iob_navail(true); - int count = 0; +#if CONFIG_NET_RECV_BUFSIZE > 0 + uint32_t recvsize; + uint32_t desire; - while ((next = tcp_nextconn(next)) != NULL) + recvsize = conn->readahead ? conn->readahead->io_pktlen : 0; + if (conn->rcv_bufs > recvsize) { - if (!IOB_QEMPTY(&next->readahead)) + desire = conn->rcv_bufs - recvsize; + if (recvwndo > desire) { - count++; + recvwndo = desire; } } - - if (count == 0) - { - return avail; - } - - if (avail > CONFIG_IOB_NBUFFERS / count) - { - avail = CONFIG_IOB_NBUFFERS / count; - } - - count = iob_get_queue_count(&conn->readahead); - if (avail > count) - { - avail -= count; - } else { - avail = 0; + recvwndo = 0; + } +#endif + + return recvwndo; +} + +/**************************************************************************** + * Name: tcp_maxrcvwin + * + * Description: + * Calculate the possible max TCP receive window for the connection. + * + * Input Parameters: + * conn - The TCP connection. + * + * Returned Value: + * The value of the TCP receive window. + ****************************************************************************/ + +static uint32_t tcp_maxrcvwin(FAR struct tcp_conn_s *conn) +{ + uint32_t recvwndo; + + /* Calculate the max possible window size for the connection. + * This needs to be in sync with tcp_get_recvwindow(). + */ + + recvwndo = tcp_calc_rcvsize(conn, (CONFIG_IOB_NBUFFERS - + CONFIG_IOB_THROTTLE) * + CONFIG_IOB_BUFSIZE); +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + recvwndo >>= conn->rcv_scale; +#endif + + if (recvwndo > UINT16_MAX) + { + recvwndo = UINT16_MAX; } - return avail; +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + recvwndo <<= conn->rcv_scale; +#endif + + return recvwndo; } /**************************************************************************** @@ -90,72 +132,50 @@ static int tcp_iob_navail(FAR struct net_driver_s *dev, * Calculate the TCP receive window for the specified device. * * Input Parameters: - * dev - The device whose TCP receive window will be updated. + * dev - The device whose TCP receive window will be updated. + * conn - The TCP connection structure holding connection information. * * Returned Value: * The value of the TCP receive window to use. * ****************************************************************************/ -uint16_t tcp_get_recvwindow(FAR struct net_driver_s *dev, +uint32_t tcp_get_recvwindow(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn) { - uint16_t iplen; - uint16_t mss; - uint16_t recvwndo; + uint32_t tailroom; + uint32_t recvwndo; int niob_avail; - int nqentry_avail; - -#ifdef CONFIG_NET_IPv6 -#ifdef CONFIG_NET_IPv4 - if (IFF_IS_IPv6(dev->d_flags)) -#endif - { - iplen = IPv6_HDRLEN; - } -#endif /* CONFIG_NET_IPv6 */ - -#ifdef CONFIG_NET_IPv4 -#ifdef CONFIG_NET_IPv6 - else -#endif - { - iplen = IPv4_HDRLEN; - } -#endif /* CONFIG_NET_IPv4 */ - - /* Calculate the packet MSS. - * - * REVISIT: The actual TCP header length is variable. TCP_HDRLEN - * is the minimum size. - */ - - mss = dev->d_pktsize - (NET_LL_HDRLEN(dev) + iplen + TCP_HDRLEN); /* Update the TCP received window based on read-ahead I/O buffer - * and IOB chain availability. At least one queue entry is required. - * If one queue entry is available, then the amount of read-ahead + * and IOB chain availability. + * The amount of read-ahead * data that can be buffered is given by the number of IOBs available * (ignoring competition with other IOB consumers). */ - niob_avail = tcp_iob_navail(dev, conn); - nqentry_avail = iob_qentry_navail(); + if (conn->readahead != NULL) + { + tailroom = iob_tailroom(conn->readahead); + } + else + { + tailroom = 0; + } + + niob_avail = iob_navail(true); /* Is there a a queue entry and IOBs available for read-ahead buffering? */ - if (nqentry_avail > 0 && niob_avail > 0) + if (niob_avail > 0) { - uint32_t rwnd; - /* The optimal TCP window size is the amount of TCP data that we can * currently buffer via TCP read-ahead buffering for the device packet * buffer. This logic here assumes that all IOBs are available for * TCP buffering. * * Assume that all of the available IOBs are can be used for buffering - * on this connection. Also assume that at least one chain is - * available concatenate the IOBs. + * on this connection. * * REVISIT: In an environment with multiple, active read-ahead TCP * sockets (and perhaps multiple network devices) or if there are @@ -164,35 +184,131 @@ uint16_t tcp_get_recvwindow(FAR struct net_driver_s *dev, * buffering for this connection. */ - rwnd = (niob_avail * CONFIG_IOB_BUFSIZE); - if (rwnd > UINT16_MAX) - { - rwnd = UINT16_MAX; - } - - /* Save the new receive window size */ - - recvwndo = (uint16_t)rwnd; + recvwndo = tailroom + (niob_avail * CONFIG_IOB_BUFSIZE); } - else if (IOB_QEMPTY(&conn->readahead)) +#if CONFIG_IOB_THROTTLE > 0 + else if (conn->readahead == NULL) { /* Advertise maximum segment size for window edge if here is no * available iobs on current "free" connection. + * + * Note: hopefully, a single mss-sized packet can be queued by + * the throttled=false case in tcp_datahandler(). */ - recvwndo = mss; + int niob_avail_no_throttle = iob_navail(false); + + recvwndo = tcp_rx_mss(dev); + if (recvwndo > niob_avail_no_throttle * CONFIG_IOB_BUFSIZE) + { + recvwndo = niob_avail_no_throttle * CONFIG_IOB_BUFSIZE; + } } - else /* nqentry_avail == 0 || niob_avail == 0 */ +#endif + else /* niob_avail == 0 */ { - /* No IOB chains or noIOBs are available. + /* No IOBs are available. * Advertise the edge of window to zero. * * NOTE: If no IOBs are available, then the next packet will be * lost if there is no listener on the connection. */ - recvwndo = 0; + recvwndo = tailroom; } + recvwndo = tcp_calc_rcvsize(conn, recvwndo); + +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + recvwndo >>= conn->rcv_scale; +#endif + + if (recvwndo > UINT16_MAX) + { + recvwndo = UINT16_MAX; + } + +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + recvwndo <<= conn->rcv_scale; +#endif + return recvwndo; } + +bool tcp_should_send_recvwindow(FAR struct tcp_conn_s *conn) +{ + FAR struct net_driver_s *dev = conn->dev; + uint32_t win; + uint32_t maxwin; + uint32_t oldwin; + uint32_t rcvseq; + uint32_t adv; + uint16_t mss; + + /* Note: rcv_adv can be smaller than rcvseq. + * For examples, when: + * + * - we shrunk the window + * - zero window probes advanced rcvseq + */ + + rcvseq = tcp_getsequence(conn->rcvseq); + if (TCP_SEQ_GT(conn->rcv_adv, rcvseq)) + { + oldwin = TCP_SEQ_SUB(conn->rcv_adv, rcvseq); + } + else + { + oldwin = 0; + } + + win = tcp_get_recvwindow(dev, conn); + + /* If the window doesn't extend, don't send. */ + + if (win <= oldwin) + { + ninfo("Returning false: " + "rcvseq=%" PRIu32 ", rcv_adv=%" PRIu32 ", " + "old win=%" PRIu32 ", new win=%" PRIu32 "\n", + rcvseq, conn->rcv_adv, oldwin, win); + return false; + } + + adv = win - oldwin; + + /* The following conditions are inspired from NetBSD TCP stack. + * + * - If we can extend the window by the half of the max possible size, + * send it. + * + * - If we can extend the window by 2 * mss, send it. + */ + + maxwin = tcp_maxrcvwin(conn); + if (2 * adv >= maxwin) + { + ninfo("Returning true: " + "adv=%" PRIu32 ", maxwin=%" PRIu32 "\n", + adv, maxwin); + return true; + } + + /* Revisit: the real expected size should be used instead. + * E.g. consider the path MTU + */ + + mss = tcp_rx_mss(dev); + if (adv >= 2 * mss) + { + ninfo("Returning true: " + "adv=%" PRIu32 ", mss=%" PRIu16 ", maxwin=%" PRIu32 "\n", + adv, mss, maxwin); + return true; + } + + ninfo("Returning false: " + "adv=%" PRIu32 ", mss=%" PRIu16 ", maxwin=%" PRIu32 "\n", + adv, mss, maxwin); + return false; +} diff --git a/net/tcp/tcp_send.c b/net/tcp/tcp_send.c index 9dcd0cbf88f..fd7eca15c01 100644 --- a/net/tcp/tcp_send.c +++ b/net/tcp/tcp_send.c @@ -45,6 +45,7 @@ #include #if defined(CONFIG_NET) && defined(CONFIG_NET_TCP) +#include #include #include #include @@ -55,6 +56,7 @@ #include #include +#include "netdev/netdev.h" #include "devif/devif.h" #include "inet/inet.h" #include "tcp/tcp.h" @@ -360,16 +362,21 @@ static void tcp_sendcommon(FAR struct net_driver_s *dev, { /* Update the TCP received window based on I/O buffer availability */ - uint16_t recvwndo = tcp_get_recvwindow(dev, conn); + uint32_t rcvseq = tcp_getsequence(conn->rcvseq); + uint32_t recvwndo = tcp_get_recvwindow(dev, conn); + + /* Update the Receiver Window */ + + conn->rcv_adv = rcvseq + recvwndo; + +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + recvwndo >>= conn->rcv_scale; +#endif /* Set the TCP Window */ tcp->wnd[0] = recvwndo >> 8; tcp->wnd[1] = recvwndo & 0xff; - - /* Update the Receiver Window */ - - conn->rcv_wnd = recvwndo; } /* Finish the IP portion of the message and calculate checksums */ @@ -507,6 +514,14 @@ void tcp_reset(FAR struct net_driver_s *dev) tcp->srcport = tcp->destport; tcp->destport = tmp16; + /* Initialize the rest of the tcp header to sane values. + * + * Note: urgp is set by tcp_ipv4_sendcomplete/tcp_ipv6_sendcomplete. + */ + + tcp->wnd[0] = 0; + tcp->wnd[1] = 0; + /* Set the packet length and swap IP addresses. */ #ifdef CONFIG_NET_IPv6 @@ -550,6 +565,45 @@ void tcp_reset(FAR struct net_driver_s *dev) tcp_sendcomplete(dev, tcp); } +/**************************************************************************** + * Name: tcp_rx_mss + * + * Description: + * Return the MSS to advertize to the peer. + * + * Input Parameters: + * dev - The device driver structure + * + * Returned Value: + * The MSS value. + * + ****************************************************************************/ + +uint16_t tcp_rx_mss(FAR struct net_driver_s *dev) +{ + uint16_t tcp_mss; + +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + if (IFF_IS_IPv6(dev->d_flags)) +#endif + { + tcp_mss = TCP_IPv6_MSS(dev); + } +#endif /* CONFIG_NET_IPv6 */ + +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + else +#endif + { + tcp_mss = TCP_IPv4_MSS(dev); + } +#endif /* CONFIG_NET_IPv4 */ + + return tcp_mss; +} + /**************************************************************************** * Name: tcp_synack * @@ -578,6 +632,7 @@ void tcp_synack(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, { struct tcp_hdr_s *tcp; uint16_t tcp_mss; + int16_t optlen = 0; /* Get values that vary with the underlying IP domain */ @@ -586,14 +641,13 @@ void tcp_synack(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, if (IFF_IS_IPv6(dev->d_flags)) #endif { - /* Get the MSS value and offset TCP header address for this packet */ + /* Get the offset TCP header address for this packet */ tcp = TCPIPv6BUF; - tcp_mss = TCP_IPv6_MSS(dev); /* Set the packet length for the TCP Maximum Segment Size */ - dev->d_len = IPv6TCP_HDRLEN + TCP_OPT_MSS_LEN; + dev->d_len = IPv6TCP_HDRLEN; } #endif /* CONFIG_NET_IPv6 */ @@ -602,32 +656,93 @@ void tcp_synack(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, else #endif { - /* Get the MSS value and offset TCP header address for this packet */ + /* Get the offset TCP header address for this packet */ tcp = TCPIPv4BUF; - tcp_mss = TCP_IPv4_MSS(dev); /* Set the packet length for the TCP Maximum Segment Size */ - dev->d_len = IPv4TCP_HDRLEN + TCP_OPT_MSS_LEN; + dev->d_len = IPv4TCP_HDRLEN; } #endif /* CONFIG_NET_IPv4 */ + tcp_mss = tcp_rx_mss(dev); + /* Save the ACK bits */ tcp->flags = ack; /* We send out the TCP Maximum Segment Size option with our ACK. */ - tcp->optdata[0] = TCP_OPT_MSS; - tcp->optdata[1] = TCP_OPT_MSS_LEN; - tcp->optdata[2] = tcp_mss >> 8; - tcp->optdata[3] = tcp_mss & 0xff; - tcp->tcpoffset = ((TCP_HDRLEN + TCP_OPT_MSS_LEN) / 4) << 4; + tcp->optdata[optlen++] = TCP_OPT_MSS; + tcp->optdata[optlen++] = TCP_OPT_MSS_LEN; + tcp->optdata[optlen++] = tcp_mss >> 8; + tcp->optdata[optlen++] = tcp_mss & 0xff; + +#ifdef CONFIG_NET_TCP_WINDOW_SCALE + if (tcp->flags == TCP_SYN || + ((tcp->flags == (TCP_ACK | TCP_SYN)) && (conn->flags & TCP_WSCALE))) + { + tcp->optdata[optlen++] = TCP_OPT_NOOP; + tcp->optdata[optlen++] = TCP_OPT_WS; + tcp->optdata[optlen++] = TCP_OPT_WS_LEN; + tcp->optdata[optlen++] = CONFIG_NET_TCP_WINDOW_SCALE_FACTOR; + } +#endif + + tcp->tcpoffset = ((TCP_HDRLEN + optlen) / 4) << 4; + dev->d_len += optlen; /* Complete the common portions of the TCP message */ tcp_sendcommon(dev, conn, tcp); } +/**************************************************************************** + * Name: tcp_send_txnotify + * + * Description: + * Notify the appropriate device driver that we are have data ready to + * be send (TCP) + * + * Input Parameters: + * psock - Socket state structure + * conn - The TCP connection structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +void tcp_send_txnotify(FAR struct socket *psock, + FAR struct tcp_conn_s *conn) +{ +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + /* If both IPv4 and IPv6 support are enabled, then we will need to select + * the device driver using the appropriate IP domain. + */ + + if (psock->s_domain == PF_INET) +#endif + { + /* Notify the device driver that send data is available */ + + netdev_ipv4_txnotify(conn->u.ipv4.laddr, conn->u.ipv4.raddr); + } +#endif /* CONFIG_NET_IPv4 */ + +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + else /* if (psock->s_domain == PF_INET6) */ +#endif /* CONFIG_NET_IPv4 */ + { + /* Notify the device driver that send data is available */ + + DEBUGASSERT(psock->s_domain == PF_INET6); + netdev_ipv6_txnotify(conn->u.ipv6.laddr, conn->u.ipv6.raddr); + } +#endif /* CONFIG_NET_IPv6 */ +} + #endif /* CONFIG_NET && CONFIG_NET_TCP */ diff --git a/net/tcp/tcp_send_buffered.c b/net/tcp/tcp_send_buffered.c index fb200d184a1..a8218d7922a 100644 --- a/net/tcp/tcp_send_buffered.c +++ b/net/tcp/tcp_send_buffered.c @@ -1,36 +1,20 @@ /**************************************************************************** * net/tcp/tcp_send_buffered.c * - * Copyright (C) 2007-2014, 2016-2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Jason Jiang + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -58,9 +42,9 @@ #include #include #include +#include #include #include -#include #include #include @@ -423,7 +407,7 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, * the write buffer has been ACKed. */ - if (ackno > TCP_WBSEQNO(wrb)) + if (TCP_SEQ_GT(ackno, TCP_WBSEQNO(wrb))) { /* Get the sequence number at the end of the data */ @@ -435,7 +419,7 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, /* Has the entire buffer been ACKed? */ - if (ackno >= lastseq) + if (TCP_SEQ_GTE(ackno, lastseq)) { ninfo("ACK: wrb=%p Freeing write buffer\n", wrb); @@ -465,7 +449,7 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, * buffers in the chain. */ - trimlen = ackno - TCP_WBSEQNO(wrb); + trimlen = TCP_SEQ_SUB(ackno, TCP_WBSEQNO(wrb)); if (trimlen > TCP_WBSENT(wrb)) { /* More data has been ACKed then we have sent? */ @@ -487,6 +471,13 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, } else if (ackno == TCP_WBSEQNO(wrb)) { + /* Reset the duplicate ack counter */ + + if ((flags & TCP_NEWDATA) != 0) + { + TCP_WBNACK(wrb) = 0; + } + /* Duplicate ACK? Retransmit data if need */ if (++TCP_WBNACK(wrb) == @@ -502,28 +493,6 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, { /* Reset the duplicate ack counter */ - TCP_WBNACK(wrb) = 0; - } - } - else if (ackno == TCP_WBSEQNO(wrb)) - { - /* Duplicate ACK? Retransmit data if need */ - - TCP_WBNACK(wrb)++; - - if (TCP_WBNACK(wrb) == - CONFIG_NET_TCP_FAST_RETRANSMIT_WATERMARK) - { - /* Do fast retransmit */ - - rexmit = true; - } - else if ((TCP_WBNACK(wrb) > - CONFIG_NET_TCP_FAST_RETRANSMIT_WATERMARK) && - TCP_WBNACK(wrb) == sq_count(&conn->unacked_q) - 1) - { - /* Reset the duplicate ack counter */ - TCP_WBNACK(wrb) = 0; } } @@ -535,13 +504,13 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, */ wrb = (FAR struct tcp_wrbuffer_s *)sq_peek(&conn->write_q); - if (wrb && TCP_WBSENT(wrb) > 0 && ackno > TCP_WBSEQNO(wrb)) + if (wrb && TCP_WBSENT(wrb) > 0 && TCP_SEQ_GT(ackno, TCP_WBSEQNO(wrb))) { uint32_t nacked; /* Number of bytes that were ACKed */ - nacked = ackno - TCP_WBSEQNO(wrb); + nacked = TCP_SEQ_SUB(ackno, TCP_WBSEQNO(wrb)); if (nacked > TCP_WBSENT(wrb)) { /* More data has been ACKed then we have sent? ASSERT? */ @@ -842,8 +811,7 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, predicted_seqno = tcp_getsequence(conn->sndseq) + sndlen; - if ((predicted_seqno > conn->sndseq_max) || - (tcp_getsequence(conn->sndseq) > predicted_seqno)) /* overflow */ + if (TCP_SEQ_GT(predicted_seqno, conn->sndseq_max)) { conn->sndseq_max = predicted_seqno; } @@ -892,53 +860,6 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, return flags; } -/**************************************************************************** - * Name: send_txnotify - * - * Description: - * Notify the appropriate device driver that we are have data ready to - * be send (TCP) - * - * Input Parameters: - * psock - Socket state structure - * conn - The TCP connection structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void send_txnotify(FAR struct socket *psock, - FAR struct tcp_conn_s *conn) -{ -#ifdef CONFIG_NET_IPv4 -#ifdef CONFIG_NET_IPv6 - /* If both IPv4 and IPv6 support are enabled, then we will need to select - * the device driver using the appropriate IP domain. - */ - - if (psock->s_domain == PF_INET) -#endif - { - /* Notify the device driver that send data is available */ - - netdev_ipv4_txnotify(conn->u.ipv4.laddr, conn->u.ipv4.raddr); - } -#endif /* CONFIG_NET_IPv4 */ - -#ifdef CONFIG_NET_IPv6 -#ifdef CONFIG_NET_IPv4 - else /* if (psock->s_domain == PF_INET6) */ -#endif /* CONFIG_NET_IPv4 */ - { - /* Notify the device driver that send data is available */ - - DEBUGASSERT(psock->s_domain == PF_INET6); - netdev_ipv6_txnotify(conn->u.ipv6.laddr, conn->u.ipv6.raddr); - } -#endif /* CONFIG_NET_IPv6 */ -} - /**************************************************************************** * Name: tcp_max_wrb_size * @@ -1275,7 +1196,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, FAR const void *buf, /* Notify the device driver of the availability of TX data */ - send_txnotify(psock, conn); + tcp_send_txnotify(psock, conn); net_unlock(); if (chunk_result == 0) diff --git a/net/tcp/tcp_send_unbuffered.c b/net/tcp/tcp_send_unbuffered.c index baf03789fc8..d4873181b79 100644 --- a/net/tcp/tcp_send_unbuffered.c +++ b/net/tcp/tcp_send_unbuffered.c @@ -220,7 +220,8 @@ static uint16_t tcpsend_eventhandler(FAR struct net_driver_s *dev, * of bytes to be acknowledged. */ - pstate->snd_acked = tcp_getsequence(tcp->ackno) - pstate->snd_isn; + pstate->snd_acked = TCP_SEQ_SUB(tcp_getsequence(tcp->ackno), + pstate->snd_isn); ninfo("ACK: acked=%" PRId32 " sent=%zd buflen=%zd\n", pstate->snd_acked, pstate->snd_sent, pstate->snd_buflen); @@ -461,53 +462,6 @@ end_wait: return flags; } -/**************************************************************************** - * Name: send_txnotify - * - * Description: - * Notify the appropriate device driver that we are have data ready to - * be send (TCP) - * - * Input Parameters: - * psock - Socket state structure - * conn - The TCP connection structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void send_txnotify(FAR struct socket *psock, - FAR struct tcp_conn_s *conn) -{ -#ifdef CONFIG_NET_IPv4 -#ifdef CONFIG_NET_IPv6 - /* If both IPv4 and IPv6 support are enabled, then we will need to select - * the device driver using the appropriate IP domain. - */ - - if (psock->s_domain == PF_INET) -#endif - { - /* Notify the device driver that send data is available */ - - netdev_ipv4_txnotify(conn->u.ipv4.laddr, conn->u.ipv4.raddr); - } -#endif /* CONFIG_NET_IPv4 */ - -#ifdef CONFIG_NET_IPv6 -#ifdef CONFIG_NET_IPv4 - else /* if (psock->s_domain == PF_INET6) */ -#endif /* CONFIG_NET_IPv4 */ - { - /* Notify the device driver that send data is available */ - - DEBUGASSERT(psock->s_domain == PF_INET6); - netdev_ipv6_txnotify(conn->u.ipv6.laddr, conn->u.ipv6.raddr); - } -#endif /* CONFIG_NET_IPv6 */ -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -584,9 +538,12 @@ ssize_t psock_tcp_send(FAR struct socket *psock, goto errout; } - /* If this is an un-connected socket, then return ENOTCONN */ + /* Check early if this is an un-connected socket, if so, then + * return -ENOTCONN. Note, we will have to check this again, as we can't + * guarantee the state won't change until we have the network locked. + */ - if (psock->s_type != SOCK_STREAM || !_SS_ISCONNECTED(psock->s_flags)) + if (psock->s_type != SOCK_STREAM) { nerr("ERROR: Not connected\n"); ret = -ENOTCONN; @@ -639,6 +596,19 @@ ssize_t psock_tcp_send(FAR struct socket *psock, */ net_lock(); + + /* Now that we have the network locked, we need to check the connection + * state again to ensure the connection is still valid. + */ + + if (!_SS_ISCONNECTED(psock->s_flags)) + { + nerr("ERROR: No longer connected\n"); + net_unlock(); + ret = -ENOTCONN; + goto errout; + } + memset(&state, 0, sizeof(struct send_s)); /* This semaphore is used for signaling and, hence, should not have @@ -679,7 +649,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, /* Notify the device driver of the availability of TX data */ - send_txnotify(psock, conn); + tcp_send_txnotify(psock, conn); /* Wait for the send to complete or an error to occur: NOTES: * net_lockedwait will also terminate if a signal is received. diff --git a/net/tcp/tcp_sendfile.c b/net/tcp/tcp_sendfile.c index 785d5feb9a3..36950a6b1ac 100644 --- a/net/tcp/tcp_sendfile.c +++ b/net/tcp/tcp_sendfile.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include diff --git a/net/tcp/tcp_setsockopt.c b/net/tcp/tcp_setsockopt.c index 19b1e4e3c56..b4082ba2d99 100644 --- a/net/tcp/tcp_setsockopt.c +++ b/net/tcp/tcp_setsockopt.c @@ -154,79 +154,52 @@ int tcp_setsockopt(FAR struct socket *psock, int option, break; case TCP_KEEPIDLE: /* Start keepalives after this IDLE period */ - if (value_len != sizeof(struct timeval)) - { - ret = -EDOM; - } - else - { - FAR struct timeval *tv = (FAR struct timeval *)value; - - if (tv == NULL) - { - ret = -EINVAL; - } - else - { - unsigned int dsecs; - - /* Get the IDLE time value. Any microsecond remainder will - * be forced to the next larger, whole decisecond value. - */ - - dsecs = (socktimeo_t)net_timeval2dsec(tv, TV2DS_CEIL); - if (dsecs > UINT16_MAX) - { - nwarn("WARNING: TCP_KEEPIDLE value out of range: %u\n", - dsecs); - ret = -EDOM; - } - else - { - conn->keepidle = (uint16_t)dsecs; - conn->keeptime = clock_systime_ticks(); /* Reset start time */ - ret = OK; - } - } - } - break; - case TCP_KEEPINTVL: /* Interval between keepalives */ - if (value_len != sizeof(struct timeval)) - { - ret = -EDOM; - } - else - { - FAR struct timeval *tv = (FAR struct timeval *)value; + { + unsigned int dsecs; - if (tv == NULL) - { - ret = -EINVAL; - } - else - { - unsigned int dsecs; + if (value == NULL) + { + return -EINVAL; + } + else if (value_len == sizeof(struct timeval)) + { + FAR struct timeval *tv = (FAR struct timeval *)value; - /* Get the IDLE time value. Any microsecond remainder will - * be forced to the next larger, whole decisecond value. - */ + /* Get the IDLE time value. Any microsecond remainder will + * be forced to the next larger, whole decisecond value. + */ - dsecs = (socktimeo_t)net_timeval2dsec(tv, TV2DS_CEIL); - if (dsecs > UINT16_MAX) - { - nwarn("WARNING: TCP_KEEPINTVL value out of range: %u\n", - dsecs); - ret = -EDOM; - } - else - { - conn->keepintvl = (uint16_t)dsecs; - conn->keeptime = clock_systime_ticks(); /* Reset start time */ - ret = OK; - } - } - } + dsecs = (socktimeo_t)net_timeval2dsec(tv, TV2DS_CEIL); + } + else if (value_len == sizeof(int)) + { + dsecs = *(FAR int *)value; + } + else + { + return -EDOM; + } + + if (dsecs > UINT16_MAX) + { + nwarn("WARNING: value out of range: %u\n", dsecs); + return -EDOM; + } + + if (option == TCP_KEEPIDLE) + { + conn->keepidle = (uint16_t)dsecs; + } + else + { + conn->keepintvl = (uint16_t)dsecs; + } + + conn->keeptime = clock_systime_ticks(); /* Reset start time */ + + ret = OK; + } break; case TCP_KEEPCNT: /* Number of keepalives before death */ diff --git a/net/tcp/tcp_wrbuffer.c b/net/tcp/tcp_wrbuffer.c index 03dff66d449..c93f7495e9f 100644 --- a/net/tcp/tcp_wrbuffer.c +++ b/net/tcp/tcp_wrbuffer.c @@ -1,37 +1,20 @@ /**************************************************************************** * net/tcp/tcp_wrbuffer.c * - * Copyright (C) 2007-2009, 2013-2014, 2018 Gregory Nutt. All rights - * reserved. - * Author: Gregory Nutt - * Jason Jiang + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/net/udp/udp.h b/net/udp/udp.h index eb5e73dbe88..71a4b2ef453 100644 --- a/net/udp/udp.h +++ b/net/udp/udp.h @@ -120,6 +120,9 @@ struct udp_conn_s uint8_t boundto; /* Index of the interface we are bound to. * Unbound: 0, Bound: 1-MAX_IFINDEX */ #endif +#if CONFIG_NET_RECV_BUFSIZE > 0 + int32_t rcvbufs; /* Maximum amount of bytes queued in recv */ +#endif /* Read-ahead buffering. * diff --git a/net/udp/udp_callback.c b/net/udp/udp_callback.c index 3a4796434f6..47d91f2cfb5 100644 --- a/net/udp/udp_callback.c +++ b/net/udp/udp_callback.c @@ -83,6 +83,14 @@ static uint16_t udp_datahandler(FAR struct net_driver_s *dev, FAR void *src_addr; uint8_t src_addr_size; +#if CONFIG_NET_RECV_BUFSIZE > 0 + while (iob_get_queue_size(&conn->readahead) > conn->rcvbufs) + { + iob = iob_remove_queue(&conn->readahead); + iob_free_chain(iob, IOBUSER_NET_UDP_READAHEAD); + } +#endif + /* Allocate on I/O buffer to start the chain (throttling as necessary). * We will not wait for an I/O buffer to become available in this context. */ @@ -211,7 +219,7 @@ static uint16_t udp_datahandler(FAR struct net_driver_s *dev, /* Add the new I/O buffer chain to the tail of the read-ahead queue */ - ret = iob_tryadd_queue(iob, NULL, &conn->readahead); + ret = iob_tryadd_queue(iob, &conn->readahead); if (ret < 0) { nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret); diff --git a/net/udp/udp_close.c b/net/udp/udp_close.c index 2e4722ed152..b2610ce407a 100644 --- a/net/udp/udp_close.c +++ b/net/udp/udp_close.c @@ -29,10 +29,14 @@ #include #include +#include + #include +#include #include #include "devif/devif.h" +#include "netdev/netdev.h" #include "udp/udp.h" #include "socket/socket.h" @@ -63,7 +67,7 @@ int udp_close(FAR struct socket *psock) unsigned int timeout = UINT_MAX; int ret; - /* Interrupts are disabled here to avoid race conditions */ + /* Lock the network to avoid race conditions */ net_lock(); @@ -102,6 +106,28 @@ int udp_close(FAR struct socket *psock) nerr("ERROR: udp_txdrain() failed: %d\n", ret); } +#ifdef CONFIG_NET_UDP_BINDTODEVICE + /* Is the socket bound to an interface device */ + + if (conn->boundto != 0) + { + FAR struct net_driver_s *dev; + + /* Yes, get the interface that we are bound do. NULL would indicate + * that the interface no longer exists for some reason. + */ + + dev = netdev_findbyindex(conn->boundto); + if (dev != NULL) + { + /* Clear the interface flag to unbind the device from the socket. + */ + + IFF_CLR_BOUND(dev->d_flags); + } + } +#endif + #ifdef CONFIG_NET_UDP_WRITE_BUFFERS /* Free any semi-permanent write buffer callback in place. */ diff --git a/net/udp/udp_conn.c b/net/udp/udp_conn.c index c5716fe4e9e..1aba26c88ac 100644 --- a/net/udp/udp_conn.c +++ b/net/udp/udp_conn.c @@ -585,6 +585,9 @@ FAR struct udp_conn_s *udp_alloc(uint8_t domain) #endif conn->lport = 0; conn->ttl = IP_TTL_DEFAULT; +#if CONFIG_NET_RECV_BUFSIZE > 0 + conn->rcvbufs = CONFIG_NET_RECV_BUFSIZE; +#endif #ifdef CONFIG_NET_UDP_WRITE_BUFFERS /* Initialize the write buffer lists */ @@ -628,7 +631,7 @@ void udp_free(FAR struct udp_conn_s *conn) /* Release any read-ahead buffers attached to the connection */ - iob_destroy_queue(&conn->readahead, IOBUSER_NET_UDP_READAHEAD); + iob_free_queue(&conn->readahead, IOBUSER_NET_UDP_READAHEAD); #ifdef CONFIG_NET_UDP_WRITE_BUFFERS /* Release any write buffers attached to the connection */ diff --git a/net/udp/udp_ioctl.c b/net/udp/udp_ioctl.c index f9362e4bd76..bb458f38bb7 100644 --- a/net/udp/udp_ioctl.c +++ b/net/udp/udp_ioctl.c @@ -33,6 +33,7 @@ #include #include +#include #include "udp/udp.h" @@ -57,18 +58,30 @@ int udp_ioctl(FAR struct udp_conn_s *conn, int cmd, FAR void *arg, size_t arglen) { + FAR struct iob_s *iob; int ret = OK; + net_lock(); + switch (cmd) { case FIONREAD: - *(FAR int *)((uintptr_t)arg) = - iob_get_queue_size(&conn->readahead); + iob = iob_peek_queue(&conn->readahead); + if (iob) + { + *(FAR int *)((uintptr_t)arg) = iob->io_pktlen; + } + else + { + *(FAR int *)((uintptr_t)arg) = 0; + } break; default: ret = -ENOTTY; break; } + net_unlock(); + return ret; } diff --git a/net/udp/udp_sendto_buffered.c b/net/udp/udp_sendto_buffered.c index e7a0cae0c59..cefe8a30cda 100644 --- a/net/udp/udp_sendto_buffered.c +++ b/net/udp/udp_sendto_buffered.c @@ -41,9 +41,9 @@ #include #include #include +#include #include #include -#include #include #include diff --git a/net/udp/udp_setsockopt.c b/net/udp/udp_setsockopt.c index e3d4dca7d7e..bd5bd997c8f 100644 --- a/net/udp/udp_setsockopt.c +++ b/net/udp/udp_setsockopt.c @@ -29,9 +29,11 @@ #include #include +#include #include #include +#include #include #include "socket/socket.h" @@ -112,30 +114,74 @@ int udp_setsockopt(FAR struct socket *psock, int option, */ case UDP_BINDTODEVICE: /* Bind socket to a specific network device */ - if (value == NULL || value_len == 0 || - (value_len > 0 && ((FAR char *)value)[0] == 0)) - { - conn->boundto = 0; /* This interface is no longer bound */ - ret = OK; - } - else - { - int ifindex; + { + FAR struct net_driver_s *dev; - /* Get the interface index corresponding to the interface name */ + /* Check if we are are unbinding the socket */ - ifindex = netdev_nametoindex(value); - if (ifindex >= 0) - { - conn->boundto = ifindex; - ret = OK; - } - else - { - ret = ifindex; - } - } + if (value == NULL || value_len == 0 || + (value_len > 0 && ((FAR char *)value)[0] == 0)) + { + /* Just report success if the socket is not bound to an + * interface. + */ + if (conn->boundto != 0) + { + /* Get the interface that we are bound do. NULL would + * indicate that the interface no longer exists for some + * reason. + */ + + dev = netdev_findbyindex(conn->boundto); + if (dev != NULL) + { + /* Clear the interface flag to unbind the device from + * the socket. + */ + + IFF_CLR_BOUND(dev->d_flags); + } + + conn->boundto = 0; /* This interface is no longer bound */ + } + + ret = OK; + } + + /* No, we are binding a socket to the interface. */ + + else + { + /* Find the interface device with this name */ + + dev = netdev_findbyname(value); + if (dev == NULL) + { + ret = -ENODEV; + } + + /* An interface may be bound only to one socket. */ + + else if (IFF_IS_BOUND(dev->d_flags)) + { + ret = -EBUSY; + } + else + { + /* Bind the interface to a socket */ + + IFF_SET_BOUND(dev->d_flags); + + /* Bind the socket to the interface */ + + DEBUGASSERT(dev->d_ifindex > 0 && + dev->d_ifindex <= MAX_IFINDEX); + conn->boundto = dev->d_ifindex; + ret = OK; + } + } + } break; #endif diff --git a/net/usrsock/usrsock_recvmsg.c b/net/usrsock/usrsock_recvmsg.c index 09b98b26181..2d895cb00fa 100644 --- a/net/usrsock/usrsock_recvmsg.c +++ b/net/usrsock/usrsock_recvmsg.c @@ -99,7 +99,7 @@ static uint16_t recvfrom_event(FAR struct net_driver_s *dev, pstate->valuelen_nontrunc = conn->resp.valuelen_nontrunc; } - if (pstate->reqstate.result == 0 || + if (pstate->reqstate.result >= 0 || pstate->reqstate.result == -EAGAIN) { /* After reception of data, mark input not ready. Daemon will @@ -379,7 +379,8 @@ ssize_t usrsock_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg, /* Did remote disconnect? */ - if (conn->flags & USRSOCK_EVENT_REMOTE_CLOSED) + if (conn->flags & USRSOCK_EVENT_REMOTE_CLOSED && + !(conn->flags & USRSOCK_EVENT_RECVFROM_AVAIL)) { ret = 0; goto errout_unlock; diff --git a/openamp/0008-ns-acknowledge-the-received-creation-message.patch b/openamp/0001-ns-acknowledge-the-received-creation-message.patch similarity index 68% rename from openamp/0008-ns-acknowledge-the-received-creation-message.patch rename to openamp/0001-ns-acknowledge-the-received-creation-message.patch index be3ecb85b6b..2270cb31edd 100644 --- a/openamp/0008-ns-acknowledge-the-received-creation-message.patch +++ b/openamp/0001-ns-acknowledge-the-received-creation-message.patch @@ -1,7 +1,7 @@ -From 3ea08a8002de5e4992bed32567ecb05c887f31be Mon Sep 17 00:00:00 2001 +From 34cacff47da59075d930a5e96b16d003b70d383d Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Mon, 7 Jan 2019 02:15:42 +0800 -Subject: [PATCH 08/10] ns: acknowledge the received creation message +Subject: [PATCH 1/3] ns: acknowledge the received creation message the two phase handsake make the client could initiate the transfer immediately without the server side send any dummy message first. @@ -10,16 +10,16 @@ Signed-off-by: Xiang Xiao --- lib/include/openamp/rpmsg.h | 1 + lib/include/openamp/rpmsg_virtio.h | 1 + - lib/rpmsg/rpmsg.c | 7 +++++-- + lib/rpmsg/rpmsg.c | 5 ++++- lib/rpmsg/rpmsg_internal.h | 4 ++-- - lib/rpmsg/rpmsg_virtio.c | 12 +++++++++--- - 5 files changed, 18 insertions(+), 7 deletions(-) + lib/rpmsg/rpmsg_virtio.c | 14 +++++++++++--- + 5 files changed, 19 insertions(+), 6 deletions(-) diff --git a/lib/include/openamp/rpmsg.h open-amp/lib/include/openamp/rpmsg.h -index 0b46ee1..318acd1 100644 +index 8b8ec2e..efdfb2b 100644 --- a/lib/include/openamp/rpmsg.h +++ open-amp/lib/include/openamp/rpmsg.h -@@ -127,6 +127,7 @@ struct rpmsg_device { +@@ -120,6 +120,7 @@ struct rpmsg_device { rpmsg_ns_bind_cb ns_bind_cb; struct rpmsg_device_ops ops; bool support_ns; @@ -28,7 +28,7 @@ index 0b46ee1..318acd1 100644 /** diff --git a/lib/include/openamp/rpmsg_virtio.h open-amp/lib/include/openamp/rpmsg_virtio.h -index 2209a48..e6e5fa2 100644 +index 12cb47f..4d3093b 100644 --- a/lib/include/openamp/rpmsg_virtio.h +++ open-amp/lib/include/openamp/rpmsg_virtio.h @@ -28,6 +28,7 @@ extern "C" { @@ -40,30 +40,29 @@ index 2209a48..e6e5fa2 100644 /** * struct rpmsg_virtio_shm_pool - shared memory pool used for rpmsg buffers diff --git a/lib/rpmsg/rpmsg.c open-amp/lib/rpmsg/rpmsg.c -index 0a8de1b..0cc80da 100644 +index 46c3691..e52144b 100644 --- a/lib/rpmsg/rpmsg.c +++ open-amp/lib/rpmsg/rpmsg.c @@ -297,10 +297,13 @@ int rpmsg_create_ept(struct rpmsg_endpoint *ept, struct rpmsg_device *rdev, + rpmsg_register_endpoint(rdev, ept); + metal_mutex_release(&rdev->lock); - rpmsg_init_ept(ept, rdev, name, addr, dest, cb, unbind_cb); +- /* Send NS announcement to remote processor */ ++ /* Send NS announcement/acknowledge to remote processor */ + if (ept->name[0] && rdev->support_ns && + ept->dest_addr == RPMSG_ADDR_ANY) + status = rpmsg_send_ns_message(ept, RPMSG_NS_CREATE); ++ else if (ept->name[0] && rdev->support_ack && ++ ept->dest_addr != RPMSG_ADDR_ANY) ++ status = rpmsg_send_ns_message(ept, RPMSG_NS_CREATE_ACK); -- if (rdev->support_ns && ept->dest_addr == RPMSG_ADDR_ANY) { -+ if (ept->name[0]) { - /* Send NS announcement to remote processor */ - metal_mutex_release(&rdev->lock); -- status = rpmsg_send_ns_message(ept, RPMSG_NS_CREATE); -+ if (rdev->support_ns && ept->dest_addr == RPMSG_ADDR_ANY) -+ status = rpmsg_send_ns_message(ept, RPMSG_NS_CREATE); -+ else if (rdev->support_ack && ept->dest_addr != RPMSG_ADDR_ANY) -+ status = rpmsg_send_ns_message(ept, RPMSG_NS_CREATE_ACK); - metal_mutex_acquire(&rdev->lock); - if (status) - rpmsg_unregister_endpoint(ept); + if (status) + rpmsg_unregister_endpoint(ept); diff --git a/lib/rpmsg/rpmsg_internal.h open-amp/lib/rpmsg/rpmsg_internal.h -index 3db6b24..d513a56 100644 +index d4536d1..e64aeff 100644 --- a/lib/rpmsg/rpmsg_internal.h +++ open-amp/lib/rpmsg/rpmsg_internal.h -@@ -44,12 +44,12 @@ extern "C" { +@@ -39,12 +39,12 @@ extern "C" { * * @RPMSG_NS_CREATE: a new remote service was just created * @RPMSG_NS_DESTROY: a known remote service was just destroyed @@ -79,10 +78,10 @@ index 3db6b24..d513a56 100644 /** diff --git a/lib/rpmsg/rpmsg_virtio.c open-amp/lib/rpmsg/rpmsg_virtio.c -index 195189d..9988a1e 100644 +index 86a23ad..640240a 100644 --- a/lib/rpmsg/rpmsg_virtio.c +++ open-amp/lib/rpmsg/rpmsg_virtio.c -@@ -586,13 +586,13 @@ static int rpmsg_virtio_ns_callback(struct rpmsg_endpoint *ept, void *data, +@@ -554,13 +554,13 @@ static int rpmsg_virtio_ns_callback(struct rpmsg_endpoint *ept, void *data, metal_mutex_acquire(&rdev->lock); _ept = rpmsg_get_endpoint(rdev, name, RPMSG_ADDR_ANY, dest); @@ -92,15 +91,18 @@ index 195189d..9988a1e 100644 _ept->dest_addr = RPMSG_ADDR_ANY; metal_mutex_release(&rdev->lock); if (_ept && _ept->ns_unbind_cb) - _ept->ns_unbind_cb(ept); + _ept->ns_unbind_cb(_ept); - } else { + } else if (ns_msg->flags == RPMSG_NS_CREATE) { if (!_ept) { /* * send callback to application, that can -@@ -607,6 +607,11 @@ static int rpmsg_virtio_ns_callback(struct rpmsg_endpoint *ept, void *data, +@@ -574,7 +574,14 @@ static int rpmsg_virtio_ns_callback(struct rpmsg_endpoint *ept, void *data, + } else { _ept->dest_addr = dest; metal_mutex_release(&rdev->lock); ++ if (_ept->name[0] && rdev->support_ack) ++ rpmsg_send_ns_message(_ept, RPMSG_NS_CREATE_ACK); } + } else { /* RPMSG_NS_CREATE_ACK */ + /* save the received destination address */ @@ -110,7 +112,7 @@ index 195189d..9988a1e 100644 } return RPMSG_SUCCESS; -@@ -659,6 +664,7 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, +@@ -627,6 +634,7 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, #endif /*!VIRTIO_MASTER_ONLY*/ vdev->features = rpmsg_virtio_get_features(rvdev); rdev->support_ns = !!(vdev->features & (1 << VIRTIO_RPMSG_F_NS)); @@ -118,15 +120,15 @@ index 195189d..9988a1e 100644 #ifndef VIRTIO_SLAVE_ONLY if (role == RPMSG_MASTER) { -@@ -754,7 +760,7 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, +@@ -722,7 +730,7 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, * Create name service announcement endpoint if device supports name * service announcement feature. */ - if (rdev->support_ns) { + if (rdev->support_ns || rdev->support_ack) { - rpmsg_init_ept(&rdev->ns_ept, rdev, "NS", - RPMSG_NS_EPT_ADDR, RPMSG_NS_EPT_ADDR, - rpmsg_virtio_ns_callback, NULL); + rpmsg_initialize_ept(&rdev->ns_ept, "NS", + RPMSG_NS_EPT_ADDR, RPMSG_NS_EPT_ADDR, + rpmsg_virtio_ns_callback, NULL); -- 2.17.1 diff --git a/openamp/0001-rpmsg-remove-the-address-check-in-rpmsg_send-rpmsg_t.patch b/openamp/0001-rpmsg-remove-the-address-check-in-rpmsg_send-rpmsg_t.patch deleted file mode 100644 index 8e2edab18ee..00000000000 --- a/openamp/0001-rpmsg-remove-the-address-check-in-rpmsg_send-rpmsg_t.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5bc0ae0942fa9a4b9d321e31445457c31c888530 Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Fri, 24 Apr 2020 01:44:31 +0800 -Subject: [PATCH 01/10] rpmsg: remove the address check in - rpmsg_send/rpmsg_trysend - -since rpmsg_send_offchannel_raw already do the same validation - -Signed-off-by: Xiang Xiao ---- - lib/include/openamp/rpmsg.h | 4 ---- - 1 file changed, 4 deletions(-) - -diff --git a/lib/include/openamp/rpmsg.h open-amp/lib/include/openamp/rpmsg.h -index f2a6454..8401c38 100644 ---- a/lib/include/openamp/rpmsg.h -+++ open-amp/lib/include/openamp/rpmsg.h -@@ -146,8 +146,6 @@ int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src, - static inline int rpmsg_send(struct rpmsg_endpoint *ept, const void *data, - int len) - { -- if (ept->dest_addr == RPMSG_ADDR_ANY) -- return RPMSG_ERR_ADDR; - return rpmsg_send_offchannel_raw(ept, ept->addr, ept->dest_addr, data, - len, true); - } -@@ -216,8 +214,6 @@ static inline int rpmsg_send_offchannel(struct rpmsg_endpoint *ept, - static inline int rpmsg_trysend(struct rpmsg_endpoint *ept, const void *data, - int len) - { -- if (ept->dest_addr == RPMSG_ADDR_ANY) -- return RPMSG_ERR_ADDR; - return rpmsg_send_offchannel_raw(ept, ept->addr, ept->dest_addr, data, - len, false); - } --- -2.17.1 - diff --git a/openamp/0001-system-nuttx-change-clock_systimespec-to-clock_systi.patch b/openamp/0001-system-nuttx-change-clock_systimespec-to-clock_systi.patch deleted file mode 100644 index 3378774c925..00000000000 --- a/openamp/0001-system-nuttx-change-clock_systimespec-to-clock_systi.patch +++ /dev/null @@ -1,29 +0,0 @@ -From fa4904c9d9ad16e791485d0ef22566427869144c Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Mon, 11 May 2020 00:03:51 +0800 -Subject: [PATCH] system: nuttx: change clock_systimespec to - clock_systime_timespec - -follow up the change from NuttX side - -Signed-off-by: Xiang Xiao ---- - lib/system/nuttx/time.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/lib/system/nuttx/time.c libmetal/lib/system/nuttx/time.c -index bafc957..986f1ba 100644 ---- a/lib/system/nuttx/time.c -+++ libmetal/lib/system/nuttx/time.c -@@ -18,7 +18,7 @@ unsigned long long metal_get_timestamp(void) - struct timespec tp; - int r; - -- r = clock_systimespec(&tp); -+ r = clock_systime_timespec(&tp); - if (!r) { - t = (unsigned long long)tp.tv_sec * NSEC_PER_SEC; - t += tp.tv_nsec; --- -2.17.1 - diff --git a/openamp/0010-Negotiate-individual-buffer-size-dynamically.patch b/openamp/0002-Negotiate-individual-buffer-size-dynamically.patch similarity index 79% rename from openamp/0010-Negotiate-individual-buffer-size-dynamically.patch rename to openamp/0002-Negotiate-individual-buffer-size-dynamically.patch index 03d14d587f0..7369bfbbd3c 100644 --- a/openamp/0010-Negotiate-individual-buffer-size-dynamically.patch +++ b/openamp/0002-Negotiate-individual-buffer-size-dynamically.patch @@ -1,21 +1,21 @@ -From 2a64e1f23b140e1e2fdabfe77ed7a11062ef341a Mon Sep 17 00:00:00 2001 -From: anchao +From effea71e4d59797cd6149a81b2c6b88dc550d972 Mon Sep 17 00:00:00 2001 +From: Chao An Date: Mon, 10 Dec 2018 16:26:39 +0800 -Subject: [PATCH 10/10] Negotiate individual buffer size dynamically +Subject: [PATCH 2/3] Negotiate individual buffer size dynamically If slave support VIRTIO_RPMSG_F_BUFSZ(0x04) feature, master determine the buffer size from config space(first 8 bytes), otherwise the default size(512 bytes) will be used. -Signed-off-by: anchao +Signed-off-by: Chao An --- lib/include/openamp/remoteproc.h | 17 +++++++++++++++++ lib/include/openamp/rpmsg_virtio.h | 4 ++++ - lib/rpmsg/rpmsg_virtio.c | 22 ++++++++++++++++------ - 3 files changed, 37 insertions(+), 6 deletions(-) + lib/rpmsg/rpmsg_virtio.c | 21 +++++++++++++++------ + 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/lib/include/openamp/remoteproc.h open-amp/lib/include/openamp/remoteproc.h -index b34cb1a..ee9162a 100644 +index f558846..a71327b 100644 --- a/lib/include/openamp/remoteproc.h +++ open-amp/lib/include/openamp/remoteproc.h @@ -303,6 +303,23 @@ struct fw_rsc_vdev { @@ -43,7 +43,7 @@ index b34cb1a..ee9162a 100644 * struct fw_rsc_vendor - remote processor vendor specific resource * @len: length of the resource diff --git a/lib/include/openamp/rpmsg_virtio.h open-amp/lib/include/openamp/rpmsg_virtio.h -index 4d3093b..7f0c573 100644 +index 4d3093b..e552b96 100644 --- a/lib/include/openamp/rpmsg_virtio.h +++ open-amp/lib/include/openamp/rpmsg_virtio.h @@ -16,6 +16,7 @@ @@ -58,7 +58,7 @@ index 4d3093b..7f0c573 100644 /* The feature bitmap for virtio rpmsg */ #define VIRTIO_RPMSG_F_NS 0 /* RP supports name service notifications */ #define VIRTIO_RPMSG_F_ACK 1 /* RP supports name service acknowledge */ -+#define VIRTIO_RPMSG_F_BUFSZ 2 /* RP supports get buffer size from config space */ ++#define VIRTIO_RPMSG_F_BUFSZ 2 /* RP supports buffer size negotiation */ /** * struct rpmsg_virtio_shm_pool - shared memory pool used for rpmsg buffers @@ -79,21 +79,21 @@ index 4d3093b..7f0c573 100644 struct virtqueue *rvq; struct virtqueue *svq; diff --git a/lib/rpmsg/rpmsg_virtio.c open-amp/lib/rpmsg/rpmsg_virtio.c -index 9988a1e..d127084 100644 +index 640240a..164dc70 100644 --- a/lib/rpmsg/rpmsg_virtio.c +++ open-amp/lib/rpmsg/rpmsg_virtio.c -@@ -138,8 +138,8 @@ static void *rpmsg_virtio_get_tx_buffer(struct rpmsg_virtio_device *rvdev, +@@ -145,8 +145,8 @@ static void *rpmsg_virtio_get_tx_buffer(struct rpmsg_virtio_device *rvdev, data = virtqueue_get_buffer(rvdev->svq, len, idx); - if (!data) { + if (!data && rvdev->svq->vq_free_cnt) { data = rpmsg_virtio_shm_pool_get_buffer(rvdev->shpool, - RPMSG_BUFFER_SIZE); - *len = RPMSG_BUFFER_SIZE; -+ rvdev->config.rxbuf_size); ++ rvdev->config.rxbuf_size); + *len = rvdev->config.rxbuf_size; *idx = 0; } } -@@ -232,7 +232,7 @@ static int _rpmsg_virtio_get_buffer_size(struct rpmsg_virtio_device *rvdev) +@@ -239,7 +239,7 @@ static int _rpmsg_virtio_get_buffer_size(struct rpmsg_virtio_device *rvdev) * If device role is Master then buffers are provided by us, * so just provide the macro. */ @@ -102,22 +102,16 @@ index 9988a1e..d127084 100644 } #endif /*!VIRTIO_SLAVE_ONLY*/ -@@ -649,11 +649,14 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, +@@ -619,6 +619,8 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, rvdev->vdev = vdev; rdev->ns_bind_cb = ns_bind_cb; vdev->priv = rvdev; + rvdev->config.txbuf_size = RPMSG_BUFFER_SIZE; + rvdev->config.rxbuf_size = RPMSG_BUFFER_SIZE; + rdev->ops.send_offchannel_raw = rpmsg_virtio_send_offchannel_raw; rdev->ops.hold_rx_buffer = rpmsg_virtio_hold_rx_buffer; rdev->ops.release_rx_buffer = rpmsg_virtio_release_rx_buffer; - rdev->ops.get_tx_payload_buffer = rpmsg_virtio_get_tx_payload_buffer; - rdev->ops.send_offchannel_nocopy = rpmsg_virtio_send_offchannel_nocopy; - rdev->ops.send_offchannel_raw = rpmsg_virtio_send_offchannel_raw; -+ - role = rpmsg_virtio_get_role(rvdev); - - #ifndef VIRTIO_MASTER_ONLY -@@ -666,6 +669,13 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, +@@ -636,6 +638,13 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, rdev->support_ns = !!(vdev->features & (1 << VIRTIO_RPMSG_F_NS)); rdev->support_ack = !!(vdev->features & (1 << VIRTIO_RPMSG_F_ACK)); @@ -131,7 +125,7 @@ index 9988a1e..d127084 100644 #ifndef VIRTIO_SLAVE_ONLY if (role == RPMSG_MASTER) { /* -@@ -726,11 +736,11 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, +@@ -696,11 +705,11 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, unsigned int idx; void *buffer; @@ -145,7 +139,7 @@ index 9988a1e..d127084 100644 if (!buffer) { return RPMSG_ERR_NO_BUFF; -@@ -741,7 +751,7 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, +@@ -711,7 +720,7 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, metal_io_block_set(shm_io, metal_io_virt_to_offset(shm_io, buffer), diff --git a/openamp/0002-rpmsg-merge-rpmsg_register_endpoint-into-rpmsg_init_.patch b/openamp/0002-rpmsg-merge-rpmsg_register_endpoint-into-rpmsg_init_.patch deleted file mode 100644 index 791efdc144e..00000000000 --- a/openamp/0002-rpmsg-merge-rpmsg_register_endpoint-into-rpmsg_init_.patch +++ /dev/null @@ -1,128 +0,0 @@ -From d58fa6ab189fded40786e7d025036a1c16c773c4 Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Fri, 24 Apr 2020 03:40:56 +0800 -Subject: [PATCH 02/10] rpmsg: merge rpmsg_register_endpoint into - rpmsg_init_ept - -so the service which use preserved address could call rpmsg_init_ept - -Signed-off-by: Xiang Xiao ---- - lib/include/openamp/rpmsg.h | 19 +++++++------------ - lib/rpmsg/rpmsg.c | 17 +++++++++++++---- - lib/rpmsg/rpmsg_internal.h | 2 -- - lib/rpmsg/rpmsg_virtio.c | 3 +-- - 4 files changed, 21 insertions(+), 20 deletions(-) - -diff --git a/lib/include/openamp/rpmsg.h open-amp/lib/include/openamp/rpmsg.h -index 8401c38..a08f9d3 100644 ---- a/lib/include/openamp/rpmsg.h -+++ open-amp/lib/include/openamp/rpmsg.h -@@ -271,6 +271,7 @@ static inline int rpmsg_trysend_offchannel(struct rpmsg_endpoint *ept, - * remoteproc address, endpoint callback, and destroy endpoint callback. - * - * @ept: pointer to rpmsg endpoint -+ * @rdev: pointer to the rpmsg device - * @name: service name associated to the endpoint - * @src: local address of the endpoint - * @dest: target address of the endpoint -@@ -278,18 +279,12 @@ static inline int rpmsg_trysend_offchannel(struct rpmsg_endpoint *ept, - * @ns_unbind_cb: end point service unbind callback, called when remote ept is - * destroyed. - */ --static inline void rpmsg_init_ept(struct rpmsg_endpoint *ept, -- const char *name, -- uint32_t src, uint32_t dest, -- rpmsg_ept_cb cb, -- rpmsg_ns_unbind_cb ns_unbind_cb) --{ -- strncpy(ept->name, name ? name : "", sizeof(ept->name)); -- ept->addr = src; -- ept->dest_addr = dest; -- ept->cb = cb; -- ept->ns_unbind_cb = ns_unbind_cb; --} -+void rpmsg_init_ept(struct rpmsg_endpoint *ept, -+ struct rpmsg_device *rdev, -+ const char *name, -+ uint32_t src, uint32_t dest, -+ rpmsg_ept_cb cb, -+ rpmsg_ns_unbind_cb ns_unbind_cb); - - /** - * rpmsg_create_ept - create rpmsg endpoint and register it to rpmsg device -diff --git a/lib/rpmsg/rpmsg.c open-amp/lib/rpmsg/rpmsg.c -index 5b9c735..eee1c28 100644 ---- a/lib/rpmsg/rpmsg.c -+++ open-amp/lib/rpmsg/rpmsg.c -@@ -182,6 +182,7 @@ static void rpmsg_unregister_endpoint(struct rpmsg_endpoint *ept) - return; - - rdev = ept->rdev; -+ ept->rdev = NULL; - - if (ept->addr != RPMSG_ADDR_ANY) - rpmsg_release_address(rdev->bitmap, RPMSG_ADDR_BMP_SIZE, -@@ -189,9 +190,18 @@ static void rpmsg_unregister_endpoint(struct rpmsg_endpoint *ept) - metal_list_del(&ept->node); - } - --void rpmsg_register_endpoint(struct rpmsg_device *rdev, -- struct rpmsg_endpoint *ept) -+void rpmsg_init_ept(struct rpmsg_endpoint *ept, -+ struct rpmsg_device *rdev, -+ const char *name, -+ uint32_t src, uint32_t dest, -+ rpmsg_ept_cb cb, -+ rpmsg_ns_unbind_cb ns_unbind_cb) - { -+ strncpy(ept->name, name ? name : "", sizeof(ept->name)); -+ ept->addr = src; -+ ept->dest_addr = dest; -+ ept->cb = cb; -+ ept->ns_unbind_cb = ns_unbind_cb; - ept->rdev = rdev; - metal_list_add_tail(&rdev->endpoints, &ept->node); - } -@@ -224,8 +234,7 @@ int rpmsg_create_ept(struct rpmsg_endpoint *ept, struct rpmsg_device *rdev, - addr = rpmsg_get_address(rdev->bitmap, RPMSG_ADDR_BMP_SIZE); - } - -- rpmsg_init_ept(ept, name, addr, dest, cb, unbind_cb); -- rpmsg_register_endpoint(rdev, ept); -+ rpmsg_init_ept(ept, rdev, name, addr, dest, cb, unbind_cb); - - if (rdev->support_ns && ept->dest_addr == RPMSG_ADDR_ANY) { - /* Send NS announcement to remote processor */ -diff --git a/lib/rpmsg/rpmsg_internal.h open-amp/lib/rpmsg/rpmsg_internal.h -index f63c958..9c46970 100644 ---- a/lib/rpmsg/rpmsg_internal.h -+++ open-amp/lib/rpmsg/rpmsg_internal.h -@@ -92,8 +92,6 @@ int rpmsg_send_ns_message(struct rpmsg_endpoint *ept, unsigned long flags); - struct rpmsg_endpoint *rpmsg_get_endpoint(struct rpmsg_device *rvdev, - const char *name, uint32_t addr, - uint32_t dest_addr); --void rpmsg_register_endpoint(struct rpmsg_device *rdev, -- struct rpmsg_endpoint *ept); - - static inline struct rpmsg_endpoint * - rpmsg_get_ept_from_addr(struct rpmsg_device *rdev, uint32_t addr) -diff --git a/lib/rpmsg/rpmsg_virtio.c open-amp/lib/rpmsg/rpmsg_virtio.c -index 8165216..4dea4c0 100644 ---- a/lib/rpmsg/rpmsg_virtio.c -+++ open-amp/lib/rpmsg/rpmsg_virtio.c -@@ -636,10 +636,9 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, - * service announcement feature. - */ - if (rdev->support_ns) { -- rpmsg_init_ept(&rdev->ns_ept, "NS", -+ rpmsg_init_ept(&rdev->ns_ept, rdev, "NS", - RPMSG_NS_EPT_ADDR, RPMSG_NS_EPT_ADDR, - rpmsg_virtio_ns_callback, NULL); -- rpmsg_register_endpoint(rdev, &rdev->ns_ept); - } - - #ifndef VIRTIO_SLAVE_ONLY --- -2.17.1 - diff --git a/openamp/0003-rpmsg-shouldn-t-allocate-0-1023-address-in-rpmsg_cre.patch b/openamp/0003-rpmsg-shouldn-t-allocate-0-1023-address-in-rpmsg_cre.patch deleted file mode 100644 index b425fa33790..00000000000 --- a/openamp/0003-rpmsg-shouldn-t-allocate-0-1023-address-in-rpmsg_cre.patch +++ /dev/null @@ -1,227 +0,0 @@ -From ca34df45f5d4893be223346b06cc75f370452386 Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Fri, 24 Apr 2020 01:33:12 +0800 -Subject: [PATCH 03/10] rpmsg: shouldn't allocate 0-1023 address in - rpmsg_create_ept - -since this region is reserved for predefined services(e.g. NS use 0x35) - -Signed-off-by: Xiang Xiao ---- - apps/examples/echo/rpmsg-echo.c | 2 +- - apps/examples/echo/rpmsg-ping.c | 2 +- - .../matrix_multiply/matrix_multiply.c | 2 +- - .../matrix_multiply/matrix_multiplyd.c | 2 +- - apps/examples/rpc_demo/rpc_demod.c | 2 +- - .../rpmsg_sample_echo/rpmsg-sample-ping.c | 2 +- - apps/tests/msg/rpmsg-flood-ping.c | 2 +- - apps/tests/msg/rpmsg-ping.c | 2 +- - apps/tests/msg/rpmsg-update.c | 2 +- - lib/include/openamp/rpmsg.h | 27 ++++++++++--------- - lib/rpmsg/rpmsg.c | 11 +++++--- - 11 files changed, 30 insertions(+), 26 deletions(-) - -diff --git a/apps/examples/echo/rpmsg-echo.c open-amp/apps/examples/echo/rpmsg-echo.c -index 0c75203..71a0bbf 100644 ---- a/apps/examples/echo/rpmsg-echo.c -+++ open-amp/apps/examples/echo/rpmsg-echo.c -@@ -58,7 +58,7 @@ int app(struct rpmsg_device *rdev, void *priv) - LPRINTF("Try to create rpmsg endpoint.\r\n"); - - ret = rpmsg_create_ept(&lept, rdev, RPMSG_SERVICE_NAME, -- 0, RPMSG_ADDR_ANY, rpmsg_endpoint_cb, -+ 1024, RPMSG_ADDR_ANY, rpmsg_endpoint_cb, - rpmsg_service_unbind); - if (ret) { - LPERROR("Failed to create endpoint.\r\n"); -diff --git a/apps/examples/echo/rpmsg-ping.c open-amp/apps/examples/echo/rpmsg-ping.c -index 3b716b0..ff639cd 100644 ---- a/apps/examples/echo/rpmsg-ping.c -+++ open-amp/apps/examples/echo/rpmsg-ping.c -@@ -11,7 +11,7 @@ This application echoes back data that was sent to it by the master core. */ - #include "platform_info.h" - #include "rpmsg-echo.h" - --#define APP_EPT_ADDR 0 -+#define APP_EPT_ADDR 1024 - #define LPRINTF(format, ...) printf(format, ##__VA_ARGS__) - #define LPERROR(format, ...) LPRINTF("ERROR: " format, ##__VA_ARGS__) - -diff --git a/apps/examples/matrix_multiply/matrix_multiply.c open-amp/apps/examples/matrix_multiply/matrix_multiply.c -index b9da29b..3928088 100644 ---- a/apps/examples/matrix_multiply/matrix_multiply.c -+++ open-amp/apps/examples/matrix_multiply/matrix_multiply.c -@@ -14,7 +14,7 @@ multiplies them and returns the result to the master core. */ - - #define MAX_SIZE 6 - #define NUM_MATRIX 2 --#define APP_EPT_ADDR 0 -+#define APP_EPT_ADDR 1024 - - #define raw_printf(format, ...) printf(format, ##__VA_ARGS__) - #define LPRINTF(format, ...) raw_printf("CLIENT> " format, ##__VA_ARGS__) -diff --git a/apps/examples/matrix_multiply/matrix_multiplyd.c open-amp/apps/examples/matrix_multiply/matrix_multiplyd.c -index 6b4a118..29c6380 100644 ---- a/apps/examples/matrix_multiply/matrix_multiplyd.c -+++ open-amp/apps/examples/matrix_multiply/matrix_multiplyd.c -@@ -92,7 +92,7 @@ int app(struct rpmsg_device *rdev, void *priv) - int ret; - - ret = rpmsg_create_ept(&lept, rdev, RPMSG_SERVICE_NAME, -- 0, RPMSG_ADDR_ANY, rpmsg_endpoint_cb, -+ 1024, RPMSG_ADDR_ANY, rpmsg_endpoint_cb, - rpmsg_service_unbind); - if (ret) { - LPERROR("Failed to create endpoint.\r\n"); -diff --git a/apps/examples/rpc_demo/rpc_demod.c open-amp/apps/examples/rpc_demo/rpc_demod.c -index 44c92a2..a4659f3 100644 ---- a/apps/examples/rpc_demo/rpc_demod.c -+++ open-amp/apps/examples/rpc_demo/rpc_demod.c -@@ -312,7 +312,7 @@ int app(struct rpmsg_device *rdev, void *priv) - LPRINTF("Try to create rpmsg endpoint.\r\n"); - - ret = rpmsg_create_ept(&app_ept, rdev, RPMSG_SERVICE_NAME, -- 0, RPMSG_ADDR_ANY, rpmsg_endpoint_cb, -+ 1024, RPMSG_ADDR_ANY, rpmsg_endpoint_cb, - rpmsg_service_unbind); - if (ret) { - LPERROR("Failed to create endpoint.\r\n"); -diff --git a/apps/examples/rpmsg_sample_echo/rpmsg-sample-ping.c open-amp/apps/examples/rpmsg_sample_echo/rpmsg-sample-ping.c -index ee866b4..14456e3 100644 ---- a/apps/examples/rpmsg_sample_echo/rpmsg-sample-ping.c -+++ open-amp/apps/examples/rpmsg_sample_echo/rpmsg-sample-ping.c -@@ -20,7 +20,7 @@ - #define BYE_MSG "goodbye!" - #define MSG_LIMIT 100 - --#define APP_EPT_ADDR 0 -+#define APP_EPT_ADDR 1024 - #define LPRINTF(format, ...) printf(format, ##__VA_ARGS__) - #define LPERROR(format, ...) LPRINTF("ERROR: " format, ##__VA_ARGS__) - -diff --git a/apps/tests/msg/rpmsg-flood-ping.c open-amp/apps/tests/msg/rpmsg-flood-ping.c -index 66489f8..28edc66 100644 ---- a/apps/tests/msg/rpmsg-flood-ping.c -+++ open-amp/apps/tests/msg/rpmsg-flood-ping.c -@@ -12,7 +12,7 @@ - #include "platform_info.h" - #include "rpmsg-ping.h" - --#define APP_EPT_ADDR 0 -+#define APP_EPT_ADDR 1024 - #define LPRINTF(format, ...) printf(format, ##__VA_ARGS__) - #define LPERROR(format, ...) LPRINTF("ERROR: " format, ##__VA_ARGS__) - -diff --git a/apps/tests/msg/rpmsg-ping.c open-amp/apps/tests/msg/rpmsg-ping.c -index 0220a27..752b16c 100644 ---- a/apps/tests/msg/rpmsg-ping.c -+++ open-amp/apps/tests/msg/rpmsg-ping.c -@@ -11,7 +11,7 @@ This application echoes back data that was sent to it by the master core. */ - #include "platform_info.h" - #include "rpmsg-ping.h" - --#define APP_EPT_ADDR 0 -+#define APP_EPT_ADDR 1024 - #define LPRINTF(format, ...) printf(format, ##__VA_ARGS__) - #define LPERROR(format, ...) LPRINTF("ERROR: " format, ##__VA_ARGS__) - -diff --git a/apps/tests/msg/rpmsg-update.c open-amp/apps/tests/msg/rpmsg-update.c -index 9b26cac..b8e08db 100644 ---- a/apps/tests/msg/rpmsg-update.c -+++ open-amp/apps/tests/msg/rpmsg-update.c -@@ -73,7 +73,7 @@ int app(struct rpmsg_device *rdev, void *priv) - LPRINTF("Try to create rpmsg endpoint.\r\n"); - - ret = rpmsg_create_ept(&lept, rdev, RPMSG_SERVICE_NAME, -- 0, RPMSG_ADDR_ANY, rpmsg_endpoint_cb, -+ 1024, RPMSG_ADDR_ANY, rpmsg_endpoint_cb, - rpmsg_service_unbind); - if (ret) { - LPERROR("Failed to create endpoint.\r\n"); -diff --git a/lib/include/openamp/rpmsg.h open-amp/lib/include/openamp/rpmsg.h -index a08f9d3..3403240 100644 ---- a/lib/include/openamp/rpmsg.h -+++ open-amp/lib/include/openamp/rpmsg.h -@@ -25,22 +25,23 @@ extern "C" { - #endif - - /* Configurable parameters */ --#define RPMSG_NAME_SIZE (32) --#define RPMSG_ADDR_BMP_SIZE (128) -+#define RPMSG_NAME_SIZE (32) -+#define RPMSG_ADDR_BMP_SIZE (128) - --#define RPMSG_NS_EPT_ADDR (0x35) --#define RPMSG_ADDR_ANY 0xFFFFFFFF -+#define RPMSG_NS_EPT_ADDR (0x35) -+#define RPMSG_RESERVED_ADDRESSES (1024) -+#define RPMSG_ADDR_ANY 0xFFFFFFFF - - /* Error macros. */ --#define RPMSG_SUCCESS 0 --#define RPMSG_ERROR_BASE -2000 --#define RPMSG_ERR_NO_MEM (RPMSG_ERROR_BASE - 1) --#define RPMSG_ERR_NO_BUFF (RPMSG_ERROR_BASE - 2) --#define RPMSG_ERR_PARAM (RPMSG_ERROR_BASE - 3) --#define RPMSG_ERR_DEV_STATE (RPMSG_ERROR_BASE - 4) --#define RPMSG_ERR_BUFF_SIZE (RPMSG_ERROR_BASE - 5) --#define RPMSG_ERR_INIT (RPMSG_ERROR_BASE - 6) --#define RPMSG_ERR_ADDR (RPMSG_ERROR_BASE - 7) -+#define RPMSG_SUCCESS 0 -+#define RPMSG_ERROR_BASE -2000 -+#define RPMSG_ERR_NO_MEM (RPMSG_ERROR_BASE - 1) -+#define RPMSG_ERR_NO_BUFF (RPMSG_ERROR_BASE - 2) -+#define RPMSG_ERR_PARAM (RPMSG_ERROR_BASE - 3) -+#define RPMSG_ERR_DEV_STATE (RPMSG_ERROR_BASE - 4) -+#define RPMSG_ERR_BUFF_SIZE (RPMSG_ERROR_BASE - 5) -+#define RPMSG_ERR_INIT (RPMSG_ERROR_BASE - 6) -+#define RPMSG_ERR_ADDR (RPMSG_ERROR_BASE - 7) - - struct rpmsg_endpoint; - struct rpmsg_device; -diff --git a/lib/rpmsg/rpmsg.c open-amp/lib/rpmsg/rpmsg.c -index eee1c28..dcc39c1 100644 ---- a/lib/rpmsg/rpmsg.c -+++ open-amp/lib/rpmsg/rpmsg.c -@@ -29,7 +29,7 @@ static uint32_t rpmsg_get_address(unsigned long *bitmap, int size) - - nextbit = metal_bitmap_next_clear_bit(bitmap, 0, size); - if (nextbit < (uint32_t)size) { -- addr = nextbit; -+ addr = RPMSG_RESERVED_ADDRESSES + nextbit; - metal_bitmap_set_bit(bitmap, nextbit); - } - -@@ -48,7 +48,8 @@ static uint32_t rpmsg_get_address(unsigned long *bitmap, int size) - static void rpmsg_release_address(unsigned long *bitmap, int size, - int addr) - { -- if (addr < size) -+ addr -= RPMSG_RESERVED_ADDRESSES; -+ if (addr >= 0 && addr < size) - metal_bitmap_clear_bit(bitmap, addr); - } - -@@ -65,7 +66,8 @@ static void rpmsg_release_address(unsigned long *bitmap, int size, - */ - static int rpmsg_is_address_set(unsigned long *bitmap, int size, int addr) - { -- if (addr < size) -+ addr -= RPMSG_RESERVED_ADDRESSES; -+ if (addr >= 0 && addr < size) - return metal_bitmap_is_bit_set(bitmap, addr); - else - return RPMSG_ERR_PARAM; -@@ -84,7 +86,8 @@ static int rpmsg_is_address_set(unsigned long *bitmap, int size, int addr) - */ - static int rpmsg_set_address(unsigned long *bitmap, int size, int addr) - { -- if (addr < size) { -+ addr -= RPMSG_RESERVED_ADDRESSES; -+ if (addr >= 0 && addr < size) { - metal_bitmap_set_bit(bitmap, addr); - return RPMSG_SUCCESS; - } else { --- -2.17.1 - diff --git a/openamp/0004-rpmsg-wait-ept-ready-in-rpmsg_send.patch b/openamp/0003-rpmsg-wait-endpoint-ready-in-rpmsg_send-and-rpmsg_se.patch similarity index 66% rename from openamp/0004-rpmsg-wait-ept-ready-in-rpmsg_send.patch rename to openamp/0003-rpmsg-wait-endpoint-ready-in-rpmsg_send-and-rpmsg_se.patch index df72f2ff331..673a319e663 100644 --- a/openamp/0004-rpmsg-wait-ept-ready-in-rpmsg_send.patch +++ b/openamp/0003-rpmsg-wait-endpoint-ready-in-rpmsg_send-and-rpmsg_se.patch @@ -1,18 +1,19 @@ -From 8a55f0f3c2fec8c817ad579b070040ee8058c536 Mon Sep 17 00:00:00 2001 -From: ligd +From b84c7f48996a9bbacdddcef9929405f674a73a81 Mon Sep 17 00:00:00 2001 +From: Guiding Li Date: Wed, 20 Feb 2019 11:36:57 +0800 -Subject: [PATCH 04/10] rpmsg: wait ept ready in rpmsg_send +Subject: [PATCH 3/3] rpmsg: wait endpoint ready in rpmsg_send and + rpmsg_send_nocopy -since the destination address need time to return from peer +because the remote need time to return the destination address -Signed-off-by: ligd +Signed-off-by: Guiding Li --- - lib/include/openamp/rpmsg.h | 48 ++++++++++++++++++++++++------------- - lib/rpmsg/rpmsg_virtio.c | 7 ------ - 2 files changed, 32 insertions(+), 23 deletions(-) + lib/include/openamp/rpmsg.h | 59 ++++++++++++++++++++++++++----------- + lib/rpmsg/rpmsg_virtio.c | 7 ----- + 2 files changed, 42 insertions(+), 24 deletions(-) diff --git a/lib/include/openamp/rpmsg.h open-amp/lib/include/openamp/rpmsg.h -index 3403240..7000453 100644 +index efdfb2b..5c8b45c 100644 --- a/lib/include/openamp/rpmsg.h +++ open-amp/lib/include/openamp/rpmsg.h @@ -15,6 +15,7 @@ @@ -36,8 +37,8 @@ index 3403240..7000453 100644 /* Error macros. */ #define RPMSG_SUCCESS 0 #define RPMSG_ERROR_BASE -2000 -@@ -129,6 +136,20 @@ int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src, - uint32_t dst, const void *data, int size, +@@ -141,6 +148,19 @@ int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src, + uint32_t dst, const void *data, int len, int wait); +/** @@ -50,14 +51,13 @@ index 3403240..7000453 100644 + */ +static inline unsigned int is_rpmsg_ept_ready(struct rpmsg_endpoint *ept) +{ -+ return (ept->dest_addr != RPMSG_ADDR_ANY) && -+ (ept->addr != RPMSG_ADDR_ANY); ++ return ept && ept->rdev && ept->dest_addr != RPMSG_ADDR_ANY; +} + /** * rpmsg_send() - send a message across to the remote processor * @ept: the rpmsg endpoint -@@ -147,8 +168,17 @@ int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src, +@@ -159,8 +179,17 @@ int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src, static inline int rpmsg_send(struct rpmsg_endpoint *ept, const void *data, int len) { @@ -77,7 +77,27 @@ index 3403240..7000453 100644 } /** -@@ -328,20 +358,6 @@ int rpmsg_create_ept(struct rpmsg_endpoint *ept, struct rpmsg_device *rdev, +@@ -433,8 +462,17 @@ static inline int rpmsg_sendto_nocopy(struct rpmsg_endpoint *ept, + static inline int rpmsg_send_nocopy(struct rpmsg_endpoint *ept, + const void *data, int len) + { +- return rpmsg_send_offchannel_nocopy(ept, ept->addr, +- ept->dest_addr, data, len); ++ int tc = 0; ++ ++ for (; tc < RPMSG_TICK_COUNT; tc += RPMSG_TICKS_PER_INTERVAL) { ++ if (is_rpmsg_ept_ready(ept)) ++ return rpmsg_send_offchannel_nocopy(ept, ept->addr, ++ ept->dest_addr, ++ data, len); ++ metal_sleep_usec(RPMSG_TICKS_PER_INTERVAL); ++ } ++ ++ return RPMSG_ERR_ADDR; + } + + /** +@@ -507,19 +545,6 @@ int rpmsg_create_ept(struct rpmsg_endpoint *ept, struct rpmsg_device *rdev, */ void rpmsg_destroy_ept(struct rpmsg_endpoint *ept); @@ -91,15 +111,14 @@ index 3403240..7000453 100644 - */ -static inline unsigned int is_rpmsg_ept_ready(struct rpmsg_endpoint *ept) -{ -- return (ept->dest_addr != RPMSG_ADDR_ANY) && -- (ept->addr != RPMSG_ADDR_ANY); +- return ept && ept->rdev && ept->dest_addr != RPMSG_ADDR_ANY; -} - #if defined __cplusplus } #endif diff --git a/lib/rpmsg/rpmsg_virtio.c open-amp/lib/rpmsg/rpmsg_virtio.c -index 4dea4c0..44b46d4 100644 +index 164dc70..c357ba8 100644 --- a/lib/rpmsg/rpmsg_virtio.c +++ open-amp/lib/rpmsg/rpmsg_virtio.c @@ -8,7 +8,6 @@ diff --git a/openamp/0005-rpmsg-return-fail-if-either-source-or-destination-ad.patch b/openamp/0005-rpmsg-return-fail-if-either-source-or-destination-ad.patch deleted file mode 100644 index fbf9cdfb8f9..00000000000 --- a/openamp/0005-rpmsg-return-fail-if-either-source-or-destination-ad.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 3ea6f30819b25281ec80c68b3abd779981311a77 Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Fri, 24 Apr 2020 02:22:15 +0800 -Subject: [PATCH 05/10] rpmsg: return fail if either source or destination - address is zero - -to help detect rpmsg_send is called before the endpoint -initialization or after the endpoint uninitialization - -Signed-off-by: Xiang Xiao ---- - lib/include/openamp/rpmsg.h | 3 +-- - lib/rpmsg/rpmsg.c | 2 +- - 2 files changed, 2 insertions(+), 3 deletions(-) - -diff --git a/lib/include/openamp/rpmsg.h open-amp/lib/include/openamp/rpmsg.h -index 7000453..1279ea2 100644 ---- a/lib/include/openamp/rpmsg.h -+++ open-amp/lib/include/openamp/rpmsg.h -@@ -146,8 +146,7 @@ int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src, - */ - static inline unsigned int is_rpmsg_ept_ready(struct rpmsg_endpoint *ept) - { -- return (ept->dest_addr != RPMSG_ADDR_ANY) && -- (ept->addr != RPMSG_ADDR_ANY); -+ return ept && ept->rdev && ept->dest_addr && ept->dest_addr != RPMSG_ADDR_ANY; - } - - /** -diff --git a/lib/rpmsg/rpmsg.c open-amp/lib/rpmsg/rpmsg.c -index dcc39c1..9da38a1 100644 ---- a/lib/rpmsg/rpmsg.c -+++ open-amp/lib/rpmsg/rpmsg.c -@@ -115,7 +115,7 @@ int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src, - { - struct rpmsg_device *rdev; - -- if (!ept || !ept->rdev || !data || dst == RPMSG_ADDR_ANY) -+ if (!ept || !ept->rdev || !data || !dst || dst == RPMSG_ADDR_ANY) - return RPMSG_ERR_PARAM; - - rdev = ept->rdev; --- -2.17.1 - diff --git a/openamp/0006-remoteproc_mmap-support-va-to-pa-da-conversion.patch b/openamp/0006-remoteproc_mmap-support-va-to-pa-da-conversion.patch deleted file mode 100644 index 3c915e825d1..00000000000 --- a/openamp/0006-remoteproc_mmap-support-va-to-pa-da-conversion.patch +++ /dev/null @@ -1,780 +0,0 @@ -From 27026fc4c781a9dbd328059884b9b94ff39ad6b9 Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Fri, 15 Mar 2019 01:51:03 +0800 -Subject: [PATCH 06/10] remoteproc_mmap support va to pa/da conversion - -1.change va from output to input/output -2.remoteproc_get_io_xxx fallback to mmap callback - -Signed-off-by: Xiang Xiao ---- - .../load_fw/zynqmp_r5_lcm_rproc_example.c | 69 +++++------ - apps/machine/zynq7/platform_info.c | 16 +-- - apps/machine/zynq7/zynq_a9_rproc.c | 40 ++++--- - apps/machine/zynqmp/platform_info.c | 6 +- - apps/machine/zynqmp/zynqmp_linux_r5_proc.c | 40 ++++--- - apps/machine/zynqmp_r5/platform_info.c | 16 +-- - apps/machine/zynqmp_r5/zynqmp_r5_a53_rproc.c | 38 +++---- - .../linux/machine/generic/platform_info.c | 52 +++++---- - lib/include/openamp/remoteproc.h | 19 ++-- - lib/remoteproc/remoteproc.c | 107 ++++++++++-------- - lib/remoteproc/rsc_table_parser.c | 2 +- - 11 files changed, 209 insertions(+), 196 deletions(-) - -diff --git a/apps/examples/load_fw/zynqmp_r5_lcm_rproc_example.c open-amp/apps/examples/load_fw/zynqmp_r5_lcm_rproc_example.c -index 26a09e5..e224631 100644 ---- a/apps/examples/load_fw/zynqmp_r5_lcm_rproc_example.c -+++ open-amp/apps/examples/load_fw/zynqmp_r5_lcm_rproc_example.c -@@ -137,86 +137,79 @@ void r5_rproc_remove(struct remoteproc *rproc) - } - } - --void *r5_rproc_mmap(struct remoteproc *rproc, -- metal_phys_addr_t *pa, metal_phys_addr_t *da, -- size_t size, unsigned int attribute, -- struct metal_io_region **io) -+int r5_rproc_mmap(struct remoteproc *rproc, -+ metal_phys_addr_t *pa, metal_phys_addr_t *da, -+ void **va, size_t size, unsigned int attribute, -+ struct metal_io_region **io) - { - struct remoteproc_mem *mem; -+ struct metal_io_region *tmpio; - struct r5_rproc_priv *priv; -- metal_phys_addr_t lpa, lda; - - priv = rproc->priv; - -- if (!da || !pa) -- return NULL; - LPRINTF("%s: pa=0x%x, da=0x%x, size=0x%x, atrribute=0x%x\r\n", - __func__, *pa, *da, size, attribute); -- lda = *da; -- lpa = *pa; - if (!attribute) - attribute = NORM_SHARED_NCACHE | PRIV_RW_USER_RW; -- if (lda <= 0x40000) { -+ if (*da <= 0x40000) { - metal_phys_addr_t lda_end; - -- lda_end = lda + size; -+ lda_end = *da + size; - if (priv->cpu_id == NODE_RPU_0 || priv->cpu_id == NODE_RPU) { -- lpa = 0xFFE00000 + lda; -- if (lda < 0x10000) -+ *pa = 0xFFE00000 + *da; -+ if (*da < 0x10000) - XPm_RequestNode(NODE_TCM_0_A, - PM_CAP_ACCESS, 0, - REQUEST_ACK_BLOCKING); -- if (lda <= 0x20000 && lda_end >= 0x10000) -+ if (*da <= 0x20000 && lda_end >= 0x10000) - XPm_RequestNode(NODE_TCM_1_A, - PM_CAP_ACCESS, 0, - REQUEST_ACK_BLOCKING); -- if (lda <= 0x30000 && lda_end >= 0x20000) -+ if (*da <= 0x30000 && lda_end >= 0x20000) - XPm_RequestNode(NODE_TCM_0_B, - PM_CAP_ACCESS, 0, - REQUEST_ACK_BLOCKING); -- if (lda <= 0x40000 && lda_end >= 0x30000) -+ if (*da <= 0x40000 && lda_end >= 0x30000) - XPm_RequestNode(NODE_TCM_1_B, - PM_CAP_ACCESS, 0, - REQUEST_ACK_BLOCKING); - } else if (priv->cpu_id == NODE_RPU_1) { -- lpa = 0xFFE90000 + lda; -- if (lda < 0x10000) -+ *pa = 0xFFE90000 + *da; -+ if (*da < 0x10000) - XPm_RequestNode(NODE_TCM_1_A, - PM_CAP_ACCESS, 0, - REQUEST_ACK_BLOCKING); -- if (lda <= 0x30000 && lda_end >= 0x20000) -+ if (*da <= 0x30000 && lda_end >= 0x20000) - XPm_RequestNode(NODE_TCM_1_B, - PM_CAP_ACCESS, 0, - REQUEST_ACK_BLOCKING); - } else { - LPERROR("mmap failed: invalid cpu node: %d\r\n", - priv->cpu_id); -- return NULL; -+ return -RPROC_EINVAL; - } - } -- if (lpa == METAL_BAD_PHYS) -- lpa = lda; -- if (lpa == METAL_BAD_PHYS) -- return NULL; -+ if (*pa == METAL_BAD_PHYS) -+ *pa = *da; -+ if (*pa == METAL_BAD_PHYS) -+ return -RPROC_EINVAL; - mem = metal_allocate_memory(sizeof(*mem)); - if (!mem) -- return NULL; -- mem->pa = lpa; -- mem->da = lda; -- -- *io = metal_allocate_memory(sizeof(struct metal_io_region)); -- if (!*io) { -+ return -RPROC_ENOMEM; -+ tmpio = metal_allocate_memory(sizeof(struct metal_io_region)); -+ if (!tmpio) { - metal_free_memory(mem); -- return NULL; -+ return -RPROC_ENOMEM; - } -- metal_io_init(*io, (void *)mem->pa, &mem->pa, size, -+ remoteproc_init_mem(mem, NULL, *pa, *da, size, tmpio); -+ metal_io_init(tmpio, (void *)mem->pa, &mem->pa, size, - sizeof(metal_phys_addr_t)<<3, attribute, NULL); -- mem->io = *io; -- metal_list_add_tail(&rproc->mems, &mem->node); -- *pa = lpa; -- *da = lda; -- mem->size = size; -- return metal_io_phys_to_virt(*io, mem->pa); -+ remoteproc_add_mem(rproc, mem); -+ *va = metal_io_phys_to_virt(tmpio, mem->pa); -+ if (io) -+ *io = tmpio; -+ return 0; - } - - int r5_rproc_start(struct remoteproc *rproc) -diff --git a/apps/machine/zynq7/platform_info.c open-amp/apps/machine/zynq7/platform_info.c -index d753e0e..7885b31 100644 ---- a/apps/machine/zynq7/platform_info.c -+++ open-amp/apps/machine/zynq7/platform_info.c -@@ -108,16 +108,16 @@ platform_create_proc(int proc_index, int rsc_index) - */ - /* mmap resource table */ - pa = (metal_phys_addr_t)rsc_table; -- (void *)remoteproc_mmap(&rproc_inst, &pa, -- NULL, rsc_size, -- NORM_NONCACHE | STRONG_ORDERED, -- &rproc_inst.rsc_io); -+ remoteproc_mmap(&rproc_inst, &pa, -+ NULL, NULL, rsc_size, -+ NORM_NONCACHE | STRONG_ORDERED, -+ &rproc_inst.rsc_io); - /* mmap shared memory */ - pa = SHARED_MEM_PA; -- (void *)remoteproc_mmap(&rproc_inst, &pa, -- NULL, SHARED_MEM_SIZE, -- NORM_NONCACHE | STRONG_ORDERED, -- NULL); -+ remoteproc_mmap(&rproc_inst, &pa, -+ NULL, NULL, SHARED_MEM_SIZE, -+ NORM_NONCACHE | STRONG_ORDERED, -+ NULL); - - /* parse resource table to remoteproc */ - ret = remoteproc_set_rsc_table(&rproc_inst, rsc_table, rsc_size); -diff --git a/apps/machine/zynq7/zynq_a9_rproc.c open-amp/apps/machine/zynq7/zynq_a9_rproc.c -index f830749..ad7cd49 100644 ---- a/apps/machine/zynq7/zynq_a9_rproc.c -+++ open-amp/apps/machine/zynq7/zynq_a9_rproc.c -@@ -94,45 +94,43 @@ static void zynq_a9_proc_remove(struct remoteproc *rproc) - metal_device_close(dev); - } - --static void * -+static int - zynq_a9_proc_mmap(struct remoteproc *rproc, metal_phys_addr_t *pa, -- metal_phys_addr_t *da, size_t size, -- unsigned int attribute, struct metal_io_region **io) -+ metal_phys_addr_t *da, void **va, size_t size, -+ unsigned int attribute, struct metal_io_region **io) - { - struct remoteproc_mem *mem; -- metal_phys_addr_t lpa, lda; - struct metal_io_region *tmpio; - -- lpa = *pa; -- lda = *da; -- -- if (lpa == METAL_BAD_PHYS && lda == METAL_BAD_PHYS) -- return NULL; -- if (lpa == METAL_BAD_PHYS) -- lpa = lda; -- if (lda == METAL_BAD_PHYS) -- lda = lpa; -+ /* va is the same as pa/da in this platform */ -+ if (*pa != METAL_BAD_PHYS) { -+ *da = *pa; -+ *va = (void *)*pa; -+ } else if (*da != METAL_BAD_PHYS) { -+ *pa = *da; -+ *va = (void *)*da; -+ } else if (*va) -+ *pa = *da = (metal_phys_addr_t)*va; -+ else -+ return -RPROC_EINVAL; - - if (!attribute) - attribute = NORM_NONCACHE | STRONG_ORDERED; - mem = metal_allocate_memory(sizeof(*mem)); - if (!mem) -- return NULL; -+ return -RPROC_ENOMEM; - tmpio = metal_allocate_memory(sizeof(*tmpio)); - if (!tmpio) { - metal_free_memory(mem); -- return NULL; -+ return -RPROC_ENOMEM; - } -- remoteproc_init_mem(mem, NULL, lpa, lda, size, tmpio); -- /* va is the same as pa in this platform */ -- metal_io_init(tmpio, (void *)lpa, &mem->pa, size, -+ remoteproc_init_mem(mem, NULL, *pa, *da, size, tmpio); -+ metal_io_init(tmpio, *va, &mem->pa, size, - sizeof(metal_phys_addr_t)<<3, attribute, NULL); - remoteproc_add_mem(rproc, mem); -- *pa = lpa; -- *da = lda; - if (io) - *io = tmpio; -- return metal_io_phys_to_virt(tmpio, mem->pa); -+ return 0; - } - - static int zynq_a9_proc_notify(struct remoteproc *rproc, uint32_t id) -diff --git a/apps/machine/zynqmp/platform_info.c open-amp/apps/machine/zynqmp/platform_info.c -index 3081ec9..17abcc5 100644 ---- a/apps/machine/zynqmp/platform_info.c -+++ open-amp/apps/machine/zynqmp/platform_info.c -@@ -84,7 +84,7 @@ static struct rpmsg_virtio_shm_pool shpool; - static struct remoteproc * - platform_create_proc(int proc_index, int rsc_index) - { -- void *rsc_table; -+ void *rsc_table = NULL; - int rsc_size; - int ret; - metal_phys_addr_t pa; -@@ -102,8 +102,8 @@ platform_create_proc(int proc_index, int rsc_index) - /* Mmap resource table */ - pa = RSC_MEM_PA; - printf("Calling mmap resource table.\r\n"); -- rsc_table = remoteproc_mmap(&rproc_inst, &pa, NULL, rsc_size, -- 0, NULL); -+ remoteproc_mmap(&rproc_inst, &pa, NULL, &rsc_table, rsc_size, -+ 0, NULL); - if (!rsc_table) { - fprintf(stderr, "ERROR: Failed to mmap resource table.\r\n"); - return NULL; -diff --git a/apps/machine/zynqmp/zynqmp_linux_r5_proc.c open-amp/apps/machine/zynqmp/zynqmp_linux_r5_proc.c -index 2e4df9d..0950d0b 100644 ---- a/apps/machine/zynqmp/zynqmp_linux_r5_proc.c -+++ open-amp/apps/machine/zynqmp/zynqmp_linux_r5_proc.c -@@ -143,38 +143,44 @@ static void zynqmp_linux_r5_proc_remove(struct remoteproc *rproc) - metal_device_close(prproc->shm_dev); - } - --static void * -+static int - zynqmp_linux_r5_proc_mmap(struct remoteproc *rproc, metal_phys_addr_t *pa, -- metal_phys_addr_t *da, size_t size, -- unsigned int attribute, struct metal_io_region **io) -+ metal_phys_addr_t *da, void **va, size_t size, -+ unsigned int attribute, struct metal_io_region **io) - { - struct remoteproc_priv *prproc; -- metal_phys_addr_t lpa, lda; - struct metal_io_region *tmpio; - - (void)attribute; - (void)size; - if (!rproc) -- return NULL; -+ return -RPROC_EINVAL; - prproc = rproc->priv; -- lpa = *pa; -- lda = *da; - -- if (lpa == METAL_BAD_PHYS && lda == METAL_BAD_PHYS) -- return NULL; -- if (lpa == METAL_BAD_PHYS) -- lpa = lda; -- if (lda == METAL_BAD_PHYS) -- lda = lpa; - tmpio = prproc->shm_io; - if (!tmpio) -- return NULL; -+ return -RPROC_EINVAL; -+ -+ if (*pa != METAL_BAD_PHYS) { -+ *da = *pa; -+ *va = metal_io_phys_to_virt(tmpio, *pa); -+ if (!*va) -+ return -RPROC_EINVAL; -+ } else if (*da != METAL_BAD_PHYS) { -+ *pa = *da; -+ *va = metal_io_phys_to_virt(tmpio, *da); -+ if (!*va) -+ return -RPROC_EINVAL; -+ } else if (*va) { -+ *pa = *da = metal_io_virt_to_phys(tmpio, *va); -+ if (*pa == METAL_BAD_PHYS) -+ return -RPROC_EINVAL; -+ } else -+ return -RPROC_EINVAL; - -- *pa = lpa; -- *da = lda; - if (io) - *io = tmpio; -- return metal_io_phys_to_virt(tmpio, lpa); -+ return 0; - } - - static int zynqmp_linux_r5_proc_notify(struct remoteproc *rproc, uint32_t id) -diff --git a/apps/machine/zynqmp_r5/platform_info.c open-amp/apps/machine/zynqmp_r5/platform_info.c -index 96c03c9..a2f7d9d 100644 ---- a/apps/machine/zynqmp_r5/platform_info.c -+++ open-amp/apps/machine/zynqmp_r5/platform_info.c -@@ -114,16 +114,16 @@ platform_create_proc(int proc_index, int rsc_index) - */ - /* mmap resource table */ - pa = (metal_phys_addr_t)rsc_table; -- (void *)remoteproc_mmap(&rproc_inst, &pa, -- NULL, rsc_size, -- NORM_NSHARED_NCACHE|PRIV_RW_USER_RW, -- &rproc_inst.rsc_io); -+ remoteproc_mmap(&rproc_inst, &pa, -+ NULL, NULL, rsc_size, -+ NORM_NSHARED_NCACHE|PRIV_RW_USER_RW, -+ &rproc_inst.rsc_io); - /* mmap shared memory */ - pa = SHARED_MEM_PA; -- (void *)remoteproc_mmap(&rproc_inst, &pa, -- NULL, SHARED_MEM_SIZE, -- NORM_NSHARED_NCACHE|PRIV_RW_USER_RW, -- NULL); -+ remoteproc_mmap(&rproc_inst, &pa, -+ NULL, NULL, SHARED_MEM_SIZE, -+ NORM_NSHARED_NCACHE|PRIV_RW_USER_RW, -+ NULL); - - /* parse resource table to remoteproc */ - ret = remoteproc_set_rsc_table(&rproc_inst, rsc_table, rsc_size); -diff --git a/apps/machine/zynqmp_r5/zynqmp_r5_a53_rproc.c open-amp/apps/machine/zynqmp_r5/zynqmp_r5_a53_rproc.c -index ee25368..ef5299c 100644 ---- a/apps/machine/zynqmp_r5/zynqmp_r5_a53_rproc.c -+++ open-amp/apps/machine/zynqmp_r5/zynqmp_r5_a53_rproc.c -@@ -109,45 +109,43 @@ static void zynqmp_r5_a53_proc_remove(struct remoteproc *rproc) - } - } - --static void * -+static int - zynqmp_r5_a53_proc_mmap(struct remoteproc *rproc, metal_phys_addr_t *pa, -- metal_phys_addr_t *da, size_t size, -+ metal_phys_addr_t *da, void **va, size_t size, - unsigned int attribute, struct metal_io_region **io) - { - struct remoteproc_mem *mem; -- metal_phys_addr_t lpa, lda; - struct metal_io_region *tmpio; - -- lpa = *pa; -- lda = *da; -- -- if (lpa == METAL_BAD_PHYS && lda == METAL_BAD_PHYS) -- return NULL; -- if (lpa == METAL_BAD_PHYS) -- lpa = lda; -- if (lda == METAL_BAD_PHYS) -- lda = lpa; -+ /* va is the same as pa/da in this platform */ -+ if (*pa != METAL_BAD_PHYS) { -+ *da = *pa; -+ *va = (void *)*pa; -+ } else if (*da != METAL_BAD_PHYS) { -+ *pa = *da; -+ *va = (void *)*da; -+ } else if (*va) -+ *pa = *da = (metal_phys_addr_t)*va; -+ else -+ return -RPROC_EINVAL; - - if (!attribute) - attribute = NORM_SHARED_NCACHE | PRIV_RW_USER_RW; - mem = metal_allocate_memory(sizeof(*mem)); - if (!mem) -- return NULL; -+ return -RPROC_ENOMEM; - tmpio = metal_allocate_memory(sizeof(*tmpio)); - if (!tmpio) { - metal_free_memory(mem); -- return NULL; -+ return -RPROC_ENOMEM; - } -- remoteproc_init_mem(mem, NULL, lpa, lda, size, tmpio); -- /* va is the same as pa in this platform */ -- metal_io_init(tmpio, (void *)lpa, &mem->pa, size, -+ remoteproc_init_mem(mem, NULL, *pa, *da, size, tmpio); -+ metal_io_init(tmpio, *va, &mem->pa, size, - sizeof(metal_phys_addr_t)<<3, attribute, NULL); - remoteproc_add_mem(rproc, mem); -- *pa = lpa; -- *da = lda; - if (io) - *io = tmpio; -- return metal_io_phys_to_virt(tmpio, mem->pa); -+ return 0; - } - - static int zynqmp_r5_a53_proc_notify(struct remoteproc *rproc, uint32_t id) -diff --git a/apps/system/linux/machine/generic/platform_info.c open-amp/apps/system/linux/machine/generic/platform_info.c -index 0b0f721..748fd83 100644 ---- a/apps/system/linux/machine/generic/platform_info.c -+++ open-amp/apps/system/linux/machine/generic/platform_info.c -@@ -300,39 +300,43 @@ static void linux_proc_remove(struct remoteproc *rproc) - } - } - --static void * -+static int - linux_proc_mmap(struct remoteproc *rproc, metal_phys_addr_t *pa, -- metal_phys_addr_t *da, size_t size, -+ metal_phys_addr_t *da, void **va, size_t size, - unsigned int attribute, struct metal_io_region **io) - { - struct remoteproc_mem *mem; - struct remoteproc_priv *prproc; -- metal_phys_addr_t lpa, lda; -- void *va; - - (void)attribute; - (void)size; -- lpa = *pa; -- lda = *da; -- -- if (lpa == METAL_BAD_PHYS && lda == METAL_BAD_PHYS) -- return NULL; -- if (lpa == METAL_BAD_PHYS) -- lpa = lda; -- if (lda == METAL_BAD_PHYS) -- lda = lpa; - - if (!rproc) -- return NULL; -+ return -RPROC_EINVAL; - prproc = rproc->priv; - mem = &prproc->shm; -- va = metal_io_phys_to_virt(mem->io, lpa); -- if (va) { -- if (io) -- *io = mem->io; -- metal_list_add_tail(&rproc->mems, &mem->node); -- } -- return va; -+ -+ if (*pa != METAL_BAD_PHYS) { -+ *da = *pa; -+ *va = metal_io_phys_to_virt(mem->io, *pa); -+ if (!*va) -+ return -RPROC_EINVAL; -+ } else if (*da != METAL_BAD_PHYS) { -+ *pa = *da; -+ *va = metal_io_phys_to_virt(mem->io, *da); -+ if (!*va) -+ return -RPROC_EINVAL; -+ } else if (*va) { -+ *pa = *da = metal_io_virt_to_phys(mem->io, *va); -+ if (*pa == METAL_BAD_PHYS) -+ return -RPROC_EINVAL; -+ } else -+ return -RPROC_EINVAL; -+ -+ remoteproc_add_mem(rproc, mem); -+ if (io) -+ *io = mem->io; -+ return 0; - } - - static int linux_proc_notify(struct remoteproc *rproc, uint32_t id) -@@ -391,7 +395,7 @@ static struct remoteproc * - platform_create_proc(int proc_index, int rsc_index) - { - struct remoteproc_priv *prproc; -- void *rsc_table, *rsc_table_shm; -+ void *rsc_table, *rsc_table_shm = NULL; - int rsc_size; - int ret; - metal_phys_addr_t pa; -@@ -420,8 +424,8 @@ platform_create_proc(int proc_index, int rsc_index) - - /* Mmap resource table */ - pa = RSC_MEM_PA; -- rsc_table_shm = remoteproc_mmap(&rproc_inst, &pa, NULL, rsc_size, -- 0, &rproc_inst.rsc_io); -+ remoteproc_mmap(&rproc_inst, &pa, NULL, &rsc_table_shm, rsc_size, -+ 0, &rproc_inst.rsc_io); - - /* parse resource table to remoteproc */ - ret = remoteproc_set_rsc_table(&rproc_inst, rsc_table_shm, rsc_size); -diff --git a/lib/include/openamp/remoteproc.h open-amp/lib/include/openamp/remoteproc.h -index a83aa12..b34cb1a 100644 ---- a/lib/include/openamp/remoteproc.h -+++ open-amp/lib/include/openamp/remoteproc.h -@@ -400,10 +400,10 @@ struct remoteproc_ops { - struct remoteproc *(*init)(struct remoteproc *rproc, - struct remoteproc_ops *ops, void *arg); - void (*remove)(struct remoteproc *rproc); -- void *(*mmap)(struct remoteproc *rproc, -- metal_phys_addr_t *pa, metal_phys_addr_t *da, -- size_t size, unsigned int attribute, -- struct metal_io_region **io); -+ int (*mmap)(struct remoteproc *rproc, -+ metal_phys_addr_t *pa, metal_phys_addr_t *da, -+ void **va, size_t size, unsigned int attribute, -+ struct metal_io_region **io); - int (*handle_rsc)(struct remoteproc *rproc, void *rsc, size_t len); - int (*config)(struct remoteproc *rproc, void *data); - int (*start)(struct remoteproc *rproc); -@@ -606,16 +606,17 @@ remoteproc_get_io_with_va(struct remoteproc *rproc, - * @rproc - pointer to the remote processor - * @pa - physical address pointer - * @da - device address pointer -+ * @va - virtual address pointer - * @size - size of the memory - * @attribute - memory attribute - * @io - pointer to the I/O region - * -- * returns pointer to the memory -+ * returns 0 for success and negative value for errors - */ --void *remoteproc_mmap(struct remoteproc *rproc, -- metal_phys_addr_t *pa, metal_phys_addr_t *da, -- size_t size, unsigned int attribute, -- struct metal_io_region **io); -+int remoteproc_mmap(struct remoteproc *rproc, -+ metal_phys_addr_t *pa, metal_phys_addr_t *da, -+ void **va, size_t size, unsigned int attribute, -+ struct metal_io_region **io); - - /** - * remoteproc_set_rsc_table -diff --git a/lib/remoteproc/remoteproc.c open-amp/lib/remoteproc/remoteproc.c -index 5afb40c..34b8cb8 100644 ---- a/lib/remoteproc/remoteproc.c -+++ open-amp/lib/remoteproc/remoteproc.c -@@ -295,13 +295,14 @@ struct metal_io_region * - remoteproc_get_io_with_pa(struct remoteproc *rproc, - metal_phys_addr_t pa) - { -- struct remoteproc_mem *mem; -+ struct metal_io_region *io; -+ int ret; - -- mem = remoteproc_get_mem(rproc, NULL, pa, METAL_BAD_PHYS, NULL, 0); -- if (mem) -- return mem->io; -- else -+ ret = remoteproc_mmap(rproc, &pa, NULL, NULL, 0, 0, &io); -+ if (ret < 0) - return NULL; -+ -+ return io; - } - - struct metal_io_region * -@@ -309,48 +310,44 @@ remoteproc_get_io_with_da(struct remoteproc *rproc, - metal_phys_addr_t da, - unsigned long *offset) - { -- struct remoteproc_mem *mem; -- -- mem = remoteproc_get_mem(rproc, NULL, METAL_BAD_PHYS, da, NULL, 0); -- if (mem) { -- struct metal_io_region *io; -- metal_phys_addr_t pa; -+ struct metal_io_region *io; -+ metal_phys_addr_t pa = METAL_BAD_PHYS; -+ int ret; - -- io = mem->io; -- pa = remoteproc_datopa(mem, da); -- *offset = metal_io_phys_to_offset(io, pa); -- return io; -- } else { -+ ret = remoteproc_mmap(rproc, &pa, &da, NULL, 0, 0, &io); -+ if (ret < 0) - return NULL; -- } -+ -+ *offset = metal_io_phys_to_offset(io, pa); -+ return io; - } - - struct metal_io_region * - remoteproc_get_io_with_va(struct remoteproc *rproc, void *va) - { -- struct remoteproc_mem *mem; -+ struct metal_io_region *io; -+ int ret; - -- mem = remoteproc_get_mem(rproc, NULL, METAL_BAD_PHYS, METAL_BAD_PHYS, -- va, 0); -- if (mem) -- return mem->io; -- else -+ ret = remoteproc_mmap(rproc, NULL, NULL, &va, 0, 0, &io); -+ if (ret < 0) - return NULL; -+ -+ return io; - } - --void *remoteproc_mmap(struct remoteproc *rproc, -- metal_phys_addr_t *pa, metal_phys_addr_t *da, -- size_t size, unsigned int attribute, -- struct metal_io_region **io) -+int remoteproc_mmap(struct remoteproc *rproc, -+ metal_phys_addr_t *pa, metal_phys_addr_t *da, -+ void **va, size_t size, unsigned int attribute, -+ struct metal_io_region **io) - { -- void *va = NULL; -+ void *lva = NULL; - metal_phys_addr_t lpa, lda; - struct remoteproc_mem *mem; - - if (!rproc) -- return NULL; -- else if (!pa && !da) -- return NULL; -+ return -RPROC_EINVAL; -+ else if (!pa && !da && !va) -+ return -RPROC_EINVAL; - if (pa) - lpa = *pa; - else -@@ -359,24 +356,40 @@ void *remoteproc_mmap(struct remoteproc *rproc, - lda = *da; - else - lda = METAL_BAD_PHYS; -- mem = remoteproc_get_mem(rproc, NULL, lpa, lda, NULL, size); -+ if (va) -+ lva = *va; -+ mem = remoteproc_get_mem(rproc, NULL, lpa, lda, lva, size); - if (mem) { -- if (lpa != METAL_BAD_PHYS) -+ if (lpa != METAL_BAD_PHYS) { - lda = remoteproc_patoda(mem, lpa); -- else if (lda != METAL_BAD_PHYS) -+ lva = metal_io_phys_to_virt(mem->io, lpa); -+ } else if (lda != METAL_BAD_PHYS) { - lpa = remoteproc_datopa(mem, lda); -+ lva = metal_io_phys_to_virt(mem->io, lpa); -+ } else if (lva != NULL) { -+ lpa = metal_io_virt_to_phys(mem->io, lva); -+ lda = remoteproc_patoda(mem, lpa); -+ } - if (io) - *io = mem->io; -- va = metal_io_phys_to_virt(mem->io, lpa); -- } else if (rproc->ops->mmap) { -- va = rproc->ops->mmap(rproc, &lpa, &lda, size, attribute, io); -+ } else { -+ int ret = -RPROC_EINVAL; -+ -+ if (rproc->ops->mmap) -+ ret = rproc->ops->mmap(rproc, &lpa, &lda, &lva, size, attribute, io); -+ -+ if (ret < 0) -+ return ret; - } - - if (pa) - *pa = lpa; - if (da) - *da = lda; -- return va; -+ if (va) -+ *va = lva; -+ -+ return 0; - } - - int remoteproc_load(struct remoteproc *rproc, const char *path, -@@ -529,8 +542,7 @@ int remoteproc_load(struct remoteproc *rproc, const char *path, - img_data = NULL; - /* get the I/O region from remoteproc */ - pa = METAL_BAD_PHYS; -- (void)remoteproc_mmap(rproc, &pa, &da, nmemsize, 0, -- &io); -+ remoteproc_mmap(rproc, &pa, &da, NULL, nmemsize, 0, &io); - if (pa == METAL_BAD_PHYS || !io) { - metal_log(METAL_LOG_ERROR, - "load failed, no mapping for 0x%llx.\r\n", -@@ -600,8 +612,9 @@ int remoteproc_load(struct remoteproc *rproc, const char *path, - - metal_log(METAL_LOG_DEBUG, - "%s, update resource table\r\n", __func__); -- rsc_table = remoteproc_mmap(rproc, NULL, &rsc_da, -- rsc_size, 0, &io); -+ rsc_table = NULL; -+ remoteproc_mmap(rproc, NULL, &rsc_da, -+ &rsc_table, rsc_size, 0, &io); - if (rsc_table) { - size_t rsc_io_offset; - -@@ -760,7 +773,7 @@ int remoteproc_load_noblock(struct remoteproc *rproc, - if (da != RPROC_LOAD_ANYADDR) { - /* get the I/O region from remoteproc */ - *pa = METAL_BAD_PHYS; -- (void)remoteproc_mmap(rproc, pa, &da, *nmlen, 0, io); -+ remoteproc_mmap(rproc, pa, &da, NULL, *nmlen, 0, io); - if (*pa == METAL_BAD_PHYS || !io) { - metal_log(METAL_LOG_ERROR, - "load failed, no mapping for 0x%llx.\r\n", -@@ -785,8 +798,8 @@ int remoteproc_load_noblock(struct remoteproc *rproc, - ret = -RPROC_ENOMEM; - goto error1; - } -- rsc_table = remoteproc_mmap(rproc, NULL, &rsc_da, -- rsc_size, 0, io); -+ remoteproc_mmap(rproc, NULL, &rsc_da, -+ &rsc_table, rsc_size, 0, io); - if (!*io) { - metal_log(METAL_LOG_ERROR, - "load failed: failed to mmap rsc\r\n"); -@@ -924,7 +937,7 @@ remoteproc_create_virtio(struct remoteproc *rproc, - metal_phys_addr_t da; - unsigned int num_descs, align; - struct metal_io_region *io; -- void *va; -+ void *va = NULL; - size_t size; - int ret; - -@@ -934,7 +947,7 @@ remoteproc_create_virtio(struct remoteproc *rproc, - num_descs = vring_rsc->num; - align = vring_rsc->align; - size = vring_size(num_descs, align); -- va = remoteproc_mmap(rproc, NULL, &da, size, 0, &io); -+ remoteproc_mmap(rproc, NULL, &da, &va, size, 0, &io); - if (!va) - goto err1; - ret = rproc_virtio_init_vring(vdev, i, notifyid, -diff --git a/lib/remoteproc/rsc_table_parser.c open-amp/lib/remoteproc/rsc_table_parser.c -index e43fa72..0bfd163 100644 ---- a/lib/remoteproc/rsc_table_parser.c -+++ open-amp/lib/remoteproc/rsc_table_parser.c -@@ -109,7 +109,7 @@ int handle_carve_out_rsc(struct remoteproc *rproc, void *rsc) - da = carve_rsc->da; - size = carve_rsc->len; - attribute = carve_rsc->flags; -- if (remoteproc_mmap(rproc, &pa, &da, size, attribute, NULL)) -+ if (remoteproc_mmap(rproc, &pa, &da, NULL, size, attribute, NULL)) - return 0; - else - return -RPROC_EINVAL; --- -2.17.1 - diff --git a/openamp/0007-rpmsg-bring-back-zero-copy-transfer.patch b/openamp/0007-rpmsg-bring-back-zero-copy-transfer.patch deleted file mode 100644 index 7ac5ba66be8..00000000000 --- a/openamp/0007-rpmsg-bring-back-zero-copy-transfer.patch +++ /dev/null @@ -1,470 +0,0 @@ -From e2233e080ef0ad62682f1725e17abb07e939ed50 Mon Sep 17 00:00:00 2001 -From: anchao -Date: Mon, 10 Dec 2018 19:39:01 +0800 -Subject: [PATCH 07/10] rpmsg: bring back zero copy transfer - -Commit-id: -b16ca55 Adding RPMsg Extension layer implementing zero-copy send and receive. - -Signed-off-by: anchao ---- - lib/include/openamp/rpmsg.h | 178 ++++++++++++++++++++++++++++++++++++ - lib/rpmsg/rpmsg.c | 58 ++++++++++++ - lib/rpmsg/rpmsg_internal.h | 3 + - lib/rpmsg/rpmsg_virtio.c | 130 +++++++++++++++++++++++++- - 4 files changed, 367 insertions(+), 2 deletions(-) - -diff --git a/lib/include/openamp/rpmsg.h open-amp/lib/include/openamp/rpmsg.h -index 1279ea2..0b46ee1 100644 ---- a/lib/include/openamp/rpmsg.h -+++ open-amp/lib/include/openamp/rpmsg.h -@@ -89,9 +89,20 @@ struct rpmsg_endpoint { - - /** - * struct rpmsg_device_ops - RPMsg device operations -+ * @hold_rx_buffer: hold RPMsg RX buffer -+ * @release_rx_buffer: release RPMsg RX buffer -+ * @get_tx_payload_buffer: get RPMsg TX buffer -+ * @send_offchannel_nocopy: send RPMsg data without copy - * @send_offchannel_raw: send RPMsg data - */ - struct rpmsg_device_ops { -+ void (*hold_rx_buffer)(struct rpmsg_device *rdev, void *rxbuf); -+ void (*release_rx_buffer)(struct rpmsg_device *rdev, void *rxbuf); -+ void *(*get_tx_payload_buffer)(struct rpmsg_device *rdev, -+ uint32_t *len, int wait); -+ int (*send_offchannel_nocopy)(struct rpmsg_device *rdev, -+ uint32_t src, uint32_t dst, -+ const void *data, int len); - int (*send_offchannel_raw)(struct rpmsg_device *rdev, - uint32_t src, uint32_t dst, - const void *data, int size, int wait); -@@ -294,6 +305,173 @@ static inline int rpmsg_trysend_offchannel(struct rpmsg_endpoint *ept, - return rpmsg_send_offchannel_raw(ept, src, dst, data, len, false); - } - -+/** -+ * @brief Holds the rx buffer for usage outside the receive callback. -+ * -+ * Calling this function prevents the RPMsg receive buffer from being released -+ * back to the pool of shmem buffers. This API can only be called at rx -+ * callback context (rpmsg_rx_cb_t). With this API, the application doesn't -+ * need to copy the message in rx callback. Instead, the rx buffer base address -+ * is saved in application context and further processed in application -+ * process. After the message is processed, the application can release the rx -+ * buffer for future reuse in vring by calling the rpmsg_release_rx_buffer() -+ * function. -+ * -+ * @param: ept The rpmsg endpoint -+ * @param: rxbuf RX buffer with message payload -+ * -+ * @see rpmsg_release_rx_buffer -+ */ -+void rpmsg_hold_rx_buffer(struct rpmsg_endpoint *ept, void *rxbuf); -+ -+/** -+ * @brief Releases the rx buffer for future reuse in vring. -+ * -+ * This API can be called at process context when the message in rx buffer is -+ * processed. -+ * -+ * @ept: the rpmsg endpoint -+ * @rxbuf: rx buffer with message payload -+ * -+ * @see rpmsg_hold_rx_buffer -+ */ -+void rpmsg_release_rx_buffer(struct rpmsg_endpoint *ept, void *rxbuf); -+ -+/** -+ * @brief Gets the tx buffer for message payload. -+ * -+ * This API can only be called at process context to get the tx buffer in vring. -+ * By this way, the application can directly put its message into the vring tx -+ * buffer without copy from an application buffer. -+ * It is the application responsibility to correctly fill the allocated tx -+ * buffer by data and passing correct parameters to the rpmsg_send_nocopy() or -+ * rpmsg_sendto_nocopy() function to perform data no-copy-send mechanism. -+ * -+ * @ept: Pointer to rpmsg endpoint -+ * @len: Pointer to store tx buffer size -+ * @wait: Boolean, wait or not for buffer to become available -+ * -+ * @return The tx buffer address on success and NULL on failure -+ * -+ * @see rpmsg_send_offchannel_nocopy -+ * @see rpmsg_sendto_nocopy -+ * @see rpmsg_send_nocopy -+ */ -+void *rpmsg_get_tx_payload_buffer(struct rpmsg_endpoint *ept, -+ uint32_t *len, int wait); -+ -+/** -+ * rpmsg_send_offchannel_nocopy() - send a message in tx buffer reserved by -+ * rpmsg_get_tx_payload_buffer() across to the remote processor. -+ * -+ * This function sends buf of length len to the remote dst address, -+ * and uses src as the source address. -+ * The message will be sent to the remote processor which the ept -+ * endpoint belongs to. -+ * The application has to take the responsibility for: -+ * 1. tx buffer reserved (rpmsg_get_tx_payload_buffer() ) -+ * 2. filling the data to be sent into the pre-allocated tx buffer -+ * 3. not exceeding the buffer size when filling the data -+ * 4. data cache coherency -+ * -+ * After the rpmsg_send_offchannel_nocopy() function is issued the tx buffer is -+ * no more owned by the sending task and must not be touched anymore unless the -+ * rpmsg_send_offchannel_nocopy() function fails and returns an error. In that -+ * case the application should try to re-issue the rpmsg_send_offchannel_nocopy() -+ * again. -+ * -+ * @ept: The rpmsg endpoint -+ * @src: The rpmsg endpoint local address -+ * @dst: The rpmsg endpoint remote address -+ * @data: TX buffer with message filled -+ * @len: Length of payload -+ * -+ * @return number of bytes it has sent or negative error value on failure. -+ * -+ * @see rpmsg_get_tx_payload_buffer -+ * @see rpmsg_sendto_nocopy -+ * @see rpmsg_send_nocopy -+ */ -+int rpmsg_send_offchannel_nocopy(struct rpmsg_endpoint *ept, uint32_t src, -+ uint32_t dst, const void *data, int len); -+ -+/** -+ * @brief Sends a message in tx buffer allocated by rpmsg_get_tx_payload_buffer() -+ * across to the remote processor, specify dst. -+ * -+ * This function sends buf of length len to the remote dst address. -+ * The message will be sent to the remote processor which the ept -+ * endpoint belongs to, using ept's source address. -+ * The application has to take the responsibility for: -+ * 1. tx buffer allocation (rpmsg_get_tx_payload_buffer() ) -+ * 2. filling the data to be sent into the pre-allocated tx buffer -+ * 3. not exceeding the buffer size when filling the data -+ * 4. data cache coherency -+ * -+ * After the rpmsg_sendto_nocopy() function is issued the tx buffer is no more -+ * owned by the sending task and must not be touched anymore unless the -+ * rpmsg_sendto_nocopy() function fails and returns an error. In that case the -+ * application should try to re-issue the rpmsg_sendto_nocopy() again. -+ * -+ * @ept: The rpmsg endpoint -+ * @data: TX buffer with message filled -+ * @len: Length of payload -+ * @dst: Destination address -+ * -+ * @return number of bytes it has sent or negative error value on failure. -+ * -+ * @see rpmsg_get_tx_payload_buffer -+ * @see rpmsg_send_offchannel_nocopy -+ * @see rpmsg_send_nocopy -+ */ -+static inline int rpmsg_sendto_nocopy(struct rpmsg_endpoint *ept, -+ const void *data, int len, uint32_t dst) -+{ -+ return rpmsg_send_offchannel_nocopy(ept, ept->addr, dst, data, len); -+} -+ -+/** -+ * rpmsg_send_nocopy() - send a message in tx buffer reserved by -+ * rpmsg_get_tx_payload_buffer() across to the remote processor. -+ * -+ * This function sends buf of length len on the ept endpoint. -+ * The message will be sent to the remote processor which the ept -+ * endpoint belongs to, using ept's source and destination addresses. -+ * The application has to take the responsibility for: -+ * 1. tx buffer reserved (rpmsg_get_tx_payload_buffer() ) -+ * 2. filling the data to be sent into the pre-allocated tx buffer -+ * 3. not exceeding the buffer size when filling the data -+ * 4. data cache coherency -+ * -+ * After the rpmsg_send_nocopy() function is issued the tx buffer is no more -+ * owned by the sending task and must not be touched anymore unless the -+ * rpmsg_send_nocopy() function fails and returns an error. In that case the -+ * application should try to re-issue the rpmsg_send_nocopy() again. -+ * -+ * @ept: The rpmsg endpoint -+ * @data: TX buffer with message filled -+ * @len: Length of payload -+ * -+ * @return number of bytes it has sent or negative error value on failure. -+ * -+ * @see rpmsg_get_tx_payload_buffer -+ * @see rpmsg_send_offchannel_nocopy -+ * @see rpmsg_sendto_nocopy -+ */ -+static inline int rpmsg_send_nocopy(struct rpmsg_endpoint *ept, const void *data, int len) -+{ -+ int tc = 0; -+ -+ for (; tc < RPMSG_TICK_COUNT; tc += RPMSG_TICKS_PER_INTERVAL) { -+ if (is_rpmsg_ept_ready(ept)) -+ return rpmsg_send_offchannel_nocopy(ept, ept->addr, -+ ept->dest_addr, data, len); -+ metal_sleep_usec(RPMSG_TICKS_PER_INTERVAL); -+ } -+ -+ return RPMSG_ERR_ADDR; -+} -+ - /** - * rpmsg_init_ept - initialize rpmsg endpoint - * -diff --git a/lib/rpmsg/rpmsg.c open-amp/lib/rpmsg/rpmsg.c -index 9da38a1..0a8de1b 100644 ---- a/lib/rpmsg/rpmsg.c -+++ open-amp/lib/rpmsg/rpmsg.c -@@ -144,6 +144,64 @@ int rpmsg_send_ns_message(struct rpmsg_endpoint *ept, unsigned long flags) - return RPMSG_SUCCESS; - } - -+void rpmsg_hold_rx_buffer(struct rpmsg_endpoint *ept, void *rxbuf) -+{ -+ struct rpmsg_device *rdev; -+ -+ if (!ept || !ept->rdev || !rxbuf) -+ return; -+ -+ rdev = ept->rdev; -+ -+ if (rdev->ops.hold_rx_buffer) -+ rdev->ops.hold_rx_buffer(rdev, rxbuf); -+} -+ -+void rpmsg_release_rx_buffer(struct rpmsg_endpoint *ept, void *rxbuf) -+{ -+ struct rpmsg_device *rdev; -+ -+ if (!ept || !ept->rdev || !rxbuf) -+ return; -+ -+ rdev = ept->rdev; -+ -+ if (rdev->ops.release_rx_buffer) -+ rdev->ops.release_rx_buffer(rdev, rxbuf); -+} -+ -+void *rpmsg_get_tx_payload_buffer(struct rpmsg_endpoint *ept, -+ uint32_t *len, int wait) -+{ -+ struct rpmsg_device *rdev; -+ -+ if (!ept || !ept->rdev || !len) -+ return NULL; -+ -+ rdev = ept->rdev; -+ -+ if (rdev->ops.get_tx_payload_buffer) -+ return rdev->ops.get_tx_payload_buffer(rdev, len, wait); -+ -+ return NULL; -+} -+ -+int rpmsg_send_offchannel_nocopy(struct rpmsg_endpoint *ept, uint32_t src, -+ uint32_t dst, const void *data, int len) -+{ -+ struct rpmsg_device *rdev; -+ -+ if (!ept || !ept->rdev || !data || !dst || dst == RPMSG_ADDR_ANY) -+ return RPMSG_ERR_PARAM; -+ -+ rdev = ept->rdev; -+ -+ if (rdev->ops.send_offchannel_nocopy) -+ return rdev->ops.send_offchannel_nocopy(rdev, src, dst, data, len); -+ -+ return RPMSG_ERR_PARAM; -+} -+ - struct rpmsg_endpoint *rpmsg_get_endpoint(struct rpmsg_device *rdev, - const char *name, uint32_t addr, - uint32_t dest_addr) -diff --git a/lib/rpmsg/rpmsg_internal.h open-amp/lib/rpmsg/rpmsg_internal.h -index 9c46970..3db6b24 100644 ---- a/lib/rpmsg/rpmsg_internal.h -+++ open-amp/lib/rpmsg/rpmsg_internal.h -@@ -35,6 +35,9 @@ extern "C" { - } while (0) - #endif - -+#define RPMSG_BUF_HELD (1U << 31) /* Flag to suggest to hold the buffer */ -+ -+#define RPMSG_LOCATE_HDR(p) (struct rpmsg_hdr *)((char *)(p) - sizeof(struct rpmsg_hdr)) - #define RPMSG_LOCATE_DATA(p) ((unsigned char *)(p) + sizeof(struct rpmsg_hdr)) - /** - * enum rpmsg_ns_flags - dynamic name service announcement flags -diff --git a/lib/rpmsg/rpmsg_virtio.c open-amp/lib/rpmsg/rpmsg_virtio.c -index 44b46d4..195189d 100644 ---- a/lib/rpmsg/rpmsg_virtio.c -+++ open-amp/lib/rpmsg/rpmsg_virtio.c -@@ -140,6 +140,7 @@ static void *rpmsg_virtio_get_tx_buffer(struct rpmsg_virtio_device *rvdev, - data = rpmsg_virtio_shm_pool_get_buffer(rvdev->shpool, - RPMSG_BUFFER_SIZE); - *len = RPMSG_BUFFER_SIZE; -+ *idx = 0; - } - } - #endif /*!VIRTIO_SLAVE_ONLY*/ -@@ -253,6 +254,118 @@ static int _rpmsg_virtio_get_buffer_size(struct rpmsg_virtio_device *rvdev) - return length; - } - -+static void rpmsg_virtio_hold_rx_buffer(struct rpmsg_device *rdev, void *rxbuf) -+{ -+ struct rpmsg_hdr *rp_hdr; -+ -+ rp_hdr = RPMSG_LOCATE_HDR(rxbuf); -+ -+ /* Set held status to keep buffer */ -+ rp_hdr->reserved = RPMSG_BUF_HELD; -+} -+ -+static void rpmsg_virtio_release_rx_buffer(struct rpmsg_device *rdev, void *rxbuf) -+{ -+ struct rpmsg_virtio_device *rvdev; -+ struct rpmsg_hdr *rp_hdr; -+ uint16_t idx; -+ uint32_t len; -+ -+ rvdev = metal_container_of(rdev, struct rpmsg_virtio_device, rdev); -+ rp_hdr = RPMSG_LOCATE_HDR(rxbuf); -+ /* The reserved field contains buffer index */ -+ idx = rp_hdr->reserved; -+ -+ metal_mutex_acquire(&rdev->lock); -+ /* Return buffer on virtqueue. */ -+ len = virtqueue_get_buffer_length(rvdev->rvq, idx); -+ rpmsg_virtio_return_buffer(rvdev, rp_hdr, len, idx); -+ metal_mutex_release(&rdev->lock); -+} -+ -+static void *rpmsg_virtio_get_tx_payload_buffer(struct rpmsg_device *rdev, -+ uint32_t *len, int wait) -+{ -+ struct rpmsg_virtio_device *rvdev; -+ struct rpmsg_hdr *rp_hdr; -+ uint16_t idx; -+ int tick_count; -+ -+ /* Get the associated remote device for channel. */ -+ rvdev = metal_container_of(rdev, struct rpmsg_virtio_device, rdev); -+ -+ if (wait) -+ tick_count = RPMSG_TICK_COUNT / RPMSG_TICKS_PER_INTERVAL; -+ else -+ tick_count = 0; -+ -+ while (1) { -+ /* Lock the device to enable exclusive access to virtqueues */ -+ metal_mutex_acquire(&rdev->lock); -+ rp_hdr = rpmsg_virtio_get_tx_buffer(rvdev, len, &idx); -+ metal_mutex_release(&rdev->lock); -+ if (rp_hdr || !tick_count) -+ break; -+ metal_sleep_usec(RPMSG_TICKS_PER_INTERVAL); -+ tick_count--; -+ } -+ -+ if (!rp_hdr) -+ return NULL; -+ -+ /* Store the index into the reserved field to be used when sending */ -+ rp_hdr->reserved = idx; -+ -+ /* Actual data buffer size is vring buffer size minus rpmsg header length */ -+ *len -= sizeof(struct rpmsg_hdr); -+ return RPMSG_LOCATE_DATA(rp_hdr); -+} -+ -+static int rpmsg_virtio_send_offchannel_nocopy(struct rpmsg_device *rdev, -+ uint32_t src, uint32_t dst, -+ const void *data, int len) -+{ -+ struct rpmsg_virtio_device *rvdev; -+ struct rpmsg_hdr rp_hdr; -+ struct rpmsg_hdr *hdr; -+ uint16_t idx; -+ int status; -+ struct metal_io_region *io; -+ -+ /* Get the associated remote device for channel. */ -+ rvdev = metal_container_of(rdev, struct rpmsg_virtio_device, rdev); -+ -+ hdr = RPMSG_LOCATE_HDR(data); -+ /* The reserved field contains buffer index */ -+ idx = hdr->reserved; -+ -+ /* Initialize RPMSG header. */ -+ rp_hdr.dst = dst; -+ rp_hdr.src = src; -+ rp_hdr.len = len; -+ rp_hdr.reserved = 0; -+ rp_hdr.flags = 0; -+ -+ /* Copy data to rpmsg buffer. */ -+ io = rvdev->shbuf_io; -+ status = metal_io_block_write(io, metal_io_virt_to_offset(io, hdr), -+ &rp_hdr, sizeof(rp_hdr)); -+ RPMSG_ASSERT(status == sizeof(rp_hdr), "failed to write header\r\n"); -+ -+ metal_mutex_acquire(&rdev->lock); -+ -+ /* Enqueue buffer on virtqueue. */ -+ len = virtqueue_get_buffer_length(rvdev->svq, idx); -+ status = rpmsg_virtio_enqueue_buffer(rvdev, hdr, len, idx); -+ RPMSG_ASSERT(status == VQUEUE_SUCCESS, "failed to enqueue buffer\r\n"); -+ /* Let the other side know that there is a job to process. */ -+ virtqueue_kick(rvdev->svq); -+ -+ metal_mutex_release(&rdev->lock); -+ -+ return len; -+} -+ - /** - * This function sends rpmsg "message" to remote device. - * -@@ -389,6 +502,8 @@ static void rpmsg_virtio_rx_callback(struct virtqueue *vq) - metal_mutex_release(&rdev->lock); - - while (rp_hdr) { -+ rp_hdr->reserved = 0; -+ - /* Get the channel node from the remote device channels list. */ - metal_mutex_acquire(&rdev->lock); - ept = rpmsg_get_ept_from_addr(rdev, rp_hdr->dst); -@@ -411,8 +526,15 @@ static void rpmsg_virtio_rx_callback(struct virtqueue *vq) - - metal_mutex_acquire(&rdev->lock); - -- /* Return used buffers. */ -- rpmsg_virtio_return_buffer(rvdev, rp_hdr, len, idx); -+ /* Check whether callback wants to hold buffer */ -+ if (rp_hdr->reserved & RPMSG_BUF_HELD) { -+ /* 'rp_hdr->reserved' field is now used as storage for -+ * 'idx' to release buffer later */ -+ rp_hdr->reserved = idx; -+ } else { -+ /* Return used buffers. */ -+ rpmsg_virtio_return_buffer(rvdev, rp_hdr, len, idx); -+ } - - rp_hdr = rpmsg_virtio_get_rx_buffer(rvdev, &len, &idx); - if (!rp_hdr) { -@@ -522,6 +644,10 @@ int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev, - rvdev->vdev = vdev; - rdev->ns_bind_cb = ns_bind_cb; - vdev->priv = rvdev; -+ rdev->ops.hold_rx_buffer = rpmsg_virtio_hold_rx_buffer; -+ rdev->ops.release_rx_buffer = rpmsg_virtio_release_rx_buffer; -+ rdev->ops.get_tx_payload_buffer = rpmsg_virtio_get_tx_payload_buffer; -+ rdev->ops.send_offchannel_nocopy = rpmsg_virtio_send_offchannel_nocopy; - rdev->ops.send_offchannel_raw = rpmsg_virtio_send_offchannel_raw; - role = rpmsg_virtio_get_role(rvdev); - --- -2.17.1 - diff --git a/openamp/0009-implement-rproc_virtio_read_config-rproc_virtio_writ.patch b/openamp/0009-implement-rproc_virtio_read_config-rproc_virtio_writ.patch deleted file mode 100644 index 3678826d573..00000000000 --- a/openamp/0009-implement-rproc_virtio_read_config-rproc_virtio_writ.patch +++ /dev/null @@ -1,119 +0,0 @@ -From 9bbc2dcd43f6107a7e0b1eec16bab10e533329f2 Mon Sep 17 00:00:00 2001 -From: Xiang Xiao -Date: Thu, 3 Jan 2019 14:20:48 +0800 -Subject: [PATCH 09/10] implement - rproc_virtio_read_config/rproc_virtio_write_config - -so the rpmsg could access the configuration space as needed - -Signed-off-by: Xiang Xiao ---- - lib/include/openamp/rpmsg_virtio.h | 14 +++++++++++ - lib/include/openamp/virtio.h | 1 + - lib/remoteproc/remoteproc_virtio.c | 40 ++++++++++++++++++++++++------ - 3 files changed, 47 insertions(+), 8 deletions(-) - -diff --git a/lib/include/openamp/rpmsg_virtio.h open-amp/lib/include/openamp/rpmsg_virtio.h -index e6e5fa2..4d3093b 100644 ---- a/lib/include/openamp/rpmsg_virtio.h -+++ open-amp/lib/include/openamp/rpmsg_virtio.h -@@ -86,6 +86,20 @@ rpmsg_virtio_get_features(struct rpmsg_virtio_device *rvdev) - return rvdev->vdev->func->get_features(rvdev->vdev); - } - -+static inline void -+rpmsg_virtio_read_config(struct rpmsg_virtio_device *rvdev, -+ uint32_t offset, void *dst, int length) -+{ -+ rvdev->vdev->func->read_config(rvdev->vdev, offset, dst, length); -+} -+ -+static inline void -+rpmsg_virtio_write_config(struct rpmsg_virtio_device *rvdev, -+ uint32_t offset, void *dst, int length) -+{ -+ rvdev->vdev->func->write_config(rvdev->vdev, offset, dst, length); -+} -+ - static inline int - rpmsg_virtio_create_virtqueues(struct rpmsg_virtio_device *rvdev, - int flags, unsigned int nvqs, -diff --git a/lib/include/openamp/virtio.h open-amp/lib/include/openamp/virtio.h -index 55c8ea5..9c8376e 100644 ---- a/lib/include/openamp/virtio.h -+++ open-amp/lib/include/openamp/virtio.h -@@ -100,6 +100,7 @@ struct virtio_device { - virtio_dev_reset_cb reset_cb; /**< user registered device callback */ - const struct virtio_dispatch *func; /**< Virtio dispatch table */ - void *priv; /**< TODO: remove pointer to virtio_device private data */ -+ unsigned int config_len; /**< config space length */ - unsigned int vrings_num; /**< number of vrings */ - struct virtio_vring_info *vrings_info; - }; -diff --git a/lib/remoteproc/remoteproc_virtio.c open-amp/lib/remoteproc/remoteproc_virtio.c -index aafc48c..7505f64 100644 ---- a/lib/remoteproc/remoteproc_virtio.c -+++ open-amp/lib/remoteproc/remoteproc_virtio.c -@@ -128,20 +128,43 @@ static uint32_t rproc_virtio_negotiate_features(struct virtio_device *vdev, - static void rproc_virtio_read_config(struct virtio_device *vdev, - uint32_t offset, void *dst, int length) - { -- (void)vdev; -- (void)offset; -- (void)dst; -- (void)length; -+ struct remoteproc_virtio *rpvdev; -+ struct fw_rsc_vdev *vdev_rsc; -+ struct metal_io_region *io; -+ char *config; -+ -+ if (offset + length > vdev->config_len || offset + length < length) -+ return; -+ -+ rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev); -+ vdev_rsc = rpvdev->vdev_rsc; -+ config = (char *)(&vdev_rsc->vring[vdev->vrings_num]); -+ io = rpvdev->vdev_rsc_io; -+ metal_io_block_read(io, -+ metal_io_virt_to_offset(io, config + offset), -+ dst, length); - } - - #ifndef VIRTIO_SLAVE_ONLY - static void rproc_virtio_write_config(struct virtio_device *vdev, - uint32_t offset, void *src, int length) - { -- (void)vdev; -- (void)offset; -- (void)src; -- (void)length; -+ struct remoteproc_virtio *rpvdev; -+ struct fw_rsc_vdev *vdev_rsc; -+ struct metal_io_region *io; -+ char *config; -+ -+ if (offset + length > vdev->config_len || offset + length < length) -+ return; -+ -+ rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev); -+ vdev_rsc = rpvdev->vdev_rsc; -+ config = (char *)(&vdev_rsc->vring[vdev->vrings_num]); -+ io = rpvdev->vdev_rsc_io; -+ metal_io_block_write(io, -+ metal_io_virt_to_offset(io, config + offset), -+ src, length); -+ rpvdev->notify(rpvdev->priv, vdev->notifyid); - } - - static void rproc_virtio_reset_device(struct virtio_device *vdev) -@@ -222,6 +245,7 @@ rproc_virtio_create_vdev(unsigned int role, unsigned int notifyid, - vdev->notifyid = notifyid; - vdev->role = role; - vdev->reset_cb = rst_cb; -+ vdev->config_len = vdev_rsc->config_len; - vdev->vrings_num = num_vrings; - vdev->func = &remoteproc_virtio_dispatch_funcs; - --- -2.17.1 - diff --git a/openamp/Makefile b/openamp/Makefile index 49637836625..10fdbfce930 100644 --- a/openamp/Makefile +++ b/openamp/Makefile @@ -20,7 +20,7 @@ include $(TOPDIR)/Make.defs -VERSION ?= 2020.04.0 +VERSION ?= 2021.04.0 include libmetal.defs include open-amp.defs diff --git a/openamp/libmetal.defs b/openamp/libmetal.defs index 058ba60e161..5683a941575 100644 --- a/openamp/libmetal.defs +++ b/openamp/libmetal.defs @@ -47,10 +47,10 @@ CSRCS += libmetal/lib/version.c CFLAGS += -DMETAL_INTERNAL LIBMETAL_HDRS_SEDEXP := \ - "s/@PROJECT_VER_MAJOR@/0/g; \ - s/@PROJECT_VER_MINOR@/1/g; \ - s/@PROJECT_VER_PATCH@/0/g; \ - s/@PROJECT_VER@/0.1.0/g; \ + "s/@PROJECT_VERSION_MAJOR@/0/g; \ + s/@PROJECT_VERSION_MINOR@/1/g; \ + s/@PROJECT_VERSION_PATCH@/0/g; \ + s/@PROJECT_VERSION@/0.1.0/g; \ s/@PROJECT_SYSTEM@/nuttx/g; \ s/@PROJECT_PROCESSOR@/$(LIBMETAL_ARCH)/g; \ s/@PROJECT_MACHINE@/$(CONFIG_ARCH_CHIP)/g; \ @@ -63,7 +63,6 @@ libmetal.zip: $(Q) curl -L https://github.com/OpenAMP/libmetal/archive/v$(VERSION).zip -o libmetal.zip $(Q) unzip -o libmetal.zip $(Q) mv libmetal-$(VERSION) libmetal - $(Q) patch -p0 < 0001-system-nuttx-change-clock_systimespec-to-clock_systi.patch .libmetal_headers:# libmetal.zip $(eval headers := $(wildcard libmetal/lib/compiler/gcc/*.h)) diff --git a/openamp/open-amp.defs b/openamp/open-amp.defs index a7e35b35fd7..1174a41fbd0 100644 --- a/openamp/open-amp.defs +++ b/openamp/open-amp.defs @@ -33,16 +33,9 @@ open-amp.zip: $(Q) curl -L https://github.com/OpenAMP/open-amp/archive/v$(VERSION).zip -o open-amp.zip $(Q) unzip -o open-amp.zip $(Q) mv open-amp-$(VERSION) open-amp - $(Q) patch -p0 < 0001-rpmsg-remove-the-address-check-in-rpmsg_send-rpmsg_t.patch - $(Q) patch -p0 < 0002-rpmsg-merge-rpmsg_register_endpoint-into-rpmsg_init_.patch - $(Q) patch -p0 < 0003-rpmsg-shouldn-t-allocate-0-1023-address-in-rpmsg_cre.patch - $(Q) patch -p0 < 0004-rpmsg-wait-ept-ready-in-rpmsg_send.patch - $(Q) patch -p0 < 0005-rpmsg-return-fail-if-either-source-or-destination-ad.patch - $(Q) patch -p0 < 0006-remoteproc_mmap-support-va-to-pa-da-conversion.patch - $(Q) patch -p0 < 0007-rpmsg-bring-back-zero-copy-transfer.patch - $(Q) patch -p0 < 0008-ns-acknowledge-the-received-creation-message.patch - $(Q) patch -p0 < 0009-implement-rproc_virtio_read_config-rproc_virtio_writ.patch - $(Q) patch -p0 < 0010-Negotiate-individual-buffer-size-dynamically.patch + $(Q) patch -p0 < 0001-ns-acknowledge-the-received-creation-message.patch + $(Q) patch -p0 < 0002-Negotiate-individual-buffer-size-dynamically.patch + $(Q) patch -p0 < 0003-rpmsg-wait-endpoint-ready-in-rpmsg_send-and-rpmsg_se.patch .openamp_headers:# open-amp.zip $(eval headers := $(wildcard open-amp/lib/include/openamp/*.h)) diff --git a/sched/Kconfig b/sched/Kconfig index b878efcaed6..3059256aeee 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -276,7 +276,7 @@ config SMP Enables support for Symmetric Multi-Processing (SMP) on a multi-CPU platform. - SMP mode must work with ARCH_INTERRUPTSTACK, here is the fail case: + N.B. SMP mode requires the use of ARCH_INTERRUPTSTACK: CPU0 thread0 -> IRQ enter -> add thread0 to block_list -> IRQ leave(crash) || @@ -285,7 +285,7 @@ config SMP CPU1 thread1 -> block_task -> take thread0 from block_list -> run thread0 CPU0 IRQ handler use thread0's stack, but thread0 may switch to CPU1, that - will caused IRQ handler stack curroption. + will caused IRQ handler stack corruption. if SMP @@ -483,13 +483,6 @@ config TASK_NAME_SIZE will be TASK_NAME_SIZE + 1. The default of 31 then results in a align-able 32-byte allocation. -config MAX_TASKS - int "Max number of tasks" - default 32 - ---help--- - The maximum number of simultaneously active tasks. This value must be - a power of two. - config SCHED_HAVE_PARENT bool "Support parent/child task relationships" default n @@ -551,11 +544,8 @@ config PREALLOC_CHILDSTATUS To prevent runaway child status allocations and to improve allocation performance, child task exit status structures are pre- allocated when the system boots. This setting determines the number - of child status structures that will be pre-allocated. If this - setting is not defined or if it is defined to be zero then a value - of 2*MAX_TASKS is used. + of child status structures that will be pre-allocated. - Note that there cannot be more than MAX_TASKS tasks in total. However, the number of child status structures may need to be significantly larger because this number includes the maximum number of tasks that are running PLUS the number of tasks that have exit'ed @@ -1573,9 +1563,9 @@ config SIG_SIGWORK default 17 depends on SCHED_WORKQUEUE || LIB_USRWORK ---help--- - SIGWORK is a non-standard signal used to wake up the internal NuttX - worker thread. This setting specifies the signal number that will be - used for SIGWORK. Default: 17 + SIGWORK is a non-standard signal used to wake up various internal + NuttX worker threads. This setting specifies the signal number + that will be used for SIGWORK. Default: 17 endmenu # Signal Numbers endmenu # Signal Configuration @@ -1609,7 +1599,7 @@ config MODULE bool "Enable loadable OS modules" default n select LIBC_MODLIB - select ARCH_USE_MODULE_TEXT if ARCH_HAVE_MODULE_TEXT + select ARCH_USE_TEXT_HEAP if ARCH_HAVE_TEXT_HEAP ---help--- Enable support for loadable OS modules. Default: n diff --git a/sched/clock/clock_systime_timespec.c b/sched/clock/clock_systime_timespec.c index 97b65268252..bfc6db7867c 100644 --- a/sched/clock/clock_systime_timespec.c +++ b/sched/clock/clock_systime_timespec.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/clock/clock_time2ticks.c b/sched/clock/clock_time2ticks.c index 352da778ada..72e5f7942aa 100644 --- a/sched/clock/clock_time2ticks.c +++ b/sched/clock/clock_time2ticks.c @@ -26,6 +26,7 @@ #include #include +#include #include "clock/clock.h" diff --git a/sched/clock/clock_timekeeping.c b/sched/clock/clock_timekeeping.c index a14ba580808..38d55e1e402 100644 --- a/sched/clock/clock_timekeeping.c +++ b/sched/clock/clock_timekeeping.c @@ -1,35 +1,20 @@ /**************************************************************************** * sched/clock/clock_timekeeping.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Max Neklyudov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/sched/clock/clock_timekeeping.h b/sched/clock/clock_timekeeping.h index 4f85ebfc014..b58e7058ced 100644 --- a/sched/clock/clock_timekeeping.h +++ b/sched/clock/clock_timekeeping.h @@ -1,35 +1,20 @@ /**************************************************************************** * sched/clock/clock_timekeeping.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Max Neklyudov + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/sched/environ/env_clearenv.c b/sched/environ/env_clearenv.c index 24f3eeab78a..8178c3b0126 100644 --- a/sched/environ/env_clearenv.c +++ b/sched/environ/env_clearenv.c @@ -28,6 +28,8 @@ #include #include +#include + #include "sched/sched.h" #include "environ/environ.h" diff --git a/sched/environ/env_dup.c b/sched/environ/env_dup.c index e0bdf2e4169..5d0df69bbde 100644 --- a/sched/environ/env_dup.c +++ b/sched/environ/env_dup.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/sched/environ/env_findvar.c b/sched/environ/env_findvar.c index 3db6a742e12..ce7df15d342 100644 --- a/sched/environ/env_findvar.c +++ b/sched/environ/env_findvar.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "environ/environ.h" diff --git a/sched/environ/env_foreach.c b/sched/environ/env_foreach.c index 52a7a814919..05a73a2e5a2 100644 --- a/sched/environ/env_foreach.c +++ b/sched/environ/env_foreach.c @@ -29,6 +29,7 @@ #include #include #include +#include #include diff --git a/sched/environ/env_release.c b/sched/environ/env_release.c index 4c6f3553c25..86442dc9410 100644 --- a/sched/environ/env_release.c +++ b/sched/environ/env_release.c @@ -27,6 +27,7 @@ #ifndef CONFIG_DISABLE_ENVIRON #include +#include #include #include diff --git a/sched/environ/env_removevar.c b/sched/environ/env_removevar.c index d21ebf3d7f9..4149b301c9f 100644 --- a/sched/environ/env_removevar.c +++ b/sched/environ/env_removevar.c @@ -28,6 +28,7 @@ #include #include +#include #include "environ/environ.h" diff --git a/sched/environ/env_setenv.c b/sched/environ/env_setenv.c index 70593bf9566..3fdc2117f8a 100644 --- a/sched/environ/env_setenv.c +++ b/sched/environ/env_setenv.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/sched/environ/env_unsetenv.c b/sched/environ/env_unsetenv.c index 888501fba55..c83646b757c 100644 --- a/sched/environ/env_unsetenv.c +++ b/sched/environ/env_unsetenv.c @@ -28,6 +28,7 @@ #include #include +#include #include #include diff --git a/sched/group/Make.defs b/sched/group/Make.defs index 14f12257491..b0a2cf7e137 100644 --- a/sched/group/Make.defs +++ b/sched/group/Make.defs @@ -53,10 +53,6 @@ ifneq ($(CONFIG_BUILD_FLAT),y) CSRCS += group_malloc.c group_zalloc.c group_free.c endif -ifneq ($(CONFIG_TLS_NELEM),0) -CSRCS += group_tlsalloc.c group_tlsfree.c -endif - # Include group build support DEPPATH += --dep-path group diff --git a/sched/group/group.h b/sched/group/group.h index 3449891803f..9436b42e028 100644 --- a/sched/group/group.h +++ b/sched/group/group.h @@ -73,6 +73,7 @@ void weak_function task_initialize(void); /* Task group data structure management */ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype); +void group_deallocate(FAR struct task_group_s *group); int group_initialize(FAR struct task_tcb_s *tcb); #ifndef CONFIG_DISABLE_PTHREAD int group_bind(FAR struct pthread_tcb_s *tcb); diff --git a/sched/group/group_addrenv.c b/sched/group/group_addrenv.c index e97b0518d6d..06b95f557ca 100644 --- a/sched/group/group_addrenv.c +++ b/sched/group/group_addrenv.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/sched/group/group_childstatus.c b/sched/group/group_childstatus.c index a0979942840..4b9cb086c28 100644 --- a/sched/group/group_childstatus.c +++ b/sched/group/group_childstatus.c @@ -25,6 +25,7 @@ #include #include +#include #include #include @@ -37,19 +38,9 @@ * Pre-processor Definitions ****************************************************************************/ -/* Note that there cannot be more that CONFIG_MAX_TASKS tasks in total. - * However, the number of child status structures may need to be - * significantly larger because this number includes the maximum number of - * tasks that are running PLUS the number of tasks that have exit'ed without - * having their exit status reaped (via wait(), waitid(), or waitpid()). - * - * Obviously, if tasks spawn children indefinitely and never have the exit - * status reaped, then you have a memory leak! - */ - #if !defined(CONFIG_PREALLOC_CHILDSTATUS) || CONFIG_PREALLOC_CHILDSTATUS == 0 # undef CONFIG_PREALLOC_CHILDSTATUS -# define CONFIG_PREALLOC_CHILDSTATUS (2*CONFIG_MAX_TASKS) +# define CONFIG_PREALLOC_CHILDSTATUS 16 #endif #ifndef CONFIG_DEBUG_INFO diff --git a/sched/group/group_create.c b/sched/group/group_create.c index 7e29280b409..6fbfcf8800a 100644 --- a/sched/group/group_create.c +++ b/sched/group/group_create.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "environ/environ.h" #include "sched/sched.h" @@ -126,7 +127,7 @@ static inline void group_inherit_identity(FAR struct task_group_s *group) int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) { FAR struct task_group_s *group; - int ret; + int ret = -ENOMEM; DEBUGASSERT(tcb && !tcb->cmn.group); @@ -138,7 +139,7 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) return -ENOMEM; } -#if defined(CONFIG_FILE_STREAM) && defined(CONFIG_MM_KERNEL_HEAP) +#if defined(CONFIG_MM_KERNEL_HEAP) /* If this group is being created for a privileged thread, then all * elements of the group must be created for privileged access. */ @@ -148,6 +149,8 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) group->tg_flags |= GROUP_FLAG_PRIVILEGED; } +# if defined(CONFIG_FILE_STREAM) + /* In a flat, single-heap build. The stream list is allocated with the * group structure. But in a kernel build with a kernel allocator, it * must be separately allocated using a user-space allocator. @@ -161,11 +164,25 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) if (!group->tg_streamlist) { - kmm_free(group); - return -ENOMEM; + goto errout_with_group; } -#endif +# endif /* defined(CONFIG_FILE_STREAM) */ +#endif /* defined(CONFIG_MM_KERNEL_HEAP) */ + + /* Alloc task info for group */ + + group->tg_info = (FAR struct task_info_s *) + group_zalloc(group, sizeof(struct task_info_s)); + + if (!group->tg_info) + { + goto errout_with_stream; + } + + /* Initial user space semaphore */ + + nxsem_init(&group->tg_info->ta_sem, 0, 1); /* Attach the group to the TCB */ @@ -180,12 +197,8 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) ret = env_dup(group); if (ret < 0) { -#if defined(CONFIG_FILE_STREAM) && defined(CONFIG_MM_KERNEL_HEAP) - group_free(group, group->tg_streamlist); -#endif - kmm_free(group); tcb->cmn.group = NULL; - return ret; + goto errout_with_group; } #ifndef CONFIG_DISABLE_PTHREAD @@ -206,6 +219,39 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) #endif return OK; + +errout_with_stream: +#if defined(CONFIG_FILE_STREAM) && defined(CONFIG_MM_KERNEL_HEAP) + group_free(group, group->tg_streamlist); +#endif +errout_with_group: + group_deallocate(group); + return ret; +} + +/**************************************************************************** + * Name: group_deallocate + * + * Description: + * Free an existing task group structure. + * + * Input Parameters: + * group = The group structure + * + ****************************************************************************/ + +void group_deallocate(FAR struct task_group_s *group) +{ + if (group) + { + if (group->tg_info) + { + nxsem_destroy(&group->tg_info->ta_sem); + group_free(group, group->tg_info); + } + + kmm_free(group); + } } /**************************************************************************** @@ -245,7 +291,7 @@ int group_initialize(FAR struct task_tcb_s *tcb) group->tg_members = kmm_malloc(GROUP_INITIAL_MEMBERS * sizeof(pid_t)); if (!group->tg_members) { - kmm_free(group); + group_deallocate(group); tcb->cmn.group = NULL; return -ENOMEM; } diff --git a/sched/group/group_exitinfo.c b/sched/group/group_exitinfo.c index 4cd54d06e5a..876c65a1031 100644 --- a/sched/group/group_exitinfo.c +++ b/sched/group/group_exitinfo.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/group/group_foreachchild.c b/sched/group/group_foreachchild.c index cf4c633ef80..81761ba6e83 100644 --- a/sched/group/group_foreachchild.c +++ b/sched/group/group_foreachchild.c @@ -24,6 +24,7 @@ #include +#include #include #include "group/group.h" diff --git a/sched/group/group_getgid.c b/sched/group/group_getgid.c index 0d891be4b1c..b5d25dfd7f6 100644 --- a/sched/group/group_getgid.c +++ b/sched/group/group_getgid.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/group/group_getuid.c b/sched/group/group_getuid.c index b312622afad..41103afeafc 100644 --- a/sched/group/group_getuid.c +++ b/sched/group/group_getuid.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/group/group_killchildren.c b/sched/group/group_killchildren.c index 16a8f26fbd4..e06197eac7e 100644 --- a/sched/group/group_killchildren.c +++ b/sched/group/group_killchildren.c @@ -28,6 +28,7 @@ #include #include #include +#include #include diff --git a/sched/group/group_leave.c b/sched/group/group_leave.c index e2ad11f8838..d2d0c2e50c2 100644 --- a/sched/group/group_leave.c +++ b/sched/group/group_leave.c @@ -250,7 +250,7 @@ static inline void group_release(FAR struct task_group_s *group) { /* Release the group container itself */ - kmm_free(group); + group_deallocate(group); } } diff --git a/sched/group/group_setgid.c b/sched/group/group_setgid.c index 95aaa49ab28..e5a4b8ebf07 100644 --- a/sched/group/group_setgid.c +++ b/sched/group/group_setgid.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/group/group_setuid.c b/sched/group/group_setuid.c index 31eca51ae5a..0a993ed3190 100644 --- a/sched/group/group_setuid.c +++ b/sched/group/group_setuid.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/group/group_setupidlefiles.c b/sched/group/group_setupidlefiles.c index 51b61de09e6..24db33ed7c1 100644 --- a/sched/group/group_setupidlefiles.c +++ b/sched/group/group_setupidlefiles.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/sched/group/group_setupstreams.c b/sched/group/group_setupstreams.c index 511ad604763..20c5127bd48 100644 --- a/sched/group/group_setupstreams.c +++ b/sched/group/group_setupstreams.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/group/group_setuptaskfiles.c b/sched/group/group_setuptaskfiles.c index 43c64349304..ca9a8e886b0 100644 --- a/sched/group/group_setuptaskfiles.c +++ b/sched/group/group_setuptaskfiles.c @@ -25,6 +25,7 @@ #include #include +#include #include diff --git a/sched/group/group_waiter.c b/sched/group/group_waiter.c index 1c4889f38a3..2eda24d15f8 100644 --- a/sched/group/group_waiter.c +++ b/sched/group/group_waiter.c @@ -76,7 +76,7 @@ void group_del_waiter(FAR struct task_group_s *group) * freed). */ - kmm_free(group); + group_deallocate(group); } } diff --git a/sched/init/nx_bringup.c b/sched/init/nx_bringup.c index 56234b88274..6815dd1729d 100644 --- a/sched/init/nx_bringup.c +++ b/sched/init/nx_bringup.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/init/nx_smpstart.c b/sched/init/nx_smpstart.c index 32a009f14bb..4bcb7125b00 100644 --- a/sched/init/nx_smpstart.c +++ b/sched/init/nx_smpstart.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/init/nx_start.c b/sched/init/nx_start.c index 07d9a7938dd..f1fb20f8799 100644 --- a/sched/init/nx_start.c +++ b/sched/init/nx_start.c @@ -63,6 +63,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_SMP_NCPUS +# define CONFIG_SMP_NCPUS 1 +#endif + #ifdef CONFIG_SMP /* This set of all CPUs */ @@ -92,7 +96,6 @@ volatile dq_queue_t g_readytorun; -#ifdef CONFIG_SMP /* In order to support SMP, the function of the g_readytorun list changes, * The g_readytorun is still used but in the SMP case it will contain only: * @@ -123,7 +126,9 @@ volatile dq_queue_t g_readytorun; * always the CPU's IDLE task. */ +#ifdef CONFIG_SMP volatile dq_queue_t g_assignedtasks[CONFIG_SMP_NCPUS]; +#endif /* g_running_tasks[] holds a references to the running task for each cpu. * It is valid only when up_interrupt_context() returns true. @@ -131,12 +136,6 @@ volatile dq_queue_t g_assignedtasks[CONFIG_SMP_NCPUS]; FAR struct tcb_s *g_running_tasks[CONFIG_SMP_NCPUS]; -#else - -FAR struct tcb_s *g_running_tasks[1]; - -#endif - /* This is the list of all tasks that are ready-to-run, but cannot be placed * in the g_readytorun list because: (1) They are higher priority than the * currently active task at the head of the g_readytorun list, and (2) the @@ -198,12 +197,11 @@ volatile pid_t g_lastpid; * 1. This hash table greatly speeds the determination of a new unique * process ID for a task, and * 2. Is used to quickly map a process ID into a TCB. - * - * It has the side effects of using more memory and limiting - * the number of tasks to CONFIG_MAX_TASKS. */ -struct pidhash_s g_pidhash[CONFIG_MAX_TASKS]; +FAR struct pidhash_s *g_pidhash; + +volatile int g_npidhash; /* This is a table of task lists. This table is indexed by the task stat * enumeration type (tstate_t) and provides a pointer to the associated @@ -303,11 +301,7 @@ uint8_t g_nx_initstate; /* See enum nx_initstate_e */ * bringing up the rest of the system. */ -#ifdef CONFIG_SMP static struct task_tcb_s g_idletcb[CONFIG_SMP_NCPUS]; -#else -static struct task_tcb_s g_idletcb[1]; -#endif /* This is the name of the idle task */ @@ -324,11 +318,7 @@ static const char g_idlename[] = "Idle Task"; * do things s little differently here for the IDLE tasks. */ -#ifdef CONFIG_SMP static FAR char *g_idleargv[CONFIG_SMP_NCPUS][2]; -#else -static FAR char *g_idleargv[1][2]; -#endif /**************************************************************************** * Public Functions @@ -352,7 +342,6 @@ static FAR char *g_idleargv[1][2]; void nx_start(void) { - int cpu = 0; int i; sinfo("Entry\n"); @@ -389,28 +378,11 @@ void nx_start(void) } #endif - /* Initialize the logic that determine unique process IDs. */ - - for (i = 0; i < CONFIG_MAX_TASKS; i++) - { - g_pidhash[i].tcb = NULL; - g_pidhash[i].pid = INVALID_PROCESS_ID; - } - /* Initialize the IDLE task TCB *******************************************/ -#ifdef CONFIG_SMP - for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) -#endif + for (i = 0; i < CONFIG_SMP_NCPUS; i++) { FAR dq_queue_t *tasklist; - int hashndx; - - /* Assign the process ID(s) of ZERO to the idle task(s) */ - - hashndx = PIDHASH(cpu); - g_pidhash[hashndx].tcb = &g_idletcb[cpu].cmn; - g_pidhash[hashndx].pid = cpu; /* Initialize a TCB for this thread of execution. NOTE: The default * value for most components of the g_idletcb are zero. The entire @@ -419,9 +391,9 @@ void nx_start(void) * that has pid == 0 and sched_priority == 0. */ - memset((void *)&g_idletcb[cpu], 0, sizeof(struct task_tcb_s)); - g_idletcb[cpu].cmn.pid = cpu; - g_idletcb[cpu].cmn.task_state = TSTATE_TASK_RUNNING; + memset((void *)&g_idletcb[i], 0, sizeof(struct task_tcb_s)); + g_idletcb[i].cmn.pid = i; + g_idletcb[i].cmn.task_state = TSTATE_TASK_RUNNING; /* Set the entry point. This is only for debug purposes. NOTE: that * the start_t entry point is not saved. That is acceptable, however, @@ -430,16 +402,16 @@ void nx_start(void) */ #ifdef CONFIG_SMP - if (cpu > 0) + if (i > 0) { - g_idletcb[cpu].cmn.start = nx_idle_trampoline; - g_idletcb[cpu].cmn.entry.main = (main_t)nx_idle_trampoline; + g_idletcb[i].cmn.start = nx_idle_trampoline; + g_idletcb[i].cmn.entry.main = (main_t)nx_idle_trampoline; } else #endif { - g_idletcb[cpu].cmn.start = nx_start; - g_idletcb[cpu].cmn.entry.main = (main_t)nx_start; + g_idletcb[i].cmn.start = nx_start; + g_idletcb[i].cmn.entry.main = (main_t)nx_start; } /* Set the task flags to indicate that this is a kernel thread and, if @@ -447,13 +419,13 @@ void nx_start(void) */ #ifdef CONFIG_SMP - g_idletcb[cpu].cmn.flags = (TCB_FLAG_TTYPE_KERNEL | - TCB_FLAG_NONCANCELABLE | - TCB_FLAG_CPU_LOCKED); - g_idletcb[cpu].cmn.cpu = cpu; + g_idletcb[i].cmn.flags = (TCB_FLAG_TTYPE_KERNEL | + TCB_FLAG_NONCANCELABLE | + TCB_FLAG_CPU_LOCKED); + g_idletcb[i].cmn.cpu = i; #else - g_idletcb[cpu].cmn.flags = (TCB_FLAG_TTYPE_KERNEL | - TCB_FLAG_NONCANCELABLE); + g_idletcb[i].cmn.flags = (TCB_FLAG_TTYPE_KERNEL | + TCB_FLAG_NONCANCELABLE); #endif #ifdef CONFIG_SMP @@ -465,18 +437,18 @@ void nx_start(void) * the IDLE task. */ - g_idletcb[cpu].cmn.affinity = SCHED_ALL_CPUS; + g_idletcb[i].cmn.affinity = SCHED_ALL_CPUS; #endif #if CONFIG_TASK_NAME_SIZE > 0 /* Set the IDLE task name */ # ifdef CONFIG_SMP - snprintf(g_idletcb[cpu].cmn.name, CONFIG_TASK_NAME_SIZE, "CPU%d IDLE", - cpu); + snprintf(g_idletcb[i].cmn.name, CONFIG_TASK_NAME_SIZE, "CPU%d IDLE", + i); # else - strncpy(g_idletcb[cpu].cmn.name, g_idlename, CONFIG_TASK_NAME_SIZE); - g_idletcb[cpu].cmn.name[CONFIG_TASK_NAME_SIZE] = '\0'; + strncpy(g_idletcb[i].cmn.name, g_idlename, CONFIG_TASK_NAME_SIZE); + g_idletcb[i].cmn.name[CONFIG_TASK_NAME_SIZE] = '\0'; # endif #endif @@ -489,41 +461,39 @@ void nx_start(void) */ #if CONFIG_TASK_NAME_SIZE > 0 - g_idleargv[cpu][0] = g_idletcb[cpu].cmn.name; + g_idleargv[i][0] = g_idletcb[i].cmn.name; #else - g_idleargv[cpu][0] = (FAR char *)g_idlename; + g_idleargv[i][0] = (FAR char *)g_idlename; #endif /* CONFIG_TASK_NAME_SIZE */ - g_idleargv[cpu][1] = NULL; - g_idletcb[cpu].argv = &g_idleargv[cpu][0]; + g_idleargv[i][1] = NULL; + g_idletcb[i].argv = &g_idleargv[i][0]; /* Then add the idle task's TCB to the head of the current ready to * run list. */ #ifdef CONFIG_SMP - tasklist = TLIST_HEAD(TSTATE_TASK_RUNNING, cpu); + tasklist = TLIST_HEAD(TSTATE_TASK_RUNNING, i); #else tasklist = TLIST_HEAD(TSTATE_TASK_RUNNING); #endif - dq_addfirst((FAR dq_entry_t *)&g_idletcb[cpu], tasklist); + dq_addfirst((FAR dq_entry_t *)&g_idletcb[i], tasklist); /* Mark the idle task as the running task */ - g_running_tasks[cpu] = &g_idletcb[cpu].cmn; + g_running_tasks[i] = &g_idletcb[i].cmn; /* Initialize the 1st processor-specific portion of the TCB * Note: other idle thread get initialized in nx_smpstart */ - if (cpu == 0) + if (i == 0) { - up_initial_state(&g_idletcb[cpu].cmn); - up_stack_frame(&g_idletcb[cpu].cmn, sizeof(struct task_info_s)); + up_initial_state(&g_idletcb[i].cmn); + up_stack_frame(&g_idletcb[i].cmn, sizeof(struct task_info_s)); } } - g_lastpid = cpu ? cpu -1 : 0; - /* Task lists are initialized */ g_nx_initstate = OSINIT_TASKLISTS; @@ -574,8 +544,10 @@ void nx_start(void) } #endif -#ifdef CONFIG_ARCH_USE_MODULE_TEXT - up_module_text_init(); +#ifdef CONFIG_ARCH_HAVE_EXTRA_HEAPS + /* Initialize any extra heap. */ + + up_extraheaps_init(); #endif #ifdef CONFIG_MM_IOB @@ -584,6 +556,36 @@ void nx_start(void) iob_initialize(); #endif + /* Initialize the logic that determine unique process IDs. */ + + g_npidhash = 4; + while (g_npidhash <= CONFIG_SMP_NCPUS) + { + g_npidhash <<= 1; + } + + g_pidhash = kmm_malloc(sizeof(struct pidhash_s) * g_npidhash); + DEBUGASSERT(g_pidhash); + + for (i = 0; i < g_npidhash; i++) + { + g_pidhash[i].tcb = NULL; + g_pidhash[i].pid = INVALID_PROCESS_ID; + } + + for (i = 0; i < CONFIG_SMP_NCPUS; i++) + { + int hashndx; + + /* Assign the process ID(s) of ZERO to the idle task(s) */ + + hashndx = PIDHASH(i); + g_pidhash[hashndx].tcb = &g_idletcb[i].cmn; + g_pidhash[hashndx].pid = i; + } + + g_lastpid = CONFIG_SMP_NCPUS - 1; + /* The memory manager is available */ g_nx_initstate = OSINIT_MEMORY; @@ -714,40 +716,36 @@ void nx_start(void) sched_note_start(&g_idletcb[0].cmn); -#ifdef CONFIG_SMP /* Initialize the IDLE group for the IDLE task of each CPU */ - for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) -#endif + for (i = 0; i < CONFIG_SMP_NCPUS; i++) { /* Allocate the IDLE group */ - DEBUGVERIFY(group_allocate(&g_idletcb[cpu], g_idletcb[cpu].cmn.flags)); + DEBUGVERIFY(group_allocate(&g_idletcb[i], g_idletcb[i].cmn.flags)); -#ifdef CONFIG_SMP - if (cpu > 0) + if (i > 0) { /* Clone stdout, stderr, stdin from the CPU0 IDLE task. */ - DEBUGVERIFY(group_setuptaskfiles(&g_idletcb[cpu])); + DEBUGVERIFY(group_setuptaskfiles(&g_idletcb[i])); } else -#endif { /* Create stdout, stderr, stdin on the CPU0 IDLE task. These * will be inherited by all of the threads created by the CPU0 * IDLE task. */ - DEBUGVERIFY(group_setupidlefiles(&g_idletcb[cpu])); + DEBUGVERIFY(group_setupidlefiles(&g_idletcb[i])); } /* Complete initialization of the IDLE group. Suppress retention * of child status in the IDLE group. */ - DEBUGVERIFY(group_initialize(&g_idletcb[cpu])); - g_idletcb[cpu].cmn.group->tg_flags = GROUP_FLAG_NOCLDWAIT; + DEBUGVERIFY(group_initialize(&g_idletcb[i])); + g_idletcb[i].cmn.group->tg_flags = GROUP_FLAG_NOCLDWAIT; } /* Start SYSLOG ***********************************************************/ @@ -771,7 +769,7 @@ void nx_start(void) /* A few basic sanity checks */ - DEBUGASSERT(this_cpu() == 0 && CONFIG_MAX_TASKS > CONFIG_SMP_NCPUS); + DEBUGASSERT(this_cpu() == 0); /* Then start the other CPUs */ @@ -805,7 +803,7 @@ void nx_start(void) /* Check stack in idle thread */ - for (i = 0; i < CONFIG_MAX_TASKS; i++) + for (i = 0; i < g_npidhash; i++) { FAR struct tcb_s *tcb; irqstate_t flags; diff --git a/sched/irq/irq_chain.c b/sched/irq/irq_chain.c index 358d04640cc..ba83b0befa0 100644 --- a/sched/irq/irq_chain.c +++ b/sched/irq/irq_chain.c @@ -24,6 +24,8 @@ #include +#include + #include "irq/irq.h" /**************************************************************************** diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 8ab676fa1b2..798a222d3ab 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/irq/irq_dispatch.c b/sched/irq/irq_dispatch.c index 1ba89546949..ab984a057cc 100644 --- a/sched/irq/irq_dispatch.c +++ b/sched/irq/irq_dispatch.c @@ -65,6 +65,10 @@ * interrupt request */ +#ifndef CONFIG_SCHED_CRITMONITOR_MAXTIME_IRQ +# define CONFIG_SCHED_CRITMONITOR_MAXTIME_IRQ 0 +#endif + #ifndef CONFIG_SCHED_IRQMONITOR # define CALL_VECTOR(ndx, vector, irq, context, arg) \ vector(irq, context, arg) diff --git a/sched/irq/irq_procfs.c b/sched/irq/irq_procfs.c index 88b6294eef6..edc4b9c1fc5 100644 --- a/sched/irq/irq_procfs.c +++ b/sched/irq/irq_procfs.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/sched/irq/irq_spinlock.c b/sched/irq/irq_spinlock.c index c4558c38fe2..0e41983b3e6 100644 --- a/sched/irq/irq_spinlock.c +++ b/sched/irq/irq_spinlock.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/irq/irq_unexpectedisr.c b/sched/irq/irq_unexpectedisr.c index cbaeaefa8d2..e0c7187211e 100644 --- a/sched/irq/irq_unexpectedisr.c +++ b/sched/irq/irq_unexpectedisr.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/sched/module/mod_modhandle.c b/sched/module/mod_modhandle.c index abcd1838846..67426b30fc4 100644 --- a/sched/module/mod_modhandle.c +++ b/sched/module/mod_modhandle.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/module/mod_rmmod.c b/sched/module/mod_rmmod.c index 61101f8b5ae..490beaf4e6c 100644 --- a/sched/module/mod_rmmod.c +++ b/sched/module/mod_rmmod.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -119,8 +120,8 @@ int rmmod(FAR void *handle) * and nullify so that the memory cannot be freed again */ -#if defined(CONFIG_ARCH_USE_MODULE_TEXT) - up_module_text_free((FAR void *)modp->textalloc); +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) + up_textheap_free((FAR void *)modp->textalloc); #else kmm_free((FAR void *)modp->textalloc); #endif diff --git a/sched/mqueue/mq_initialize.c b/sched/mqueue/mq_initialize.c index a95d05b45a7..2c0febe1114 100644 --- a/sched/mqueue/mq_initialize.c +++ b/sched/mqueue/mq_initialize.c @@ -114,7 +114,7 @@ mq_msgblockalloc(FAR sq_queue_t *queue, uint16_t nmsgs, * Name: nxmq_initialize * * Description: - * This function initializes the messasge system. This function must + * This function initializes the message system. This function must * be called early in the initialization sequence before any of the * other message interfaces execute. * diff --git a/sched/mqueue/mq_msgfree.c b/sched/mqueue/mq_msgfree.c index 92b76e5eaa7..f53f8e9962d 100644 --- a/sched/mqueue/mq_msgfree.c +++ b/sched/mqueue/mq_msgfree.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/sched/mqueue/mq_msgqfree.c b/sched/mqueue/mq_msgqfree.c index c681a797a2d..2b99cc86dd3 100644 --- a/sched/mqueue/mq_msgqfree.c +++ b/sched/mqueue/mq_msgqfree.c @@ -38,12 +38,12 @@ * Description: * This function deallocates an initialized message queue structure. * First, it deallocates all of the queued messages in the message - * queue. It is assumed that this message is fully unlinked and - * closed so that no thread will attempt access it while it is being - * deleted. + * queue. It is assumed that this message queue is fully unlinked + * and closed so that no thread will attempt to access it while it + * is being deleted. * * Input Parameters: - * msgq - Named essage queue to be freed + * msgq - Named message queue to be freed * * Returned Value: * None diff --git a/sched/mqueue/mq_rcvinternal.c b/sched/mqueue/mq_rcvinternal.c index bfc53b44de2..a7b278822b2 100644 --- a/sched/mqueue/mq_rcvinternal.c +++ b/sched/mqueue/mq_rcvinternal.c @@ -59,7 +59,7 @@ * msglen - Size of the buffer in bytes * * Returned Value: - * One success, zero (OK) is returned. A negated errno value is returned + * On success, zero (OK) is returned. A negated errno value is returned * on any failure: * * EPERM Message queue opened not opened for reading. @@ -108,7 +108,7 @@ int nxmq_verify_receive(FAR struct mqueue_inode_s *msgq, * received message. * * Returned Value: - * One success, zero (OK) is returned. A negated errno value is returned + * On success, zero (OK) is returned. A negated errno value is returned * on any failure. * * Assumptions: diff --git a/sched/mqueue/mq_receive.c b/sched/mqueue/mq_receive.c index ad86568bffc..9586e641e89 100644 --- a/sched/mqueue/mq_receive.c +++ b/sched/mqueue/mq_receive.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -203,7 +204,7 @@ ssize_t nxmq_receive(mqd_t mqdes, FAR char *msg, size_t msglen, * prio - If not NULL, the location to store message priority. * * Returned Value: - * One success, the length of the selected message in bytes is returned. + * On success, the length of the selected message in bytes is returned. * On failure, -1 (ERROR) is returned and the errno is set appropriately: * * EAGAIN The queue was empty, and the O_NONBLOCK flag was set diff --git a/sched/mqueue/mq_sndinternal.c b/sched/mqueue/mq_sndinternal.c index 449aec3a394..3c4b6e2d850 100644 --- a/sched/mqueue/mq_sndinternal.c +++ b/sched/mqueue/mq_sndinternal.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -62,7 +63,7 @@ * prio - The priority of the message * * Returned Value: - * One success, 0 (OK) is returned. On failure, a negated errno value is + * On success, 0 (OK) is returned. On failure, a negated errno value is * returned. * * EINVAL Either msg or msgq is NULL or the value of prio is invalid. diff --git a/sched/mqueue/mq_timedreceive.c b/sched/mqueue/mq_timedreceive.c index a0213825ab4..981bcb0636b 100644 --- a/sched/mqueue/mq_timedreceive.c +++ b/sched/mqueue/mq_timedreceive.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -336,7 +337,7 @@ ssize_t nxmq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen, * abstime - the absolute time to wait until a timeout is declared. * * Returned Value: - * One success, the length of the selected message in bytes is returned. + * On success, the length of the selected message in bytes is returned. * On failure, -1 (ERROR) is returned and the errno is set appropriately: * * EAGAIN The queue was empty, and the O_NONBLOCK flag was set diff --git a/sched/mqueue/mq_timedsend.c b/sched/mqueue/mq_timedsend.c index 9735d75aaaf..087b8152ea8 100644 --- a/sched/mqueue/mq_timedsend.c +++ b/sched/mqueue/mq_timedsend.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/sched/mqueue/mq_waitirq.c b/sched/mqueue/mq_waitirq.c index 8582cc7ff0b..9f2a014d83b 100644 --- a/sched/mqueue/mq_waitirq.c +++ b/sched/mqueue/mq_waitirq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/paging/pg_miss.c b/sched/paging/pg_miss.c index 452014b50d5..5aebffc35b2 100644 --- a/sched/paging/pg_miss.c +++ b/sched/paging/pg_miss.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index 2a3b58dba52..681fe3ec3a5 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -38,10 +38,6 @@ ifeq ($(CONFIG_SMP),y) CSRCS += pthread_setaffinity.c pthread_getaffinity.c endif -ifeq ($(CONFIG_PTHREAD_CLEANUP),y) -CSRCS += pthread_cleanup.c -endif - # Include pthread build support DEPPATH += --dep-path pthread diff --git a/sched/pthread/pthread.h b/sched/pthread/pthread.h index b309a502cad..8a3317a5f70 100644 --- a/sched/pthread/pthread.h +++ b/sched/pthread/pthread.h @@ -82,10 +82,6 @@ struct task_group_s; /* Forward reference */ int pthread_setup_scheduler(FAR struct pthread_tcb_s *tcb, int priority, start_t start, pthread_startroutine_t entry); -#ifdef CONFIG_PTHREAD_CLEANUP -void pthread_cleanup_popall(FAR struct tcb_s *tcb); -#endif - int pthread_completejoin(pid_t pid, FAR void *exit_value); void pthread_destroyjoin(FAR struct task_group_s *group, FAR struct join_s *pjoin); diff --git a/sched/pthread/pthread_cancel.c b/sched/pthread/pthread_cancel.c index dcc58f6390f..22d35f3e076 100644 --- a/sched/pthread/pthread_cancel.c +++ b/sched/pthread/pthread_cancel.c @@ -24,9 +24,12 @@ #include +#include + #include #include #include +#include #include #include "sched/sched.h" @@ -82,21 +85,15 @@ int pthread_cancel(pthread_t thread) if (tcb == this_task()) { + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + tcb->flags |= TCB_FLAG_CANCEL_DOING; +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) + up_pthread_exit(((FAR struct pthread_tcb_s *)tcb)->exit, + PTHREAD_CANCELED); +#else pthread_exit(PTHREAD_CANCELED); - } - -#ifdef CONFIG_PTHREAD_CLEANUP - /* Perform any stack pthread clean-up callbacks. - * - * REVISIT: In this case, the clean-up callback will execute on the - * thread of the caller of pthread cancel, not on the thread of - * the thread-to-be-canceled. This is a problem when deferred - * cancellation is not supported because, for example, the clean-up - * function will be unable to unlock its own mutexes. - */ - - pthread_cleanup_popall(tcb); #endif + } /* Complete pending join operations */ diff --git a/sched/pthread/pthread_completejoin.c b/sched/pthread/pthread_completejoin.c index 2681755e98d..26c784f936b 100644 --- a/sched/pthread/pthread_completejoin.c +++ b/sched/pthread/pthread_completejoin.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/pthread/pthread_create.c b/sched/pthread/pthread_create.c index 1c4af3b9b92..aa88c8ae3c0 100644 --- a/sched/pthread/pthread_create.c +++ b/sched/pthread/pthread_create.c @@ -64,41 +64,47 @@ const pthread_attr_t g_default_pthread_attr = PTHREAD_ATTR_INITIALIZER; ****************************************************************************/ /**************************************************************************** - * Name: pthread_argsetup + * Name: pthread_tcb_setup * * Description: - * This functions sets up parameters in the Task Control Block (TCB) in + * This function sets up parameters in the Task Control Block (TCB) in * preparation for starting a new thread. * - * pthread_argsetup() is called from nxtask_init() and nxtask_start() to + * pthread_tcb_setup() is called from nxtask_init() and nxtask_start() to * create a new task (with arguments cloned via strdup) or pthread_create() * which has one argument passed by value (distinguished by the pthread * boolean argument). * * Input Parameters: * tcb - Address of the new task's TCB + * trampoline - User space pthread startup function * arg - The argument to provide to the pthread on startup. + * exit - The user-space pthread exit function * * Returned Value: * None * ****************************************************************************/ -static inline void pthread_argsetup(FAR struct pthread_tcb_s *tcb, - pthread_addr_t arg) +static inline void pthread_tcb_setup(FAR struct pthread_tcb_s *ptcb, + pthread_trampoline_t trampoline, + pthread_addr_t arg, + pthread_exitroutine_t exit) { #if CONFIG_TASK_NAME_SIZE > 0 /* Copy the pthread name into the TCB */ - snprintf(tcb->cmn.name, CONFIG_TASK_NAME_SIZE, - "pt-%p", tcb->cmn.entry.pthread); + snprintf(ptcb->cmn.name, CONFIG_TASK_NAME_SIZE, + "pt-%p", ptcb->cmn.entry.pthread); #endif /* CONFIG_TASK_NAME_SIZE */ /* For pthreads, args are strictly pass-by-value; that actual * type wrapped by pthread_addr_t is unknown. */ - tcb->arg = arg; + ptcb->trampoline = trampoline; + ptcb->arg = arg; + ptcb->exit = exit; } /**************************************************************************** @@ -150,9 +156,8 @@ static void pthread_start(void) FAR struct pthread_tcb_s *ptcb = (FAR struct pthread_tcb_s *)this_task(); FAR struct task_group_s *group = ptcb->cmn.group; FAR struct join_s *pjoin = (FAR struct join_s *)ptcb->joininfo; - pthread_addr_t exit_status; - DEBUGASSERT(group && pjoin); + DEBUGASSERT(group != NULL && pjoin != NULL); /* Successfully spawned, add the pjoin to our data set. */ @@ -180,16 +185,23 @@ static void pthread_start(void) * to switch to user-mode before calling into the pthread. */ + DEBUGASSERT(ptcb->trampoline != NULL && ptcb->cmn.entry.pthread != NULL); + #ifdef CONFIG_BUILD_FLAT - exit_status = (*ptcb->cmn.entry.pthread)(ptcb->arg); + ptcb->trampoline(ptcb->cmn.entry.pthread, ptcb->arg); #else - up_pthread_start(ptcb->cmn.entry.pthread, ptcb->arg); - exit_status = NULL; + up_pthread_start(ptcb->trampoline, ptcb->cmn.entry.pthread, ptcb->arg); #endif - /* The thread has returned (should never happen in the kernel mode case) */ + /* The thread has returned (should never happen) */ - pthread_exit(exit_status); + DEBUGPANIC(); +#ifndef CONFIG_BUILD_FLAT + ptcb->cmn.flags &= ~TCB_FLAG_CANCEL_PENDING; + ptcb->cmn.flags |= TCB_FLAG_CANCEL_DOING; + + up_pthread_exit(ptcb->exit, NULL); +#endif } /**************************************************************************** @@ -197,17 +209,21 @@ static void pthread_start(void) ****************************************************************************/ /**************************************************************************** - * Name: pthread_create + * Name: nx_pthread_create * * Description: - * This function creates and activates a new thread with a specified + * This function creates and activates a new thread with specified * attributes. * * Input Parameters: - * thread - * attr - * start_routine - * arg + * trampoline - The user space startup function + * thread - The pthread handle to be used + * attr - It points to a pthread_attr_t structure whose contents are + * used at thread creation time to determine attributes + * for the new thread + * entry - The new thread starts execution by invoking entry + * arg - It is passed as the sole argument of entry + * exit - The user-space pthread exit function * * Returned Value: * OK (0) on success; a (non-negated) errno value on failure. The errno @@ -215,8 +231,10 @@ static void pthread_start(void) * ****************************************************************************/ -int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, - pthread_startroutine_t start_routine, pthread_addr_t arg) +int nx_pthread_create(pthread_trampoline_t trampoline, FAR pthread_t *thread, + FAR const pthread_attr_t *attr, + pthread_startroutine_t entry, pthread_addr_t arg, + pthread_exitroutine_t exit) { FAR struct pthread_tcb_s *ptcb; FAR struct tls_info_s *info; @@ -228,6 +246,9 @@ int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, int ret; bool group_joined = false; + DEBUGASSERT(trampoline != NULL); + DEBUGASSERT(exit != NULL); + /* If attributes were not supplied, use the default attributes */ if (!attr) @@ -315,6 +336,10 @@ int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, DEBUGASSERT(info == ptcb->cmn.stack_alloc_ptr); + /* Attach per-task info in group to TLS */ + + info->tl_task = ptcb->cmn.group->tg_info; + /* Should we use the priority and scheduler specified in the pthread * attributes? Or should we use the current thread's priority and * scheduler? @@ -415,7 +440,7 @@ int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, /* Initialize the task control block */ ret = pthread_setup_scheduler(ptcb, param.sched_priority, pthread_start, - start_routine); + entry); if (ret != OK) { errcode = EBUSY; @@ -440,7 +465,7 @@ int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, * passed by value */ - pthread_argsetup(ptcb, arg); + pthread_tcb_setup(ptcb, trampoline, arg, exit); /* Join the parent's task group */ diff --git a/sched/pthread/pthread_exit.c b/sched/pthread/pthread_exit.c index bc6086fced9..8ef8ee7e6e4 100644 --- a/sched/pthread/pthread_exit.c +++ b/sched/pthread/pthread_exit.c @@ -29,11 +29,13 @@ #include #include #include +#include #include #include #include #include +#include #include "sched/sched.h" #include "task/task.h" @@ -50,7 +52,7 @@ * Terminate execution of a thread started with pthread_create. * * Input Parameters: - * exit_valie + * exit_value * * Returned Value: * None @@ -59,7 +61,7 @@ * ****************************************************************************/ -void pthread_exit(FAR void *exit_value) +void nx_pthread_exit(FAR void *exit_value) { FAR struct tcb_s *tcb = this_task(); sigset_t set = ALL_SIGNAL_SET; @@ -87,12 +89,6 @@ void pthread_exit(FAR void *exit_value) tcb->cpcount = 0; #endif -#ifdef CONFIG_PTHREAD_CLEANUP - /* Perform any stack pthread clean-up callbacks */ - - pthread_cleanup_popall(tcb); -#endif - /* Complete pending join operations */ status = pthread_completejoin(getpid(), exit_value); diff --git a/sched/pthread/pthread_findjoininfo.c b/sched/pthread/pthread_findjoininfo.c index d9d9cc71142..181b480b762 100644 --- a/sched/pthread/pthread_findjoininfo.c +++ b/sched/pthread/pthread_findjoininfo.c @@ -25,6 +25,7 @@ #include #include +#include #include "group/group.h" #include "pthread/pthread.h" diff --git a/sched/pthread/pthread_getaffinity.c b/sched/pthread/pthread_getaffinity.c index 28f4dc62ae6..a4ed14e7075 100644 --- a/sched/pthread/pthread_getaffinity.c +++ b/sched/pthread/pthread_getaffinity.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/sched/pthread/pthread_join.c b/sched/pthread/pthread_join.c index 328708bc31e..f200461b3e3 100644 --- a/sched/pthread/pthread_join.c +++ b/sched/pthread/pthread_join.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/pthread/pthread_mutexconsistent.c b/sched/pthread/pthread_mutexconsistent.c index 2020cba30ac..48fb5f52a01 100644 --- a/sched/pthread/pthread_mutexconsistent.c +++ b/sched/pthread/pthread_mutexconsistent.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/pthread/pthread_mutexdestroy.c b/sched/pthread/pthread_mutexdestroy.c index 8f9de588dc5..a6d9f9efd4c 100644 --- a/sched/pthread/pthread_mutexdestroy.c +++ b/sched/pthread/pthread_mutexdestroy.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/pthread/pthread_release.c b/sched/pthread/pthread_release.c index 16d43e81b50..5c55427de4d 100644 --- a/sched/pthread/pthread_release.c +++ b/sched/pthread/pthread_release.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/pthread/pthread_setaffinity.c b/sched/pthread/pthread_setaffinity.c index 3b8d1c51a2c..d383542f21b 100644 --- a/sched/pthread/pthread_setaffinity.c +++ b/sched/pthread/pthread_setaffinity.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/sched/sched/sched.h b/sched/sched/sched.h index 00334cbc6cd..b87c0107db3 100644 --- a/sched/sched/sched.h +++ b/sched/sched/sched.h @@ -40,20 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Although task IDs can take the (positive, non-zero) - * range of pid_t, the number of tasks that will be supported - * at any one time is (artificially) limited by the CONFIG_MAX_TASKS - * configuration setting. Limiting the number of tasks speeds certain - * OS functions (this is the only limitation in the number of - * tasks built into the design). - */ - -#if CONFIG_MAX_TASKS & (CONFIG_MAX_TASKS - 1) -# error CONFIG_MAX_TASKS must be power of 2 -#endif - -#define MAX_TASKS_MASK (CONFIG_MAX_TASKS-1) -#define PIDHASH(pid) ((pid) & MAX_TASKS_MASK) +#define PIDHASH(pid) ((pid) & (g_npidhash - 1)) /* These are macros to access the current CPU and the current task on a CPU. * These macros are intended to support a future SMP implementation. @@ -254,12 +241,11 @@ extern volatile pid_t g_lastpid; * 1. This hash table greatly speeds the determination of a new unique * process ID for a task, and * 2. Is used to quickly map a process ID into a TCB. - * - * It has the side effects of using more memory and limiting the number - * of tasks to CONFIG_MAX_TASKS. */ -extern struct pidhash_s g_pidhash[CONFIG_MAX_TASKS]; +extern FAR struct pidhash_s *g_pidhash; + +extern volatile int g_npidhash; /* This is a table of task lists. This table is indexed by the task stat * enumeration type (tstate_t) and provides a pointer to the associated diff --git a/sched/sched/sched_cpuload.c b/sched/sched/sched_cpuload.c index dcd9deb2f6a..5a16b708606 100644 --- a/sched/sched/sched_cpuload.c +++ b/sched/sched/sched_cpuload.c @@ -160,13 +160,13 @@ static inline void nxsched_cpu_process_cpuload(int cpu) void weak_function nxsched_process_cpuload(void) { int i; - -#ifdef CONFIG_SMP irqstate_t flags; /* Perform scheduler operations on all CPUs. */ flags = enter_critical_section(); + +#ifdef CONFIG_SMP for (i = 0; i < CONFIG_SMP_NCPUS; i++) { nxsched_cpu_process_cpuload(i); @@ -191,7 +191,7 @@ void weak_function nxsched_process_cpuload(void) * total. */ - for (i = 0; i < CONFIG_MAX_TASKS; i++) + for (i = 0; i < g_npidhash; i++) { g_pidhash[i].ticks >>= 1; total += g_pidhash[i].ticks; @@ -202,9 +202,7 @@ void weak_function nxsched_process_cpuload(void) g_cpuload_total = total; } -#ifdef CONFIG_SMP leave_critical_section(flags); -#endif } /**************************************************************************** @@ -230,7 +228,7 @@ void weak_function nxsched_process_cpuload(void) int clock_cpuload(int pid, FAR struct cpuload_s *cpuload) { irqstate_t flags; - int hash_index = PIDHASH(pid); + int hash_index; int ret = -ESRCH; DEBUGASSERT(cpuload); @@ -241,6 +239,7 @@ int clock_cpuload(int pid, FAR struct cpuload_s *cpuload) */ flags = enter_critical_section(); + hash_index = PIDHASH(pid); /* Make sure that the entry is valid (TCB field is not NULL) and matches * the requested PID. The first check is needed if the thread has exited. diff --git a/sched/sched/sched_critmonitor.c b/sched/sched/sched_critmonitor.c index a9a3268f676..76a1656456e 100644 --- a/sched/sched/sched_critmonitor.c +++ b/sched/sched/sched_critmonitor.c @@ -26,6 +26,7 @@ #include #include +#include #include "sched/sched.h" @@ -35,6 +36,18 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_SCHED_CRITMONITOR_MAXTIME_PREEMPTION +# define CONFIG_SCHED_CRITMONITOR_MAXTIME_PREEMPTION 0 +#endif + +#ifndef CONFIG_SCHED_CRITMONITOR_MAXTIME_CSECTION +# define CONFIG_SCHED_CRITMONITOR_MAXTIME_CSECTION 0 +#endif + +#ifndef CONFIG_SCHED_CRITMONITOR_MAXTIME_THREAD +# define CONFIG_SCHED_CRITMONITOR_MAXTIME_THREAD 0 +#endif + #if CONFIG_SCHED_CRITMONITOR_MAXTIME_PREEMPTION > 0 # define CHECK_PREEMPTION(pid, elapsed) \ do \ diff --git a/sched/sched/sched_foreach.c b/sched/sched/sched_foreach.c index dc7a8eea163..0a074cb42be 100644 --- a/sched/sched/sched_foreach.c +++ b/sched/sched/sched_foreach.c @@ -62,16 +62,16 @@ void nxsched_foreach(nxsched_foreach_t handler, FAR void *arg) /* Visit each active task */ - for (ndx = 0; ndx < CONFIG_MAX_TASKS; ndx++) + flags = enter_critical_section(); + for (ndx = 0; ndx < g_npidhash; ndx++) { /* This test and the function call must be atomic */ - flags = enter_critical_section(); if (g_pidhash[ndx].tcb) { handler(g_pidhash[ndx].tcb, arg); } - - leave_critical_section(flags); } + + leave_critical_section(flags); } diff --git a/sched/sched/sched_get_stackinfo.c b/sched/sched/sched_get_stackinfo.c index 7d6bda0ae34..ab5edd94097 100644 --- a/sched/sched/sched_get_stackinfo.c +++ b/sched/sched/sched_get_stackinfo.c @@ -69,16 +69,6 @@ int nxsched_get_stackinfo(pid_t pid, FAR struct stackinfo_s *stackinfo) qtcb = rtcb; } - else if (pid == -1) - { - /* We can always query our main thread */ - - qtcb = nxsched_get_tcb(rtcb->group->tg_pid); - if (qtcb == NULL) - { - return -ENOENT; - } - } else { /* Get the task to be queried */ diff --git a/sched/sched/sched_getparam.c b/sched/sched/sched_getparam.c index 39f49698969..fd196be53b2 100644 --- a/sched/sched/sched_getparam.c +++ b/sched/sched/sched_getparam.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/sched/sched_getstreams.c b/sched/sched/sched_getstreams.c index 17ec8e71abe..481149dd5d1 100644 --- a/sched/sched/sched_getstreams.c +++ b/sched/sched/sched_getstreams.c @@ -24,6 +24,8 @@ #include #include +#include + #include "sched/sched.h" #ifdef CONFIG_FILE_STREAM diff --git a/sched/sched/sched_gettcb.c b/sched/sched/sched_gettcb.c index a43ad63c41e..9b31aa2404d 100644 --- a/sched/sched/sched_gettcb.c +++ b/sched/sched/sched_gettcb.c @@ -60,10 +60,6 @@ FAR struct tcb_s *nxsched_get_tcb(pid_t pid) if (pid >= 0) { - /* Get the hash_ndx associated with the pid */ - - hash_ndx = PIDHASH(pid); - /* The test and the return setup should be atomic. This still does * not provide proper protection if the recipient of the TCB does not * also protect against the task associated with the TCB from @@ -72,6 +68,10 @@ FAR struct tcb_s *nxsched_get_tcb(pid_t pid) flags = enter_critical_section(); + /* Get the hash_ndx associated with the pid */ + + hash_ndx = PIDHASH(pid); + /* Verify that the correct TCB was found. */ if (pid == g_pidhash[hash_ndx].pid) diff --git a/sched/sched/sched_idletask.c b/sched/sched/sched_idletask.c index bda337967aa..c48b0f43f43 100644 --- a/sched/sched/sched_idletask.c +++ b/sched/sched/sched_idletask.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/sched/sched_releasetcb.c b/sched/sched/sched_releasetcb.c index d46bb21a60e..1f95c4e1ba4 100644 --- a/sched/sched/sched_releasetcb.c +++ b/sched/sched/sched_releasetcb.c @@ -48,6 +48,7 @@ static void nxsched_releasepid(pid_t pid) { + irqstate_t flags = enter_critical_section(); int hash_ndx = PIDHASH(pid); /* Make any pid associated with this hash available. Note: @@ -67,6 +68,8 @@ static void nxsched_releasepid(pid_t pid) g_cpuload_total -= g_pidhash[hash_ndx].ticks; g_pidhash[hash_ndx].ticks = 0; #endif + + leave_critical_section(flags); } /**************************************************************************** diff --git a/sched/sched/sched_setpriority.c b/sched/sched/sched_setpriority.c index 7487962a58b..842926fc7df 100644 --- a/sched/sched/sched_setpriority.c +++ b/sched/sched/sched_setpriority.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/sched/sched_sporadic.c b/sched/sched/sched_sporadic.c index 0beb70d0beb..190412db37e 100644 --- a/sched/sched/sched_sporadic.c +++ b/sched/sched/sched_sporadic.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/sched/sched/sched_unlock.c b/sched/sched/sched_unlock.c index 3991b16f521..a3b25f6db4d 100644 --- a/sched/sched/sched_unlock.c +++ b/sched/sched/sched_unlock.c @@ -24,6 +24,8 @@ #include +#include + #include #include #include diff --git a/sched/sched/sched_verifytcb.c b/sched/sched/sched_verifytcb.c index 3d10d24c49a..82db055e31f 100644 --- a/sched/sched/sched_verifytcb.c +++ b/sched/sched/sched_verifytcb.c @@ -68,5 +68,12 @@ bool nxsched_verify_tcb(FAR struct tcb_s *tcb) * information available. */ - return tcb == g_pidhash[PIDHASH(tcb->pid)].tcb; + irqstate_t flags; + bool vaild; + + flags = enter_critical_section(); + vaild = tcb == g_pidhash[PIDHASH(tcb->pid)].tcb; + leave_critical_section(flags); + + return vaild; } diff --git a/sched/sched/sched_waitid.c b/sched/sched/sched_waitid.c index 47de010bad8..543a2a7e4b2 100644 --- a/sched/sched/sched_waitid.c +++ b/sched/sched/sched_waitid.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/sched/sched_waitpid.c b/sched/sched/sched_waitpid.c index 06798c73002..d13b718964a 100644 --- a/sched/sched/sched_waitpid.c +++ b/sched/sched/sched_waitpid.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/semaphore/sem_clockwait.c b/sched/semaphore/sem_clockwait.c index 7269bfa8447..c27c110b870 100644 --- a/sched/semaphore/sem_clockwait.c +++ b/sched/semaphore/sem_clockwait.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/semaphore/sem_recover.c b/sched/semaphore/sem_recover.c index f3a4cf1db0d..1f28f54b02b 100644 --- a/sched/semaphore/sem_recover.c +++ b/sched/semaphore/sem_recover.c @@ -24,6 +24,8 @@ #include +#include + #include #include #include diff --git a/sched/semaphore/sem_tickwait.c b/sched/semaphore/sem_tickwait.c index 15e7f18ce8f..7cc4e042878 100644 --- a/sched/semaphore/sem_tickwait.c +++ b/sched/semaphore/sem_tickwait.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/semaphore/sem_timedwait.c b/sched/semaphore/sem_timedwait.c index c072fc80993..dc9711efe75 100644 --- a/sched/semaphore/sem_timedwait.c +++ b/sched/semaphore/sem_timedwait.c @@ -22,6 +22,8 @@ * Included Files ****************************************************************************/ +#include + #include /**************************************************************************** diff --git a/sched/semaphore/sem_trywait.c b/sched/semaphore/sem_trywait.c index 9608f2ee4b7..3648aac26c1 100644 --- a/sched/semaphore/sem_trywait.c +++ b/sched/semaphore/sem_trywait.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/semaphore/sem_waitirq.c b/sched/semaphore/sem_waitirq.c index 2dfaf2e783c..08170b55ccf 100644 --- a/sched/semaphore/sem_waitirq.c +++ b/sched/semaphore/sem_waitirq.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/signal/sig_action.c b/sched/signal/sig_action.c index b657ff686c9..312d07ef09e 100644 --- a/sched/signal/sig_action.c +++ b/sched/signal/sig_action.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/sched/signal/sig_default.c b/sched/signal/sig_default.c index 6ea3887d244..5f4ad913379 100644 --- a/sched/signal/sig_default.c +++ b/sched/signal/sig_default.c @@ -224,7 +224,14 @@ static void nxsig_abnormal_termination(int signo) * REVISIT: This will not work if HAVE_GROUP_MEMBERS is not set. */ - pthread_exit(NULL); + rtcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + rtcb->flags |= TCB_FLAG_CANCEL_DOING; +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) + up_pthread_exit(((FAR struct pthread_tcb_s *)rtcb)->exit, + PTHREAD_CANCELED); +#else + pthread_exit(PTHREAD_CANCELED); +#endif } else #endif diff --git a/sched/signal/sig_dispatch.c b/sched/signal/sig_dispatch.c index a07fd0e768a..1b5edb3ee30 100644 --- a/sched/signal/sig_dispatch.c +++ b/sched/signal/sig_dispatch.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/sched/signal/sig_notification.c b/sched/signal/sig_notification.c index 2c0cf3c984a..19efd5bb0cc 100644 --- a/sched/signal/sig_notification.c +++ b/sched/signal/sig_notification.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/signal/sig_pending.c b/sched/signal/sig_pending.c index 0726d2cadcc..50a006db37f 100644 --- a/sched/signal/sig_pending.c +++ b/sched/signal/sig_pending.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/task/exit.c b/sched/task/exit.c index 16fbceff1e4..97d0b7a05b3 100644 --- a/sched/task/exit.c +++ b/sched/task/exit.c @@ -87,12 +87,6 @@ void exit(int status) group_kill_children(tcb); #endif -#ifdef CONFIG_PTHREAD_CLEANUP - /* Perform any stack pthread clean-up callbacks */ - - pthread_cleanup_popall(tcb); -#endif - #if !defined(CONFIG_DISABLE_PTHREAD) && !defined(CONFIG_PTHREAD_MUTEX_UNSAFE) /* Recover any mutexes still held by the canceled thread */ diff --git a/sched/task/task_cancelpt.c b/sched/task/task_cancelpt.c index 8fcada35693..c7c393f015c 100644 --- a/sched/task/task_cancelpt.c +++ b/sched/task/task_cancelpt.c @@ -53,10 +53,12 @@ #include #include +#include #include #include #include +#include #include "sched/sched.h" #include "semaphore/semaphore.h" @@ -139,7 +141,14 @@ bool enter_cancellation_point(void) if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) { + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + tcb->flags |= TCB_FLAG_CANCEL_DOING; +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) + up_pthread_exit(((FAR struct pthread_tcb_s *)tcb)->exit, + PTHREAD_CANCELED); +#else pthread_exit(PTHREAD_CANCELED); +#endif } else #endif @@ -226,7 +235,14 @@ void leave_cancellation_point(void) if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) { + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + tcb->flags |= TCB_FLAG_CANCEL_DOING; +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) + up_pthread_exit(((FAR struct pthread_tcb_s *)tcb)->exit, + PTHREAD_CANCELED); +#else pthread_exit(PTHREAD_CANCELED); +#endif } else #endif diff --git a/sched/task/task_delete.c b/sched/task/task_delete.c index 1e1d7c5f82c..39608eb0339 100644 --- a/sched/task/task_delete.c +++ b/sched/task/task_delete.c @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index f216e3f5be8..ce939b3a22f 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/task/task_init.c b/sched/task/task_init.c index ba34b93bc6a..7a757fedd10 100644 --- a/sched/task/task_init.c +++ b/sched/task/task_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -85,7 +86,7 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, main_t entry, FAR char * const argv[]) { uint8_t ttype = tcb->cmn.flags & TCB_FLAG_TTYPE_MASK; - FAR struct task_info_s *info; + FAR struct tls_info_s *info; int ret; #ifndef CONFIG_DISABLE_PTHREAD @@ -121,7 +122,7 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, /* Allocate the stack for the TCB */ ret = up_create_stack(&tcb->cmn, - sizeof(struct task_info_s) + stack_size, + sizeof(struct tls_info_s) + stack_size, ttype); } @@ -132,7 +133,7 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, /* Initialize thread local storage */ - info = up_stack_frame(&tcb->cmn, sizeof(struct task_info_s)); + info = up_stack_frame(&tcb->cmn, sizeof(struct tls_info_s)); if (info == NULL) { ret = -ENOMEM; @@ -141,6 +142,8 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, DEBUGASSERT(info == tcb->cmn.stack_alloc_ptr); + info->tl_task = tcb->cmn.group->tg_info; + /* Initialize the task control block */ ret = nxtask_setup_scheduler(tcb, priority, nxtask_start, diff --git a/sched/task/task_posixspawn.c b/sched/task/task_posixspawn.c index 7e56eb3cd29..2f09bdf0871 100644 --- a/sched/task/task_posixspawn.c +++ b/sched/task/task_posixspawn.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/task/task_reparent.c b/sched/task/task_reparent.c index e1254b324aa..e6c725332e2 100644 --- a/sched/task/task_reparent.c +++ b/sched/task/task_reparent.c @@ -24,6 +24,7 @@ #include +#include #include #include diff --git a/sched/task/task_setcancelstate.c b/sched/task/task_setcancelstate.c index bb08b542c37..63f3ef3fa25 100644 --- a/sched/task/task_setcancelstate.c +++ b/sched/task/task_setcancelstate.c @@ -112,7 +112,14 @@ int task_setcancelstate(int state, FAR int *oldstate) if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) { + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + tcb->flags |= TCB_FLAG_CANCEL_DOING; +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) + up_pthread_exit(((FAR struct pthread_tcb_s *)tcb)->exit, + PTHREAD_CANCELED); +#else pthread_exit(PTHREAD_CANCELED); +#endif } else #endif diff --git a/sched/task/task_setcanceltype.c b/sched/task/task_setcanceltype.c index b14fec53e0d..f33aeb1fc5d 100644 --- a/sched/task/task_setcanceltype.c +++ b/sched/task/task_setcanceltype.c @@ -100,7 +100,14 @@ int task_setcanceltype(int type, FAR int *oldtype) #ifndef CONFIG_DISABLE_PTHREAD if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) { + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + tcb->flags |= TCB_FLAG_CANCEL_DOING; +#if !defined(CONFIG_BUILD_FLAT) && defined(__KERNEL__) + up_pthread_exit(((FAR struct pthread_tcb_s *)tcb)->exit, + PTHREAD_CANCELED); +#else pthread_exit(PTHREAD_CANCELED); +#endif } else #endif diff --git a/sched/task/task_setup.c b/sched/task/task_setup.c index afb8b92df94..c9e9eb73d74 100644 --- a/sched/task/task_setup.c +++ b/sched/task/task_setup.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -78,10 +79,10 @@ static const char g_noname[] = ""; static int nxtask_assign_pid(FAR struct tcb_s *tcb) { + FAR struct pidhash_s *pidhash; pid_t next_pid; int hash_ndx; - int tries; - int ret = ERROR; + int i; /* NOTE: * ERROR means that the g_pidhash[] table is completely full. @@ -96,17 +97,17 @@ static int nxtask_assign_pid(FAR struct tcb_s *tcb) /* We'll try every allowable pid */ - for (tries = 0; tries < CONFIG_MAX_TASKS; tries++) +retry: + + /* Get the next process ID candidate */ + + next_pid = g_lastpid + 1; + for (i = 0; i < g_npidhash; i++) { - /* Get the next process ID candidate */ - - next_pid = ++g_lastpid; - /* Verify that the next_pid is in the valid range */ if (next_pid <= 0) { - g_lastpid = 1; next_pid = 1; } @@ -126,16 +127,57 @@ static int nxtask_assign_pid(FAR struct tcb_s *tcb) g_pidhash[hash_ndx].ticks = 0; #endif tcb->pid = next_pid; + g_lastpid = next_pid; - ret = OK; - goto out; + leave_critical_section(flags); + return OK; } + + next_pid++; } -out: + /* If we get here, then the g_pidhash[] table is completely full. + * We will alloc new space and copy original g_pidhash to it to + * expand space. + */ - leave_critical_section(flags); - return ret; + pidhash = kmm_malloc(g_npidhash * 2 * sizeof(struct pidhash_s)); + if (pidhash == NULL) + { + leave_critical_section(flags); + return -ENOMEM; + } + + g_npidhash *= 2; + + /* Reset the new hash table to the initial state */ + + for (i = 0; i < g_npidhash; i++) + { + pidhash[i].tcb = NULL; + pidhash[i].pid = INVALID_PROCESS_ID; + } + + /* All original pid and hash_ndx are mismatch, + * so we need to rebuild their relationship + */ + + for (i = 0; i < g_npidhash / 2; i++) + { + hash_ndx = PIDHASH(g_pidhash[i].pid); + DEBUGASSERT(pidhash[hash_ndx].tcb == NULL); + pidhash[hash_ndx].tcb = g_pidhash[i].tcb; + pidhash[hash_ndx].pid = g_pidhash[i].pid; + } + + /* Release resource for original g_pidhash, using new g_pidhash */ + + kmm_free(g_pidhash); + g_pidhash = pidhash; + + /* Let's try every allowable pid again */ + + goto retry; } /**************************************************************************** diff --git a/sched/task/task_spawn.c b/sched/task/task_spawn.c index 97d1df0986c..d5740c1eb7c 100644 --- a/sched/task/task_spawn.c +++ b/sched/task/task_spawn.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -311,7 +312,7 @@ int task_spawn(FAR const char *name, main_t entry, { struct sched_param param; pid_t proxy; - pid_t pid; + pid_t pid = INVALID_PROCESS_ID; #ifdef CONFIG_SCHED_WAITPID int status; #endif @@ -373,6 +374,7 @@ int task_spawn(FAR const char *name, main_t entry, if (ret < 0) { serr("ERROR: nxsched_get_param failed: %d\n", ret); + g_spawn_parms.pid = NULL; spawn_semgive(&g_spawn_parmsem); return ret; } @@ -441,6 +443,7 @@ errout_with_lock: #ifdef CONFIG_SCHED_WAITPID sched_unlock(); #endif + g_spawn_parms.pid = NULL; spawn_semgive(&g_spawn_parmsem); return ret; } diff --git a/sched/task/task_spawnparms.c b/sched/task/task_spawnparms.c index 970ea8731f4..eb2e44f745d 100644 --- a/sched/task/task_spawnparms.c +++ b/sched/task/task_spawnparms.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/task/task_start.c b/sched/task/task_start.c index 7d94386266c..bbc5abe314c 100644 --- a/sched/task/task_start.c +++ b/sched/task/task_start.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/sched/task/task_starthook.c b/sched/task/task_starthook.c index 924f3516536..00e39c64dda 100644 --- a/sched/task/task_starthook.c +++ b/sched/task/task_starthook.c @@ -24,6 +24,7 @@ #include +#include #include #include "task/task.h" diff --git a/sched/timer/timer_settime.c b/sched/timer/timer_settime.c index 1aa0c416982..d32ee9df167 100644 --- a/sched/timer/timer_settime.c +++ b/sched/timer/timer_settime.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/sched/wdog/wd_start.c b/sched/wdog/wd_start.c index 9b6d09e80db..d285fc72ece 100644 --- a/sched/wdog/wd_start.c +++ b/sched/wdog/wd_start.c @@ -50,6 +50,10 @@ # define MAX(a,b) (((a) > (b)) ? (a) : (b)) #endif +#ifndef CONFIG_SCHED_CRITMONITOR_MAXTIME_WDOG +# define CONFIG_SCHED_CRITMONITOR_MAXTIME_WDOG 0 +#endif + #if CONFIG_SCHED_CRITMONITOR_MAXTIME_WDOG > 0 # define CALL_FUNC(func, arg) \ do \ diff --git a/sched/wqueue/kwork_inherit.c b/sched/wqueue/kwork_inherit.c index e1d0762c6e1..2acfeb65754 100644 --- a/sched/wqueue/kwork_inherit.c +++ b/sched/wqueue/kwork_inherit.c @@ -25,6 +25,8 @@ #include #include +#include +#include #include #include diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 0d16c92042c..0f96f4ed959 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -66,6 +66,8 @@ "munmap","sys/mman.h","defined(CONFIG_FS_RAMMAP)","int","FAR void *","size_t" "nx_mkfifo","nuttx/fs/fs.h","defined(CONFIG_PIPES) && CONFIG_DEV_FIFO_SIZE > 0","int","FAR const char *","mode_t","size_t" "nx_pipe","nuttx/fs/fs.h","defined(CONFIG_PIPES) && CONFIG_DEV_PIPE_SIZE > 0","int","int [2]|FAR int *","size_t","int" +"nx_pthread_create","nuttx/pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_trampoline_t","FAR pthread_t *","FAR const pthread_attr_t *","pthread_startroutine_t","pthread_addr_t","pthread_exitroutine_t" +"nx_pthread_exit","nuttx/pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","noreturn","pthread_addr_t" "nx_vsyslog","nuttx/syslog/syslog.h","","int","int","FAR const IPTR char *","FAR va_list *" "nxsched_get_stackinfo","nuttx/sched.h","","int","pid_t","FAR struct stackinfo_s *" "nxsched_get_streams","nuttx/sched.h","defined(CONFIG_FILE_STREAM)","FAR struct streamlist *" @@ -81,15 +83,11 @@ "pread","unistd.h","","ssize_t","int","FAR void *","size_t","off_t" "pselect","sys/select.h","","int","int","FAR fd_set *","FAR fd_set *","FAR fd_set *","FAR const struct timespec *","FAR const sigset_t *" "pthread_cancel","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t" -"pthread_cleanup_pop","pthread.h","defined(CONFIG_PTHREAD_CLEANUP)","void","int" -"pthread_cleanup_push","pthread.h","defined(CONFIG_PTHREAD_CLEANUP)","void","pthread_cleanup_t","FAR void *" "pthread_cond_broadcast","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_cond_t *" "pthread_cond_clockwait","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_cond_t *","FAR pthread_mutex_t *","clockid_t","FAR const struct timespec *" "pthread_cond_signal","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_cond_t *" "pthread_cond_wait","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_cond_t *","FAR pthread_mutex_t *" -"pthread_create","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_t *","FAR const pthread_attr_t *","pthread_startroutine_t","pthread_addr_t" "pthread_detach","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t" -"pthread_exit","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","noreturn","pthread_addr_t" "pthread_getaffinity_np","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_SMP)","int","pthread_t","size_t","FAR cpu_set_t*" "pthread_getschedparam","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","FAR int *","FAR struct sched_param *" "pthread_join","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","FAR pthread_addr_t *" @@ -179,8 +177,6 @@ "timer_getoverrun","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","timer_t" "timer_gettime","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","timer_t","FAR struct itimerspec *" "timer_settime","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","timer_t","int","FAR const struct itimerspec *","FAR struct itimerspec *" -"tls_alloc","nuttx/tls.h","CONFIG_TLS_NELEM > 0","int" -"tls_free","nuttx/tls.h","CONFIG_TLS_NELEM > 0","int","int" "umount2","sys/mount.h","!defined(CONFIG_DISABLE_MOUNTPOINT)","int","FAR const char *","unsigned int" "unlink","unistd.h","!defined(CONFIG_DISABLE_MOUNTPOINT)","int","FAR const char *" "unsetenv","stdlib.h","!defined(CONFIG_DISABLE_ENVIRON)","int","FAR const char *" diff --git a/tools/ci/docker/linux/Dockerfile b/tools/ci/docker/linux/Dockerfile index b43eac81a2e..c534bfbf748 100644 --- a/tools/ci/docker/linux/Dockerfile +++ b/tools/ci/docker/linux/Dockerfile @@ -106,12 +106,18 @@ RUN mkdir -p xtensa-esp32-elf-gcc && \ curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r3/xtensa-esp32-elf-gcc8_4_0-esp-2020r3-linux-amd64.tar.gz" \ | tar -C xtensa-esp32-elf-gcc --strip-components 1 -xz -RUN echo "ESP Binaries: 2021/02/20" +RUN mkdir -p xtensa-esp32s2-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r3/xtensa-esp32s2-elf-gcc8_4_0-esp-2020r3-linux-amd64.tar.gz" \ + | tar -C xtensa-esp32s2-elf-gcc --strip-components 1 -xz + +RUN echo "ESP Binaries: 2021/06/01" RUN mkdir -p /tools/blobs && cd /tools/blobs \ && curl -s -L "https://github.com/espressif/esp-nuttx-bootloader/releases/download/latest/bootloader-esp32.bin" -o bootloader-esp32.bin \ && curl -s -L "https://github.com/espressif/esp-nuttx-bootloader/releases/download/latest/bootloader-esp32c3.bin" -o bootloader-esp32c3.bin \ + && curl -s -L "https://github.com/espressif/esp-nuttx-bootloader/releases/download/latest/bootloader-esp32s2.bin" -o bootloader-esp32s2.bin \ && curl -s -L "https://github.com/espressif/esp-nuttx-bootloader/releases/download/latest/partition-table-esp32.bin" -o partition-table-esp32.bin \ - && curl -s -L "https://github.com/espressif/esp-nuttx-bootloader/releases/download/latest/partition-table-esp32c3.bin" -o partition-table-esp32c3.bin + && curl -s -L "https://github.com/espressif/esp-nuttx-bootloader/releases/download/latest/partition-table-esp32c3.bin" -o partition-table-esp32c3.bin \ + && curl -s -L "https://github.com/espressif/esp-nuttx-bootloader/releases/download/latest/partition-table-esp32s2.bin" -o partition-table-esp32s2.bin ############################################################################### # Build image for tool required by Renesas builds @@ -203,6 +209,7 @@ RUN apt-get update -qq && DEBIAN_FRONTEND="noninteractive" apt-get install -y -q libxext-dev libxext-dev:i386 \ linux-libc-dev:i386 \ linux-headers-generic \ + ninja-build \ python3 \ python3-pip \ python-is-python3 \ @@ -249,6 +256,11 @@ ENV PATH="/tools/riscv64-unknown-elf-gcc/bin:$PATH" # ESP32 toolchain COPY --from=nuttx-toolchain-esp32 /tools/xtensa-esp32-elf-gcc/ xtensa-esp32-elf-gcc/ ENV PATH="/tools/xtensa-esp32-elf-gcc/bin:$PATH" + +# ESP32-S2 toolchain +COPY --from=nuttx-toolchain-esp32 /tools/xtensa-esp32s2-elf-gcc/ xtensa-esp32s2-elf-gcc/ +ENV PATH="/tools/xtensa-esp32s2-elf-gcc/bin:$PATH" + RUN mkdir -p /tools/blobs/esp-bins COPY --from=nuttx-toolchain-esp32 /tools/blobs/* /tools/blobs/esp-bins/ RUN pip3 install esptool @@ -272,6 +284,8 @@ RUN mkdir -p /tools/ccache/bin && \ ln -sf `which ccache` /tools/ccache/bin/riscv64-unknown-elf-g++ && \ ln -sf `which ccache` /tools/ccache/bin/xtensa-esp32-elf-gcc && \ ln -sf `which ccache` /tools/ccache/bin/xtensa-esp32-elf-g++ && \ + ln -sf `which ccache` /tools/ccache/bin/xtensa-esp32s2-elf-gcc && \ + ln -sf `which ccache` /tools/ccache/bin/xtensa-esp32s2-elf-g++ && \ ln -sf `which ccache` /tools/ccache/bin/avr-gcc && \ ln -sf `which ccache` /tools/ccache/bin/avr-g++ && \ ln -sf `which ccache` /tools/ccache/bin/rx-elf-gcc diff --git a/tools/ci/testlist/all.dat b/tools/ci/testlist/all.dat index b630b10f6ae..a83a4b8d1d5 100644 --- a/tools/ci/testlist/all.dat +++ b/tools/ci/testlist/all.dat @@ -5,6 +5,7 @@ -imxrt1060-evk:libcxxtest -launchxl-cc1310:nsh -launchxl-tms57004:nsh +-lm3s6965-ek:qemu-nxflat -lpcxpresso-lpc1768:thttpd -moxa:nsh -olimex-lpc1766stk:slip-httpd diff --git a/tools/ci/testlist/arm-13.dat b/tools/ci/testlist/arm-13.dat index 3d48e0ac190..5656de6595f 100644 --- a/tools/ci/testlist/arm-13.dat +++ b/tools/ci/testlist/arm-13.dat @@ -7,4 +7,5 @@ -eagle100:thttpd -launchxl-cc1310:nsh -launchxl-tms57004:nsh +-lm3s6965-ek:qemu-nxflat -tms570ls31x-usb-kit:nsh diff --git a/tools/ci/testlist/sim01.dat b/tools/ci/testlist/sim-01.dat similarity index 96% rename from tools/ci/testlist/sim01.dat rename to tools/ci/testlist/sim-01.dat index 1edd98dd68f..bb9292aa66d 100644 --- a/tools/ci/testlist/sim01.dat +++ b/tools/ci/testlist/sim-01.dat @@ -10,9 +10,10 @@ -Darwin,sim:linuxi2c # macOS doesn't support 32bit(CONFIG_SIM_M32=y) anymore +-Darwin,sim:elf +-Darwin,sim:foc -Darwin,sim:loadable -Darwin,sim:module32 --Darwin,sim:foc # macOS doesn't have X11 -Darwin,sim:lvgl diff --git a/tools/ci/testlist/sim02.dat b/tools/ci/testlist/sim-02.dat similarity index 88% rename from tools/ci/testlist/sim02.dat rename to tools/ci/testlist/sim-02.dat index 677370d37f5..1974acb1962 100644 --- a/tools/ci/testlist/sim02.dat +++ b/tools/ci/testlist/sim-02.dat @@ -1,6 +1,7 @@ /sim/*/*/*/[o-z]* # macOS doesn't support 32bit anymore(CONFIG_SIM_M32=y) +-Darwin,sim:posix_spawn -Darwin,sim:rpproxy -Darwin,sim:rpserver -Darwin,sim:sotest32 diff --git a/tools/configure_completion.bash b/tools/configure_completion.bash new file mode 100644 index 00000000000..f28b1bf009b --- /dev/null +++ b/tools/configure_completion.bash @@ -0,0 +1,82 @@ +#!/usr/bin/env bash +# tools/configure_completion.bash +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# + +function _nuttx_configure_completion +{ + local colon_idx=2 + local num_options=0 + + # Skip ./tools/configure.sh script options. + while [[ "${#COMP_WORDS[@]}" != "${colon_idx}" ]] && [[ "${COMP_WORDS[$((colon_idx - 1))]}" == '-'* ]] + do + # If "-a" is among the provided arguments, consider the apps directory. + if [ "${COMP_WORDS[$((colon_idx - 1))]}" == "-a" ]; then + colon_idx=$((colon_idx + 2)) + num_options=$((num_options + 2)) + else + colon_idx=$((colon_idx + 1)) + num_options=$((num_options + 1)) + fi + done + + # When the command line is complete, COMP_WORDS array will have 5 elements + # plus the options. + # The script may return when this state is reached. + if [ "${#COMP_WORDS[@]}" == $((5 + num_options)) ]; then + return + fi + + # If the last provided argument is "-a", do not execute autocompletion + # algorithm. + if [ "${COMP_WORDS[-2]}" == "-a" ]; then + return + fi + + local search_dir="" + local search_pattern="" + local reply_suffix="" + + if [ "${COMP_WORDS[${colon_idx}]}" == ':' ]; then + local board_name=${COMP_WORDS[$((colon_idx - 1))]} + local config_name=${COMP_WORDS[$((colon_idx + 1))]} + + search_dir="boards/*/*/${board_name}/configs/" + search_pattern="${config_name}" + reply_suffix=" " + else + search_dir="boards/*/*/" + search_pattern="${COMP_WORDS[$((1 + num_options))]}" + reply_suffix=":" + fi + + local wordlist + local suggestions + wordlist=$(find ${search_dir} -maxdepth 1 -mindepth 1 -type d -exec basename {} \;) 2>/dev/null + suggestions=($(compgen -W "${wordlist}" -- "${search_pattern}")) + + if [ "${#suggestions[@]}" == "1" ]; then + # If there's only one match, complete with the appropriate reply suffix. + COMPREPLY=("${suggestions[0]}${reply_suffix}") + else + # More than one suggestion resolved, respond with the suggestions intact. + COMPREPLY=("${suggestions[@]}") + fi +} + +complete -o bashdefault -o default -o nospace -F _nuttx_configure_completion ./tools/configure.sh \ No newline at end of file diff --git a/tools/esp32/backtrace.gdbscript b/tools/esp32/backtrace.gdbscript index c38cf3049a3..5f825eee75c 100644 --- a/tools/esp32/backtrace.gdbscript +++ b/tools/esp32/backtrace.gdbscript @@ -54,19 +54,19 @@ # 4.7.1.5 Windowed Procedure-Call Protocol define esp32_bt - set $pc = $arg0 - set $a0 = $arg1 - set $a1 = $arg2 - set $pc_topbits = (int)$pc & 0xc0000000 + set $x_pc = $arg0 + set $x_a0 = $arg1 + set $x_a1 = $arg2 + set $pc_topbits = (int)$x_pc & 0xc0000000 # The return address from xtensa_sig_deliver to _xtensa_sig_trampoline set $sig_tramp_ra = (int)(_xtensa_sig_trampoline + 2 * 3) - print/a $pc + print/a $x_pc while (1) # Note: "- 3" to workaround the case where "call" is # the last instruction in the calling function. - set $next_pc = (($a0 & 0x3fffffff) | $pc_topbits) - 3 + set $next_pc = (($x_a0 & 0x3fffffff) | $pc_topbits) - 3 print/a $next_pc - if ($a0 == $sig_tramp_ra) + if ($x_a0 == $sig_tramp_ra) # A special logic for xtensa_sig_deliver print "--- SIGNAL ---" @@ -77,14 +77,14 @@ define esp32_bt print/a $next_pc # XXX local var offset assumption - set $regs = (int *)$a1 + set $regs = (int *)$x_a1 # Note: REG_A0 == 2 # Note: REG_A1 == 3 set $next_a0 = $regs[2] set $next_a1 = $regs[3] else - set $next_bsa = (int *)($a1 - 16) + set $next_bsa = (int *)($x_a1 - 16) set $next_a0 = $next_bsa[0] set $next_a1 = $next_bsa[1] end @@ -95,11 +95,11 @@ define esp32_bt # on the stack must be explicitly set to zero." loop_break end - if ($next_a1 <= $a1) + if ($next_a1 <= $x_a1) print "stack went backward. corrupted?" loop_break end - set $a0 = $next_a0 - set $a1 = $next_a1 + set $x_a0 = $next_a0 + set $x_a1 = $next_a1 end end diff --git a/tools/esp32/mk_qemu_img.sh b/tools/esp32/mk_qemu_img.sh index 357b9647921..4dfaeae0112 100755 --- a/tools/esp32/mk_qemu_img.sh +++ b/tools/esp32/mk_qemu_img.sh @@ -23,6 +23,9 @@ SCRIPT_NAME=$(basename "${0}") BOOTLOADER_IMG="" PARTITION_IMG="" +BOOTLOADER_OFFSET=0x1000 +PARTITION_OFFSET=0x8000 +NUTTX_OFFSET=0x10000 NUTTX_IMG="nuttx.bin" FLASH_IMG="esp32_qemu_img.bin" @@ -39,6 +42,10 @@ usage() { echo "" } +imgappend() { + dd of="${1}" if="${2}" bs=1 seek="$(printf '%d' ${3})" conv=notrunc status=none +} + while [ -n "${1}" ]; do case "${1}" in -b ) @@ -82,10 +89,10 @@ printf "Generating %s...\n" "${FLASH_IMG}" printf "\tBootloader: %s\n" "${BOOTLOADER_IMG}" printf "\tPartition Table: %s\n" "${PARTITION_IMG}" -dd if=/dev/zero bs=1024 count=4096 of="${FLASH_IMG}" && \ -dd if="${BOOTLOADER_IMG}" bs=1 seek="$(printf '%d' 0x1000)" of="${FLASH_IMG}" conv=notrunc && \ -dd if="${PARTITION_IMG}" bs=1 seek="$(printf '%d' 0x8000)" of="${FLASH_IMG}" conv=notrunc && \ -dd if="${NUTTX_IMG}" bs=1 seek="$(printf '%d' 0x10000)" of="${FLASH_IMG}" conv=notrunc +dd if=/dev/zero bs=1024 count=4096 of="${FLASH_IMG}" status=none +imgappend ${FLASH_IMG} ${BOOTLOADER_IMG} ${BOOTLOADER_OFFSET} +imgappend ${FLASH_IMG} ${PARTITION_IMG} ${PARTITION_OFFSET} +imgappend ${FLASH_IMG} ${NUTTX_IMG} ${NUTTX_OFFSET} if [ ${?} -ne 0 ]; then printf "Failed to generate %s!\n" "${FLASH_IMG}" diff --git a/tools/esp32s2/Config.mk b/tools/esp32s2/Config.mk new file mode 100644 index 00000000000..54f9d7670b2 --- /dev/null +++ b/tools/esp32s2/Config.mk @@ -0,0 +1,107 @@ +############################################################################ +# tools/esp32s2/Config.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# These are the macros that will be used in the NuttX make system to compile +# and assemble source files and to insert the resulting object files into an +# archive. These replace the default definitions at tools/Config.mk + +ifeq ($(CONFIG_ESP32S2_FLASH_2M),y) + FLASH_SIZE := 2MB +else ifeq ($(CONFIG_ESP32S2_FLASH_4M),y) + FLASH_SIZE := 4MB +else ifeq ($(CONFIG_ESP32S2_FLASH_8M),y) + FLASH_SIZE := 8MB +else ifeq ($(CONFIG_ESP32S2_FLASH_16M),y) + FLASH_SIZE := 16MB +endif + +ifeq ($(CONFIG_ESP32S2_FLASH_MODE_DIO),y) + FLASH_MODE := dio +else ifeq ($(CONFIG_ESP32S2_FLASH_MODE_DOUT),y) + FLASH_MODE := dout +else ifeq ($(CONFIG_ESP32S2_FLASH_MODE_QIO),y) + FLASH_MODE := qio +else ifeq ($(CONFIG_ESP32S2_FLASH_MODE_QOUT),y) + FLASH_MODE := qout +endif + +ifeq ($(CONFIG_ESP32S2_FLASH_FREQ_80M),y) + FLASH_FREQ := 80m +else ifeq ($(CONFIG_ESP32S2_FLASH_FREQ_40M),y) + FLASH_FREQ := 40m +else ifeq ($(CONFIG_ESP32S2_FLASH_FREQ_26M),y) + FLASH_FREQ := 26m +else ifeq ($(CONFIG_ESP32S2_FLASH_FREQ_20M),y) + FLASH_FREQ := 20m +endif + +ESPTOOL_ELF2IMG_OPTS := -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ) + +ifeq ($(CONFIG_ESP32S2_FLASH_DETECT),y) + ESPTOOL_WRITEFLASH_OPTS := -fs detect -fm dio -ff $(FLASH_FREQ) +else + ESPTOOL_WRITEFLASH_OPTS := -fs $(FLASH_SIZE) -fm dio -ff $(FLASH_FREQ) +endif + +ifdef ESPTOOL_BINDIR + BL_OFFSET=0x1000 + PT_OFFSET=0x8000 + BOOTLOADER=$(ESPTOOL_BINDIR)/bootloader-esp32s2.bin + PARTITION_TABLE=$(ESPTOOL_BINDIR)/partition-table-esp32s2.bin + FLASH_BL=$(BL_OFFSET) $(BOOTLOADER) + FLASH_PT=$(PT_OFFSET) $(PARTITION_TABLE) +endif + +# POSTBUILD -- Perform post build operations + +define POSTBUILD + $(Q) echo "MKIMAGE: ESP32S2 binary" + $(Q) if ! esptool.py version 1>/dev/null 2>&1; then \ + echo ""; \ + echo "esptool.py not found. Please run: \"pip install esptool\""; \ + echo ""; \ + echo "Run make again to create the nuttx.bin image."; \ + exit 1; \ + fi + $(Q) if [ -z $(FLASH_SIZE) ]; then \ + echo "Missing Flash memory size configuration for the ESP32S2 chip."; \ + exit 1; \ + fi + esptool.py -c esp32-s2 elf2image $(ESPTOOL_ELF2IMG_OPTS) -o nuttx.bin nuttx + $(Q) echo "Generated: nuttx.bin (ESP32S2 compatible)" +endef + +# ESPTOOL_BAUD -- Serial port baud rate used when flashing/reading via esptool.py + +ESPTOOL_BAUD ?= 921600 + +# DOWNLOAD -- Download binary image via esptool.py + +define DOWNLOAD + + $(eval ESPTOOL_BINS := $(FLASH_BL) $(FLASH_PT) 0x10000 $(1).bin) + + $(Q) if [ -z $(ESPTOOL_PORT) ]; then \ + echo "DOWNLOAD error: Missing serial port device argument."; \ + echo "USAGE: make download ESPTOOL_PORT= [ ESPTOOL_BAUD= ] [ ESPTOOL_BINDIR= ]"; \ + exit 1; \ + fi + esptool.py -c esp32-s2 -p $(ESPTOOL_PORT) -b $(ESPTOOL_BAUD) write_flash $(ESPTOOL_WRITEFLASH_OPTS) $(ESPTOOL_BINS) +endef diff --git a/tools/mksyscall.c b/tools/mksyscall.c index 02e65f6bb63..352bd1c4b7f 100644 --- a/tools/mksyscall.c +++ b/tools/mksyscall.c @@ -612,8 +612,16 @@ static void generate_wrapper(int nfixed, int nparms) * prototype */ - fprintf(stream, "%s UP_WRAPSYM(%s)(", g_parm[RETTYPE_INDEX], - g_parm[NAME_INDEX]); + if (strcmp(g_parm[RETTYPE_INDEX], "noreturn") == 0) + { + fprintf(stream, "void "); + } + else + { + fprintf(stream, "%s ", g_parm[RETTYPE_INDEX]); + } + + fprintf(stream, "UP_WRAPSYM(%s)(", g_parm[NAME_INDEX]); /* Generate the formal parameter list */ @@ -655,15 +663,24 @@ static void generate_wrapper(int nfixed, int nparms) /* Generate the result variable definition for non-void function */ - if (strcmp(g_parm[RETTYPE_INDEX], "void") != 0) + if (strcmp(g_parm[RETTYPE_INDEX], "void") != 0 && + strcmp(g_parm[RETTYPE_INDEX], "noreturn") != 0) { fprintf(stream, " %s result;\n", g_parm[RETTYPE_INDEX]); } /* Generate the wrapped (real) function prototype definition */ - fprintf(stream, " %s UP_REALSYM(%s)(", g_parm[RETTYPE_INDEX], - g_parm[NAME_INDEX]); + if (strcmp(g_parm[RETTYPE_INDEX], "noreturn") == 0) + { + fprintf(stream, " void "); + } + else + { + fprintf(stream, " %s ", g_parm[RETTYPE_INDEX]); + } + + fprintf(stream, "UP_REALSYM(%s)(", g_parm[NAME_INDEX]); /* Generate the formal parameter list */ @@ -767,7 +784,8 @@ static void generate_wrapper(int nfixed, int nparms) * value are a special case. */ - if (strcmp(g_parm[RETTYPE_INDEX], "void") == 0) + if (strcmp(g_parm[RETTYPE_INDEX], "void") == 0 || + strcmp(g_parm[RETTYPE_INDEX], "noreturn") == 0) { fprintf(stream, " UP_REALSYM(%s)(", g_parm[NAME_INDEX]); } @@ -798,7 +816,8 @@ static void generate_wrapper(int nfixed, int nparms) fprintf(stream, " sched_note_syscall_leave(SYS_%s, ", g_parm[NAME_INDEX]); - if (strcmp(g_parm[RETTYPE_INDEX], "void") == 0) + if (strcmp(g_parm[RETTYPE_INDEX], "void") == 0 || + strcmp(g_parm[RETTYPE_INDEX], "noreturn") == 0) { fprintf(stream, "0"); } @@ -813,7 +832,8 @@ static void generate_wrapper(int nfixed, int nparms) * value, do nothing. */ - if (strcmp(g_parm[RETTYPE_INDEX], "void") == 0) + if (strcmp(g_parm[RETTYPE_INDEX], "void") == 0 || + strcmp(g_parm[RETTYPE_INDEX], "noreturn") == 0) { fprintf(stream, "}\n"); } diff --git a/tools/nxstyle.c b/tools/nxstyle.c index 3fadfd59932..3105e3ff700 100644 --- a/tools/nxstyle.c +++ b/tools/nxstyle.c @@ -221,6 +221,10 @@ static const char *g_white_list[] = "_Exit", + /* Ref: stdatomic.h */ + + "_Atomic", + /* Ref: unwind-arm-common.h */ "_Unwind", @@ -1858,10 +1862,9 @@ int main(int argc, char **argv, char **envp) else if (line[n + 1] == '/') { - /* Check for "http://" or "https://" */ + /* Check for URI schemes, e.g. "http://" or "https://" */ - if ((n < 5 || strncmp(&line[n - 5], "http://", 7) != 0) && - (n < 6 || strncmp(&line[n - 6], "https://", 8) != 0)) + if (n == 0 || strncmp(&line[n - 1], "://", 3) != 0) { ERROR("C++ style comment", lineno, n); n++; diff --git a/tools/showsize.sh b/tools/showsize.sh index bc6c1434779..4d99ca8d0f1 100755 --- a/tools/showsize.sh +++ b/tools/showsize.sh @@ -2,36 +2,20 @@ ############################################################################ # tools/showsize.sh # -# Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Lorenz Meier (Original concept) -# Gregory Nutt (This instantiation) +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: +# http://www.apache.org/licenses/LICENSE-2.0 # -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. # ############################################################################ diff --git a/video/videomode/edid_parse.c b/video/videomode/edid_parse.c index 28faefac8e5..00f814721b6 100644 --- a/video/videomode/edid_parse.c +++ b/video/videomode/edid_parse.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/video/videomode/videomode_lookup.c b/video/videomode/videomode_lookup.c index 31ae91e5443..2d8ac620355 100644 --- a/video/videomode/videomode_lookup.c +++ b/video/videomode/videomode_lookup.c @@ -1,39 +1,20 @@ /**************************************************************************** * video/videomode/videomode_lookup.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Derives from logic in FreeBSD which has an equivalent 3-clause BSD - * license: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (c) 2006 Itronix Inc. All rights reserved. - * Written by Garrett D'Amore for Itronix Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of Itronix Inc. may not be used to endorse - * or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/video/videomode/videomode_sort.c b/video/videomode/videomode_sort.c index b9bafb139de..1377068748a 100644 --- a/video/videomode/videomode_sort.c +++ b/video/videomode/videomode_sort.c @@ -1,36 +1,20 @@ /**************************************************************************** * video/videomode/videomode_sort.c * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Derives from logic in FreeBSD which has an compatible 2-clause BSD - * license: + * http://www.apache.org/licenses/LICENSE-2.0 * - * Copyright (c) 2006 The NetBSD Foundation. All rights reserved. - * Author: Michael Lorenz - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE NETBSD FOUNDATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/wireless/bluetooth/bt_att.c b/wireless/bluetooth/bt_att.c index 9119338edd1..9e816c3700f 100644 --- a/wireless/bluetooth/bt_att.c +++ b/wireless/bluetooth/bt_att.c @@ -48,6 +48,7 @@ #include #include +#include #include #include diff --git a/wireless/bluetooth/bt_conn.c b/wireless/bluetooth/bt_conn.c index 590c9b57757..40cd2279076 100644 --- a/wireless/bluetooth/bt_conn.c +++ b/wireless/bluetooth/bt_conn.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include diff --git a/wireless/bluetooth/bt_hcicore.c b/wireless/bluetooth/bt_hcicore.c index e3f64887387..0ee98e33a88 100644 --- a/wireless/bluetooth/bt_hcicore.c +++ b/wireless/bluetooth/bt_hcicore.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include diff --git a/wireless/bluetooth/bt_queue.c b/wireless/bluetooth/bt_queue.c index 1c26b70b253..3d237f59103 100644 --- a/wireless/bluetooth/bt_queue.c +++ b/wireless/bluetooth/bt_queue.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Common essage queue attributes */ +/* Common message queue attributes */ #define BT_MSGSIZE sizeof(struct bt_bufmsg_s) #define BT_MSGFLAGS 0 diff --git a/wireless/bluetooth/bt_smp.c b/wireless/bluetooth/bt_smp.c index 29a8a07a1f0..98f1f35fd28 100644 --- a/wireless/bluetooth/bt_smp.c +++ b/wireless/bluetooth/bt_smp.c @@ -47,6 +47,7 @@ #include #include +#include #include #include diff --git a/wireless/ieee802154/ieee802154_primitive.c b/wireless/ieee802154/ieee802154_primitive.c index f066414e1a3..03596b42956 100644 --- a/wireless/ieee802154/ieee802154_primitive.c +++ b/wireless/ieee802154/ieee802154_primitive.c @@ -26,6 +26,8 @@ #include #include +#include +#include #include #include diff --git a/wireless/ieee802154/mac802154_device.c b/wireless/ieee802154/mac802154_device.c index c1e31ec566f..f718d3a1831 100644 --- a/wireless/ieee802154/mac802154_device.c +++ b/wireless/ieee802154/mac802154_device.c @@ -43,6 +43,8 @@ #include #include #include +#include +#include #include #include #include