diff --git a/arch/arm/src/kinetis/chip/kinetis_mcg.h b/arch/arm/src/kinetis/chip/kinetis_mcg.h
index e426b02e586..fe8dccc60e1 100644
--- a/arch/arm/src/kinetis/chip/kinetis_mcg.h
+++ b/arch/arm/src/kinetis/chip/kinetis_mcg.h
@@ -142,7 +142,7 @@
 
 #define MCG_C5_PRDIV_SHIFT        (0)       /* Bits 0-4: PLL External Reference Divider */
 #define MCG_C5_PRDIV_MASK         (31 << MCG_C5_PRDIV_SHIFT)
-#  define MCG_C5_PRDIV(n)         (((n)-1) << MCG_C5_PRDIV_SHIFT) /* Divide factor n=1..25 */
+#  define MCG_C5_PRDIV(n)         ((uint32_t)((n)-1) << MCG_C5_PRDIV_SHIFT) /* n=1..25 */
 #define MCG_C5_PLLSTEN            (1 << 5)  /* Bit 5:  PLL Stop Enable */
 #define MCG_C5_PLLCLKEN           (1 << 6)  /* Bit 6:  PLL Clock Enable */
                                             /* Bit 7: Reserved */
@@ -151,7 +151,7 @@
 
 #define MCG_C6_VDIV_SHIFT         (0)       /* Bits 0-4: VCO Divider */
 #define MCG_C6_VDIV_MASK          (31 << MCG_C6_VDIV_SHIFT)
-#  define MCG_C6_VDIV(n)          (((n)-24) << MCG_C6_VDIV_SHIFT) /* Divide factor n=24..55 */
+#  define MCG_C6_VDIV(n)          ((uint32_t)((n)-24) << MCG_C6_VDIV_SHIFT) /* n=24..55 */
 #define MCG_C6_CME                (1 << 5)  /* Bit 5:  Clock Monitor Enable */
 #define MCG_C6_PLLS               (1 << 6)  /* Bit 6:  PLL Select */
 #define MCG_C6_LOLIE              (1 << 7)  /* Bit 7:  Loss of Lock Interrrupt Enable */
diff --git a/configs/freedom-k64f/README.txt b/configs/freedom-k64f/README.txt
index 8fea59243a0..9ef9660763c 100644
--- a/configs/freedom-k64f/README.txt
+++ b/configs/freedom-k64f/README.txt
@@ -347,10 +347,8 @@ Where <subdir> is one of the following:
 
   nsh:
   ---
-    Configures the NuttShell (nsh) located at apps/examples/nsh.  The
-    Configuration enables both the serial and telnet NSH interfaces.
-    Support for the board's SPI-based MicroSD card is included
-    (but not passing tests as of this writing).
+    Configures the NuttShell (nsh) located at apps/examples/nsh using a
+    serial console on UART3.
 
     NOTES:
 
@@ -373,9 +371,8 @@ Where <subdir> is one of the following:
     3. The Serial Console is provided on UART3 with the correct pin
        configuration for use with an Arduino Serial Shield.
 
-    4. An SDHC driver is under work and can be enabled in the NSH configuration
-       for further testing be setting the following configuration values as
-       follows:
+    4. An SDHC driver is has not yet been tested but can be enabled in the NSH
+       configuration by setting the following configuration values as follows:
 
       CONFIG_KINETIS_SDHC=y                : Enable the SDHC driver
 
diff --git a/configs/freedom-k64f/include/board.h b/configs/freedom-k64f/include/board.h
index 07af717c708..37125bac41c 100644
--- a/configs/freedom-k64f/include/board.h
+++ b/configs/freedom-k64f/include/board.h
@@ -59,20 +59,23 @@
  */
 
 #define BOARD_EXTCLOCK       1              /* External clock */
-#define BOARD_EXTAL_FREQ     48000000       /* 50MHz Oscillator */
+#define BOARD_EXTAL_FREQ     50000000       /* 50MHz Oscillator from Micrel PHY */
 #define BOARD_XTAL32_FREQ    32768          /* 32KHz RTC Oscillator */
 
 /* PLL Configuration.  Either the external clock or crystal frequency is used to
  * select the PRDIV value. Only reference clock frequencies are supported that will
  * produce a 2MHz reference clock to the PLL.
  *
- *   PLL Input frequency:   PLLIN  = REFCLK/PRDIV = 50MHz/25 = 2MHz
- *   PLL Output frequency:  PLLOUT = PLLIN*VDIV   = 2Mhz*48 = 96MHz
+ *   PLL Input frequency:   PLLIN  = REFCLK / PRDIV = 50  Mhz  / 20 = 2.5 MHz
+ *   PLL Output frequency:  PLLOUT = PLLIN  * VDIV  = 2.5 Mhz  * 48 = 120 MHz
  *   MCG Frequency:         PLLOUT = 96MHz
+ *
+ * PRDIV register value is the divider minus one.  So 20 -> 19
+ * VDIV  regiser value is offset by 24.  So 28 -> 24
  */
 
-#define BOARD_PRDIV          19             /* PLL External Reference Divider */
-#define BOARD_VDIV           24             /* PLL VCO Divider (frequency multiplier) */
+#define BOARD_PRDIV          20             /* PLL External Reference Divider */
+#define BOARD_VDIV           48             /* PLL VCO Divider (frequency multiplier) */
 
 #define BOARD_PLLIN_FREQ     (BOARD_EXTAL_FREQ / BOARD_PRDIV)
 #define BOARD_PLLOUT_FREQ    (BOARD_PLLIN_FREQ * BOARD_VDIV)
@@ -80,10 +83,10 @@
 
 /* SIM CLKDIV1 dividers */
 
-#define BOARD_OUTDIV1        1              /* Core        = MCG, 96MHz */
-#define BOARD_OUTDIV2        2              /* Bus         = MCG/2, 48MHz */
-#define BOARD_OUTDIV3        2              /* FlexBus     = MCG/2, 48MHz */
-#define BOARD_OUTDIV4        4              /* Flash clock = MCG/4, 24MHz */
+#define BOARD_OUTDIV1        1              /* Core        = MCG,    120 MHz */
+#define BOARD_OUTDIV2        2              /* Bus         = MCG / 2, 60 MHz */
+#define BOARD_OUTDIV3        2              /* FlexBus     = MCG / 2, 60 MHz */
+#define BOARD_OUTDIV4        4              /* Flash clock = MCG / 4, 30 MHz */
 
 #define BOARD_CORECLK_FREQ  (BOARD_MCG_FREQ / BOARD_OUTDIV1)
 #define BOARD_BUS_FREQ      (BOARD_MCG_FREQ / BOARD_OUTDIV2)