diff --git a/arch/arm/src/imxrt/chip/imxrt_ccm.h b/arch/arm/src/imxrt/chip/imxrt_ccm.h index 17210052f29..6337b1c5286 100644 --- a/arch/arm/src/imxrt/chip/imxrt_ccm.h +++ b/arch/arm/src/imxrt/chip/imxrt_ccm.h @@ -582,52 +582,52 @@ #define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ #define CCM_CCGRX_CG0_SHIFT (0) -#define CCM_CCGRX_CG0_MASK (0x3) +#define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) # define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) #define CCM_CCGRX_CG1_SHIFT (2) -#define CCM_CCGRX_CG1_MASK (0x3) +#define CCM_CCGRX_CG1_MASK (0x3 << CCM_CCGRX_CG1_SHIFT) # define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) #define CCM_CCGRX_CG2_SHIFT (4) -#define CCM_CCGRX_CG2_MASK (0x3) +#define CCM_CCGRX_CG2_MASK (0x3 << CCM_CCGRX_CG2_SHIFT) # define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) #define CCM_CCGRX_CG3_SHIFT (6) -#define CCM_CCGRX_CG3_MASK (0x3) +#define CCM_CCGRX_CG3_MASK (0x3 << CCM_CCGRX_CG3_SHIFT) # define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) #define CCM_CCGRX_CG4_SHIFT (8) -#define CCM_CCGRX_CG4_MASK (0x3) +#define CCM_CCGRX_CG4_MASK (0x3 << CCM_CCGRX_CG4_SHIFT) # define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) #define CCM_CCGRX_CG5_SHIFT (10) -#define CCM_CCGRX_CG5_MASK (0x3) +#define CCM_CCGRX_CG5_MASK (0x3 << CCM_CCGRX_CG5_SHIFT) # define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) #define CCM_CCGRX_CG6_SHIFT (12) -#define CCM_CCGRX_CG6_MASK (0x3) +#define CCM_CCGRX_CG6_MASK (0x3 << CCM_CCGRX_CG6_SHIFT) # define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) #define CCM_CCGRX_CG7_SHIFT (14) -#define CCM_CCGRX_CG7_MASK (0x3) +#define CCM_CCGRX_CG7_MASK (0x3 << CCM_CCGRX_CG7_SHIFT) # define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) #define CCM_CCGRX_CG8_SHIFT (16) -#define CCM_CCGRX_CG8_MASK (0x3) +#define CCM_CCGRX_CG8_MASK (0x3 << CCM_CCGRX_CG8_SHIFT) # define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) #define CCM_CCGRX_CG9_SHIFT (18) -#define CCM_CCGRX_CG9_MASK (0x3) +#define CCM_CCGRX_CG9_MASK (0x3 << CCM_CCGRX_CG9_SHIFT) # define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) #define CCM_CCGRX_CG10_SHIFT (20) -#define CCM_CCGRX_CG10_MASK (0x3) +#define CCM_CCGRX_CG10_MASK (0x3 << CCM_CCGRX_CG10_SHIFT) # define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) #define CCM_CCGRX_CG11_SHIFT (22) -#define CCM_CCGRX_CG11_MASK (0x3) +#define CCM_CCGRX_CG11_MASK (0x3 << CCM_CCGRX_CG11_SHIFT) # define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) #define CCM_CCGRX_CG12_SHIFT (24) -#define CCM_CCGRX_CG12_MASK (0x3) +#define CCM_CCGRX_CG12_MASK (0x3 << CCM_CCGRX_CG12_SHIFT) # define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) #define CCM_CCGRX_CG13_SHIFT (26) -#define CCM_CCGRX_CG13_MASK (0x3) +#define CCM_CCGRX_CG13_MASK (0x3 << CCM_CCGRX_CG13_SHIFT) # define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) #define CCM_CCGRX_CG14_SHIFT (28) -#define CCM_CCGRX_CG14_MASK (0x3) +#define CCM_CCGRX_CG14_MASK (0x3 << CCM_CCGRX_CG14_SHIFT) # define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) #define CCM_CCGRX_CG15_SHIFT (30) -#define CCM_CCGRX_CG15_MASK (0x3) +#define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) # define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) /* Module Enable Overide Register */ diff --git a/arch/arm/src/imxrt/imxrt_lowputc.c b/arch/arm/src/imxrt/imxrt_lowputc.c index 5c784c4d96c..f0946b5d99d 100644 --- a/arch/arm/src/imxrt/imxrt_lowputc.c +++ b/arch/arm/src/imxrt/imxrt_lowputc.c @@ -168,37 +168,63 @@ static const struct uart_config_s g_console_config = void imxrt_lpuart_clock_enable (uint32_t base) { + uint32_t regval; + if (base == IMXRT_LPUART1_BASE) { - putreg32(CCM_CG_ALL << CCM_CCGRX_CG12_SHIFT, IMXRT_CCM_CCGR5); + regval = getreg32(IMXRT_CCM_CCGR5); + regval &= ~ CCM_CCGRX_CG12_MASK; + regval |= (CCM_CG_ALL << CCM_CCGRX_CG12_SHIFT); + putreg32(regval, IMXRT_CCM_CCGR5); } else if (base == IMXRT_LPUART2_BASE) { - putreg32(CCM_CG_ALL << CCM_CCGRX_CG14_SHIFT, IMXRT_CCM_CCGR0); + regval = getreg32(IMXRT_CCM_CCGR0); + regval &= ~ CCM_CCGRX_CG14_MASK; + regval |= (CCM_CG_ALL << CCM_CCGRX_CG14_SHIFT); + putreg32(regval, IMXRT_CCM_CCGR0); } else if (base == IMXRT_LPUART3_BASE) { - putreg32(CCM_CG_ALL << CCM_CCGRX_CG6_SHIFT, IMXRT_CCM_CCGR0); + regval = getreg32(IMXRT_CCM_CCGR0); + regval &= ~ CCM_CCGRX_CG6_MASK; + regval |= (CCM_CG_ALL << CCM_CCGRX_CG6_SHIFT); + putreg32(regval, IMXRT_CCM_CCGR0); } else if (base == IMXRT_LPUART4_BASE) { - putreg32(CCM_CG_ALL << CCM_CCGRX_CG12_SHIFT, IMXRT_CCM_CCGR1); + regval = getreg32(IMXRT_CCM_CCGR1); + regval &= ~ CCM_CCGRX_CG12_MASK; + regval |= (CCM_CG_ALL << CCM_CCGRX_CG12_SHIFT); + putreg32(regval, IMXRT_CCM_CCGR1); } else if (base == IMXRT_LPUART5_BASE) { - putreg32(CCM_CG_ALL << CCM_CCGRX_CG1_SHIFT, IMXRT_CCM_CCGR3); + regval = getreg32(IMXRT_CCM_CCGR3); + regval &= ~ CCM_CCGRX_CG1_MASK; + regval |= (CCM_CG_ALL << CCM_CCGRX_CG1_SHIFT); + putreg32(regval, IMXRT_CCM_CCGR3); } else if (base == IMXRT_LPUART6_BASE) { - putreg32(CCM_CG_ALL << CCM_CCGRX_CG4_SHIFT, IMXRT_CCM_CCGR3); + regval = getreg32(IMXRT_CCM_CCGR3); + regval &= ~ CCM_CCGRX_CG4_MASK; + regval |= (CCM_CG_ALL << CCM_CCGRX_CG4_SHIFT); + putreg32(regval, IMXRT_CCM_CCGR3); } else if (base == IMXRT_LPUART7_BASE) { - putreg32(CCM_CG_ALL << CCM_CCGRX_CG13_SHIFT, IMXRT_CCM_CCGR5); + regval = getreg32(IMXRT_CCM_CCGR5); + regval &= ~ CCM_CCGRX_CG13_MASK; + regval |= (CCM_CG_ALL << CCM_CCGRX_CG13_SHIFT); + putreg32(regval, IMXRT_CCM_CCGR5); } else if (base == IMXRT_LPUART8_BASE) { - putreg32(CCM_CG_ALL << CCM_CCGRX_CG7_SHIFT, IMXRT_CCM_CCGR6); + regval = getreg32(IMXRT_CCM_CCGR6); + regval &= ~ CCM_CCGRX_CG7_MASK; + regval |= (CCM_CG_ALL << CCM_CCGRX_CG7_SHIFT); + putreg32(regval, IMXRT_CCM_CCGR6); } }