diff --git a/arch/arm/src/armv7-m/dwt.h b/arch/arm/src/armv7-m/dwt.h index b47c0380067..6320d26dcf9 100644 --- a/arch/arm/src/armv7-m/dwt.h +++ b/arch/arm/src/armv7-m/dwt.h @@ -1,4 +1,4 @@ -/*********************************************************************************************** +/*************************************************************************************** * arch/arm/src/armv7-m/dwt.h * * Copyright (c) 2009 - 2013 ARM LIMITED @@ -6,6 +6,7 @@ * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: + * * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright @@ -14,7 +15,7 @@ * - Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without * specific prior written permission. - * * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -57,22 +58,22 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************/ + ***********************************************************************************************/ #ifndef __ARCH_ARM_SRC_ARMV7_M_DWT_H #define __ARCH_ARM_SRC_ARMV7_M_DWT_H -/******************************************************************************************************* +/*********************************************************************************************** * Pre-processor Definitions - *******************************************************************************************************/ + ***********************************************************************************************/ -/* Data Watchpoint and Trace Register (DWT) Definitions ************************************************/ +/* Data Watchpoint and Trace Register (DWT) Definitions ****************************************/ -/* DWT Register Base Address ***************************************************************************/ +/* DWT Register Base Address *******************************************************************/ #define DWT_BASE (0xe0001000ul) -/* DWT Register Addresses ******************************************************************************/ +/* DWT Register Addresses **********************************************************************/ #define DWT_CTRL (DWT_BASE + 0x0000) /* Control Register */ #define DWT_CYCCNT (DWT_BASE + 0x0004) /* Cycle Count Register */ @@ -95,80 +96,96 @@ #define DWT_MASK3 (DWT_BASE + 0x0054) /* Mask Register 3 */ #define DWT_FUNCTION3 (DWT_BASE + 0x0058) /* Function Register 3 */ -/* DWT Register Bit Field Definitions ******************************************************************/ +/* DWT Register Bit Field Definitions **********************************************************/ -#define DWT_CTRL_NUMCOMP_SHIFT 28 /* DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_MASK (0xFul << DWT_CTRL_NUMCOMP_Pos) /* DWT CTRL: NUMCOMP Mask */ -#define DWT_CTRL_NOTRCPKT_SHIFT 27 /* DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_MASK (0x1ul << DWT_CTRL_NOTRCPKT_Pos) /* DWT CTRL: NOTRCPKT Mask */ -#define DWT_CTRL_NOEXTTRIG_SHIFT 26 /* DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_MASK (0x1ul << DWT_CTRL_NOEXTTRIG_Pos) /* DWT CTRL: NOEXTTRIG Mask */ -#define DWT_CTRL_NOCYCCNT_SHIFT 25 /* DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_MASK (0x1ul << DWT_CTRL_NOCYCCNT_Pos) /* DWT CTRL: NOCYCCNT Mask */ -#define DWT_CTRL_NOPRFCNT_SHIFT 24 /* DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_MASK (0x1ul << DWT_CTRL_NOPRFCNT_Pos) /* DWT CTRL: NOPRFCNT Mask */ -#define DWT_CTRL_CYCEVTENA_SHIFT 22 /* DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_MASK (0x1ul << DWT_CTRL_CYCEVTENA_Pos) /* DWT CTRL: CYCEVTENA Mask */ -#define DWT_CTRL_FOLDEVTENA_SHIFT 21 /* DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_MASK (0x1ul << DWT_CTRL_FOLDEVTENA_Pos) /* DWT CTRL: FOLDEVTENA Mask */ -#define DWT_CTRL_LSUEVTENA_SHIFT 20 /* DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_MASK (0x1ul << DWT_CTRL_LSUEVTENA_Pos) /* DWT CTRL: LSUEVTENA Mask */ -#define DWT_CTRL_SLEEPEVTENA_SHIFT 19 /* DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_MASK (0x1ul << DWT_CTRL_SLEEPEVTENA_Pos) /* DWT CTRL: SLEEPEVTENA Mask */ -#define DWT_CTRL_EXCEVTENA_SHIFT 18 /* DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_MASK (0x1ul << DWT_CTRL_EXCEVTENA_Pos) /* DWT CTRL: EXCEVTENA Mask */ -#define DWT_CTRL_CPIEVTENA_SHIFT 17 /* DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_MASK (0x1ul << DWT_CTRL_CPIEVTENA_Pos) /* DWT CTRL: CPIEVTENA Mask */ -#define DWT_CTRL_EXCTRCENA_SHIFT 16 /* DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_MASK (0x1ul << DWT_CTRL_EXCTRCENA_Pos) /* DWT CTRL: EXCTRCENA Mask */ -#define DWT_CTRL_PCSAMPLENA_SHIFT 12 /* DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_MASK (0x1ul << DWT_CTRL_PCSAMPLENA_Pos) /* DWT CTRL: PCSAMPLENA Mask */ -#define DWT_CTRL_SYNCTAP_SHIFT 10 /* DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_MASK (0x3ul << DWT_CTRL_SYNCTAP_Pos) /* DWT CTRL: SYNCTAP Mask */ -#define DWT_CTRL_CYCTAP_SHIFT 9 /* DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_MASK (0x1ul << DWT_CTRL_CYCTAP_Pos) /* DWT CTRL: CYCTAP Mask */ -#define DWT_CTRL_POSTINIT_SHIFT 5 /* DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_MASK (0xful << DWT_CTRL_POSTINIT_Pos) /* DWT CTRL: POSTINIT Mask */ -#define DWT_CTRL_POSTPRESET_SHIFT 1 /* DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_MASK (0xful << DWT_CTRL_POSTPRESET_Pos) /* DWT CTRL: POSTPRESET Mask */ -#define DWT_CTRL_CYCCNTENA_SHIFT 0 /* DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_MASK (0x1ul << DWT_CTRL_CYCCNTENA_Pos) /* DWT CTRL: CYCCNTENA Mask */ +/* DWT CTRL */ -#define DWT_CPICNT_CPICNT_SHIFT 0 /* DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_MASK (0xfful << DWT_CPICNT_CPICNT_Pos) /* DWT CPICNT: CPICNT Mask */ +#define DWT_CTRL_NUMCOMP_SHIFT 28 +#define DWT_CTRL_NUMCOMP_MASK (0xFul << DWT_CTRL_NUMCOMP_SHIFT) +#define DWT_CTRL_NOTRCPKT_SHIFT 27 +#define DWT_CTRL_NOTRCPKT_MASK (0x1ul << DWT_CTRL_NOTRCPKT_SHIFT) +#define DWT_CTRL_NOEXTTRIG_SHIFT 26 +#define DWT_CTRL_NOEXTTRIG_MASK (0x1ul << DWT_CTRL_NOEXTTRIG_SHIFT) +#define DWT_CTRL_NOCYCCNT_SHIFT 25 +#define DWT_CTRL_NOCYCCNT_MASK (0x1ul << DWT_CTRL_NOCYCCNT_SHIFT) +#define DWT_CTRL_NOPRFCNT_SHIFT 24 +#define DWT_CTRL_NOPRFCNT_MASK (0x1ul << DWT_CTRL_NOPRFCNT_SHIFT) +#define DWT_CTRL_CYCEVTENA_SHIFT 22 +#define DWT_CTRL_CYCEVTENA_MASK (0x1ul << DWT_CTRL_CYCEVTENA_SHIFT) +#define DWT_CTRL_FOLDEVTENA_SHIFT 21 +#define DWT_CTRL_FOLDEVTENA_MASK (0x1ul << DWT_CTRL_FOLDEVTENA_SHIFT) +#define DWT_CTRL_LSUEVTENA_SHIFT 20 +#define DWT_CTRL_LSUEVTENA_MASK (0x1ul << DWT_CTRL_LSUEVTENA_SHIFT) +#define DWT_CTRL_SLEEPEVTENA_SHIFT 19 +#define DWT_CTRL_SLEEPEVTENA_MASK (0x1ul << DWT_CTRL_SLEEPEVTENA_SHIFT) +#define DWT_CTRL_EXCEVTENA_SHIFT 18 +#define DWT_CTRL_EXCEVTENA_MASK (0x1ul << DWT_CTRL_EXCEVTENA_SHIFT) +#define DWT_CTRL_CPIEVTENA_SHIFT 17 +#define DWT_CTRL_CPIEVTENA_MASK (0x1ul << DWT_CTRL_CPIEVTENA_SHIFT) +#define DWT_CTRL_EXCTRCENA_SHIFT 16 +#define DWT_CTRL_EXCTRCENA_MASK (0x1ul << DWT_CTRL_EXCTRCENA_SHIFT) +#define DWT_CTRL_PCSAMPLENA_SHIFT 12 +#define DWT_CTRL_PCSAMPLENA_MASK (0x1ul << DWT_CTRL_PCSAMPLENA_SHIFT) +#define DWT_CTRL_SYNCTAP_SHIFT 10 +#define DWT_CTRL_SYNCTAP_MASK (0x3ul << DWT_CTRL_SYNCTAP_SHIFT) +#define DWT_CTRL_CYCTAP_SHIFT 9 +#define DWT_CTRL_CYCTAP_MASK (0x1ul << DWT_CTRL_CYCTAP_SHIFT) +#define DWT_CTRL_POSTINIT_SHIFT 5 +#define DWT_CTRL_POSTINIT_MASK (0xful << DWT_CTRL_POSTINIT_SHIFT) +#define DWT_CTRL_POSTPRESET_SHIFT 1 +#define DWT_CTRL_POSTPRESET_MASK (0xful << DWT_CTRL_POSTPRESET_SHIFT) +#define DWT_CTRL_CYCCNTENA_SHIFT 0 +#define DWT_CTRL_CYCCNTENA_MASK (0x1ul << DWT_CTRL_CYCCNTENA_SHIFT) -#define DWT_EXCCNT_EXCCNT_SHIFT 0 /* DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_MASK (0xfful << DWT_EXCCNT_EXCCNT_Pos) /* DWT EXCCNT: EXCCNT Mask */ +/* DWT CPICNT */ -#define DWT_SLEEPCNT_SLEEPCNT_SHIFT 0 /* DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_MASK (0xfful << DWT_SLEEPCNT_SLEEPCNT_Pos) /* DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_CPICNT_CPICNT_SHIFT 0 +#define DWT_CPICNT_CPICNT_MASK (0xfful << DWT_CPICNT_CPICNT_SHIFT) -#define DWT_LSUCNT_LSUCNT_SHIFT 0 /* DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_MASK (0xfful << DWT_LSUCNT_LSUCNT_Pos) /* DWT LSUCNT: LSUCNT Mask */ +/* DWT EXCCNT */ -#define DWT_FOLDCNT_FOLDCNT_SHIFT 0 /* DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_MASK (0xfful << DWT_FOLDCNT_FOLDCNT_Pos) /* DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_EXCCNT_EXCCNT_SHIFT 0 +#define DWT_EXCCNT_EXCCNT_MASK (0xfful << DWT_EXCCNT_EXCCNT_SHIFT) -#define DWT_MASK_MASK_SHIFT 0 /* DWT MASK: MASK Position */ -#define DWT_MASK_MASK_MASK (0x1ful << DWT_MASK_MASK_Pos) /* DWT MASK: MASK Mask */ +/* DWT SLEEPCNT */ -#define DWT_FUNCTION_MATCHED_SHIFT 24 /* DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_MASK (0x1ul << DWT_FUNCTION_MATCHED_Pos) /* DWT FUNCTION: MATCHED Mask */ -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /* DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_MASK (0xful << DWT_FUNCTION_DATAVADDR1_Pos) /* DWT FUNCTION: DATAVADDR1 Mask */ -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /* DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_MASK (0xful << DWT_FUNCTION_DATAVADDR0_Pos) /* DWT FUNCTION: DATAVADDR0 Mask */ -#define DWT_FUNCTION_DATAVSIZE_SHIFT 10 /* DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_MASK (0x3ul << DWT_FUNCTION_DATAVSIZE_Pos) /* DWT FUNCTION: DATAVSIZE Mask */ -#define DWT_FUNCTION_LNK1ENA_SHIFT 9 /* DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_MASK (0x1ul << DWT_FUNCTION_LNK1ENA_Pos) /* DWT FUNCTION: LNK1ENA Mask */ -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /* DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_MASK (0x1ul << DWT_FUNCTION_DATAVMATCH_Pos) /* DWT FUNCTION: DATAVMATCH Mask */ -#define DWT_FUNCTION_CYCMATCH_SHIFT 7 /* DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_MASK 0x1ul << DWT_FUNCTION_CYCMATCH_Pos) /* DWT FUNCTION: CYCMATCH Mask */ -#define DWT_FUNCTION_EMITRANGE_SHIFT 5 /* DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_MASK (0x1ul << DWT_FUNCTION_EMITRANGE_Pos) /* DWT FUNCTION: EMITRANGE Mask */ -#define DWT_FUNCTION_FUNCTION_SHIFT 0 /* DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_MASK (0xful << DWT_FUNCTION_FUNCTION_Pos) /* DWT FUNCTION: FUNCTION Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_SHIFT 0 +#define DWT_SLEEPCNT_SLEEPCNT_MASK (0xfful << DWT_SLEEPCNT_SLEEPCNT_SHIFT) + +/* DWT LSUCNT */ + +#define DWT_LSUCNT_LSUCNT_SHIFT 0 +#define DWT_LSUCNT_LSUCNT_MASK (0xfful << DWT_LSUCNT_LSUCNT_SHIFT) + +/* DWT FOLDCNT */ + +#define DWT_FOLDCNT_FOLDCNT_SHIFT 0 +#define DWT_FOLDCNT_FOLDCNT_MASK (0xfful << DWT_FOLDCNT_FOLDCNT_SHIFT) + +/* DWT MASK */ + +#define DWT_MASK_MASK_SHIFT 0 +#define DWT_MASK_MASK_MASK (0x1ful << DWT_MASK_MASK_SHIFT) + +/* DWT FUNCTION */ + +#define DWT_FUNCTION_MATCHED_SHIFT 24 +#define DWT_FUNCTION_MATCHED_MASK (0x1ul << DWT_FUNCTION_MATCHED_SHIFT) +#define DWT_FUNCTION_DATAVADDR1_SHIFT 16 +#define DWT_FUNCTION_DATAVADDR1_MASK (0xful << DWT_FUNCTION_DATAVADDR1_SHIFT) +#define DWT_FUNCTION_DATAVADDR0_SHIFT 12 +#define DWT_FUNCTION_DATAVADDR0_MASK (0xful << DWT_FUNCTION_DATAVADDR0_SHIFT) +#define DWT_FUNCTION_DATAVSIZE_SHIFT 10 +#define DWT_FUNCTION_DATAVSIZE_MASK (0x3ul << DWT_FUNCTION_DATAVSIZE_SHIFT) +#define DWT_FUNCTION_LNK1ENA_SHIFT 9 +#define DWT_FUNCTION_LNK1ENA_MASK (0x1ul << DWT_FUNCTION_LNK1ENA_SHIFT) +#define DWT_FUNCTION_DATAVMATCH_SHIFT 8 +#define DWT_FUNCTION_DATAVMATCH_MASK (0x1ul << DWT_FUNCTION_DATAVMATCH_SHIFT) +#define DWT_FUNCTION_CYCMATCH_SHIFT 7 +#define DWT_FUNCTION_CYCMATCH_MASK 0x1ul << DWT_FUNCTION_CYCMATCH_SHIFT) +#define DWT_FUNCTION_EMITRANGE_SHIFT 5 +#define DWT_FUNCTION_EMITRANGE_MASK (0x1ul << DWT_FUNCTION_EMITRANGE_SHIFT) +#define DWT_FUNCTION_FUNCTION_SHIFT 0 +#define DWT_FUNCTION_FUNCTION_MASK (0xful << DWT_FUNCTION_FUNCTION_SHIFT) #endif /* __ARCH_ARM_SRC_ARMV7_M_DWT_H */ diff --git a/arch/arm/src/armv7-m/itm.h b/arch/arm/src/armv7-m/itm.h index 9bafa0c7030..0578c8d4e5d 100644 --- a/arch/arm/src/armv7-m/itm.h +++ b/arch/arm/src/armv7-m/itm.h @@ -6,6 +6,7 @@ * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: + * * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright @@ -14,7 +15,7 @@ * - Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without * specific prior written permission. - * * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -79,69 +80,83 @@ /* ITM Register Addresses **********************************************************************/ -#define ITM_PORT(i) (ITM_BASE+(i*4)) /* Stimulus Port 32-bit */ -#define ITM_TER (ITM_BASE+0x0e00) /* Trace Enable Register */ -#define ITM_TPR (ITM_BASE+0x0e40) /* Trace Privilege Register */ -#define ITM_TCR (ITM_BASE+0x0e80) /* Trace Control Register */ -#define ITM_IWR (ITM_BASE+0x0ef8) /* Integration Write Register */ -#define ITM_IRR (ITM_BASE+0x0efc) /* Integration Read Register */ -#define ITM_IMCR (ITM_BASE+0x0f00) /* Integration Mode Control Register */ -#define ITM_LAR (ITM_BASE+0x0fb0) /* Lock Access Register */ -#define ITM_LSR (ITM_BASE+0x0fb4) /* Lock Status Register */ -#define ITM_PID4 (ITM_BASE+0x0fd0) /* Peripheral Identification Register #4 */ -#define ITM_PID5 (ITM_BASE+0x0fd4) /* Peripheral Identification Register #5 */ -#define ITM_PID6 (ITM_BASE+0x0fd8) /* Peripheral Identification Register #6 */ -#define ITM_PID7 (ITM_BASE+0x0fdc) /* Peripheral Identification Register #7 */ -#define ITM_PID0 (ITM_BASE+0x0fe0) /* Peripheral Identification Register #0 */ -#define ITM_PID1 (ITM_BASE+0x0fe4) /* Peripheral Identification Register #1 */ -#define ITM_PID2 (ITM_BASE+0x0fe8) /* Peripheral Identification Register #2 */ -#define ITM_PID3 (ITM_BASE+0x0fec) /* Peripheral Identification Register #3 */ -#define ITM_CID0 (ITM_BASE+0x0ff0) /* Component Identification Register #0 */ -#define ITM_CID1 (ITM_BASE+0x0ff4) /* Component Identification Register #1 */ -#define ITM_CID2 (ITM_BASE+0x0ff8) /* Component Identification Register #2 */ -#define ITM_CID3 (ITM_BASE+0x0ffc) /* Component Identification Register #3 */ +#define ITM_PORT(i) (ITM_BASE + (i * 4)) /* Stimulus Port 32-bit */ +#define ITM_TER (ITM_BASE + 0x0e00) /* Trace Enable Register */ +#define ITM_TPR (ITM_BASE + 0x0e40) /* Trace Privilege Register */ +#define ITM_TCR (ITM_BASE + 0x0e80) /* Trace Control Register */ +#define ITM_IWR (ITM_BASE + 0x0ef8) /* Integration Write Register */ +#define ITM_IRR (ITM_BASE + 0x0efc) /* Integration Read Register */ +#define ITM_IMCR (ITM_BASE + 0x0f00) /* Integration Mode Control Register */ +#define ITM_LAR (ITM_BASE + 0x0fb0) /* Lock Access Register */ +#define ITM_LSR (ITM_BASE + 0x0fb4) /* Lock Status Register */ +#define ITM_PID4 (ITM_BASE + 0x0fd0) /* Peripheral Identification Register #4 */ +#define ITM_PID5 (ITM_BASE + 0x0fd4) /* Peripheral Identification Register #5 */ +#define ITM_PID6 (ITM_BASE + 0x0fd8) /* Peripheral Identification Register #6 */ +#define ITM_PID7 (ITM_BASE + 0x0fdc) /* Peripheral Identification Register #7 */ +#define ITM_PID0 (ITM_BASE + 0x0fe0) /* Peripheral Identification Register #0 */ +#define ITM_PID1 (ITM_BASE + 0x0fe4) /* Peripheral Identification Register #1 */ +#define ITM_PID2 (ITM_BASE + 0x0fe8) /* Peripheral Identification Register #2 */ +#define ITM_PID3 (ITM_BASE + 0x0fec) /* Peripheral Identification Register #3 */ +#define ITM_CID0 (ITM_BASE + 0x0ff0) /* Component Identification Register #0 */ +#define ITM_CID1 (ITM_BASE + 0x0ff4) /* Component Identification Register #1 */ +#define ITM_CID2 (ITM_BASE + 0x0ff8) /* Component Identification Register #2 */ +#define ITM_CID3 (ITM_BASE + 0x0ffc) /* Component Identification Register #3 */ /* ITM Register Bit Field Definitions **********************************************************/ -#define ITM_TPR_PRIVMASK_Pos 0 /* ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xful << ITM_TPR_PRIVMASK_Pos) /* ITM TPR: PRIVMASK Mask */ +/* ITM TPR */ -#define ITM_TCR_BUSY_Pos 23 /* ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /* ITM TCR: BUSY Mask */ -#define ITM_TCR_TraceBusID_Pos 16 /* ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7ful << ITM_TCR_TraceBusID_Pos) /* ITM TCR: ATBID Mask */ -#define ITM_TCR_GTSFREQ_Pos 10 /* ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3ul << ITM_TCR_GTSFREQ_Pos) /* ITM TCR: Global timestamp frequency Mask */ -#define ITM_TCR_TSPrescale_Pos 8 /* ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /* ITM TCR: TSPrescale Mask */ -#define ITM_TCR_SWOENA_Pos 4 /* ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /* ITM TCR: SWOENA Mask */ -#define ITM_TCR_DWTENA_Pos 3 /* ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /* ITM TCR: DWTENA Mask */ -#define ITM_TCR_SYNCENA_Pos 2 /* ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /* ITM TCR: SYNCENA Mask */ -#define ITM_TCR_TSENA_Pos 1 /* ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /* ITM TCR: TSENA Mask */ -#define ITM_TCR_ITMENA_Pos 0 /* ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /* ITM TCR: ITM Enable bit Mask */ +#define ITM_TPR_PRIVMASK_SHIFT 0 +#define ITM_TPR_PRIVMASK_MASK (0xful << ITM_TPR_PRIVMASK_SHIFT) -#define ITM_IWR_ATVALIDM_Pos 0 /* ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /* ITM IWR: ATVALIDM Mask */ +/* ITM TCR */ -#define ITM_IRR_ATREADYM_Pos 0 /* ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /* ITM IRR: ATREADYM Mask */ +#define ITM_TCR_BUSY_SHIFT 23 +#define ITM_TCR_BUSY_MASK (1ul << ITM_TCR_BUSY_SHIFT) +#define ITM_TCR_TraceBusID_SHIFT 16 +#define ITM_TCR_TraceBusID_MASK (0x7ful << ITM_TCR_TraceBusID_SHIFT) +#define ITM_TCR_GTSFREQ_SHIFT 10 +#define ITM_TCR_GTSFREQ_MASK (3ul << ITM_TCR_GTSFREQ_SHIFT) +#define ITM_TCR_TSPrescale_SHIFT 8 +#define ITM_TCR_TSPrescale_MASK (3ul << ITM_TCR_TSPrescale_SHIFT) +#define ITM_TCR_SWOENA_SHIFT 4 +#define ITM_TCR_SWOENA_MASK (1ul << ITM_TCR_SWOENA_SHIFT) +#define ITM_TCR_DWTENA_SHIFT 3 +#define ITM_TCR_DWTENA_MASK (1ul << ITM_TCR_DWTENA_SHIFT) +#define ITM_TCR_SYNCENA_SHIFT 2 +#define ITM_TCR_SYNCENA_MASK (1ul << ITM_TCR_SYNCENA_SHIFT) +#define ITM_TCR_TSENA_SHIFT 1 +#define ITM_TCR_TSENA_MASK (1ul << ITM_TCR_TSENA_SHIFT) +#define ITM_TCR_ITMENA_SHIFT 0 +#define ITM_TCR_ITMENA_MASK (1ul << ITM_TCR_ITMENA_SHIFT) -#define ITM_IMCR_INTEGRATION_Pos 0 /* ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /* ITM IMCR: INTEGRATION Mask */ +/* ITM IWR */ -#define ITM_LSR_ByteAcc_Pos 2 /* ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /* ITM LSR: ByteAcc Mask */ -#define ITM_LSR_Access_Pos 1 /* ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /* ITM LSR: Access Mask */ -#define ITM_LSR_Present_Pos 0 /* ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /* ITM LSR: Present Mask */ +#define ITM_IWR_ATVALIDM_SHIFT 0 +#define ITM_IWR_ATVALIDM_MASK (1ul << ITM_IWR_ATVALIDM_SHIFT) -#define ITM_RXBUFFER_EMPTY 0x5aa55aa5 /* Value identifying g_itm_rxbuffer is ready for next character. */ +/* ITM IRR */ + +#define ITM_IRR_ATREADYM_SHIFT 0 +#define ITM_IRR_ATREADYM_MASK (1ul << ITM_IRR_ATREADYM_SHIFT) + +/* ITM IMCR */ + +#define ITM_IMCR_INTEGRATION_SHIFT 0 +#define ITM_IMCR_INTEGRATION_MASK(1ul << ITM_IMCR_INTEGRATION_SHIFT) + +/* ITM LSR */ + +#define ITM_LSR_ByteAcc_SHIFT 2 +#define ITM_LSR_ByteAcc_MASK (1ul << ITM_LSR_ByteAcc_SHIFT) +#define ITM_LSR_Access_SHIFT 1 +#define ITM_LSR_Access_MASK (1ul << ITM_LSR_Access_SHIFT) +#define ITM_LSR_Present_SHIFT 0 +#define ITM_LSR_Present_MASK (1ul << ITM_LSR_Present_SHIFT) + +/* Value identifying g_itm_rxbuffer is ready for next character. */ + +#define ITM_RXBUFFER_EMPTY 0x5aa55aa5 /*********************************************************************************************** * Public Data diff --git a/arch/arm/src/armv7-m/tpi.h b/arch/arm/src/armv7-m/tpi.h index 3993667f9ea..efef6684e34 100644 --- a/arch/arm/src/armv7-m/tpi.h +++ b/arch/arm/src/armv7-m/tpi.h @@ -6,6 +6,7 @@ * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: + * * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright @@ -14,7 +15,7 @@ * - Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without * specific prior written permission. - * * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -67,110 +68,133 @@ ***********************************************************************************************/ /* Trace Port Interface Register (TPI) Definitions *********************************************/ + /* TPI Register Base Address *******************************************************************/ -#define TPI_BASE (0xe0040000ul) +#define TPI_BASE (0xe0040000ul) /* TPI Register Addresses **********************************************************************/ -#define TPI_SSPSR (TPI_BASE+0x0000) /* Supported Parallel Port Size Register */ -#define TPI_CSPSR (TPI_BASE+0x0004) /* Current Parallel Port Size Register */ -#define TPI_ACPR (TPI_BASE+0x0010) /* Asynchronous Clock Prescaler Register */ -#define TPI_SPPR (TPI_BASE+0x00f0) /* Selected Pin Protocol Register */ -#define TPI_FFSR (TPI_BASE+0x0300) /* Formatter and Flush Status Register */ -#define TPI_FFCR (TPI_BASE+0x0304) /* Formatter and Flush Control Register */ -#define TPI_FSCR (TPI_BASE+0x0308) /* Formatter Synchronization Counter Register */ -#define TPI_TRIGGER (TPI_BASE+0x0ee8) /* TRIGGER */ -#define TPI_FIFO0 (TPI_BASE+0x0eec) /* Integration ETM Data */ -#define TPI_ITATBCTR2 (TPI_BASE+0x0ef0) /* ITATBCTR2 */ -#define TPI_ITATBCTR0 (TPI_BASE+0x0ef8) /* ITATBCTR0 */ -#define TPI_FIFO1 (TPI_BASE+0x0efc) /* Integration ITM Data */ -#define TPI_ITCTRL (TPI_BASE+0x0f00) /* Integration Mode Control */ -#define TPI_CLAIMSET (TPI_BASE+0x0fa0) /* Claim tag set */ -#define TPI_CLAIMCLR (TPI_BASE+0x0fa4) /* Claim tag clear */ -#define TPI_DEVID (TPI_BASE+0x0fc8) /* TPIU_DEVID */ -#define TPI_DEVTYPE (TPI_BASE+0x0fcc) /* TPIU_DEVTYPE */ +#define TPI_SSPSR (TPI_BASE + 0x0000) /* Supported Parallel Port Size Register */ +#define TPI_CSPSR (TPI_BASE + 0x0004) /* Current Parallel Port Size Register */ +#define TPI_ACPR (TPI_BASE + 0x0010) /* Asynchronous Clock Prescaler Register */ +#define TPI_SPPR (TPI_BASE + 0x00f0) /* Selected Pin Protocol Register */ +#define TPI_FFSR (TPI_BASE + 0x0300) /* Formatter and Flush Status Register */ +#define TPI_FFCR (TPI_BASE + 0x0304) /* Formatter and Flush Control Register */ +#define TPI_FSCR (TPI_BASE + 0x0308) /* Formatter Synchronization Counter Register */ +#define TPI_TRIGGER (TPI_BASE + 0x0ee8) /* TRIGGER */ +#define TPI_FIFO0 (TPI_BASE + 0x0eec) /* Integration ETM Data */ +#define TPI_ITATBCTR2 (TPI_BASE + 0x0ef0) /* ITATBCTR2 */ +#define TPI_ITATBCTR0 (TPI_BASE + 0x0ef8) /* ITATBCTR0 */ +#define TPI_FIFO1 (TPI_BASE + 0x0efc) /* Integration ITM Data */ +#define TPI_ITCTRL (TPI_BASE + 0x0f00) /* Integration Mode Control */ +#define TPI_CLAIMSET (TPI_BASE + 0x0fa0) /* Claim tag set */ +#define TPI_CLAIMCLR (TPI_BASE + 0x0fa4) /* Claim tag clear */ +#define TPI_DEVID (TPI_BASE + 0x0fc8) /* TPIU_DEVID */ +#define TPI_DEVTYPE (TPI_BASE + 0x0fcc) /* TPIU_DEVTYPE */ /* TPI Register Bit Field Definitions **********************************************************/ -#define TPI_ACPR_PRESCALER_Pos 0 /* TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1ffful << TPI_ACPR_PRESCALER_Pos) /* TPI ACPR: PRESCALER Mask */ +/* TPI ACPR */ -#define TPI_SPPR_TXMODE_Pos 0 /* TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3ul << TPI_SPPR_TXMODE_Pos) /* TPI SPPR: TXMODE Mask */ +#define TPI_ACPR_PRESCALER_SHIFT 0 +#define TPI_ACPR_PRESCALER_MASK (0x1ffful << TPI_ACPR_PRESCALER_SHIFT) -#define TPI_FFSR_FtNonStop_Pos 3 /* TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1ul << TPI_FFSR_FtNonStop_Pos) /* TPI FFSR: FtNonStop Mask */ -#define TPI_FFSR_TCPresent_Pos 2 /* TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1ul << TPI_FFSR_TCPresent_Pos) /* TPI FFSR: TCPresent Mask */ -#define TPI_FFSR_FtStopped_Pos 1 /* TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1ul << TPI_FFSR_FtStopped_Pos) /* TPI FFSR: FtStopped Mask */ -#define TPI_FFSR_FlInProg_Pos 0 /* TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1ul << TPI_FFSR_FlInProg_Pos) /* TPI FFSR: FlInProg Mask */ +/* TPI SPPR */ -#define TPI_FFCR_TrigIn_Pos 8 /* TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1ul << TPI_FFCR_TrigIn_Pos) /* TPI FFCR: TrigIn Mask */ -#define TPI_FFCR_EnFCont_Pos 1 /* TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1ul << TPI_FFCR_EnFCont_Pos) /* TPI FFCR: EnFCont Mask */ +#define TPI_SPPR_TXMODE_SHIFT 0 +#define TPI_SPPR_TXMODE_MASK (0x3ul << TPI_SPPR_TXMODE_SHIFT) -#define TPI_TRIGGER_TRIGGER_Pos 0 /* TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1ul << TPI_TRIGGER_TRIGGER_Pos) /* TPI TRIGGER: TRIGGER Mask */ +/* TPI FFSR */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /* TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3ul << TPI_FIFO0_ITM_ATVALID_Pos) /* TPI FIFO0: ITM_ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27 /* TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3ul << TPI_FIFO0_ITM_bytecount_Pos) /* TPI FIFO0: ITM_bytecount Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /* TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3ul << TPI_FIFO0_ETM_ATVALID_Pos) /* TPI FIFO0: ETM_ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24 /* TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3ul << TPI_FIFO0_ETM_bytecount_Pos) /* TPI FIFO0: ETM_bytecount Mask */ -#define TPI_FIFO0_ETM2_Pos 16 /* TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xfful << TPI_FIFO0_ETM2_Pos) /* TPI FIFO0: ETM2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8 /* TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xfful << TPI_FIFO0_ETM1_Pos) /* TPI FIFO0: ETM1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0 /* TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xfful << TPI_FIFO0_ETM0_Pos) /* TPI FIFO0: ETM0 Mask */ +#define TPI_FFSR_FtNonStop_SHIFT 3 +#define TPI_FFSR_FtNonStop_MASK (0x1ul << TPI_FFSR_FtNonStop_SHIFT) +#define TPI_FFSR_TCPresent_SHIFT 2 +#define TPI_FFSR_TCPresent_MASK (0x1ul << TPI_FFSR_TCPresent_SHIFT) +#define TPI_FFSR_FtStopped_SHIFT 1 +#define TPI_FFSR_FtStopped_MASK (0x1ul << TPI_FFSR_FtStopped_SHIFT) +#define TPI_FFSR_FlInProg_SHIFT 0 +#define TPI_FFSR_FlInProg_MASK (0x1ul << TPI_FFSR_FlInProg_SHIFT) -#define TPI_ITATBCTR2_ATREADY_Pos 0 /* TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1ul << TPI_ITATBCTR2_ATREADY_Pos) /* TPI ITATBCTR2: ATREADY Mask */ +/* TPI FFCR */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /* TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3ul << TPI_FIFO1_ITM_ATVALID_Pos) /* TPI FIFO1: ITM_ATVALID Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27 /* TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3ul << TPI_FIFO1_ITM_bytecount_Pos) /* TPI FIFO1: ITM_bytecount Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /* TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3ul << TPI_FIFO1_ETM_ATVALID_Pos) /* TPI FIFO1: ETM_ATVALID Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24 /* TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3ul << TPI_FIFO1_ETM_bytecount_Pos) /* TPI FIFO1: ETM_bytecount Mask */ -#define TPI_FIFO1_ITM2_Pos 16 /* TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xfful << TPI_FIFO1_ITM2_Pos) /* TPI FIFO1: ITM2 Mask */ -#define TPI_FIFO1_ITM1_Pos 8 /* TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xfful << TPI_FIFO1_ITM1_Pos) /* TPI FIFO1: ITM1 Mask */ -#define TPI_FIFO1_ITM0_Pos 0 /* TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xfful << TPI_FIFO1_ITM0_Pos) /* TPI FIFO1: ITM0 Mask */ +#define TPI_FFCR_TrigIn_SHIFT 8 +#define TPI_FFCR_TrigIn_MASK (0x1ul << TPI_FFCR_TrigIn_SHIFT) +#define TPI_FFCR_EnFCont_SHIFT 1 +#define TPI_FFCR_EnFCont_MASK (0x1ul << TPI_FFCR_EnFCont_SHIFT) -#define TPI_ITATBCTR0_ATREADY_Pos 0 /* TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1ul << TPI_ITATBCTR0_ATREADY_Pos) /* TPI ITATBCTR0: ATREADY Mask */ +#define TPI_TRIGGER_TRIGGER_SHIFT 0 +#define TPI_TRIGGER_TRIGGER_MASK (0x1ul << TPI_TRIGGER_TRIGGER_SHIFT) -#define TPI_ITCTRL_Mode_Pos 0 /* TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1ul << TPI_ITCTRL_Mode_Pos) /* TPI ITCTRL: Mode Mask */ +/* TPI FIFO0 */ -#define TPI_DEVID_NRZVALID_Pos 11 /* TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1ul << TPI_DEVID_NRZVALID_Pos) /* TPI DEVID: NRZVALID Mask */ -#define TPI_DEVID_MANCVALID_Pos 10 /* TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1ul << TPI_DEVID_MANCVALID_Pos) /* TPI DEVID: MANCVALID Mask */ -#define TPI_DEVID_PTINVALID_Pos 9 /* TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1ul << TPI_DEVID_PTINVALID_Pos) /* TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6 /* TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7ul << TPI_DEVID_MinBufSz_Pos) /* TPI DEVID: MinBufSz Mask */ -#define TPI_DEVID_AsynClkIn_Pos 5 /* TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1ul << TPI_DEVID_AsynClkIn_Pos) /* TPI DEVID: AsynClkIn Mask */ -#define TPI_DEVID_NrTraceInput_Pos 0 /* TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1ful << TPI_DEVID_NrTraceInput_Pos) /* TPI DEVID: NrTraceInput Mask */ +#define TPI_FIFO0_ITM_ATVALID_SHIFT 29 +#define TPI_FIFO0_ITM_ATVALID_MASK (0x3ul << TPI_FIFO0_ITM_ATVALID_SHIFT) +#define TPI_FIFO0_ITM_bytecount_SHIFT 27 +#define TPI_FIFO0_ITM_bytecount_MASK (0x3ul << TPI_FIFO0_ITM_bytecount_SHIFT) +#define TPI_FIFO0_ETM_ATVALID_SHIFT 26 +#define TPI_FIFO0_ETM_ATVALID_MASK (0x3ul << TPI_FIFO0_ETM_ATVALID_SHIFT) +#define TPI_FIFO0_ETM_bytecount_SHIFT 24 +#define TPI_FIFO0_ETM_bytecount_MASK (0x3ul << TPI_FIFO0_ETM_bytecount_SHIFT) +#define TPI_FIFO0_ETM2_SHIFT 16 +#define TPI_FIFO0_ETM2_MASK (0xfful << TPI_FIFO0_ETM2_SHIFT) +#define TPI_FIFO0_ETM1_SHIFT 8 +#define TPI_FIFO0_ETM1_MASK (0xfful << TPI_FIFO0_ETM1_SHIFT) +#define TPI_FIFO0_ETM0_SHIFT 0 +#define TPI_FIFO0_ETM0_MASK (0xfful << TPI_FIFO0_ETM0_SHIFT) -#define TPI_DEVTYPE_SubType_Pos 0 /* TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xful << TPI_DEVTYPE_SubType_Pos) /* TPI DEVTYPE: SubType Mask */ -#define TPI_DEVTYPE_MajorType_Pos 4 /* TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xful << TPI_DEVTYPE_MajorType_Pos) /* TPI DEVTYPE: MajorType Mask */ +/* TPI ITATBCTR2 */ + +#define TPI_ITATBCTR2_ATREADY_SHIFT 0 +#define TPI_ITATBCTR2_ATREADY_MASK (0x1ul << TPI_ITATBCTR2_ATREADY_SHIFT) + +/* TPI FIFO1 */ + +#define TPI_FIFO1_ITM_ATVALID_SHIFT 29 +#define TPI_FIFO1_ITM_ATVALID_MASK (0x3ul << TPI_FIFO1_ITM_ATVALID_SHIFT) +#define TPI_FIFO1_ITM_bytecount_SHIFT 27 +#define TPI_FIFO1_ITM_bytecount_MASK (0x3ul << TPI_FIFO1_ITM_bytecount_SHIFT) +#define TPI_FIFO1_ETM_ATVALID_SHIFT 26 +#define TPI_FIFO1_ETM_ATVALID_MASK (0x3ul << TPI_FIFO1_ETM_ATVALID_SHIFT) +#define TPI_FIFO1_ETM_bytecount_SHIFT 24 +#define TPI_FIFO1_ETM_bytecount_MASK (0x3ul << TPI_FIFO1_ETM_bytecount_SHIFT) +#define TPI_FIFO1_ITM2_SHIFT 16 +#define TPI_FIFO1_ITM2_MASK (0xfful << TPI_FIFO1_ITM2_SHIFT) +#define TPI_FIFO1_ITM1_SHIFT 8 +#define TPI_FIFO1_ITM1_MASK (0xfful << TPI_FIFO1_ITM1_SHIFT) +#define TPI_FIFO1_ITM0_SHIFT 0 +#define TPI_FIFO1_ITM0_MASK (0xfful << TPI_FIFO1_ITM0_SHIFT) + +/* TPI ITATBCTR0 */ + +#define TPI_ITATBCTR0_ATREADY_SHIFT 0 +#define TPI_ITATBCTR0_ATREADY_MASK (0x1ul << TPI_ITATBCTR0_ATREADY_SHIFT) + +/* TPI ITCTRL */ + +#define TPI_ITCTRL_Mode_SHIFT 0 +#define TPI_ITCTRL_Mode_MASK (0x1ul << TPI_ITCTRL_Mode_SHIFT) + +/* TPI DEVID */ + +#define TPI_DEVID_NRZVALID_SHIFT 11 +#define TPI_DEVID_NRZVALID_MASK (0x1ul << TPI_DEVID_NRZVALID_SHIFT) +#define TPI_DEVID_MANCVALID_SHIFT 10 +#define TPI_DEVID_MANCVALID_MASK (0x1ul << TPI_DEVID_MANCVALID_SHIFT) +#define TPI_DEVID_PTINVALID_SHIFT 9 +#define TPI_DEVID_PTINVALID_MASK (0x1ul << TPI_DEVID_PTINVALID_SHIFT) +#define TPI_DEVID_MinBufSz_SHIFT 6 +#define TPI_DEVID_MinBufSz_MASK (0x7ul << TPI_DEVID_MinBufSz_SHIFT) +#define TPI_DEVID_AsynClkIn_SHIFT 5 +#define TPI_DEVID_AsynClkIn_MASK (0x1ul << TPI_DEVID_AsynClkIn_SHIFT) +#define TPI_DEVID_NrTraceInput_SHIFT 0 +#define TPI_DEVID_NrTraceInput_MASK (0x1ful << TPI_DEVID_NrTraceInput_SHIFT) + +/* TPI DEVTYPE */ + +#define TPI_DEVTYPE_SubType_SHIFT 0 +#define TPI_DEVTYPE_SubType_MASK (0xful << TPI_DEVTYPE_SubType_SHIFT) +#define TPI_DEVTYPE_MajorType_SHIFT 4 +#define TPI_DEVTYPE_MajorType_MASK (0xful << TPI_DEVTYPE_MajorType_SHIFT) #endif /* __ARCH_ARM_SRC_ARMV7_M_TPI_H */ diff --git a/arch/arm/src/armv7-m/up_itm.c b/arch/arm/src/armv7-m/up_itm.c index c3774ac6f5c..5a62cddbf28 100644 --- a/arch/arm/src/armv7-m/up_itm.c +++ b/arch/arm/src/armv7-m/up_itm.c @@ -99,8 +99,8 @@ uint32_t itm_sendchar(uint32_t ch) { - if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (getreg32(ITM_TER) & (1UL << 0))) /* ITM Port #0 enabled */ + if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_MASK) && /* ITM enabled */ + (getreg32(ITM_TER) & (1UL << 0))) /* ITM Port #0 enabled */ { while (getreg32(ITM_PORT(0)) == 0); putreg8((uint8_t)ch, ITM_PORT(0)); diff --git a/arch/arm/src/armv7-m/up_itm_syslog.c b/arch/arm/src/armv7-m/up_itm_syslog.c index d63fed09adb..dc1258ba60f 100644 --- a/arch/arm/src/armv7-m/up_itm_syslog.c +++ b/arch/arm/src/armv7-m/up_itm_syslog.c @@ -110,7 +110,7 @@ static int itm_putc(int ch) { /* ITM enabled */ - if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0) + if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_MASK) == 0) { return EOF; }