mirror of
https://github.com/apache/nuttx.git
synced 2026-06-05 15:58:59 +08:00
Add exception handling logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3023 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -166,6 +166,22 @@ static int up_getgrp(unsigned int irq)
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return -EINVAL;
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}
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/****************************************************************************
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* Name: avr32_xcptn
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*
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* Description:
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* Handlers for unexpected execptions. All are fatal error conditions.
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*
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****************************************************************************/
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static int avr32_xcptn(int irq, FAR void *context)
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{
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(void)irqsave();
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lldbg("PANIC!!! Exception IRQ: %d\n", irq);
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@@ -177,6 +193,7 @@ static int up_getgrp(unsigned int irq)
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void up_irqinitialize(void)
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{
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int group;
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int irq;
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/* Initialize the table that provides the value of the IPR register to
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* use to assign a group to different interrupt priorities.
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@@ -194,9 +211,9 @@ void up_irqinitialize(void)
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*/
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for (group = 0; group < AVR32_IRQ_MAXGROUPS; group++)
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{
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putreg32(g_ipr[0], AVR32_INTC_IPR(group));
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}
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{
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putreg32(g_ipr[0], AVR32_INTC_IPR(group));
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}
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/* currents_regs is non-NULL only while processing an interrupt */
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@@ -204,9 +221,10 @@ void up_irqinitialize(void)
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/* Attach the exception handlers */
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#ifdef CONFIG_DEBUG
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#warning "Missing logic"
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#endif
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for (irq = 0; irq < AVR32_IRQ_NEVENTS; irq++)
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{
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irq_attach(irq, avr32_xcptn);
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}
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/* And finally, enable interrupts */
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@@ -246,10 +264,13 @@ int up_prioritize_irq(int irq, int priority)
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* Name: avr32_intirqno
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*
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* Description:
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* Return the highest priority pending INT0 interrupt.
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* Return the highest priority pending INTn interrupt (hwere n=level).
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* This is called directly from interrupt handling logic. This should be
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* save since the UC3B will save all C scratch/volatile registers (and
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* this function should not alter the perserved/static registers).
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*
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****************************************************************************/
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#warning "Is this safe to call from assembly?"
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unsigned int avr32_intirqno(unsigned int level)
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{
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/* Get the group that caused the interrupt: "ICRn identifies the group with
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+152
-103
@@ -38,41 +38,51 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/avr32/avr32.h>
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#include <arch/irq.h>
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/****************************************************************************
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* External Symbols
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****************************************************************************/
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.global avr32_int0irqno /* Returns the IRQ number of an INT0 interrupt */
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.global avr32_int1irqno /* Returns the IRQ number of an INT1 interrupt */
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.global avr32_int2irqno /* Returns the IRQ number of an INT2 interrupt */
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.global avr32_int3irqno /* Returns the IRQ number of an INT3 interrupt */
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.global up_doirq /* Dispatch an IRQ */
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.global up_fullcontextrestore /* Restore new task contex */
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.global avr32_int0irqno /* Returns IRQ number of INT0 event */
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.global avr32_int1irqno /* Returns IRQ number of INT1 event */
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.global avr32_int2irqno /* Returns IRQ number of INT2 event */
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.global avr32_int3irqno /* Returns IRQ number of INT3 event */
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.global up_doirq /* Dispatch an IRQ */
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.global up_fullcontextrestore /* Restore new task contex */
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/****************************************************************************
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* Macros
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****************************************************************************/
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#warning "Missing Logic"
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/* Exception entry logic. On entry, thee context save area looks like: */
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/* xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx SR PC */
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/* ^ ^+2*4 */
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/* Upon joining common logic, the context save are will look like: */
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/* xx xx xx xx xx xx xx xx xx xx xx xx xx xx 10 SR PC */
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/* ^ ^+3*4 */
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/* and r10 will hold the exception's IRQ number */
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.macro HANDLER, label, irqno
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\label:
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rjmp avr32_excptcommon /* FIXME!!! Need IRQ in a register */
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st.w --sp, r10
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mov r10, \irqno
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rjmp avr32_xcptcommon /* FIXME!!! Need IRQ in a register */
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.endm
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/****************************************************************************
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* Exception Vector Table
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****************************************************************************/
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/* The Exception Vector Base Address (EVBA) register will contain "a pointer
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* to the exception routines. All exception routines start at this address,
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* or at a defined offset relative to the address. Special alignment
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* requirements may apply for EVBA, depending on the implementation of the
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* interrupt controller."
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*/
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/* The Exception Vector Base Address (EVBA) register will contain "a */
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/* pointer to the exception routines. All exception routines start at this */
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/* address, or at a defined offset relative to the address. Special */
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/* alignment requirements may apply for EVBA, depending on the */
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/* implementation of the interrupt controller." */
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/* REVISIT: This alignment requirement may be different on other AVR32s */
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/* REVISIT: This alignment requirement may be different on other AVR32s */
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.text
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.balign 0x200
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@@ -80,85 +90,83 @@
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.global vectortab
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.type vectortab, @function
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vectortab:
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lda.w pc, avr32_unrec /* EVBA+0x00 Unrecoverable exception */
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lda.w pc, avr32_tlbmult /* EVBA+0x04 TLB multiple hit */
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lda.w pc, avr32_busdata /* EVBA+0x08 Bus error data fetch */
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lda.w pc, avr32_businst /* EVBA+0x0c Bus error instruction fetch */
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lda.w pc, avr32_nmi /* EVBA+0x10 NMI */
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lda.w pc, avr32_instaddr /* EVBA+0x14 Instruction Address */
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lda.w pc, avr32_itlbrot /* EVBA+0x18 ITLB Protection */
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lda.w pc, avr32_bp /* EVBA+0x1c Breakpoint */
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lda.w pc, avr32_invinst /* EVBA+0x20 Illegal Opcode */
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lda.w pc, avr32_unimpinst /* EVBA+0x24 Unimplemented instruction */
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lda.w pc, avr32_priv /* EVBA+0x28 Privilege violation */
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lda.w pc, avr32_fp /* EVBA+0x2c Floating-point */
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lda.w pc, avr32_cop /* EVBA+0x30 Coprocessor absent */
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lda.w pc, avr32_rddata /* EVBA+0x34 Data Address (Read) */
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lda.w pc, avr32_wrdata /* EVBA+0x38 Data Address (Write) */
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lda.w pc, avr32_tddtlbprot /* EVBA+0x3c DTLB Protection (Read) */
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lda.w pc, avr32_wrdtlbprot /* EVBA+0x40 DTLB Protection (Write) */
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lda.w pc, avr32_dltbmod /* EVBA+0x44 DTLB Modified */
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lda.w pc, avr32_unrec /* EVBA+0x00 Unrecoverable exception */
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lda.w pc, avr32_tlbmult /* EVBA+0x04 TLB multiple hit */
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lda.w pc, avr32_busdata /* EVBA+0x08 Bus error data fetch */
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lda.w pc, avr32_businst /* EVBA+0x0c Bus error instr fetch */
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lda.w pc, avr32_nmi /* EVBA+0x10 NMI */
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lda.w pc, avr32_instaddr /* EVBA+0x14 Instruction Address */
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lda.w pc, avr32_itlbrot /* EVBA+0x18 ITLB Protection */
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lda.w pc, avr32_bp /* EVBA+0x1c Breakpoint */
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lda.w pc, avr32_invinst /* EVBA+0x20 Illegal Opcode */
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lda.w pc, avr32_unimpinst /* EVBA+0x24 Unimplemented instruction */
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lda.w pc, avr32_priv /* EVBA+0x28 Privilege violation */
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lda.w pc, avr32_fp /* EVBA+0x2c Floating-point */
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lda.w pc, avr32_cop /* EVBA+0x30 Coprocessor absent */
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lda.w pc, avr32_rddata /* EVBA+0x34 Data Address (Read) */
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lda.w pc, avr32_wrdata /* EVBA+0x38 Data Address (Write) */
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lda.w pc, avr32_tddtlbprot /* EVBA+0x3c DTLB Protection (Read) */
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lda.w pc, avr32_wrdtlbprot /* EVBA+0x40 DTLB Protection (Write) */
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lda.w pc, avr32_dltbmod /* EVBA+0x44 DTLB Modified */
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.rept 2
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lda.w pc, avr32_badvector /* EVBA+0x48-0x4c No such vector */
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lda.w pc, avr32_badvector /* EVBA+0x48-0x4c No such vector */
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.endr
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lda.w pc, avr32_itlbmiss /* EVBA+0x50 ITLB Miss */
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lda.w pc, avr32_itlbmiss /* EVBA+0x50 ITLB Miss */
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.rept 3
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lda.w pc, avr32_badvector /* EVBA+0x54-0x5c No such vector */
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lda.w pc, avr32_badvector /* EVBA+0x54-0x5c No such vector */
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.endr
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lda.w pc, avr32_rddtlb /* EVBA+0x60 DTLB Miss (Read) */
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lda.w pc, avr32_rddtlb /* EVBA+0x60 DTLB Miss (Read) */
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.rept 3
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lda.w pc, avr32_badvector /* EVBA+0x64-0x6c No such vector */
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lda.w pc, avr32_badvector /* EVBA+0x64-0x6c No such vector */
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.endr
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lda.w pc, avr32_wrdtlb /* EVBA+0x70 DTLB Miss (Write) */
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lda.w pc, avr32_wrdtlb /* EVBA+0x70 DTLB Miss (Write) */
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.rept (3+4*8)
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lda.w pc, avr32_badvector /* EVBA+0x74-0xfc No such vector */
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lda.w pc, avr32_badvector /* EVBA+0x74-0xfc No such vector */
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.endr
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lda.w pc, avr32_super /* EVBA+0x100 Supervisor call */
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lda.w pc, avr32_super /* EVBA+0x100 Supervisor call */
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/****************************************************************************
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* Interrupts
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****************************************************************************/
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/* The interrupt controller must provide an address that is relative to the
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* the EVBA so it is natural to define these interrupt vectors just after
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* the exception table.
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* On entry to each interrupt handler, R8-R12, LR, PC and SR have already been
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* pushed onto the system stack by the MCU.
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*
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* An interrupt may disappear while it is being fetched by the CPU and, hence,
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* spurious interrupt may result.
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*/
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/* The interrupt controller must provide an address that is relative to the */
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/* the EVBA so it is natural to define these interrupt vectors just after */
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/* the exception table. On entry to each interrupt handler, R8-R12, LR, PC */
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/* and SR have already been pushed onto the system stack by the MCU. */
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/* */
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/* An interrupt may disappear while it is being fetched by the CPU and, */
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/* hence spurious interrupt may result. */
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.balign 4
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.global avr32_int0
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avr32_int0:
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mov r12, 0 /* r12=interrupt level 0 */
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rjmp avr32_intcommon /* Jump to common interrupt handling logic */
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mov r12, 0 /* r12=interrupt level 0 */
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rjmp avr32_intcommon /* Jump to common interrupt handling logic */
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.balign 4
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.global avr32_int1
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avr32_int1:
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mov r12, 1 /* r12=interrupt level 1 */
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rjmp avr32_intcommon /* Jump to common interrupt handling logic */
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mov r12, 1 /* r12=interrupt level 1 */
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rjmp avr32_intcommon /* Jump to common interrupt handling logic */
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.balign 4
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.global avr32_int2
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avr32_int2:
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mov r12, 2 /* r12=interrupt level 2 */
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rjmp avr32_intcommon /* Jump to common interrupt handling logic */
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mov r12, 2 /* r12=interrupt level 2 */
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rjmp avr32_intcommon /* Jump to common interrupt handling logic */
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.balign 4
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.global avr32_int3
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avr32_int3:
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mov r12, 3 /* r12=interrupt level 3 */
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mov r12, 3 /* r12=interrupt level 3 */
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/* Common interrupt handling logic. R12 holds the interrupt level index */
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/* Common interrupt handling logic. R12 holds the interrupt level index */
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avr32_intcommon:
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mcall .Lavr32_intirqno /* Get the IRQ number of the int0 event */
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cp.w r12, 0 /* Negated errno returned if spurious interrupt */
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brge avr32_common /* Jump to the common exception handling logic */
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rete /* Ignore spurious interrupt */
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mcall .Lavr32_intirqno /* Get the IRQ number of the int0 event */
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cp.w r12, 0 /* Negative returned if spurious interrupt */
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brge avr32_common /* Jump to the common xcptn handling logic */
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rete /* Ignore spurious interrupt */
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.Lavr32_intirqno:
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.word avr32_intirqno
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@@ -167,41 +175,79 @@ avr32_intcommon:
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* Exception Vector Handlers
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****************************************************************************/
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/* Exception Handlers */
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/* Exception Handlers: */
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/* On entry to each, the context save area looks like this: */
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/* xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx SR PC */
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/* ^ ^+2*4 */
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HANDLER avr32_unrec, AVR32_IRQ_UNREC /* Unrecoverable exception */
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HANDLER avr32_tlbmult, AVR32_IRQ_TLBMULT /* TLB multiple hit */
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HANDLER avr32_unrec, AVR32_IRQ_UNREC /* Unrecoverable xcptn */
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HANDLER avr32_tlbmult, AVR32_IRQ_TLBMULT /* TLB multiple hit */
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HANDLER avr32_busdata, AVR32_IRQ_BUSDATA /* Bus error data fetch */
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HANDLER avr32_businst, AVR32_IRQ_BUSINST /* Bus error instruction fetch */
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HANDLER avr32_nmi, AVR32_IRQ_NMI /* NMI */
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HANDLER avr32_instaddr, AVR32_IRQ_INSTADDR /* Instruction Address */
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HANDLER avr32_itlbrot, AVR32_IRQ_ITLBPROT /* ITLB Protection */
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HANDLER avr32_bp, AVR32_IRQ_BP /* Breakpoint */
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HANDLER avr32_invinst, AVR32_IRQ_INVINST /* Illegal Opcode */
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HANDLER avr32_unimpinst, AVR32_IRQ_UNIMPINST /* Unimplemented instruction */
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HANDLER avr32_priv, AVR32_IRQ_PRIV /* Privilege violation */
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HANDLER avr32_fp, AVR32_IRQ_FP /* Floating-point */
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HANDLER avr32_cop, AVR32_IRQ_COP /* Coprocessor absent */
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HANDLER avr32_rddata, AVR32_IRQ_RDDATA /* Data Address (Read) */
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HANDLER avr32_wrdata, AVR32_IRQ_WRDATA /* Data Address (Write) */
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HANDLER avr32_tddtlbprot, AVR32_IRQ_RDDTLBPROT /* DTLB Protection (Read) */
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HANDLER avr32_wrdtlbprot, AVR32_IRQ_WRDTLBPROT /* DTLB Protection (Write) */
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HANDLER avr32_dltbmod, AVR32_IRQ_DLTBMOD /* DTLB Modified */
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HANDLER avr32_itlbmiss, AVR32_IRQ_ITLBMISS /* ITLB Miss */
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HANDLER avr32_rddtlb, AVR32_IRQ_RDDTLB /* DTLB Miss (Read) */
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HANDLER avr32_wrdtlb, AVR32_IRQ_WRDTLB /* DTLB Miss (Write) */
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HANDLER avr32_super, AVR32_IRQ_SUPER /* Supervisor call */
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HANDLER avr32_badvector, AVR32_IRQ_BADVECTOR /* No such vector */
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HANDLER avr32_businst, AVR32_IRQ_BUSINST /* Bus err instr fetch */
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HANDLER avr32_nmi, AVR32_IRQ_NMI /* NMI */
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HANDLER avr32_instaddr, AVR32_IRQ_INSTADDR /* Instruction Address */
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HANDLER avr32_itlbrot, AVR32_IRQ_ITLBPROT /* ITLB Protection */
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HANDLER avr32_bp, AVR32_IRQ_BP /* Breakpoint */
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HANDLER avr32_invinst, AVR32_IRQ_INVINST /* Illegal Opcode */
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HANDLER avr32_unimpinst, AVR32_IRQ_UNIMPINST /* Unimplemented intsr */
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HANDLER avr32_priv, AVR32_IRQ_PRIV /* Privilege violation */
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HANDLER avr32_fp, AVR32_IRQ_FP /* Floating-point */
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HANDLER avr32_cop, AVR32_IRQ_COP /* Coprocessor absent */
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HANDLER avr32_rddata, AVR32_IRQ_RDDATA /* Data Address (RD) */
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HANDLER avr32_wrdata, AVR32_IRQ_WRDATA /* Data Address (WR) */
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HANDLER avr32_tddtlbprot, AVR32_IRQ_RDDTLBPROT /* DTLB Protection (RD) */
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HANDLER avr32_wrdtlbprot, AVR32_IRQ_WRDTLBPROT /* DTLB Protection (WR) */
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HANDLER avr32_dltbmod, AVR32_IRQ_DLTBMOD /* DTLB Modified */
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HANDLER avr32_itlbmiss, AVR32_IRQ_ITLBMISS /* ITLB Miss */
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HANDLER avr32_rddtlb, AVR32_IRQ_RDDTLB /* DTLB Miss (RD) */
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HANDLER avr32_wrdtlb, AVR32_IRQ_WRDTLB /* DTLB Miss (WR) */
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HANDLER avr32_super, AVR32_IRQ_SUPER /* Supervisor call */
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HANDLER avr32_badvector, AVR32_IRQ_BADVECTOR /* No such vector */
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/* Common exception handling logic. Unlike the interrupt handlers, the
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* exception handlers do not save R8-R12, and LR on the stack. Only the PC
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* and SR have been pushed onto the system stack by the MCU. The following
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* loic creates a common stack frame for exception handlers prior to joining
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* to the common interrupt/exception logic below.
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*/
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/* Common exception handling logic. Unlike the interrupt handlers, the */
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/* exception handlers do not save R8-R12, and LR on the stack. Only the PC */
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/* and SR have been pushed onto the system stack by the MCU. The following */
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/* logic creates a common stack frame for exception handlers prior to */
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/* joining to the common interrupt/exception logic below. */
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/* */
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/* The context save area looks like this on entry to the HANDLER above. */
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/* xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx SR PC */
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/* ^ ^+2*4 */
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/* Upon joining common logic here, the context save are will loke: */
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/* xx xx xx xx xx xx xx xx xx xx xx xx xx xx 10 SR PC */
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/* ^ ^+3*4 */
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/* and r10 will hold the exception's IRQ number */
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/* */
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/* either (1) non-time-critical, or (2) fatal. Obvious, that would not be */
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/* the case if TLB missing handling is required. Such time-critical vector */
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/* handling should be handled differently. */
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avr32_excptcommon:
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#warning "Missing Logic"
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avr32_xcptcommon:
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/* Save r10-r12, lr on the stack: */
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/* xx xx xx xx xx xx xx xx xx xx xx LR 12 11 10 SR PC */
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/* ^ ^+4*4 ^+6*4 */
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stm --sp, r11-r12, lr
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/* Move SR and PC into the expected position: */
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/* xx xx xx xx xx xx xx xx xx SR PC LI 12 11 10 SR PC */
|
||||
/* ^ ^+8*4 */
|
||||
|
||||
ld.w r11, sp[4*4]
|
||||
ld.w r12, sp[5*4]
|
||||
stm --sp, r11-r12
|
||||
|
||||
/* Save r8 and r8: */
|
||||
/* xx xx xx xx xx xx xx xx xx SR PC LI 12 11 10 SR PC */
|
||||
/* ^ ^+6*4 ^+8*4 */
|
||||
|
||||
st.w sp[6*4], r9
|
||||
st.w sp[7*4], r8
|
||||
|
||||
/* Move the IRQ number in r12 and fall through to the common event handling */
|
||||
/* logic. */
|
||||
|
||||
mov r12, r10
|
||||
|
||||
/****************************************************************************
|
||||
* Common Event Handling Logic
|
||||
@@ -215,7 +261,7 @@ avr32_excptcommon:
|
||||
/* */
|
||||
/* The context save area looks like this: */
|
||||
/* xx xx xx xx xx xx xx xx xx SR PC LR 12 11 10 09 08 */
|
||||
/* ^ +8*4 */
|
||||
/* ^ ^+8*4 */
|
||||
/* This function will finish construction of the register save structure */
|
||||
/* and call the IRQ dispatching logic. */
|
||||
|
||||
@@ -256,12 +302,12 @@ avr32_common:
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
mov r7, sp
|
||||
lddpc sp, .Lup_instackbase
|
||||
lddpc sp, .Linstackbaseptr
|
||||
#endif
|
||||
|
||||
/* Call up_doirq with r12=IRQ number and r11=register save area */
|
||||
|
||||
mcall .Lup_doirq
|
||||
mcall .Ldoirqptr
|
||||
|
||||
/* Restore the user stack pointer. */
|
||||
/* 07 06 05 04 03 02 01 00 SP SR PC LR 12 11 10 09 08 */
|
||||
@@ -296,13 +342,19 @@ avr32_common:
|
||||
/* the task context to restore. */
|
||||
|
||||
1:
|
||||
lddpc pc, .Lup_fullcontextrestore
|
||||
lddpc pc, .Lfullcontextrestoreptr
|
||||
|
||||
.Lup_doirq:
|
||||
.Ldoirqptr:
|
||||
.word up_doirq
|
||||
.Lup_fullcontextrestore:
|
||||
.Lfullcontextrestoreptr:
|
||||
.word up_fullcontextrestore
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
.Linstackbaseptr:
|
||||
.word .Lintstackbase
|
||||
#endif
|
||||
.size vectortab, .-vectortab
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_interruptstack
|
||||
************************************************************************************/
|
||||
@@ -314,11 +366,8 @@ avr32_common:
|
||||
.type up_interruptstack, object
|
||||
up_interruptstack:
|
||||
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~3)
|
||||
up_intstackbase:
|
||||
.Lintstackbase:
|
||||
.size up_interruptstack, .-up_interruptstack
|
||||
.Lup_instackbase
|
||||
.word up_intstackbase
|
||||
.size .Lup_instackbase, .-.Lup_instackbase
|
||||
#endif
|
||||
.end
|
||||
|
||||
|
||||
Reference in New Issue
Block a user