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page tables must be aligned

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2900 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2010-08-31 03:51:19 +00:00
parent cd4dd3b038
commit c739018316
5 changed files with 92 additions and 75 deletions
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arch/arm/src/arm/pg_macros.h
+10
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@@ -69,6 +69,11 @@
#if CONFIG_PAGING_PAGESIZE == 1024 #if CONFIG_PAGING_PAGESIZE == 1024
/* Base of the L2 page table (aligned to 4Kb byte boundaries) */
# define PGTABLE_L2_BASE_PADDR PGTABLE_L2_FINE_PBASE
# define PGTABLE_L2_BASE_VADDR PGTABLE_L2_FINE_VBASE
/* Number of pages in an L2 table per L1 entry */ /* Number of pages in an L2 table per L1 entry */
# define PTE_NPAGES PTE_TINY_NPAGES # define PTE_NPAGES PTE_TINY_NPAGES
@@ -91,6 +96,11 @@
#elif CONFIG_PAGING_PAGESIZE == 4096 #elif CONFIG_PAGING_PAGESIZE == 4096
/* Base of the L2 page table (aligned to 1Kb byte boundaries) */
# define PGTABLE_L2_BASE_PADDR PGTABLE_L2_COARSE_PBASE
# define PGTABLE_L2_BASE_VADDR PGTABLE_L2_COARSE_VBASE
/* Number of pages in an L2 table per L1 entry */ /* Number of pages in an L2 table per L1 entry */
# define PTE_NPAGES PTE_SMALL_NPAGES # define PTE_NPAGES PTE_SMALL_NPAGES
arch/arm/src/dm320/dm320_boot.c
+2 -2
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@@ -173,7 +173,7 @@ static void up_vectormapping(void)
while (vector_paddr < end_paddr) while (vector_paddr < end_paddr)
{ {
up_setlevel2coarseentry(PGTABLE_L2_BASE_VADDR, vector_paddr, vector_vaddr, up_setlevel2coarseentry(PGTABLE_L2_COARSE_VBASE, vector_paddr, vector_vaddr,
MMU_L2_VECTORFLAGS); MMU_L2_VECTORFLAGS);
vector_paddr += 4096; vector_paddr += 4096;
vector_vaddr += 4096; vector_vaddr += 4096;
@@ -181,7 +181,7 @@ static void up_vectormapping(void)
/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */ /* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
up_setlevel1entry(PGTABLE_L2_BASE_PADDR, DM320_VECTOR_VCOARSE, MMU_L1_VECTORFLAGS); up_setlevel1entry(PGTABLE_L2_COARSE_PBASE, DM320_VECTOR_VCOARSE, MMU_L1_VECTORFLAGS);
} }
/************************************************************************************ /************************************************************************************
arch/arm/src/dm320/dm320_memorymap.h
+4 -2
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@@ -197,12 +197,14 @@
#define PGTABLE_BASE_PADDR DM320_SDRAM_PADDR #define PGTABLE_BASE_PADDR DM320_SDRAM_PADDR
#define PGTABLE_SDRAM_PADDR PGTABLE_BASE_PADDR #define PGTABLE_SDRAM_PADDR PGTABLE_BASE_PADDR
#define PGTABLE_L2_BASE_PADDR (PGTABLE_BASE_PADDR+0x00000800) #define PGTABLE_L2_COARSE_PBASE (PGTABLE_BASE_PADDR+0x00000800)
#define PGTABLE_L2_FINE_PBASE (PGTABLE_BASE_PADDR+0x00001000)
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE) #define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
#define PGTABLE_BASE_VADDR DM320_SDRAM_VADDR #define PGTABLE_BASE_VADDR DM320_SDRAM_VADDR
#define PGTABLE_SDRAM_VADDR PGTABLE_BASE_VADDR #define PGTABLE_SDRAM_VADDR PGTABLE_BASE_VADDR
#define PGTABLE_L2_BASE_VADDR (PGTABLE_BASE_VADDR+0x00000800) #define PGTABLE_L2_COARSE_VBASE (PGTABLE_BASE_VADDR+0x00000800)
#define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+0x00001000)
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE) #define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR) #define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR)
arch/arm/src/lpc313x/lpc313x_boot.c
+2 -2
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@@ -275,7 +275,7 @@ static void up_vectormapping(void)
while (vector_paddr < end_paddr) while (vector_paddr < end_paddr)
{ {
up_setlevel2coarseentry(PGTABLE_L2_BASE_VADDR, vector_paddr, up_setlevel2coarseentry(PGTABLE_L2_COARSE_VBASE, vector_paddr,
vector_vaddr, MMU_L2_VECTORFLAGS); vector_vaddr, MMU_L2_VECTORFLAGS);
vector_paddr += 4096; vector_paddr += 4096;
vector_vaddr += 4096; vector_vaddr += 4096;
@@ -283,7 +283,7 @@ static void up_vectormapping(void)
/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */ /* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
up_setlevel1entry(PGTABLE_L2_BASE_PADDR, LPC313X_VECTOR_VCOARSE, up_setlevel1entry(PGTABLE_L2_COARSE_PBASE, LPC313X_VECTOR_VCOARSE,
MMU_L1_VECTORFLAGS); MMU_L1_VECTORFLAGS);
} }
#endif #endif
arch/arm/src/lpc313x/lpc313x_memorymap.h
+8 -3
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@@ -321,10 +321,15 @@
* normal operation). We will reuse this memory for coarse page tables as follows: * normal operation). We will reuse this memory for coarse page tables as follows:
*/ */
#define PGTABLE_L2_OFFSET ((LPC313X_LAST_PSECTION >> 20) << 2) #define PGTABLE_L2_COARSE_OFFSET ((((LPC313X_LAST_PSECTION >> 20) + 255) & ~255) << 2)
#define PGTABLE_L2_BASE_PADDR (PGTABLE_BASE_PADDR+PGTABLE_L2_OFFSET) #define PGTABLE_L2_COARSE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_COARSE_OFFSET)
#define PGTABLE_L2_COARSE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_COARSE_OFFSET)
#define PGTABLE_L2_FINE_OFFSET ((((LPC313X_LAST_PSECTION >> 20) + 1023) & ~1023) << 2)
#define PGTABLE_L2_FINE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_FINE_OFFSET)
#define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_FINE_OFFSET)
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE) #define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
#define PGTABLE_L2_BASE_VADDR (PGTABLE_BASE_VADDR+PGTABLE_L2_OFFSET)
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE) #define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR) #define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR)