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stm32h5/adc: fix TROVS bit and watchdog threshold register writes
Fix adc_oversample() where priv->trovs (a bool, 0 or 1) was OR'd directly into setbits instead of using ADC_CFGR2_TROVS (bit 9). This caused triggered oversampling to never actually be enabled. Fix ANIOC_WDOG_UPPER and ANIOC_WDOG_LOWER ioctls where the TR1 register was overwritten with only the new threshold value, zeroing out the opposite threshold and the AWDFILT digital filter bits. Use read-modify-write to preserve the other fields. Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
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@@ -1069,7 +1069,10 @@ static void adc_oversample(struct adc_dev_s *dev)
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(priv->ovsr << ADC_CFGR2_OVSR_SHIFT) |
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(priv->ovsr << ADC_CFGR2_OVSR_SHIFT) |
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(priv->ovss << ADC_CFGR2_OVSS_SHIFT);
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(priv->ovss << ADC_CFGR2_OVSS_SHIFT);
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setbits |= priv->trovs;
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if (priv->trovs)
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{
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setbits |= ADC_CFGR2_TROVS;
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}
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adc_modifyreg(priv, STM32_ADC_CFGR2_OFFSET, clrbits, setbits);
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adc_modifyreg(priv, STM32_ADC_CFGR2_OFFSET, clrbits, setbits);
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}
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}
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@@ -1811,7 +1814,8 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
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/* Set the watchdog threshold register */
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/* Set the watchdog threshold register */
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regval = ((arg << ADC_TR1_HT1_SHIFT) & ADC_TR1_HT1_MASK);
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regval &= ~ADC_TR1_HT1_MASK;
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regval |= ((arg << ADC_TR1_HT1_SHIFT) & ADC_TR1_HT1_MASK);
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adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval);
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adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval);
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/* Ensure analog watchdog is enabled */
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/* Ensure analog watchdog is enabled */
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@@ -1845,7 +1849,8 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
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/* Set the watchdog threshold register */
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/* Set the watchdog threshold register */
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regval = ((arg << ADC_TR1_LT1_SHIFT) & ADC_TR1_LT1_MASK);
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regval &= ~ADC_TR1_LT1_MASK;
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regval |= ((arg << ADC_TR1_LT1_SHIFT) & ADC_TR1_LT1_MASK);
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adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval);
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adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval);
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/* Ensure analog watchdog is enabled */
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/* Ensure analog watchdog is enabled */
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