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New LIS331DL driver and VSN updates from Uros

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3457 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-04-03 14:26:05 +00:00
parent 434a24d88f
commit c6eb9d6c3f
6 changed files with 332 additions and 120 deletions
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arch/arm/src/lpc313x/lpc313x_i2c.c
+1 -1
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@@ -50,7 +50,7 @@
#include <debug.h> #include <debug.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <nuttx/i2c.h> #include <nuttx/i2c/i2c.h>
#include <arch/irq.h> #include <arch/irq.h>
#include <arch/board/board.h> #include <arch/board/board.h>
arch/arm/src/stm32/chip/stm32_i2c.h
+5 -1
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@@ -102,7 +102,7 @@
#define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */ #define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */
#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT) #define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT)
#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */ #define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */
#define I2C_CR2_ITEVTEN (1 << 9) /* Bit 9: Event Interrupt Enable */ #define I2C_CR2_ITEVFEN (1 << 9) /* Bit 9: Event Interrupt Enable */
#define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */ #define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */
#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */ #define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */
#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */ #define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */
@@ -135,6 +135,7 @@
#define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */ #define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */
#define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */ #define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */
#define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */ #define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */
/* Bit 5: Reserved */
#define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */ #define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */
#define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */ #define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */
#define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */ #define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */
@@ -142,9 +143,12 @@
#define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */ #define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */
#define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */ #define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */
#define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */ #define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */
/* Bit 13: Reserved */
#define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */ #define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */
#define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */ #define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */
#define I2C_SR1_ERRORMASK (I2C_SR1_BERR|I2C_SR1_ARLO|I2C_SR1_AF|I2C_SR1_OVR|I2C_SR1_PECERR)
/* Status register 2 */ /* Status register 2 */
#define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */ #define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */
arch/arm/src/stm32/stm32_i2c.c
+321 -113
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arch/arm/src/stm32/stm32_i2c.h
+1 -1
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@@ -41,7 +41,7 @@
************************************************************************************/ ************************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/i2c.h> #include <nuttx/i2c/i2c.h>
#include "chip.h" #include "chip.h"
#include "chip/stm32_i2c.h" #include "chip/stm32_i2c.h"
arch/z80/src/ez80/ez80_i2c.c
+2 -2
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@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/z80/src/ez80/ez80_i2c.c * arch/z80/src/ez80/ez80_i2c.c
* *
* Copyright(C) 2009 Gregory Nutt. All rights reserved. * Copyright(C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -47,7 +47,7 @@
#include <assert.h> #include <assert.h>
#include <debug.h> #include <debug.h>
#include <nuttx/i2c.h> #include <nuttx/i2c/i2c.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/board/board.h> #include <arch/board/board.h>
arch/z80/src/z8/z8_i2c.c
+2 -2
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@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/z80/src/z8/z8_i2c.c * arch/z80/src/z8/z8_i2c.c
* *
* Copyright(C) 2009 Gregory Nutt. All rights reserved. * Copyright(C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -47,7 +47,7 @@
#include <assert.h> #include <assert.h>
#include <debug.h> #include <debug.h>
#include <nuttx/i2c.h> #include <nuttx/i2c/i2c.h>
#include <arch/board/board.h> #include <arch/board/board.h>
#include <eZ8.h> /* eZ8 Register definitions */ #include <eZ8.h> /* eZ8 Register definitions */