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esp32s3/wireless: Fix typo

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The CPU 2 interrupt source (which is not used for anything else) is
used to off-load BLE data after a SPI flash operation.
This commit is contained in:
Tiago Medicci Serrano
2023-10-09 17:13:13 -03:00
committed by Xiang Xiao
parent fae075a749
commit c60d5c2ea1
1 changed files with 1 additions and 1 deletions
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arch/xtensa/src/esp32s3/esp32s3_wireless.c
+1 -1
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@@ -741,7 +741,7 @@ IRAM_ATTR void esp_post_semcache(struct esp_semcache_s *sc)
sc->count++; sc->count++;
/* Enable CPU 0 interrupt. This will generate an IRQ as soon as non-IRAM /* Enable CPU 2 interrupt. This will generate an IRQ as soon as non-IRAM
* are (re)enabled. * are (re)enabled.
*/ */