arch/arm/src/imxrt/imxrt_clockconfig.c: If SDRAM is actived it was only running at 40MHz. This was becaus imxrt_clockconfig.c changed the SEMC clock divider after the DCD was configured. This commit corrects that.

arch/arm/src/imxrt/Kconfig

@@ -121,6 +121,10 @@ config IMXRT_HAVE_LCD
 	bool
 	default n
 
+config IMXRT_SEMC_INIT_DONE
+	bool
+	default n
+
 menu "i.MX RT Peripheral Selection"
 
 config IMXRT_EDMA

arch/arm/src/imxrt/imxrt_clockconfig.c

@@ -324,10 +324,14 @@ void imxrt_clockconfig(void)
   reg |= CCM_CSCMR1_PERCLK_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_PERCLK_PODF_DIVIDER));
   putreg32(reg, IMXRT_CCM_CSCMR1);
 
+#ifndef CONFIG_IMXRT_SEMC_INIT_DONE
+  /* Configure SEMC Clock only if not already done by DCD SDRAM init. */
+
   reg  = getreg32(IMXRT_CCM_CBCDR);
   reg &= ~CCM_CBCDR_SEMC_PODF_MASK;
   reg |= CCM_CBCDR_SEMC_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_SEMC_PODF_DIVIDER));
   putreg32(reg, IMXRT_CCM_CBCDR);
+#endif
 
   /* Set PRE_PERIPH_CLK to Board Selection */
 

configs/imxrt1050-evk/Kconfig

@@ -20,6 +20,7 @@ endchoice # Boot Flash
 config IMXRT1050_EVK_SDRAM
 	bool "Enable SDRAM"
 	default n
+	select IMXRT_SEMC_INIT_DONE
 	---help---
 		Activate DCD configuration of SDRAM