diff --git a/arch/arm/src/lpc54xx/chip/lpc54_i2c.h b/arch/arm/src/lpc54xx/chip/lpc54_i2c.h index 1513845dfa8..78fc75da6cb 100644 --- a/arch/arm/src/lpc54xx/chip/lpc54_i2c.h +++ b/arch/arm/src/lpc54xx/chip/lpc54_i2c.h @@ -51,260 +51,342 @@ /* Shared I2C registers */ -#define LPC54_I2C_CFG_OFFSET 0x0800 /* Configuration for shared functions */ -#define LPC54_I2C_STAT_OFFSET 0x0804 /* Status register for shared functions */ -#define LPC54_I2C_INTENSET_OFFSET 0x0808 /* Interrupt enable set and read */ -#define LPC54_I2C_INTENCLR_OFFSET 0x080c /* Interrupt enable clear */ -#define LPC54_I2C_TIMEOUT_OFFSET 0x0810 /* Time-out value */ -#define LPC54_I2C_CLKDIV_OFFSET 0x0814 /* Clock pre-divider for the entire I2C interface */ -#define LPC54_I2C_INTSTAT_OFFSET 0x0818 /* Interrupt status register for shared functions */ +#define LPC54_I2C_CFG_OFFSET 0x0800 /* Configuration for shared functions */ +#define LPC54_I2C_STAT_OFFSET 0x0804 /* Status register for shared functions */ +#define LPC54_I2C_INTENSET_OFFSET 0x0808 /* Interrupt enable set and read */ +#define LPC54_I2C_INTENCLR_OFFSET 0x080c /* Interrupt enable clear */ +#define LPC54_I2C_TIMEOUT_OFFSET 0x0810 /* Time-out value */ +#define LPC54_I2C_CLKDIV_OFFSET 0x0814 /* Clock pre-divider for the entire I2C interface */ +#define LPC54_I2C_INTSTAT_OFFSET 0x0818 /* Interrupt status register for shared functions */ /* Master function registers */ -#define LPC54_I2C_MSTCTL_OFFSET 0x0820 /* Master control */ -#define LPC54_I2C_MSTTIME_OFFSET 0x0824 /* Master timing configuration */ -#define LPC54_I2C_MSTDAT_OFFSET 0x0828 /* Combined Master receiver and transmitter data */ +#define LPC54_I2C_MSTCTL_OFFSET 0x0820 /* Master control */ +#define LPC54_I2C_MSTTIME_OFFSET 0x0824 /* Master timing configuration */ +#define LPC54_I2C_MSTDAT_OFFSET 0x0828 /* Combined Master receiver and transmitter data */ /* Slave function registers */ -#define LPC54_I2C_SLVCTL_OFFSET 0x0840 /* Slave control */ -#define LPC54_I2C_SLVDAT_OFFSET 0x0844 /* Combined Slave receiver and transmitter data */ -#define LPC54_I2C_SLVADR0_OFFSET 0x0848 /* Slave address 0 */ -#define LPC54_I2C_SLVADR1_OFFSET 0x084c /* Slave address 1 */ -#define LPC54_I2C_SLVADR2_OFFSET 0x0850 /* Slave address 2 */ -#define LPC54_I2C_SLVADR3_OFFSET 0x0854 /* Slave address 3 */ -#define LPC54_I2C_SLVQUAL0_OFFSET 0x0858 /* Slave qualification for address 0 */ +#define LPC54_I2C_SLVCTL_OFFSET 0x0840 /* Slave control */ +#define LPC54_I2C_SLVDAT_OFFSET 0x0844 /* Combined Slave receiver and transmitter data */ +#define LPC54_I2C_SLVADR0_OFFSET 0x0848 /* Slave address 0 */ +#define LPC54_I2C_SLVADR1_OFFSET 0x084c /* Slave address 1 */ +#define LPC54_I2C_SLVADR2_OFFSET 0x0850 /* Slave address 2 */ +#define LPC54_I2C_SLVADR3_OFFSET 0x0854 /* Slave address 3 */ +#define LPC54_I2C_SLVQUAL0_OFFSET 0x0858 /* Slave qualification for address 0 */ /* Monitor function registers */ -#define LPC54_I2C_MONRXDAT_OFFSET 0x0880 /* Monitor receiver data */ +#define LPC54_I2C_MONRXDAT_OFFSET 0x0880 /* Monitor receiver data */ /* ID register */ -#define LPC54_I2C_ID_OFFSET 0x0ffc /* I2C module Identification */ +#define LPC54_I2C_ID_OFFSET 0x0ffc /* I2C module Identification */ /* Register addresses *******************************************************************************/ -#define LPC54_I2C0_CFG (LPC54_FLEXCOMM0_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C0_STAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C0_INTENSET (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C0_INTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C0_TIMEOUT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C0_CLKDIV (LPC54_FLEXCOMM0_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C0_INTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C0_MSTCTL (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C0_MSTTIME (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C0_MSTDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C0_SLVCTL (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C0_SLVDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C0_SLVADR0 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C0_SLVADR1 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C0_SLVADR2 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C0_SLVADR3 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C0_SLVQUAL0 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C0_MONRXDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C0_ID (LPC54_FLEXCOMM0_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C0_CFG (LPC54_FLEXCOMM0_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C0_STAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C0_INTENSET (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C0_INTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C0_TIMEOUT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C0_CLKDIV (LPC54_FLEXCOMM0_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C0_INTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C0_MSTCTL (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C0_MSTTIME (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C0_MSTDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C0_SLVCTL (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C0_SLVDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C0_SLVADR0 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C0_SLVADR1 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C0_SLVADR2 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C0_SLVADR3 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C0_SLVQUAL0 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C0_MONRXDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C0_ID (LPC54_FLEXCOMM0_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C1_CFG (LPC54_FLEXCOMM1_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C1_STAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C1_INTENSET (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C1_INTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C1_TIMEOUT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C1_CLKDIV (LPC54_FLEXCOMM1_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C1_INTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C1_MSTCTL (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C1_MSTTIME (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C1_MSTDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C1_SLVCTL (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C1_SLVDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C1_SLVADR0 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C1_SLVADR1 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C1_SLVADR2 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C1_SLVADR3 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C1_SLVQUAL0 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C1_MONRXDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C1_ID (LPC54_FLEXCOMM1_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C1_CFG (LPC54_FLEXCOMM1_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C1_STAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C1_INTENSET (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C1_INTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C1_TIMEOUT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C1_CLKDIV (LPC54_FLEXCOMM1_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C1_INTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C1_MSTCTL (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C1_MSTTIME (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C1_MSTDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C1_SLVCTL (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C1_SLVDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C1_SLVADR0 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C1_SLVADR1 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C1_SLVADR2 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C1_SLVADR3 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C1_SLVQUAL0 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C1_MONRXDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C1_ID (LPC54_FLEXCOMM1_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C2_CFG (LPC54_FLEXCOMM2_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C2_STAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C2_INTENSET (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C2_INTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C2_TIMEOUT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C2_CLKDIV (LPC54_FLEXCOMM2_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C2_INTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C2_MSTCTL (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C2_MSTTIME (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C2_MSTDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C2_SLVCTL (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C2_SLVDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C2_SLVADR0 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C2_SLVADR1 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C2_SLVADR2 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C2_SLVADR3 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C2_SLVQUAL0 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C2_MONRXDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C2_ID (LPC54_FLEXCOMM2_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C2_CFG (LPC54_FLEXCOMM2_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C2_STAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C2_INTENSET (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C2_INTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C2_TIMEOUT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C2_CLKDIV (LPC54_FLEXCOMM2_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C2_INTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C2_MSTCTL (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C2_MSTTIME (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C2_MSTDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C2_SLVCTL (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C2_SLVDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C2_SLVADR0 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C2_SLVADR1 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C2_SLVADR2 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C2_SLVADR3 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C2_SLVQUAL0 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C2_MONRXDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C2_ID (LPC54_FLEXCOMM2_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C3_CFG (LPC54_FLEXCOMM3_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C3_STAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C3_INTENSET (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C3_INTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C3_TIMEOUT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C3_CLKDIV (LPC54_FLEXCOMM3_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C3_INTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C3_MSTCTL (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C3_MSTTIME (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C3_MSTDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C3_SLVCTL (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C3_SLVDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C3_SLVADR0 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C3_SLVADR1 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C3_SLVADR2 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C3_SLVADR3 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C3_SLVQUAL0 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C3_MONRXDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C3_ID (LPC54_FLEXCOMM3_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C3_CFG (LPC54_FLEXCOMM3_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C3_STAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C3_INTENSET (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C3_INTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C3_TIMEOUT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C3_CLKDIV (LPC54_FLEXCOMM3_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C3_INTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C3_MSTCTL (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C3_MSTTIME (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C3_MSTDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C3_SLVCTL (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C3_SLVDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C3_SLVADR0 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C3_SLVADR1 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C3_SLVADR2 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C3_SLVADR3 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C3_SLVQUAL0 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C3_MONRXDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C3_ID (LPC54_FLEXCOMM3_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C4_CFG (LPC54_FLEXCOMM4_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C4_STAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C4_INTENSET (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C4_INTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C4_TIMEOUT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C4_CLKDIV (LPC54_FLEXCOMM4_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C4_INTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C4_MSTCTL (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C4_MSTTIME (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C4_MSTDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C4_SLVCTL (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C4_SLVDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C4_SLVADR0 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C4_SLVADR1 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C4_SLVADR2 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C4_SLVADR3 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C4_SLVQUAL0 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C4_MONRXDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C4_ID (LPC54_FLEXCOMM4_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C4_CFG (LPC54_FLEXCOMM4_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C4_STAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C4_INTENSET (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C4_INTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C4_TIMEOUT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C4_CLKDIV (LPC54_FLEXCOMM4_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C4_INTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C4_MSTCTL (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C4_MSTTIME (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C4_MSTDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C4_SLVCTL (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C4_SLVDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C4_SLVADR0 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C4_SLVADR1 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C4_SLVADR2 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C4_SLVADR3 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C4_SLVQUAL0 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C4_MONRXDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C4_ID (LPC54_FLEXCOMM4_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C5_CFG (LPC54_FLEXCOMM5_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C5_STAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C5_INTENSET (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C5_INTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C5_TIMEOUT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C5_CLKDIV (LPC54_FLEXCOMM5_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C5_INTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C5_MSTCTL (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C5_MSTTIME (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C5_MSTDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C5_SLVCTL (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C5_SLVDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C5_SLVADR0 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C5_SLVADR1 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C5_SLVADR2 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C5_SLVADR3 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C5_SLVQUAL0 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C5_MONRXDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C5_ID (LPC54_FLEXCOMM5_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C5_CFG (LPC54_FLEXCOMM5_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C5_STAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C5_INTENSET (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C5_INTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C5_TIMEOUT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C5_CLKDIV (LPC54_FLEXCOMM5_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C5_INTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C5_MSTCTL (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C5_MSTTIME (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C5_MSTDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C5_SLVCTL (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C5_SLVDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C5_SLVADR0 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C5_SLVADR1 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C5_SLVADR2 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C5_SLVADR3 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C5_SLVQUAL0 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C5_MONRXDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C5_ID (LPC54_FLEXCOMM5_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C6_CFG (LPC54_FLEXCOMM6_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C6_STAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C6_INTENSET (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C6_INTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C6_TIMEOUT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C6_CLKDIV (LPC54_FLEXCOMM6_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C6_INTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C6_MSTCTL (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C6_MSTTIME (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C6_MSTDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C6_SLVCTL (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C6_SLVDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C6_SLVADR0 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C6_SLVADR1 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C6_SLVADR2 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C6_SLVADR3 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C6_SLVQUAL0 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C6_MONRXDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C6_ID (LPC54_FLEXCOMM6_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C6_CFG (LPC54_FLEXCOMM6_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C6_STAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C6_INTENSET (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C6_INTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C6_TIMEOUT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C6_CLKDIV (LPC54_FLEXCOMM6_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C6_INTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C6_MSTCTL (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C6_MSTTIME (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C6_MSTDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C6_SLVCTL (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C6_SLVDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C6_SLVADR0 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C6_SLVADR1 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C6_SLVADR2 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C6_SLVADR3 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C6_SLVQUAL0 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C6_MONRXDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C6_ID (LPC54_FLEXCOMM6_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C7_CFG (LPC54_FLEXCOMM7_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C7_STAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C7_INTENSET (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C7_INTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C7_TIMEOUT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C7_CLKDIV (LPC54_FLEXCOMM7_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C7_INTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C7_MSTCTL (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C7_MSTTIME (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C7_MSTDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C7_SLVCTL (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C7_SLVDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C7_SLVADR0 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C7_SLVADR1 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C7_SLVADR2 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C7_SLVADR3 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C7_SLVQUAL0 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C7_MONRXDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C7_ID (LPC54_FLEXCOMM7_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C7_CFG (LPC54_FLEXCOMM7_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C7_STAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C7_INTENSET (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C7_INTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C7_TIMEOUT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C7_CLKDIV (LPC54_FLEXCOMM7_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C7_INTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C7_MSTCTL (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C7_MSTTIME (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C7_MSTDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C7_SLVCTL (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C7_SLVDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C7_SLVADR0 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C7_SLVADR1 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C7_SLVADR2 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C7_SLVADR3 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C7_SLVQUAL0 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C7_MONRXDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C7_ID (LPC54_FLEXCOMM7_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C8_CFG (LPC54_FLEXCOMM8_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C8_STAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C8_INTENSET (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C8_INTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C8_TIMEOUT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C8_CLKDIV (LPC54_FLEXCOMM8_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C8_INTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C8_MSTCTL (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C8_MSTTIME (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C8_MSTDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C8_SLVCTL (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C8_SLVDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C8_SLVADR0 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C8_SLVADR1 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C8_SLVADR2 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C8_SLVADR3 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C8_SLVQUAL0 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C8_MONRXDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C8_ID (LPC54_FLEXCOMM8_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C8_CFG (LPC54_FLEXCOMM8_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C8_STAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C8_INTENSET (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C8_INTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C8_TIMEOUT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C8_CLKDIV (LPC54_FLEXCOMM8_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C8_INTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C8_MSTCTL (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C8_MSTTIME (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C8_MSTDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C8_SLVCTL (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C8_SLVDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C8_SLVADR0 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C8_SLVADR1 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C8_SLVADR2 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C8_SLVADR3 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C8_SLVQUAL0 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C8_MONRXDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C8_ID (LPC54_FLEXCOMM8_BASE + LPC54_I2C_ID_OFFSET -#define LPC54_I2C9_CFG (LPC54_FLEXCOMM9_BASE + LPC54_I2C_CFG_OFFSET) -#define LPC54_I2C9_STAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_STAT_OFFSET) -#define LPC54_I2C9_INTENSET (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTENSET_OFFSET) -#define LPC54_I2C9_INTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTENCLR_OFFSET) -#define LPC54_I2C9_TIMEOUT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_TIMEOUT_OFFSET) -#define LPC54_I2C9_CLKDIV (LPC54_FLEXCOMM9_BASE + LPC54_I2C_CLKDIV_OFFSET) -#define LPC54_I2C9_INTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTSTAT_OFFSET) -#define LPC54_I2C9_MSTCTL (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTCTL_OFFSET) -#define LPC54_I2C9_MSTTIME (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTTIME_OFFSET) -#define LPC54_I2C9_MSTDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTDAT_OFFSET) -#define LPC54_I2C9_SLVCTL (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVCTL_OFFSET) -#define LPC54_I2C9_SLVDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVDAT_OFFSET) -#define LPC54_I2C9_SLVADR0 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR0_OFFSET) -#define LPC54_I2C9_SLVADR1 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR1_OFFSET) -#define LPC54_I2C9_SLVADR2 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR2_OFFSET) -#define LPC54_I2C9_SLVADR3 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR3_OFFSET) -#define LPC54_I2C9_SLVQUAL0 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVQUAL0_OFFSET) -#define LPC54_I2C9_MONRXDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MONRXDAT_OFFSET) -#define LPC54_I2C9_ID (LPC54_FLEXCOMM9_BASE + LPC54_I2C_ID_OFFSET +#define LPC54_I2C9_CFG (LPC54_FLEXCOMM9_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C9_STAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C9_INTENSET (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C9_INTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C9_TIMEOUT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C9_CLKDIV (LPC54_FLEXCOMM9_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C9_INTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C9_MSTCTL (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C9_MSTTIME (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C9_MSTDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C9_SLVCTL (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C9_SLVDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C9_SLVADR0 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C9_SLVADR1 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C9_SLVADR2 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C9_SLVADR3 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C9_SLVQUAL0 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C9_MONRXDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C9_ID (LPC54_FLEXCOMM9_BASE + LPC54_I2C_ID_OFFSET /* Register bit definitions *************************************************************************/ /* Configuration for shared functions */ -#define I2C_CFG_ -/* Status register for shared functions */ -#define I2C_STAT_ -/* Interrupt enable set and read */ -#define I2C_INTENSET_ -/* Interrupt enable clear */ -#define I2C_INTENCLR_ + +#define I2C_CFG_MSTEN (1 << 0) /* Bit 0: Master enable */ +#define I2C_CFG_SLVEN (1 << 1) /* Bit 1: Slave enable */ +#define I2C_CFG_MONEN (1 << 2) /* Bit 2: Monitor enable */ +#define I2C_CFG_TIMEOUTEN (1 << 3) /* Bit 3: I2C bus time-out enable */ +#define I2C_CFG_MONCLKSTR (1 << 4) /* Bit 4: Monitor function clock stretching */ +#define I2C_CFG_HSCAPABLE (1 << 5) /* Bit 5: High-speed mode capable enable */ + +#define I2C_CFG_ALLENABLES 0x1f + +/* Status, set and write, and clear register for shared functions */ +/* Master function state codes (MSTSTATE) */ + +#define I2C_MASTER_STATE_IDLE (0) /* Idle */ +#define I2C_MASTER_STATE_RXAVAIL (1) /* Received data is available (Master Receiver mode) */ +#define I2C_MASTER_STATE_TXOK (2) /* Data can be transmitted (Master Transmitter mode) */ +#define I2C_MASTER_STATE_ADDRNAK (3) /* Slave NACKed address */ +#define I2C_MASTER_STATE_DATANAK (4) /* Slave NACKed transmitted data */ + +/* Slave function state codes (SLVSTATE) */ + +#define I2C_SLAVE_STATE_ADDR (0) /* Address plus R/W received */ +#define I2C_SLAVE_STATE_RXAVAIL (1) /* Received data is available (Slave Receiver mode) */ +#define I2C_SLAVE_STATE_TXOK (2) /* Data can be transmitted (Slave Transmitter mode) */ + +#define I2C_INT_MSTPENDING (1 << 0) /* Bit 0 Master Pending interrupt */ +#define I2C_STAT_MSTSTATE_SHIFT (1) /* Bits 1-3: Master State code (status only) */ +#define I2C_STAT_MSTSTATE_MASK (7 << I2C_STAT_MSTSTATE_SHIFT) +# define I2C_STAT_MSTSTATE_IDLE (0 << I2C_STAT_MSTSTATE_SHIFT) /* Idle */ +# define I2C_STAT_MSTSTATE_RXAVAIL (1 << I2C_STAT_MSTSTATE_SHIFT) /* Receive ready */ +# define I2C_STAT_MSTSTATE_TXOK (2 << I2C_STAT_MSTSTATE_SHIFT) /* Transmit ready */ +# define I2C_STAT_MSTSTATE_ADDRNAK (3 << I2C_STAT_MSTSTATE_SHIFT) /* NACK Address */ +# define I2C_STAT_MSTSTATE_DATANAK (4 << I2C_STAT_MSTSTATE_SHIFT) /* NACK Data */ +#define I2C_INT_MSTARBLOSS (1 << 4) /* Bit 4: Master Arbitration Loss interrupt */ +#define I2C_INT_MSTSTSTPERR (1 << 6) /* Bit 6: Master Start/Stop Error interrupt */ +#define I2C_INT_SLVPENDING (1 << 8) /* Bit 8: Slave Pending interrupt */ +#define I2C_STAT_SLVSTATE_SHIFT (9) /* Bits 9-10: Slave State code (status only) */ +#define I2C_STAT_SLVSTATE_MASK (3 << I2C_STAT_SLVSTATE_SHIFT) +# define I2C_STAT_SLVSTATE_ADDR (0 << I2C_STAT_SLVSTATE_SHIFT) /* Slave address */ +# define I2C_STAT_SLVSTATE_RXAVAIL (1 << I2C_STAT_SLVSTATE_SHIFT) /* Slave receive */ +# define I2C_STAT_SLVSTATE_TXOK (2 << I2C_STAT_SLVSTATE_SHIFT) /* Slave transmit */ +#define I2C_INT_SLVNOTSTR (1 << 11) /* Bit 11: Slave Not Stretching interrupt */ +#define I2C_STAT_SLVIDX_SHIFT (12) /* Bits 12-13: Slave address match Index (status only) */ +#define I2C_STAT_SLVIDX_MASK (3 << I2C_STAT_SLVIDX_SHIFT) +# define I2C_STAT_SLVIDX_ADDR0 (0 << I2C_STAT_SLVIDX_SHIFT) /* Slave address 0 was matched */ +# define I2C_STAT_SLVIDX_ADDR1 (1 << I2C_STAT_SLVIDX_SHIFT) /* Slave address 1 was matched */ +# define I2C_STAT_SLVIDX_ADDR2 (2 << I2C_STAT_SLVIDX_SHIFT) /* Slave address 2 was matched */ +# define I2C_STAT_SLVIDX_ADDR3 (3 << I2C_STAT_SLVIDX_SHIFT) /* Slave address 3 was matched */ +#define I2C_STAT_SLVSEL (1 << 14) /* Bit 14: Slave selected flag (Slave only) */ +#define I2C_INT_SLVDESEL (1 << 15) /* Bit 15: Slave Deselect interrupt */ +#define I2C_INT_MONRDY (1 << 16) /* Bit 16: Monitor data Ready interrupt */ +#define I2C_INT_MONOV (1 << 17) /* Bit 17: Monitor Overrun interrupt */ +#define I2C_STAT_MONACTIVE (1 << 18) /* Bit 18: Monitor Active flag (status only) */ +#define I2C_INT_MONIDLE (1 << 19) /* Bit 19: Monitor Idle interrupt */ +#define I2C_INT_EVENTTIMEOUT (1 << 24) /* Bit 24: Event time-out interrupt */ +#define I2C_INT_SCLTIMEOUT (1 << 25) /* Bit 25: SCL time-out interrupt */ + +#define I2C_INT_MSTPENDING (1 << 0) /* Bit 0 Master Pending interrupt */ +#define I2C_INT_MSTARBLOSS (1 << 4) /* Bit 4: Master Arbitration Loss interrupt */ +#define I2C_INT_MSTSTSTPERR (1 << 6) /* Bit 6: Master Start/Stop Error interrupt */ +#define I2C_INT_SLVPENDING (1 << 8) /* Bit 8: Slave Pending interrupt */ +#define I2C_INT_SLVNOTSTR (1 << 11) /* Bit 11: Slave Not Stretching interrupt */ +#define I2C_INT_SLVDESEL (1 << 15) /* Bit 15: Slave Deselect interrupt */ +#define I2C_INT_MONRDY (1 << 16) /* Bit 16: Monitor data Ready interrupt */ +#define I2C_INT_MONOV (1 << 17) /* Bit 17: Monitor Overrun interrupt */ +#define I2C_INT_MONIDLE (1 << 19) /* Bit 19: Monitor Idle interrupt */ +#define I2C_INT_EVENTTIMEOUT (1 << 24) /* Bit 24: Event time-out interrupt */ +#define I2C_INT_SCLTIMEOUT (1 << 25) /* Bit 25: SCL time-out interrupt */ + +#define I2C_INT_ALL 0x030b8951 + /* Time-out value */ #define I2C_TIMEOUT_ + /* Clock pre-divider for the entire I2C interface */ -#define I2C_CLKDIV_ + +#define I2C_CLKDIV_SHIFT (0) /* Bits 0-15: I2C clock divider */ +#define I2C_CLKDIV_MASK (0xffff << I2C_CLKDIV_SHIFT) +# define I2C_CLKDIV(n) ((uint32_t)((n)-1) << I2C_CLKDIV_SHIFT) + /* Interrupt status register for shared functions */ #define I2C_INTSTAT_ + /* Master control */ -#define I2C_MSTCTL_ + +#define I2C_MSTCTL_MSTCONTINUE (1 << 0) /* Bit 0: Master Continue */ +#define I2C_MSTCTL_MSTSTART (1 << 1) /* Bit 1: Master Start control */ +#define I2C_MSTCTL_MSTSTOP (1 << 2) /* Bit 2: Master Stop control */ +#define I2C_MSTCTL_MSTDMA (1 << 3) /* Bit 3: Master DMA enable */ + /* Master timing configuration */ -#define I2C_MSTTIME_ + +#define I2C_MSTTIME_SCLLOW_SHIFT (0) /* Bits 0-2 Master SCL Low time */ +#define I2C_MSTTIME_SCLLOW_MASK (7 << I2C_MSTTIME_SCLLOW_SHIFT) +# define I2C_MSTTIME_SCLLOW(n) ((uint32_t)((n)-2) << I2C_MSTTIME_SCLLOW_SHIFT) +#define I2C_MSTTIME_SCLHIGH_SHIFT (4) /* Bits 4-6 Master SCL High time */ +#define I2C_MSTTIME_SCLHIGH_MASK (7 << I2C_MSTTIME_SCLHIGH_SHIFT) +# define I2C_MSTTIME_SCLHIGH(n) ((uint32_t)((n)-2) << I2C_MSTTIME_SCLHIGH_SHIFT) + /* Combined Master receiver and transmitter data */ #define I2C_MSTDAT_ /* Slave control */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_syscon.h b/arch/arm/src/lpc54xx/chip/lpc54_syscon.h index 3688364a332..5a21b2105ac 100644 --- a/arch/arm/src/lpc54xx/chip/lpc54_syscon.h +++ b/arch/arm/src/lpc54xx/chip/lpc54_syscon.h @@ -824,12 +824,11 @@ #define SYSCON_ASYNCPRESET_CTIMER3 (1 << 13) /* Bit 13: CTIMER3 reset control */ #define SYSCON_ASYNCPRESET_CTIMER4 (1 << 14) /* Bit 14: CTIMER4 reset control */ -/* Async peripheral clock control */ -#define SYSCON_ASYNCAPBCLKCTRL_ -/* Set bits in ASYNCAPBCLKCTRL */ -#define SYSCON_ASYNCAPBCLKCTRLSET_ -/* Clear bits in ASYNCAPBCLKCTRL */ -#define SYSCON_ASYNCAPBCLKCTRLCLR_ +/* Async peripheral clock control, set and clear registers */ + +#define SYSCON_ASYNCAPBCLKCTRL_CTIMER3 (1 << 13) /* Bit 13: CTIMER3 clock control */ +#define SYSCON_ASYNCAPBCLKCTRL_CTIMER4 (1 << 14) /* Bit 14: CTIMER4 clock control */ + /* Async APB clock source select A */ #define SYSCON_ASYNCAPBCLKSELA_ diff --git a/arch/arm/src/lpc54xx/lpc546x_enableclk.h b/arch/arm/src/lpc54xx/lpc546x_enableclk.h new file mode 100644 index 00000000000..f3833f86310 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc546x_enableclk.h @@ -0,0 +1,263 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc546x_enableclk.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC546X_ENABLECLK_H +#define __ARCH_ARM_SRC_LPC54XX_LPC546X_ENABLECLK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define lpc54_periph0_enableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLSET0) +#define lpc54_periph1_enableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLSET1) +#define lpc54_periph2_enableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLSET2) +#define lpc54_asynch_enableclk(b) putreg32((b), LPC54_SYSCON_ASYNCAPBCLKCTRLSET) + +#define lpc54_periph0_disableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLCLR0) +#define lpc54_periph1_disableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLCLR1) +#define lpc54_periph2_disableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLCLR2) +#define lpc54_asynch_disableclk(b) putreg32((b), LPC54_SYSCON_ASYNCAPBCLKCTRLCLR) + +#define lpc54_periph0_isenabled(b) ((getreg32(LPC54_SYSCON_AHBCLKCTRL0) & (b)) != 0) +#define lpc54_periph1_isenabled(b) ((getreg32(LPC54_SYSCON_AHBCLKCTRL1) & (b)) != 0) +#define lpc54_periph2_isenabled(b) ((getreg32(LPC54_SYSCON_AHBCLKCTRL2) & (b)) != 0) +#define lpc54_asynch_isenabled(b) ((getreg32(LPC54_SYSCON_ASYNCAPBCLKCTRL) & (b)) != 0) + +/* Enable peripheral clocking */ + +#define lpc54_rom_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_ROM) +#define lpc54_sram1_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_SRAM1) +#define lpc54_sram2_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_SRAM2) +#define lpc54_sram3_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_SRAM3) +#define lpc54_flash_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_FLASH) +#define lpc54_fmc_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_FMC) +#define lpc54_eeprom_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_EEPROM) +#define lpc54_spifi_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_SPIFI) +#define lpc54_inputmux_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_INPUTMUX) +#define lpc54_iocon_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_IOCON) +#define lpc54_gpio0_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GPIO0) +#define lpc54_gpio1_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GPIO1) +#define lpc54_gpio2_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GPIO2) +#define lpc54_gpio3_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GPIO3) +#define lpc54_pint_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_PINT) +#define lpc54_gint_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GINT) +#define lpc54_dma_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_DMA) +#define lpc54_crc_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_CRC) +#define lpc54_wwdt_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_WWDT) +#define lpc54_rtc_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_RTC) +#define lpc54_adc0_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_ADC0) + +#define lpc54_mrt_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_MRT) +#define lpc54_rit_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_RIT) +#define lpc54_sct0_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_SCT0) +#define lpc54_mcan0_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_MCAN0) +#define lpc54_mcan1_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_MCAN1) +#define lpc54_utick_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_UTICK) +#define lpc54_flexcomm0_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM0) +#define lpc54_flexcomm1_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM1) +#define lpc54_flexcomm2_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM2) +#define lpc54_flexcomm3_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM3) +#define lpc54_flexcomm4_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM4) +#define lpc54_flexcomm5_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM5) +#define lpc54_flexcomm6_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM6) +#define lpc54_flexcomm7_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM7) +#define lpc54_dmic_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_DMIC) +#define lpc54_ctimer2_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_CTIMER2) +#define lpc54_usb0d_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_USB0D) +#define lpc54_ctimer0_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_CTIMER0) +#define lpc54_ctimer1_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_CTIMER1) + +#define lpc54_lcd_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_LCD) +#define lpc54_sdio_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SDIO) +#define lpc54_usb1h_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1H) +#define lpc54_usb1d_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1D) +#define lpc54_usb1ram_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1RAM) +#define lpc54_emc_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_EMC) +#define lpc54_eth_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_ETH) +#define lpc54_gpio4_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_GPIO4) +#define lpc54_gpio5_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_GPIO5) +#define lpc54_otp_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_OTP) +#define lpc54_rng_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_RNG) +#define lpc54_flexcomm8_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_FLEXCOMM8) +#define lpc54_flexcomm9_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_FLEXCOMM9) +#define lpc54_usb0hmr_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB0HMR) +#define lpc54_usb0hsl_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB0HSL) +#define lpc54_sha_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SHA) +#define lpc54_sc0_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SC0) +#define lpc54_sc1_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SC1) + +#define lpc54_ctimer3_enableclk() lpc54_asynch_enableclk(SYSCON_ASYNCAPBCLKCTRL_CTIMER3) +#define lpc54_ctimer4_enableclk() lpc54_asynch_enableclk(SYSCON_ASYNCAPBCLKCTRL_CTIMER4) + +/* Disable peripheral clocking */ + +#define lpc54_rom_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_ROM) +#define lpc54_sram1_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_SRAM1) +#define lpc54_sram2_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_SRAM2) +#define lpc54_sram3_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_SRAM3) +#define lpc54_flash_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_FLASH) +#define lpc54_fmc_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_FMC) +#define lpc54_eeprom_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_EEPROM) +#define lpc54_spifi_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_SPIFI) +#define lpc54_inputmux_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_INPUTMUX) +#define lpc54_iocon_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_IOCON) +#define lpc54_gpio0_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GPIO0) +#define lpc54_gpio1_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GPIO1) +#define lpc54_gpio2_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GPIO2) +#define lpc54_gpio3_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GPIO3) +#define lpc54_pint_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_PINT) +#define lpc54_gint_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GINT) +#define lpc54_dma_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_DMA) +#define lpc54_crc_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_CRC) +#define lpc54_wwdt_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_WWDT) +#define lpc54_rtc_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_RTC) +#define lpc54_adc0_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_ADC0) + +#define lpc54_mrt_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_MRT) +#define lpc54_rit_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_RIT) +#define lpc54_sct0_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_SCT0) +#define lpc54_mcan0_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_MCAN0) +#define lpc54_mcan1_disableclk() lpc54_periph1_disableclkSYSCON_AHBCLKCTRL1_MCAN1) +#define lpc54_utick_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_UTICK) +#define lpc54_flexcomm0_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM0) +#define lpc54_flexcomm1_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM1) +#define lpc54_flexcomm2_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM2) +#define lpc54_flexcomm3_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM3) +#define lpc54_flexcomm4_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM4) +#define lpc54_flexcomm5_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM5) +#define lpc54_flexcomm6_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM6) +#define lpc54_flexcomm7_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM7) +#define lpc54_dmic_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_DMIC) +#define lpc54_ctimer2_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_CTIMER2) +#define lpc54_usb0d_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_USB0D) +#define lpc54_ctimer0_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_CTIMER0) +#define lpc54_ctimer1_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_CTIMER1) + +#define lpc54_lcd_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_LCD) +#define lpc54_sdio_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SDIO) +#define lpc54_usb1h_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1H) +#define lpc54_usb1d_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1D) +#define lpc54_usb1ram_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1RAM) +#define lpc54_emc_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_EMC) +#define lpc54_eth_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_ETH) +#define lpc54_gpio4_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_GPIO4) +#define lpc54_gpio5_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_GPIO5) +#define lpc54_otp_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_OTP) +#define lpc54_rng_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_RNG) +#define lpc54_flexcomm8_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_FLEXCOMM8) +#define lpc54_flexcomm9_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_FLEXCOMM9) +#define lpc54_usb0hmr_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB0HMR) +#define lpc54_usb0hsl_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB0HSL) +#define lpc54_sha_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SHA) +#define lpc54_sc0_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SC0) +#define lpc54_sc1_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SC1) + +#define lpc54_ctimer3_disableclk() lpc54_asynch_disableclk(SYSCON_ASYNCAPBCLKCTRL_CTIMER3) +#define lpc54_ctimer4_disableclk() lpc54_asynch_disableclk(SYSCON_ASYNCAPBCLKCTRL_CTIMER4) + +/* Check if peripheral clocking is enabled */ + +#define lpc54_rom_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_ROM) +#define lpc54_sram1_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_SRAM1) +#define lpc54_sram2_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_SRAM2) +#define lpc54_sram3_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_SRAM3) +#define lpc54_flash_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_FLASH) +#define lpc54_fmc_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_FMC) +#define lpc54_eeprom_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_EEPROM) +#define lpc54_spifi_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_SPIFI) +#define lpc54_inputmux_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_INPUTMUX) +#define lpc54_iocon_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_IOCON) +#define lpc54_gpio0_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GPIO0) +#define lpc54_gpio1_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GPIO1) +#define lpc54_gpio2_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GPIO2) +#define lpc54_gpio3_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GPIO3) +#define lpc54_pint_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_PINT) +#define lpc54_gint_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GINT) +#define lpc54_dma_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_DMA) +#define lpc54_crc_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_CRC) +#define lpc54_wwdt_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_WWDT) +#define lpc54_rtc_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_RTC) +#define lpc54_adc0_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_ADC0) + +#define lpc54_mrt_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_MRT) +#define lpc54_rit_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_RIT) +#define lpc54_sct0_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_SCT0) +#define lpc54_mcan0_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_MCAN0) +#define lpc54_mcan1_isenabled() lpc54_periph1_isenabledSYSCON_AHBCLKCTRL1_MCAN1) +#define lpc54_utick_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_UTICK) +#define lpc54_flexcomm0_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM0) +#define lpc54_flexcomm1_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM1) +#define lpc54_flexcomm2_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM2) +#define lpc54_flexcomm3_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM3) +#define lpc54_flexcomm4_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM4) +#define lpc54_flexcomm5_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM5) +#define lpc54_flexcomm6_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM6) +#define lpc54_flexcomm7_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM7) +#define lpc54_dmic_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_DMIC) +#define lpc54_ctimer2_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_CTIMER2) +#define lpc54_usb0d_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_USB0D) +#define lpc54_ctimer0_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_CTIMER0) +#define lpc54_ctimer1_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_CTIMER1) + +#define lpc54_lcd_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_LCD) +#define lpc54_sdio_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SDIO) +#define lpc54_usb1h_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1H) +#define lpc54_usb1d_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1D) +#define lpc54_usb1ram_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1RAM) +#define lpc54_emc_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_EMC) +#define lpc54_eth_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_ETH) +#define lpc54_gpio4_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_GPIO4) +#define lpc54_gpio5_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_GPIO5) +#define lpc54_otp_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_OTP) +#define lpc54_rng_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_RNG) +#define lpc54_flexcomm8_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_FLEXCOMM8) +#define lpc54_flexcomm9_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_FLEXCOMM9) +#define lpc54_usb0hmr_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB0HMR) +#define lpc54_usb0hsl_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB0HSL) +#define lpc54_sha_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SHA) +#define lpc54_sc0_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SC0) +#define lpc54_sc1_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SC1) + +#define lpc54_ctimer3_isenabled() lpc54_asynch_isenabled(SYSCON_ASYNCAPBCLKCTRL_CTIMER3) +#define lpc54_ctimer4_isenabled() lpc54_asynch_isenabled(SYSCON_ASYNCAPBCLKCTRL_CTIMER4) + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC546X_ENABLECLK_H */ diff --git a/arch/arm/src/lpc54xx/lpc546x_power.h b/arch/arm/src/lpc54xx/lpc546x_power.h index e3e56d0f340..8bce39b6301 100644 --- a/arch/arm/src/lpc54xx/lpc546x_power.h +++ b/arch/arm/src/lpc54xx/lpc546x_power.h @@ -53,98 +53,98 @@ * selected component; clearling the bit enables it. */ -#define lpc54_enable0(s) putreg32((s), LPC54_SYSCON_PDRUNCFGCLR0) -#define lpc54_enable1(s) putreg32((s), LPC54_SYSCON_PDRUNCFGCLR1) -#define lpc54_disable0(s) putreg32((s), LPC54_SYSCON_PDRUNCFGSET0) -#define lpc54_disable1(s) putreg32((s), LPC54_SYSCON_PDRUNCFGSET1) -#define lpc54_isenabled0(s) ((getreg32(LPC54_SYSCON_PDRUNCFG0) & (s)) == 0) -#define lpc54_isenabled1(s) ((getreg32(LPC54_SYSCON_PDRUNCFG1) & (s)) == 0) +#define lpc54_powerup0(s) putreg32((s), LPC54_SYSCON_PDRUNCFGCLR0) +#define lpc54_powerup1(s) putreg32((s), LPC54_SYSCON_PDRUNCFGCLR1) +#define lpc54_powerdown0(s) putreg32((s), LPC54_SYSCON_PDRUNCFGSET0) +#define lpc54_powerdown1(s) putreg32((s), LPC54_SYSCON_PDRUNCFGSET1) +#define lpc54_ispowered0(s) ((getreg32(LPC54_SYSCON_PDRUNCFG0) & (s)) == 0) +#define lpc54_ispowered1(s) ((getreg32(LPC54_SYSCON_PDRUNCFG1) & (s)) == 0) /* Enable power */ -#define lpc54_fro_enable() lpc54_enable0(SYSCON_PDRUNCFG0_FRO) -#define lpc54_ts_enable() lpc54_enable0(SYSCON_PDRUNCFG0_TS) -#define lpc54_bodrst_enable() lpc54_enable0(SYSCON_PDRUNCFG0_BODRST) -#define lpc54_bodintr_enable() lpc54_enable0(SYSCON_PDRUNCFG0_BODINTR) -#define lpc54_vd2ana_enable() lpc54_enable0(SYSCON_PDRUNCFG0_VD2ANA) -#define lpc54_adc0_enable() lpc54_enable0(SYSCON_PDRUNCFG0_ADC0) -#define lpc54_sramx_enable() lpc54_enable0(SYSCON_PDRUNCFG0_SRAMX) -#define lpc54_sam0_enable() lpc54_enable0(SYSCON_PDRUNCFG0_SRAM0) -#define lpc54_sram123_enable() lpc54_enable0(SYSCON_PDRUNCFG0_SRAM123) -#define lpc54_usbram_enable() lpc54_enable0(SYSCON_PDRUNCFG0_USBRAM) -#define lpc54_vdda_enable() lpc54_enable0(SYSCON_PDRUNCFG0_VDDA) -#define lpc54_wdtosc_enable() lpc54_enable0(SYSCON_PDRUNCFG0_WDTOSC) -#define lpc54_usb0phy_enable() lpc54_enable0(SYSCON_PDRUNCFG0_USB0PHY) -#define lpc54_syspll_enable() lpc54_enable0(SYSCON_PDRUNCFG0_SYSPLL) -#define lpc54_vrefp_enable() lpc54_enable0(SYSCON_PDRUNCFG0_VREFP) -#define lpc54_vd3_enable() lpc54_enable0(SYSCON_PDRUNCFG0_VD3) -#define lpc54_vd4_enable() lpc54_enable0(SYSCON_PDRUNCFG0_VD4) -#define lpc54_vd5_enable() lpc54_enable0(SYSCON_PDRUNCFG0_VD5) -#define lpc54_vd6_enable() lpc54_enable0(SYSCON_PDRUNCFG0_VD6) +#define lpc54_fro_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_FRO) +#define lpc54_ts_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_TS) +#define lpc54_bodrst_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_BODRST) +#define lpc54_bodintr_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_BODINTR) +#define lpc54_vd2ana_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD2ANA) +#define lpc54_adc0_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_ADC0) +#define lpc54_sramx_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_SRAMX) +#define lpc54_sam0_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_SRAM0) +#define lpc54_sram123_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_SRAM123) +#define lpc54_usbram_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_USBRAM) +#define lpc54_vdda_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VDDA) +#define lpc54_wdtosc_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_WDTOSC) +#define lpc54_usb0phy_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_USB0PHY) +#define lpc54_syspll_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_SYSPLL) +#define lpc54_vrefp_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VREFP) +#define lpc54_vd3_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD3) +#define lpc54_vd4_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD4) +#define lpc54_vd5_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD5) +#define lpc54_vd6_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD6) -#define lpc54_usb1phy_enable() lpc54_enable1(SYSCON_PDRUNCFG1_USB1PHY) -#define lpc54_usb1pll_enable() lpc54_enable1(SYSCON_PDRUNCFG1_USB1PLL) -#define lpc54_audpll_enable() lpc54_enable1(SYSCON_PDRUNCFG1_AUDPLL) -#define lpc54_sysosc_enable() lpc54_enable1(SYSCON_PDRUNCFG1_SYSOSC) -#define lpc54_eeprom_enable() lpc54_enable1(SYSCON_PDRUNCFG1_EEPROM) -#define lpc54_rng_enable() lpc54_enable1(SYSCON_PDRUNCFG1_RNG) +#define lpc54_usb1phy_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_USB1PHY) +#define lpc54_usb1pll_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_USB1PLL) +#define lpc54_audpll_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_AUDPLL) +#define lpc54_sysosc_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_SYSOSC) +#define lpc54_eeprom_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_EEPROM) +#define lpc54_rng_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_RNG) /* Disable power */ -#define lpc54_fro_disable() lpc54_disable0(SYSCON_PDRUNCFG0_FRO) -#define lpc54_ts_disable() lpc54_disable0(SYSCON_PDRUNCFG0_TS) -#define lpc54_bodrst_disable() lpc54_disable0(SYSCON_PDRUNCFG0_BODRST) -#define lpc54_bodintr_disable() lpc54_disable0(SYSCON_PDRUNCFG0_BODINTR) -#define lpc54_vd2ana_disable() lpc54_disable0(SYSCON_PDRUNCFG0_VD2ANA) -#define lpc54_adc0_disable() lpc54_disable0(SYSCON_PDRUNCFG0_ADC0) -#define lpc54_sramx_disable() lpc54_disable0(SYSCON_PDRUNCFG0_SRAMX) -#define lpc54_sam0_disable() lpc54_disable0(SYSCON_PDRUNCFG0_SRAM0) -#define lpc54_sram123_disable() lpc54_disable0(SYSCON_PDRUNCFG0_SRAM123) -#define lpc54_usbram_disable() lpc54_disable0(SYSCON_PDRUNCFG0_USBRAM) -#define lpc54_vdda_disable() lpc54_disable0(SYSCON_PDRUNCFG0_VDDA) -#define lpc54_wdtosc_disable() lpc54_disable0(SYSCON_PDRUNCFG0_WDTOSC) -#define lpc54_usb0phy_disable() lpc54_disable0(SYSCON_PDRUNCFG0_USB0PHY) -#define lpc54_syspll_disable() lpc54_disable0(SYSCON_PDRUNCFG0_SYSPLL) -#define lpc54_vrefp_disable() lpc54_disable0(SYSCON_PDRUNCFG0_VREFP) -#define lpc54_vd3_disable() lpc54_disable0(SYSCON_PDRUNCFG0_VD3) -#define lpc54_vd4_disable() lpc54_disable0(SYSCON_PDRUNCFG0_VD4) -#define lpc54_vd5_disable() lpc54_disable0(SYSCON_PDRUNCFG0_VD5) -#define lpc54_vd6_disable() lpc54_disable0(SYSCON_PDRUNCFG0_VD6) +#define lpc54_fro_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_FRO) +#define lpc54_ts_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_TS) +#define lpc54_bodrst_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_BODRST) +#define lpc54_bodintr_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_BODINTR) +#define lpc54_vd2ana_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD2ANA) +#define lpc54_adc0_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_ADC0) +#define lpc54_sramx_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_SRAMX) +#define lpc54_sam0_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_SRAM0) +#define lpc54_sram123_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_SRAM123) +#define lpc54_usbram_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_USBRAM) +#define lpc54_vdda_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VDDA) +#define lpc54_wdtosc_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_WDTOSC) +#define lpc54_usb0phy_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_USB0PHY) +#define lpc54_syspll_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_SYSPLL) +#define lpc54_vrefp_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VREFP) +#define lpc54_vd3_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD3) +#define lpc54_vd4_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD4) +#define lpc54_vd5_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD5) +#define lpc54_vd6_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD6) -#define lpc54_usb1phy_disable() lpc54_disable1(SYSCON_PDRUNCFG1_USB1PHY) -#define lpc54_usb1pll_disable() lpc54_disable1(SYSCON_PDRUNCFG1_USB1PLL) -#define lpc54_audpll_disable() lpc54_disable1(SYSCON_PDRUNCFG1_AUDPLL) -#define lpc54_sysosc_disable() lpc54_disable1(SYSCON_PDRUNCFG1_SYSOSC) -#define lpc54_eeprom_disable() lpc54_disable1(SYSCON_PDRUNCFG1_EEPROM) -#define lpc54_rng_disable() lpc54_disable1(SYSCON_PDRUNCFG1_RNG) +#define lpc54_usb1phy_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_USB1PHY) +#define lpc54_usb1pll_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_USB1PLL) +#define lpc54_audpll_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_AUDPLL) +#define lpc54_sysosc_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_SYSOSC) +#define lpc54_eeprom_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_EEPROM) +#define lpc54_rng_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_RNG) /* Test if power is enabled */ -#define lpc54_fro_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_FRO) -#define lpc54_ts_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_TS) -#define lpc54_bodrst_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_BODRST) -#define lpc54_bodintr_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_BODINTR) -#define lpc54_vd2ana_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_VD2ANA) -#define lpc54_adc0_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_ADC0) -#define lpc54_sramx_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_SRAMX) -#define lpc54_sam0_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_SRAM0) -#define lpc54_sram123_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_SRAM123) -#define lpc54_usbram_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_USBRAM) -#define lpc54_vdda_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_VDDA) -#define lpc54_wdtosc_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_WDTOSC) -#define lpc54_usb0phy_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_USB0PHY) -#define lpc54_syspll_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_SYSPLL) -#define lpc54_vrefp_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_VREFP) -#define lpc54_vd3_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_VD3) -#define lpc54_vd4_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_VD4) -#define lpc54_vd5_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_VD5) -#define lpc54_vd6_isenabled() lpc54_isenabled0(SYSCON_PDRUNCFG0_VD6) +#define lpc54_fro_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_FRO) +#define lpc54_ts_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_TS) +#define lpc54_bodrst_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_BODRST) +#define lpc54_bodintr_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_BODINTR) +#define lpc54_vd2ana_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD2ANA) +#define lpc54_adc0_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_ADC0) +#define lpc54_sramx_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_SRAMX) +#define lpc54_sam0_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_SRAM0) +#define lpc54_sram123_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_SRAM123) +#define lpc54_usbram_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_USBRAM) +#define lpc54_vdda_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VDDA) +#define lpc54_wdtosc_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_WDTOSC) +#define lpc54_usb0phy_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_USB0PHY) +#define lpc54_syspll_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_SYSPLL) +#define lpc54_vrefp_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VREFP) +#define lpc54_vd3_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD3) +#define lpc54_vd4_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD4) +#define lpc54_vd5_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD5) +#define lpc54_vd6_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD6) -#define lpc54_usb1phy_isenabled() lpc54_isenabled1(SYSCON_PDRUNCFG1_USB1PHY) -#define lpc54_usb1pll_isenabled() lpc54_isenabled1(SYSCON_PDRUNCFG1_USB1PLL) -#define lpc54_audpll_isenabled() lpc54_isenabled1(SYSCON_PDRUNCFG1_AUDPLL) -#define lpc54_sysosc_isenabled() lpc54_isenabled1(SYSCON_PDRUNCFG1_SYSOSC) -#define lpc54_eeprom_isenabled() lpc54_isenabled1(SYSCON_PDRUNCFG1_EEPROM) -#define lpc54_rng_isenabled() lpc54_isenabled1(SYSCON_PDRUNCFG1_RNG) +#define lpc54_usb1phy_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_USB1PHY) +#define lpc54_usb1pll_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_USB1PLL) +#define lpc54_audpll_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_AUDPLL) +#define lpc54_sysosc_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_SYSOSC) +#define lpc54_eeprom_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_EEPROM) +#define lpc54_rng_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_RNG) #endif /* __ARCH_ARM_SRC_LPC54XX_LPC546X_PERIPHPOWER_H */ diff --git a/arch/arm/src/lpc54xx/lpc546x_reset.h b/arch/arm/src/lpc54xx/lpc546x_reset.h new file mode 100644 index 00000000000..cd6ded40d13 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc546x_reset.h @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc546x_reset.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC546X_RESET_H +#define __ARCH_ARM_SRC_LPC54XX_LPC546X_RESET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define lpc54_reset_peripheral0(m) \ + lpc54_reset(LPC54_SYSCON_PRESETCTRLSET0, LPC54_SYSCON_PRESETCTRLCLR0, \ + LPC54_SYSCON_PRESETCTRL0, (m)) + +#define lpc54_reset_peripheral1(m) \ + lpc54_reset(LPC54_SYSCON_PRESETCTRLSET1, LPC54_SYSCON_PRESETCTRLCLR1, \ + LPC54_SYSCON_PRESETCTRL1, (m)) + +#define lpc54_reset_peripheral2(m) \ + lpc54_reset(LPC54_SYSCON_PRESETCTRLSET2, LPC54_SYSCON_PRESETCTRLCLR2, \ + LPC54_SYSCON_PRESETCTRL2, (m)) + +#define lpc54_reset_async_peripheral(m) \ + lpc54_reset(LPC54_SYSCON_ASYNCPRESETCTRLSET, LPC54_SYSCON_ASYNCPRESETCTRLCLR, \ + LPC54_SYSCON_ASYNCPRESETCTRL, (m)) + +#define lpc54_reset_flash() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_FLASH) +#define lpc54_reset_fmc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_FMC) +#define lpc54_reset_eeprom() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_EEPROM) +#define lpc54_reset_spifi() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_SPIFI) +#define lpc54_reset_inputmux() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_INPUTMUX) +#define lpc54_reset_iocon() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_IOCON) +#define lpc54_reset_gpio0() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO0) +#define lpc54_reset_gpio1() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO1) +#define lpc54_reset_gpio2() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO2) +#define lpc54_reset_gpio3() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO3) +#define lpc54_reset_pint() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_PINT) +#define lpc54_reset_gint() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GINT) +#define lpc54_reset_dma() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_DMA) +#define lpc54_reset_crc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_CRC) +#define lpc54_reset_wwdt() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_WWDT) +#define lpc54_reset_rtc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_RTC) +#define lpc54_reset_adc0() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_ADC0) + +#define lpc54_reset_mrt() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_MRT) +#define lpc54_reset_sct0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_SCT0) +#define lpc54_reset_mcan0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_MCAN0) +#define lpc54_reset_mcan1() lpc54_reset_peripheral1SYSCON_PRESETCTRL1_MCAN1) +#define lpc54_reset_utick() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_UTICK) +#define lpc54_reset_flexcomm0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM0) +#define lpc54_reset_flexcomm1() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM1) +#define lpc54_reset_flexcomm2() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM2) +#define lpc54_reset_flexcomm3() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM3) +#define lpc54_reset_flexcomm4() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM4) +#define lpc54_reset_flexcomm5() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM5) +#define lpc54_reset_flexcomm6() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM6) +#define lpc54_reset_flexcomm7() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM7) +#define lpc54_reset_dmic() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_DMIC) +#define lpc54_reset_ctimer2() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER2) +#define lpc54_reset_usb0d() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_USB0D) +#define lpc54_reset_ctimer0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER0) +#define lpc54_reset_ctimer1() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER1) + +#define lpc54_reset_lcd() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_LCD) +#define lpc54_reset_sdio() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SDIO) +#define lpc54_reset_usb1h() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1H) +#define lpc54_reset_usb1d() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1D) +#define lpc54_reset_usb1ram() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1RAM) +#define lpc54_reset_emc() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_EMC) +#define lpc54_reset_eth() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_ETH) +#define lpc54_reset_gpio4() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_GPIO4) +#define lpc54_reset_gpio5() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_GPIO5) +#define lpc54_reset_otp() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_OTP) +#define lpc54_reset_rng() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_RNG) +#define lpc54_reset_flexcomm8() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_FLEXCOMM8) +#define lpc54_reset_flexcomm9() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_FLEXCOMM9) +#define lpc54_reset_usb0hmr() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB0HMR) +#define lpc54_reset_usb0hsl() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB0HSL) +#define lpc54_reset_sha() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SHA) +#define lpc54_reset_sc0() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SC0) +#define lpc54_reset_sc1() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SC1) + +#define lpc54_reset_ctimer3() lpc54_reset_async_peripheral(SYSCON_ASYNCPRESET_CTIMER3) +#define lpc54_reset_ctimer4() lpc54_reset_async_peripheral(SYSCON_ASYNCPRESET_CTIMER4) + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC546X_RESET_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_clockconfig.c b/arch/arm/src/lpc54xx/lpc54_clockconfig.c index ba61540fe5d..1263767f6f2 100644 --- a/arch/arm/src/lpc54xx/lpc54_clockconfig.c +++ b/arch/arm/src/lpc54xx/lpc54_clockconfig.c @@ -99,7 +99,7 @@ static void lpc54_setvoltage(uint32_t freq) static void lpc54_power_pll(void) { - lpc54_vd3_enable(); + lpc54_vd3_powerup(); while ((getreg32(0x40020054) & (1 << 6)) == 0) { } @@ -176,7 +176,7 @@ static void lpc54_configure_pll(FAR const struct pll_setup_s *pllsetup) /* Power off PLL during setup changes */ - lpc54_syspll_disable(); + lpc54_syspll_powerdown(); /* Write PLL setup data */ @@ -206,7 +206,7 @@ static void lpc54_configure_pll(FAR const struct pll_setup_s *pllsetup) /* Initialize and power up PLL */ putreg32(maxcco, LPC54_SYSCON_SYSPLLMDEC); - lpc54_syspll_enable(); + lpc54_syspll_powerup(); /* Set MREQ to activate */ @@ -228,7 +228,7 @@ static void lpc54_configure_pll(FAR const struct pll_setup_s *pllsetup) /* Enable PLL */ - lpc54_syspll_enable(); + lpc54_syspll_powerup(); } /* Wait for the lock? */ @@ -261,7 +261,7 @@ void lpc54_clockconfig(FAR const struct pll_setup_s *pllsetup) /* Set up the clock sources */ /* Power up the FRO 12MHz clock source */ - lpc54_fro_enable(); + lpc54_fro_powerup(); /* Switch to FRO 12MHz first to ensure we can change voltage without * accidentally being below the voltage for current speed. diff --git a/arch/arm/src/lpc54xx/lpc54_emc.c b/arch/arm/src/lpc54xx/lpc54_emc.c index dbff4184cde..1c570a8f2eb 100644 --- a/arch/arm/src/lpc54xx/lpc54_emc.c +++ b/arch/arm/src/lpc54xx/lpc54_emc.c @@ -54,6 +54,8 @@ #include "chip/lpc54_syscon.h" #include "chip/lpc54_emc.h" +#include "lpc54_config.h" +#include "lpc54_enableclk.h" #include "lpc54_reset.h" #include "lpc54_emc.h" @@ -237,7 +239,7 @@ void lpc54_emc_initialize(FAR const struct emc_config_s *config) /* Enable EMC clock */ - putreg32(SYSCON_AHBCLKCTRL2_EMC, LPC54_SYSCON_AHBCLKCTRLSET2); + lpc54_emc_enableclk(); /* Reset the EMC */ diff --git a/arch/arm/src/lpc54xx/lpc54_enableclk.h b/arch/arm/src/lpc54xx/lpc54_enableclk.h new file mode 100644 index 00000000000..56a2c1194dc --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_enableclk.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_enableclk.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_ENABLECLK_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_ENABLECLK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the correct definitions for the configured chip */ + +#if defined(CONFIG_ARCH_FAMILY_LPC546XX) +# include "lpc546x_enableclk.h" +#else +# error "Unsupported LPC54 architecture" +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_ENABLECLK_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.c b/arch/arm/src/lpc54xx/lpc54_i2c_master.c index 582efd34ee5..15f1e9fbf87 100644 --- a/arch/arm/src/lpc54xx/lpc54_i2c_master.c +++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.c @@ -64,6 +64,7 @@ #include "chip/lpc54_flexcomm.h" #include "chip/lpc54_i2c.h" #include "lpc54_config.h" +#include "lpc54_enableclk.h" #include "lpc54_i2c_master.h" #include @@ -115,7 +116,7 @@ static int lpc54_i2c_reset(FAR struct i2c_master_s * dev); #endif /**************************************************************************** - * I2C device operations + * Private Data ****************************************************************************/ struct i2c_ops_s lpc54_i2c_ops = @@ -157,6 +158,38 @@ static struct lpc54_i2cdev_s g_i2c8_dev; static struct lpc54_i2cdev_s g_i2c9_dev; #endif +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_i2c_putreg + * + * Description: + * Set the frequency for the next transfer + * + ****************************************************************************/ + +static inline void lpc54_i2c_putreg(struct lpc54_i2cdev_s *priv, + unsigned int regoffset, uint32_t regval) +{ + putreg32(value, priv->base + regoffset); +} + +/**************************************************************************** + * Name: lpc54_i2c_gettreg + * + * Description: + * Set the frequency for the next transfer + * + ****************************************************************************/ + +static inline void lpc54_i2c_gettreg(struct lpc54_i2cdev_s *priv, + unsigned int regoffset) +{ + return getreg32(priv->base + regoffset); +} + /**************************************************************************** * Name: lpc54_i2c_setfrequency * @@ -168,12 +201,70 @@ static struct lpc54_i2cdev_s g_i2c9_dev; static void lpc54_i2c_setfrequency(struct lpc54_i2cdev_s *priv, uint32_t frequency) { + uint32_t scl; + uint32_t divider; + uint32_t best_scl; + uint32_t best_div; + uint32_t err; + uint32_t best_err; + uint32_t regval; + /* Has the I2C frequency changed? */ if (frequency != priv->frequency) { /* Yes.. instantiate the new I2C frequency */ -#warning Missing logic + + best_err = 0; + + for (scl = 9; scl >= 2; scl--) + { + /* Calculate ideal divider value for the current scl candidate. + * + * SCL High Time: Thi = divider * SCLhi + * SCL High Time: Tlo = divider * SCLlo + * Fscl = Finput / (Thi + Tlo) + * + * If Thi == TloL: Fscl = Finput / (divider * SCL * 2) + * Or: divider = Finput / (Fscl * SCL * 2) + */ + + divider = priv->fclock / (frequency * scl * 2); + + /* Adjust it if it is out of range */ + + if (divider > 0x00010000) + { + divider = 0x00010000; + } + + /* Calculate the frequency error */ + + err = priv->fclock - (frequency * scl * 2 * divider); + if (err < best_err || best_err == 0) + { + best_div = divider; + best_scl = scl; + best_err = err; + } + + if (err == 0 || divider >= 0x10000) + { + /* Break out of the loop early ifeither exact value was found or + * the divider is at its maximum value. + */ + + break; + } + } + + /* Instantiate the new I2C frequency */ + + regval = I2C_CLKDIV(best_div); + lpc54_i2c_putreg(priv, LPC54_I2C_CLKDIV_OFFSET, regval); + + regval = I2C_MSTTIME_SCLLOW(n) | I2C_MSTTIME_SCLHIGH(n); + lpc54_i2c_putreg(LPC54_I2C_MSTTIME_OFFSET, regval); priv->frequency = frequency; } @@ -189,7 +280,25 @@ static void lpc54_i2c_setfrequency(struct lpc54_i2cdev_s *priv, static int lpc54_i2c_start(struct lpc54_i2cdev_s *priv) { -#warning Missing logic + struct i2c_msg_s *msg = priv->msgs; + uint32_t regval; + + /* Write the address with the R/W bit */ + + if ((I2C_M_READ & msg->flags) == I2C_M_READ) + { + regval = I2C_READADDR8(msg->addr); + } + else + { + regval = I2C_WRITEADDR8(msg->addr); + } + + lpc54_i2c_putreg(priv, LPC54_I2C_MSTDAT_OFFSET, regval); + + /* Initiate the Start */ + + lpc54_i2c_putreg(priv, LPC54_I2C_MSTCTL_OFFSET, I2C_MSTCTL_MSTSTART); return priv->nmsg; } @@ -248,6 +357,21 @@ void lpc32_i2c_nextmsg(struct lpc54_i2cdev_s *priv) } } +/**************************************************************************** + * Name: lpc54_i2c_statemachine + * + * Description: + * This is the I2C transfer state machine that implements the actual + * transfer. It may be called from the interrupt level or is may be used + * without interrupts in a polled mode. + * + ****************************************************************************/ + +static void lpc54_i2c_statemachine(struct lpc54_i2cdev_s *priv) +{ +#warning Missing logic +} + /**************************************************************************** * Name: lpc54_i2c_interrupt * @@ -264,7 +388,7 @@ static int lpc54_i2c_interrupt(int irq, FAR void *context, FAR void *arg) DEBUGASSERT(priv != NULL); - state = getreg32(priv->base + LPC54_I2C_STAT_OFFSET); + state = lpc54_i2c_getreg(priv, LPC54_I2C_STAT_OFFSET); msg = priv->msgs; #warning Missing logic @@ -377,7 +501,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM0 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM0, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm0_enableclk(); /* Set FLEXCOMM0 to the I2C peripheral, locking that configuration * in place. @@ -413,7 +537,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM1 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM1, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm1_enableclk(); /* Set FLEXCOMM1 to the I2C peripheral, locking that configuration * in place. @@ -449,7 +573,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM2 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM2, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm2_enableclk(); /* Set FLEXCOMM2 to the I2C peripheral, locking that configuration * in place. @@ -485,7 +609,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM3 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM3, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm3_enableclk(); /* Set FLEXCOMM3 to the I2C peripheral, locking that configuration * in place. @@ -521,7 +645,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM4 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM4, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm4_enableclk(); /* Set FLEXCOMM4 to the I2C peripheral, locking that configuration * in place. @@ -557,7 +681,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM5 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM5, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm5_enableclk(); /* Set FLEXCOMM5 to the I2C peripheral, locking that configuration * in place. @@ -593,7 +717,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM6 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM6, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm6_enableclk(); /* Set FLEXCOMM6 to the I2C peripheral, locking that configuration * in place. @@ -629,7 +753,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM7 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM7, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm7_enableclk(); /* Set FLEXCOMM7 to the I2C peripheral, locking that configuration * in place. @@ -665,7 +789,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM8 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM8, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm8_enableclk(); /* Set FLEXCOMM8 to the I2C peripheral, locking that configuration * in place. @@ -701,7 +825,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM9 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM9, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm9_enableclk(); /* Set FLEXCOMM9 to the I2C peripheral, locking that configuration * in place. @@ -738,8 +862,16 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) leave_critical_section(flags); - /* Enable the I2C peripheral and configure master mode */ -#Missing logic + /* Install our operations */ + + priv->dev.ops = &lpc54_i2c_ops; + + /* Enable the I2C peripheral in the master mode */ + + regval = lpc54_i2c_getreg(priv, LPC54_I2C_CFG_OFFSET); + regval &= I2C_CFG_ALLENABLES; + regval |= I2C_CFG_MSTEN; + lpc54_i2c_putreg(priv, LPC54_I2C_CFG_OFFSET, regval) /* Set the default I2C frequency */ @@ -765,13 +897,13 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) irq_attach(priv->irq, lpc54_i2c_interrupt, priv); - /* Enable Interrupt Handler */ + /* Disable interrupts at the I2C peripheral */ + + lpc54_i2c_putreg(priv, LPC54_I2C_INTENCLR_OFFSET, I2C_INT_ALL); + + /* Enable interrupts at the NVIC */ up_enable_irq(priv->irq); - - /* Install our operations */ - - priv->dev.ops = &lpc54_i2c_ops; return &priv->dev; } @@ -786,11 +918,18 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) int lpc54_i2cbus_uninitialize(FAR struct i2c_master_s * dev) { struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *) dev; + uint32_t regval; /* Disable I2C interrupts */ #warning Missing logic /* Disable the I2C peripheral */ + + regval = lpc54_i2c_getreg(priv, LPC54_I2C_CFG_OFFSET); + regval &= I2C_CFG_ALLENABLES; + regval &= ~I2C_CFG_MSTEN; + lpc54_i2c_putreg(priv, LPC54_I2C_CFG_OFFSET, regval) + #warning Missing logic /* Disable the Flexcomm interface at the NVIC and detach the interrupt. */ diff --git a/arch/arm/src/lpc54xx/lpc54_lcd.c b/arch/arm/src/lpc54xx/lpc54_lcd.c index 97908719033..25cb80fc333 100644 --- a/arch/arm/src/lpc54xx/lpc54_lcd.c +++ b/arch/arm/src/lpc54xx/lpc54_lcd.c @@ -52,6 +52,8 @@ #include "up_arch.h" #include "chip/lpc54_syscon.h" #include "chip/lpc54_pinmux.h" +#include "lpc54_config.h" +#include "lpc54_enableclk.h" #include "lpc54_gpio.h" #include "lpc54_reset.h" #include "lpc54_lcd.h" @@ -532,7 +534,7 @@ int up_fbinitialize(int display) /* Enable clocking to the LCD peripheral */ - putreg32(SYSCON_AHBCLKCTRL2_LCD, LPC54_SYSCON_AHBCLKCTRLSET2); + lpc54_lcd_enableclk(); /* Route Main clock (or LCK CLKIN) to the LCD. */ @@ -873,7 +875,7 @@ void up_fbuninitialize(int display) /* Disable clocking to the LCD peripheral */ - putreg32(SYSCON_AHBCLKCTRL2_LCD, LPC54_SYSCON_AHBCLKCTRLCLR2); + lpc54_lcd_disableclk(); } /**************************************************************************** diff --git a/arch/arm/src/lpc54xx/lpc54_lowputc.c b/arch/arm/src/lpc54xx/lpc54_lowputc.c index c069be0dc9a..9d556bae14f 100644 --- a/arch/arm/src/lpc54xx/lpc54_lowputc.c +++ b/arch/arm/src/lpc54xx/lpc54_lowputc.c @@ -58,6 +58,7 @@ #include "chip/lpc54_usart.h" #include "lpc54_config.h" +#include "lpc54_enableclk.h" #include "lpc54_clockconfig.h" #include "lpc54_gpio.h" #include "lpc54_lowputc.h" @@ -410,7 +411,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART0 /* Attach 12 MHz clock to FLEXCOMM0 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM0, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm0_enableclk(); /* Set FLEXCOMM0 to the USART peripheral, locking that configuration in place. */ @@ -436,7 +437,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART1 /* Attach 12 MHz clock to FLEXCOMM1 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM1, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm1_enableclk(); /* Set FLEXCOMM1 to the USART peripheral, locking that configuration in place. */ @@ -462,7 +463,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART2 /* Attach 12 MHz clock to FLEXCOMM2 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM2, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm2_enableclk(); /* Set FLEXCOMM2 to the USART peripheral, locking that configuration in place. */ @@ -488,7 +489,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART3 /* Attach 12 MHz clock to FLEXCOMM3 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM3, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm3_enableclk(); /* Set FLEXCOMM3 to the USART peripheral, locking that configuration in place. */ @@ -514,7 +515,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART4 /* Attach 12 MHz clock to FLEXCOMM4 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM4, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm4_enableclk(); /* Set FLEXCOMM4 to the USART peripheral, locking that configuration in place. */ @@ -540,7 +541,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART5 /* Attach 12 MHz clock to FLEXCOMM5 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM5, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm5_enableclk(); /* Set FLEXCOMM5 to the USART peripheral, locking that configuration in place. */ @@ -566,7 +567,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART6 /* Attach 12 MHz clock to FLEXCOMM6 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM6, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm6_enableclk(); /* Set FLEXCOMM6 to the USART peripheral, locking that configuration in place. */ @@ -592,7 +593,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART7 /* Attach 12 MHz clock to FLEXCOMM7 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM7, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm7_enableclk(); /* Set FLEXCOMM7 to the USART peripheral, locking that configuration in place. */ @@ -618,7 +619,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART8 /* Attach 12 MHz clock to FLEXCOMM8 */ - putreg32(SYSCON_AHBCLKCTRL2_FLEXCOMM8, LPC54_SYSCON_AHBCLKCTRLSET2); + lpc54_flexcomm8_enableclk(); /* Set FLEXCOMM8 to the USART peripheral, locking that configuration in place. */ @@ -644,7 +645,7 @@ void lpc54_lowsetup(void) #ifdef HAVE_USART9 /* Attach 12 MHz clock to FLEXCOMM9 */ - putreg32(SYSCON_AHBCLKCTRL2_FLEXCOMM9, LPC54_SYSCON_AHBCLKCTRLSET2); + lpc54_flexcomm9_enableclk(); /* Set FLEXCOMM9 to the USART peripheral, locking that configuration in place. */ diff --git a/arch/arm/src/lpc54xx/lpc54_reset.h b/arch/arm/src/lpc54xx/lpc54_reset.h index de4d3fe6596..b00434a6a35 100644 --- a/arch/arm/src/lpc54xx/lpc54_reset.h +++ b/arch/arm/src/lpc54xx/lpc54_reset.h @@ -42,87 +42,16 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +/* Include the correct definitions for the configured chip */ -#define lpc54_reset_peripheral0(m) \ - lpc54_reset(LPC54_SYSCON_PRESETCTRLSET0, LPC54_SYSCON_PRESETCTRLCLR0, \ - LPC54_SYSCON_PRESETCTRL0, (m)) - -#define lpc54_reset_peripheral1(m) \ - lpc54_reset(LPC54_SYSCON_PRESETCTRLSET1, LPC54_SYSCON_PRESETCTRLCLR1, \ - LPC54_SYSCON_PRESETCTRL1, (m)) - -#define lpc54_reset_peripheral2(m) \ - lpc54_reset(LPC54_SYSCON_PRESETCTRLSET2, LPC54_SYSCON_PRESETCTRLCLR2, \ - LPC54_SYSCON_PRESETCTRL2, (m)) - -#define lpc54_reset_async_peripheral(m) \ - lpc54_reset(LPC54_SYSCON_ASYNCPRESETCTRLSET, LPC54_SYSCON_ASYNCPRESETCTRLCLR, \ - LPC54_SYSCON_ASYNCPRESETCTRL, (m)) - -#define lpc54_reset_flash() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_FLASH) -#define lpc54_reset_fmc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_FMC) -#define lpc54_reset_eeprom() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_EEPROM) -#define lpc54_reset_spifi() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_SPIFI) -#define lpc54_reset_inputmux() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_INPUTMUX) -#define lpc54_reset_iocon() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_IOCON) -#define lpc54_reset_gpio0() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO0) -#define lpc54_reset_gpio1() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO1) -#define lpc54_reset_gpio2() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO2) -#define lpc54_reset_gpio3() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO3) -#define lpc54_reset_pint() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_PINT) -#define lpc54_reset_gint() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GINT) -#define lpc54_reset_dma() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_DMA) -#define lpc54_reset_crc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_CRC) -#define lpc54_reset_wwdt() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_WWDT) -#define lpc54_reset_rtc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_RTC) -#define lpc54_reset_adc0() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_ADC0) - -#define lpc54_reset_mrt() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_MRT) -#define lpc54_reset_sct0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_SCT0) -#define lpc54_reset_mcan0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_MCAN0) -#define lpc54_reset_mcan1() lpc54_reset_peripheral1SYSCON_PRESETCTRL1_MCAN1) -#define lpc54_reset_utick() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_UTICK) -#define lpc54_reset_flexcomm0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM0) -#define lpc54_reset_flexcomm1() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM1) -#define lpc54_reset_flexcomm2() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM2) -#define lpc54_reset_flexcomm3() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM3) -#define lpc54_reset_flexcomm4() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM4) -#define lpc54_reset_flexcomm5() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM5) -#define lpc54_reset_flexcomm6() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM6) -#define lpc54_reset_flexcomm7() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM7) -#define lpc54_reset_dmic() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_DMIC) -#define lpc54_reset_ctimer2() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER2) -#define lpc54_reset_usb0d() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_USB0D) -#define lpc54_reset_ctimer0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER0) -#define lpc54_reset_ctimer1() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER1) - -#define lpc54_reset_lcd() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_LCD) -#define lpc54_reset_sdio() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SDIO) -#define lpc54_reset_usb1h() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1H) -#define lpc54_reset_usb1d() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1D) -#define lpc54_reset_usb1ram() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1RAM) -#define lpc54_reset_emc() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_EMC) -#define lpc54_reset_eth() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_ETH) -#define lpc54_reset_gpio4() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_GPIO4) -#define lpc54_reset_gpio5() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_GPIO5) -#define lpc54_reset_otp() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_OTP) -#define lpc54_reset_rng() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_RNG) -#define lpc54_reset_flexcomm8() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_FLEXCOMM8) -#define lpc54_reset_flexcomm9() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_FLEXCOMM9) -#define lpc54_reset_usb0hmr() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB0HMR) -#define lpc54_reset_usb0hsl() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB0HSL) -#define lpc54_reset_sha() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SHA) -#define lpc54_reset_sc0() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SC0) -#define lpc54_reset_sc1() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SC1) - -#define lpc54_reset_ctimer3() lpc54_reset_async_peripheral(SYSCON_ASYNCPRESET_CTIMER3) -#define lpc54_reset_ctimer4() lpc54_reset_async_peripheral(SYSCON_ASYNCPRESET_CTIMER4) +#if defined(CONFIG_ARCH_FAMILY_LPC546XX) +# include "lpc546x_reset.h" +#else +# error "Unsupported LPC54 architecture" +#endif /**************************************************************************** - * Public Functions + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.c b/arch/arm/src/lpc54xx/lpc54_spi_master.c index 710c95e1909..5d7b34b7522 100644 --- a/arch/arm/src/lpc54xx/lpc54_spi_master.c +++ b/arch/arm/src/lpc54xx/lpc54_spi_master.c @@ -58,6 +58,7 @@ #include "chip/lpc54_flexcomm.h" #include "chip/lpc54_spi.h" #include "lpc54_config.h" +#include "lpc54_enableclk.h" #include "lpc54_spi_master.h" #ifdef HAVE_SPI_MASTER_DEVICE @@ -660,7 +661,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM0 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM0, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm0_enableclk(); /* Set FLEXCOMM0 to the SPI peripheral, locking that configuration * in place. @@ -693,7 +694,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM1 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM1, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm1_enableclk(); /* Set FLEXCOMM1 to the SPI peripheral, locking that configuration * in place. @@ -726,7 +727,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM2 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM2, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm2_enableclk(); /* Set FLEXCOMM2 to the SPI peripheral, locking that configuration * in place. @@ -759,7 +760,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM3 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM3, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm3_enableclk(); /* Set FLEXCOMM3 to the SPI peripheral, locking that configuration * in place. @@ -792,7 +793,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM4 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM4, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm4_enableclk(); /* Set FLEXCOMM4 to the SPI peripheral, locking that configuration * in place. @@ -825,7 +826,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM5 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM5, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm5_enableclk(); /* Set FLEXCOMM5 to the SPI peripheral, locking that configuration * in place. @@ -858,7 +859,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM6 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM6, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm6_enableclk(); /* Set FLEXCOMM6 to the SPI peripheral, locking that configuration * in place. @@ -891,7 +892,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM7 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM7, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm7_enableclk(); /* Set FLEXCOMM7 to the SPI peripheral, locking that configuration * in place. @@ -924,7 +925,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM8 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM8, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm8_enableclk(); /* Set FLEXCOMM8 to the SPI peripheral, locking that configuration * in place. @@ -957,7 +958,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port) { /* Attach 12 MHz clock to FLEXCOMM9 */ - putreg32(SYSCON_AHBCLKCTRL1_FLEXCOMM9, LPC54_SYSCON_AHBCLKCTRLSET1); + lpc54_flexcomm9_enableclk(); /* Set FLEXCOMM9 to the SPI peripheral, locking that configuration * in place.