diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig index 5e7361f1025..1ebd05f3faa 100644 --- a/arch/arm/src/s32k1xx/Kconfig +++ b/arch/arm/src/s32k1xx/Kconfig @@ -44,7 +44,7 @@ config ARCH_CHIP_S32K146 config ARCH_CHIP_S32K148 bool "S32K148" select ARCH_CHIP_S32K14X - select S32K1XX_HAVE_ETHMAC + select S32K1XX_HAVE_ENET select S32K1XX_HAVE_SAI ---help--- Cortex-M4F, 2Mb FLASH, 256Kb RAM incl. 4Kb FlexRAM @@ -66,10 +66,11 @@ config ARCH_CHIP_S32K14X select S32K1XX_HAVE_EWM select S32K1XX_HAVE_SPLL select S32K1XX_HAVE_HSRUN + select S32K1XX_HAVE_LMEM # Chip Capabilities -config S32K1XX_HAVE_ETHMAC +config S32K1XX_HAVE_ENET bool default n @@ -85,6 +86,10 @@ config S32K1XX_HAVE_HSRUN bool default n +config S32K1XX_HAVE_LMEM + bool + default n + config S32K1XX_HAVE_QSPI bool default n @@ -115,6 +120,11 @@ config S32K1XX_EDMA bool "eDMA" default n +config S32K1XX_ENET + bool "Ethernet" + default n + depends on S32K1XX_HAVE_ENET + config S32K1XX_LPUART0 bool "LPUART0" default n @@ -147,6 +157,10 @@ config S32K1XX_LPSPI1 endmenu # S32K1XX Peripheral Selection +config S32K1XX_WDT_DISABLE + bool "Disable watchdog on reset" + default y + menu "S32K1xx GPIO Interrupt Configuration" config S32K1XX_GPIOIRQ diff --git a/arch/arm/src/s32k1xx/Make.defs b/arch/arm/src/s32k1xx/Make.defs index de6d4cb94d7..de491e0ca87 100644 --- a/arch/arm/src/s32k1xx/Make.defs +++ b/arch/arm/src/s32k1xx/Make.defs @@ -54,7 +54,8 @@ endif CHIP_ASRCS = CHIP_CSRCS = s32k1xx_start.c s32k1xx_lowputc.c s32k1xx_clockconfig.c -CHIP_CSRCS += s32k1xx_periphclocks.c s32k1xx_pin.c +CHIP_CSRCS += s32k1xx_periphclocks.c s32k1xx_pin.c s32k1xx_pingpio.c +CHIP_CSRCS += s32k1xx_idle.c ifeq ($(CONFIG_S32K1XX_LPUART),y) CHIP_CSRCS += s32k1xx_serial.c diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h new file mode 100644 index 00000000000..e72e25081fd --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h @@ -0,0 +1,128 @@ +/************************************************************************************ + * arch/arm/src/s32k1xx/chip/s32k1xx_lmem.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LMEM_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LMEM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#ifdef CONFIG_S32K1XX_HAVE_LMEM + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* LMEM Register Offsets ************************************************************/ + +#define S32K1XX_LMEM_PCCCR_OFFSET 0x0000 /* Cache control register */ +#define S32K1XX_LMEM_PCCLCR_OFFSET 0x0004 /* Cache line control register */ +#define S32K1XX_LMEM_PCCSAR_OFFSET 0x0008 /* Cache search address register */ +#define S32K1XX_LMEM_PCCCVR_OFFSET 0x000c /* Cache read/write value register */ +#define S32K1XX_LMEM_PCCRMR_OFFSET 0x0020 /* Cache regions mode register */ + +/* LMEM Register Addresses **********************************************************/ + +#define S32K1XX_LMEM_PCCCR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCCR_OFFSET) +#define S32K1XX_LMEM_PCCLCR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCLCR_OFFSET) +#define S32K1XX_LMEM_PCCSAR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCSAR_OFFSET) +#define S32K1XX_LMEM_PCCCVR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCCVR_OFFSET) +#define S32K1XX_LMEM_PCCRMR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCRMR_OFFSET) + +/* LMEM Register Bitfield Definitions ***********************************************/ + +/* Cache control register */ + +#define LMEM_PCCCR_ENCACHE (1 << 0) /* Bit 0: Cache enable */ +#define LMEM_PCCCR_PCCR2 (1 << 2) /* Bit 2: Forces all to write through */ +#define LMEM_PCCCR_PCCR3 (1 << 3) /* Bit 3: No allocation on cache misses */ +#define LMEM_PCCCR_INVW0 (1 << 24) /* Bit 24: Invalidate Way 0 */ +#define LMEM_PCCCR_PUSHW0 (1 << 25) /* Bit 25: Push Way 0 */ +#define LMEM_PCCCR_INVW1 (1 << 26) /* Bit 26: Invalidate Way 1 */ +#define LMEM_PCCCR_PUSHW1 (1 << 27) /* Bit 27: Push Way 1 */ +#define LMEM_PCCCR_GO (1 << 31) /* Bit 31: Initiate Cache Command */ + +/* Cache line control register */ + +#define LMEM_PCCLCR_LGO (1 << 0) /* Bit 0: Initiate Cache Line Command */ +#define LMEM_PCCLCR_CACHEADDR_SHIFT (2) /* Bits 2-13: Cache address */ +#define LMEM_PCCLCR_CACHEADDR_MASK (0x7ff << LMEM_PCCLCR_CACHEADDR_SHIFT) +# define LMEM_PCCLCR_CACHEADDR(n) ((uint32_t)(n) << LMEM_PCCLCR_CACHEADDR_SHIFT) +#define LMEM_PCCLCR_WSEL (1 << 14) /* Bit 14: Way select */ +# define LMEM_PCCLCR_WSEL_WAY0 (0) /* Way0 */ +# define LMEM_PCCLCR_WSEL_WAY0 (1 << 14) /* Way1 */ +#define LMEM_PCCLCR_TDSEL (1 << 16) /* Bit 16: Tag/Data Select */ +# define LMEM_PCCLCR_TDSEL_DATA (0) /* Data */ +# define LMEM_PCCLCR_TDSEL_TAG (1 << 16) /* Tag */ +#define LMEM_PCCLCR_LCIVB (1 << 20) /* Bit 20: Line Command Initial Valid Bit */ +#define LMEM_PCCLCR_LCWAY (1 << 22) /* Bit 22: Line Command Way */ +# define LMEM_PCCLCR_LCWAY_WAY0 (0) /* Way0 */ +# define LMEM_PCCLCR_LCWAY_WAY (1 << 22) /* Way1 */ +#define LMEM_PCCLCR_LCMD_SHIFT (24) /* Bits 24-25: Line Command */ +#define LMEM_PCCLCR_LCMD_MASK (3 << LMEM_PCCLCR_LCMD_SHIFT) +# define LMEM_PCCLCR_LCMD_SEARCH (0 << LMEM_PCCLCR_LCMD_SHIFT) /* Search and read or write */ +# define LMEM_PCCLCR_LCMD_INVLD (1 << LMEM_PCCLCR_LCMD_SHIFT) /* Invalidate */ +# define LMEM_PCCLCR_LCMD_PUSH (2 << LMEM_PCCLCR_LCMD_SHIFT) /* Push */ +# define LMEM_PCCLCR_LCMD_CLEAR (3 << LMEM_PCCLCR_LCMD_SHIFT) /* Clear */ +#define LMEM_PCCLCR_LADSEL (1 << 26) /* Bit 26: Line Address Select */ +# define LMEM_PCCLCR_LADSEL_CACHE (0) /* Cache address */ +# define LMEM_PCCLCR_LADSEL_PHYS (1 << 26) /* Physical address */ +#define LMEM_PCCLCR_LACC (1 << 27) /* Bit 27: Line access type */ +# define LMEM_PCCLCR_LACC_READ (0) /* Read */ +# define LMEM_PCCLCR_LACC_WRITE (1 << 27) /* Write */ + +/* Cache search address register */ + +#define LMEM_PCCSAR_LGO (1 << 0) /* Bit 0: Initiate Cache Line Command */ +#define LMEM_PCCSAR_PHYADDR_MASK (0xfffffffc) /* Bits 2-31: Physical Address (Bits 2-31) */ + +/* Cache read/write value register (32-bit data) */ + +/* Cache regions mode register */ + +#define LMEM_REGION_NONCACHEABLE 0 /* 0, 1: Non-cacheable */ +#define LMEM_REGION_WRITE_THROUGH 2 /* 2: Write-through */ +#define LMEM_REGION_WRITE_BACK 3 /* 3: Write-back */ + +#define LMEM_PCCRMR_REGION_SHIFT(n) ((15 - (n)) << 1) /* Region n mode, n=0-15 */ +#define LMEM_PCCRMR_REGION_MASK(n) (3 << LMEM_PCCRMR_REGION_SHIFT(n)) +# define LMEM_PCCRMR_REGION(n,m) ((uint32_t)(m) << LMEM_PCCRMR_REGION_SHIFT(n)) + +#endif /* CONFIG_S32K1XX_HAVE_LMEM */ +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LMEM_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h new file mode 100644 index 00000000000..6c37c386b5b --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h @@ -0,0 +1,250 @@ +/**************************************************************************************************** + * arch/arm/src/s32k1xx/chip/s32k1xx_mpu.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MPU_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MPU_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +#define S32K1XX_MPU_NSLAVE_PORTS 5 +#define S32K1XX_MPU_NREGIONS 16 + +/* MPU Register Offsets *****************************************************************************/ + +#define S32K1XX_MPU_CESR_OFFSET 0x000 /* Control/Error Status Register */ +#define S32K1XX_MPU_SLAVEPORT_OFFSET(s) (0x0010 + ((s) << 3)) /* Slave port s offset, s=0..4 */ +# define S32K1XX_MPU_EAR_OFFSET 0x0000 /* Slave port error address register */ +# define S32K1XX_MPU_EDR_OFFSET 0x0004 /* Slave port error detail register */ +#define S32K1XX_MPU_RGD_OFFSET(r) (0x0400 + ((r) << 4)) /* Region n descriptor */ +# define S32K1XX_MPU_RGD_WORD0_OFFSET 0x0000 /* Region n descriptor word 0 */ +# define S32K1XX_MPU_RGD_WORD1_OFFSET 0x0004 /* Region n descriptor word 1 */ +# define S32K1XX_MPU_RGD_WORD2_OFFSET 0x0008 /* Region n descriptor word 2 */ +# define S32K1XX_MPU_RGD_WORD3_OFFSET 0x000c /* Region n descriptor word 3 */ +#define S32K1XX_MPU_RGDAAC_OFFSET(r) (0x0800 + ((r) << 2)) /* Region n descriptor alternate access control */ + +/* MPU Register Addresses ***************************************************************************/ + +#define S32K1XX_MPU_CESR (S32K1XX_MPU_BASE + S32K1XX_MPU_CESR_OFFSET) +#define S32K1XX_MPU_SLAVEPORT_BASE(s) (S32K1XX_MPU_BASE + S32K1XX_MPU_SLAVEPORT_OFFSET(s)) +# define S32K1XX_MPU_EAR(s) (32K1XX_MPU_SLAVEPORT_BASE(s) + S32K1XX_MPU_EAR_OFFSET) +# define S32K1XX_MPU_EDR(s) (32K1XX_MPU_SLAVEPORT_BASE(s) + S32K1XX_MPU_EDR_OFFSET) +#define S32K1XX_MPU_RGD_BASE(r) (S32K1XX_MPU_BASE + S32K1XX_MPU_RGD_OFFSET(r)) +# define S32K1XX_MPU_RGD_WORD0(r) (S32K1XX_MPU_RGD_BASE(r) + S32K1XX_MPU_RGD_WORD0_OFFSET) +# define S32K1XX_MPU_RGD_WORD1(r) (S32K1XX_MPU_RGD_BASE(r) + S32K1XX_MPU_RGD_WORD1_OFFSET) +# define S32K1XX_MPU_RGD_WORD2(r) (S32K1XX_MPU_RGD_BASE(r) + S32K1XX_MPU_RGD_WORD2_OFFSET) +# define S32K1XX_MPU_RGD_WORD3(r) (S32K1XX_MPU_RGD_BASE(r) + S32K1XX_MPU_RGD_WORD3_OFFSET) +#define S32K1XX_MPU_RGDAAC(r) (S32K1XX_MPU_BASE + S32K1XX_MPU_RGDAAC_OFFSET(r)) + +/* MPU Register Bitfield Definitions ****************************************************************/ + +/* Control/Error Status Register */ + +#define MPU_CESR_VLD (1 << 0) /* Bit 0: Valid */ +#define MPU_CESR_NRGD_SHIFT (8) /* Bits 8-11: Number Of Region Descriptors */ +#define MPU_CESR_NRGD_MASK (15 << MPU_CESR_NRGD_SHIFT) +# define MPU_CESR_NRGD_8 (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */ +# define MPU_CESR_NRGD_12 (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */ +# define MPU_CESR_NRGD_16 (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */ +#define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number Of Slave Ports */ +#define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT) +#define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware Revision Level */ +#define MPU_CESR_HRL_MASK (15 << MPU_CESR_HRL_SHIFT) +#define MPU_CESR_SPERR4 (1 << 27) /* Bit 27: Slave Port 4 Error */ +#define MPU_CESR_SPERR3 (1 << 28) /* Bit 28: Slave Port 3 Error */ +#define MPU_CESR_SPERR2 (1 << 29) /* Bit 29: Slave Port 2 Error */ +#define MPU_CESR_SPERR1 (1 << 30) /* Bit 30: Slave Port 1 Error */ +#define MPU_CESR_SPERR0 (1 << 31) /* Bit 31: Slave Port 0 Error */ + +/* Slave port error address register (32-bit error address) */ + +/* Slave port error detail register */ + +#define MPU_EDR_ERW (1 << 0) /* Bit 0: Error Read/Write */ +# define MPU_EDR_ERW_READ (0) /* Read */ +# define MPU_EDR_ERW_WRITE (1 << 0) /* Write */ +#define MPU_EDR_EATTR_SHIFT (1) /* Bits 1-3: Error Attributes */ +#define MPU_EDR_EATTR_MASK (7 << MPU_EDR_EATTR_SHIFT) +# define MPU_EDR_EATTR_IUSER (0 << MPU_EDR_EATTR_SHIFT) /* User mode, instruction access */ +# define MPU_EDR_EATTR_DUSER (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */ +# define MPU_EDR_EATTR_ISUPER (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */ +# define MPU_EDR_EATTR_DSUPER (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */ +#define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error Master Number */ +#define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT) +#define MPU_EDR_EPID_SHIFT (8) /* Bits 8-15: Error Process Identification */ +#define MPU_EDR_EPID_MASK (0xff << MPU_EDR_EPID_SHIFT) +#define MPU_EDR_EACD_SHIFT (16) /* Bits 16-31: Error Access Control Detail */ +#define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT) + +/* Region n descriptor word 0 */ + +#define MPU_RGD_WORD0_SRTADDR_MASK 0xffffffe0 /* Bits 5-31: Start Address bits 5-31 */ + +/* Region n descriptor word 1 */ + +#define MPU_RGD_WORD1_ENDADDR_MASK 0xffffffe0 /* Bits 5-31: End Address bits 5-31 */ + +/* Region n descriptor word 2 */ + +#define MPU_RGD_WORD2_M0UM_SHIFT (0) /* Bits 0-2: Bus Master 0 User Mode Access Control */ +#define MPU_RGD_WORD2_M0UM_MASK (7 << MPU_RGD_WORD2_M0UM_SHIFT) +# define MPU_RGD_WORD2_M0UM_XACCESS (1 << MPU_RGD_WORD2_M0UM_SHIFT) +# define MPU_RGD_WORD2_M0UM_WACCESS (2 << MPU_RGD_WORD2_M0UM_SHIFT) +# define MPU_RGD_WORD2_M0UM_RACCESS (4 << MPU_RGD_WORD2_M0UM_SHIFT) +#define MPU_RGD_WORD2_M0SM_SHIFT (3) /* Bits 3-4: Bus Master 0 Supervisor Mode Access Control */ +#define MPU_RGD_WORD2_M0SM_MASK (3 << MPU_RGD_WORD2_M0SM_SHIFT) +# define MPU_RGD_WORD2_M0SM_RWX (0 << MPU_RGD_WORD2_M0SM_SHIFT) /* Read, write and execute allowed */ +# define MPU_RGD_WORD2_M0SM_RX (1 << MPU_RGD_WORD2_M0SM_SHIFT) /* Read and execute allowed */ +# define MPU_RGD_WORD2_M0SM_RW (2 << MPU_RGD_WORD2_M0SM_SHIFT) /* Read and write allowed */ +# define MPU_RGD_WORD2_M0SM_M0UM (3 << MPU_RGD_WORD2_M0SM_SHIFT) /* Same as User mode defined in M0UM */ +#define MPU_RGD_WORD2_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier enable */ +#define MPU_RGD_WORD2_M1UM_SHIFT (6) /* Bits 6-8: Bus Master 1 User Mode Access Control */ +#define MPU_RGD_WORD2_M1UM_MASK (7 << MPU_RGD_WORD2_M1UM_SHIFT) +# define MPU_RGD_WORD2_M1UM_XACCESS (1 << MPU_RGD_WORD2_M1UM_SHIFT) +# define MPU_RGD_WORD2_M1UM_WACCESS (2 << MPU_RGD_WORD2_M1UM_SHIFT) +# define MPU_RGD_WORD2_M1UM_RACCESS (4 << MPU_RGD_WORD2_M1UM_SHIFT) +#define MPU_RGD_WORD2_M1SM_SHIFT (9) /* Bits 9-10: Bus Master 1 Supervisor Mode Access Control */ +#define MPU_RGD_WORD2_M1SM_MASK (3 << MPU_RGD_WORD2_M1SM_SHIFT) +# define MPU_RGD_WORD2_M1SM_RWX (0 << MPU_RGD_WORD2_M1SM_SHIFT) /* Read, write and execute allowed */ +# define MPU_RGD_WORD2_M1SM_RX (1 << MPU_RGD_WORD2_M1SM_SHIFT) /* Read and execute allowed */ +# define MPU_RGD_WORD2_M1SM_RW (2 << MPU_RGD_WORD2_M1SM_SHIFT) /* Read and write allowed */ +# define MPU_RGD_WORD2_M1SM_M1UM (3 << MPU_RGD_WORD2_M1SM_SHIFT) /* Same as User mode defined in M1UM */ +#define MPU_RGD_WORD2_M1PE (1 << 11) /* Bit 11: Bus Master 1 Process Identifier enable */ +#define MPU_RGD_WORD2_M2UM_SHIFT (12) /* Bits 12-14: Bus Master 2 User Mode Access control */ +#define MPU_RGD_WORD2_M2UM_MASK (7 << MPU_RGD_WORD2_M2UM_SHIFT) +# define MPU_RGD_WORD2_M2UM_XACCESS (1 << MPU_RGD_WORD2_M2UM_SHIFT) +# define MPU_RGD_WORD2_M2UM_WACCESS (2 << MPU_RGD_WORD2_M2UM_SHIFT) +# define MPU_RGD_WORD2_M2UM_RACCESS (4 << MPU_RGD_WORD2_M2UM_SHIFT) +#define MPU_RGD_WORD2_M2SM_SHIFT (15) /* Bits 15-16: Bus Master 2 Supervisor Mode Access Control */ +#define MPU_RGD_WORD2_M2SM_MASK (3 << MPU_RGD_WORD2_M2SM_SHIFT) +# define MPU_RGD_WORD2_M2SM_RWX (0 << MPU_RGD_WORD2_M2SM_SHIFT) /* Read, write and execute allowed */ +# define MPU_RGD_WORD2_M2SM_RX (1 << MPU_RGD_WORD2_M2SM_SHIFT) /* Read and execute allowed */ +# define MPU_RGD_WORD2_M2SM_RW (2 << MPU_RGD_WORD2_M2SM_SHIFT) /* Read and write allowed */ +# define MPU_RGD_WORD2_M2SM_M2UM (3 << MPU_RGD_WORD2_M2SM_SHIFT) /* Same as User mode defined in M2UM */ +#define MPU_RGD_WORD2_M3UM_SHIFT (18) /* Bits 18-20: Bus Master 3 User Mode Access Control */ +#define MPU_RGD_WORD2_M3UM_MASK (7 << MPU_RGD_WORD2_M3UM_SHIFT) +# define MPU_RGD_WORD2_M3UM_XACCESS (1 << MPU_RGD_WORD2_M3UM_SHIFT) +# define MPU_RGD_WORD2_M3UM_WACCESS (2 << MPU_RGD_WORD2_M3UM_SHIFT) +# define MPU_RGD_WORD2_M3UM_RACCESS (4 << MPU_RGD_WORD2_M3UM_SHIFT) +#define MPU_RGD_WORD2_M3SM_SHIFT (21) /* Bits 21-22: Bus Master 3 Supervisor Mode Access Control */ +#define MPU_RGD_WORD2_M3SM_MASK (3 << MPU_RGD_WORD2_M3SM_SHIFT) +# define MPU_RGD_WORD2_M3SM_RWX (0 << MPU_RGD_WORD2_M3SM_SHIFT) /* Read, write and execute allowed */ +# define MPU_RGD_WORD2_M3SM_RX (1 << MPU_RGD_WORD2_M3SM_SHIFT) /* Read and execute allowed */ +# define MPU_RGD_WORD2_M3SM_RW (2 << MPU_RGD_WORD2_M3SM_SHIFT) /* Read and write allowed */ +# define MPU_RGD_WORD2_M3SM_M3UM (3 << MPU_RGD_WORD2_M3SM_SHIFT) /* Same as User mode defined in M3UM */ +#define MPU_RGD_WORD2_M4WE (1 << 24) /* Bit 24: Bus Master 4 Write Enable */ +#define MPU_RGD_WORD2_M4RE (1 << 25) /* Bit 25: Bus Master 4 Read Enable */ +#define MPU_RGD_WORD2_M5RE (1 << 27) /* Bit 27: Bus Master 5 Read Enable */ +#define MPU_RGD_WORD2_M6WE (1 << 28) /* Bit 28: Bus Master 6 Write Enable */ +#define MPU_RGD_WORD2_M6RE (1 << 29) /* Bit 29: Bus Master 6 Read Enable */ +#define MPU_RGD_WORD2_M7WE (1 << 30) /* Bit 30: Bus Master 7 Write Enable */ +#define MPU_RGD_WORD2_M7RE (1 << 31) /* Bit 31: Bus Master 7 Read Enable */ + +/* Region n descriptor word 3 */ + +#define MPU_RGD_WORD3_VLD (1 << 0) /* Bit 0: Valid */ +#define MPU_RGD_WORD3_PIDMASK_SHIFT (16) /* Bits 16-23: Process Identifier Mask */ +#define MPU_RGD_WORD3_PIDMASK_MASK (0xff << MPU_RGD_WORD3_PIDMASK_SHIFT) +# define MPU_RGD_WORD3_PIDMASK(n) ((uint32_t)(n) << MPU_RGD_WORD3_PIDMASK_SHIFT) +#define MPU_RGD_WORD3_PID_SHIFT (24) /* Bits 24-31: Process Identifier */ +#define MPU_RGD_WORD3_PID_MASK (0xff << MPU_RGD_WORD3_PID_SHIFT) +# define MPU_RGD_WORD3_PID(n) ((uint32_t)(n) << MPU_RGD_WORD3_PID_SHIFT) + +/* Region n descriptor alternate access control */ +#define MPU_RGDAAC_ + +#define MPU_RGDAAC_M0UM_SHIFT (0) /* Bits 0-2: Bus Master 0 User Mode Access Control */ +#define MPU_RGDAAC_M0UM_MASK (7 << MPU_RGDAAC_M0UM_SHIFT) +# define MPU_RGDAAC_M0UM_XACCESS (1 << MPU_RGDAAC_M0UM_SHIFT) +# define MPU_RGDAAC_M0UM_WACCESS (2 << MPU_RGDAAC_M0UM_SHIFT) +# define MPU_RGDAAC_M0UM_RACCESS (4 << MPU_RGDAAC_M0UM_SHIFT) +#define MPU_RGDAAC_M0SM_SHIFT (3) /* Bits 3-4: Bus Master 0 Supervisor Mode Access Control */ +#define MPU_RGDAAC_M0SM_MASK (3 << MPU_RGDAAC_M0SM_SHIFT) +# define MPU_RGDAAC_M0SM_RWX (0 << MPU_RGDAAC_M0SM_SHIFT) /* Read, write and execute allowed */ +# define MPU_RGDAAC_M0SM_RX (1 << MPU_RGDAAC_M0SM_SHIFT) /* Read and execute allowed */ +# define MPU_RGDAAC_M0SM_RW (2 << MPU_RGDAAC_M0SM_SHIFT) /* Read and write allowed */ +# define MPU_RGDAAC_M0SM_M0UM (3 << MPU_RGDAAC_M0SM_SHIFT) /* Same as User mode defined in M0UM */ +#define MPU_RGDAAC_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier enable */ +#define MPU_RGDAAC_M1UM_SHIFT (6) /* Bits 6-8: Bus Master 1 User Mode Access Control */ +#define MPU_RGDAAC_M1UM_MASK (7 << MPU_RGDAAC_M1UM_SHIFT) +# define MPU_RGDAAC_M1UM_XACCESS (1 << MPU_RGDAAC_M1UM_SHIFT) +# define MPU_RGDAAC_M1UM_WACCESS (2 << MPU_RGDAAC_M1UM_SHIFT) +# define MPU_RGDAAC_M1UM_RACCESS (4 << MPU_RGDAAC_M1UM_SHIFT) +#define MPU_RGDAAC_M1SM_SHIFT (9) /* Bits 9-10: Bus Master 1 Supervisor Mode Access Control */ +#define MPU_RGDAAC_M1SM_MASK (3 << MPU_RGDAAC_M1SM_SHIFT) +# define MPU_RGDAAC_M1SM_RWX (0 << MPU_RGDAAC_M1SM_SHIFT) /* Read, write and execute allowed */ +# define MPU_RGDAAC_M1SM_RX (1 << MPU_RGDAAC_M1SM_SHIFT) /* Read and execute allowed */ +# define MPU_RGDAAC_M1SM_RW (2 << MPU_RGDAAC_M1SM_SHIFT) /* Read and write allowed */ +# define MPU_RGDAAC_M1SM_M1UM (3 << MPU_RGDAAC_M1SM_SHIFT) /* Same as User mode defined in M1UM */ +#define MPU_RGDAAC_M1PE (1 << 11) /* Bit 11: Bus Master 1 Process Identifier enable */ +#define MPU_RGDAAC_M2UM_SHIFT (12) /* Bits 12-14: Bus Master 2 User Mode Access control */ +#define MPU_RGDAAC_M2UM_MASK (7 << MPU_RGDAAC_M2UM_SHIFT) +# define MPU_RGDAAC_M2UM_XACCESS (1 << MPU_RGDAAC_M2UM_SHIFT) +# define MPU_RGDAAC_M2UM_WACCESS (2 << MPU_RGDAAC_M2UM_SHIFT) +# define MPU_RGDAAC_M2UM_RACCESS (4 << MPU_RGDAAC_M2UM_SHIFT) +#define MPU_RGDAAC_M2SM_SHIFT (15) /* Bits 15-16: Bus Master 2 Supervisor Mode Access Control */ +#define MPU_RGDAAC_M2SM_MASK (3 << MPU_RGDAAC_M2SM_SHIFT) +# define MPU_RGDAAC_M2SM_RWX (0 << MPU_RGDAAC_M2SM_SHIFT) /* Read, write and execute allowed */ +# define MPU_RGDAAC_M2SM_RX (1 << MPU_RGDAAC_M2SM_SHIFT) /* Read and execute allowed */ +# define MPU_RGDAAC_M2SM_RW (2 << MPU_RGDAAC_M2SM_SHIFT) /* Read and write allowed */ +# define MPU_RGDAAC_M2SM_M2UM (3 << MPU_RGDAAC_M2SM_SHIFT) /* Same as User mode defined in M2UM */ +#define MPU_RGDAAC_M3UM_SHIFT (18) /* Bits 18-20: Bus Master 3 User Mode Access Control */ +#define MPU_RGDAAC_M3UM_MASK (7 << MPU_RGDAAC_M3UM_SHIFT) +# define MPU_RGDAAC_M3UM_XACCESS (1 << MPU_RGDAAC_M3UM_SHIFT) +# define MPU_RGDAAC_M3UM_WACCESS (2 << MPU_RGDAAC_M3UM_SHIFT) +# define MPU_RGDAAC_M3UM_RACCESS (4 << MPU_RGDAAC_M3UM_SHIFT) +#define MPU_RGDAAC_M3SM_SHIFT (21) /* Bits 21-22: Bus Master 3 Supervisor Mode Access Control */ +#define MPU_RGDAAC_M3SM_MASK (3 << MPU_RGDAAC_M3SM_SHIFT) +# define MPU_RGDAAC_M3SM_RWX (0 << MPU_RGDAAC_M3SM_SHIFT) /* Read, write and execute allowed */ +# define MPU_RGDAAC_M3SM_RX (1 << MPU_RGDAAC_M3SM_SHIFT) /* Read and execute allowed */ +# define MPU_RGDAAC_M3SM_RW (2 << MPU_RGDAAC_M3SM_SHIFT) /* Read and write allowed */ +# define MPU_RGDAAC_M3SM_M3UM (3 << MPU_RGDAAC_M3SM_SHIFT) /* Same as User mode defined in M3UM */ +#define MPU_RGDAAC_M4WE (1 << 24) /* Bit 24: Bus Master 4 Write Enable */ +#define MPU_RGDAAC_M4RE (1 << 25) /* Bit 25: Bus Master 4 Read Enable */ +#define MPU_RGDAAC_M5RE (1 << 27) /* Bit 27: Bus Master 5 Read Enable */ +#define MPU_RGDAAC_M6WE (1 << 28) /* Bit 28: Bus Master 6 Write Enable */ +#define MPU_RGDAAC_M6RE (1 << 29) /* Bit 29: Bus Master 6 Read Enable */ +#define MPU_RGDAAC_M7WE (1 << 30) /* Bit 30: Bus Master 7 Write Enable */ +#define MPU_RGDAAC_M7RE (1 << 31) /* Bit 31: Bus Master 7 Read Enable */ + +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MPU_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h index b1f5054fc46..fe20bdb4319 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h @@ -31,6 +31,25 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * + * Some of the definitions within this file derive from NXP sample code for + * the S32K1xx MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * ************************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_WDOG_H @@ -97,6 +116,27 @@ #define WDOG_CNT_CNTHIGH_SHIFT (8) /* Bits 8-15: High byte of the Watchdog Counter */ #define WDOG_CNT_CNTHIGH_MASK (0xff << WDOG_CNT_CNTHIGH_SHIFT) +/* The refresh write sequence can be either: + * + * If WDOG_CS[CMD32EN] is 0: + * 1) Two 16-bit writes: 0xa602, 0xb480 + * 2) Four 8-bit writes: 0xa6, 0x02, 0xb4, 0x80 + * If WDOG_CS[CMD32EN] is 1: + * 3) One 32-bit write (0xb480a602) + */ + +#define WDOG_CNT_REFRESH_HWORD1 0xa602 +#define WDOG_CNT_REFRESH_HWORD2 0xb480 +#define WDOG_CNT_REFRESH_BYTE1 0xa6 +#define WDOG_CNT_REFRESH_BYTE2 0x02 +#define WDOG_CNT_REFRESH_BYTE3 0xb4 +#define WDOG_CNT_REFRESH_BYTE4 0x80 +#define WDOG_CNT_REFRESH_DWORD 0xb480a602 + +/* Value to unlock the watchdog registers */ + +#define WDOG_CNT_UNLOCK 0xd928c520 + /* Watchdog Timeout Value Register */ #define WDOG_TOVAL_TOVALLOW_SHIFT (0) /* Bits 0-7: Low byte of the timeout value */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c index bae5f81b839..344f2428e17 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c +++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c @@ -620,10 +620,15 @@ s32k1xx_transition_systemclock(const struct scg_system_clock_config_s *cfg) ret = s32k1xx_set_sysclk_configuration(run_mode, cfg); if (ret == OK) { - /* Wait for system clock to transition. */ + /* Wait for system clock to transition. + * + * e10777: The SCG_RCCR[SCS] and SCG_HCCR[SCS] may have a corrupted + * status during the interval when the system clock is switching. + * Workaround: The SCS field should be read twice by the software to + * ensure the system clock switch has completed. + */ -#warning REVISIT -#ifdef ERRATA_E10777 +#if 1 /* Errata E10777 */ timeout = 10; #else timeout = 1; diff --git a/arch/arm/src/s32k1xx/s32k1xx_idle.c b/arch/arm/src/s32k1xx/s32k1xx_idle.c new file mode 100644 index 00000000000..1c8f448356c --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_idle.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/arm/src/s32k1xx/s32k1xx_idle.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} diff --git a/arch/arm/src/s32k1xx/s32k1xx_lowputc.c b/arch/arm/src/s32k1xx/s32k1xx_lowputc.c index 47a5ea63818..039e3e60223 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lowputc.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lowputc.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "up_arch.h" @@ -378,10 +379,9 @@ int s32k1xx_lpuart_configure(uint32_t base, } else { - /* Here should be added support of other bit modes. */ + /* REVISIT: Here should be added support of other bit modes. */ -#warning missing logic - return ERROR; + return -ENOSYS; } regval |= LPUART_CTRL_RE | LPUART_CTRL_TE; diff --git a/arch/arm/src/s32k1xx/s32k1xx_pingpio.c b/arch/arm/src/s32k1xx/s32k1xx_pingpio.c new file mode 100644 index 00000000000..95de4bb1cae --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_pingpio.c @@ -0,0 +1,135 @@ +/**************************************************************************** + * arch/arm/src/s32k1xx/s32k1xx_pingpio.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "up_arch.h" +#include "hardware/s32k1xx_gpio.h" +#include "s32k1xx_pin.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void s32k1xx_gpiowrite(uint32_t pinset, bool value) +{ + uintptr_t base; + unsigned int port; + unsigned int pin; + + DEBUGASSERT((pinset & _PIN_MODE_MASK) == _PIN_MODE_GPIO); + DEBUGASSERT((pinset & _PIN_IO_MASK) == _PIN_OUTPUT); + + /* Get the port number and pin number */ + + port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; + pin = (pinset & _PIN_MASK) >> _PIN_SHIFT; + + DEBUGASSERT(port < S32K1XX_NPORTS); + if (port < S32K1XX_NPORTS) + { + /* Get the base address of GPIO block for this port */ + + base = S32K1XX_GPIO_BASE(port); + + /* Set or clear the output */ + + if (value) + { + putreg32((1 << pin), base + S32K1XX_GPIO_PSOR_OFFSET); + } + else + { + putreg32((1 << pin), base + S32K1XX_GPIO_PCOR_OFFSET); + } + } +} + +/**************************************************************************** + * Name: s32k1xx_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool s32k1xx_gpioread(uint32_t pinset) +{ + uintptr_t base; + uint32_t regval; + unsigned int port; + unsigned int pin; + bool ret = false; + + DEBUGASSERT((pinset & _PIN_MODE_MASK) == _PIN_MODE_GPIO); + DEBUGASSERT((pinset & _PIN_IO_MASK) == _PIN_INPUT); + + /* Get the port number and pin number */ + + port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; + pin = (pinset & _PIN_MASK) >> _PIN_SHIFT; + + DEBUGASSERT(port < S32K1XX_NPORTS); + if (port < S32K1XX_NPORTS) + { + /* Get the base address of GPIO block for this port */ + + base = S32K1XX_GPIO_BASE(port); + + /* return the state of the pin */ + + regval = getreg32(base + S32K1XX_GPIO_PDIR_OFFSET); + ret = ((regval & (1 << pin)) != 0); + } + return ret; +} + diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c index c8ae72fed6e..de1d73a6ed0 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_start.c +++ b/arch/arm/src/s32k1xx/s32k1xx_start.c @@ -51,15 +51,48 @@ # include "s32k1xx_userspace.h" #endif +#include "hardware/s32k1xx_lmem.h" #include "s32k1xx_clockconfig.h" #include "s32k1xx_lowputc.h" #include "s32k1xx_serial.h" +#include "s32k1xx_wdog.h" #include "s32k1xx_start.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Memory Map ***************************************************************/ + +/* 0x0000:0000 - Beginning of the internal FLASH. Address of vectors. + * Mapped as boot memory address 0x0000:0000 at reset. + * 0x07ff:ffff - End of flash region (assuming the max of 2MiB of FLASH). + * 0x1000:0000 - Start of internal SRAM and start of .data (_sdata) + * + * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. + * The RAM is implemented such that the SRAM_L and SRAM_U + * ranges form a contiguous block in the memory map. Thus, the + * actual SRAM start address is SAM_L which some MCU-specific + * value in the range 0x1000:0000 and 0x1fff:ffff. SRAM_U + * then always starts at 0x2000:0000 + + * - End of .data (_edata) and start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, + * start of heap. NOTE that the ARM uses a decrement before + * store stack so that the correct initial value is the end of + * the stack + 4; + * 0x2fff:ffff - End of internal SRAM and end of heap. The actual end of + * SRAM_U will depend on the amount of memory supported by the + * MCU/ + * + * NOTE: ARM EABI requires 64 bit stack alignment. + */ + +#define IDLE_STACKSIZE (CONFIG_IDLETHREAD_STACKSIZE & ~7) +#define IDLE_STACK ((uintptr_t)&_ebss + IDLE_STACKSIZE) +#define HEAP_BASE ((uintptr_t)&_ebss + IDLE_STACKSIZE) + /**************************************************************************** * Name: showprogress * @@ -74,12 +107,28 @@ # define showprogress(c) #endif +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ + +const uintptr_t g_idle_topstack = HEAP_BASE; + /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: s32k1xx_fpuconfig + * Name: s32k1xx_fpu_config * * Description: * Configure the FPU. Relative bit settings: @@ -103,7 +152,7 @@ #ifdef CONFIG_ARCH_FPU #ifndef CONFIG_ARMV7M_LAZYFPU -static inline void s32k1xx_fpuconfig(void) +static inline void s32k1xx_fpu_config(void) { uint32_t regval; @@ -131,7 +180,7 @@ static inline void s32k1xx_fpuconfig(void) putreg32(regval, NVIC_CPACR); } #else -static inline void s32k1xx_fpuconfig(void) +static inline void s32k1xx_fpu_config(void) { uint32_t regval; @@ -161,7 +210,31 @@ static inline void s32k1xx_fpuconfig(void) #endif #else -# define s32k1xx_fpuconfig() +# define s32k1xx_fpu_config() +#endif + +/**************************************************************************** + * Name: s32k1xx_mpu_config + * + * Description: + * Enable all bus masters. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET) +static inline void s32k1xx_mpu_config(void) +{ + uint32_t regval; + + /* Bus masters 0-2 are already enabled r/w/x in supervisor and user modes + * after reset. Enable also bus master 3 (ENET) in S/U modes in default + * region 0: User=r+w+x, Supervisor=same as used. + */ + + regval = (MPU_RGDAAC_M3UM_XACCESS | MPU_RGDAAC_M3UM_WACCESS | + MPU_RGDAAC_M3UM_RACCESS | MPU_RGDAAC_M3SM_M3UM; + putreg32(regval, S32K1XX_MPU_RGDAAC(0)); +} #endif /**************************************************************************** @@ -194,6 +267,20 @@ void __start(void) s32k1xx_lowsetup(); showprogress('A'); +#ifdef CONFIG_S32K1XX_WDT_DISABLE + /* Disable the watchdog timer */ + + s32k1xx_wdog_disable(); + showprogress('B'); +#endif + +#ifdef CONFIG_S32K1XX_HAVE_LMEM + /* Initialize the cache (if supported) */ + + s32k1xx_cache_config(); + showprogress('C'); +#endif + /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ @@ -203,7 +290,7 @@ void __start(void) *dest++ = 0; } - showprogress('B'); + showprogress('D'); /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is @@ -216,19 +303,27 @@ void __start(void) *dest++ = *src++; } - showprogress('C'); + showprogress('E'); /* Initialize the FPU (if configured) */ - s32k1xx_fpuconfig(); - showprogress('D'); + s32k1xx_fpu_config(); + showprogress('F'); + +#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET) + /* Enable all MPU bus masters */ + + s32k1xx_mpu_config(); + showprogress('G'); +} +#endif /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT s32k1xx_earlyserialinit(); #endif - showprogress('E'); + showprogress('H'); /* For the case of the separate user-/kernel-space build, perform whatever * platform specific initialization of the user memory is required. @@ -238,13 +333,13 @@ void __start(void) #ifdef CONFIG_BUILD_PROTECTED s32k1xx_userspace(); - showprogress('F'); + showprogress('I'); #endif /* Initialize onboard resources */ s32k1xx_board_initialize(); - showprogress('G'); + showprogress('J'); /* Then start NuttX */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_wdog.h b/arch/arm/src/s32k1xx/s32k1xx_wdog.h new file mode 100644 index 00000000000..63c58137b44 --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_wdog.h @@ -0,0 +1,127 @@ +/**************************************************************************** + * arch/arm/src/s32k1xx/s32k1xx_wdog.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_WDOG_H +#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_WDOG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" +#include "hardware/s32k1xx_wdog.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: s32k1xx_wdog_disable + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during boot-up. This must be called + * before up_serialinit. + * + * REVISIT: Hardcoded assumption that WDOG clock derives for LPO_CLK + * + ****************************************************************************/ + +static inline void s32k1xx_wdog_disable(void) +{ + uint32_t regval; + + /* Write of the WDOG unlock key to CNT register. This must be done in + * order to allow any modifications to the WDOG configuration. + */ + + putreg32(WDOG_CNT_UNLOCK, S32K1XX_WDOG_CNT); + + /* The dummy read is used in order to make sure that the WDOG registers + * will be configured only after the write of the unlock value was + * completed. + */ + + (void)getreg32(S32K1XX_WDOG_CNT); + + /* Initial write of WDOG configuration register: Enables support for + * 32-bit refresh/unlock command write words, clock select from LPO, + * update enable, watchdog disabled. + */ + + regval = (WDOG_CS_CMD32EN | WDOG_CS_CLK_LPOCLK |WDOG_CS_UPDATE); + putreg32(regval, S32K1XX_WDOG_CNT); + + /* Configure timeout to the maximum: */ + + putreg32(0xffff, S32K1XX_WDOG_TOVAL); +} + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_WDOG_H */ diff --git a/boards/arm/s32k1xx/s32k118evb/scripts/flash.ld b/boards/arm/s32k1xx/s32k118evb/scripts/flash.ld index 0e89d0e070c..a6af6a403ae 100644 --- a/boards/arm/s32k1xx/s32k118evb/scripts/flash.ld +++ b/boards/arm/s32k1xx/s32k118evb/scripts/flash.ld @@ -42,6 +42,7 @@ * * SRAM_L 1ffffc00 - 1fffffff 1Kb * SRAM_U 20000000 - 200057ff 22Kb + */ MEMORY {