diff --git a/arch/arm/src/lc823450/lc823450_dma.c b/arch/arm/src/lc823450/lc823450_dma.c
index 916a7a9182c..b228f706d54 100644
--- a/arch/arm/src/lc823450/lc823450_dma.c
+++ b/arch/arm/src/lc823450/lc823450_dma.c
@@ -150,9 +150,11 @@ static int dma_interrupt_core(void *context)
   struct lc823450_phydmach_s *pdmach;
   struct lc823450_dmach_s *dmach;
   sq_entry_t *q_ent;
+  irqstate_t flags;
 
   pdmach = (struct lc823450_phydmach_s *)context;
 
+  flags = spin_lock_irqsave();
   q_ent = pdmach->req_q.tail;
   DEBUGASSERT(q_ent);
   dmach = (struct lc823450_dmach_s *)q_ent;
@@ -160,11 +162,17 @@ static int dma_interrupt_core(void *context)
   if (dmach->nxfrs == 0)
     {
       /* finish one transfer */
+
       sq_remlast(&pdmach->req_q);
+      spin_unlock_irqrestore(flags);
 
       if (dmach->callback)
         dmach->callback((DMA_HANDLE)dmach, dmach->arg, 0);
     }
+  else
+    {
+      spin_unlock_irqrestore(flags);
+    }
 
   up_disable_clk(LC823450_CLOCK_DMA);
   phydmastart(pdmach);
diff --git a/arch/arm/src/lc823450/lc823450_gpio.c b/arch/arm/src/lc823450/lc823450_gpio.c
index dde194ac837..bb8aab5d3cb 100644
--- a/arch/arm/src/lc823450/lc823450_gpio.c
+++ b/arch/arm/src/lc823450/lc823450_gpio.c
@@ -54,10 +54,6 @@
 #  include <nuttx/ioex.h>
 #endif
 
-#ifdef CONFIG_SMP
-#  include <nuttx/spinlock.h>
-#endif
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -79,10 +75,6 @@ static FAR struct ioex_dev_s *g_ioex_dev;
 static FAR struct vgpio_ops_s *vgpio_ops[GPIO_VIRTUAL_NUM];
 #endif /* CONFIG_LC823450_VGPIO */
 
-#ifdef CONFIG_SMP
-static volatile spinlock_t g_gpio_lock;
-#endif
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -247,12 +239,12 @@ int lc823450_gpio_mux(uint16_t gpiocfg)
 
   if (port <= (GPIO_PORT5 >> GPIO_PORT_SHIFT))
     {
-      irqstate_t flags = enter_critical_section();
+      irqstate_t flags = spin_lock_irqsave();
       val = getreg32(PMDCNT0 + (port * 4));
       val &= ~(3 << (2 * pin));
       val |= (mux << (2 *pin));
       putreg32(val, PMDCNT0 + (port * 4));
-      leave_critical_section(flags);
+      spin_unlock_irqrestore(flags);
     }
   else
     {
@@ -295,7 +287,7 @@ int lc823450_gpio_config(uint16_t gpiocfg)
 
       /* Handle the GPIO configuration by the basic mode of the pin */
 
-      flags = enter_critical_section();
+      flags = spin_lock_irqsave();
 
       /* pull up/down specified */
 
@@ -320,7 +312,7 @@ int lc823450_gpio_config(uint16_t gpiocfg)
             break;
         }
 
-      leave_critical_section(flags);
+      spin_unlock_irqrestore(flags);
     }
 #ifdef CONFIG_IOEX
   else if (port <= (GPIO_PORTEX >> GPIO_PORT_SHIFT))
@@ -408,12 +400,7 @@ void lc823450_gpio_write(uint16_t gpiocfg, bool value)
 
       regaddr = lc823450_get_gpio_data(port);
 
-#ifdef CONFIG_SMP
-      flags = up_irq_save();
-      spin_lock(&g_gpio_lock);
-#else
-      flags = enter_critical_section();
-#endif
+      flags = spin_lock_irqsave();
 
       /* Write the value (0 or 1).  To the data register */
 
@@ -430,12 +417,7 @@ void lc823450_gpio_write(uint16_t gpiocfg, bool value)
 
       putreg32(regval, regaddr);
 
-#ifdef CONFIG_SMP
-      spin_unlock(&g_gpio_lock);
-      up_irq_restore(flags);
-#else
-      leave_critical_section(flags);
-#endif
+      spin_unlock_irqrestore(flags);
   }
 #ifdef CONFIG_IOEX
   else if (port <= (GPIO_PORTEX >> GPIO_PORT_SHIFT))
diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c
index 46e81330a40..52b8b4c2893 100644
--- a/arch/arm/src/lc823450/lc823450_irq.c
+++ b/arch/arm/src/lc823450/lc823450_irq.c
@@ -632,6 +632,7 @@ void up_enable_irq(int irq)
   uintptr_t regaddr;
   uint32_t regval;
   uint32_t bit;
+  irqstate_t flags;
 
 #ifdef CONFIG_LC823450_VIRQ
   if (irq >= LC823450_IRQ_VIRTUAL &&
@@ -657,6 +658,8 @@ void up_enable_irq(int irq)
        * set the bit in the System Handler Control and State Register.
        */
 
+      flags = spin_lock_irqsave();
+
       if (irq >= LC823450_IRQ_NIRQS)
         {
           /* Clear already asserted IRQ */
@@ -677,6 +680,8 @@ void up_enable_irq(int irq)
           regval |= bit;
           putreg32(regval, regaddr);
         }
+
+      spin_unlock_irqrestore(flags);
     }
 
   /* lc823450_dumpnvic("enable", irq); */
@@ -697,12 +702,19 @@ void up_ack_irq(int irq)
       return;
     }
 
-  board_autoled_on(LED_CPU0 + up_cpu_index());
-
 #ifdef CONFIG_DVFS
   lc823450_dvfs_exit_idle(irq);
 #endif
 
+  board_autoled_on(LED_CPU0 + up_cpu_index());
+
+#ifdef CONFIG_SMP
+  if (irq > LC823450_IRQ_LPDSP0 && 1 == up_cpu_index())
+    {
+      irqwarn("*** warning irq(%d) handled on CPU1.");
+    }
+#endif
+
 #ifdef CONFIG_LC823450_SLEEP_MODE
   extern void up_update_idle_time(void);
   up_update_idle_time();
@@ -798,7 +810,7 @@ int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype)
   port = (irq & 0x70) >> 4;
   gpio = irq & 0xf;
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave();
 
   regaddr = INTC_REG(EXTINTnCND_BASE, port);
   regval = getreg32(regaddr);
@@ -808,7 +820,7 @@ int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype)
 
   putreg32(regval, regaddr);
 
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(flags);
 
   return OK;
 }
diff --git a/arch/arm/src/lc823450/lc823450_pwm.h b/arch/arm/src/lc823450/lc823450_pwm.h
new file mode 100644
index 00000000000..1c364f86e25
--- /dev/null
+++ b/arch/arm/src/lc823450/lc823450_pwm.h
@@ -0,0 +1,115 @@
+/****************************************************************************
+ * arch/arm/src/lc823450/lc823450_pwm.h
+ *
+ *   Copyright (C) 2014-2017 Sony Corporation. All rights reserved.
+ *   Author: Nobutaka Toyoshima <Nobutaka.Toyoshima@jp.sony.com>
+ *   Author: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LC823450_LC823450_PWM_H
+#define __ARCH_ARM_SRC_LC823450_LC823450_PWM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/drivers/pwm.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Addresses *******************************************************/
+
+#define LC823450_MTM0_REGBASE   0x40043000
+#define LC823450_MTM1_REGBASE   0x40044000
+
+#define LC823450_MTM_OPR        0x00
+#define LC823450_MTM_SYNC       0x04
+#define LC823450_MTM_PWM        0x08
+#define LC823450_MTM_FCTL       0x0c
+
+#define LC823450_MTM_0CTL       0x40
+#define LC823450_MTM_0IOCL      0x44
+#define LC823450_MTM_0STS       0x4C
+#define LC823450_MTM_0CNT       0x50
+#define LC823450_MTM_0A         0x54
+#define LC823450_MTM_0B         0x58
+#define LC823450_MTM_0SOL       0x5C
+#define LC823450_MTM_0BA        0x60
+#define LC823450_MTM_0BB        0x64
+#define LC823450_MTM_0PSCL      0x68
+#define LC823450_MTM_0TIER      0x6C
+#define LC823450_MTM_0TISR      0x70
+
+#define LC823450_MTM_1CTL       0x80
+#define LC823450_MTM_1IOCL      0x84
+#define LC823450_MTM_1STS       0x8C
+#define LC823450_MTM_1CNT       0x90
+#define LC823450_MTM_1A         0x94
+#define LC823450_MTM_1B         0x98
+#define LC823450_MTM_1SOL       0x9C
+#define LC823450_MTM_1BA        0xA0
+#define LC823450_MTM_1BB        0xA4
+#define LC823450_MTM_1PSCL      0xA8
+#define LC823450_MTM_1TIER      0xAC
+#define LC823450_MTM_1TISR      0xB0
+
+/* PWM Identifier ***********************************************************/
+
+#define LC823450_PWMTIMER0_CH0  0
+#define LC823450_PWMTIMER0_CH1  1
+#define LC823450_PWMTIMER1_CH0  2
+#define LC823450_PWMTIMER1_CH1  3
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+EXTERN FAR struct pwm_lowerhalf_s *lc823450_pwminitialize(int timer);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_SRC_LC823450_LC823450_PWM_H */
diff --git a/arch/arm/src/lc823450/lc823450_timerisr.c b/arch/arm/src/lc823450/lc823450_timerisr.c
index 1357219b262..256fa50acc9 100644
--- a/arch/arm/src/lc823450/lc823450_timerisr.c
+++ b/arch/arm/src/lc823450/lc823450_timerisr.c
@@ -109,6 +109,11 @@
 #  define rMT30CNT  (LC823450_MTM3_REGBASE + LC823450_MTM_0CNT)
 #endif /* CONFIG_PROFILE */
 
+#ifndef container_of
+#  define container_of(ptr, type, member) \
+    ((type *)((void *)(ptr) - offsetof(type, member)))
+#endif
+
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -175,7 +180,7 @@ static void hrt_queue_refresh(void)
   struct hrt_s *tmp;
   irqstate_t flags;
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave();
   elapsed = (uint64_t)getreg32(rMT20CNT) * (1000 * 1000) * 10 / XT1OSC_CLK;
 
   for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent))
@@ -193,7 +198,9 @@ cont:
       if (tmp->usec <= 0)
         {
           dq_rem(pent, &hrt_timer_queue);
+          spin_unlock_irqrestore(flags);
           nxsem_post(&tmp->sem);
+          flags = spin_lock_irqsave();
           goto cont;
         }
       else
@@ -202,12 +209,12 @@ cont:
         }
     }
 
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(flags);
 }
 #endif
 
 /****************************************************************************
- * Name: hrt_queue_refresh
+ * Name: hrt_usleep_setup
  ****************************************************************************/
 
 #ifdef CONFIG_HRT_TIMER
@@ -217,7 +224,7 @@ static void hrt_usleep_setup(void)
   struct hrt_s *head;
   irqstate_t flags;
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave();
   head = container_of(hrt_timer_queue.head, struct hrt_s, ent);
   if (head == NULL)
     {
@@ -225,7 +232,7 @@ static void hrt_usleep_setup(void)
 
       modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0x0);
       modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0x0);
-      leave_critical_section(flags);
+      spin_unlock_irqrestore(flags);
       return;
     }
 
@@ -244,12 +251,10 @@ static void hrt_usleep_setup(void)
   putreg32(0, rMT20CNT);   /* counter */
   putreg32(count, rMT20A); /* AEVT counter */
 
-  up_enable_irq(LC823450_IRQ_MTIMER20);
-
   /* Enable MTM2-Ch0 */
 
   putreg32(1, rMT2OPR);
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(flags);
 }
 #endif
 
@@ -273,6 +278,10 @@ static int hrt_interrupt(int irq, FAR void *context, FAR void *arg)
   return OK;
 }
 
+/****************************************************************************
+ * Name: hrt_usleep_add
+ ****************************************************************************/
+
 static void hrt_usleep_add(struct hrt_s *phrt)
 {
   dq_entry_t *pent;
@@ -284,7 +293,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
 
   hrt_queue_refresh();
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave();
 
   /* add phrt to hrt_timer_queue */
 
@@ -305,7 +314,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
       dq_addlast(&phrt->ent, &hrt_timer_queue);
     }
 
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(flags);
 
   hrt_usleep_setup();
 }
@@ -350,21 +359,20 @@ int up_timerisr(int irq, uint32_t *regs, FAR void *arg)
    /* Process timer interrupt */
 
 #ifdef CONFIG_DVFS
-    extern void lc823450_dvfs_tick_callback(void);
-    lc823450_dvfs_tick_callback();
+  lc823450_dvfs_tick_callback();
 #endif
 
 #ifdef CONFIG_LC823450_MTM0_TICK
-   /* Clear the interrupt (BEVT) */
+  /* Clear the interrupt (BEVT) */
 
-   putreg32(1 << 1, rMT00STS);
+  putreg32(1 << 1, rMT00STS);
 #endif
 
-   sched_process_timer();
+  sched_process_timer();
 
 #ifdef CONFIG_LCA_SOUNDSKIP_CHECK
-   extern void lca_check_soundskip(void);
-   lca_check_soundskip();
+  extern void lca_check_soundskip(void);
+  lca_check_soundskip();
 #endif
 
 #ifdef CHECK_INTERVAL
@@ -375,7 +383,7 @@ int up_timerisr(int irq, uint32_t *regs, FAR void *arg)
   hsuart_wdtimer();
 #endif /* CONFIG_HSUART */
 
-   return 0;
+  return 0;
 }
 
 /****************************************************************************
@@ -474,6 +482,8 @@ void arm_timer_initialize(void)
   modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0);
 
   (void)irq_attach(LC823450_IRQ_MTIMER20, (xcpt_t)hrt_interrupt, NULL);
+  up_enable_irq(LC823450_IRQ_MTIMER20);
+
 #endif /* CONFIG_HRT_TIMER */
 #ifdef CONFIG_PROFILE
 
@@ -619,7 +629,7 @@ int up_hr_gettime(FAR struct timespec *tp)
   irqstate_t   flags;
   uint64_t f;
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave();
 
   /* Get the elapsed time */
 
@@ -630,7 +640,7 @@ int up_hr_gettime(FAR struct timespec *tp)
   f = up_get_timer_fraction();
   elapsed += f;
 
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(flags);
 
   tmrinfo("elapsed = %lld \n", elapsed);
 
diff --git a/arch/arm/src/lc823450/lc823450_usbdev.c b/arch/arm/src/lc823450/lc823450_usbdev.c
index f5311e377bf..27e804fb971 100644
--- a/arch/arm/src/lc823450/lc823450_usbdev.c
+++ b/arch/arm/src/lc823450/lc823450_usbdev.c
@@ -716,10 +716,13 @@ static int lc823450_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
 {
   struct lc823450_req_s *privreq = (struct lc823450_req_s *)req;
   struct lc823450_ep_s *privep = (struct lc823450_ep_s *)ep;
+  irqstate_t flags;
 
   /* remove request from req_queue */
 
+  flags = spin_lock_irqsave();
   sq_remafter(&privreq->q_ent, &privep->req_q);
+  spin_unlock_irqrestore(flags);
   return 0;
 }
 
@@ -1251,6 +1254,9 @@ static void subintr_epin(uint8_t epnum, struct lc823450_ep_s *privep)
 {
   /* Send packet done */
 
+  irqstate_t flags;
+  flags = spin_lock_irqsave();
+
   if (privep->req_q.tail)
     {
       struct usbdev_req_s *req;
@@ -1259,6 +1265,9 @@ static void subintr_epin(uint8_t epnum, struct lc823450_ep_s *privep)
       /* Dequeue from TXQ */
 
       q_ent = sq_remlast(&privep->req_q);
+
+      spin_unlock_irqrestore(flags);
+
       req = &container_of(q_ent, struct lc823450_req_s, q_ent)->req;
 
       /* Write to TX FIFO */
@@ -1272,6 +1281,7 @@ static void subintr_epin(uint8_t epnum, struct lc823450_ep_s *privep)
     }
   else
     {
+      spin_unlock_irqrestore(flags);
       epcmd_write(epnum, USB_EPCMD_EMPTY_CLR);
     }
 }
@@ -1288,6 +1298,9 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep)
 {
   /* Packet receive from host */
 
+  irqstate_t flags;
+  flags = spin_lock_irqsave();
+
   if (privep->req_q.tail)
     {
       struct usbdev_req_s *req;
@@ -1296,6 +1309,7 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep)
       /* Dequeue from Reqbuf poll */
 
       q_ent = sq_remlast(&privep->req_q);
+
       req = &container_of(q_ent, struct lc823450_req_s, q_ent)->req;
       if (privep->req_q.tail == NULL)
         {
@@ -1304,6 +1318,8 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep)
           lc823450_epack(epnum, 0);
         }
 
+      spin_unlock_irqrestore(flags);
+
       /* PIO */
 
       epcmd_write(epnum, USB_EPCMD_READY_CLR);
@@ -1315,6 +1331,7 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep)
     }
   else
     {
+      spin_unlock_irqrestore(flags);
       uinfo("REQ Buffer Exhault\n");
       epcmd_write(epnum, USB_EPCMD_READY_CLR);
     }
diff --git a/configs/lc823450-xgevk/README.txt b/configs/lc823450-xgevk/README.txt
index 6c4e95e6f57..7562eef9aee 100644
--- a/configs/lc823450-xgevk/README.txt
+++ b/configs/lc823450-xgevk/README.txt
@@ -27,6 +27,15 @@ Settings
 ^^^^^^^^
 
 1. eMMC boot and SRAM boot via openocd are supported.
+
+If you do SRAM boot via openocd+gdb, please specify hookpost-load in .gdbinit
+to set MSP (main stack pointer) as follows.
+
+  define hookpost-load
+    print *(uint32_t *)0x02040000
+    set $sp=$
+  end
+
 2. If SWD connection is lost, please specify lower adaptor clock.
 3. Both CPUs are running at 160MHz.
 4. Internal SRAMs (seg0 to seg5) are used.
@@ -36,9 +45,8 @@ Settings
 SMP related Status
 ^^^^^^^^^^^^^^^^^^
 
-Currently SMP feature works on the board but might not be stable.
-In addition, console output might be corrupted if the both CPUs
-output into the console because UART operates in FIFO mode.
+Currently all applications except for ostest work in SMP mode but might stop
+due to deadlocks or ASSERT().
 
 CPU activities are shown at D9 (CPU0) and D10 (CPU1) respectively.
 
@@ -188,7 +196,7 @@ then dd the files to the kernel partition (/dev/mtdblock0p4) and the IPL2 partit
 
 10. Audio playback (WAV/44.1k/16bit/2ch only)
 
-Firstly, please check the jumper pin settings as follows.
+Firstly, please make sure that the jumper pins are set as follows.
 
   JP1, JP2 => short
   JP3, JP4 => open
@@ -200,6 +208,46 @@ To play WAV file on uSD card,
   nxplayer> play /mnt/sd1/sample.wav
   nxplayer> volume 50
 
+Please note that a WAV file which contains sub-chunks other than "fmt"
+and "data" is not supported in pcm_decode.c So, if your wav file contains
+meta-data, please remove the sub-chunks before playing.
+
+11. Networking
+
+lc823450/rndis configuration supports networking features with RNDIS.
+To use this feature, you have to connect the board to a RNDIS host.
+Currently Linux host is only tested but Windows host should work.
+
+If DHCP server is available, you would see ifconfig results like:
+
+nsh> ifconfig
+eth0 Link encap:Ethernet HWaddr 00:e0:de:ad:be:ff at UP
+     inet addr:192.168.1.244 DRaddr:192.168.1.1 Mask:255.255.255.0
+
+
+lo   Link encap:Local Loopback at UP
+     inet addr:127.0.0.1 DRaddr:127.0.0.1 Mask:255.0.0.0
+
+
+             IPv4   TCP   UDP  ICMP
+Received     0007  0000  0006  0000
+Dropped      0001  0000  0000  0000
+  IPv4        VHL: 0000   Frg: 0001
+  Checksum   0000  0000  0000  ----
+  TCP         ACK: 0000   SYN: 0000
+              RST: 0000  0000
+  Type       0000  ----  ----  0000
+Sent         0003  0000  0003  0000
+  Rexmit     ----  0000  ----  ----
+
+However, you might need to add a routing table if you want to send
+a packet via the router.
+
+nsh> addroute 0.0.0.0/0 192.168.1.1
+nsh> route
+SEQ TARGET NETMASK ROUTER
+   1. 0.0.0.0 0.0.0.0 192.168.1.1
+
 
 TODO
 ^^^^
diff --git a/configs/lc823450-xgevk/audio/defconfig b/configs/lc823450-xgevk/audio/defconfig
index af21efe27e9..36fde91ec97 100644
--- a/configs/lc823450-xgevk/audio/defconfig
+++ b/configs/lc823450-xgevk/audio/defconfig
@@ -41,6 +41,7 @@ CONFIG_FAT_LFN=y
 CONFIG_FS_FATTIME=y
 CONFIG_FS_FAT=y
 CONFIG_FS_PROCFS=y
+CONFIG_HRT_TIMER=y
 CONFIG_I2C_RESET=y
 CONFIG_I2CTOOL_MAXBUS=1
 CONFIG_I2C=y
@@ -50,6 +51,7 @@ CONFIG_LC823450_I2C0=y
 CONFIG_LC823450_I2C1=y
 CONFIG_LC823450_I2S0=y
 CONFIG_LC823450_MTD=y
+CONFIG_LC823450_MTM0_TICK=y
 CONFIG_LC823450_SDIF_SDC=y
 CONFIG_LC823450_SPI_DMA=y
 CONFIG_LC823450_UART0=y
@@ -116,6 +118,7 @@ CONFIG_SERIAL_TERMIOS=y
 CONFIG_SMP_NCPUS=2
 CONFIG_SMP=y
 # CONFIG_SPI_EXCHANGE is not set
+CONFIG_SPINLOCK_IRQ=y
 CONFIG_SPI=y
 CONFIG_START_DAY=3
 CONFIG_START_MONTH=10
diff --git a/configs/lc823450-xgevk/nsh/defconfig b/configs/lc823450-xgevk/nsh/defconfig
index 38b4a925da3..77c91d01315 100644
--- a/configs/lc823450-xgevk/nsh/defconfig
+++ b/configs/lc823450-xgevk/nsh/defconfig
@@ -39,12 +39,14 @@ CONFIG_EXAMPLES_WATCHDOG=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_WRITABLE=y
+CONFIG_HRT_TIMER=y
 CONFIG_I2C_RESET=y
 CONFIG_I2C=y
 CONFIG_I2CTOOL_MAXBUS=1
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LC823450_I2C0=y
 CONFIG_LC823450_I2C1=y
+CONFIG_LC823450_MTM0_TICK=y
 CONFIG_LC823450_SPI_DMA=y
 CONFIG_LC823450_UART0=y
 CONFIG_LC823450_WDT=y
@@ -100,6 +102,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=3072
 CONFIG_RAM_SIZE=1044480
 CONFIG_RAM_START=0x02001000
 CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_RTC_DATETIME=y
 CONFIG_RTC=y
 CONFIG_SCHED_ATEXIT=y
@@ -115,6 +118,7 @@ CONFIG_SDCLONE_DISABLE=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SMP_NCPUS=2
 CONFIG_SMP=y
+CONFIG_SPINLOCK_IRQ=y
 CONFIG_SPI=y
 CONFIG_START_DAY=3
 CONFIG_START_MONTH=10
diff --git a/configs/lc823450-xgevk/rndis/defconfig b/configs/lc823450-xgevk/rndis/defconfig
index f8d43f2e932..a4038e20396 100644
--- a/configs/lc823450-xgevk/rndis/defconfig
+++ b/configs/lc823450-xgevk/rndis/defconfig
@@ -43,6 +43,7 @@ CONFIG_FAT_LFN=y
 CONFIG_FS_FATTIME=y
 CONFIG_FS_FAT=y
 CONFIG_FS_PROCFS=y
+CONFIG_HRT_TIMER=y
 CONFIG_I2C_RESET=y
 CONFIG_I2CTOOL_MAXBUS=1
 CONFIG_I2C=y
@@ -55,6 +56,7 @@ CONFIG_LC823450_I2C0=y
 CONFIG_LC823450_I2C1=y
 CONFIG_LC823450_I2S0=y
 CONFIG_LC823450_MTD=y
+CONFIG_LC823450_MTM0_TICK=y
 CONFIG_LC823450_SDIF_SDC=y
 CONFIG_LC823450_SPI_DMA=y
 CONFIG_LC823450_UART0=y
@@ -81,6 +83,7 @@ CONFIG_NET_PKT=y
 CONFIG_NET_ROUTE=y
 CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP_RWND_CONTROL=y
 CONFIG_NET_TCP_WRITE_BUFFERS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
@@ -123,6 +126,7 @@ CONFIG_NX_BLOCKING=y
 # CONFIG_NX_DISABLE_1BPP is not set
 CONFIG_NXFONT_MONO5X8=y
 CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/sd1"
+CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y
 CONFIG_NX=y
 CONFIG_PIPES=y
 CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048
diff --git a/configs/lc823450-xgevk/usb/defconfig b/configs/lc823450-xgevk/usb/defconfig
index 164f4b96466..6e718622800 100644
--- a/configs/lc823450-xgevk/usb/defconfig
+++ b/configs/lc823450-xgevk/usb/defconfig
@@ -43,6 +43,7 @@ CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FATTIME=y
 CONFIG_FS_PROCFS=y
+CONFIG_HRT_TIMER=y
 CONFIG_I2C_RESET=y
 CONFIG_I2C=y
 CONFIG_I2CTOOL_MAXBUS=1
@@ -50,6 +51,7 @@ CONFIG_INTELHEX_BINARY=y
 CONFIG_LC823450_I2C0=y
 CONFIG_LC823450_I2C1=y
 CONFIG_LC823450_MTD=y
+CONFIG_LC823450_MTM0_TICK=y
 CONFIG_LC823450_SDIF_SDC=y
 CONFIG_LC823450_SPI_DMA=y
 CONFIG_LC823450_UART0=y
@@ -101,6 +103,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=3072
 CONFIG_RAM_SIZE=1044480
 CONFIG_RAM_START=0x02001000
 CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_RTC_DATETIME=y
 CONFIG_RTC=y
 CONFIG_SCHED_ATEXIT=y
@@ -117,6 +120,7 @@ CONFIG_SENSORS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SMP_NCPUS=2
 CONFIG_SMP=y
+CONFIG_SPINLOCK_IRQ=y
 CONFIG_SPI=y
 CONFIG_START_DAY=3
 CONFIG_START_MONTH=10