diff --git a/arch/arm/src/tiva/tiva_enableclks.h b/arch/arm/src/tiva/tiva_enableclks.h
index fca31484f5d..240d0170c04 100644
--- a/arch/arm/src/tiva/tiva_enableclks.h
+++ b/arch/arm/src/tiva/tiva_enableclks.h
@@ -251,6 +251,11 @@
 #  define tiva_ssi2_disableclk()   tiva_ssi_disableclk(2)
 #  define tiva_ssi3_disableclk()   tiva_ssi_disableclk(3)
 #else
+#  define tiva_ssi0_enableclk()    tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI0)
+#  define tiva_ssi1_enableclk()    tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI1)
+
+#  define tiva_ssi0_disableclk()   tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI0)
+#  define tiva_ssi1_disableclk()   tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI1)
 #endif
 
 /* I2C Run Mode Clock Gating Control */
diff --git a/arch/arm/src/tiva/tiva_ssi.c b/arch/arm/src/tiva/tiva_ssi.c
index dfe1d737a5c..1df8de7d09e 100644
--- a/arch/arm/src/tiva/tiva_ssi.c
+++ b/arch/arm/src/tiva/tiva_ssi.c
@@ -57,6 +57,7 @@
 
 #include "chip.h"
 #include "tiva_gpio.h"
+#include "tiva_enableclks.h"
 #include "tiva_ssi.h"
 #include "chip/tiva_pinmap.h"
 
@@ -1473,12 +1474,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       priv = &g_ssidev[SSI0_NDX];
 
-      /* Enable the SSI0 peripheral */
+      /* Enable clocking to the SSI0 peripheral */
 
-      regval = getreg32(TIVA_SYSCON_RCGC1);
-      regval |= SYSCON_RCGC1_SSI0;
-      putreg32(regval, TIVA_SYSCON_RCGC1);
-      ssivdbg("RCGC1: %08x\n", regval);
+      tiva_ssi0_enableclk();
 
       /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
        * logic in this file makes no assumptions about chip select)
@@ -1497,12 +1495,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       priv = &g_ssidev[SSI1_NDX];
 
-      /* Enable the SSI1 peripheral */
+      /* Enable clocking to the SSI1 peripheral */
 
-      regval = getreg32(TIVA_SYSCON_RCGC1);
-      regval |= SYSCON_RCGC1_SSI1;
-      putreg32(regval, TIVA_SYSCON_RCGC1);
-      ssivdbg("RCGC1: %08x\n", regval);
+      tiva_ssi1_enableclk();
 
       /* Configure SSI1 GPIOs */