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SAMA5D2: Add pin multiplexing definition file and other necessary changes for the SAMA5D2

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This commit is contained in:
Gregory Nutt
2015-09-10 13:05:24 -06:00
parent 7ad8c32adf
commit c1b83cfbc8
11 changed files with 1510 additions and 175 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/sama5/Kconfig
+181
View File
@@ -17,6 +17,10 @@ config SAMA5_HAVE_ICM
bool
default n
config SAMA5_HAVE_RXLP
bool
default n
config SAMA5_HAVE_UART0
bool
default n
@@ -57,6 +61,26 @@ config SAMA5_HAVE_USART4
bool
default n
config SAMA5_HAVE_FLEXCOM0
bool
default n
config SAMA5_HAVE_FLEXCOM1
bool
default n
config SAMA5_HAVE_FLEXCOM2
bool
default n
config SAMA5_HAVE_FLEXCOM3
bool
default n
config SAMA5_HAVE_FLEXCOM4
bool
default n
config SAMA5_HAVE_CAN0
bool
default n
@@ -145,6 +169,24 @@ config SAMA5_HAVE_VDEC
bool
default n
# Summary configuratinos
config SAMA5_FLEXCOM
bool
default n
config SAMA5_FLEXCOM_USART
bool
default n
config SAMA5_FLEXCOM_SPI
bool
default n
config SAMA5_FLEXCOM_TWI
bool
default n
# Chip Selection
config ARCH_CHIP_SAMA5D2
@@ -156,11 +198,16 @@ config ARCH_CHIP_SAMA5D2
select SAMA5_HAVE_EMACB
select SAMA5_HAVE_ICM
select SAMA5_HAVE_LCDC
select SAMA5_HAVE_RXLP
select SAMA5_HAVE_UART0
select SAMA5_HAVE_UART1
select SAMA5_HAVE_UART2
select SAMA5_HAVE_UART3
select SAMA5_HAVE_UART4
select SAMA5_HAVE_FLEXCOM0
select SAMA5_HAVE_FLEXCOM1
select SAMA5_HAVE_FLEXCOM2
select SAMA5_HAVE_FLEXCOM3
select SAMA5_HAVE_QSPI
select SAMA5_HAVE_XDMA
select SAMA5_HAVE_SAIC
@@ -379,6 +426,11 @@ config SAMA5_SAIC
depends on SAMA5_HAVE_SAIC
select ARMV7A_DECODEFIQ
config SAMA5_RXLP
bool "Low power asynchronous receiver"
default y
depends on SAMA5_HAVE_RXLP
config SAMA5_UART0
bool "UART 0"
default y
@@ -449,6 +501,36 @@ config SAMA5_USART4
select ARCH_HAVE_USART4
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_FLEXCOM0
bool "FLEXCOM 0"
default n
depends on SAMA5_HAVE_FLEXCOM0
select SAMA5_FLEXCOM
config SAMA5_FLEXCOM1
bool "FLEXCOM 1"
default n
depends on SAMA5_HAVE_FLEXCOM1
select SAMA5_FLEXCOM
config SAMA5_FLEXCOM2
bool "FLEXCOM 2"
default n
depends on SAMA5_HAVE_FLEXCOM2
select SAMA5_FLEXCOM
config SAMA5_FLEXCOM3
bool "FLEXCOM 3"
default n
depends on SAMA5_HAVE_FLEXCOM3
select SAMA5_FLEXCOM
config SAMA5_FLEXCOM4
bool "FLEXCOM 4"
default n
depends on SAMA5_HAVE_FLEXCOM4
select SAMA5_FLEXCOM
config SAMA5_TWI0
bool "Two-Wire Interface 0 (TWI0)"
default n
@@ -703,6 +785,105 @@ config SAMA5_PIOE_IRQ
endif # PIO_IRQ
menu "Flexcom Configuration"
depends on SAMA5_FLEXCOM
choice
prompt "FLEXCOM0 Configuration"
default SAMA5_FLEXCOM0_USART
depends on SAMA5_FLEXCOM0
config SAMA5_FLEXCOM0_USART
bool "USART"
select SAMA5_FLEXCOM_USART
config SAMA5_FLEXCOM0_SPI
bool "SPI"
select SAMA5_FLEXCOM_SPI
config SAMA5_FLEXCOM0_SPI
bool "TWI"
select SAMA5_FLEXCOM_TWI
endchoice # FLEXCOM0 Configuration
choice
prompt "FLEXCOM1 Configuration"
default SAMA5_FLEXCOM1_USART
depends on SAMA5_FLEXCOM1
config SAMA5_FLEXCOM1_USART
bool "USART"
select SAMA5_FLEXCOM_USART
config SAMA5_FLEXCOM1_SPI
bool "SPI"
select SAMA5_FLEXCOM_SPI
config SAMA5_FLEXCOM1_SPI
bool "TWI"
select SAMA5_FLEXCOM_TWI
endchoice # FLEXCOM1 Configuration
choice
prompt "FLEXCOM2 Configuration"
default SAMA5_FLEXCOM2_USART
depends on SAMA5_FLEXCOM2
config SAMA5_FLEXCOM2_USART
bool "USART"
select SAMA5_FLEXCOM_USART
config SAMA5_FLEXCOM2_SPI
bool "SPI"
select SAMA5_FLEXCOM_SPI
config SAMA5_FLEXCOM2_SPI
bool "TWI"
select SAMA5_FLEXCOM_TWI
endchoice # FLEXCOM2 Configuration
choice
prompt "FLEXCOM3 Configuration"
default SAMA5_FLEXCOM3_USART
depends on SAMA5_FLEXCOM3
config SAMA5_FLEXCOM3_USART
bool "USART"
select SAMA5_FLEXCOM_USART
config SAMA5_FLEXCOM3_SPI
bool "SPI"
select SAMA5_FLEXCOM_SPI
config SAMA5_FLEXCOM3_SPI
bool "TWI"
select SAMA5_FLEXCOM_TWI
endchoice # FLEXCOM3 Configuration
choice
prompt "FLEXCOM4 Configuration"
default SAMA5_FLEXCOM4_USART
depends on SAMA5_FLEXCOM4
config SAMA5_FLEXCOM4_USART
bool "USART"
select SAMA5_FLEXCOM_USART
config SAMA5_FLEXCOM4_SPI
bool "SPI"
select SAMA5_FLEXCOM_SPI
config SAMA5_FLEXCOM4_SPI
bool "TWI"
select SAMA5_FLEXCOM_TWI
endchoice # FLEXCOM4 Configuration
endmenu # Flexcom Configuration
menu "DBGU Configuration"
depends on SAMA5_DBGU
arch/arm/src/sama5/chip/sam_pinmap.h
+3 -1
View File
@@ -43,7 +43,9 @@
#include <nuttx/config.h>
#include <arch/sama5/chip.h>
#if defined(ATSAMA5D3)
#if defined(ATSAMA5D2)
# include "chip/sama5d3x_pinmap.h"
#elif defined(ATSAMA5D3)
# include "chip/sama5d3x_pinmap.h"
#elif defined(ATSAMA5D4)
# include "chip/sama5d4x_pinmap.h"
arch/arm/src/sama5/chip/sam_pmc.h
+2
View File
@@ -384,6 +384,7 @@
#endif
#if defined(ATSAMA5D3) || defined(ATSAMA5D4)
# undef SAMA5_HAVE_PCK_INT_PRES /* Supports conditional compilation */
# define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */
# define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT)
# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */
@@ -394,6 +395,7 @@
# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */
# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */
#elif defined(ATSAMA5D2)
# define SAMA5_HAVE_PCK_INT_PRES 1 /* Supports conditional compilation */
# define PMC_PCK_PRES_SHIFT (4) /* Bits 4-11: Programmable Clock Prescaler */
# define PMC_PCK_PRES_MASK (0xff << PMC_PCK_PRES_SHIFT)
# define PMC_PCK_PRES(n) ((uint32_t)(n) << PMC_PCK_PRES_SHIFT)
arch/arm/src/sama5/chip/sama5d2x_memorymap.h
+19 -2
View File
@@ -172,7 +172,15 @@
# define SAM_UDPHS_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: UDPHS */
# define SAM_ADC_OFFSET 0x00030000 /* 0x00030000-0x00033fff: ADC */
/* 0x00034000-0x00037fff: Reserved */
# define SAM_PIOA_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: PIOA */
# define SAM_PIO_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: PIO */
# define SAM_PIOA_OFFSET 0x00038000 /* 0x00038000-0x0003803f: PIOA */
# define SAM_PIOB_OFFSET 0x00038040 /* 0x00038040-0x0003807f: PIOB */
# define SAM_PIOC_OFFSET 0x00038080 /* 0x00038080-0x000380bf: PIOC */
# define SAM_PIOD_OFFSET 0x000380c0 /* 0x000380c0-0x000380ff: PIOD */
# define SAM_SPIOA_OFFSET 0x00039000 /* 0x00039000-0x0003903f: Secure PIOA */
# define SAM_SPIOB_OFFSET 0x00039040 /* 0x00039040-0x0003907f: Secure PIOB */
# define SAM_SPIOC_OFFSET 0x00039080 /* 0x00039080-0x000390bf: Secure PIOC */
# define SAM_SPIOD_OFFSET 0x000390c0 /* 0x000390c0-0x000390ff: Secure PIOD */
# define SAM_MATRIX1_OFFSET 0x0003c000 /* 0x0003c000-0x0003ffff: MATRIX1 */
# define SAM_SECUMOD_OFFSET 0x00040000 /* 0x00040000-0x00043fff: SECUMOD */
# define SAM_TDES_OFFSET 0x00044000 /* 0x00044000-0x00047fff: TDES */
@@ -313,6 +321,7 @@
#define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_AXIMX_MMUFLAGS MMU_IOFLAGS
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
#define SAM_L2CC_MMUFLAGS MMU_IOFLAGS
/* If the NFC is not being used, the NFC SRAM can be used as general purpose
* SRAM (cached). If the NFC is used, then the NFC SRAM should be treated
@@ -509,7 +518,15 @@
#define SAM_TWI1_VBASE (SAM_PERIPHC_VSECTION+SAM_TWI1_OFFSET)
#define SAM_UDPHS_VBASE (SAM_PERIPHC_VSECTION+SAM_UDPHS_OFFSET)
#define SAM_ADC_VBASE (SAM_PERIPHC_VSECTION+SAM_ADC_OFFSET)
#define SAM_PIOA_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOA_OFFSET)
#define SAM_PIO_VBASE (SAM_PERIPHC_VSECTION+SAM_PIO_OFFSET)
# define SAM_PIOA_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOA_OFFSET)
# define SAM_PIOB_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOB_OFFSET)
# define SAM_PIOC_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOC_OFFSET)
# define SAM_PIOD_VBASE (SAM_PERIPHC_VSECTION+SAM_PIOD_OFFSET)
# define SAM_SPIOA_VBASE (SAM_PERIPHC_VSECTION+SAM_SPIOA_OFFSET)
# define SAM_SPIOB_VBASE (SAM_PERIPHC_VSECTION+SAM_SPIOB_OFFSET)
# define SAM_SPIOC_VBASE (SAM_PERIPHC_VSECTION+SAM_SPIOC_OFFSET)
# define SAM_SPIOD_VBASE (SAM_PERIPHC_VSECTION+SAM_SPIOD_OFFSET)
#define SAM_MATRIX1_VBASE (SAM_PERIPHC_VSECTION+SAM_MATRIX1_OFFSET)
#define SAM_SECUMOD_VBASE (SAM_PERIPHC_VSECTION+SAM_SECUMOD_OFFSET)
#define SAM_TDES_VBASE (SAM_PERIPHC_VSECTION+SAM_TDES_OFFSET)
arch/arm/src/sama5/chip/sama5d2x_pinmap.h
Executable
+804
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/sama5/sam_pck.c
+29 -8
View File
@@ -106,6 +106,9 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc,
uint32_t regval;
uint32_t clkin;
uint32_t actual;
#ifdef SAMA5_HAVE_PCK_INT_PRES
uint32_t pres;
#endif
/* Pick a clock source. Several are possible but only MCK, PLLA, the
* MAINCK,or SCK are supported here.
@@ -152,6 +155,23 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc,
return 0;
}
#ifdef SAMA5_HAVE_PCK_INT_PRES
/* Programmable Clock frequency is selected clock freqency divided by PRES + 1 */
pres = clkin / frequency;
if (pres < 1)
{
pres = 1;
}
else if (pres > (PMC_PCK_PRES_MASK + 1))
{
pres = PMC_PCK_PRES_MASK + 1;
}
regval |= PMC_PCK_PRES(pres - 1);
actual = frequency / pres;
#else
/* The the larger smallest divisor that does not exceed the requested
* frequency.
*/
@@ -164,40 +184,41 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc,
else if (frequency >= (clkin >> 1))
{
regval |= PMC_PCK_PRES_DIV2;
actual = clkin >> 1;
actual = clkin >> 1;
}
else if (frequency >= (clkin >> 2))
{
regval |= PMC_PCK_PRES_DIV4;
actual = clkin >> 2;
actual = clkin >> 2;
}
else if (frequency >= (clkin >> 3))
{
regval |= PMC_PCK_PRES_DIV8;
actual = clkin >> 3;
actual = clkin >> 3;
}
else if (frequency >= (clkin >> 4))
{
regval |= PMC_PCK_PRES_DIV16;
actual = clkin >> 4;
actual = clkin >> 4;
}
else if (frequency >= (clkin >> 5))
{
regval |= PMC_PCK_PRES_DIV32;
actual = clkin >> 5;
actual = clkin >> 5;
}
else if (frequency >= (clkin >> 6))
{
regval |= PMC_PCK_PRES_DIV64;
actual = clkin >> 6;
actual = clkin >> 6;
}
else
{
sdbg("ERROR: frequency cannot be realized.\n");
sdbg(" frequency=%d MCK=%d\n",
frequency, clkin);
sdbg(" frequency=%lu clkin=%lu\n",
(unsigned long)frequency, (unsigned long)clkin);
return 0;
}
#endif
/* Disable the programmable clock, configure the PCK output pin, then set
* the selected configuration.
arch/arm/src/sama5/sam_pio.c
+27 -4
View File
@@ -78,11 +78,22 @@
* contiguous. If not defined, then we need to do a table lookup.
*/
#ifndef SAM_PION_VBASE
#if !defined(SAM_PION_VBASE) && SAM_NPIO > 0
const uintptr_t g_piobase[SAM_NPIO] =
{
SAM_PIOA_VBASE, SAM_PIOB_VBASE, SAM_PIOC_VBASE, SAM_PIOD_VBASE,
SAM_PIOA_VBASE,
#if SAM_NPIO > 1
SAM_PIOB_VBASE,
#endif
#if SAM_NPIO > 2
SAM_PIOC_VBASE,
#endif
#if SAM_NPIO > 3
SAM_PIOD_VBASE,
#endif
#if SAM_NPIO > 4
SAM_PIOE_VBASE
#endif
};
#endif
@@ -91,10 +102,22 @@ const uintptr_t g_piobase[SAM_NPIO] =
****************************************************************************/
/* Maps a port number to the standard port character */
#ifdef CONFIG_DEBUG_GPIO
#if defined(CONFIG_DEBUG_GPIO) && SAM_NPIO > 0
static const char g_portchar[SAM_NPIO] =
{
'A', 'B', 'C', 'D', 'E'
'A',
#if SAM_NPIO > 1
'B',
#endif
#if SAM_NPIO > 2
'C',
#endif
#if SAM_NPIO > 3
'D',
#endif
#if SAM_NPIO > 4
'E'
#endif
};
#endif
arch/arm/src/sama5/sam_pio.h
+9 -158
View File
@@ -2,7 +2,7 @@
* arch/arm/src/sama5/sam_pio.h
* Parallel Input/Output (PIO) definitions for the SAMA5
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -46,177 +46,28 @@
#include <stdint.h>
#include <stdbool.h>
#include <arch/sama5/chip.h>
#include "chip/sam_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#if !defined(CONFIG_SAMA5_PIOA_IRQ) && !defined(CONFIG_SAMA5_PIOB_IRQ) && \
!defined(CONFIG_SAMA5_PIOC_IRQ) && !defined(CONFIG_SAMA5_PIOD_IRQ) && \
!defined(CONFIG_SAMA5_PIOE_IRQ) && !defined(CONFIG_SAMA5_PIOF_IRQ)
# undef CONFIG_SAMA5_PIO_IRQ
#endif
/* Definitions and types customized for each SAMA5Dx familiy */
#ifndef CONFIG_DEBUG
# undef CONFIG_DEBUG_GPIO
#endif
#define PIO_HAVE_PULLDOWN 1
#define PIO_HAVE_PERIPHCD 1
#define PIO_HAVE_SCHMITT 1
#define PIO_HAVE_DRIVE 1
#define SAM_NPIO 5 /* (5) PIOA-E */
/* Bit-encoded input to sam_configpio() ********************************************/
/* 32-bit Encoding:
*
* .... .... .MMM CCCC CDDI IISV PPPB BBBB
*/
/* Input/Output mode:
*
* .... .... .MMM .... .... .... .... ....
*/
#define PIO_MODE_SHIFT (20) /* Bits 20-22: PIO mode */
#define PIO_MODE_MASK (7 << PIO_MODE_SHIFT)
# define PIO_INPUT (0 << PIO_MODE_SHIFT) /* Input */
# define PIO_OUTPUT (1 << PIO_MODE_SHIFT) /* Output */
# define PIO_PERIPHA (2 << PIO_MODE_SHIFT) /* Controlled by periph A signal */
# define PIO_PERIPHB (3 << PIO_MODE_SHIFT) /* Controlled by periph B signal */
# define PIO_PERIPHC (4 << PIO_MODE_SHIFT) /* Controlled by periph C signal */
# define PIO_PERIPHD (5 << PIO_MODE_SHIFT) /* Controlled by periph D signal */
/* These bits set the configuration of the pin:
* NOTE: No definitions for parallel capture mode
*
* .... .... .... CCCC C... .... .... ....
*/
#define PIO_CFG_SHIFT (15) /* Bits 15-19: PIO configuration bits */
#define PIO_CFG_MASK (31 << PIO_CFG_SHIFT)
# define PIO_CFG_DEFAULT (0 << PIO_CFG_SHIFT) /* Default, no attribute */
# define PIO_CFG_PULLUP (1 << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
# define PIO_CFG_PULLDOWN (2 << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
# define PIO_CFG_DEGLITCH (4 << PIO_CFG_SHIFT) /* Bit 17: Internal glitch filter */
# define PIO_CFG_OPENDRAIN (8 << PIO_CFG_SHIFT) /* Bit 18: Open drain */
# define PIO_CFG_SCHMITT (16 << PIO_CFG_SHIFT) /* Bit 19: Schmitt trigger */
/* Drive Strength:
*
* .... .... .... .... .DD. .... .... ....
*/
#define PIO_DRIVE_SHIFT (13) /* Bits 13-14: Drive strength */
#define PIO_DRIVE_MASK (7 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_LOW (0 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_MEDIUM (2 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_HIGH (3 << PIO_DRIVE_SHIFT)
/* Additional interrupt modes:
*
* .... .... .... .... ...I II.. .... ....
*/
#define PIO_INT_SHIFT (10) /* Bits 9-12: PIO interrupt bits */
#define PIO_INT_MASK (7 << PIO_INT_SHIFT)
# define _PIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
# define _PIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
# define _PIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
# define _PIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
# define _PIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
# define PIO_INT_HIGHLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_RH)
# define PIO_INT_LOWLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_FL)
# define PIO_INT_RISING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_RH)
# define PIO_INT_FALLING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_FL)
# define PIO_INT_BOTHEDGES (0)
/* If the pin is an interrupt, then this determines if the pin is a secure interrupt:
*
* .... .... .... .... .... ..S. .... ....
*/
#ifdef SAMA5_SAIC
# define PIO_INT_SECURE (1 << 9) /* Bit 9: Secure interrupt */
#if defined(ATSAMA5D2)
# include "sama5d2x_pio.h"
#elif defined(ATSAMA5D3) || defined(ATSAMA5D4)
# include "sama5d3x4x_pio.h"
#else
# define PIO_INT_SECURE (0)
# error Unrecognized SAMA5 architecture
#endif
#define PIO_INT_UNSECURE (0)
/* If the pin is an PIO output, then this identifies the initial output value:
*
* .... .... .... .... .... ...V .... ....
*/
#define PIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */
#define PIO_OUTPUT_CLEAR (0)
/* This identifies the PIO port:
*
* .... .... .... .... .... .... PPP. ....
*/
#define PIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
#define PIO_PORT_MASK (7 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOA (0 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOB (1 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOC (2 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOD (3 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOE (4 << PIO_PORT_SHIFT)
/* This identifies the bit in the port:
*
* .... .... .... .... .... .... ...B BBBB
*/
#define PIO_PIN_SHIFT (0) /* Bits 0-4: PIO number: 0-31 */
#define PIO_PIN_MASK (31 << PIO_PIN_SHIFT)
#define PIO_PIN0 (0 << PIO_PIN_SHIFT)
#define PIO_PIN1 (1 << PIO_PIN_SHIFT)
#define PIO_PIN2 (2 << PIO_PIN_SHIFT)
#define PIO_PIN3 (3 << PIO_PIN_SHIFT)
#define PIO_PIN4 (4 << PIO_PIN_SHIFT)
#define PIO_PIN5 (5 << PIO_PIN_SHIFT)
#define PIO_PIN6 (6 << PIO_PIN_SHIFT)
#define PIO_PIN7 (7 << PIO_PIN_SHIFT)
#define PIO_PIN8 (8 << PIO_PIN_SHIFT)
#define PIO_PIN9 (9 << PIO_PIN_SHIFT)
#define PIO_PIN10 (10 << PIO_PIN_SHIFT)
#define PIO_PIN11 (11 << PIO_PIN_SHIFT)
#define PIO_PIN12 (12 << PIO_PIN_SHIFT)
#define PIO_PIN13 (13 << PIO_PIN_SHIFT)
#define PIO_PIN14 (14 << PIO_PIN_SHIFT)
#define PIO_PIN15 (15 << PIO_PIN_SHIFT)
#define PIO_PIN16 (16 << PIO_PIN_SHIFT)
#define PIO_PIN17 (17 << PIO_PIN_SHIFT)
#define PIO_PIN18 (18 << PIO_PIN_SHIFT)
#define PIO_PIN19 (19 << PIO_PIN_SHIFT)
#define PIO_PIN20 (20 << PIO_PIN_SHIFT)
#define PIO_PIN21 (21 << PIO_PIN_SHIFT)
#define PIO_PIN22 (22 << PIO_PIN_SHIFT)
#define PIO_PIN23 (23 << PIO_PIN_SHIFT)
#define PIO_PIN24 (24 << PIO_PIN_SHIFT)
#define PIO_PIN25 (25 << PIO_PIN_SHIFT)
#define PIO_PIN26 (26 << PIO_PIN_SHIFT)
#define PIO_PIN27 (27 << PIO_PIN_SHIFT)
#define PIO_PIN28 (28 << PIO_PIN_SHIFT)
#define PIO_PIN29 (29 << PIO_PIN_SHIFT)
#define PIO_PIN30 (30 << PIO_PIN_SHIFT)
#define PIO_PIN31 (31 << PIO_PIN_SHIFT)
/************************************************************************************
* Public Types
************************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t pio_pinset_t;
/* SAM_PION_VBASE will only be defined if the PIO register blocks are contiguous.
* If not defined, then we need to do a table lookup.
*/
arch/arm/src/sama5/sama5d2x_memorymap.c
+2 -2
View File
@@ -103,7 +103,7 @@ const struct section_mapping_s g_section_mapping[] =
*/
#ifdef CONFIG_ARCH_LOWVECTORS
{ SAM_SRAMREMAP_PSECTION, SAM_SRAMREMAP_vSECTION,
{ SAM_SRAMREMAP_PSECTION, SAM_SRAMREMAP_VSECTION,
SAM_SRAMREMAP_MMUFLAGS, SAM_SRAMREMAP_NSECTIONS
},
#endif
@@ -134,7 +134,7 @@ const struct section_mapping_s g_section_mapping[] =
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
},
#if defined(CONFIG_ARCH_CHIP_SAMA5D2) && !defined(CONFIG_ARCH_L2CACHE)
#if defined(CONFIG_ARCH_CHIP_SAMA5D2) && defined(CONFIG_ARCH_L2CACHE)
/* The SAMA5D2 features a second 128-Kbyte SRAM that can be allocated
* either to the L2 cache controller or used as an internal SRAM. After
* reset, this block is connected to the L2 cache controller. The
arch/arm/src/sama5/sama5d2x_pio.h
+221
View File
@@ -0,0 +1,221 @@
/************************************************************************************
* arch/arm/src/sama5/sama5d2x_pio.h
* Parallel Input/Output (PIO) definitions for the SAMA5D2 family
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMA5D2X_PIO_H
#define __ARCH_ARM_SRC_SAMA5_SAMA5D2X_PIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip/sam_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#if !defined(CONFIG_SAMA5_PIOA_IRQ) && !defined(CONFIG_SAMA5_PIOB_IRQ) && \
!defined(CONFIG_SAMA5_PIOC_IRQ) && !defined(CONFIG_SAMA5_PIOD_IRQ)
# undef CONFIG_SAMA5_PIO_IRQ
#endif
#ifndef CONFIG_DEBUG
# undef CONFIG_DEBUG_GPIO
#endif
#define PIO_HAVE_PULLDOWN 1
#define PIO_HAVE_PERIPHCD 1
#define PIO_HAVE_SCHMITT 1
#define PIO_HAVE_DRIVE 1
#define SAM_NPIO 4 /* (4) PIOA-D */
/* Bit-encoded input to sam_configpio() ********************************************/
/* 32-bit Encoding:
*
* .... ...M MMMM CCCC CDDI IISV .PPB BBBB
*/
/* Input/Output mode:
*
* .... ...M MMMM .... .... .... .... ....
*/
#define PIO_MODE_SHIFT (20) /* Bits 20-24: PIO mode */
#define PIO_MODE_MASK (15 << PIO_MODE_SHIFT)
# define PIO_INPUT (0 << PIO_MODE_SHIFT) /* Input */
# define PIO_OUTPUT (1 << PIO_MODE_SHIFT) /* Output */
# define PIO_ANALOG (2 << PIO_MODE_SHIFT) /* Analog */
# define PIO_PERIPHA (3 << PIO_MODE_SHIFT) /* Controlled by periph A signal */
# define PIO_PERIPHB (4 << PIO_MODE_SHIFT) /* Controlled by periph B signal */
# define PIO_PERIPHC (5 << PIO_MODE_SHIFT) /* Controlled by periph C signal */
# define PIO_PERIPHD (6 << PIO_MODE_SHIFT) /* Controlled by periph D signal */
# define PIO_PERIPHE (7 << PIO_MODE_SHIFT) /* Controlled by periph E signal */
# define PIO_PERIPHF (8 << PIO_MODE_SHIFT) /* Controlled by periph F signal */
/* These bits set the configuration of the pin:
* NOTE: No definitions for parallel capture mode
*
* .... .... .... CCCC C... .... .... ....
*/
#define PIO_CFG_SHIFT (15) /* Bits 15-19: PIO configuration bits */
#define PIO_CFG_MASK (31 << PIO_CFG_SHIFT)
# define PIO_CFG_DEFAULT (0 << PIO_CFG_SHIFT) /* Default, no attribute */
# define PIO_CFG_PULLUP (1 << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
# define PIO_CFG_PULLDOWN (2 << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
# define PIO_CFG_DEGLITCH (4 << PIO_CFG_SHIFT) /* Bit 17: Internal glitch filter */
# define PIO_CFG_OPENDRAIN (8 << PIO_CFG_SHIFT) /* Bit 18: Open drain */
# define PIO_CFG_SCHMITT (16 << PIO_CFG_SHIFT) /* Bit 19: Schmitt trigger */
/* Drive Strength:
*
* .... .... .... .... .DD. .... .... ....
*/
#define PIO_DRIVE_SHIFT (13) /* Bits 13-14: Drive strength */
#define PIO_DRIVE_MASK (7 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_LOW (0 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_MEDIUM (2 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_HIGH (3 << PIO_DRIVE_SHIFT)
/* Additional interrupt modes:
*
* .... .... .... .... ...I II.. .... ....
*/
#define PIO_INT_SHIFT (10) /* Bits 9-12: PIO interrupt bits */
#define PIO_INT_MASK (7 << PIO_INT_SHIFT)
# define _PIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
# define _PIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
# define _PIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
# define _PIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
# define _PIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
# define PIO_INT_HIGHLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_RH)
# define PIO_INT_LOWLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_FL)
# define PIO_INT_RISING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_RH)
# define PIO_INT_FALLING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_FL)
# define PIO_INT_BOTHEDGES (0)
/* If the pin is an interrupt, then this determines if the pin is a secure interrupt:
*
* .... .... .... .... .... ..S. .... ....
*/
#ifdef SAMA5_SAIC
# define PIO_INT_SECURE (1 << 9) /* Bit 9: Secure interrupt */
#else
# define PIO_INT_SECURE (0)
#endif
#define PIO_INT_UNSECURE (0)
/* If the pin is an PIO output, then this identifies the initial output value:
*
* .... .... .... .... .... ...V .... ....
*/
#define PIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */
#define PIO_OUTPUT_CLEAR (0)
/* This identifies the PIO port:
*
* .... .... .... .... .... .... .PP. ....
*/
#define PIO_PORT_SHIFT (5) /* Bit 5-6: Port number */
#define PIO_PORT_MASK (3 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOA (0 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOB (1 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOC (2 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOD (3 << PIO_PORT_SHIFT)
/* This identifies the bit in the port:
*
* .... .... .... .... .... .... ...B BBBB
*/
#define PIO_PIN_SHIFT (0) /* Bits 0-4: PIO number: 0-31 */
#define PIO_PIN_MASK (31 << PIO_PIN_SHIFT)
#define PIO_PIN0 (0 << PIO_PIN_SHIFT)
#define PIO_PIN1 (1 << PIO_PIN_SHIFT)
#define PIO_PIN2 (2 << PIO_PIN_SHIFT)
#define PIO_PIN3 (3 << PIO_PIN_SHIFT)
#define PIO_PIN4 (4 << PIO_PIN_SHIFT)
#define PIO_PIN5 (5 << PIO_PIN_SHIFT)
#define PIO_PIN6 (6 << PIO_PIN_SHIFT)
#define PIO_PIN7 (7 << PIO_PIN_SHIFT)
#define PIO_PIN8 (8 << PIO_PIN_SHIFT)
#define PIO_PIN9 (9 << PIO_PIN_SHIFT)
#define PIO_PIN10 (10 << PIO_PIN_SHIFT)
#define PIO_PIN11 (11 << PIO_PIN_SHIFT)
#define PIO_PIN12 (12 << PIO_PIN_SHIFT)
#define PIO_PIN13 (13 << PIO_PIN_SHIFT)
#define PIO_PIN14 (14 << PIO_PIN_SHIFT)
#define PIO_PIN15 (15 << PIO_PIN_SHIFT)
#define PIO_PIN16 (16 << PIO_PIN_SHIFT)
#define PIO_PIN17 (17 << PIO_PIN_SHIFT)
#define PIO_PIN18 (18 << PIO_PIN_SHIFT)
#define PIO_PIN19 (19 << PIO_PIN_SHIFT)
#define PIO_PIN20 (20 << PIO_PIN_SHIFT)
#define PIO_PIN21 (21 << PIO_PIN_SHIFT)
#define PIO_PIN22 (22 << PIO_PIN_SHIFT)
#define PIO_PIN23 (23 << PIO_PIN_SHIFT)
#define PIO_PIN24 (24 << PIO_PIN_SHIFT)
#define PIO_PIN25 (25 << PIO_PIN_SHIFT)
#define PIO_PIN26 (26 << PIO_PIN_SHIFT)
#define PIO_PIN27 (27 << PIO_PIN_SHIFT)
#define PIO_PIN28 (28 << PIO_PIN_SHIFT)
#define PIO_PIN29 (29 << PIO_PIN_SHIFT)
#define PIO_PIN30 (30 << PIO_PIN_SHIFT)
#define PIO_PIN31 (31 << PIO_PIN_SHIFT)
/************************************************************************************
* Public Types
************************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t pio_pinset_t;
#endif /* __ARCH_ARM_SRC_SAMA5_SAMA5D2X_PIO_H */
arch/arm/src/sama5/sama5d3x4x_pio.h
+213
View File
@@ -0,0 +1,213 @@
/************************************************************************************
* arch/arm/src/sama5/sama5d3x4x_pio.h
* Parallel Input/Output (PIO) definitions for the SAMA5D23 and SAMA5D4 families
*
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMA5D3X4X_PIO_H
#define __ARCH_ARM_SRC_SAMA5_SAMA5D3X4X_PIO_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#if !defined(CONFIG_SAMA5_PIOA_IRQ) && !defined(CONFIG_SAMA5_PIOB_IRQ) && \
!defined(CONFIG_SAMA5_PIOC_IRQ) && !defined(CONFIG_SAMA5_PIOD_IRQ) && \
!defined(CONFIG_SAMA5_PIOE_IRQ) && !defined(CONFIG_SAMA5_PIOF_IRQ)
# undef CONFIG_SAMA5_PIO_IRQ
#endif
#ifndef CONFIG_DEBUG
# undef CONFIG_DEBUG_GPIO
#endif
#define PIO_HAVE_PULLDOWN 1
#define PIO_HAVE_PERIPHCD 1
#define PIO_HAVE_SCHMITT 1
#define PIO_HAVE_DRIVE 1
#define SAM_NPIO 5 /* (5) PIOA-E */
/* Bit-encoded input to sam_configpio() ********************************************/
/* 32-bit Encoding:
*
* .... .... .MMM CCCC CDDI IISV PPPB BBBB
*/
/* Input/Output mode:
*
* .... .... .MMM .... .... .... .... ....
*/
#define PIO_MODE_SHIFT (20) /* Bits 20-22: PIO mode */
#define PIO_MODE_MASK (7 << PIO_MODE_SHIFT)
# define PIO_INPUT (0 << PIO_MODE_SHIFT) /* Input */
# define PIO_OUTPUT (1 << PIO_MODE_SHIFT) /* Output */
# define PIO_PERIPHA (2 << PIO_MODE_SHIFT) /* Controlled by periph A signal */
# define PIO_PERIPHB (3 << PIO_MODE_SHIFT) /* Controlled by periph B signal */
# define PIO_PERIPHC (4 << PIO_MODE_SHIFT) /* Controlled by periph C signal */
# define PIO_PERIPHD (5 << PIO_MODE_SHIFT) /* Controlled by periph D signal */
/* These bits set the configuration of the pin:
* NOTE: No definitions for parallel capture mode
*
* .... .... .... CCCC C... .... .... ....
*/
#define PIO_CFG_SHIFT (15) /* Bits 15-19: PIO configuration bits */
#define PIO_CFG_MASK (31 << PIO_CFG_SHIFT)
# define PIO_CFG_DEFAULT (0 << PIO_CFG_SHIFT) /* Default, no attribute */
# define PIO_CFG_PULLUP (1 << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
# define PIO_CFG_PULLDOWN (2 << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
# define PIO_CFG_DEGLITCH (4 << PIO_CFG_SHIFT) /* Bit 17: Internal glitch filter */
# define PIO_CFG_OPENDRAIN (8 << PIO_CFG_SHIFT) /* Bit 18: Open drain */
# define PIO_CFG_SCHMITT (16 << PIO_CFG_SHIFT) /* Bit 19: Schmitt trigger */
/* Drive Strength:
*
* .... .... .... .... .DD. .... .... ....
*/
#define PIO_DRIVE_SHIFT (13) /* Bits 13-14: Drive strength */
#define PIO_DRIVE_MASK (7 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_LOW (0 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_MEDIUM (2 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_HIGH (3 << PIO_DRIVE_SHIFT)
/* Additional interrupt modes:
*
* .... .... .... .... ...I II.. .... ....
*/
#define PIO_INT_SHIFT (10) /* Bits 9-12: PIO interrupt bits */
#define PIO_INT_MASK (7 << PIO_INT_SHIFT)
# define _PIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
# define _PIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
# define _PIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
# define _PIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
# define _PIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
# define PIO_INT_HIGHLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_RH)
# define PIO_INT_LOWLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_FL)
# define PIO_INT_RISING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_RH)
# define PIO_INT_FALLING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_FL)
# define PIO_INT_BOTHEDGES (0)
/* If the pin is an interrupt, then this determines if the pin is a secure interrupt:
*
* .... .... .... .... .... ..S. .... ....
*/
#ifdef SAMA5_SAIC
# define PIO_INT_SECURE (1 << 9) /* Bit 9: Secure interrupt */
#else
# define PIO_INT_SECURE (0)
#endif
#define PIO_INT_UNSECURE (0)
/* If the pin is an PIO output, then this identifies the initial output value:
*
* .... .... .... .... .... ...V .... ....
*/
#define PIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */
#define PIO_OUTPUT_CLEAR (0)
/* This identifies the PIO port:
*
* .... .... .... .... .... .... PPP. ....
*/
#define PIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
#define PIO_PORT_MASK (7 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOA (0 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOB (1 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOC (2 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOD (3 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOE (4 << PIO_PORT_SHIFT)
/* This identifies the bit in the port:
*
* .... .... .... .... .... .... ...B BBBB
*/
#define PIO_PIN_SHIFT (0) /* Bits 0-4: PIO number: 0-31 */
#define PIO_PIN_MASK (31 << PIO_PIN_SHIFT)
#define PIO_PIN0 (0 << PIO_PIN_SHIFT)
#define PIO_PIN1 (1 << PIO_PIN_SHIFT)
#define PIO_PIN2 (2 << PIO_PIN_SHIFT)
#define PIO_PIN3 (3 << PIO_PIN_SHIFT)
#define PIO_PIN4 (4 << PIO_PIN_SHIFT)
#define PIO_PIN5 (5 << PIO_PIN_SHIFT)
#define PIO_PIN6 (6 << PIO_PIN_SHIFT)
#define PIO_PIN7 (7 << PIO_PIN_SHIFT)
#define PIO_PIN8 (8 << PIO_PIN_SHIFT)
#define PIO_PIN9 (9 << PIO_PIN_SHIFT)
#define PIO_PIN10 (10 << PIO_PIN_SHIFT)
#define PIO_PIN11 (11 << PIO_PIN_SHIFT)
#define PIO_PIN12 (12 << PIO_PIN_SHIFT)
#define PIO_PIN13 (13 << PIO_PIN_SHIFT)
#define PIO_PIN14 (14 << PIO_PIN_SHIFT)
#define PIO_PIN15 (15 << PIO_PIN_SHIFT)
#define PIO_PIN16 (16 << PIO_PIN_SHIFT)
#define PIO_PIN17 (17 << PIO_PIN_SHIFT)
#define PIO_PIN18 (18 << PIO_PIN_SHIFT)
#define PIO_PIN19 (19 << PIO_PIN_SHIFT)
#define PIO_PIN20 (20 << PIO_PIN_SHIFT)
#define PIO_PIN21 (21 << PIO_PIN_SHIFT)
#define PIO_PIN22 (22 << PIO_PIN_SHIFT)
#define PIO_PIN23 (23 << PIO_PIN_SHIFT)
#define PIO_PIN24 (24 << PIO_PIN_SHIFT)
#define PIO_PIN25 (25 << PIO_PIN_SHIFT)
#define PIO_PIN26 (26 << PIO_PIN_SHIFT)
#define PIO_PIN27 (27 << PIO_PIN_SHIFT)
#define PIO_PIN28 (28 << PIO_PIN_SHIFT)
#define PIO_PIN29 (29 << PIO_PIN_SHIFT)
#define PIO_PIN30 (30 << PIO_PIN_SHIFT)
#define PIO_PIN31 (31 << PIO_PIN_SHIFT)
/************************************************************************************
* Public Types
************************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t pio_pinset_t;
#endif /* __ARCH_ARM_SRC_SAMA5_SAMA5D3X4X_PIO_H */