Update README and TODO list

2026-06-06 00:14:22 +08:00 · 2015-06-25 13:39:57 -06:00
parent ae729d7a27
commit c1990bb2ea
1 changed files with 2 additions and 0 deletions
@@ -82,6 +82,8 @@
 * Yields:
 *
 *   PLLACK = 25 * 12MHz / 1 = 300MHz
 *
 * REVISIT: Isn't the actual multiplier = MUL+1?  Is this being overclocked at 312MHz?
 */
 #define BOARD_CKGR_PLLAR_STMODE    PMC_CKGR_PLLAR_STMODE_FAST