diff --git a/arch/xtensa/src/common/espressif/esp_openeth.c b/arch/xtensa/src/common/espressif/esp_openeth.c
index 5d261b0baab..8a8c072f9fe 100644
--- a/arch/xtensa/src/common/espressif/esp_openeth.c
+++ b/arch/xtensa/src/common/espressif/esp_openeth.c
@@ -30,10 +30,7 @@
 #include <netinet/if_ether.h>
 #include <nuttx/net/netdev_lowerhalf.h>
 
-#include "hardware/esp32_soc.h"
-#include "esp32_irq.h"
-
-#ifdef CONFIG_ESP32_OPENETH
+#include <chip.h>
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -43,7 +40,7 @@
 
 /* DMA buffers configuration */
 #define DMA_BUF_SIZE 1600
-#define RX_BUF_COUNT CONFIG_ESP32_OPENETH_DMA_RX_BUFFER_NUM
+
 /* Only need 1 TX buf because packets are transmitted immediately */
 #define TX_BUF_COUNT 1
 
@@ -462,8 +459,9 @@ int esp_openeth_initialize(void)
 
   if (REG_READ(OPENETH_MODER_REG) != OPENETH_MODER_DEFAULT)
     {
-      nerr("CONFIG_ESP32_OPENETH should only be used when running in QEMU.");
-      nerr("When running the app on the ESP32, use ESP32 EMAC instead.");
+      nerr("Openeth should only be used when running in QEMU.");
+      nerr("When running the app on the real hardware,"
+           "use the real MAC instead.");
       abort();
     }
 
@@ -512,8 +510,8 @@ int esp_openeth_initialize(void)
 
   /* Setup interrupts */
 
-  priv->cpuint = esp32_setup_irq(0, ESP32_PERIPH_EMAC,
-                                 1, ESP32_CPUINT_LEVEL);
+  priv->cpuint = OPENETH_SETUP_IRQ(0, OPENETH_PERIPH_MAC,
+                                 1, OPENETH_CPUINT_LEVEL);
   if (priv->cpuint < 0)
     {
       nerr("ERROR: Failed allocate interrupt\n");
@@ -531,7 +529,7 @@ int esp_openeth_initialize(void)
 
   /* Attach the interrupt */
 
-  ret = irq_attach(ESP32_IRQ_EMAC, openeth_isr_handler, priv);
+  ret = irq_attach(OPENETH_IRQ_MAC, openeth_isr_handler, priv);
 
   /* Register the device with the OS so that socket IOCTLs can be
    * performed.
@@ -552,5 +550,3 @@ err:
   nerr("Failed initializing ret = %d", ret);
   abort();
 }
-
-#endif /* CONFIG_ESP32_OPENETH */
diff --git a/arch/xtensa/src/esp32/chip.h b/arch/xtensa/src/esp32/chip.h
index 1fd16a250b0..47412cf93aa 100644
--- a/arch/xtensa/src/esp32/chip.h
+++ b/arch/xtensa/src/esp32/chip.h
@@ -30,10 +30,23 @@
 #include "chip_macros.h"
 #include "chip_memory.h"
 
+#if defined(CONFIG_ESP32_OPENETH) && !defined(__ASSEMBLY__)
+#include "hardware/esp32_soc.h"
+#include "esp32_irq.h"
+#endif
+
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
+#if defined(CONFIG_ESP32_OPENETH)
+#define OPENETH_PERIPH_MAC   ESP32_PERIPH_EMAC
+#define OPENETH_CPUINT_LEVEL ESP32_CPUINT_LEVEL
+#define OPENETH_IRQ_MAC      ESP32_IRQ_EMAC
+#define OPENETH_SETUP_IRQ    esp32_setup_irq
+#define RX_BUF_COUNT CONFIG_ESP32_OPENETH_DMA_RX_BUFFER_NUM
+#endif
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig
index 64968c3d813..e3793d0abf8 100644
--- a/arch/xtensa/src/esp32s3/Kconfig
+++ b/arch/xtensa/src/esp32s3/Kconfig
@@ -1658,6 +1658,27 @@ config ESP32S3_WIFI_LISTEN_INTERVAL
 
 endmenu # ESP32S3_WIFI
 
+config ESP32S3_OPENETH
+	bool "Opencores Ethernet MAC"
+	default n
+	depends on !ESP32S3_WIFI
+	select NET
+	select SCHED_WORKQUEUE
+	---help---
+		Enable ESP32S3 ethernet opencores support for use with QEMU.
+		Disable this if you are using the real device.
+
+if ESP32S3_OPENETH
+
+config ESP32S3_OPENETH_DMA_RX_BUFFER_NUM
+	int "Number of Ethernet DMA Rx buffers"
+	range 1 64
+	default 4
+	---help---
+		Number of DMA receive buffers, each buffer is 1600 bytes.
+
+endif # ESP32S3_OPENETH
+
 menu "BLE Configuration"
 	depends on ESP32S3_BLE
 
diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs
index 608a985129f..1e5ecdacd76 100644
--- a/arch/xtensa/src/esp32s3/Make.defs
+++ b/arch/xtensa/src/esp32s3/Make.defs
@@ -206,6 +206,10 @@ endif
 CHIP_CSRCS += esp32s3_pm.c
 endif
 
+ifeq ($(CONFIG_ESP32S3_OPENETH),y)
+CHIP_CSRCS += esp_openeth.c
+endif
+
 #############################################################################
 # Espressif HAL for 3rd Party Platforms
 #############################################################################
diff --git a/arch/xtensa/src/esp32s3/chip.h b/arch/xtensa/src/esp32s3/chip.h
index 725c54dd092..de74a17c482 100644
--- a/arch/xtensa/src/esp32s3/chip.h
+++ b/arch/xtensa/src/esp32s3/chip.h
@@ -30,10 +30,23 @@
 #include "chip_macros.h"
 #include "chip_memory.h"
 
+#if defined(CONFIG_ESP32S3_OPENETH) && !defined(__ASSEMBLY__)
+#include "hardware/esp32s3_soc.h"
+#include "esp32s3_irq.h"
+#endif
+
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
+#if defined(CONFIG_ESP32S3_OPENETH)
+#define OPENETH_PERIPH_MAC   ESP32S3_PERIPH_MAC
+#define OPENETH_CPUINT_LEVEL ESP32S3_CPUINT_LEVEL
+#define OPENETH_IRQ_MAC      ESP32S3_IRQ_MAC
+#define OPENETH_SETUP_IRQ    esp32s3_setup_irq
+#define RX_BUF_COUNT CONFIG_ESP32S3_OPENETH_DMA_RX_BUFFER_NUM
+#endif
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
index 35d026f37e8..47ca7321b9a 100644
--- a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
@@ -40,7 +40,7 @@
  ****************************************************************************/
 
 #define DR_REG_USB_BASE                         0x60080000
-
+#define DR_REG_EMAC_BASE                        0x600CD000
 #define DR_REG_ASSIST_DEBUG_BASE                0x600CE000
 #define DR_REG_WORLD_CNTL_BASE                  0x600D0000
 #define DR_REG_DPORT_END                        0x600D3FFC