diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S
index b5bab002203..bce82d50b58 100644
--- a/arch/arm/src/armv7-a/arm_head.S
+++ b/arch/arm/src/armv7-a/arm_head.S
@@ -505,14 +505,9 @@ __start:
 	/* Then write the configured control register */
 
 	mcr		CP15_SCTLR(r0)			/* Write control reg */
-
-	/* Read the Main ID register.  This will be available in R1 after
-	 * MMU trampoline (not currently used)
-	 */
-
-	mrc		CP15_MIDR(r1)			/* Read main id reg */
-	mov		r1, r1					/* Null-avoiding nop */
-	mov		r1, r1					/* Null-avoiding nop */
+	.rept	12						/* Cortex A8 wants lots of NOPs here */
+	nop
+	.endr
 
 	/* And "jump" to .Lvstart in the newly mapped virtual address space */
 
diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S
index a11570515c2..36497e75520 100644
--- a/arch/arm/src/armv7-a/arm_pghead.S
+++ b/arch/arm/src/armv7-a/arm_pghead.S
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/armv7-a/arm_pghead.S
  *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -491,14 +491,9 @@ __start:
 	/* Then write the configured control register */
 
 	mcr		CP15_SCTLR(r0)			/* Write control reg */
-
-	/* Read the Main ID register.  This will be available in R1 after
-	 * MMU trampoline (not currently used)
-	 */
-
-	mrc		CP15_MIDR(r1)			/* Read main id reg */
-	mov		r1, r1					/* Null-avoiding nop */
-	mov		r1, r1					/* Null-avoiding nop */
+	.rept	12						/* Cortex A8 wants lots of NOPs here */
+	nop
+	.endr
 
 	/* And "jump" to .Lvstart in the newly mapped virtual address space */