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stm32: stm32l15xx_rcc: add support for using MSI as system clock

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This commit is contained in:
Juha Niskanen
2017-04-05 07:15:19 -06:00
committed by Gregory Nutt
parent c543185123
commit bff341fdfc
1 changed files with 11 additions and 6 deletions
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arch/arm/src/stm32/stm32l15xxx_rcc.c
+11 -6
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@@ -579,12 +579,11 @@ static void stm32_stdclockconfig(void)
#endif #endif
/* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. /* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. */
* NOTE that only PLL, HSE, or HSI are supported for the system clock
* in this implementation #if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \
*/ ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC))
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
/* The PLL is using the HSE, or the HSE is the system clock. In either /* The PLL is using the HSE, or the HSE is the system clock. In either
* case, we need to enable HSE clocking. * case, we need to enable HSE clocking.
*/ */
@@ -599,7 +598,9 @@ static void stm32_stdclockconfig(void)
return; return;
} }
#elif (STM32_CFGR_PLLSRC == 0) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) #elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_CFGR_PLLSRC == 0)
/* The PLL is using the HSI, or the HSI is the system clock. In either /* The PLL is using the HSI, or the HSI is the system clock. In either
* case, we need to enable HSI clocking. * case, we need to enable HSI clocking.
*/ */
@@ -616,6 +617,8 @@ static void stm32_stdclockconfig(void)
#endif #endif
#if (STM32_SYSCLK_SW != RCC_CFGR_SW_MSI)
/* Increasing the CPU frequency (in the same voltage range): /* Increasing the CPU frequency (in the same voltage range):
* *
* After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the * After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the
@@ -651,6 +654,8 @@ static void stm32_stdclockconfig(void)
regval |= FLASH_ACR_PRFTEN; regval |= FLASH_ACR_PRFTEN;
putreg32(regval, STM32_FLASH_ACR); putreg32(regval, STM32_FLASH_ACR);
#endif /* STM32_SYSCLK_SW != RCC_CFGR_SW_MSI */
/* Set the HCLK source/divider */ /* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR); regval = getreg32(STM32_RCC_CFGR);