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Fix typos in comments and documentation (#750)

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* Fix typos in comments and documentation
This commit is contained in:
hartmannathan
2020-04-08 08:45:35 -04:00
committed by GitHub
parent 9c7841aff1
commit bfc153ca27
54 changed files with 133 additions and 134 deletions
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boards/Kconfig
+6 -6
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@@ -179,10 +179,10 @@ config ARCH_BOARD_EKKLM3S9B96
an EKK-LM3S9B96 which is a Cortex-M3.
config ARCH_BOARD_ESP32CORE
bool "Expressif ESP32 Core board V2"
bool "Espressif ESP32 Core board V2"
depends on ARCH_CHIP_ESP32
---help---
The ESP32 is a dual-core system from Expressif with two Harvard
The ESP32 is a dual-core system from Espressif with two Harvard
architecture Xtensa LX6 CPUs. All embedded memory, external memory
and peripherals are located on the data bus and/or the instruction
bus of these CPUs. With some minor exceptions, the address mapping
@@ -568,7 +568,7 @@ config ARCH_BOARD_MAKERLISP
depends on ARCH_CHIP_EZ80F91
select ARCH_HAVE_LEDS
---help---
ez80Acclaim! Microcontroller. This port use the MakerLips machine
ez80Acclaim! Microcontroller. This port use the MakerLisp machine
based on an eZ80F091 part, and the Zilog ZDS-II Windows command line
tools. The development environment is Cygwin under Windows. A
Windows native development environment is available but has not
@@ -1205,13 +1205,13 @@ config ARCH_BOARD_QEMU_I486
depends on ARCH_X86 || ARCH_I486
---help---
Port of NuttX to QEMU in i486 mode. This port will also run on real i486
hardwared (Google the Bifferboard).
hardware (Google the Bifferboard).
config ARCH_BOARD_INTEL64_QEMU
bool "Intel64 for Qemu simulator"
depends on ARCH_X86_64 || ARCH_INTEL64
---help---
Port of NuttX to QEMU in intel64 mode. This port will also run on real
Port of NuttX to QEMU in intel64 mode. This port will also run on real
generic Intel64 hardware.
config ARCH_BOARD_RX65N
@@ -1732,7 +1732,7 @@ config ARCH_BOARD_STM32L476_MDK
select ARCH_HAVE_IRQBUTTONS
---help---
Motorola Mods Development Board (MDK) features STM32L476ME MCU.
The STM32L476ME is a Cortex-M4 optimised for low-power operation
The STM32L476ME is a Cortex-M4 optimised for low-power operation
at up to 80MHz operation with 1024Kb Flash memory and 96+32Kb SRAM.
config ARCH_BOARD_STM32L_DISCOVERY
boards/README.txt
+13 -14
View File
@@ -167,7 +167,7 @@ http://nuttx.org/Documentation/NuttXConfigVariables.html.
Supported Boards
^^^^^^^^^^^^^^^^
boards/avr/atmeta/amber
boards/avr/atmega/amber
This is placeholder for the SoC Robotics Amber Web Server that is based
on the Atmel AVR ATMega128 MCU. There is not much there yet and what is
there is untested due to tool-related issues.
@@ -255,12 +255,11 @@ boards/arm/tiva/ekk-lm3s9b96
an EKK-LM3S9B96 which is a Cortex-M3.
boards/xtensa/esp32/esp-core
The ESP32 is a dual-core system from Expressif with two Harvard
architecture Xtensa LX6 CPUs. All embedded memory, external memory and
nd peripherals are located on the data bus and/or the instruction bus of
bus of these CPUs. With some minor exceptions, the address mapping of two
CPUs is symmetric, meaning they use the same addresses to access the same
memory.
The ESP32 is a dual-core system from Espressif with two Harvard architecture
Xtensa LX6 CPUs. All embedded memory, external memory and peripherals are
located on the data bus and/or the instruction bus of bus of these CPUs.
With some minor exceptions, the address mapping of two CPUs is symmetric,
meaning they use the same addresses to access the same memory.
boards/z80/ez80/ez80f0910200kitg
ez80Acclaim! Microcontroller. This port use the Zilog ez80f0910200kitg
@@ -278,11 +277,11 @@ boards/arm/stm32/fire-stm32v2
the boards are supported but only version 2 has been tested.
boards/mips/pic32mz/flipnclick-pic32mz
Board support for the Mikroe Flip&Click PIC32MZ board. This board is an
Board support for the Mikroe Flip&Click PIC32MZ board. This board is a
chipKit Arduino-compatible board (but can also be used with the Mikroe
bootloader). It has with four Mikroe Click bus interfaces in addition to
standard Arduino connectors. This board features the Microchip
PIC32MZ2048EFH100 MCU running at 200 MHz (252Mhz capable).
PIC32MZ2048EFH100 MCU running at 200 MHz (252 MHz capable).
boards/arm/sam34/flipnclick-sam3x
Board support for the Mikroe Flip&Click STM32X board. This board is an
@@ -372,7 +371,7 @@ boards/arm/lpc17xx_40xx/lx_cpu
LPC1788) and Xilinx Spartan 6 XC6SLX9
boards/z80/ez80/makerlisp
This port use the MakerLips machine based on an eZ80F091 ez80Acclaim!
This port use the MakerLisp machine based on an eZ80F091 ez80Acclaim!
Microcontroller, and the Zilog ZDS-II Windows command line tools. The
development environment is Cygwin under Windows. A Windows native
development environment is available but has not been verified.
@@ -623,7 +622,7 @@ boards/arm/lpc17xx_40xx/pnev5180b
boards/x86/qemu/qemu-i486
Port of NuttX to QEMU in i486 mode. This port will also run on real i486
hardwared (Google the Bifferboard).
hardware (Google the Bifferboard).
boards/risc-v/nr5m100/nr5m100-nexys4
Port of NuttX to RISC-V platform on IQ-Analog NR5M100 RISC-V FPGA platform.
@@ -752,7 +751,7 @@ boards/arm/stm32/stm32f103-minimum
Generic STM32F103C8T6 Minimum ARM Development Board.
boards/arm/stm32/stm32f4discovery
STMicro STM32F4-Discovery board based on the STMIcro STM32F407VGT6 MCU.
STMicro STM32F4-Discovery board based on the STMicro STM32F407VGT6 MCU.
boards/arm/stm32/stm32f411e-disco
This is a minimal configuration that supports low-level test of the
@@ -771,7 +770,7 @@ boards/arm/stm32f7/stm32f746g-ws
boards/arm/stm32l4/stm32l476-mdk
Motorola Mods Development Board (MDK) features STM32L476ME MCU.
The STM32L476ME is a Cortex-M4 optimised for low-power operation
The STM32L476ME is a Cortex-M4 optimised for low-power operation
at up to 80MHz operation with 1024Kb Flash memory and 96+32Kb SRAM.
boards/arm/stm32f7/stm32f769i-disco
@@ -922,7 +921,7 @@ tools/configure.sh
See tools/README.txt for more information about these scripts.
And if your application directory is not in the standard loction (../apps
And if your application directory is not in the standard location (../apps
or ../apps-<version>), then you should also specify the location of the
application directory on the command line like:
boards/arm/imxrt/imxrt1020-evk/include/board.h
+1 -1
View File
@@ -63,7 +63,7 @@
* 528Mhz = (24Mhz * 22) / 1
*
* AHB_CLOCK_ROOT = PLL6fOut / IMXRT_AHB_PODF_DIVIDER
* 1Hz to 500 Mhz = Mhz / IMXRT_ARM_CLOCK_DIVIDER
* 1Hz to 500 MHz = MHz / IMXRT_ARM_CLOCK_DIVIDER
* IMXRT_ARM_CLOCK_DIVIDER = 1
* 500Mhz = 500Mhz / 1
*
boards/arm/imxrt/imxrt1050-evk/include/board.h
+1 -1
View File
@@ -63,7 +63,7 @@
* 600Mhz = (24Mhz * 100/2) / 2
*
* AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER
* 1Hz to 600 Mhz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
* 1Hz to 600 MHz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
* IMXRT_ARM_CLOCK_DIVIDER = 1
* 600Mhz = 600Mhz / 1
*
boards/arm/imxrt/imxrt1060-evk/include/board.h
+1 -1
View File
@@ -63,7 +63,7 @@
* 600Mhz = (24Mhz * 100/2) / 2
*
* AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER
* 1Hz to 600 Mhz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
* 1Hz to 600 MHz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
* IMXRT_ARM_CLOCK_DIVIDER = 1
* 600Mhz = 600Mhz / 1
*
boards/arm/kinetis/freedom-k64f/include/board.h
+2 -2
View File
@@ -70,8 +70,8 @@
* a KINETIS_MCG_PLL_REF_MIN >= PLLIN <= KINETIS_MCG_PLL_REF_MIN reference
* clock to the PLL.
*
* PLL Input frequency: PLLIN = REFCLK / PRDIV = 50 Mhz / 20 = 2.5 MHz
* PLL Output frequency: PLLOUT = PLLIN * VDIV = 2.5 Mhz * 48 = 120 MHz
* PLL Input frequency: PLLIN = REFCLK / PRDIV = 50 MHz / 20 = 2.5 MHz
* PLL Output frequency: PLLOUT = PLLIN * VDIV = 2.5 MHz * 48 = 120 MHz
* MCG Frequency: PLLOUT = 120 MHz
*
* PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE.
boards/arm/kinetis/freedom-k66f/include/board.h
+6 -6
View File
@@ -74,9 +74,9 @@
* KINETIS_MCG_PLL_REF_MIN >= PLLIN <=KINETIS_MCG_PLL_REF_MAX reference
* clock to the PLL.
*
* PLL Input frequency: PLLIN = REFCLK / PRDIV = 12 Mhz / 1 = 12 MHz
* PLL Output frequency: PLLOUT = PLLIN * VDIV = 12 Mhz * 30 = 360 MHz
* MCG Frequency: PLLOUT = 180 Mhz = 360 MHz /
* PLL Input frequency: PLLIN = REFCLK / PRDIV = 12 MHz / 1 = 12 MHz
* PLL Output frequency: PLLOUT = PLLIN * VDIV = 12 MHz * 30 = 360 MHz
* MCG Frequency: PLLOUT = 180 MHz = 360 MHz /
* KINETIS_MCG_PLL_INTERNAL_DIVBY
*
* PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE.
@@ -114,7 +114,7 @@
#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK
#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ
/* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 Mhz Xtal
/* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 MHz Xtal
* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
* SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ]
* 48Mhz = 168Mhz X [(1 + 1) / (6 + 1)]
@@ -131,8 +131,8 @@
/* Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1))
* SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)]
* 90 Mhz = 180 Mhz X [(0 + 1) / (1 + 1)]
* 90 Mhz = 180 Mhz / (1 + 1) * (0 + 1)
* 90 MHz = 180 MHz X [(0 + 1) / (1 + 1)]
* 90 MHz = 180 MHz / (1 + 1) * (0 + 1)
*/
#define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1
boards/arm/kinetis/teensy-3.x/include/board.h
+1 -1
View File
@@ -92,7 +92,7 @@
*
* Board can be overclocked at 96MHz (per PJRC.com)
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = Mhz*48 = 96MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = MHz*48 = 96MHz
* MCG Frequency: PLLOUT = 96MHz
*/
boards/arm/kinetis/twr-k64f120m/include/board.h
+1 -1
View File
@@ -64,7 +64,7 @@
*
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 50MHz/20 = 2.5 MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2.5Mhz*48 = 120MHz
* MCG Frequency: PLLOUT = 120 Mhz
* MCG Frequency: PLLOUT = 120 MHz
*/
#define BOARD_PRDIV 20 /* PLL External Reference Divider */
boards/arm/str71x/olimex-strp711/README.txt
+1 -1
View File
@@ -46,7 +46,7 @@ Olimex STR-P711
- Power supply filtering capacitor
- RESET circuit
- RESET button
- 4 Mhz crystal oscillator
- 4 MHz crystal oscillator
- 32768 Hz crystal and RTC
Power Supply
boards/arm/str71x/olimex-strp711/include/board.h
+1 -1
View File
@@ -58,7 +58,7 @@
* - Power supply filtering capacitor
* - RESET circuit
* - RESET button
* - 4 Mhz crystal oscillator
* - 4 MHz crystal oscillator
* - 32768 Hz crystal and RTC
*
****************************************************************************/
boards/avr/atmega/amber/README.txt
+1 -1
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@@ -345,7 +345,7 @@ Build Notes:
cd avr-lib-1.7.1
3. Configure avr-lib. Assuming that WinAVR is installed at the following
loction:
location:
export PATH=/cygdrive/c/WinAVR/bin:$PATH
./configure --build=`./config.guess` --host=avr
boards/risc-v/nr5m100/nr5m100-nexys4/README.txt
+2 -2
View File
@@ -67,13 +67,13 @@ Development Environment
cores require a separate I and D bus with cache SRAM and an external memory cache controller,
etc. This in addition to the pipeline registers adds additional gate count.
The nr5m100-nexys4 core runs at 83.333 Mhz which provides about 18 Mhz effective operating
The nr5m100-nexys4 core runs at 83.333 MHz which provides about 18 MHz effective operating
speed with the multi-clock per instruction architecture. If you are looking for a higher
performance platform, you should check out the PULP Platform ( http://www.pulp-platform.org ).
That is an FPGA design with a 4-stage pipeline RISC-V core, though not currently supported
by NuttX. The NR5M100 project will likely pull in the RISC-V core from that design next,
though this will probably not be available soon. With a bit of work, it is possible to
run the nr5m100-nexys4 core at 170 Mhz with a 6.5 clocks-per-instruction state machine.
run the nr5m100-nexys4 core at 170 MHz with a 6.5 clocks-per-instruction state machine.
This would give an effective performance of about 26Mhz.
Development Environment
boards/xtensa/esp32/esp32-core/README.txt
+4 -4
View File
@@ -1,7 +1,7 @@
README for the Expressif ESP32 Core board (V2)
README for the Espressif ESP32 Core board (V2)
==============================================
The ESP32 is a dual-core system from Expressif with two Harvard
The ESP32 is a dual-core system from Espressif with two Harvard
architecture Xtensa LX6 CPUs. All embedded memory, external memory and
peripherals are located on the data bus and/or the instruction bus of
these CPUs. With some minor exceptions, the address mapping of two CPUs
@@ -173,7 +173,7 @@ Memory Map
IRAM for PRO cpu: 0x40080000 0x400a0000 RX iram0_0_seg
- Interrupt Vectors
- Low level handlers
- Xtensa/Expressif libraries
- Xtensa/Espressif libraries
RTC fast memory: 0x400c0000 0x400c2000 RWX rtc_iram_seg (PRO_CPU only)
- .rtc.text (unused?)
FLASH: 0x400d0018 0x40400018 RX iram0_2_seg (actually FLASH)
@@ -752,7 +752,7 @@ Things to Do
1. There is no support for an interrupt stack yet.
2. There is no clock initialization logic in place. This depends on logic in
Expressif libriaries. The board comes up using that basic 40 Mhz crystal
Espressif libraries. The board comes up using that basic 40 MHz crystal
for clocking. Getting to 80 MHz will require clocking initialization in
esp32_clockconfig.c.