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SAMD21: Update SAMD SYSCTRL and NVMCTRL definitions for the SAMD21

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This commit is contained in:
Gregory Nutt
2015-06-21 11:40:23 -06:00
parent 0546eb7d04
commit bf40b36a27
5 changed files with 334 additions and 205 deletions
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arch/arm/src/samdl/chip/samd_fuses.h
+1 -1
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@@ -10,7 +10,7 @@
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller * "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015 * Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* *
* Fuse-related definitions derive from Atmel sample code: * Some fuse-related definitions derive from Atmel sample code:
* *
* Copyright (c) 2013 Atmel Corporation. All rights reserved. * Copyright (c) 2013 Atmel Corporation. All rights reserved.
* *
arch/arm/src/samdl/chip/samd_nvmctrl.h
+17 -2
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@@ -7,6 +7,8 @@
* References: * References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013 * Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@@ -48,7 +50,7 @@
#include "chip.h" #include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD20 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/******************************************************************************************** /********************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
@@ -87,6 +89,14 @@
# define NVMCTRL_CTRLA_CMD_WP (0x04 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Page */ # define NVMCTRL_CTRLA_CMD_WP (0x04 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Page */
# define NVMCTRL_CTRLA_CMD_EAR (0x05 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Auxiliary Row */ # define NVMCTRL_CTRLA_CMD_EAR (0x05 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Auxiliary Row */
# define NVMCTRL_CTRLA_CMD_WAP (0x06 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Auxiliary Page */ # define NVMCTRL_CTRLA_CMD_WAP (0x06 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Auxiliary Page */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define NVMCTRL_CTRLA_CMD_SF (0x0a << NVMCTRL_CTRLA_CMD_SHIFT) /* Security Flow Command */
# define NVMCTRL_CTRLA_CMD_WL (0x0f << NVMCTRL_CTRLA_CMD_SHIFT) /* Write lockbits */
# define NVMCTRL_CTRLA_CMD_RWWEEER (0x1a << NVMCTRL_CTRLA_CMD_SHIFT) /* RWWEE Erase Row */
# define NVMCTRL_CTRLA_CMD_RWWEEEP (0x1c << NVMCTRL_CTRLA_CMD_SHIFT) /* RWWEE Write Page */
#endif
# define NVMCTRL_CTRLA_CMD_LR (0x40 << NVMCTRL_CTRLA_CMD_SHIFT) /* Lock Region */ # define NVMCTRL_CTRLA_CMD_LR (0x40 << NVMCTRL_CTRLA_CMD_SHIFT) /* Lock Region */
# define NVMCTRL_CTRLA_CMD_UR (0x41 << NVMCTRL_CTRLA_CMD_SHIFT) /* Unlock Region */ # define NVMCTRL_CTRLA_CMD_UR (0x41 << NVMCTRL_CTRLA_CMD_SHIFT) /* Unlock Region */
# define NVMCTRL_CTRLA_CMD_SPRM (0x42 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set power reduction mode */ # define NVMCTRL_CTRLA_CMD_SPRM (0x42 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set power reduction mode */
@@ -132,6 +142,11 @@
# define NVMCTRL_PARAM_PSZ_512B (6 << NVMCTRL_PARAM_PSZ_SHIFT) /* 512 bytes */ # define NVMCTRL_PARAM_PSZ_512B (6 << NVMCTRL_PARAM_PSZ_SHIFT) /* 512 bytes */
# define NVMCTRL_PARAM_PSZ_1KB (7 << NVMCTRL_PARAM_PSZ_SHIFT) /* 1024 bytes */ # define NVMCTRL_PARAM_PSZ_1KB (7 << NVMCTRL_PARAM_PSZ_SHIFT) /* 1024 bytes */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define NVMCTRL_PARAM_RWWEEP_SHIFT (20) /* Bits 20-31: Read whle write EEPROM emulation area pages */
# define NVMCTRL_PARAM_RWWEEP_MASK (0xfff << NVMCTRL_PARAM_RWWEEP_SHIFT)
#endif
/* Interrupt clear register */ /* Interrupt clear register */
/* Interrupt set register */ /* Interrupt set register */
/* Interface flags status and clear register */ /* Interface flags status and clear register */
@@ -168,5 +183,5 @@
* Public Functions * Public Functions
********************************************************************************************/ ********************************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 */ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_NVMCTRL_H */ #endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_NVMCTRL_H */
arch/arm/src/samdl/chip/samd_sysctrl.h
+121 -7
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@@ -7,6 +7,8 @@
* References: * References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013 * Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@@ -48,7 +50,7 @@
#include "chip.h" #include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD20 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/******************************************************************************************** /********************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
@@ -69,8 +71,20 @@
#define SAM_SYSCTRL_DFLLMUL_OFFSET 0x002c /* DFLL48M multiplier */ #define SAM_SYSCTRL_DFLLMUL_OFFSET 0x002c /* DFLL48M multiplier */
#define SAM_SYSCTRL_DFLLSYNC_OFFSET 0x0030 /* DFLL48M synchronization */ #define SAM_SYSCTRL_DFLLSYNC_OFFSET 0x0030 /* DFLL48M synchronization */
#define SAM_SYSCTRL_BOD33_OFFSET 0x0034 /* 3.3V brown-out detector control */ #define SAM_SYSCTRL_BOD33_OFFSET 0x0034 /* 3.3V brown-out detector control */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SYSCTRL_VREG_OFFSET 0x003c /* Voltage regulator system control */
#endif
#define SAM_SYSCTRL_VREF_OFFSET 0x0040 /* Voltage references system control */ #define SAM_SYSCTRL_VREF_OFFSET 0x0040 /* Voltage references system control */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SYSCTRL_DPLLCTRLA_OFFSET 0x0044 /* DPLL Control A */
# define SAM_SYSCTRL_DPLLRATIO_OFFSET 0x0048 /* DPLL ratio control */
# define SAM_SYSCTRL_DPLLCTRLB_OFFSET 0x0048 /* DPLL Control B */
# define SAM_SYSCTRL_DPLLSTATUS_OFFSET 0x0048 /* DPLL status */
#endif
/* SYSCTRL register addresses ***************************************************************/ /* SYSCTRL register addresses ***************************************************************/
#define SAM_SYSCTRL_INTENCLR (SAM_SYSCTRL_BASE+SAM_SYSCTRL_INTENCLR_OFFSET) #define SAM_SYSCTRL_INTENCLR (SAM_SYSCTRL_BASE+SAM_SYSCTRL_INTENCLR_OFFSET)
@@ -87,8 +101,20 @@
#define SAM_SYSCTRL_DFLLMUL (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DFLLMUL_OFFSET) #define SAM_SYSCTRL_DFLLMUL (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DFLLMUL_OFFSET)
#define SAM_SYSCTRL_DFLLSYNC (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DFLLSYNC_OFFSET) #define SAM_SYSCTRL_DFLLSYNC (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DFLLSYNC_OFFSET)
#define SAM_SYSCTRL_BOD33 (SAM_SYSCTRL_BASE+SAM_SYSCTRL_BOD33_OFFSET) #define SAM_SYSCTRL_BOD33 (SAM_SYSCTRL_BASE+SAM_SYSCTRL_BOD33_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SYSCTRL_VREG (SAM_SYSCTRL_BASE+SAM_SYSCTRL_VREG_OFFSET)
#endif
#define SAM_SYSCTRL_VREF (SAM_SYSCTRL_BASE+SAM_SYSCTRL_VREF_OFFSET) #define SAM_SYSCTRL_VREF (SAM_SYSCTRL_BASE+SAM_SYSCTRL_VREF_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SYSCTRL_DPLLCTRLA (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLCTRLA_OFFSET)
# define SAM_SYSCTRL_DPLLRATIO (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLRATIO_OFFSET)
# define SAM_SYSCTRL_DPLLCTRLB (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLCTRLB_OFFSET)
# define SAM_SYSCTRL_DPLLSTATUS (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLSTATUS_OFFSET)
#endif
/* SYSCTRL register bit definitions *********************************************************/ /* SYSCTRL register bit definitions *********************************************************/
/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and /* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and
@@ -107,11 +133,20 @@
#define SYSCTRL_INT_BOD33RDY (1 << 9) /* Bit 9: BOD33 ready interrupt */ #define SYSCTRL_INT_BOD33RDY (1 << 9) /* Bit 9: BOD33 ready interrupt */
#define SYSCTRL_INT_BOD33DET (1 << 10) /* Bit 10: BOD33 detection interrupt */ #define SYSCTRL_INT_BOD33DET (1 << 10) /* Bit 10: BOD33 detection interrupt */
#define SYSCTRL_INT_B33SRDY (1 << 11) /* Bit 11: BOD33 synchronization ready interrupt */ #define SYSCTRL_INT_B33SRDY (1 << 11) /* Bit 11: BOD33 synchronization ready interrupt */
#define SYSCTRL_INT_BOD12RDY (1 << 12) /* Bit 12: BOD12 ready interrupt */
#define SYSCTRL_INT_BOD12DET (1 << 13) /* Bit 13: BOD12 detection interrupt */
#define SYSCTRL_INT_B12SRDY (1 << 14) /* Bit 14: BOD12 synchronization ready interrupt */
#define SYSCTRL_INT_ALL (0x00007fff) #if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SYSCTRL_INT_BOD12RDY (1 << 12) /* Bit 12: BOD12 ready interrupt */
# define SYSCTRL_INT_BOD12DET (1 << 13) /* Bit 13: BOD12 detection interrupt */
# define SYSCTRL_INT_B12SRDY (1 << 14) /* Bit 14: BOD12 synchronization ready interrupt */
# define SYSCTRL_INT_ALL (0x00007fff)
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SYSCTRL_INT_DPLLLCKR (1 << 15) /* Bit 15: DPLL lock rise interrupt */
# define SYSCTRL_INT_DPLLLCKF (1 << 16) /* Bit 16: DPLL lock fall interrupt */
# define SYSCTRL_INT_DPLLLTO (1 << 17) /* Bit 17: DPLL lock timeout interrupt */
# define SYSCTRL_INT_ALL (0x00038fff)
#endif
/* External multi-purpose crystal oscillator control register */ /* External multi-purpose crystal oscillator control register */
@@ -174,7 +209,11 @@
#define SYSCTRL_OSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */ #define SYSCTRL_OSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define SYSCTRL_OSC32K_EN32K (1 << 2) /* Bit 2: 32kHz Output enable */ #define SYSCTRL_OSC32K_EN32K (1 << 2) /* Bit 2: 32kHz Output enable */
#define SYSCTRL_OSC32K_EN1K (1 << 3) /* Bit 3: 1kHz Output enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SYSCTRL_OSC32K_EN1K (1 << 3) /* Bit 3: 1kHz Output enable */
#endif
#define SYSCTRL_OSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define SYSCTRL_OSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SYSCTRL_OSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */ #define SYSCTRL_OSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define SYSCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */ #define SYSCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
@@ -229,10 +268,21 @@
#define SYSCTRL_DFLLCTRL_MODE (1 << 2) /* Bit 2: Operating mode selection */ #define SYSCTRL_DFLLCTRL_MODE (1 << 2) /* Bit 2: Operating mode selection */
#define SYSCTRL_DFLLCTRL_STABLE (1 << 3) /* Bit 3: Stable DFLL frequency */ #define SYSCTRL_DFLLCTRL_STABLE (1 << 3) /* Bit 3: Stable DFLL frequency */
#define SYSCTRL_DFLLCTRL_LLAW (1 << 4) /* Bit 4: Lose lock after wake */ #define SYSCTRL_DFLLCTRL_LLAW (1 << 4) /* Bit 4: Lose lock after wake */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DFLLCTRL_USBCRM (1 << 5) /* Bit 5: USB clock recovery mode */
# define SYSCTRL_DFLLCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#endif
#define SYSCTRL_DFLLCTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */ #define SYSCTRL_DFLLCTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define SYSCTRL_DFLLCTRL_CCDIS (1 << 8) /* Bit 8: Chill cycle disable */ #define SYSCTRL_DFLLCTRL_CCDIS (1 << 8) /* Bit 8: Chill cycle disable */
#define SYSCTRL_DFLLCTRL_QLDIS (1 << 9) /* Bit 9: Quick Lock Disable */ #define SYSCTRL_DFLLCTRL_QLDIS (1 << 9) /* Bit 9: Quick Lock Disable */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DFLLCTRL_BPLCKC (1 << 10) /* Bit 10: Bypass coards lock */
# define SYSCTRL_DFLLCTRL_WAITLOCK (1 << 11) /* Bit 11: Wait lock */
#endif
/* DFLL48M value register */ /* DFLL48M value register */
#define SYSCTRL_DFLLVAL_FINE_SHIFT (0) /* Bits 0-9: Fine value */ #define SYSCTRL_DFLLVAL_FINE_SHIFT (0) /* Bits 0-9: Fine value */
@@ -297,6 +347,13 @@
#define SYSCTRL_BOD33_LEVEL_MASK (0x3f << SYSCTRL_BOD33_LEVEL_SHIFT) #define SYSCTRL_BOD33_LEVEL_MASK (0x3f << SYSCTRL_BOD33_LEVEL_SHIFT)
# define SYSCTRL_BOD33_LEVEL(n) ((n) << SYSCTRL_BOD33_LEVEL_SHIFT) # define SYSCTRL_BOD33_LEVEL(n) ((n) << SYSCTRL_BOD33_LEVEL_SHIFT)
/* Voltage regulator system control register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_VREG_RUNSTDBY (1 << 6) /* Bit 6: Run in Standby */
# define SYSCTRL_VREG_FORCELDO (1 << 13) /* Bit 13: Force LDO voltage regulator */
#endif
/* Voltage references system control register */ /* Voltage references system control register */
#define SYSCTRL_VREF_TSEN (1 << 1) /* Bit 1: Temperature sensor enable */ #define SYSCTRL_VREF_TSEN (1 << 1) /* Bit 1: Temperature sensor enable */
@@ -305,6 +362,63 @@
#define SYSCTRL_VREF_CALIB_MASK (0x7ff << SYSCTRL_VREF_CALIB_SHIFT) #define SYSCTRL_VREF_CALIB_MASK (0x7ff << SYSCTRL_VREF_CALIB_SHIFT)
# define SYSCTRL_VREF_CALIB(n) ((n) << SYSCTRL_VREF_CALIB_SHIFT) # define SYSCTRL_VREF_CALIB(n) ((n) << SYSCTRL_VREF_CALIB_SHIFT)
/* DPLL Control A register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DPLLCTRLA_ENABLE (1 << 1) /* Bit 1: DPLL Enable */
# define SYSCTRL_DPLLCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in Standby */
# define SYSCTRL_DPLLCTRLA_ONDEMAND (1 << 7) /* Bit 7: On Demand Clock Activation */
#endif
/* DPLL ratio control registers */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DPLLRATIO_LDR_SHIFT (0) /* Bits 0-11: Loop Divider Ratio */
# define SYSCTRL_DPLLRATIO_LDR_MASK (0xfff << SYSCTRL_DPLLRATIO_LDR_SHIFT)
# define SYSCTRL_DPLLRATIO_LDR(n) ((uint32_t)(n) << SYSCTRL_DPLLRATIO_LDR_SHIFT)
# define SYSCTRL_DPLLRATIO_LDRFRAC_SHIFT (16) /* Bits 16-19: Loop Divider Ratio Fractional Part */
# define SYSCTRL_DPLLRATIO_LDRFRAC_MASK (15 << SYSCTRL_DPLLRATIO_LDRFRAC_SHIFT)
# define SYSCTRL_DPLLRATIO_LDRFRAC(n) ((uint32_t)(n) << SYSCTRL_DPLLRATIO_LDRFRAC_SHIFT)
#endif
/* DPLL Control B register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DPLLCTRLB_FILTER_SHIFT (0) /* Bits 0-1: Proportional Integral Filter Selection */
# define SYSCTRL_DPLLCTRLB_FILTER_MASK (3 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT)
# define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (0 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* Default filter mode */
# define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (1 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* Low bandwidth filter */
# define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (2 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* High bandwidth filter */
# define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (3 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* High damping filter */
# define SYSCTRL_DPLLCTRLB_LPEN (1 << 2) /* Bit 2: Low-Power Enable */
# define SYSCTRL_DPLLCTRLB_WUF (1 << 3) /* Bit 3: Wake Up Fast */
# define SYSCTRL_DPLLCTRLB_REFCLK_SHIFT (4) /* Bits 4-5: Reference Clock Selection */
# define SYSCTRL_DPLLCTRLB_REFCLK_MASK (3 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT)
# define SYSCTRL_DPLLCTRLB_REFCLK_XOSC32 (0 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* XOSC32 clock reference */
# define SYSCTRL_DPLLCTRLB_REFCLK_XOSC (1 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* XOSC clock reference */
# define SYSCTRL_DPLLCTRLB_REFCLK_GCLKDPLL (2 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* GCLK_DPLL clock reference */
# define SYSCTRL_DPLLCTRLB_LTIME_SHIFT (8) /* Bits 8-10: Lock Time */
# define SYSCTRL_DPLLCTRLB_LTIME_MASK (7 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT)
# define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (0 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* No time-out */
# define SYSCTRL_DPLLCTRLB_LTIME_8MS (4 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 8 ms */
# define SYSCTRL_DPLLCTRLB_LTIME_9MS (5 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 9 ms */
# define SYSCTRL_DPLLCTRLB_LTIME_10MS (6 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 10 ms */
# define SYSCTRL_DPLLCTRLB_LTIME_11MS (7 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 11 ms */
# define SYSCTRL_DPLLCTRLB_LBYPASS (1 << 12) /* Bit 12: Lock Bypass */
# define SYSCTRL_DPLLCTRLB_DIV_SHIFT (16) /* Bits 16-26: */
# define SYSCTRL_DPLLCTRLB_DIV_MASK (0x7ff << SYSCTRL_DPLLCTRLB_DIV_SHIFT)
# define SYSCTRL_DPLLCTRLB_DIV(n) ((uint32_t)(n) << SYSCTRL_DPLLCTRLB_DIV_SHIFT)
#endif
/* DPLL status register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DPLLSTATUS_LOCK (1 << 0) /* Bit 0: DPLL Lock Status */
# define SYSCTRL_DPLLSTATUS_CLKRDY (1 << 1) /* Bit 1: Output Clock Ready */
# define SYSCTRL_DPLLSTATUS_ENABLE (1 << 2) /* Bit 2: DPLL Enable */
# define SYSCTRL_DPLLSTATUS_DIV (1 << 3) /* Bit 3: Divider Enable */
#endif
/******************************************************************************************** /********************************************************************************************
* Public Types * Public Types
********************************************************************************************/ ********************************************************************************************/
@@ -317,5 +431,5 @@
* Public Functions * Public Functions
********************************************************************************************/ ********************************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 */ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_SYSCTRL_H */ #endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_SYSCTRL_H */
arch/arm/src/samdl/sam_fuses.h
+1 -1
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@@ -44,7 +44,7 @@
#include "sam_config.h" #include "sam_config.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
# include "chip/samd_fuses.h" # include "chip/samd_fuses.h"
#elif defined(CONFIG_ARCH_FAMILY_SAML21) #elif defined(CONFIG_ARCH_FAMILY_SAML21)
# include "chip/saml_fuses.h" # include "chip/saml_fuses.h"
arch/arm/src/samdl/samd_gclk.c
+2 -2
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@@ -47,7 +47,7 @@
#include "up_arch.h" #include "up_arch.h"
#include "sam_gclk.h" #include "sam_gclk.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD20 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
@@ -205,4 +205,4 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
sam_gclck_waitsyncbusy(); sam_gclck_waitsyncbusy();
} }
#endif /* CONFIG_ARCH_FAMILY_SAMD20 */ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */