From bedd5d382debae10ad5e5247acc885aa5594aa91 Mon Sep 17 00:00:00 2001 From: ligd Date: Thu, 25 Aug 2022 22:19:14 +0800 Subject: [PATCH] armv7-a: icache also need SMP cache coherency configuration This can fixes the random crash happened sometime during boot. Signed-off-by: ligd --- arch/arm/src/armv7-a/arm_cpuhead.S | 4 ++-- arch/arm/src/armv7-a/arm_head.S | 2 +- arch/arm/src/armv7-a/arm_pghead.S | 2 +- arch/arm/src/armv7-a/arm_scu.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpuhead.S b/arch/arm/src/armv7-a/arm_cpuhead.S index 7fe1b924742..56ca754c2b2 100644 --- a/arch/arm/src/armv7-a/arm_cpuhead.S +++ b/arch/arm/src/armv7-a/arm_cpuhead.S @@ -318,7 +318,7 @@ __cpu3_start: * after SMP cache coherency has been setup. */ -#if 0 /* !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) */ +#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) /* Dcache enable * * SCTLR_C Bit 2: DCache enable @@ -327,7 +327,7 @@ __cpu3_start: orr r0, r0, #(SCTLR_C) #endif -#ifndef CPU_ICACHE_DISABLE +#if !defined(CPU_ICACHE_DISABLE) && !defined(CONFIG_SMP) /* Icache enable * * SCTLR_I Bit 12: ICache enable diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index e0061bd5501..abbc74ccac0 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -452,7 +452,7 @@ __start: orr r0, r0, #(SCTLR_C) #endif -#ifndef CPU_ICACHE_DISABLE +#if !defined(CPU_ICACHE_DISABLE) && !defined(CONFIG_SMP) /* Icache enable * * SCTLR_I Bit 12: ICache enable diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S index e53563d7757..df56291712b 100644 --- a/arch/arm/src/armv7-a/arm_pghead.S +++ b/arch/arm/src/armv7-a/arm_pghead.S @@ -434,7 +434,7 @@ __start: orr r0, r0, #(SCTLR_C) #endif -#ifndef CPU_ICACHE_DISABLE +#if !defined(CPU_ICACHE_DISABLE) && !defined(CONFIG_SMP) /* Icache enable * * SCTLR_I Bit 12: ICache enable diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c index 8f0c6cac4d3..ad3329b1b64 100644 --- a/arch/arm/src/armv7-a/arm_scu.c +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -203,6 +203,6 @@ void arm_enable_smp(int cpu) arm_set_actlr(regval); regval = arm_get_sctlr(); - regval |= SCTLR_C; + regval |= SCTLR_C | SCTLR_I; arm_set_sctlr(regval); }