diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index d22009df375..3a667731d9b 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2381,26 +2381,38 @@ if STM32_HRTIM1 config STM32_HRTIM_MASTER bool "HRTIM MASTER" default n + ---help--- + Enable HRTIM Master Timer config STM32_HRTIM_TIMA bool "HRTIM TIMA" default n + ---help--- + Enable HRTIM Timer A config STM32_HRTIM_TIMB bool "HRTIM TIMB" default n + ---help--- + Enable HRTIM Timer B config STM32_HRTIM_TIMC bool "HRTIM TIMC" default n + ---help--- + Enable HRTIM Timer C config STM32_HRTIM_TIMD bool "HRTIM TIMD" default n + ---help--- + Enable HRTIM Timer D config STM32_HRTIM_TIME bool "HRTIM TIME" default n + ---help--- + Enable HRTIM Timer E endif # STM32_HRTIM @@ -5853,10 +5865,15 @@ if STM32_HRTIM1 config STM32_HRTIM_DISABLE_CHARDRV bool "HRTIM Disable Character Driver" default n + ---help--- + In most cases we do not need HRTIM Character Driver, so we can disable it + and save some memory. menuconfig STM32_HRTIM_ADC - bool "HRTIM ADC Configuration" + bool "HRTIM ADC Triggering" default n + ---help--- + Enable HRTIM ADC Triggering support. if STM32_HRTIM_ADC @@ -5897,33 +5914,54 @@ endif # STM32_HRTIM_ADC config STM32_HRTIM_DAC bool "HRTIM DAC Triggering" default n + ---help--- + Enable HRTIM DAC Triggering support. config STM32_HRTIM_PWM bool "HRTIM PWM Outputs" default n + ---help--- + Enable HRTIM PWM Outputs support. config STM32_HRTIM_CAP bool "HRTIM Capture" default n + ---help--- + Enable HRTIM Capture support. config STM32_HRTIM_INTERRUPTS bool "HRTIM Interrupts" default n + ---help--- + Enable HRTIM Interrupts support. config STM32_HRTIM_BURST bool "HRTIM Burst Mode" depends on STM32_HRTIM_PWM default n + ---help--- + Enable HRTIM Burst Mode support for PWM outputs. config STM32_HRTIM_DEADTIME bool "HRTIM Dead-time" depends on STM32_HRTIM_PWM default n + ---help--- + Enable HRTIM Deadtime support for PWM outputs. config STM32_HRTIM_PUSHPULL - bool "HRTIM push-pull mode" + bool "HRTIM Push-Pull Mode" depends on STM32_HRTIM_PWM default n + ---help--- + Enable HRTIM Push-Pull Mode support for PWM outputs. + +config STM32_HRTIM_CHOPPER + bool "HRTIM Chopper" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Chopper Mode for PWM outputs. config STM32_HRTIM_DMA bool "HRTIM DMA" @@ -5933,11 +5971,6 @@ config STM32_HRTIM_DMABURST bool "HRTIM DMA Burst" default n -config STM32_HRTIM_CHOPPER - bool "HRTIM Chopper" - depends on STM32_HRTIM_PWM - default n - config STM32_HRTIM_AUTODELAY bool "HRTIM Autodelay" depends on STM32_HRTIM_PWM @@ -5946,6 +5979,8 @@ config STM32_HRTIM_AUTODELAY menuconfig STM32_HRTIM_EVENTS bool "HRTIM Events Configuration" default n + ---help--- + Enable HRTIM Events support. if STM32_HRTIM_EVENTS @@ -5994,6 +6029,8 @@ endif # STM32_HRTIM_EVENTS menuconfig STM32_HRTIM_FAULTS bool "HRTIM Faults Configuration" default n + ---help--- + Enable HRTIM Faults support. if STM32_HRTIM_FAULTS @@ -6018,6 +6055,11 @@ endif # STM32_HRTIM_FAULTS config STM32_HRTIM_CLK_FROM_PLL bool "HRTIM Clock from PLL" default n + ---help--- + Set PLL as the clock source for HRTIM. + This configuration requires the following conditions: + 1) system clock is PLL, + 2) SYSCLK and PCLK2 ratio must be 1 o 2. menu "HRTIM Master Configuration" depends on STM32_HRTIM_MASTER @@ -6446,6 +6488,22 @@ config STM32_ADC4_DMA DMA transfer, which is necessary if multiple channels are read or if very high trigger frequencies are used. +config STM32_ADC1_INJECTED + bool "ADC1 INJECTED" + depends on STM32_ADC1 && STM32_STM32F33XX + default n + ---help--- + Support for ADC1 injected channels. + Only for STM32_STM32F33XX at this moment. + +config STM32_ADC2_INJECTED + bool "ADC2 INJECTED" + depends on STM32_ADC2 && STM32_STM32F33XX + default n + ---help--- + Support for ADC2 injected channels. + Only for STM32_STM32F33XX at this moment. + endmenu menu "SDADC Configuration" diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h index ebfc857273b..60c9bf92eb7 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h @@ -1042,13 +1042,13 @@ /* Common Control Register 1 */ -#define HRTIM_CR1_MUDIS (1 << 0) /* Bit 0 */ -#define HRTIM_CR1_TAUDIS (1 << 1) /* Bit 1 */ -#define HRTIM_CR1_TBUDIS (1 << 2) /* Bit 2 */ -#define HRTIM_CR1_TCUDIS (1 << 3) /* Bit 3 */ -#define HRTIM_CR1_TDUDIS (1 << 4) /* Bit 4 */ -#define HRTIM_CR1_TEUDIS (1 << 5) /* Bit 5 */ -#define HRTIM_CR1_AD1USRC_SHIFT 16 /* Bits 16-18 */ +#define HRTIM_CR1_MUDIS (1 << 0) /* Bit 0: Master Update Disable */ +#define HRTIM_CR1_TAUDIS (1 << 1) /* Bit 1: Timer A Update Disable */ +#define HRTIM_CR1_TBUDIS (1 << 2) /* Bit 2: Timer B Update Disable */ +#define HRTIM_CR1_TCUDIS (1 << 3) /* Bit 3: Timer C Update Disable */ +#define HRTIM_CR1_TDUDIS (1 << 4) /* Bit 4: Timer D Update Disable */ +#define HRTIM_CR1_TEUDIS (1 << 5) /* Bit 5: Timer E Update Disable */ +#define HRTIM_CR1_AD1USRC_SHIFT 16 /* Bits 16-18: ADC Trigger 1 Update Source */ #define HRTIM_CR1_AD1USRC_MASK (7 << HRTIM_CR1_AD1USRC_SHIFT) # define HRTIM_CR1_AD1USRC_MT (0 << HRTIM_CR1_AD1USRC_SHIFT) /* 000: Mater Timer */ # define HRTIM_CR1_AD1USRC_TA (1 << HRTIM_CR1_AD1USRC_SHIFT) /* 001: Timer A */ @@ -1056,7 +1056,7 @@ # define HRTIM_CR1_AD1USRC_TC (3 << HRTIM_CR1_AD1USRC_SHIFT) /* 011: Timer C */ # define HRTIM_CR1_AD1USRC_TD (4 << HRTIM_CR1_AD1USRC_SHIFT) /* 100: Timer D */ # define HRTIM_CR1_AD1USRC_TE (5 << HRTIM_CR1_AD1USRC_SHIFT) /* 101: Timer A */ -#define HRTIM_CR1_AD2USRC_SHIFT 19 /* Bits 19-21 */ +#define HRTIM_CR1_AD2USRC_SHIFT 19 /* Bits 19-21: ADC Trigger 2 Update Source */ #define HRTIM_CR1_AD2USRC_MASK (7 << HRTIM_CR1_AD2USRC_SHIFT) # define HRTIM_CR1_AD2USRC_MT (0 << HRTIM_CR1_AD2USRC_SHIFT) /* 000: Mater Timer */ # define HRTIM_CR1_AD2USRC_TA (1 << HRTIM_CR1_AD2USRC_SHIFT) /* 001: Timer A */ @@ -1064,7 +1064,7 @@ # define HRTIM_CR1_AD2USRC_TC (3 << HRTIM_CR1_AD2USRC_SHIFT) /* 011: Timer C */ # define HRTIM_CR1_AD2USRC_TD (4 << HRTIM_CR1_AD2USRC_SHIFT) /* 100: Timer D */ # define HRTIM_CR1_AD2USRC_TE (5 << HRTIM_CR1_AD2USRC_SHIFT) /* 101: Timer A */ -#define HRTIM_CR1_AD3USRC_SHIFT 22 /* Bits 22-24 */ +#define HRTIM_CR1_AD3USRC_SHIFT 22 /* Bits 22-24: ADC Trigger 3 Update Source */ #define HRTIM_CR1_AD3USRC_MASK (7 << HRTIM_CR1_AD3USRC_SHIFT) # define HRTIM_CR1_AD3USRC_MT (0 << HRTIM_CR1_AD3USRC_SHIFT) /* 000: Mater Timer */ # define HRTIM_CR1_AD3USRC_TA (1 << HRTIM_CR1_AD3USRC_SHIFT) /* 001: Timer A */ @@ -1072,7 +1072,7 @@ # define HRTIM_CR1_AD3USRC_TC (3 << HRTIM_CR1_AD3USRC_SHIFT) /* 011: Timer C */ # define HRTIM_CR1_AD3USRC_TD (4 << HRTIM_CR1_AD3USRC_SHIFT) /* 100: Timer D */ # define HRTIM_CR1_AD3USRC_TE (5 << HRTIM_CR1_AD3USRC_SHIFT) /* 101: Timer A */ -#define HRTIM_CR1_AD4USRC_SHIFT 25 /* Bits 25-27 */ +#define HRTIM_CR1_AD4USRC_SHIFT 25 /* Bits 25-27: ADC Trigger 4 Update Source */ #define HRTIM_CR1_AD4USRC_MASK (7 << HRTIM_CR1_AD4USRC_SHIFT) # define HRTIM_CR1_AD4USRC_MT (0 << HRTIM_CR1_AD4USRC_SHIFT) /* 000: Mater Timer */ # define HRTIM_CR1_AD4USRC_TA (1 << HRTIM_CR1_AD4USRC_SHIFT) /* 001: Timer A */ diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index c83456458c9..7df316a037a 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -212,6 +212,8 @@ (hrtim)->hd_ops->cmp_update(hrtim, tim, index, cmp) #define HRTIM_PER_SET(hrtim, tim, per) \ (hrtim)->hd_ops->per_update(hrtim, tim, per) +#define HRTIM_REP_SET(hrtim, tim, per) \ + (hrtim)->hd_ops->rep_update(hrtim, tim, per) #define HRTIM_PER_GET(hrtim, tim) \ (hrtim)->hd_ops->per_get(hrtim, tim) #define HRTIM_FCLK_GET(hrtim, tim) \ diff --git a/configs/stm32f334-disco/README.txt b/configs/stm32f334-disco/README.txt index e69de29bb2d..5e2d5b3f13e 100644 --- a/configs/stm32f334-disco/README.txt +++ b/configs/stm32f334-disco/README.txt @@ -0,0 +1,36 @@ +README +====== + +This README discusses issues unique to NuttX configurations for the +STMicro 32F3348DISCOVERY development board featuring the STM32F334C8 +MCU. The STM32F334C8 is a 72MHz Cortex-M4 operation with 64kB Flash +memory and 16KB RAM. The board features: + + - On-board ST-LINK/V2 for programming and debugging, + - High brightness LED dimming with buck converter + - One buck/boost converter + - Four user LEDs and two push-buttons, + - Easy access to most MCU pins. + +Refer to http://www.st.com/en/evaluation-tools/32f3348discovery.html for +further information about this board. + +Configurations +============== + + nsh: + ---- + + Configures the NuttShell (nsh) located at apps/examples/nsh. + + powerled: + --------- + + This is a configuration for onboard high brightness LED dimming. + + buckboost: + --------- + + This configuration uses apps/examples/smps and onboard buck/boost converter. + + WARNING: current limit is not implemented! diff --git a/configs/stm32f334-disco/buckboost/defconfig b/configs/stm32f334-disco/buckboost/defconfig new file mode 100644 index 00000000000..6910e821216 --- /dev/null +++ b/configs/stm32f334-disco/buckboost/defconfig @@ -0,0 +1,135 @@ +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f334-disco" +CONFIG_ARCH_BOARD_STM32F334_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN_PROXY_STACKSIZE=512 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +# CONFIG_DEV_NULL is not set +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POLL=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DRIVERS_SMPS=y +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" +CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 +CONFIG_EXAMPLES_SMPS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_MAX_TASKS=4 +CONFIG_MAX_WDOGPARMS=1 +CONFIG_NAME_MAX=16 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DD=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_ECHO=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_FREE=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HELP=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MB=y +CONFIG_NSH_DISABLE_MH=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_MW=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SH=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_TELNETD=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=512 +CONFIG_POWER=y +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PREALLOC_WDOGS=1 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y +CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_BUFFER_SIZE=128 +CONFIG_STM32_ADC1_INJECTED=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_ADC1_TRG2=y +CONFIG_STM32_HRTIM_ADC=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DEADTIME=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMA_DT=y +CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMA_PWM_CH2=y +CONFIG_STM32_HRTIM_TIMA_PWM=y +CONFIG_STM32_HRTIM_TIMA=y +CONFIG_STM32_HRTIM_TIMB_DT=y +CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMB_PWM_CH2=y +CONFIG_STM32_HRTIM_TIMB_PWM=y +CONFIG_STM32_HRTIM_TIMB=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_WDOG_INTRESERVE=0