diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index d4d1354d884..eb16234ab41 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -254,6 +254,10 @@ config SAMV7_SSC bool default n +config SAMV7_HAVE_TC + bool + default n + config SAMV7_HAVE_TWIHS2 bool default n @@ -419,64 +423,24 @@ config SAMV7_SSC0 select SAMV7_SSC config SAMV7_TC0 - bool "Timer/Counter 0 (TC0)" + bool "Timer Counter 0 (ch. 0, 1, 2) (TC0)" default n - select SAMV7_TC + select SAMV7_HAVE_TC config SAMV7_TC1 - bool "Timer/Counter 1 (TC1)" + bool "Timer Counter 1 (ch. 3, 4, 5) (TC1)" default n - select SAMV7_TC + select SAMV7_HAVE_TC config SAMV7_TC2 - bool "Timer/Counter 2 (TC2)" + bool "Timer Counter 2 (ch. 6, 7, 8) (TC2)" default n - select SAMV7_TC + select SAMV7_HAVE_TC config SAMV7_TC3 - bool "Timer/Counter 3 (TC3)" + bool "Timer Counter 3 (ch. 9, 10, 11) (TC2)" default n - select SAMV7_TC - -config SAMV7_TC4 - bool "Timer/Counter 4 (TC4)" - default n - select SAMV7_TC - -config SAMV7_TC5 - bool "Timer/Counter 5 (TC5)" - default n - select SAMV7_TC - -config SAMV7_TC6 - bool "Timer/Counter 6 (TC6)" - default n - select SAMV7_TC - -config SAMV7_TC7 - bool "Timer/Counter 7 (TC7)" - default n - select SAMV7_TC - -config SAMV7_TC8 - bool "Timer/Counter 8 (TC8)" - default n - select SAMV7_TC - -config SAMV7_TC9 - bool "Timer/Counter 9 (TC8)" - default n - select SAMV7_TC - -config SAMV7_TC10 - bool "Timer/Counter 10 (TC9)" - default n - select SAMV7_TC - -config SAMV7_TC11 - bool "Timer/Counter 11 (TC8)" - default n - select SAMV7_TC + select SAMV7_HAVE_TC config SAMV7_TRNG bool "True Random Number Generator (TRNG)" @@ -1208,6 +1172,227 @@ config SAMV7_SSC_DUMPBUFFERS endmenu # SSC Configuration +if SAMV7_HAVE_TC +menu "Timer/counter Configuration" + +if SAMV7_TC0 + +config SAMV7_TC0_CLK0 + bool "Enable TC0 channel 0 clock input pin" + default n + +config SAMV7_TC0_TIOA0 + bool "Enable TC0 channel 0 output A" + default n + +config SAMV7_TC0_TIOB0 + bool "Enable TC0 channel 0 output B" + default n + +config SAMV7_TC0_CLK1 + bool "Enable TC0 channel 1 clock input pin" + default n + +config SAMV7_TC0_TIOA1 + bool "Enable TC0 channel 1 output A" + default n + +config SAMV7_TC0_TIOB1 + bool "Enable TC0 channel 1 output B" + default n + +config SAMV7_TC0_CLK2 + bool "Enable TC0 channel 2 clock input pin" + default n + +config SAMV7_TC0_TIOA2 + bool "Enable TC0 channel 2 output A" + default n + +config SAMV7_TC0_TIOB2 + bool "Enable TC0 channel 2 output B" + default n + +endif # SAMV7_TC0 + +if SAMV7_TC1 + +config SAMV7_TC1_CLK3 + bool "Enable TC1 channel 3 clock input pin" + default n + +config SAMV7_TC1_TIOA3 + bool "Enable TC1 channel 3 output A" + default n + +config SAMV7_TC1_TIOB3 + bool "Enable TC1 channel 3 output B" + default n + +config SAMV7_TC1_CLK4 + bool "Enable TC1 channel 4 clock input pin" + default n + +config SAMV7_TC1_TIOA4 + bool "Enable TC1 channel 4 output A" + default n + +config SAMV7_TC1_TIOB4 + bool "Enable TC1 channel 4 output B" + default n + +config SAMV7_TC1_CLK5 + bool "Enable TC1 channel 5 clock input pin" + default n + +config SAMV7_TC1_TIOA5 + bool "Enable TC1 channel 5 output A" + default n + +config SAMV7_TC1_TIOB5 + bool "Enable TC1 channel 5 output B" + default n + +endif # SAMV7_TC1 + +if SAMV7_TC2 + +config SAMV7_TC2_CLK6 + bool "Enable TC2 channel 6 clock input pin" + default n + +config SAMV7_TC2_TIOA6 + bool "Enable TC2 channel 6 output A" + default n + +config SAMV7_TC2_TIOB6 + bool "Enable TC2 channel 6 output B" + default n + +config SAMV7_TC2_CLK7 + bool "Enable TC2 channel 7 clock input pin" + default n + +config SAMV7_TC2_TIOA7 + bool "Enable TC2 channel 7 output A" + default n + +config SAMV7_TC2_TIOB7 + bool "Enable TC2 channel 7 output B" + default n + +config SAMV7_TC2_CLK8 + bool "Enable TC2 channel 8 clock input pin" + default n + +config SAMV7_TC2_TIOA8 + bool "Enable TC2 channel 8 output A" + default n + +config SAMV7_TC2_TIOB8 + bool "Enable TC2 channel 8 output B" + default n + +endif # SAMV7_TC2 + +if SAMV7_TC3 +config SAMV7_TC3_CLK9 + bool "Enable TC3 channel 9 clock input pin" + default n + +config SAMV7_TC3_TIOA9 + bool "Enable TC3 channel 9 output A" + default n + +config SAMV7_TC3_TIOB9 + bool "Enable TC3 channel 9 output B" + default n + +config SAMV7_TC3_CLK10 + bool "Enable TC3 channel 10 clock input pin" + default n + +config SAMV7_TC3_TIOA10 + bool "Enable TC3 channel 10 output A" + default n + +config SAMV7_TC3_TIOB10 + bool "Enable TC3 channel 10 output B" + default n + +config SAMV7_TC3_CLK11 + bool "Enable TC3 channel 11 clock input pin" + default n + +config SAMV7_TC3_TIOA11 + bool "Enable TC3 channel 11 output A" + default n + +config SAMV7_TC3_TIOB11 + bool "Enable TC3 channel 11 output B" + default n + +endif # SAMV7_TC3 + +config SAMV7_ONESHOT + bool "TC one-shot wrapper" + default n if !SCHED_TICKLESS + default y if SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config SAMV7_FREERUN + bool "TC free-running wrapper" + default n if !SCHED_TICKLESS + default y if SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +if SCHED_TICKLESS + +config SAMV7_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + default 0 + range 0 8 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the one-shot timer needed by the OS. + +config SAMV7_TICKLESS_FREERUN + int "Tickless free-running timer channel" + default 1 + range 0 8 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS. + +endif + +config SAMV7_TC_DEBUG + bool "TC debug" + depends on DEBUG + default n + ---help--- + Output high level Timer/Counter device debug information. + Requires also DEBUG. If this option AND DEBUG_VERBOSE are + enabled, then the system will be overwhelmed the timer debug + output. If DEBUG_VERBOSE is disabled, then debug output will + only indicate if/when timer-related errors occur. This + latter mode is completely usable. + +config SAMV7_TC_REGDEBUG + bool "TC register level debug" + depends on DEBUG + default n + ---help--- + Output detailed register-level Timer/Counter device debug + information. Very invasive! Requires also DEBUG. + +endmenu # Timer/counter Configuration +endif # SAMV7_HAVE_TC + menu "HSMCI device driver options" depends on SAMV7_HSMCI diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index d54d5e656bd..6dcb42b9625 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -160,6 +160,19 @@ ifeq ($(CONFIG_SAMV7_SSC),y) CHIP_CSRCS += sam_ssc.c endif +ifeq ($(CONFIG_SAMV7_HAVE_TC),y) +CHIP_CSRCS += sam_tc.c +ifeq ($(CONFIG_SAMV7_ONESHOT),y) +CHIP_CSRCS += sam_oneshot.c +endif +ifeq ($(CONFIG_SAMV7_FREERUN),y) +CHIP_CSRCS += sam_freerun.c +endif +ifeq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += sam_tickless.c +endif +endif + ifeq ($(CONFIG_SAMV7_HSMCI),y) CHIP_CSRCS += sam_hsmci.c sam_hsmci_clkdiv.c endif diff --git a/arch/arm/src/samv7/chip/sam_tc.h b/arch/arm/src/samv7/chip/sam_tc.h new file mode 100644 index 00000000000..98d4343e5b6 --- /dev/null +++ b/arch/arm/src/samv7/chip/sam_tc.h @@ -0,0 +1,636 @@ +/************************************************************************************ + * arch/arm/src/samv7/chip/sam_tc.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H +#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/sam_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define SAM_TC_NCHANNELS 3 /* Number of channels per TC peripheral */ + +/* TC Register Offsets **************************************************************/ + +#define SAM_TC_CHAN_OFFSET(n) ((n) << 6) /* Channel n offset */ +#define SAM_TC_CCR_OFFSET 0x0000 /* Channel Control Register */ +#define SAM_TC_CMR_OFFSET 0x0004 /* Channel Mode Register */ +#define SAM_TC_SMMR_OFFSET 0x0008 /* Stepper Motor Mode Register */ +#define SAM_TC_RAB_OFFSET 0x000c /* Register AB */ +#define SAM_TC_CV_OFFSET 0x0010 /* Counter Value */ +#define SAM_TC_RA_OFFSET 0x0014 /* Register A */ +#define SAM_TC_RB_OFFSET 0x0018 /* Register B */ +#define SAM_TC_RC_OFFSET 0x001c /* Register C */ +#define SAM_TC_SR_OFFSET 0x0020 /* Status Register */ +#define SAM_TC_IER_OFFSET 0x0024 /* Interrupt Enable Register */ +#define SAM_TC_IDR_OFFSET 0x0028 /* Interrupt Disable Register */ +#define SAM_TC_IMR_OFFSET 0x002c /* Interrupt Mask Register */ +#define SAM_TC_EMR_OFFSET 0x0030 /* Extended Mode Register */ + +#define SAM_TCn_CCR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CCR_OFFSET) +#define SAM_TCn_CMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CMR_OFFSET) +#define SAM_TCn_SMMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_SMMR_OFFSET) +#define SAM_TCn_RAB_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RAB_OFFSET) +#define SAM_TCn_CV_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CV_OFFSET) +#define SAM_TCn_RA_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RA_OFFSET) +#define SAM_TCn_RB_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RB_OFFSET) +#define SAM_TCn_RC_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RC_OFFSET) +#define SAM_TCn_SR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_SR_OFFSET) +#define SAM_TCn_IER_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IER_OFFSET) +#define SAM_TCn_IDR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IDR_OFFSET) +#define SAM_TCn_IMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IMR_OFFSET) +#define SAM_TCn_EMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_EMR_OFFSET) + +#define SAM_TC0_CCR_OFFSET SAM_TCn_CCR_OFFSET(0) +#define SAM_TC0_CMR_OFFSET SAM_TCn_CMR_OFFSET(0) +#define SAM_TC0_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(0) +#define SAM_TC0_RAB_OFFSET SAM_TCn_RAB_OFFSET(0) +#define SAM_TC0_CV_OFFSET SAM_TCn_CV_OFFSET(0) +#define SAM_TC0_RA_OFFSET SAM_TCn_RA_OFFSET(0) +#define SAM_TC0_RB_OFFSET SAM_TCn_RB_OFFSET(0) +#define SAM_TC0_RC_OFFSET SAM_TCn_RC_OFFSET(0) +#define SAM_TC0_SR_OFFSET SAM_TCn_SR_OFFSET(0) +#define SAM_TC0_IER_OFFSET SAM_TCn_IER_OFFSET(0) +#define SAM_TC0_IDR_OFFSET SAM_TCn_IDR_OFFSET(0) +#define SAM_TC0_IMR_OFFSET SAM_TCn_IMR_OFFSET(0) +#define SAM_TC0_EMR_OFFSET SAM_TCn_EMR_OFFSET(0) + +#define SAM_TC1_CCR_OFFSET SAM_TCn_CCR_OFFSET(1) +#define SAM_TC1_CMR_OFFSET SAM_TCn_CMR_OFFSET(1) +#define SAM_TC1_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(1) +#define SAM_TC1_RAB_OFFSET SAM_TCn_RAB_OFFSET(1) +#define SAM_TC1_CV_OFFSET SAM_TCn_CV_OFFSET(1) +#define SAM_TC1_RA_OFFSET SAM_TCn_RA_OFFSET(1) +#define SAM_TC1_RB_OFFSET SAM_TCn_RB_OFFSET(1) +#define SAM_TC1_RC_OFFSET SAM_TCn_RC_OFFSET(1) +#define SAM_TC1_SR_OFFSET SAM_TCn_SR_OFFSET(1) +#define SAM_TC1_IER_OFFSET SAM_TCn_IER_OFFSET(1) +#define SAM_TC1_IDR_OFFSET SAM_TCn_IDR_OFFSET(1) +#define SAM_TC1_IMR_OFFSET SAM_TCn_IMR_OFFSET(1) +#define SAM_TC1_EMR_OFFSET SAM_TCn_EMR_OFFSET(1) + +#define SAM_TC2_CCR_OFFSET SAM_TCn_CCR_OFFSET(2) +#define SAM_TC2_CMR_OFFSET SAM_TCn_CMR_OFFSET(2) +#define SAM_TC2_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(2) +#define SAM_TC2_RAB_OFFSET SAM_TCn_RAB_OFFSET(2) +#define SAM_TC2_CV_OFFSET SAM_TCn_CV_OFFSET(2) +#define SAM_TC2_RA_OFFSET SAM_TCn_RA_OFFSET(2) +#define SAM_TC2_RB_OFFSET SAM_TCn_RB_OFFSET(2) +#define SAM_TC2_RC_OFFSET SAM_TCn_RC_OFFSET(2) +#define SAM_TC2_SR_OFFSET SAM_TCn_SR_OFFSET(2) +#define SAM_TC2_IER_OFFSET SAM_TCn_IER_OFFSET(2) +#define SAM_TC2_IDR_OFFSET SAM_TCn_IDR_OFFSET(2) +#define SAM_TC2_IMR_OFFSET SAM_TCn_IMR_OFFSET(2) +#define SAM_TC2_EMR_OFFSET SAM_TCn_EMR_OFFSET(2) + +#define SAM_TC_BCR_OFFSET 0x00c0 /* Block Control Register */ +#define SAM_TC_BMR_OFFSET 0x00c4 /* Block Mode Register */ +#define SAM_TC_QIER_OFFSET 0x00c8 /* QDEC Interrupt Enable Register */ +#define SAM_TC_QIDR_OFFSET 0x00cc /* QDEC Interrupt Disable Register */ +#define SAM_TC_QIMR_OFFSET 0x00d0 /* QDEC Interrupt Mask Register */ +#define SAM_TC_QISR_OFFSET 0x00d4 /* QDEC Interrupt Status Register */ +#define SAM_TC_FMR_OFFSET 0x00d8 /* Fault Mode Register */ +#define SAM_TC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ + +/* TC Register Addresses ************************************************************/ + +#define SAM_TC012_CHAN_BASE(n) (SAM_TC012_BASE+SAM_TC_CHAN_OFFSET(n)) + +#define SAM_TC012_CCR(n) (SAM_TC012_BASE+SAM_TCn_CCR_OFFSET(n)) +#define SAM_TC012_CMR(n) (SAM_TC012_BASE+SAM_TCn_CMR_OFFSET(n)) +#define SAM_TC012_SMMR(n) (SAM_TC012_BASE+SAM_TCn_SMMR_OFFSET(n)) +#define SAM_TC012_RAB(n) (SAM_TC012_BASE+SAM_TCn_RAB_OFFSET(n)) +#define SAM_TC012_CV(n) (SAM_TC012_BASE+SAM_TCn_CV_OFFSET(n)) +#define SAM_TC012_RA(n) (SAM_TC012_BASE+SAM_TCn_RA_OFFSET(n)) +#define SAM_TC012_RB(n) (SAM_TC012_BASE+SAM_TCn_RB(n)) +#define SAM_TC012_RC(n) (SAM_TC012_BASE+SAM_TCn_RC_OFFSET(n)) +#define SAM_TC012_SR(n) (SAM_TC012_BASE+SAM_TCn_SR_OFFSET(n)) +#define SAM_TC012_IER(n) (SAM_TC012_BASE+SAM_TCn_IER_OFFSET(n)) +#define SAM_TC012_IDR(n) (SAM_TC012_BASE+SAM_TCn_IDR_OFFSET(n)) +#define SAM_TC012_IMR(n) (SAM_TC012_BASE+SAM_TCn_IMR_OFFSET(n)) +#define SAM_TC012_EMR(n) (SAM_TC012_BASE+SAM_TCn_EMR_OFFSET(n)) + +#define SAM_TC0_CCR SAM_TC012_CCR(0) +#define SAM_TC0_CMR SAM_TC012_CMR(0) +#define SAM_TC0_SMMR SAM_TC012_SMMR(0) +#define SAM_TC0_RAB SAM_TC012_RAB(0) +#define SAM_TC0_CV SAM_TC012_CV(0) +#define SAM_TC0_RA SAM_TC012_RA(0) +#define SAM_TC0_RB SAM_TC012_RB(0) +#define SAM_TC0_RC SAM_TC012_RC(0) +#define SAM_TC0_SR SAM_TC012_SR(0) +#define SAM_TC0_IER SAM_TC012_IER(0) +#define SAM_TC0_IDR SAM_TC012_IDR(0) +#define SAM_TC0_IMR SAM_TC012_IMR(0) +#define SAM_TC0_EMR SAM_TC012_EMR(0) + +#define SAM_TC1_CCR SAM_TC012_CCR(1) +#define SAM_TC1_CMR SAM_TC012_CMR(1) +#define SAM_TC1_SMMR SAM_TC012_SMMR(1) +#define SAM_TC1_RAB SAM_TC012_RAB(1) +#define SAM_TC1_CV SAM_TC012_CV(1) +#define SAM_TC1_RA SAM_TC012_RA(1) +#define SAM_TC1_RB SAM_TC012_RB(1) +#define SAM_TC1_RC SAM_TC012_RC(1) +#define SAM_TC1_SR SAM_TC012_SR(1) +#define SAM_TC1_IER SAM_TC012_IER(1) +#define SAM_TC1_IDR SAM_TC012_IDR(1) +#define SAM_TC1_IMR SAM_TC012_IMR(1) +#define SAM_TC1_EMR SAM_TC012_EMR(1) + +#define SAM_TC2_CCR SAM_TC012_CCR(2) +#define SAM_TC2_CMR SAM_TC012_CMR(2) +#define SAM_TC2_SMMR SAM_TC012_SMMR(2) +#define SAM_TC2_RAB SAM_TC012_RAB(2) +#define SAM_TC2_CV SAM_TC012_CV(2) +#define SAM_TC2_RA SAM_TC012_RA(2) +#define SAM_TC2_RB SAM_TC012_RB(2) +#define SAM_TC2_RC SAM_TC012_RC(2) +#define SAM_TC2_SR SAM_TC012_SR(2) +#define SAM_TC2_IER SAM_TC012_IER(2) +#define SAM_TC2_IDR SAM_TC012_IDR(2) +#define SAM_TC2_IMR SAM_TC012_IMR(2) +#define SAM_TC2_EMR SAM_TC012_EMR(2) + +#define SAM_TC012_BCR (SAM_TC012_BASE+SAM_TC_BCR_OFFSET) +#define SAM_TC012_BMR (SAM_TC012_BASE+SAM_TC_BMR_OFFSET) +#define SAM_TC012_QIER (SAM_TC012_BASE+SAM_TC_QIER_OFFSET) +#define SAM_TC012_QIDR (SAM_TC012_BASE+SAM_TC_QIDR_OFFSET) +#define SAM_TC012_QIMR (SAM_TC012_BASE+SAM_TC_QIMR_OFFSET) +#define SAM_TC012_QISR (SAM_TC012_BASE+SAM_TC_QISR_OFFSET) +#define SAM_TC012_FMR (SAM_TC012_BASE+SAM_TC_FMR_OFFSET) +#define SAM_TC012_WPMR (SAM_TC012_BASE+SAM_TC_WPMR_OFFSET) + +#define SAM_TC345_CHAN_BASE(n) (SAM_TC345_BASE+SAM_TC_CHAN_OFFSET((n)-3)) + +#define SAM_TC345_CCR(n) (SAM_TC345_BASE+SAM_TCn_CCR_OFFSET((n)-3)) +#define SAM_TC345_CMR(n) (SAM_TC345_BASE+SAM_TCn_CMR_OFFSET((n)-3)) +#define SAM_TC345_SMMR(n) (SAM_TC345_BASE+SAM_TCn_SMMR_OFFSET((n)-3)) +#define SAM_TC345_RAB(n) (SAM_TC345_BASE+SAM_TCn_RAB_OFFSET((n)-3)) +#define SAM_TC345_CV(n) (SAM_TC345_BASE+SAM_TCn_CV_OFFSET((n)-3)) +#define SAM_TC345_RA(n) (SAM_TC345_BASE+SAM_TCn_RA_OFFSET((n)-3)) +#define SAM_TC345_RB(n) (SAM_TC345_BASE+SAM_TCn_RB_OFFSET((n)-3)) +#define SAM_TC345_RC(n) (SAM_TC345_BASE+SAM_TCn_RC_OFFSET((n)-3)) +#define SAM_TC345_SR(n) (SAM_TC345_BASE+SAM_TCn_SR_OFFSET((n)-3)) +#define SAM_TC345_IER(n) (SAM_TC345_BASE+SAM_TCn_IER_OFFSET((n)-3)) +#define SAM_TC345_IDR(n) (SAM_TC345_BASE+SAM_TCn_IDR_OFFSET((n)-3)) +#define SAM_TC345_IMR(n) (SAM_TC345_BASE+SAM_TCn_IMR_OFFSET((n)-3)) +#define SAM_TC345_EMR(n) (SAM_TC345_BASE+SAM_TCn_EMR_OFFSET((n)-3)) + +#define SAM_TC3_CCR SAM_TC345_CCR(3) +#define SAM_TC3_CMR SAM_TC345_CMR(3) +#define SAM_TC3_SMMR SAM_TC345_SMMR(3) +#define SAM_TC3_RAB SAM_TC345_RAB(3) +#define SAM_TC3_CV SAM_TC345_CV(3) +#define SAM_TC3_RA SAM_TC345_RA(3) +#define SAM_TC3_RB SAM_TC345_RB(3) +#define SAM_TC3_RC SAM_TC345_RC(3) +#define SAM_TC3_SR SAM_TC345_SR(3) +#define SAM_TC3_IER SAM_TC345_IER(3) +#define SAM_TC3_IDR SAM_TC345_IDR(3) +#define SAM_TC3_IMR SAM_TC345_IMR(3) +#define SAM_TC3_EMR SAM_TC345_EMR(3) + +#define SAM_TC4_CCR SAM_TC345_CCR(4) +#define SAM_TC4_CMR SAM_TC345_CMR(4) +#define SAM_TC4_SMMR SAM_TC345_SMMR(4) +#define SAM_TC4_RAB SAM_TC345_RAB(4) +#define SAM_TC4_CV SAM_TC345_CV(4) +#define SAM_TC4_RA SAM_TC345_RA(4) +#define SAM_TC4_RB SAM_TC345_RB(4) +#define SAM_TC4_RC SAM_TC345_RC(4) +#define SAM_TC4_SR SAM_TC345_SR(4) +#define SAM_TC4_IER SAM_TC345_IER(4) +#define SAM_TC4_IDR SAM_TC345_IDR(4) +#define SAM_TC4_IMR SAM_TC345_IMR(4) +#define SAM_TC4_EMR SAM_TC345_EMR(4) + +#define SAM_TC5_CCR SAM_TC345_CCR(5) +#define SAM_TC5_CMR SAM_TC345_CMR(5) +#define SAM_TC5_SMMR SAM_TC345_SMMR(5) +#define SAM_TC5_RAB SAM_TC345_RAB(5) +#define SAM_TC5_CV SAM_TC345_CV(5) +#define SAM_TC5_RA SAM_TC345_RA(5) +#define SAM_TC5_RB SAM_TC345_RB(5) +#define SAM_TC5_RC SAM_TC345_RC(5) +#define SAM_TC5_SR SAM_TC345_SR(5) +#define SAM_TC5_IER SAM_TC345_IER(5) +#define SAM_TC5_IDR SAM_TC345_IDR(5) +#define SAM_TC5_IMR SAM_TC345_IMR(5) +#define SAM_TC5_EMR SAM_345_EMR(5) + +#define SAM_TC345_BCR (SAM_TC345_BASE+SAM_TC_BCR_OFFSET) +#define SAM_TC345_BMR (SAM_TC345_BASE+SAM_TC_BMR_OFFSET) +#define SAM_TC345_QIER (SAM_TC345_BASE+SAM_TC_QIER_OFFSET) +#define SAM_TC345_QIDR (SAM_TC345_BASE+SAM_TC_QIDR_OFFSET) +#define SAM_TC345_QIMR (SAM_TC345_BASE+SAM_TC_QIMR_OFFSET) +#define SAM_TC345_QISR (SAM_TC345_BASE+SAM_TC_QISR_OFFSET) +#define SAM_TC345_FMR (SAM_TC345_BASE+SAM_TC_FMR_OFFSET) +#define SAM_TC345_WPMR (SAM_TC345_BASE+SAM_TC_WPMR_OFFSET) + +#define SAM_TC678_CHAN_BASE(n) (SAM_TC678_BASE+SAM_TC_CHAN_OFFSET((n)-6)) + +#define SAM_TC678_CCRn(n) (SAM_TC678_BASE+SAM_TCn_CCR_OFFSET((n)-6)) +#define SAM_TC678_CMR(n) (SAM_TC678_BASE+SAM_TCn_CMR_OFFSET((n)-6)) +#define SAM_TC678_SMMR(n) (SAM_TC678_BASE+SAM_TCn_SMMR_OFFSET((n)-6)) +#define SAM_TC678_RAB(n) (SAM_TC678_BASE+SAM_TCn_RAB_OFFSET((n)-6)) +#define SAM_TC678_CV(n) (SAM_TC678_BASE+SAM_TCn_CV_OFFSET((n)-6)) +#define SAM_TC678_RA(n) (SAM_TC678_BASE+SAM_TCn_RA_OFFSET((n)-6)) +#define SAM_TC678_RB(n) (SAM_TC678_BASE+SAM_TCn_RB((n)-6)) +#define SAM_TC678_RC(n) (SAM_TC678_BASE+SAM_TCn_RC_OFFSET((n)-6)) +#define SAM_TC678_SR(n) (SAM_TC678_BASE+SAM_TCn_SR_OFFSET((n)-6)) +#define SAM_TC678_IER(n) (SAM_TC678_BASE+SAM_TCn_IER_OFFSET((n)-6)) +#define SAM_TC678_IDR(n) (SAM_TC678_BASE+SAM_TCn_IDR_OFFSET((n)-6)) +#define SAM_TC678_IMR(n) (SAM_TC678_BASE+SAM_TCn_IMR_OFFSET((n)-6)) +#define SAM_TC678_EMR(n) (SAM_TC678_BASE+SAM_TCn_EMR_OFFSET((n)-6)) + +#define SAM_TC6_CCR SAM_TC678_CCR(6) +#define SAM_TC6_CMR SAM_TC678_CMR(6) +#define SAM_TC6_SMMR SAM_TC678_SMMR(6) +#define SAM_TC6_RAB SAM_TC678_RAB(6) +#define SAM_TC6_CV SAM_TC678_CV(6) +#define SAM_TC6_RA SAM_TC678_RA(6) +#define SAM_TC6_RB SAM_TC678_RB(6) +#define SAM_TC6_RC SAM_TC678_RC(6) +#define SAM_TC6_SR SAM_TC678_SR(6) +#define SAM_TC6_IER SAM_TC678_IER(6) +#define SAM_TC6_IDR SAM_TC678_IDR(6) +#define SAM_TC6_IMR SAM_TC678_IMR(6) +#define SAM_TC6_EMR SAM_TC678_EMR(6) + +#define SAM_TC7_CCR SAM_TC678_CCR(7) +#define SAM_TC7_CMR SAM_TC678_CMR(7) +#define SAM_TC7_SMMR SAM_TC678_SMMR(7) +#define SAM_TC7_RAB SAM_TC678_RAB(7) +#define SAM_TC7_CV SAM_TC678_CV(7) +#define SAM_TC7_RA SAM_TC678_RA(7) +#define SAM_TC7_RB SAM_TC678_RB(7) +#define SAM_TC7_RC SAM_TC678_RC(7) +#define SAM_TC7_SR SAM_TC678_SR(7) +#define SAM_TC7_IER SAM_TC678_IER(7) +#define SAM_TC7_IDR SAM_TC678_IDR(7) +#define SAM_TC7_IMR SAM_TC678_IMR(7) +#define SAM_TC7_EMR SAM_TC678_EMR(7) + +#define SAM_TC8_CCR SAM_TC678_CCR(8) +#define SAM_TC8_CMR SAM_TC678_CMR(8) +#define SAM_TC8_SMMR SAM_TC678_SMMR(8) +#define SAM_TC8_RAB SAM_TC678_RAB(8) +#define SAM_TC8_CV SAM_TC678_CV(8) +#define SAM_TC8_RA SAM_TC678_RA(8) +#define SAM_TC8_RB SAM_TC678_RB(8) +#define SAM_TC8_RC SAM_TC678_RC(8) +#define SAM_TC8_SR SAM_TC678_SR(8) +#define SAM_TC8_IER SAM_TC678_IER(8) +#define SAM_TC8_IDR SAM_TC678_IDR(8) +#define SAM_TC8_IMR SAM_TC678_IMR(8) +#define SAM_TC8_EMR SAM_TC678_EMR(8) + +#define SAM_TC678_BCR (SAM_TC678_BASE+SAM_TC_BCR_OFFSET) +#define SAM_TC678_BMR (SAM_TC678_BASE+SAM_TC_BMR_OFFSET) +#define SAM_TC678_QIER (SAM_TC678_BASE+SAM_TC_QIER_OFFSET) +#define SAM_TC678_QIDR (SAM_TC678_BASE+SAM_TC_QIDR_OFFSET) +#define SAM_TC678_QIMR (SAM_TC678_BASE+SAM_TC_QIMR_OFFSET) +#define SAM_TC678_QISR (SAM_TC678_BASE+SAM_TC_QISR_OFFSET) +#define SAM_TC678_FMR (SAM_TC678_BASE+SAM_TC_FMR_OFFSET) +#define SAM_TC678_WPMR (SAM_TC678_BASE+SAM_TC_WPMR_OFFSET) + +#define SAM_TC901_CHAN_BASE(n) (SAM_TC901_BASE+SAM_TC_CHAN_OFFSET((n)-9)) + +#define SAM_TC901_CCRn(n) (SAM_TC901_BASE+SAM_TCn_CCR_OFFSET((n)-9)) +#define SAM_TC901_CMR(n) (SAM_TC901_BASE+SAM_TCn_CMR_OFFSET((n)-9)) +#define SAM_TC901_SMMR(n) (SAM_TC901_BASE+SAM_TCn_SMMR_OFFSET((n)-9)) +#define SAM_TC901_RAB(n) (SAM_TC901_BASE+SAM_TCn_RAB_OFFSET((n)-9)) +#define SAM_TC901_CV(n) (SAM_TC901_BASE+SAM_TCn_CV_OFFSET((n)-9)) +#define SAM_TC901_RA(n) (SAM_TC901_BASE+SAM_TCn_RA_OFFSET((n)-9)) +#define SAM_TC901_RB(n) (SAM_TC901_BASE+SAM_TCn_RB((n)-9)) +#define SAM_TC901_RC(n) (SAM_TC901_BASE+SAM_TCn_RC_OFFSET((n)-9)) +#define SAM_TC901_SR(n) (SAM_TC901_BASE+SAM_TCn_SR_OFFSET((n)-9)) +#define SAM_TC901_IER(n) (SAM_TC901_BASE+SAM_TCn_IER_OFFSET((n)-9)) +#define SAM_TC901_IDR(n) (SAM_TC901_BASE+SAM_TCn_IDR_OFFSET((n)-9)) +#define SAM_TC901_IMR(n) (SAM_TC901_BASE+SAM_TCn_IMR_OFFSET((n)-9)) +#define SAM_TC901_EMR(n) (SAM_TC901_BASE+SAM_TCn_EMR_OFFSET((n)-9)) + +#define SAM_TC9_CCR SAM_TC901_CCR(9) +#define SAM_TC9_CMR SAM_TC901_CMR(9) +#define SAM_TC9_SMMR SAM_TC901_SMMR(9) +#define SAM_TC9_RAB SAM_TC901_RAB(9) +#define SAM_TC9_CV SAM_TC901_CV(9) +#define SAM_TC9_RA SAM_TC901_RA(9) +#define SAM_TC9_RB SAM_TC901_RB(9) +#define SAM_TC9_RC SAM_TC901_RC(9) +#define SAM_TC9_SR SAM_TC901_SR(9) +#define SAM_TC9_IER SAM_TC901_IER(9) +#define SAM_TC9_IDR SAM_TC901_IDR(9) +#define SAM_TC9_IMR SAM_TC901_IMR(9) +#define SAM_TC9_EMR SAM_TC901_EMR(9) + +#define SAM_TC10_CCR SAM_TC901_CCR(10) +#define SAM_TC10_CMR SAM_TC901_CMR(10) +#define SAM_TC10_SMMR SAM_TC901_SMMR(10) +#define SAM_TC10_RAB SAM_TC901_RAB(10) +#define SAM_TC10_CV SAM_TC901_CV(10) +#define SAM_TC10_RA SAM_TC901_RA(10) +#define SAM_TC10_RB SAM_TC901_RB(10) +#define SAM_TC10_RC SAM_TC901_RC(10) +#define SAM_TC10_SR SAM_TC901_SR(10) +#define SAM_TC10_IER SAM_TC901_IER(10) +#define SAM_TC10_IDR SAM_TC901_IDR(10) +#define SAM_TC10_IMR SAM_TC901_IMR(10) +#define SAM_TC10_EMR SAM_TC901_EMR(10) + +#define SAM_TC11_CCR SAM_TC901_CCR(11) +#define SAM_TC11_CMR SAM_TC901_CMR(11) +#define SAM_TC11_SMMR SAM_TC901_SMMR(11) +#define SAM_TC11_RAB SAM_TC901_RAB(11) +#define SAM_TC11_CV SAM_TC901_CV(11) +#define SAM_TC11_RA SAM_TC901_RA(11) +#define SAM_TC11_RB SAM_TC901_RB(11) +#define SAM_TC11_RC SAM_TC901_RC(11) +#define SAM_TC11_SR SAM_TC901_SR(11) +#define SAM_TC11_IER SAM_TC901_IER(11) +#define SAM_TC11_IDR SAM_TC901_IDR(11) +#define SAM_TC11_IMR SAM_TC901_IMR(11) +#define SAM_TC11_EMR SAM_TC901_EMR(11) + +#define SAM_TC901_BCR (SAM_TC901_BASE+SAM_TC_BCR_OFFSET) +#define SAM_TC901_BMR (SAM_TC901_BASE+SAM_TC_BMR_OFFSET) +#define SAM_TC901_QIER (SAM_TC901_BASE+SAM_TC_QIER_OFFSET) +#define SAM_TC901_QIDR (SAM_TC901_BASE+SAM_TC_QIDR_OFFSET) +#define SAM_TC901_QIMR (SAM_TC901_BASE+SAM_TC_QIMR_OFFSET) +#define SAM_TC901_QISR (SAM_TC901_BASE+SAM_TC_QISR_OFFSET) +#define SAM_TC901_FMR (SAM_TC901_BASE+SAM_TC_FMR_OFFSET) +#define SAM_TC901_WPMR (SAM_TC901_BASE+SAM_TC_WPMR_OFFSET) + +/* TC Register Bit Definitions ******************************************************/ + +/* Channel Control Register */ + +#define TC_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */ +#define TC_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */ + +/* Channel Mode Register -- All modes */ + +#define TC_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection */ +#define TC_CMR_TCCLKS_MASK (7 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS(n) ((uint32_t)(n) << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_TCLK1 (0 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK1 Clock selected */ +# define TC_CMR_TCCLKS_TCLK2 (1 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK2 Clock selected */ +# define TC_CMR_TCCLKS_TCLK3 (2 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK3 Clock selected */ +# define TC_CMR_TCCLKS_TCLK4 (3 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK4 Clock selected */ +# define TC_CMR_TCCLKS_TCLK5 (4 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK5 Clock selected */ +# define TC_CMR_TCCLKS_XC0 (5 << TC_CMR_TCCLKS_SHIFT) /* XC0 Clock selected */ +# define TC_CMR_TCCLKS_XC1 (6 << TC_CMR_TCCLKS_SHIFT) /* XC1 Clock selected */ +# define TC_CMR_TCCLKS_XC2 (7 << TC_CMR_TCCLKS_SHIFT) /* XC2 Clock selected */ +#define TC_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert */ +#define TC_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection */ +#define TC_CMR_BURST_MASK (3 << TC_CMR_BURST_SHIFT) +# define TC_CMR_BURST_NONE (0 << TC_CMR_BURST_SHIFT) /* Clock not gated by external signal */ +# define TC_CMR_BURST_XC0 (1 << TC_CMR_BURST_SHIFT) /* XXC0 ANDed with clock */ +# define TC_CMR_BURST_XC1 (2 << TC_CMR_BURST_SHIFT) /* XC1 ANDed with clock */ +# define TC_CMR_BURST_XC2 (3 << TC_CMR_BURST_SHIFT) /* XC2 ANDed with clock */ + +/* Channel Mode Register -- Capture mode */ + +#define TC_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (1 << 7) /* Bit 7: Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG_MASK (3 << TC_CMR_ETRGEDG_SHIFT) +# define TC_CMR_ETRGEDG_NONE (0 << TC_CMR_ETRGEDG_SHIFT) /* Clock not gated by external signal */ +# define TC_CMR_ETRGEDG_RISING (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */ +# define TC_CMR_ETRGEDG_FALLING (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */ +# define TC_CMR_ETRGEDG_BOTH (3 << TC_CMR_ETRGEDG_SHIFT) /* EDGE Each edge */ +#define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */ +#define TC_CMR_CAPTURE (0) /* Bit 15: 0=Capture Mode */ +#define TC_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Edge Selection */ +#define TC_CMR_LDRA_MASK (3 << TC_CMR_LDRA_SHIFT) +# define TC_CMR_LDRA_NONE (0 << TC_CMR_LDRA_SHIFT) /* None */ +# define TC_CMR_LDRA_RISING (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ +# define TC_CMR_LDRA_FALLING (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ +# define TC_CMR_LDRA_BOTH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */ +#define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Edge Selection */ +#define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT) +# define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */ +# define TC_CMR_LDRB_RISING (1 << TC_CMR_LDRB_SHIFT) /* Rising edge of TIOA */ +# define TC_CMR_LDRB_FALLING (2 << TC_CMR_LDRB_SHIFT) /* Falling edge of TIOA */ +# define TC_CMR_LDRB_BOTH (3 << TC_CMR_LDRB_SHIFT) /* Each edge of TIOA */ +#define TC_CMR_SBSMPLR_SHIFT (20) /* Bits 20-22: Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR_MASK (7 << TC_CMR_SBSMPLR_SHIFT) +# define TC_CMR_SBSMPLR_ONE (0 << TC_CMR_SBSMPLR_SHIFT) /* Load on each selected edge */ +# define TC_CMR_SBSMPLR_HALF (1 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 2 selected edges */ +# define TC_CMR_SBSMPLR_4TH (2 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 4 selected edges */ +# define TC_CMR_SBSMPLR_8TH (3 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 8 selected edges */ +# define TC_CMR_SBSMPLR_16TH (4 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 16 selected edges */ + +/* Channel Mode Register -- Waveform mode */ + +#define TC_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection */ +#define TC_CMR_EEVTEDG_MASK (3 << TC_CMR_EEVTEDG_SHIFT) +# define TC_CMR_EEVTEDG_NONE (0 << TC_CMR_EEVTEDG_SHIFT) /* None */ +# define TC_CMR_EEVTEDG_RISING (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */ +# define TC_CMR_EEVTEDG_FALLING (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */ +# define TC_CMR_EEVTEDG_BOTH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */ +#define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection */ +#define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT) +# define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB(1) input */ +# define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 output */ +# define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 output */ +# define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 output */ +#define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable */ +#define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection */ +#define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT) +# define TC_CMR_WAVSEL_UP (0 << TC_CMR_WAVSEL_SHIFT) /* UP mode w/o trigger on RC Compare */ +# define TC_CMR_WAVSEL_UPDOWN (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o trigger on RC Compare */ +# define TC_CMR_WAVSEL_UPRC (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode w/ trigger on RC Compare */ +# define TC_CMR_WAVSEL_UPDOWNRC (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN w/ with trigger on RC Compare */ +#define TC_CMR_WAVE (1 << 15) /* Bit 15: 1=Waveform Mode */ +#define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA */ +#define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT) +# define TC_CMR_ACPA_NONE (0 << TC_CMR_ACPA_SHIFT) /* None */ +# define TC_CMR_ACPA_SET (1 << TC_CMR_ACPA_SHIFT) /* Set */ +# define TC_CMR_ACPA_CLEAR (2 << TC_CMR_ACPA_SHIFT) /* Clear */ +# define TC_CMR_ACPA_TOGGLE (3 << TC_CMR_ACPA_SHIFT) /* Toggle */ +#define TC_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA */ +#define TC_CMR_ACPC_MASK (3 << TC_CMR_ACPC_SHIFT) +# define TC_CMR_ACPC_NONE (0 << TC_CMR_ACPC_SHIFT) /* None */ +# define TC_CMR_ACPC_SET (1 << TC_CMR_ACPC_SHIFT) /* Set */ +# define TC_CMR_ACPC_CLEAR (2 << TC_CMR_ACPC_SHIFT) /* Clear */ +# define TC_CMR_ACPC_TOGGLE (3 << TC_CMR_ACPC_SHIFT) /* Toggle */ +#define TC_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA */ +#define TC_CMR_AEEVT_MASK (3 << TC_CMR_AEEVT_SHIFT) +# define TC_CMR_AEEVT_NONE (0 << TC_CMR_AEEVT_SHIFT) /* None */ +# define TC_CMR_AEEVT_SET (1 << TC_CMR_AEEVT_SHIFT) /* Set */ +# define TC_CMR_AEEVT_CLEAR (2 << TC_CMR_AEEVT_SHIFT) /* Clear */ +# define TC_CMR_AEEVT_TOGGLE (3 << TC_CMR_AEEVT_SHIFT) /* Toggle */ +#define TC_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG_MASK (3 << TC_CMR_ASWTRG_SHIFT) +# define TC_CMR_ASWTRG_NONE (0 << TC_CMR_ASWTRG_SHIFT) /* None */ +# define TC_CMR_ASWTRG_SET (1 << TC_CMR_ASWTRG_SHIFT) /* Set */ +# define TC_CMR_ASWTRG_CLEAR (2 << TC_CMR_ASWTRG_SHIFT) /* Clear */ +# define TC_CMR_ASWTRG_TOGGLE (3 << TC_CMR_ASWTRG_SHIFT) /* Toggle */ +#define TC_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB */ +#define TC_CMR_BCPB_MASK (3 << TC_CMR_BCPB_SHIFT) +# define TC_CMR_BCPB_NONE (0 << TC_CMR_BCPB_SHIFT) /* None */ +# define TC_CMR_BCPB_SET (1 << TC_CMR_BCPB_SHIFT) /* Set */ +# define TC_CMR_BCPB_CLEAR (2 << TC_CMR_BCPB_SHIFT) /* Clear */ +# define TC_CMR_BCPB_TOGGLE (3 << TC_CMR_BCPB_SHIFT) /* Toggle */ +#define TC_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB */ +#define TC_CMR_BCPC_MASK (3 << TC_CMR_BCPC_SHIFT) +# define TC_CMR_BCPC_NONE (0 << TC_CMR_BCPC_SHIFT) /* None */ +# define TC_CMR_BCPC_SET (1 << TC_CMR_BCPC_SHIFT) /* Set */ +# define TC_CMR_BCPC_CLEAR (2 << TC_CMR_BCPC_SHIFT) /* Clear */ +# define TC_CMR_BCPC_TOGGLE (3 << TC_CMR_BCPC_SHIFT) /* Toggle */ +#define TC_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB */ +#define TC_CMR_BEEVT_MASK (3 << TC_CMR_BEEVT_SHIFT) +# define TC_CMR_BEEVT_NONE (0 << TC_CMR_BEEVT_SHIFT) /* None */ +# define TC_CMR_BEEVT_SET (1 << TC_CMR_BEEVT_SHIFT) /* Set */ +# define TC_CMR_BEEVT_CLEAR (2 << TC_CMR_BEEVT_SHIFT) /* Clear */ +# define TC_CMR_BEEVT_TOGGLE (3 << TC_CMR_BEEVT_SHIFT) /* Toggle */ +#define TC_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG_MASK (3 << TC_CMR_BSWTRG_SHIFT) +# define TC_CMR_BSWTRG_NONE (0 << TC_CMR_BSWTRG_SHIFT) /* None */ +# define TC_CMR_BSWTRG_SET (1 << TC_CMR_BSWTRG_SHIFT) /* Set */ +# define TC_CMR_BSWTRG_CLEAR (2 << TC_CMR_BSWTRG_SHIFT) /* Clear */ +# define TC_CMR_BSWTRG_TOGGLE (3 << TC_CMR_BSWTRG_SHIFT) /* Toggle */ + +/* Stepper Motor Mode Register */ + +#define TC_SMMR_GCEN (1 << 0) /* Bit 0: Gray Count Enable */ +#define TC_SMMR_DOWN (1 << 1) /* Bit 1: DOWN Count */ + +/* Register AB (32-bit capture value) */ +/* Counter Value (32-bit counter value) */ +/* Register A (32-bit value) */ +/* Register B (32-bit value) */ +/* Register C (32-bit value) */ + +/* Status Register, Interrupt Enable Register, Interrupt Disable Register, and + * Interrupt Mask Register + */ + +#define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow Status */ +#define TC_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun Status */ +#define TC_INT_CPAS (1 << 2) /* Bit 2: RA Compare Status */ +#define TC_INT_CPBS (1 << 3) /* Bit 3: RB Compare Status */ +#define TC_INT_CPCS (1 << 4) /* Bit 4: RC Compare Status */ +#define TC_INT_LDRAS (1 << 5) /* Bit 5: RA Loading Status */ +#define TC_INT_LDRBS (1 << 6) /* Bit 6: RB Loading Status */ +#define TC_INT_ETRGS (1 << 7) /* Bit 7: External Trigger Status */ +#define TC_INT_ALL (0xff) + +#define TC_SR_CLKSTA (1 << 16) /* Bit 16: Clock Enabling Status */ +#define TC_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror */ +#define TC_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror */ + +/* Extended Mode Register */ + +#define TC_EMR_TRIGSRCA_SHIFT (0) /* Bits 0-1: Trigger source for input A */ +#define TC_EMR_TRIGSRCA_MASK (3 << TC_EMR_TRIGSRCA_SHIFT) +# define TC_EMR_TRIGSRCA_TIOA (0 << TC_EMR_TRIGSRCA_SHIFT) /* Trigger/capture input A driven by TIOAx */ +# define TC_EMR_TRIGSRCA_PWM (1 << TC_EMR_TRIGSRCA_SHIFT) /* Trigger/capture input A driven by PWMx */ +#define TC_EMR_TRIGSRCB_SHIFT (4) /* Bits 4-5: Trigger source for input B */ +#define TC_EMR_TRIGSRCB_MASK (3 << TC_EMR_TRIGSRCB_SHIFT) +# define TC_EMR_TRIGSRCB_TIOB (0 << TC_EMR_TRIGSRCB_SHIFT) /* Trigger/capture input B driven by TIOBx */ +# define TC_EMR_TRIGSRCB_PWM (1 << TC_EMR_TRIGSRCB_SHIFT) /* Trigger/capture input B driven PWMx */ +#define TC_EMR_NODIVCLK (1 << 8) /* Bit 8: No divided clock */ + +/* Block Control Register */ + +#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command */ + +/* Block Mode Register */ + +#define TC_BMR_TC0XC0S_SHIFT (0) /* Bits 0-1: External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_MASK (3 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT) /* TCLK0 Signal to XC0 */ +# define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT) /* TIOA1 Signal to XC0 */ +# define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT) /* TIOA2 Signal to XC0 */ +#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT) /* TCLK1 Signal to XC1 */ +# define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT) /* TIOA0 Signal to XC1 */ +# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) /* TIOA2 Signal to XC1 */ +#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) /* TCLK2 Signal to XC2 */ +# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) /* TIOA0 Signal to XC2 */ +# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) /* TIOA1 Signal to XC2 */ +#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder ENabled */ +#define TC_BMR_POSEN (1 << 9) /* Bit 9: POSition ENabled */ +#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: SPEED ENabled */ +#define TC_BMR_QDTRANS (1 << 11) /* Bit 11: Quadrature Decoding TRANSparent */ +#define TC_BMR_EDGPHA (1 << 12) /* Bit 12: EDGe on PHA count mode */ +#define TC_BMR_INVA (1 << 13) /* Bit 13: INVerted phA */ +#define TC_BMR_INVB (1 << 14) /* Bit 14: INVerted phB */ +#define TC_BMR_INVIDX (1 << 15) /* Bit 15: INVerted InDeX */ +#define TC_BMR_SWAP (1 << 16) /* Bit 16: SWAP PHA and PHB */ +#define TC_BMR_IDXPHB (1 << 17) /* Bit 17: InDeX pin is PHB pin */ +#define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: MAXimum FILTer */ +#define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT) +# define TC_BMR_MAXFILT(n) ((uint32_t)(n) << TC_BMR_MAXFILT_SHIFT) + +/* QDEC Interrupt Enable Register, QDEC Interrupt Disable Register, QDEC Interrupt Mask Register, and QDEC Interrupt Status Register. + */ + +#define TC_QINT_IDX (1 << 0) /* Bit 0: Index */ +#define TC_QINT_DIRCHG (1 << 1) /* Bit 1: Direction change */ +#define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature ERRor */ + +#define TC_QISR_DIRR (1 << 8) /* Bit 8: Direction */ + +/* Fault Mode Register */ + +#define TC_FMR_ENCF0 (1 << 0) /* Bit 0: ENable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (1 << 1) /* Bit 1: ENable Compare Fault Channel 1 */ + +/* Write Protect Mode Register */ + +#define TC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define TC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define TC_WPMR_WPKEY_MASK (0xffffff << TC_WPMR_WPKEY_SHIFT) +# define TC_WPMR_WPKEY (0x54494d << TC_WPMR_WPKEY_SHIFT) /* "TIM" in ASCII */ + +#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H */ diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c new file mode 100644 index 00000000000..2ccacb08727 --- /dev/null +++ b/arch/arm/src/samv7/sam_tc.c @@ -0,0 +1,1535 @@ +/**************************************************************************** + * arch/arm/src/SAMV7/sam_tc.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * + * SAMV71 Series Data Sheet + * NuttX SAMA5 timer/counter driver + * Atmel NoOS sample code for the SAMA5. + * + * The Atmel sample code has a BSD compatible license that requires this + * copyright notice: + * + * Copyright (c) 2011, Atmel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the names NuttX nor Atmel nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "sam_periphclks.h" +#include "chip/sam_pinmap.h" +#include "chip/sam_pmc.h" +#include "sam_gpio.h" +#include "sam_tc.h" + +#if defined(CONFIG_SAMV7_TC0) || defined(CONFIG_SAMV7_TC1) || \ + defined(CONFIG_SAMV7_TC2) || defined(CONFIG_SAMV7_TC3) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ +/* This structure describes the static configuration of a TC channel */ + +struct sam_chconfig_s +{ + uintptr_t base; /* Channel register base address */ + gpio_pinset_t clkset; /* CLK input PIO configuration */ + gpio_pinset_t tioaset; /* Output A PIO configuration */ + gpio_pinset_t tiobset; /* Output B PIO configuration */ +}; + +/* This structure describes the static configuration of a TC */ + +struct sam_tcconfig_s +{ + uintptr_t base; /* TC register base address */ + uint8_t pid; /* Peripheral ID */ + uint8_t chfirst; /* First channel number */ + uint8_t tc; /* Timer/counter number */ + + /* Channels */ + + struct sam_chconfig_s channel[3]; +}; + +/* This structure describes one timer counter channel */ + +struct sam_tc_s; +struct sam_chan_s +{ + struct sam_tc_s *tc; /* Parent timer/counter */ + uintptr_t base; /* Channel register base address */ + tc_handler_t handler; /* Attached interrupt handler */ + void *arg; /* Interrupt handler argument */ + uint8_t chan; /* Channel number (0, 1, or 2 OR 3, 4, or 5) */ + bool inuse; /* True: channel is in use */ +}; + +/* This structure describes one timer/counter */ + +struct sam_tc_s +{ + sem_t exclsem; /* Assures mutually exclusive access to TC */ + uintptr_t base; /* Register base address */ + uint8_t pid; /* Peripheral ID/irq number */ + uint8_t tc; /* Timer/channel number (0 or 1) */ + bool initialized; /* True: Timer data has been initialized */ + + /* Channels */ + + struct sam_chan_s channel[3]; + + /* Debug stuff */ + +#ifdef CONFIG_SAMV7_TC_REGDEBUG + bool wr; /* True:Last was a write */ + uint32_t regaddr; /* Last address */ + uint32_t regval; /* Last value */ + int ntimes; /* Number of times */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers ********************************************************/ + +static void sam_takesem(struct sam_tc_s *tc); +#define sam_givesem(tc) (sem_post(&tc->exclsem)) + +#ifdef CONFIG_SAMV7_TC_REGDEBUG +static void sam_regdump(struct sam_chan_s *chan, const char *msg); +static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, + uint32_t regval); +#else +# define sam_regdump(chan,msg) +# define sam_checkreg(tc,wr,regaddr,regval) (false) +#endif + +static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, + unsigned int offset); +static inline void sam_tc_putreg(struct sam_chan_s *chan, + unsigned int offset, uint32_t regval); + +static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, + unsigned int offset); +static inline void sam_chan_putreg(struct sam_chan_s *chan, + unsigned int offset, uint32_t regval); + +/* Interrupt Handling *******************************************************/ + +static int sam_tc_interrupt(struct sam_tc_s *tc); +#ifdef CONFIG_SAMV7_TC0 +static int sam_tc012_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_SAMV7_TC1 +static int sam_tc345_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_SAMV7_TC2 +static int sam_tc678_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_SAMV7_TC3 +static int sam_tc901_interrupt(int irq, void *context); +#endif + +/* Initialization ***********************************************************/ + +static int sam_tc_freqdiv_lookup(uint32_t ftcin, int ndx); +static uint32_t sam_tc_divfreq_lookup(uint32_t ftcin, int ndx); +static inline struct sam_chan_s *sam_tc_initialize(int channel); + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* Static timer configuration */ + +#ifdef CONFIG_SAMV7_TC0 +static const struct sam_tcconfig_s g_tc012config = +{ + .base = SAM_TC012_BASE, + .pid = SAM_PID_TC0, + .chfirst = 0, + .tc = 0, + .channel = + { + [0] = + { + .base = SAM_TC012_CHAN_BASE(0), +#ifdef CONFIG_SAMV7_TC0_CLK0 + .clkset = PIO_TC0_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC0_TIOA0 + .tioaset = PIO_TC0_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC0_TIOB0 + .tiobset = PIO_TC0_IOB, +#else + .tiobset = 0, +#endif + }, + [1] = + { + .base = SAM_TC012_CHAN_BASE(1), +#ifdef CONFIG_SAMV7_TC0_CLK1 + .clkset = PIO_TC1_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC0_TIOA1 + .tioaset = PIO_TC1_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC0_TIOB1 + .tiobset = PIO_TC1_IOB, +#else + .tiobset = 0, +#endif + }, + [2] = + { + .base = SAM_TC012_CHAN_BASE(2), +#ifdef CONFIG_SAMV7_TC0_CLK2 + .clkset = PIO_TC2_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC0_TIOA2 + .tioaset = PIO_TC2_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC0_TIOB2 + .tiobset = PIO_TC2_IOB, +#else + .tiobset = 0, +#endif + }, + }, +}; +#endif + +#ifdef CONFIG_SAMV7_TC1 +static const struct sam_tcconfig_s g_tc345config = +{ + .base = SAM_TC345_BASE, + .pid = SAM_PID_TC1, + .chfirst = 3, + .tc = 1, + .channel = + { + [0] = + { + .base = SAM_TC345_CHAN_BASE(3), +#ifdef CONFIG_SAMV7_TC1_CLK3 + .clkset = PIO_TC3_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC1_TIOA3 + .tioaset = PIO_TC3_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC1_TIOB3 + .tiobset = PIO_TC3_IOB, +#else + .tiobset = 0, +#endif + }, + [1] = + { + .base = SAM_TC345_CHAN_BASE(4), +#ifdef CONFIG_SAMV7_TC1_CLK4 + .clkset = PIO_TC4_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC1_TIOA4 + .tioaset = PIO_TC4_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC1_TIOB4 + .tiobset = PIO_TC4_IOB, +#else + .tiobset = 0, +#endif + }, + [2] = + { + .base = SAM_TC345_CHAN_BASE(5), +#ifdef CONFIG_SAMV7_TC1_CLK5 + .clkset = PIO_TC5_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC1_TIOA5 + .tioaset = PIO_TC5_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC1_TIOB5 + .tiobset = PIO_TC5_IOB, +#else + .tiobset = 0, +#endif + }, + }, +}; +#endif + +#ifdef CONFIG_SAMV7_TC2 +static const struct sam_tcconfig_s g_tc678config = +{ + .base = SAM_TC678_BASE, + .pid = SAM_PID_TC2, + .chfirst = 6, + .tc = 2, + .channel = + { + [0] = + { + .base = SAM_TC678_CHAN_BASE(6), +#ifdef CONFIG_SAMV7_TC2_CLK6 + .clkset = PIO_TC6_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOA6 + .tioaset = PIO_TC6_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOB6 + .tiobset = PIO_TC6_IOB, +#else + .tiobset = 0, +#endif + }, + [1] = + { + .base = SAM_TC678_CHAN_BASE(7), +#ifdef CONFIG_SAMV7_TC2_CLK7 + .clkset = PIO_TC7_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOA7 + .tioaset = PIO_TC7_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOB7 + .tiobset = PIO_TC7_IOB, +#else + .tiobset = 0, +#endif + }, + [2] = + { + .base = SAM_TC345_CHAN_BASE(8), +#ifdef CONFIG_SAMV7_TC2_CLK8 + .clkset = PIO_TC8_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOA8 + .tioaset = PIO_TC8_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOB8 + .tiobset = PIO_TC8_IOB, +#else + .tiobset = 0, +#endif + }, + }, +}; +#endif + +#ifdef CONFIG_SAMV7_TC3 +static const struct sam_tcconfig_s g_tc901config = +{ + .base = SAM_TC901_BASE, + .pid = SAM_PID_TC3, + .chfirst = 9, + .tc = 3, + .channel = + { + [0] = + { + .base = SAM_TC901_CHAN_BASE(9), +#ifdef CONFIG_SAMV7_TC2_CLK9 + .clkset = PIO_TC9_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOA9 + .tioaset = PIO_TC9_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOB9 + .tiobset = PIO_TC9_IOB, +#else + .tiobset = 0, +#endif + }, + [1] = + { + .base = SAM_TC901_CHAN_BASE(10), +#ifdef CONFIG_SAMV7_TC2_CLK10 + .clkset = PIO_TC10_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOA10 + .tioaset = PIO_TC10_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOB10 + .tiobset = PIO_TC10_IOB, +#else + .tiobset = 0, +#endif + }, + [2] = + { + .base = SAM_TC345_CHAN_BASE(11), +#ifdef CONFIG_SAMV7_TC2_CLK11 + .clkset = PIO_TC11_CLK, +#else + .clkset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOA11 + .tioaset = PIO_TC11_IOA, +#else + .tioaset = 0, +#endif +#ifdef CONFIG_SAMV7_TC2_TIOB11 + .tiobset = PIO_TC11_IOB, +#else + .tiobset = 0, +#endif + }, + }, +}; +#endif + +/* Timer/counter state */ + +#ifdef CONFIG_SAMV7_TC0 +static struct sam_tc_s g_tc012; +#endif + +#ifdef CONFIG_SAMV7_TC1 +static struct sam_tc_s g_tc345; +#endif + +#ifdef CONFIG_SAMV7_TC2 +static struct sam_tc_s g_tc678; +#endif + +#ifdef CONFIG_SAMV7_TC3 +static struct sam_tc_s g_tc901; +#endif + +/* TC frequency data. This table provides the frequency for each selection of TCCLK */ + +#define TC_NDIVIDERS 4 +#define TC_NDIVOPTIONS 5 + +/* This is the list of divider values: divider = (1 << value) */ + +static const uint8_t g_log2divider[TC_NDIVIDERS] = +{ + 1, /* TIMER_CLOCK1 -> div2 */ + 3, /* TIMER_CLOCK2 -> div8 */ + 5, /* TIMER_CLOCK3 -> div32 */ + 7 /* TIMER_CLOCK4 -> div128 */ +}; + +/* TC register lookup used by sam_tc_setregister */ + +#define TC_NREGISTERS 3 + +static const uint8_t g_regoffset[TC_NREGISTERS] = +{ + SAM_TC_RA_OFFSET, /* Register A */ + SAM_TC_RB_OFFSET, /* Register B */ + SAM_TC_RC_OFFSET /* Register C */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ +/**************************************************************************** + * Low-level Helpers + ****************************************************************************/ +/**************************************************************************** + * Name: sam_takesem + * + * Description: + * Take the wait semaphore (handling false alarm wakeups due to the receipt + * of signals). + * + * Input Parameters: + * dev - Instance of the SDIO device driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sam_takesem(struct sam_tc_s *tc) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&tc->exclsem) != 0) + { + /* The only case that an error should occr here is if the wait was + * awakened by a signal. + */ + + ASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: sam_regdump + * + * Description: + * Dump all timer/counter channel and global registers + * + * Input Parameters: + * chan - The timer/counter channel state + * msg - Message to print with the data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_TC_REGDEBUG +static void sam_regdump(struct sam_chan_s *chan, const char *msg) +{ + struct sam_tc_s *tc = chan->tc; + uintptr_t base; + + base = tc->base; + lldbg("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); + lldbg(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), + getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); + + base = chan->base; + lldbg("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); + lldbg(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), + getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); + lldbg(" RA: %08x RB: %08x RC: %08x SR: %08x\n", + getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), + getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET)); + lldbg(" IMR: %08x\n", + getreg32(base+SAM_TC_IMR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: sam_checkreg + * + * Description: + * Check if the current register access is a duplicate of the preceding. + * + * Input Parameters: + * tc - The timer/counter peripheral state + * wr - True:write access false:read access + * regval - The regiser value associated with the access + * regaddr - The address of the register being accessed + * + * Returned Value: + * true: This is the first register access of this type. + * flase: This is the same as the preceding register access. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_TC_REGDEBUG +static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, + uint32_t regval) +{ + if (wr == tc->wr && /* Same kind of access? */ + regaddr == tc->regaddr && /* Same register address? */ + regval == tc->regval) /* Same register value? */ + { + /* Yes, then just keep a count of the number of times we did this. */ + + tc->ntimes++; + return false; + } + else + { + /* Did we do the previous operation more than once? */ + + if (tc->ntimes > 0) + { + /* Yes... show how many times we did it */ + + lldbg("...[Repeats %d times]...\n", tc->ntimes); + } + + /* Save information about the new access */ + + tc->wr = wr; + tc->regval = regval; + tc->regaddr = regaddr; + tc->ntimes = 0; + } + + /* Return true if this is the first time that we have done this operation */ + + return true; +} +#endif + +/**************************************************************************** + * Name: sam_tc_getreg + * + * Description: + * Read an SPI register + * + ****************************************************************************/ + +static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, + unsigned int offset) +{ + struct sam_tc_s *tc = chan->tc; + uint32_t regaddr = tc->base + offset; + uint32_t regval = getreg32(regaddr); + +#ifdef CONFIG_SAMV7_TC_REGDEBUG + if (sam_checkreg(tc, false, regaddr, regval)) + { + lldbg("%08x->%08x\n", regaddr, regval); + } +#endif + + return regval; +} + +/**************************************************************************** + * Name: sam_tc_putreg + * + * Description: + * Write a value to an SPI register + * + ****************************************************************************/ + +static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, + unsigned int offset) +{ + struct sam_tc_s *tc = chan->tc; + uint32_t regaddr = tc->base + offset; + +#ifdef CONFIG_SAMV7_TC_REGDEBUG + if (sam_checkreg(tc, true, regaddr, regval)) + { + lldbg("%08x<-%08x\n", regaddr, regval); + } +#endif + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: sam_chan_getreg + * + * Description: + * Read an SPI register + * + ****************************************************************************/ + +static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, + unsigned int offset) +{ + uint32_t regaddr = chan->base + offset; + uint32_t regval = getreg32(regaddr); + +#ifdef CONFIG_SAMV7_TC_REGDEBUG + if (sam_checkreg(chan->tc, false, regaddr, regval)) + { + lldbg("%08x->%08x\n", regaddr, regval); + } +#endif + + return regval; +} + +/**************************************************************************** + * Name: sam_chan_putreg + * + * Description: + * Write a value to an SPI register + * + ****************************************************************************/ + +static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, + uint32_t regval) +{ + uint32_t regaddr = chan->base + offset; + +#ifdef CONFIG_SAMV7_TC_REGDEBUG + if (sam_checkreg(chan->tc, true, regaddr, regval)) + { + lldbg("%08x<-%08x\n", regaddr, regval); + } +#endif + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Interrupt Handling + ****************************************************************************/ +/**************************************************************************** + * Name: sam_tc_interrupt + * + * Description: + * Common timer channel interrupt handling. + * + * Input Parameters: + * tc Timer status instance + * + * Returned Value: + * A pointer to the initialized timer channel structure associated with tc + * and channel. NULL is returned on any failure. + * + * On successful return, the caller holds the tc exclusive access semaphore. + * + ****************************************************************************/ + +static int sam_tc_interrupt(struct sam_tc_s *tc) +{ + struct sam_chan_s *chan; + uint32_t sr; + uint32_t imr; + uint32_t pending; + int i; + + /* Process interrupts on each channel */ + + for (i = 0; i < 3; i++) + { + /* Get the handy channel reference */ + + chan = &tc->channel[i]; + + /* Get the interrupt status for this channel */ + + sr = sam_chan_getreg(chan, SAM_TC_SR_OFFSET); + imr = sam_chan_getreg(chan, SAM_TC_IMR_OFFSET); + pending = sr & imr; + + /* Are there any pending interrupts for this channel? */ + + if (pending) + { + /* Yes... if we have pending interrupts then interrupts must be + * enabled and we must have a handler attached. + */ + + DEBUGASSERT(chan->handler); + if (chan->handler) + { + /* Execute the callback */ + + chan->handler(chan, chan->arg, sr); + } + else + { + /* Should never happen */ + + sam_chan_putreg(chan, SAM_TC_IDR_OFFSET, TC_INT_ALL); + } + } + } + + return OK; +} + +/**************************************************************************** + * Name: sam_tcABC_interrupt + * + * Description: + * Timer block interrupt handlers + * + * Input Parameters: + * chan TC channel structure + * sr The status register value that generated the interrupt + * + * Returned Value: + * A pointer to the initialized timer channel structure associated with tc + * and channel. NULL is returned on any failure. + * + * On successful return, the caller holds the tc exclusive access semaphore. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_TC0 +static int sam_tc012_interrupt(int irq, void *context) +{ + return sam_tc_interrupt(&g_tc012); +} +#endif + +#ifdef CONFIG_SAMV7_TC1 +static int sam_tc345_interrupt(int irq, void *context) +{ + return sam_tc_interrupt(&g_tc345); +} +#endif + +#ifdef CONFIG_SAMV7_TC2 +static int sam_tc678_interrupt(int irq, void *context) +{ + return sam_tc_interrupt(&g_tc678); +} +#endif + +#ifdef CONFIG_SAMV7_TC3 +static int sam_tc901_interrupt(int irq, void *context) +{ + return sam_tc_interrupt(&g_tc901); +} +#endif + +/**************************************************************************** + * Initialization + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_tc_freqdiv_lookup + * + * Description: + * Given the TC input frequency (Ftcin) and a divider index, return the value of + * the Ftcin divider. + * + * Input Parameters: + * ftcin - TC input frequency + * ndx - Divider index + * + * Returned Value: + * The Ftcin input divider value + * + ****************************************************************************/ + +static int sam_tc_freqdiv_lookup(uint32_t ftcin, int ndx) +{ + /* The final option is to use the SLOW clock */ + + if (ndx >= TC_NDIVIDERS) + { + /* Not really a divider. In this case, the board is actually driven + * by the 32.768KHz slow clock. This returns a value that looks like + * correct divider if MCK were the input. + */ + + return ftcin / BOARD_SLOWCLK_FREQUENCY; + } + else + { + return 1 << g_log2divider[ndx]; + } +} + +/**************************************************************************** + * Name: sam_tc_divfreq_lookup + * + * Description: + * Given the TC input frequency (Ftcin) and a divider index, return the + * value of the divided frequency + * + * Input Parameters: + * ftcin - TC input frequency + * ndx - Divider index + * + * Returned Value: + * The divided frequency value + * + ****************************************************************************/ + +static uint32_t sam_tc_divfreq_lookup(uint32_t ftcin, int ndx) +{ + /* The final option is to use the SLOW clock */ + + if (ndx >= TC_NDIVIDERS) + { + return BOARD_SLOWCLK_FREQUENCY; + } + else + { + return ftcin >> g_log2divider[ndx]; + } +} + +/**************************************************************************** + * Name: sam_tc_initialize + * + * Description: + * There is no global, one-time initialization of timer/counter data + * structures. Rather, this function is called each time that a channel + * is allocated and, if the channel has not been initialized, it will be + * initialized then. + * + * Input Parameters: + * channel TC channel number (see TC_CHANx definitions) + * + * Returned Value: + * A pointer to the initialized timer channel structure associated with tc + * and channel. NULL is returned on any failure. + * + * On successful return, the caller holds the tc exclusive access semaphore. + * + ****************************************************************************/ + +static inline struct sam_chan_s *sam_tc_initialize(int channel) +{ + struct sam_tc_s *tc; + const struct sam_tcconfig_s *tcconfig; + struct sam_chan_s *chan; + const struct sam_chconfig_s *chconfig; + irqstate_t flags; + xcpt_t handler; + uint32_t regval; + uint8_t ch; + int i; + + /* Select the timer/counter and get the index associated with the + * channel. + */ + +#ifdef CONFIG_SAMV7_TC0 + if (channel >= 0 && channel < 3) + { + tc = &g_tc012; + tcconfig = &g_tc012config; + handler = sam_tc012_interrupt; + } + else +#endif +#ifdef CONFIG_SAMV7_TC1 + if (channel >= 3 && channel < 6) + { + tc = &g_tc345; + tcconfig = &g_tc345config; + handler = sam_tc345_interrupt; + } + else +#endif +#ifdef CONFIG_SAMV7_TC2 + if (channel >= 6 && channel < 9) + { + tc = &g_tc678; + tcconfig = &g_tc678config; + handler = sam_tc678_interrupt; + } + else +#endif +#ifdef CONFIG_SAMV7_TC3 + if (channel >= 9 && channel < 12) + { + tc = &g_tc901; + tcconfig = &g_tc901config; + handler = sam_tc901_interrupt; + } + else +#endif + { + /* Timer/counter is not invalid or not enabled */ + + tcdbg("ERROR: Bad channel number: %d\n", channel); + return NULL; + } + + /* Has the timer counter been initialized. We have to be careful here + * because there is no semaphore protection. + */ + + flags = irqsave(); + if (!tc->initialized) + { + /* Initialize the timer counter data structure. */ + + memset(tc, 0, sizeof(struct sam_tc_s)); + sem_init(&tc->exclsem, 0, 1); + tc->base = tcconfig->base; + tc->tc = channel < 3 ? 0 : 1; + tc->pid = tcconfig->pid; + + /* Initialize the channels */ + + for (i = 0, ch = tcconfig->chfirst; i < SAM_TC_NCHANNELS; i++) + { + tcdbg("Initializing TC%d channel %d\n", tcconfig->tc, ch); + + /* Initialize the channel data structure */ + + chan = &tc->channel[i]; + chconfig = &tcconfig->channel[i]; + + chan->tc = tc; + chan->base = chconfig->base; + chan->chan = ch++; + + /* Configure channel input/output pins */ + + if (chconfig->clkset) + { + /* Configure clock input pin */ + + sam_configgpio(chconfig->clkset); + } + + if (chconfig->tioaset) + { + /* Configure output A pin */ + + sam_configgpio(chconfig->tioaset); + } + + if (chconfig->tiobset) + { + /* Configure output B pin */ + + sam_configgpio(chconfig->tiobset); + } + + /* Disable and clear all channel interrupts */ + + sam_chan_putreg(chan, SAM_TC_IDR_OFFSET, TC_INT_ALL); + (void)sam_chan_getreg(chan, SAM_TC_SR_OFFSET); + } + + /* Set the maximum TC peripheral clock frequency */ + + regval = PMC_PCR_PID(tcconfig->pid) | PMC_PCR_CMD | PMC_PCR_EN; + putreg32(regval, SAM_PMC_PCR); + + /* Enable clocking to the timer counter */ + + sam_enableperiph0(tcconfig->pid); + + /* Attach the timer interrupt handler and enable the timer interrupts */ + + (void)irq_attach(tc->pid, handler); + up_enable_irq(tc->pid); + + /* Now the channel is initialized */ + + tc->initialized = true; + } + + /* Get exclusive access to the timer/count data structure */ + + sam_takesem(tc); + irqrestore(flags); + + /* Get the requested channel structure */ + + chan = &tc->channel[channel - tcconfig->chfirst]; + + /* Is it available? */ + + if (chan->inuse) + { + /* No.. return a failure */ + + tcdbg("Channel %d is in-used\n", channel); + sam_givesem(tc); + return NULL; + } + + /* Mark the channel "inuse" */ + + chan->inuse = true; + + /* And return the channel with the semaphore locked */ + + sam_regdump(chan, "Initialized"); + return chan; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ +/**************************************************************************** + * Name: sam_tc_allocate + * + * Description: + * Configures a Timer Counter to operate in the given mode. The timer is + * stopped after configuration and must be restarted with sam_tc_start(). + * All the interrupts of the timer are also disabled. + * + * Input Parameters: + * channel TC channel number (see TC_CHANx definitions) + * mode Operating mode (TC_CMR value). + * + * Returned Value: + * On success, a non-NULL handle value is returned. This handle may be + * used with subsequent timer/counter interfaces to manage the timer. A + * NULL handle value is returned on a failure. + * + ****************************************************************************/ + +TC_HANDLE sam_tc_allocate(int channel, int mode) +{ + struct sam_chan_s *chan; + + /* Initialize the timer/counter data (if necessary) and get exclusive + * access to the requested channel. + */ + + tcvdbg("channel=%d mode=%08x\n", channel, mode); + + chan = sam_tc_initialize(channel); + if (chan) + { + /* Disable TC clock */ + + sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS); + + /* Disable channel interrupts */ + + sam_chan_putreg(chan, SAM_TC_IDR_OFFSET, TC_INT_ALL); + + /* Clear and pending status */ + + (void)sam_chan_getreg(chan, SAM_TC_SR_OFFSET); + + /* And set the requested mode */ + + sam_chan_putreg(chan, SAM_TC_CMR_OFFSET, mode); + sam_regdump(chan, "Allocated"); + sam_givesem(chan->tc); + } + + /* Return an opaque reference to the channel */ + + tcvdbg("Returning %p\n", chan); + return (TC_HANDLE)chan; +} + +/**************************************************************************** + * Name: sam_tc_free + * + * Description: + * Release the handle previously allocated by sam_tc_allocate(). + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sam_tc_free(TC_HANDLE handle) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + + tcvdbg("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse); + DEBUGASSERT(chan && chan->inuse); + + /* Make sure that interrupts are detached and disabled and that the channel + * is stopped and disabled. + */ + + sam_tc_attach(handle, NULL, NULL, 0); + sam_tc_stop(handle); + + /* Mark the channel as available */ + + chan->inuse = false; +} + +/**************************************************************************** + * Name: sam_tc_start + * + * Description: + * Reset and Start the TC Channel. Enables the timer clock and performs a + * software reset to start the counting. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * + ****************************************************************************/ + +void sam_tc_start(TC_HANDLE handle) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + + tcvdbg("Starting channel %d inuse=%d\n", chan->chan, chan->inuse); + DEBUGASSERT(chan && chan->inuse); + + /* Read the SR to clear any pending interrupts on this channel */ + + (void)sam_chan_getreg(chan, SAM_TC_SR_OFFSET); + + /* Then enable the timer (by setting the CLKEN bit). Setting SWTRIG + * will also reset the timer counter and starting the timer. + */ + + sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKEN | TC_CCR_SWTRG); + sam_regdump(chan, "Started"); +} + +/**************************************************************************** + * Name: sam_tc_stop + * + * Description: + * Stop TC Channel. Disables the timer clock, stopping the counting. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * + ****************************************************************************/ + +void sam_tc_stop(TC_HANDLE handle) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + + tcvdbg("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse); + DEBUGASSERT(chan && chan->inuse); + + sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS); + sam_regdump(chan, "Stopped"); +} + +/**************************************************************************** + * Name: sam_tc_attach + * + * Description: + * Attach or detach an interrupt handler to the timer interrupt. The + * interrupt is detached if the handler argument is NULL. + * + * Input Parameters: + * handle The handle that represents the timer state + * handler The interrupt handler that will be invoked when the interrupt + * condition occurs + * arg An opaque argument that will be provided when the interrupt + * handler callback is executed. + * mask The value of the timer interrupt mask register that defines + * which interrupts should be disabled. + * + * Returned Value: + * + ****************************************************************************/ + +tc_handler_t sam_tc_attach(TC_HANDLE handle, tc_handler_t handler, + void *arg, uint32_t mask) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + tc_handler_t oldhandler; + irqstate_t flags; + + DEBUGASSERT(chan); + + /* Remember the old interrupt handler and set the new handler */ + + flags = irqsave(); + oldhandler = chan->handler; + chan->handler = handler; + + /* Don't enable interrupt if we are detaching no matter what the caller + * says. + */ + + if (!handler) + { + arg = NULL; + mask = 0; + } + + chan->arg = arg; + + /* Now enable interrupt as requested */ + + sam_chan_putreg(chan, SAM_TC_IDR_OFFSET, TC_INT_ALL & ~mask); + sam_chan_putreg(chan, SAM_TC_IER_OFFSET, TC_INT_ALL & mask); + irqrestore(flags); + + return oldhandler; +} + +/**************************************************************************** + * Name: sam_tc_getpending + * + * Description: + * Return the current contents of the interrupt status register, clearing + * all pending interrupts. + * + * Input Parameters: + * handle The handle that represents the timer state + * + * Returned Value: + * The value of the channel interrupt status register. + * + ****************************************************************************/ + +uint32_t sam_tc_getpending(TC_HANDLE handle) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + DEBUGASSERT(chan); + return sam_chan_getreg(chan, SAM_TC_SR_OFFSET); +} + +/**************************************************************************** + * Name: sam_tc_setregister + * + * Description: + * Set TC_REGA, TC_REGB, or TC_REGC register. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * regid One of {TC_REGA, TC_REGB, or TC_REGC} + * regval Then value to set in the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + + DEBUGASSERT(chan && regid < TC_NREGISTERS); + + tcvdbg("Channel %d: Set register RC%d to %08lx\n", + chan->chan, regid, (unsigned long)regval); + + sam_chan_putreg(chan, g_regoffset[regid], regval); + sam_regdump(chan, "Set register"); +} + +/**************************************************************************** + * Name: sam_tc_getregister + * + * Description: + * Get the current value of the TC_REGA, TC_REGB, or TC_REGC register. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * regid One of {TC_REGA, TC_REGB, or TC_REGC} + * + * Returned Value: + * The value of the specified register. + * + ****************************************************************************/ + +uint32_t sam_tc_getregister(TC_HANDLE handle, int regid) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + DEBUGASSERT(chan); + return sam_chan_getreg(chan, g_regoffset[regid]); +} + +/**************************************************************************** + * Name: sam_tc_getcounter + * + * Description: + * Return the current value of the timer counter register + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * The current value of the timer counter register for this channel. + * + ****************************************************************************/ + +uint32_t sam_tc_getcounter(TC_HANDLE handle) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + DEBUGASSERT(chan); + return sam_chan_getreg(chan, SAM_TC_CV_OFFSET); +} + +/**************************************************************************** + * Name: sam_tc_divfreq + * + * Description: + * Return the divided timer input frequency that is currently driving the + * the timer counter. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * The timer counter frequency. + * + ****************************************************************************/ + +uint32_t sam_tc_divfreq(TC_HANDLE handle) +{ + struct sam_chan_s *chan = (struct sam_chan_s *)handle; + uint32_t regval; + int tcclks; + + DEBUGASSERT(chan); + + /* Get the the TC_CMR register contents for this channel and extract the + * TCCLKS index. + */ + + regval = sam_chan_getreg(chan, SAM_TC_CMR_OFFSET); + tcclks = (regval & TC_CMR_TCCLKS_MASK) >> TC_CMR_TCCLKS_SHIFT; + + /* And use the TCCLKS index to calculate the timer counter frequency */ + + return sam_tc_divfreq_lookup(BOARD_MCK_FREQUENCY, tcclks); +} + +/**************************************************************************** + * Name: sam_tc_divisor + * + * Description: + * Finds the best MCK divisor given the timer frequency and MCK. The + * result is guaranteed to satisfy the following equation: + * + * (Ftcin / (div * 65536)) <= freq <= (Ftcin / dev) + * + * where: + * freq - the desired frequency + * Ftcin - The timer/counter input frequency + * div - With DIV being the highest possible value. + * + * Input Parameters: + * frequency Desired timer frequency. + * div Divisor value. + * tcclks TCCLKS field value for divisor. + * + * Returned Value: + * Zero (OK) if a proper divisor has been found, otherwise a negated errno + * value indicating the nature of the failure. + * + ****************************************************************************/ + +int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) +{ + int ndx = 0; + + tcvdbg("frequency=%d\n", frequency); + + /* Satisfy lower bound. That is, the value of the divider such that: + * + * frequency >= (tc_input_frequency * 65536) / divider. + */ + + while (frequency < (sam_tc_divfreq_lookup(BOARD_MCK_FREQUENCY, ndx) >> 16)) + { + if (++ndx > TC_NDIVOPTIONS) + { + /* If no divisor can be found, return -ERANGE */ + + tcdbg("Lower bound search failed\n"); + return -ERANGE; + } + } + + /* Try to maximize DIV while still satisfying upper bound. That the + * value of the divider such that: + * + * frequency < tc_input_frequency / divider. + */ + + for (; ndx < (TC_NDIVOPTIONS-1); ndx++) + { + if (frequency > sam_tc_divfreq_lookup(BOARD_MCK_FREQUENCY, ndx + 1)) + { + break; + } + } + + /* Return the divider value */ + + if (div) + { + uint32_t value = sam_tc_freqdiv_lookup(BOARD_MCK_FREQUENCY, ndx); + tcvdbg("return div=%lu\n", (unsigned long)value); + *div = value; + } + + /* Return the TCCLKS selection */ + + if (tcclks) + { + tcvdbg("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx)); + *tcclks = TC_CMR_TCCLKS(ndx); + } + + return OK; +} + +#endif /* CONFIG_SAMV7_TC0 || CONFIG_SAMV7_TC1 || CONFIG_SAMV7_TC2 || CONFIG_SAMV7_TC3 */ diff --git a/arch/arm/src/samv7/sam_tc.h b/arch/arm/src/samv7/sam_tc.h new file mode 100644 index 00000000000..421b0835cad --- /dev/null +++ b/arch/arm/src/samv7/sam_tc.h @@ -0,0 +1,366 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_tc.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_TC_H +#define __ARCH_ARM_SRC_SAMV7_SAM_TC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "chip/sam_tc.h" + +#if defined(CONFIG_SAMV7_TC0) || defined(CONFIG_SAMV7_TC1) || \ + defined(CONFIG_SAMV7_TC2) || defined(CONFIG_SAMV7_TC3) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The timer/counter and channel arguments to sam_tc_allocate() */ + +#define TC_CHAN0 0 /* TC0 */ +#define TC_CHAN1 1 +#define TC_CHAN2 2 +#define TC_CHAN3 3 /* TC1 */ +#define TC_CHAN4 4 +#define TC_CHAN5 5 +#define TC_CHAN6 6 /* TC2 */ +#define TC_CHAN7 7 +#define TC_CHAN8 8 + +/* Register identifier used with sam_tc_setregister */ + +#define TC_REGA 0 +#define TC_REGB 1 +#define TC_REGC 2 + +/* Timer debug is enabled if any timer client is enabled */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_ANALOG +# undef CONFIG_SAMV7_TC_REGDEBUG +#endif + +#if !defined(CONFIG_SAMV7_TC_DEBUG) && defined(CONFIG_SAMV7_ADC) && defined(CONFIG_DEBUG_ANALOG) +# define CONFIG_SAMV7_TC_DEBUG 1 +#endif + +/* Timer/counter debug output */ + +#ifdef CONFIG_SAMV7_TC_DEBUG +# define tcdbg dbg +# define tcvdbg vdbg +# define tclldbg lldbg +# define tcllvdbg llvdbg +#else +# define tcdbg(x...) +# define tcvdbg(x...) +# define tclldbg(x...) +# define tcllvdbg(x...) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ +/* An opaque handle used to represent a timer channel */ + +typedef void *TC_HANDLE; + +/* Timer interrupt callback. When a timer interrupt expires, the client will + * receive: + * + * tch - The handle that represents the timer state + * arg - An opaque argument provided when the interrupt was registered + * sr - The value of the timer interrupt status register at the time + * that the interrupt occurred. + */ + +typedef void (*tc_handler_t)(TC_HANDLE tch, void *arg, uint32_t sr); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_tc_allocate + * + * Description: + * Configures a Timer Counter to operate in the given mode. The timer is + * stopped after configuration and must be restarted with sam_tc_start(). + * All the interrupts of the timer are also disabled. + * + * Input Parameters: + * channel TC channel number (see TC_CHANx definitions) + * mode Operating mode (TC_CMR value). + * + * Returned Value: + * On success, a non-NULL handle value is returned. This handle may be + * used with subsequent timer/counter interfaces to manage the timer. A + * NULL handle value is returned on a failure. + * + ****************************************************************************/ + +TC_HANDLE sam_tc_allocate(int channel, int mode); + +/**************************************************************************** + * Name: sam_tc_free + * + * Description: + * Release the handle previously allocated by sam_tc_allocate(). + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sam_tc_free(TC_HANDLE handle); + +/**************************************************************************** + * Name: sam_tc_start + * + * Description: + * Reset and Start the TC Channel. Enables the timer clock and performs a + * software reset to start the counting. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * + ****************************************************************************/ + +void sam_tc_start(TC_HANDLE handle); + +/**************************************************************************** + * Name: sam_tc_stop + * + * Description: + * Stop TC Channel. Disables the timer clock, stopping the counting. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * + ****************************************************************************/ + +void sam_tc_stop(TC_HANDLE handle); + +/**************************************************************************** + * Name: sam_tc_attach/sam_tc_detach + * + * Description: + * Attach or detach an interrupt handler to the timer interrupt. The + * interrupt is detached if the handler argument is NULL. + * + * Input Parameters: + * handle The handle that represents the timer state + * handler The interrupt handler that will be invoked when the interrupt + * condition occurs + * arg An opaque argument that will be provided when the interrupt + * handler callback is executed. Ignored if handler is NULL. + * mask The value of the timer interrupt mask register that defines + * which interrupts should be disabled. Ignored if handler is + * NULL. + * + * Returned Value: + * The address of the previous handler, if any. + * + ****************************************************************************/ + +tc_handler_t sam_tc_attach(TC_HANDLE handle, tc_handler_t handler, + void *arg, uint32_t mask); + +#define sam_tc_detach(h) sam_tc_attach(h, NULL, NULL, 0) + +/**************************************************************************** + * Name: sam_tc_getpending + * + * Description: + * Return the current contents of the interrutp status register, clearing + * all pending interrupts. + * + * Input Parameters: + * handle The handle that represents the timer state + * + * Returned Value: + * The value of the channel interrupt status register. + * + ****************************************************************************/ + +uint32_t sam_tc_getpending(TC_HANDLE handle); + +/**************************************************************************** + * Name: sam_tc_setregister + * + * Description: + * Set TC_REGA, TC_REGB, or TC_REGC register. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * regid One of {TC_REGA, TC_REGB, or TC_REGC} + * regval Then value to set in the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval); + +/**************************************************************************** + * Name: sam_tc_getregister + * + * Description: + * Get the current value of the TC_REGA, TC_REGB, or TC_REGC register. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * regid One of {TC_REGA, TC_REGB, or TC_REGC} + * + * Returned Value: + * The value of the specified register. + * + ****************************************************************************/ + +uint32_t sam_tc_getregister(TC_HANDLE handle, int regid); + +/**************************************************************************** + * Name: sam_tc_getcounter + * + * Description: + * Return the current value of the timer counter register + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * The current value of the timer counter register for this channel. + * + ****************************************************************************/ + +uint32_t sam_tc_getcounter(TC_HANDLE handle); + +/**************************************************************************** + * Name: sam_tc_infreq + * + * Description: + * Return the timer input frequency, that is, the MCK frequency divided + * down so that the timer/counter is driven within its maximum frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * The timer input frequency. + * + ****************************************************************************/ + +uint32_t sam_tc_infreq(void); + +/**************************************************************************** + * Name: sam_tc_divfreq + * + * Description: + * Return the divided timer input frequency that is currently driving the + * the timer counter. + * + * Input Parameters: + * handle Channel handle previously allocated by sam_tc_allocate() + * + * Returned Value: + * The timer counter frequency. + * + ****************************************************************************/ + +uint32_t sam_tc_divfreq(TC_HANDLE handle); + +/**************************************************************************** + * Name: sam_tc_divisor + * + * Description: + * Finds the best MCK divisor given the timer frequency and MCK. The + * result is guaranteed to satisfy the following equation: + * + * (Ftcin / (div * 65536)) <= freq <= (Ftcin / div) + * + * where: + * freq - the desired frequency + * Ftcin - The timer/counter input frequency + * div - With DIV being the highest possible value. + * + * Input Parameters: + * frequency Desired timer frequency. + * div Divisor value. + * tcclks TCCLKS field value for divisor. + * + * Returned Value: + * Zero (OK) if a proper divisor has been found, otherwise a negated errno + * value indicating the nature of the failure. + * + ****************************************************************************/ + +int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_SAMV7_TC0 || CONFIG_SAMV7_TC1 || CONFIG_SAMV7_TC2 || CONFIG_SAMV7_TC3 */ +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_TC_H */